ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 1 -
GENERAL DESCRIPTION
The AK4628 is a sin gle chip COD EC that i nclude s two chann els of ADC and eight c hannels of DAC. T he
ADC outputs 2 4bit data and the DAC accepts up to 24bit i nput da ta. The ADC has the Enhanced D ual Bit
architecture with wide dynamic range. The DAC introduces the newly developed Advanced Multi-Bit
architecture, and achi eves wid er dyna mic ran ge and low er outb and nois e. An au xiliary di gital aud io in put
interface maybe use d instead o f the ADC for passing audio data to the prim ary audio out put port. Control
may be set directly by pins or programmed through a separate serial interface.
The AK4628 has a dynami c range of 102dB for ADC, 106dB for DAC and is well suited for digital surround
for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as
the AK4112B. The AK4628 is available in a small 44pin LQFP packag e whi c h will redu ce system space.
*AC-3 is a trademark of Dolby Labora tories.
FEATURES
2ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 92dB
- Dynamic Range, S/N: 102dB
- Digital HPF for offset cancellation
- I/F format: MSB justified, I2S or TDM
- Overflow flag
8ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM
- Individual channel digital volume with 128 levels and 0.5dB step
- Soft mute
- De-emphasis for 32kH z, 4 4.1kH z and 48kHz
- Zero Detect Function
High Jitter Tolerance
TTL Level Digital I/F
3-wire Serial and I2C Bus µP I/F for mode setting
Master clock: 256fs, 384fs or 512fs for fs=32kHz to 48kHz
128fs, 192fs or 256fs for fs=64kHz to 96kHz
128fs for fs=120kHz to 192kHz
Power Supply: 4.5 to 5.5V
Power Supply for output buffer: 2.7 to 5.5V
Small 44pin LQFP
AK4529 Pin Compatible
High Performance Multi-channel Audio CODEC
AK4628
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 2 -
Block Diagram
Audio
I/F
LPF
LPF DAC DATT
LPF DAC DATT
LPF DAC DATT
LPF DAC DATT
LPF DAC DATT
LOUT1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
DAC DATT
AK4628
ADC HPF
ADC HPF
RIN
LIN
LRCK
BICK
SDOUT1
SDOUT2
SDOUT3
AC3
SDIN
MCKO
LRCK
BICK
XTI
XTO DIR
SDTO
AK4112B
RX4RX3 RX2 RX1
LRCK
BICK
SDTI1
SDTI2
SDTI3
DAUX
SDOS
MCLK
LRCK
BICK
SDOUT
SDIN1
SDIN2
SDIN3
MCLK
SDTO
Format
Converter
SDOUT4
SDTI4
SDIN4
LPF DAC DATT
LPF DAC DATT
LOUT4
ROUT4
Block Diagram (DIR and AC-3 DSP are external parts)
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 3 -
Ordering Guide
AK4628VQ -40 ∼ +85°C 44pin LQFP(0.8mm pitch)
AKD4628 Evaluation Board for AK4628
Pin Layout
S
DOS
TDM0
1
I2C
44
2
S
MUTE 3
B
ICK 4
L
RCK 5
S
DTI1 6
S
DTI2 7
S
DTI3 8
S
DTO 9
D
AUX 10
D
FS0 11
LOOP0/SDA/CDTI
43
DIF1/SCL/CCLK
42
41
40
MCLK
39
DZF1
38
AVSS
37
A
VDD
36
VREFH
35
VCOM
34
SDTI4 12
DZFE 13
TVDD 14
DVDD 15
DVSS 16
17
TST1 18
CAD1 19
CAD0 20
LOUT4 21
ROUT4 22
33
32
31
30
29
28
27
26
25
24
23
DZF2/OVF
RIN
LIN
NC
TST2
ROUT1
LOUT 1
ROUT2
LOUT 2
ROUT3
LOUT 3
AK462 8VQ
Top View
PDN
DIF0/CSN
P/S
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 4 -
Compatibility with AK4529
1. Functions
Functions AK4529 AK4628
DAC Sampling freque ncy Up to 96kHz Up to 192kHz
TDM128 (96kHz) Not available Available
Digital Attenuator 256 levels 128 levels
Soft Mute Soft mute function is independent of
Digital attenuator. Soft mute function is not independent of
Dig i tal attenu ator.
DAC channel power -down Not available Available
2. Pin Configuration
pin# AK4529 AK4628
11 DFS DFS0
18 TST TST1
29 NC TST2
44 TDM TDM0
3. Register
Addr AK4529 AK4628
00H TDM TDM0
00H Not available TDM1
01H DFS DFS0
01H Not available DFS1
01H Not available CKS1, CKS0
09H Not available PD4, PD3, PD2, PD1
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 5 -
PIN/FUNCTION
No. Pin Name I/O Function
1 SDOS I SDTO Source Select Pin (Note 1)
“L”: Internal ADC output, “H”: DAUX input
SDOS pin should be set to “L” when TDM = “1”.
2 I2C I Control Mode Select Pin
“L”: 3-wire Serial, “H”: I2C Bus
3 SMUTE I Soft Mute Pin (Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute rele ases.
4 BICK I Audio Serial Data Clock Pin
5 LRCK I Input Channel Clock Pin
6 SDTI1 I DAC1 Audio Serial Data Input Pin
7 SDTI2 I DAC2 Audio Serial Data Input Pin
8 SDTI3 I DAC3 Audio Serial Data Input Pin
9 SDTO O Audio Serial Data Output Pin
10 DAUX I AUX Audio Serial Data Input Pin
11 DFS0 I Double Speed Sampling M ode Pin (Note 1)
“L”: Normal Speed, “ H”: Double Speed
12 SDTI4 I DAC4 Audio Serial Da ta Input Pin
13 DZFE I Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all eight channels)
14 TVDD - Output Buffer Power Supply Pin, 2.7V∼5.5V
15 DVDD - Digital Power Suppl y Pin, 4.5V ∼5.5V
16 DV SS - Digital Ground Pin, 0V
17 PDN I Power-Down & Reset Pin
When “L” , the AK4628 is powered-dow n and the control registers are reset to default
state. If the state of P/S or CAD1- 0 chan ges, then the AK 4628 must be r eset by PDN .
18 TST1 I Test Pin
This pin should be connected to DVSS.
19 CAD1 I Chip Address 1 P in
20 CAD0 I Chip Address 0 P in
21 LOUT4 O DAC4 Lch Analog Output Pin
22 ROUT4 O DAC4 Rch Analog Output P i n
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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No. Pin Name I/O Function
23 LOUT3 O DAC3 Lch Analog Output Pin
24 ROUT3 O DAC3 Rch Analog Output P i n
25 LOUT2 O DAC2 Lch Analog Output Pin
26 ROUT2 O DAC2 Rch Ana log O ut put P i n
27 LOUT1 O DAC1 Lch Analog Output Pin
28 ROUT1 O DAC1 Rch Ana log O ut put P i n
29 TST2 I Test pin (Internal pull-down pin)
This pin should be left floating or connected to AVSS.
30 NC - No Connect
No internal bondi ng.
31 LIN I Lch Analog Inpu t Pin
32 RIN I Rch Analog Input Pin
DZF2 O Zero Input Detect 2 Pin (Note 2)
When the in put data o f the gro up 1 fol low to tal 8 192 L RCK cycle s with “0” input da ta,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to
“H”. It always is in “L” when P/S is “H”.
33
OVF O Analog Input Overflow Detect Pin (Note 3)
This pin goes to “H” if the an alog input of Lch or Rch overfl ows.
34 VCOM O Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2µF is used to reduce power-supply noise.
35 VREF H I Positive Voltage Reference Input Pin, AVDD
36 AVDD - Analog Power Supply Pin, 4.5V∼5.5V
37 AVSS - Analog Ground Pin, 0V
38 DZF 1 O Zero Input Detect 1 Pin (Note 2)
When the in put data o f the gro up 1 fol low to tal 8 192 L RCK cycle s with “0” input da ta,
this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “0”, this pin goes to
“H”. Output is selected by setting DZFE pin when P/S is “H”.
39 MCLK I Master Clock Input Pin
40 P/S I Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
DIF0 I Audio Data Interface Format 0 Pin in parallel control mode 41 CSN I Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I2C bus control mode
DIF1 I Audio Data Interface Format 1 Pin in parallel control mode 42 SCL/CCLK I Control Data Clock Pin in serial control mode
I2C = “L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus)
LOOP0 I Loopback Mode 0 Pin in paral lel control mode
Enables digital loop-back from AD C to 4 DACs.
43
SDA/CDTI I/O Control Data Input Pin in serial control mode
I2C = “L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus)
44 TDM0 I TDM I/F Format Mode Pin (Note 1)
“L”: Normal mode , “H ”: TDM mode
Notes: 1. SDOS, SMUTE, DFS0, and TDM0 pins are ORed with register data if P/S = “L”.
2. The group 1 and 2 can be selected by DZ FM3-0 bits if P/S = “L” and DZFE = “L”.
3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode.
4. All digital input pins exce p t for pull- dow n shou ld no t be left floatin g.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 7 -
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 5)
Parameter Symbol min max Units
Power Supplies Analog
Digital
Output buffer
|AVSS-DVSS| (Note 6)
AVDD
DVDD
TVDD
∆GND
-0.3
-0.3
-0.3
-
6.0
6.0
6.0
0.3
V
V
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Analog Input Voltage VINA -0.3 AVDD+0.3 V
Digital Input Voltage
(Expect LRCK , BICK pins)
(LRCK, BICK pins)
VIND1
VIND2
-0.3
-0.3
DVDD+0.3
TVDD+0.3
V
V
Ambient Temper ature (pow er applied) Ta -40 85 °C
Storage Temperature Tstg -65 150 °C
Notes: 5. All voltages with respect to ground.
6. AVSS and DVSS must be connected to the same analog gro und plane.
WARNING: Operat ion at or beyond the se limits may result in permane nt dam age to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 5)
Parameter Symbol min typ max Units
Power Supplies
(Note 7) Analog
Digital
Output buffer
AVDD
DVDD
TVDD
4.5
4.5
2.7
5.0
5.0
5.0
5.5
5.5
5.5
V
V
V
Notes: 5. All voltages with respect to ground.
7. The power up sequence between AVDD, DVDD and TVDD is not critical.
Do not turn off only the A K4628 under the co ndition that a surroundi ng device is powered on an d the I2C bus is
in use.
WARNING: AK M assumes no respo nsibility for the usage be yond the conditions in this datasheet.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 8 -
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kH z at fs=96kH z,
20Hz~40kHz at fs=192kHz; unless ot herwise specified)
Parameter min typ max Units
ADC Analo g Input Characteristics
Resolution 24 Bits
S/(N+D) (-0.5dBFS) fs=48kHz
fs=96kHz 84
- 92
86
dB
dB
DR (-60dBFS) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94
88
93
102
96
102
dB
dB
dB
S/N (Note 8) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94
88
93
102
96
102
dB
dB
dB
Interchannel Isola t ion 90 110 dB
DC Accuracy
Interchannel G ain Misma tc h 0.2 0.3 dB
Gain Drift 20 - ppm/°C
Input Voltage AIN=0.62 xVREFH 2.90 3.10 3.30 Vpp
Input Resistance (Note 9) 15 25 kΩ
Power Supply Rejection (Note 10) 50 dB
DAC Analog Output Charac ter ist ics
Resolution 24 Bits
S/(N+D) fs=48kHz
fs=96kHz
fs=192kHz
80
78
-
90
88
88
dB
dB
dB
DR (-60dBFS) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
95
88
94
-
-
106
100
106
100
106
dB
dB
dB
dB
dB
S/N (Note 11) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
95
88
94
-
-
106
100
106
100
106
dB
dB
dB
dB
dB
Interchannel Isola t ion 90 110 dB
DC Accuracy
Interchannel G ain Misma tch 0.2 0.5 dB
Gain Drift 20 -
ppm/°C
Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp
Load Resistance 5
kΩ
Power Supply Rejection (Note 10) 50 dB
Notes: 8. S/N measured by CCIR-A RM is 98dB(@fs=48kHz).
9. Input resistance is 16kΩ typically at fs=96kHz.
10. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage.
11. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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Parameter min typ max Units
Power Supplies
Power Supply Current (AVDD+DVDD+TVDD)
Normal Operation (PDN = “H”)
AVDD fs=48kHz, 96kHz
fs=192kHz
DVDD+TVDD fs=48kHz (Note 12)
fs=96kHz
fs=192kHz
Power-down mode (PDN = “L”) (Note 13)
45
34
18
24
27
80
67
51
27
36
40
200
mA
mA
mA
mA
mA
µA
Notes: 12. TVDD=0.1mA(typ).
13. In the pow er- down mode. All digital i nput pins i nclud ing cloc k pins (M CLK, BICK , LRCK) are held DV SS.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 10 -
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter Symbol min typ max Units
ADC Digital Filter (Decimation LPF):
Passband (Note 14) ±0.1dB
-0.2dB
-3.0dB
PB 0
-
-
20.0
23.0
18.9
-
-
kHz
kHz
kHz
Stopband SB 28 kHz
Passband Ripple PR ±0.04 dB
Stopband Attenuation SA 68 dB
Group Delay (Note 15) GD 16 1/fs
Group Delay Distort ion ∆GD 0 µs
ADC Digital Filter (HPF):
Frequency Response (Note 14) -3dB
-0.1dB FR 1.0
6.5 Hz
Hz
DAC Digital Filter:
Passband (Note 14) -0.1dB
-6.0dB PB 0
-
24.0 21.8
- kHz
kHz
Stopband SB 26.2 kHz
Passband Ripple PR ±0.02 dB
Stopband Attenuation S A 54 d B
Group Delay (Note 15) GD 19.2 1/fs
DAC Digital Filter + Analog Filter:
Frequenc y Response: 0 ∼ 20.0kHz
40.0kHz ( Note 1 6)
80.0kHz ( Note 1 6)
FR
FR
FR
±0.2
±0.3
±1.0
dB
dB
dB
Notes:
14. The passba nd and stopband frequencies scale with fs.
For example, 21.8kHz at –0.1dB is 0.454 x fs.
15. The calcula ting delay time which occurr ed by digital filtering. This time is from setting the input of a nalog signal to
setting the 24bit data of both channels to the output register for ADC.
For DAC, this time is from sett ing the 20/24bit data of both channels on input register to the output of analog
signal.
16. 40.0kHz; fs=96kHz , 80.0kHz; fs=19 2kH z.
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Inp ut Voltage VIH
VIL 2.2
- -
- -
0.8 V
V
High-Level Output Voltage
(SDTO, LRCK, BICK pins: Iout=-100µA)
(DZF1, DZF2/OVF pins: Iout=-100µA)
Low-Level Output Voltage
(SDTO, LRCK, BICK,DZF1, DZF2/OVF pins:
Iout= 100µA)
(SDA pins: Iout= 3mA)
VOH
VOH
VOL
VOL
TVDD-0.5
AVDD-0.5
-
-
-
-
-
-
-
-
0.5
0.4
V
V
V
V
Input Leakage Current (Note 17) Iin - - ±10 µA
Note 17: TST2 pin has an internal pull-dow n device, nominally 100 kohm .
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
256fsn, 128fsd:
Pulse Width Low
Pulse Width High
384fsn, 192fsd:
Pulse Width Low
Pulse Width High
512fsn, 256fsd:
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
8.192
27
27
12.288
20
20
16.384
15
15
12.288
18.432
24.576
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
LRCK Timing
Normal mode (TDM0= “0 ”, TDM1= “0”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
32
64
120
45
48
96
192
55
kHz
kHz
kHz
%
TDM256 mode (TDM0= “1”, TDM1= “0”)
LRCK frequenc y
“H” time
“L” time
fsn
tLRH
tLRL
32
1/256fs
1/256fs
48
kHz
ns
ns
TDM128 mode (TDM0= “1”, TDM1= “1”)
LRCK frequenc y
“H” time
“L” time
fsn
tLRH
tLRL
64
1/128fs
1/128fs
96
kHz
ns
ns
Audio Interface Timing
Normal mode (TDM0= “0”, TDM1= “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK E dge to BICK “↑” (Note 18)
BICK “↑” to LRCK Edge (Note 18)
LRCK to SDTO(MSB)
BICK “↓” to SDTO
SDTI1-4,DA UX H old Time
SDTI1-4,DAUX Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
32
20
20
20
20
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDM256 mode (TDM0= “1”, TDM1= “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK E dge to BICK “↑” (Note 18)
BICK “↑” to LRCK Edge (Note 18)
BICK “↓” to SDTO
SDTI1 Hold Time
SDTI1 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDM128 mode (TDM0= “1”, TDM1= “1”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK E dge to BICK “↑” (Note 18)
BICK “↑” to LRCK Edge (Note 18)
BICK “↓” to SDTO
SDTI1-2 Hold Time
SDTI1-2 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 18. BICK rising edge must not occur at the same time as LRCK edge.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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Parameter Symbol min typ max Units
Control Interface T iming (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing (I2C Bus mode):
SCL Clock F reque nc y
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first cloc k pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Cond ition
SDA Hold Time from SCL Falling (Note 19)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
4.0
0
100
-
-
-
-
-
-
-
1.0
0.3
-
50
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
Power-down & Reset Timing
PDN Pulse Width (Note 20)
PDN “↑” to SDTO valid (Note 21)
tPD
tPDV
150
522
ns
1/fs
Notes: 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
20. The AK4628 can be reset by bringing PDN “L” to “H” upon power-up.
21. These cycles are the number of LRCK r ising from PDN rising.
22. I2C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Micro systems Co., Ltd I2C components conveys a licens e under the Philips
I2C patent to us e the components in the I2C system, provided the system conform to the I2C
specifications defined by Philips.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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Timing Diagram 1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
1/fsn, 1/fsd
LRCK VIH
VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing (TDM= “0”)
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
1/fs
LRCK VIH
VIL
tLRLtLRH
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing (TDM= “1”)
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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tLRB
LRCK
VIH
BICK VIL
tLRS
SDTO 50%TVDD
tBSD
VIH
VIL
tBLR
tSDS
SDTI VIH
VIL
tSDH
Audio Interface Timing (TDM= “0”)
tLRB
LRCK
VIH
BICK VIL
SDTO 50%TVDD
tBSD
VIH
VIL
tBLR
tSDS
SDTI VIH
VIL
tSDH
Audio Interface Timing (TDM= “1”)
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 15 -
tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRITE Command Input Timing (3-wire Serial mode)
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing (3-wire Serial mode)
tHIGH
SCL
SDA VIH
tLOW
tBUF
tHD:STA
tR tF
tHD:DAT tSU:DAT tSU:STA
Stop Start Start Stop
tSU:STO
VIL
VIH
VIL
tSP
I2C Bus mode Timing
tPD
VIL
PDN
tPDV
SDTO 50%TVDD
VIH
Power-down & Reset Timing
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 16 -
OPERATION OVERVIEW
System Clock
The external clock s, which are required to oper ate the AK4628, are MCLK, LRCK and BICK. MCLK shou ld be
synchronized with LRCK but t he phase i s not c ritica l. The re are two m ethods to set M CLK fr equenc y. In Manual S ettin g
Mode (ACKS = “0”: Defau lt), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each
sampling speed is se t automatically. (Table 2, 3, 4). I n Auto Setting Mode (ACKS = “1”), as MCLK fre quency is detected
automaticall y (Table 5), and the internal master cloc k become s the appropriate fre quency (Table 6), it is not necessary to
set DFS.
External clocks (MCLK, BICK) should always be present whenever the AK4628 is in normal operat ion mode (PDN =
“H”). If these clocks are not prov ided, the AK4628 may draw excess current because the device utilizes dynamic
refreshed logic inter na lly. If the external c l ocks are not present, the AK4628 sho u ld be i n the pow er-dow n mode (P DN =
“L”) or in the reset mode (RST N = “0”). After exiting reset at power-up etc ., the AK4628 is in the power-down m ode until
MCLK and LRCK are input.
DFS1 DFS0 Sampling Speed (fs)
0 0 Normal Speed Mode 32kHz~48kHz
0 1 Double Speed Mode 64kHz~96kHz
Default
1 0 Quad Speed Mode 120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK MCLK (MHz) BICK (MHz)
fs 256fs 384fs 512fs 64fs
32.0kHz 8.1920 12.2880 16.3840 2.0480
44.1kHz 11.2896 16.9344 22.5792 2.8224
48.0kHz 12.2880 18.4320 24.5760 3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK MCLK (MHz) BICK (MHz)
fs 128fs 192fs 256fs 64fs
88.2kHz 11.2896 16.9344 22.5792 5.6448
96.0kHz 12.2880 18.4320 24.5760 6.1440
Table 3. System Clock Example (Dou ble S peed Mode @ Ma nua l Sett ing Mode)
(Note: At Double speed mode(DFS1= “0”, DFS0 = “1”), 128fs and 192fs are not available for ADC.)
LRCK MCLK (MHz) BICK (MHz)
fs 128fs 192fs 256fs 64fs
176.4kHz 22.5792 - - 11.2896
192.0kHz 24.5760 - - 12.2880
Table 4. System Clock Example (Quad S pee d Mode @ Manua l S etting M ode)
(Note: At Quad speed mode(DFS1= “1”, DFS0 = “0”) are not available for ADC.)
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 17 -
MCLK Sampling Speed
512fs Normal
256fs Double
128fs Quad
Table 5. Sampling Speed (Auto Se tting Mode)
LRCK MCLK (MHz)
fs 128fs 256fs 512fs
Sampling
Speed
32.0kHz - - 16.3840
44.1kHz - - 22.5792
48.0kHz - - 24.5760
Normal
88.2kHz - 22.5792 -
96.0kHz - 24.5760 - Double
176.4kHz 22.5792 - -
192.0kHz 24.5760 - - Quad
Table 6. Syste m Cloc k Exam ple ( A uto Se tti ng Mode)
De-emphasis Filter
The AK4628 incl udes the digital de-emphasis filter (tc=50/15µs) by IIR filter. De-emphasis filter is not availa ble in
Double Speed Mode and Quad Speed Mode. This filter corresponds to thre e sampling fre quencies (32kHz, 44.1kHz,
48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0 (DAC1: DEMA1-0, D AC2:
DEMB1-0, DAC3: DEMC1-0, DAC4: DEMD 1-0, see “Register Definitions”).
Mode Sampling Speed DEM1 DEM0 DEM
0 Normal Speed 0 0 44.1kHz
1 Normal Speed 0 1 OFF
2 Normal Speed 1 0 48kHz
3 Normal Speed 1 1 32kHz
Default
Table 8. De-emphas is contro l
Digital High Pass Filter
The ADC has a digital high pass filter for DC offse t cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and
scales with sampling rate (fs).
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 18 -
Audio Serial Interface Format
When TDM= “L”, four modes can be selected by the DIF1-0 as shown in Table 8. In all modes the serial data is
MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are
latched on the rising edge of BICK.
Figures 1∼4 shows the timing at SDOS = “L”. In this ca se, the SDTO outputs the ADC output da ta. When SDOS = “H”,
the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2, 3, 6, 7, 10, 11 in SDTI input
formats can be used for 16-20bit data by zeroing the unused LS Bs.
LRCK BICK
Mode TDM 1 TDM0 DIF1 DIF0 SDTO SDTI1-4,
DAUX I/O I/O
0 0 0 0 0
24bit, Left
justified 20bit, Right
justified H/L I ≥ 48fs I
1 0 0 0 1
24bit, Left
justified 24bit, Right
justified H/L I ≥ 48fs I
2 0 0 1 0
24bit, Left
justified 24bit, Left
justified H/L I ≥ 48fs I Default
3 0 0 1 1 24bit, I2S 24bit, I2S L/H I
≥ 48fs I
Table 8. Audi o data forma ts (N ormal mode)
The audio serial interfac e format becomes the TDM mode if TDM0 pin is se t to “H”. In the TDM256 mode, the serial data
of all DAC (eight c hannels) is inp ut to the SD TI1 pin. The input da ta to SD TI2-4 pins a re ignored. BICK shou ld be fi xed
to 256fs. “H” time and “ L” time of LRCK sho uld be 1/256f s at least. Four modes can be selected by the D IF1-0 as shown
in Table 9. In all m odes the se rial data is MS B-fir st, 2’s complime nt format. The S DTO is cloc ked out o n the falling e dge
of BICK and the SDTI1 are latched on the rising edge of BICK. SDOS and LOOP1-0 should be set to “0” at the TDM
mode. TDM128 Mode can be set by TDM1 as show in Table10. In Double Speed Mode, the serial data of DAC (four
channels; L1, R1, L2, R2) is input to the SDTI1 pin. Other four data (L3, R3, L4, R4) are input to the SDTI2. TDM0 pin
and TDM0 register should be set to “H” if TDM256 Mode is selected. TDM0 pin and TDM0 register, TDM1 register
should be set to “H” if Double Speed Mode is selected in T D M128 Mo de.
LRCK BICK
Mode TDM 1 TDM0 DIF1 DIF0 SDTO SDTI1 I/O I/O
4 0 1 0 0
24bit, Left
justified 20bit, Right
justified ↑ I 256fs I
5 0 1 0 1
24bit, Left
justified 24bit, Right
justified ↑ I 256fs I
6 0 1 1 0
24bit, Left
justified 24bit, Left
justified ↑ I 256fs I
7 0 1 1 1 24bit, I2S 24bit, I2S ↓ I 256fs I
Table 9. Audio data formats (T DM25 6 mode )
LRCK BICK
Mode TDM 1 TDM0 DIF1 DIF0 SDTO SDTI1,
SDTI2 I/O I/O
8 1 1 0 0
24bit, Left
justified 20bit, Right
justified ↑ I 128fs I
9 1 1 0 1
24bit, Left
justified 24bit, Right
justified ↑ I 128fs I
10 1 1 1 0
24bit, Left
justified 24bit, Left
justified ↑ I 128fs I
11 1 1 1 1 24bit, I2S 24bit, I2S ↓ I 128fs I
Table 10. Audio data formats (TDM128 m ode)
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 19 -
LRCK
BICK(64fs)
SDTO
o
0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0
23
1
22 023 22 12 11 10 0 23
SDTI(i) 118 019 8 7 118 019 8 7
Lch Data Rch Data
Don’t Care Don’t Care
12 11 10
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Figure 1. Mode 0 Timing
LRCK
BICK(64fs)
SDTO
o
0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0
23
1
22 023 22 16 15 14 0 23
SDTI(i) 122 023 8 7 122 023 8 7
23:MSB, 0:LSB Lch Data Rch Data
Don’t Care Don’t Care
16 15 14
Figure 2. Mode 1 Timing
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 21 22 23 24 31 0 1 2 0
23
1
22 1 23 22 23
SDTI
(
i
)
22 23 0 2223
23:MSB, 0:LSB Lch Dat a Rch Data
Don’t Care
2
2 1
28 29 30
23
0
22 23 24 31
1
0Don’t Care
2
21
28 29 30
0
Figure 3. Mode 2 Timing
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 3 22 23 24 25 0 0 1
SDTI
(
i
)
3129 30
23 22 1
22 23 0
23:MSB, 0:LSB Lch Data Rch Data
Don’t Care
2
2 1
0
2 3 22 23 24 25 0 31 29 30
23 22 1
2223 0 Don’t Care
2
21
0
1
Figure 4. Mode 3 Timing
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 20 -
256 BICK
BICK(256fs)
SDTO(o)
SDTI1(i)
22 0
Lch
32 BICK
18 0
L1
32 BICK
18 0
R1
32 BI CK
18 0
L2
32 BICK
18 0
R2
32 BICK
18 0
L3
32 BI CK
18 0
R3
32 BICK
18 0
L4
32 BI CK
18 0
R4
32 BI CK
22 0
Rch
32 BI CK
22 23
19 19 19 19 19
23
19 19 19
23
19
LRCK
Figure 5. Mode 4 Timing
256 BICK
BICK(256fs)
SDTO(o)
SDTI1(i)
22 0
Lch
32 BICK
22 0
L1
32 BICK
22 0
R1
32 BI CK
22 0
L2
32 BICK
22 0
R2
32 BICK
22 0
L3
32 BI CK
22 0
R3
32 BICK
22 0
L4
32 BI CK
22 0
R4
32 BI CK
22 0
Rch
32 BI CK
22 23
23 23 23 23 23
23
23 23 23
23
23
LRCK
Figure 6. Mode 5 Timing
256 BICK
BICK(256fs)
SDTO(o)
SDTI1(i)
22 0
Lch
32 BICK
22 0
L1
32 BICK
22 0
R1
32 BI CK
22 0
L2
32 BICK
22 0
R2
32 BICK
22 0
L3
32 BI CK
22 0
R3
32 BICK
22 0
L4
32 BI CK
22 0
R4
32 BI CK
22 0
Rch
32 BI CK
22
22
23
23 23 23 23 23
23
23 23 23
23
23
LRCK
Figure 7. Mode 6 Timing
256 BICK
BICK(256fs)
SDTO(o)
SDTI1(i)
23 0
Lch
32 BICK
23 0
L1
32 BICK
23 0
R1
32 BI CK
23 0
L2
32 BICK
23 0
R2
32 BICK
23 0
L3
32 BI CK
23 0
R3
32 BICK
23 0
L4
32 BI CK
23 0
R4
32 BI CK
23 0
Rch
32 BI CK
23
23
LRCK
Figure 8. Mode 7 Timing
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 21 -
128 BICK
BICK(128fs)
SDTO(o) 22 0
Lch
32 BI CK
L1
32 BI CK R1
32 BICK L2
32 BICK R2
32 BI CK
L3
32 BI CK R3
32 BICK L4
32 BICK R4
32 BICK
22 0
Rch
32 BI CK
22 23 23 23
SDTI1(i) 18 018 018 018 0
19 19 19 19 19
LRCK
SDTI2(i) 18 018 018 018 0 19 19 19 19 19
Figure 9. Mode 8 Timing
128 BICK
BICK(128fs)
22 0
Lch
32 BI CK
L1
32 BI CK R1
32 BICK L2
32 BICK R2
32 BI CK
L3
32 BI CK R3
32 BICK L4
32 BICK R4
32 BICK
22 0
Rch
32 BI CK
22
23 23 23
SDTI1(i) 22 022 022 022 0
23 23 23 23 19
LRCK
SDTI2(i) 22 022 022 022 0 23 23 23 23 19
Figure 10. Mo de 9 Timing
128 BICK
BICK(128fs)
SDTO(o) 22 0
Lch
32 BI CK
L1
32 BI CK R1
32 BICK L2
32 BICK R2
32 BI CK
L3
32 BI CK R3
32 BICK L4
32 BICK R4
32 BI CK
22 0
Rc h
32 BI CK
22 23 23 23
LRCK
SDTI1(i) 22 022 022 022 0 23 23 23 23 22 23
SDTI2(i) 22 022 022 022 0 23 23 23 23 22 23
Figure 11. Mode 10 Timing
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 22 -
128 BICK
BICK(128fs)
SDTO(o) 22 0
Lch
32 BI CK
L1
32 BI CK R1
32 BICK L2
32 BICK R2
32 BI CK
L3
32 BI CK R3
32 BICK L4
32 BICK R4
32 BICK
22 0
Rc h
32 BI CK
23 23 23
SDTI1(i) 22 022 022 022 0 23 23 23 23 23
SDTI2(i) 22 022 022 022 0
23 23 23 23 23
LRCK
Figure 12. Mode 11 Timing
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 23 -
Overflow Detection
The AK4628 has overf low detect func tion for analog inpu t. Overflow dete ct function is enable if OVFE bit is set to “1” at
serial control mode. OV F pin goes to “H” if analog inpu t of Lch or Rch overflows (m ore than -0.3dBF S). OVF output for
overflowed analo g inpu t has the same group dela y as ADC (GD = 16/fs = 333µs @fs=4 8kH z). OVF is “L” for 522/fs
(=11.8ms @fs=48kHz) after PDN = “↑”, and then overflo w detection is enabled.
Zero Detection
The AK4628 has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM3-0 bits if P/S = “L”
and DZFE = “L” (Table 11). DZF1 pi n corresponds to the group 1 chann els and DZF2 pin co rresponds to the g roup 2
channels. However DZ F2 pin becomes OV F pin if OVF E bit is set to “1” . Zero detect ion mode is se t to mode 0 if DZFE=
“H” regardless of P/S pin. DZF1 is AND of all eight cha nnels and DZF 2 is disabled (“L” ) at mode 0. Table 12 shows the
relation of P/S, DZFE, OVFE and DZF.
When the inpu t data of all cha nne ls in the group 1(group 2) are continuo us ly ze ros for 81 92 LR CK cyc le s, D ZF 1(DZF 2)
pin goes to “H”. DZF1(DZF2) pin immediately goes to “L” if input data of any channels in the group 1(group 2) is not
zero after going DZF1(DZF 2) “H”.
DZFM AOUT
Mode 3 2 1 0 L1 R1 L2 R2 L3 R3 L4 R4
0 0 0 0 0 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1
1 0 0 0 1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2 DZF2
2 0 0 1 0 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2 DZF2 DZF2
3 0 0 1 1 DZF1 DZF1 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2
4 0 1 0 0 DZF1 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2
5 0 1 0 1 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2
6 0 1 1 0 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2
7 0 1 1 1 disable (DZF1=DZF2 = “L”)
8 1 0 0 0 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2
9 1 0 0 1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
disable (DZF1=DZF2 = “L”)
Default
Table 11. Zero detect control
P/S pin DZFE pin OVFE bit DZF mode DZF1 pin DZF2/OV F pin
“L” disable Mode 7 “L” “L” “H” (parallel mode) “H” disable Mode 0 AND of 6ch “L ”
“0” Selectable Selectable Selectable “L” “1” Selectable Selectable OVF output
“0” Mode 0 AND of 6ch “L”
“L” (serial mod e )
“H” “1” Mode 0 AN D of 6ch OVF output
Table 12. DZF1-2 pins outputs
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 24 -
Digital Attenuator
AK4628 has c hannel-indepe ndent di gital attenua tor (128 leve ls, 0.5dB st ep). Attenuat ion level of eac h channel can be set
by each ATT7-0 bits (Table 13).
ATT7-0 Attenuation Level
00H 0dB
01H -0.5dB
02H -1.0dB
: :
7DH -62.5dB
7EH -63dB
7FH MUTE (-∞)
:
FEH MUTE (-∞)
FFH MUTE (-∞)
Default
Table 13. Attenuation level of digital attenuator
Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 14). Transition between set
values is the soft transition. Therefore, the switc hing no ise does not occ ur in the transi tion.
Mode ATS1 ATS0 ATT speed
0 0 0 1792/fs
1 0 1 896/fs
2 1 0 256/fs
3 1 1 256/fs
Default
Table 14. Transition time betwee n set values of ATT7-0 bits
The transition between set values is soft transition of 1792 levels in mode 0. It takes 1792/fs (37.3ms@fs=48kHz) from
00H(0dB) to 7FH(MUTE) in mode 0. If PDN pin goes to “L”, the ATTs are initialized to 00H. The ATTs are 00H when
RSTN = “0”. When RSTN return to “1”, the ATTs fade to their current value.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 25 -
Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-∞ during ATT_DATA×A TT transition time (Table 14) from the current ATT level. When the SMUTE pin is returned to
“L”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
A
ttenuation
DZF1,2
ATT Level
-∞
A
OU
T
8192/fs
GD GD
(1)
(2)
(3)
(4)
(1)
Notes:
(1) ATT_DATA×ATT transition time ( Table 16). For example, in Norm al Speed Mode, this time is 179 2LRCK cycles
(1792/fs) at ATT_D ATA=00H. ATT transition of the soft-mute is from 00H to 7FH
(2) The analog ou tput corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancel led before attenuating t o -∞ after starting the operatio n, the attenuation is disco ntinued and
returned to ATT level by the same cycle.
(4) When the input da ta at all the chan nels of the group are cont inuously zeros for 819 2 LRCK cycles, DZF pin of each
channel goes to “H”. DZF pin immediately goes to “L” if the input data of e ither channel of t he group are not zero
after going DZ F “H”.
Figure 13. Soft mute and zero detection
System Reset
The AK4628 should be reset once by bringi ng P DN = “L” upon power-up. The AK 4628 is power ed up and the inter na l
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4628 is in the
power-down mode until MCLK and LRCK are input.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 26 -
Power-Down
The ADC and DACs of AK4628 are placed in the power-down mode by bringing PDN “L” and both digital filters are
reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the
analog outpu ts go to VCOM voltage and DZF 1-2 pins go to “L”. This reset should always be done after power-up. In case
of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522 cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after exiting
the power-dow n mode. The analog outp uts are VCOM volta ge during the initializa tion. Figure 14 show s the sequences of
the power-dow n and the power-up.
The ADC and all DACs can be powered-down individually by PWADN and PWDAN bits. And DAC1-4 can be
power-down individually by PD1-4 bits. In this case, the internal register values are not initialized. When PWADN = “0”,
SDTO goes to “ L”. When PWDA N = “0” and P D1-4 = “ 0”, the ana log outpu ts go to VCO M voltage and D ZF1-2 pins go
to “H”. Because some click noise occurs, the analog output should muted externally if the click noise influences system
application.
A
DC Intern a l
State
PDN 522/fs
Normal Operation Power-down Init Cycle Normal Operation
(1)
Don’t care
GD GD
Clock In
MCLK,LRCK,SCLK
A
DC In
(Analog)
“0”data
A
DC Out
(Digital)
Normal Operation Power-down Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD
External
Mute Mute ON
GD
(3)
(3)
(4) (5)
(6) (6)
(9)
516/fs
Init Cycle
(2)
DZF1/DZF2
(7)
(8)
10∼11/fs (10)
Notes:
(1) The analog part of ADC is init ialized after exiting the powe r-down state.
(2) The analog part of DAC is init ialized after exiting the powe r-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the e nd of initialization of t he analog part. Please mute the di gital output externall y if the click
noise influences system application.
(6) Click noise occurs at the fall ing edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the e xternal clocks (MCLK , BICK and LRCK ) are stopped, the AK4628 s hould be in the p ower-down mode.
(8) DZF pins ar e “L” in the power-down mode (PDN = “L”).
(9) Please mute the analog output exter nal ly if the cl ick noi se (6) influenc es system appli c ation.
(10) DZF= “L” for 10∼11/fs after PDN= “↑”.
Figure 14. Power-down/up sequence example
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 27 -
Reset Function
When RSTN = “0”, AD C and DACs are powered-down b ut the inte rnal register are not initialized. The a nalog outputs g o
to VCOM voltage, DZF1-2 pins go to “ H” and SDTO pin go es to “L”. Because some click noise occurs, the analo g output
should muted exter nal ly if the click noi se influe nce s sys tem application. Figur e 15 shows the powe r-up se que nce .
A
D C Intern al
State
RSTN bit
Normal Operation Digital Block Power-down Normal Operation
Don’ t care
GD GD
Clock In
MCLK,LRCK,SCLK
A
D C In
(Analog)
“0”data
A
DC Out
(Digital)
Normal Operation Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD GD
(2)
(2)
(3) (4)
(6) (6)
DZF1/DZF2
(7)
Internal
RSTN bit
Digital Block Power-down
1~2/fs (9)4~5/fs (9)
4∼5/fs (8)
(5)
516/fs
Init Cycle
(1)
Notes:
(1) The analog part of ADC is initialized after exit ing the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application.
(5) The analog outputs go to VCOM voltage.
(6) Cli ck noise occu rs at 4 ∼5/fs after RSTN bit becomes “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) The external cloc ks (MCLK, BICK and LRCK ) can be stopped in the reset mode. When e xiting the reset mode, “1”
should be written to RSTN bit afte r the externa l clocks (M CLK, BICK and LRCK) are fed.
(8) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit become s “ 1”.
(9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 15. Reset sequence example
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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DAC partial Power-Down Function
All DACs of AK4628 can be powered-down individually by PD1-4 bits. The analog part of DAC is in power-down by
PD1-4 bits =”1”, how ever, the digi tal part is not in power-down by it. Even if a ll DACs w ere set in power-down by the
partial power-dow n bits, the digital part continue to funct ion. The analog o utput of the ch anne l whic h is set in
power-dow n by PD 1-4 bits is fixe d to the voltage of V CO M. And thou gh D ZF detecti on is bein g done, the result of DZF
detection stops reflecting to DZF1-2 pins. Because some click noise occurs in both set-up and release of power-down,
either the analog output should be muted externally or PD1-4 bits should be set up when it is in PWDAN bit =”0” or
RSTN bit =”0”, if the click noise infl uences system a pplication. Fig ure 16 shows the seq uence of the power- down and the
power-up by P D1-4 bits.
PD1-4 bit
DZF1/DZF2
8192/fs
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD GD
(1)
(3) (3)
(2)
DAC Digital
Internal State
Normal Operation Normal Operation
DAC Analog
Internal State Power-down
Normal Operation
Clock In
MCLK,LRCK,SCLK
DAC In
(Digital)
DAC Out
(Analog)
Normal Operation Channel
(4)
(5)
GD
8192/fs
GD
Power-down
Normal Operation Normal Operation
(2)
(3) (3)
(4)
Power Dow n C hannel
DZF Detect
Inte rn a l S ta te
DZF Detect
Inte rn a l S ta te
“0”data
(6)
Notes:
(1) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(2) Analog output of the DAC powered down by PD1-4 =”1” is fixe d to the volta ge of VCOM.
(3) Immediately after PD1-4 bits a re changed, some click no ise occurs at the output of the channel change d by the own
PD bits.
(4) Though DZF detection is being done at a certain channel which set up PD1-4 =”1”, the result of DZF detection
stops reflect ing to DZF1-2 pins.
(5) DZF detection of the DAC which is set up by the power-down setting is ignored, and D ZF1-2 pins become ”H”.
(6) When the powe r-dow n fu n ctio n is set up and the channel has input signa l, e ven if the pa rt ial pow er - down function
is set up, DZF1-2 bits do not become ”H”.
Figure 16. DAC partial p owe r-dow n exam ple
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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Serial Control Interface
The AK4628 can c ontrol its functions via register s. Internal registers may be wr itten by 2 types of control m ode. The chip
address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be
initialized. When the state of P/S pin is changed, the AK4628 s hould be reset by PDN pin.
* Writing to control regi ster is invalid w hen PDN = “L”.
* AK4628 does not suppor t the read com m and.
(1) 3-wire Serial Control Mode (I2C = “L”)
Internal register s may be writte n to the 3 wir e µP interface pi ns (CSN, CCLK and CDTI). T he data on this inter face
consists of Chip a ddress (2bits, CA D0/1), Read/ Write (1bit, F ixed to “1”, Write on ly), Regi ster address (MS B first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. F or write operations, da ta is latched after a low -to-high transi tion of CSN. The clock
speed of CCLK is 5MHz(max).
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: Read/Write (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 17. 3-wire S erial Cont rol I/F Tim ing
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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(2) I2C-bus Control Mode (I2C= “H”)
AK4628 suppor ts the standar d- m ode I2C-bus (m ax:1 00kHz ) . Then AK46 28 does n ot suppor t a fast-m ode I2C-bus
system (max:400kHz). The CSN pin should be connected to DVDD at the I2C-bus mode.
Figure 17 show s the data transfer sequence at the I2C-bu s mode. All comm ands are preceded by a S TART condition.
A HIGH to LOW transi tion on the SDA line while SCL is H IGH indicates a START condition (Fig ure 22). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data
direction bit (R/W) (Figure 19). The most significant five bits of the slave address are fixed as “00100”. The next
two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The
hard-wired input pins (CAD 1 pin and CAD0 pin) set them. If the slave addre ss ma tch that of the AK462 8 and R/W
bit is “0”, the AK46 28 generate s the acknowledge an d the write operation is executed. If R/W bit is “1”, the AK4628
generates the not acknowledge since the AK4628 can be only a slave-receiver. The master must generate the
acknowled ge-related clock p ulse and release the SDA line (HI GH) during the ack nowledge clock pulse (Figure 23).
The second byte consists of the address for control registers of the AK4628. The format is MSB first, and those most
significant 3-b its ar e fixed t o zer os (Figur e 20) . Those data after the seco nd by te con tain contr ol data. The form at is
MSB first, 8bits (Figure 21). The AK4628 generates an acknowledge after each byte has been received. A data
transfer is always termina ted by a STOP condition ge nerated by the m aster. A LOW to HIGH transitio n on the SDA
line while SCL is HIGH defi nes a STOP condition (Figure 22).
The AK4628 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4628 ge nerates an acknowledge, and awaits the next da ta again. The master can transmit more than one byte
instead of termina ting the write cycle after the first data byte is transferre d. After the receipt of each data , the internal
5bits address cou nter is incremented by one, and the next data is take n into next address automa tically. If the address
exceed 1FH prior to generati ng the sto p conditi on, the addre ss counter wil l “roll over ” to 00H and t he previo us data
will be overwritten.
The data on the SDA line must be s table dur ing the HIG H period of the clock. The HIGH or LOW state of the data
line can only c hange when the clock signal on the S CL line is LO W (Figure 24) except for the START an d the STOP
condition.
SDA
S
T
A
R
T
A
C
K
A
C
K
SSlave
A
ddress
A
C
K
Sub
A
ddress(n) Data(n) P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W
A
C
K
Figure 18. Data transfer sequence at the I2C-bus m ode
0 0 1 0 0 CAD1 CAD0 R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 19. The first byte
* * * A4 A3 A2 A1 A0
(*: Don’t care)
Figure 20. The second byte
D7 D6 D5 D4 D3 D2 D1 D0
Figure 21. Byte structure after the second byte
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 31 -
SCL
SDA
stop co ndi t ionstart condition
SP
Figure 22. START and STOP condit ions
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
MASTER
DATA
OUTPUT BY
SLAVE(AK4529)
1 98
START
CONDITION
not acknowledge
clock pulse for
acknowledgement
S
2
Figure 23. Acknowledge on the I2C-bus
SCL
SDA
data line
stable;
data valid
change
of data
allowed
Figure 24. Bit transfer on the I2C-bus
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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Mapping of Pr ogra m Reg i st er s
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 0 TDM1 TDM0 DIF1 DIF0 0 SMUTE
01H Control 2 0 DFS1 LOOP1 LOOP0 SDOS DFS0 ACKS 0
02H LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
03H ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H ROUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06H LOUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H ROUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
08H De-emphasis DEMD1 DEMD0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0
09H ATT speed
& Power Down Control 0 PD4 ATS1 ATS0 PD3 PD2 PD1 RSTN
0AH Zero detect OVFE DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN
0BH LOUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
0CH ROUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Note: For addresses from 0DH to 1FH, data is not written.
When PDN goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timi ng is reset and DZF1-2 pins go to “H ”, but registers are not initia lized
to their default values.
SMUTE, DFS0, SDOS and TDM0 are ORed with pins.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 33 -
Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 0 TDM1 TDM0 DIF1 DIF0 0 SMUTE
Default 0 0 0 0 1 0 0 0
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
Register bit of SMUTE is O Red with the SMU TE pin if P/S = “L”.
DIF1-0: Audio Data Interface Modes (see Table 8, 9, 10)
Initial: “10”, mode 2
TDM1-0: TDM Format Select (see Table 8, 9, 10)
Mode TDM1 TDM0 SDTI Sampling Speed
0 0 0 1-4 Normal, Doub le, Four Times Speed
1 0 1 1 Normal Speed
2 1 1 1-2 Normal, Doub le Speed
Register bit of TDM0 is ORed with the TDM0 pin if P/S = “L”.
TDM0 pin shoul d be “L” if the register control is used.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 34 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 0 DFS1 LOOP1 LOOP0 SDOS DFS0 ACKS 0
Default 0 0 0 0 0 0 0 0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting M ode
1: Enable, Auto Setting Mode
Master clock freque ncy is de tecte d aut om aticall y at ACK S bit “1”. In this case, the setting of DF S are
ignored. When this bit is “0”, DFS0, 1 set the sampling speed mode.
DFS1-0: Sampling speed mode (see Table 1.)
Register bit of DFS0 is ORed with DFS0 pin if P/S = “L”.
The setting of DFS is ignor ed at ACKS bit “1”.
SDOS: SDTO source select
0: ADC
1: DAUX
Register bit of SDOS is ORed with SDOS pin if P/S = “L”.
SDOS should be set to “0” at TDM bit “1”.
In the case of PWADN=”0” and PWDAN=”0”, the setting of SDOS becomes invalid. And ADC is selected.
The output of SDTO becomes “L” at PWADN=”0”.
LOOP1-0: Loopback mode en a ble
00: Normal (No loop back)
01: LIN → LOUT1, LOUT2, LOUT3, LOUT4
RIN → ROUT1, ROUT2, ROUT3, ROUT4
The digital ADC output (DAUX input if SDOS = “1”) is connected to the digital DAC input. In this
mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO at loopback mode
becomes mode 2 at mode 0, and mode 3 at mode 1, respe ctively.
10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)
SDTI1(R) → SDTI2(R), SDTI3(R), SDTI4(R)
In this mode the inpu t DAC data to SDTI2-4 is ignored.
11: N/A
LOOP1-0 should be set to “00” at TDM bit “1”.
In the case of PWADN=”0” and PWDAN=”0”, the setting of LOOP1-0 becomes invalid. And ADC is selected.
And it becomes the normal operation (No loop back).
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 35 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
03H ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H ROUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06H LOUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H ROUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
0BH LOUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
0CH ROUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Default 0 0 0 0 0 0 0 0
ATT7-0: Attenuation Level (see Table 13.)
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
08H De-emphasis DEMD1 DEMD0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0
Default 0 1 0 1 0 1 0 1
DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (see Table 7.)
Initial: “01”, OFF
DEMB1-0: De-emphasis resp onse control for DAC2 data on SDTI2 (see Table 7.)
Initial: “01”, OFF
DEMC1-0: De-emphasis resp onse control for DAC3 data on SDTI3 (see Table 7.)
Initial: “01”, OFF
DEMD1-0: De-emphasis response control for DAC4 data on SDTI4 (see Table 7.)
Initial: “01”, OFF
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
09H ATT speed
& Power Down Control 0 PD4
ATS1 ATS0 PD3 PD2 PD1 RSTN
Default 0 0 0 0 0 0 0 1
RSTN: Internal timing reset
0: Reset. DZF1-2 pins go to “H”, but registers are not initialized.
1: Normal operation
ATS1-0: Digital attenuator transit ion time setting (see Table 14.)
Initial: “00”, mode 0
PD1-0: Power-down control (0: Power- up, 1: Power-down)
PD1: Power down control of DAC1
PD2: Power down control of DAC2
PD3: Power down control of DAC3
PD4: Power down control of DAC4
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0AH Zero detect OVFE DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN
Default 0 0 1 1 1 1 1 1
PWDAN: Power-down control of DAC1-4
0: Power-down
1: Normal operation
PWADN: Power-down control of ADC
0: Power-down
1: Normal operation
PWVRN: Power-down c ontrol of refe rence voltage
0: Power-down
1: Normal operation
DZFM3-0: Zero detect mode select (see Table 11.)
Initial: “0111”, disable
OVFE: Overflow detecti on enable
0: Disable, pin#33 becomes DZF2 pin.
1: Enable, pin#33 become s OVF pin.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 37 -
SYSTEM DESIGN
Figure 25 shows the system connection diagram . An evaluation b oard is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Condition: TVDD=5V, 3-wire serial control mode, CAD1-0 = “00”
TDM0 44
43
42
41
40
39
38
37
36
35
34
SDOS
1
2
3
4
5
6
7
8
9
11
10
I2C
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS0
RIN
CDTI
CCL
K
MCL
K
DZF1
AVSS
VREFH
AVDD
VCOM
SDTI4
DZF2 33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
DVDD
DZFE
TVDD
DVSS
TST1
CAD1
CAD0
LOUT4
ROUT4
LIN
NC
TST2
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
AK4628
+
0.1u
0.1u
2.2u
+
5
uP
A
nalog GroundDigital Ground
(DIR)
DSP
A
nalog 5V
+10u
A
udio
(MPEG/
A
C3)
Digital
A
udio
Sourc e
PDN
CSN
P/S
SMUTE
0.1u
10u
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
Power-down
control
MUTE
MUTE
Figure 25. Typical Connection Diagram
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 38 -
Analog Ground Digital Ground
System
Controller
TDM0
SDOS1
2
3
4
5
6
7
8
9
11
10
I2C
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS0
RIN
LOOP0/SDA/CDTI
DIF1/SCL/CCL
K
MCL
K
DZF1
AVSS
VREFH
AVDD
VCOM
SDTI4
DZF2/OVF
12
13
14
15
16
17
18
19
20
21
22
DVDD
DZFE
TVDD
DVSS
TST1
CAD1
CAD0
LOUT4
ROUT4
LIN
NC
TST2
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
AK4628
PDN
DIF0/CSN
P/S
SMUTE
33
32
31
30
29
28
27
26
25
23
24
44
43
42
41
40
39
38
37
36
35
34
Figure 26. Ground Layout
Note: AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK4628 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up
sequence is not critical. AVSS and DV SS of th e AK4628 mu st be connected to analog grou nd plane. System analog
ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoup ling capacitors should be as near to the AK4628 as possible, with the small value ceramic capacitor being
the nearest.
2. Voltage Reference Inputs
The voltage of VREFH sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1µF
ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic
capacitor attached to VCOM pi n eliminates the effects of high frequency noise . No load current may be draw n from
VCOM pin. All signals, espec ial ly clocks, sh ou ld be kept awa y from the VREFH and VCOM pins in order to avoid
unwanted coup lin g into the AK 46 28.
3. Analog Inputs
ADC inputs are single-ended and internally biased to VCO M. The input s ignal range scales with the supply voltage and
nominally 0.62 x VREFH Vpp (typ)@fs=48kHz. The ADC output data format 2’s compliment. The DC offset is removed
by the internal HPF.
The AK4628 s amples the analo g inputs at 64 fs. The digital f ilter rejects n oise above the stop ban d except for multiples o f
64fs. The AK4628 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
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4. Analog Outputs
The analog outpu ts are also sing le- ende d an d centere d aro und the VCO M vol tage. The in pu t signa l range scales with th e
supply voltage and nom inal ly 0.6 x V REFH V pp. The DA C inpu t data for mat is 2’s c ompleme nt. The output vo ltage is a
positive full sc ale for 7FFFFFH (@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000 000H(@24bit). The internal analog filters r emove most of the noise generated by the delta-sigma
modulator of D AC beyon d the audi o pass b a nd.
DC offsets on analog ou tputs are eliminated by AC coupling si nce DAC outp uts have DC offsets of a few mV.
Peripheral I/F Example
The AK4628 can accept the signal of device with a nominal 3.3V supply because of TTL input. The power supply for
output buffer (TVDD) of the AK4628 should be 3.3V when the peripheral devices operate at a nominal 3.3V supply.
Figure 27 shows a n example with the mixed system of 3.3V a nd 5V .
3.3V Analog
5V Anal o g
3.3V Digital
5V Digital
PLL I/F
A
udio signal
DSP
A
K4112B
A
nalog Digital
Control signal
uP &
Others
A
K4628
5V for input
3.3V for output
Figure 27. Power supply connection example
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 40 -
PACKAGE
0.15
0.17
±
0.05
0.37±0.10
10.00
1.70max
111
23
33
44
p
in LQFP
(
Unit: mm
)
10.00
12.80±0.30
34
44
0.80
22
12
12.80±0.30
0∼0.2
0°
∼
10°
0.60
±
0.20
Package & Lea d frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) pl ate
ASAHI KASEI [AK4628]
MS0211-E-02 2004/03
- 41 -
MARKING
A
K4628VQ
XXXXXXX
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: A K4628VQ
4) Asahi Kasei Logo
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or appl icat ion, c onsult t he A sahi K asei M icros yst ems Co., Lt d. (AK M) s ales off ic e or aut horized
distr ibutor concerning their current st atus.
• AKM assumes no liability f or infringement of any patent, intellect ual property, or other right in the
application or use of any inf ormation contained herein.
• Any export of these products, or devices or systems containing them, may require an export lic ense
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither int ended nor authorized for use as critic al components in any safety, life
support, or other hazard relat ed device or syst em, and AKM assumes no responsibility r elating to
any such u se, except with t he express writt en consent of the R epresentati ve Director of AKM. As
used here:
(a) A hazard related device or syst em is o ne designed or intended f or life support or maint enance of
safety or for applications i n medicine, aeros pace, nuclear energy, or other f ields, in which its
failur e to funct ion or perform may reasona bly be expec t ed to resu lt in loss of life or i n signific ant
injury or damage to person or pr operty.
(b) A critic al component is one whose f ailure to func tion or perf orm may reasonably be expected to
result, whether direct ly or indirect ly, in the loss of the safety or effectiveness of the device or
system cont aining it, and which must therefore meet very high st andards of performance and
reliability.
• It is the responsibility of t he buyer or distributor of an AKM product who distributes, disposes of, or
otherwis e places the product with a third par ty to notify that party in adv ance of the above content
and condition s, and the buyer or dist ributor agr ees to assume any and al l responsi bility and liabi lity
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such not ification.