SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
DMulti-Rate Operation From 155 Mbps Up To
2.5 Gbps
DLow Power Consumption
DInput Offset Cancellation
DHigh Input Dynamic Range
DOutput Disable
DOutput Polarity Select
DCML Data Outputs
DReceive Signal Strength Indicator (RSSI)
DLoss Of Signal Detection (LOS)
DSingle 3.3-V Supply
DSurface Mount Small Footprint 3 mm ×
3 mm 16-Pin QFN Package
applications
DSONET/SDH Transmission Systems at OC3,
OC12, OC24, OC48
D1.0625-Gbps and 2.125-Gbps Fibre Channel
Receivers
DGigabit Ethernet Receivers
description
The ONET2501PA is a versatile high-speed limiting amplifier for multiple fiber optic applications with data rates
up to 2.5 Gbps.
This device provides a gain of about 50 dB, which ensures a fully differential output swing for input signals as
low as 3 mVp−p.
The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal
swings as high as 1200 mVp−p.
The ONET2501PA is available in a small footprint 3 mm × 3 mm, 16-pin QFN package. The circuit requires a
single 3.3-V supply.
This power efficient limiting amplifier is characterized for operation from –40°C to 85°C
Copyright 2005, Texas Instruments Incorporated
! "#$! #%"! &!$
&#"! " ! $""! $ !'$ !$ $( !#$!
!&& )!* &#"! "$+ &$ ! $"$%* "%#&$
!$!+ %% $!$
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
block diagram
A simplified block diagram of the ONET2501PA is shown in Figure 1.
This compact, low power 2.5-Gbps limiting amplifier consists of a high-speed data path with of fset cancellation
block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.
The limiting amplifier requires a single 3.3-V supply voltage. All circuit parts are described in detail below.
Input Buffer
DOUT+
DOUT−
DIN+
DIN−
+
Gain Stage
++ +
COC2 COC1
DISABLE
LOS
TH
VCC
GND
OUTPOL
Bandgap Voltage
Reference and
Bias Current
Generation
Gain Stage Gain Stage
Loss of Signal
and
RSSI Detection
Offset
Cancellation
−
VCCO
RSSI
CML
Output
Buffer
+
−−−−
Figure 1. Block Diagram
high-speed data path
The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2 × 50-Ω on-chip line termination to VCC, three gain stages, which provide
the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available
at the output pins DOUT+/DOUT–, which provide 2 × 50-Ω back-termination to VCCO. The output stage also
includes a data polarity switching function, which is controlled by the OUTPOL input, and a disable function,
controlled by the signal applied to the DISABLE input pin.
An offset cancellation compensates inevitable internal of fset voltages and thus ensures proper operation even
for small input data signals.
The low frequency cutoff is as low as 45 kHz with the built-in filter capacitor.
For applications, which require even lower cutoff frequencies, an additional external filter capacitor may be
connected to the COC1/COC2 pins.
los of signal and RSSI detection
The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block
a signal is generated, which is linearly proportional to the input amplitude over a wide input voltage range. This
signal is available at the RSSI output pin.
Furthermore, this circuit block compares the input signal to a threshold, which can be programmed by means
of an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of
signal is indicated at the LOS pin.
SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
The relationship between the LOS assert voltage VAST (in mVP-P) and the external resistor RTH (in kΩ)
connected to the TH pin can be approximated as given below:
RTH +43 kW
VASTńmVp*p*600 W
VAST +43 mVp*p
RTHńkW)0.6
bandgap voltage and bias generation
The ONET2501PA limiting amplifier is supplied by a single 3.3-V ±10% supply voltage connected to the VCC
and VCCO pins. This voltage is referred to ground (GND).
An on-chip bandgap voltage circuitry generates a supply voltage independent reference from which all other
internally required voltages and bias currents are derived.
package
For the ONET2501PA a small footprint 3 mm × 3 mm 16-pin QFN package is used, with a lead pitch of 0,5 mm .
The pin out is shown in Figure 2.
GND
COC2
COC1
RSSI
1
2
3
4
VCC
DIN+
DIN−
VCC
RGT PACKAGE
(TOP VIEW)
12
11
10
9
16
VCCO
DOUT+
DOUT−
OUTPOL
15 14 13
5678
TH
DISABLE
LOS
GND
EP
Figure 2. Pin Out of ONET2501PA in a 3 mm y 3 mm 16-Pin QFN Package, Top View
SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
terminal functions
The following table shows a pin description for the ONET2501PA in a 3 mm x 3 mm 16-pin QFN package.
TERMINAL
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
VCC 1, 4 Supply 3.3-V ±10% supply voltage
DIN+2Analog in Noninverted data input. On-chip 50-Ω terminated to VCC.
DIN– 3 Analog in Inverted data input. On-chip 50-Ω terminated to VCC.
TH 5 Analog in LOS threshold adjustment with resistor to GND.
DISABLE 6 CMOS in Disables CML output stage when set to high level.
LOS 7 CMOS out High level indicates that the input signal amplitude is below the programmed threshold level.
GND 8, 16, EP Supply Circuit ground. Exposed die pad (EP) must be grounded.
OUTPOL 9 CMOS in Output data signal polarity select (internally pulled up): Setting to high level or leaving pin open selects
normal polarity. Low level selects inverted polarity.
DOUT– 10 CML out Inverted data output. On-chip 50-Ω back-terminated to VCCO
DOUT+ 11 CML out Noninverted data output. On-chip 50-Ω back-terminated to VCCO
VCCO 12 Supply 3.3-V ±10% supply voltage for output stage
RSSI 13 Analog out Analog output voltage proportional to the input data amplitude. Indicates the strength of the received
signal (RSSI).
COC1 14 Analog Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin
and COC2 (pin 15). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
COC2 15 Analog Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin
and COC1 (pin 14). To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
absolute maximum ratings
over operating free-air temperature range unless otherwise noted†
VALUE UNIT
VCC, VCCO Supply voltage, See Note 1 –0.3 to 4 V
VDIN+, VDIN− Voltage at DIN+, DIN–, See Note 1 0.5 to 4 V
VTH, V
DISABLE, VLOS, V
OUTPOL, V
DOUT+,
VDOUT−, VRSSI, VCOC1, VCOC2 Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT–, RSSI,
COC1, and COC2, See Note 1 –0.3 to 4 V
VCOC,DIFF Differential voltage between COC1 and COC2 ±1 V
VDIN,DIFF Differential voltage between DIN+ and DIN– ±2.5 V
ILOS Current into LOS –1 to 9 mA
IDIN+, IDIN−, IDOUT+, IDOUT– Continuous current at inputs and outputs –25 to 25 mA
ESD ESD rating at all pins 3kV (HBM)
TJ(max) Maximum junction temperature 125 °C
Tstg Storage temperature range −65 to 85 °C
TACharacterized free-air operating temperature range −40 to 85 °C
TLLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN TYP MAX UNIT
Supply voltage, VCC, VCCO 3 3.3 3.6 V
Operating free-air temperature, TA−40 85 °C
dc electrical characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC, V
CCO Supply voltage 3 3.3 3.6 V
ICC Supply current DISABLE = low (excludes CML output current) 32 40 mA
VOD
Differential data output voltage swing
DISABLE = high 0.25 10 mVp−p
VOD Differential data output voltage swing DISABLE = low 600 780 1200 mVp−p
rIN, rOUT Data input/output resistance Single ended 50 Ω
RSSI output voltage
Input = 2 mVp−p, RRSSI ≥ 10 kΩ100
mV
RSSI output voltage Input = 80 mVp−p, RRSSI ≥ 10 kΩ2800 mV
RSSI linearity 20-dB input signal, VIN ≤ 80 mVpp ±3% ±8%
V(IN_MIN) Data input sensitivity BER < 10–10 3 5 mVp−p
V(IN_MAX) Data input overload 1200 mVp−p
CMOS input high voltage 2.1 V
CMOS input low voltage 0.6 V
LOS high voltage ISINK = –30 µA 2.4 V
LOS low voltage ISOURCE = 1 mA 0.8 V
LOS hysteresis 223−1 PRBS (at 2.5 Gbps and 155 Mbps) 2.5 4.5 dB
VAST LOS assert threshold range 223−1 PRBS (at 2.5 Gbps and 155 Mbps) 5−40 mVp−p
PSNR Power supply noise rejection f < 2 MHz 26 dB
ac electrical characteristics
over recommended operating conditions (unless otherwise noted) typical operating condition is at VCC = 3.3 V and
TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low frequency −3-dB bandwidth
COC = open 45 70
kHz
Low frequency −3-dB bandwidth COC = 100 nF 0.8 kHz
Data rate 2.5 Gb/s
vNI Input referred noise 300 µVRMS
K28.5 pattern at 2.5 Gbps 8.5 25
DJ Deterministic jitter, See Note 2 223−1 PRBS equivalent pattern at 2.5 Gbps 9.3 30 ps
p−p
DJ
Deterministic jitter, See Note 2
223−1 PRBS equivalent pattern at 155 Mbps 25 50
psp−p
RJ
Random jitter
Input = 5 mVpp 6.5
psRMS
RJ Random jitter Input = 10 mVpp 3psRMS
trOutput rise time 20% to 80% 60 85 ps
tfOutput fall time 20% to 80% 60 85 ps
tDIS Disable response time 20 ns
tLOS LOS assert/deassert time 2 100 µs
NOTE 2: Deterministic jitter does not include pulse-width distortion due to residual small output offset voltage.
SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 3 shows the ONET2501PA connected with an ac-coupled interface to the data signal source as well as
to the output load.
Besides the ac-coupling capacitors C1 through C4 in the input and output data signal lines, the only required
external component is the LOS threshold setting resistor RTH. In addition, an optional external filter capacitor
(COC) may be used if a lower cutoff frequency is desired.
VCC
DIN+
DIN−
DISABLE LOS
DOUT−
DOUT+
GND
DIN+
DIN− DOUT−
DOUT+
GND
VCCO
OUTPOL
VCC
VCC
RSSI
LOS
DISABLE
ONET2501PA
16-Pin QFN
COC2
COC1
OUTPOL
TH
RSSI
COC
Optional
C1
C2
C3
C4
RTH
Figure 3. Basic Application Circuit With AC-Coupled I/Os
SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = VCCO = 3.3 V and TA = 25°C, unless otherwise noted
Figure 4
VID − Differential Input Voltage − mVP-P
0
100
200
300
400
500
600
700
800
900
123456
V
OD
− Differential Output Voltage − mV
P-P
DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35 40
Figure 5
VID − Differential Input Voltage − mVP-P
Random Jitter − psRMS
RANDOM JITTER
vs
DIFFERENTIAL INPUT VOLTAGE
Figure 6
VID − Differential Input Voltage − mVP-P
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Bit Error Ratio
10-18
100
10-2
10-4
10-6
10-8
10-10
10-12
10-14
10-16
BIT ERROR RATIO
vs
DIFFERENTIAL INPUT VOLTAGE
0
5
10
15
20
25
30
35
40
45
50
55
60
f − Frequency − MHz
Small Signal Gain − dB
SMALL SIGNAL GAIN
vs
FREQUENCY
0.01 0.1 10k1 10 100 1k
Figure 7
SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = VCCO = 3.3 V and TA = 25°C, unless otherwise noted
Figure 8
t − Time − 100 ps/Div
V
OD
− Differential Output Voltage − 100 mV/Div
OUTPUT EYE-DIAGRAM at 2.5 GBPS
and MINIMUM INPUT VOLTAGE (5 mVPP)
t − Time − 100 ps/Div
VOD − Differential Output Voltage − 100 mV/Div
OUTPUT EYE-DIAGRAM at 2.5 GBPS
and MAXIMUM INPUT VOLTAGE (1200 mVPP)
Figure 9
Figure 10
Rth − Threshold Voltage Setting Resistance − kΩ
0
10
20
30
40
50
60
70
012345678910
LOS Assert/Deassert Voltage − mV
P-P
LOS ASSERT/DEASSERT VOLTAGE
vs
THRESHOLD VOLTAGE SETTING RESISTANCE
LOS Deassert Voltage
LOS Assert Voltage
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
SDD11 − Differential Input Return Gain − dB
DIFFERENTIAL INPUT RETURN GAIN
vs
FREQUENCY
0.1 1 5
f − Frequency − GHz
Figure 11
SLLS602B − MARCH 2004 − REVISED OCTOBER 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = VCCO = 3.3 V and TA = 25°C, unless otherwise noted
Figure 12
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
SDD22 − Differential Output Return Gain − dB
DIFFERENTIAL OUTPUT RETURN GAIN
vs
FREQUENCY
0.1 1 5
f − Frequency − GHz VID − Differential Input Voltage − mVP-P
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
2600
2800
0 102030405060708090
RSSI − Receive Signal Strength Indicator Voltage − mV
RECEIVE SIGNAL STRENGTH INDICATOR VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
Figure 13
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ONET2501PARGTT NRND QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ONET2501PARGTTG4 NRND QFN RGT 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ONET2501PARGTT QFN RGT 16 250 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ONET2501PARGTT QFN RGT 16 250 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP®Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright ©2012, Texas Instruments Incorporated
