ASIC/FPGA
ASIC/FPGA 1
CARD A CARD C
BACKPLANE
DS10BR254
1:4 LVDS
Repeater
Discrete
Serializer
ASIC/FPGA 2
Discrete
Deserializer 1
Discrete
Deserializer 2
CARD B
DS10BR254
www.ti.com
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
DS10BR254 1.5 Gbps 1:4 LVDS Repeater
Check for Samples: DS10BR254
1FEATURES DESCRIPTION
The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater
2• DC - 1.5 Gbps Low Jitter, Low Skew, Low optimized for high-speed signal routing and
Power Operation distribution over FR-4 printed circuit board
• Wide Input Common Mode Voltage Range backplanes and balanced cables. Fully differential
Allows for DC-Coupled Interface to LVDS, CML signal paths ensure exceptional signal integrity and
and LVPECL Drivers noise immunity.
• Redundant Inputs The device has two different LVDS input channels
• LOS Circuitry Detects Open Inputs Fault and a select pin determines which input is active. A
Condition loss-of-signal (LOS) circuit monitors both input
channels and a unique LOS pin is asserted when no
• Integrated 100ΩInput and Output signal is detected at that input.
Terminations Wide input common mode range allows the switch to
• 8 kV ESD on LVDS I/O Pins Protects Adjoining accept signals with LVDS, CML and LVPECL levels;
Components the output levels are LVDS. A very small package
• Small 6 mm x 6 mm WQFN-40 Space Saving footprint requires a minimal space on the board while
Package the flow-through pinout allows easy board layout.
Each differential input and output is internally
APPLICATIONS terminated with a 100Ωresistor to lower device return
losses, reduce component count and further minimize
• Clock Distribution board space.
• Clock and Data Buffering and Muxing
• OC-12 / STM-4
• SD/HD SDI Routers
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
NC
NC
VDD
IN1+
VDD
OUT0+
OUT0-
OUT1+
1
2
3
4
30
28
27
29
(GND)
DAP
IN1-
IN2+
IN2-
VDD
OUT1-
VDD
OUT2+
OUT2-
5
6
7
8
26
24
23
25
NC
NC
OUT3+
OUT3-
9
10
22
21
NC
NC
NC
SEL_in
11
12
13
14
VDD
GND
NC
NC
15
16
17
18
NC
NC
19
20
NC
NC
PWDN
LOS1
40
38
37
39
LOS2
PWDN0
PWDN1
PWDN2
36
34
33
35
PWDN3
NC
32
31
IN1+
IN1-
IN2+
IN2-
PWDNn
4
OUT0+
OUT0-
OUT1+
OUT1-
OUT2+
OUT2-
OUT3+
OUT3-
LOSn
PWDN
Control and LOS
Circuitry 2
SEL_in
DS10BR254
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
www.ti.com
Block Diagram
Connection Diagram
Figure 1. DS10BR254 Pin Diagram
See Package Number RTA0040A
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DS10BR254
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin
Pin Name I/O, Type Pin Description
Number
IN1+, IN1-, 4, 5, I, LVDS Inverting and non-inverting high speed LVDS input pins.
IN2+, IN2-, 6, 7,
OUT0+, OUT0-, 29, 28, O, LVDS Inverting and non-inverting high speed LVDS output pins.
OUT1+, OUT1-, 27, 26,
OUT2+, OUT2-, 24, 23,
OUT3+, OUT3- 22, 21
SEL_in 14 I, LVCMOS This pin selects which LVDS input is active.
LOS1, 37, O, LVCMOS Loss Of Signal output pins, LOSn report when an open input fault condition is
LOS2 36 detected at the input, INn. These are open drain outputs. External pull up
resistors are required.
PWDN0, 35, I, LVCMOS Channel output power down pin. When the PWDNn is set to L, the channel
PWDN1, 34 output OUTn is in the power down mode.
PWDN2, 33,
PWDN3 32
PWDN 38 I, LVCMOS Device power down pin. When the PWDN is set to L, the device is in the
power down mode.
VDD 3, 8, Power Power supply pins.
15,25, 30
GND 16, DAP Power Ground pin and a pad (DAP - die attach pad).
NC 1, 2 NC NO CONNECT pins. May be left floating.
9, 10,
11, 12,
13, 17,
18, 19,
20, 31,
39, 40
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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DS10BR254
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
www.ti.com
Absolute Maximum Ratings(1)(2)
Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VCC + 0.3V)
LVCMOS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Input Voltage −0.3V to +4V
Differential Input Voltage |VID| 1V
LVDS Output Voltage −0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage 0.0V to +1V
LVDS Output Short Circuit Current Duration 5 ms
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range Soldering (4 sec.) +260°C
Maximum Package Power SQA Package 4.65W
Dissipation at 25°C Derate SQA Package 37.2 mW/°C above +25°C
Package Thermal θJA +26.9°C/W
Resistance θJC +3.8°C/W
ESD Susceptibility HBM(3) ≥8 kV
MM(4) ≥250V
CDM(5) ≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Differential Input Voltage (VID) 0 1 V
Operating Free Air Temperature (TA)−40 +25 +85 °C
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Product Folder Links: DS10BR254
DS10BR254
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 2.0 VDD V
VIL Low Level Input Voltage GND 0.8 V
IIH High Level Input Current VIN = 3.6V 0 ±10 μA
VCC = 3.6V
IIL Low Level Input Current VIN = GND 0 ±10 μA
VCC = 3.6V
VCL Input Clamp Voltage ICL =−18 mA, VCC = 0V −0.9 −1.5 V
VOL Low Level Output Voltage IOL= 4 mA 0.26 0.4 V
LVDS INPUT DC SPECIFICATIONS
VID Input Differential Voltage 0 1 V
VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV
VTL Differential Input Low Threshold −100 0 mV
VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC - V
0.05
VIN = +3.6V or 0V ±1 ±10 μA
IIN Input Current VCC = 3.6V or 0V
CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF
RIN Input Termination Resistor Between IN+ and IN- 100 Ω
LVDS OUTPUT DC SPECIFICATIONS
VOD Differential Output Voltage 250 350 450 mV
RL= 100Ω
ΔVOD Change in Magnitude of VOD for Complimentary -35 35 mV
Output States
VOS Offset Voltage 1.05 1.2 1.375 V
RL= 100Ω
ΔVOS Change in Magnitude of VOS for Complimentary -35 35 mV
Output States
IOS Output Short Circuit Current(4) OUT to GND -35 -55 mA
OUT to VCC 7 55 mA
COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF
ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω
SUPPLY CURRENT
ICC Supply Current PWDN = H 113 135 mA
ICCZ Power Down Supply Current PWDN = L 50 60 mA
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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DS10BR254
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
www.ti.com
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS
tPLHD Differential Propagation Delay Low to 440 650 ps
High(1) RL= 100Ω
tPHLD Differential Propagation Delay High to 400 650 ps
Low(1)
tSKD1 Pulse Skew |tPLHD −tPHLD|(1)(2) 40 100 ps
tSKD2 Channel to Channel Skew(1)(3) 40 125 ps
tSKD3 Part to Part Skew(1)(4) 50 200 ps
tLHT Rise Time(1) 150 300 ps
RL= 100Ω
tHLT Fall Time(1) 150 300 ps
tON Any PWDN to Output Active Time 8 20 μs
tOFF Any PWDN to Output Inactive Time 5 12 ns
tSEL Select Time 5 12 ns
JITTER PERFORMANCE(1)
tRJ1 VID = 350 mV 135 MHz 0.5 1 ps
VCM = 1.2V
tRJ2 311 MHz 0.5 1 ps
Random Jitter Clock (RZ)
(RMS Value)(5)
tRJ3 503 MHz 0.5 1 ps
tRJ4 750 MHz 0.5 1 ps
tDJ1 VID = 350 mV 270 Mbps 6 22 ps
VCM = 1.2V
tDJ2 622 Mbps 6 21 ps
Deterministic Jitter K28.5 (NRZ)
(Peak to Peak Value)(6)
tDJ3 1.0625 Gbps 9 18 ps
tDJ4 1.5 Gbps 9 17 ps
tTJ1 VID = 350 mV 270 Mbps 0.01 0.03 UIP-P
VCM = 1.2V
tTJ2 622 Mbps 0.01 0.03 UIP-P
PRBS-23 (NRZ)
Total Jitter(7)
tTJ3 1.0625 Gbps 0.01 0.04 UIP-P
tTJ4 1.5 Gbps 0.01 0.06 UIP-P
(1) Specification is specified by characterization and is not tested in production.
(2) tSKD1, |tPLHD −tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
(3) tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode
(any one input to all outputs).
(4) tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(5) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(6) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(7) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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Product Folder Links: DS10BR254
RL
OUT+
OUT-
IN+
IN-
Signal Generator
¼ DS10BR254
R D
R D RL
VOL
OUT+
OUT-
IN+
IN-
Power Supply
Power Supply
¼ DS10BR254 VOH
DS10BR254
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
APPLICATION INFORMATION
DC TEST CIRCUITS
AC TEST CIRCUITS AND TIMING DIAGRAMS
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
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OUT+
OUT-
50:50:
VCC
CML3.3V or CML2.5V
Driver
100: Differential T-Line
DS10BR254
Receiver
IN+
IN-
100:
OUT+
OUT-
DS10BR254
Receiver
IN+
IN-
100: Differential T-Line
100:
LVDS
Driver
DS10BR254
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
www.ti.com
FUNCTIONAL DESCRIPTION
The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and distribution over
lossy FR-4 printed circuit board backplanes and balanced cables.
Table 1. Input Select Truth Table
CONTROL Pin (SEL_in) State Input Selected
0 IN1
1 IN2
Input Interfacing
The DS10BR254 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS10BR254 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS10BR254 inputs are internally terminated with a 100Ωresistor.
Figure 2. Typical LVDS Driver DC-Coupled Interface to an DS10BR254 Input
Figure 3. Typical CML Driver DC-Coupled Interface to an DS10BR254 Input
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Product Folder Links: DS10BR254
OUT+
OUT-
CML or
LVPECL or
LVDS
IN+
IN-
100:
100: Differential T-Line Differential
Receiver
DS10BR254
Driver
100:
OUT+
OUT-
150-250:
100: Differential T-Line LVDS
Receiver
IN+
IN-
100:
LVPECL
Driver
150-250:
DS10BR254
www.ti.com
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
Figure 4. Typical LVPECL Driver DC-Coupled Interface to an DS10BR254 Input
Output Interfacing
The DS10BR254 outputs signals compliant to the LVDS standard. Its outputs can be DC-coupled to most
common differential receivers. The following figure illustrates typical DC-coupled interface to common differential
receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a
common mode input range that can accomodate LVDS compliant signals, it is recommended to check respective
receiver's data sheet prior to implementing the suggested interface implementation.
Figure 5. Typical DS10BR254 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
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120
110
100
90
80
70
600 0.8 1.6 2.4 3.2 4.0
SUPPLY CURRENT (mA)
DATA RATE (Gbps)
1 Output ON
2 Outputs ON
3 Outputs ON
All Outputs ON
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
DS10BR254
SNLS260D –DECEMBER 2007–REVISED APRIL 2013
www.ti.com
Typical Performance
Figure 6. A 1.5 Gbps NRZ PRBS-7 After 2" Figure 7. A 1.06 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline Differential FR-4 Stripline
V:100 mV / DIV, H:100 ps / DIV V:100 mV / DIV, H:200 ps / DIV
Figure 8. A 622 Mbps NRZ PRBS-7 After 2" Figure 9. A 270 Mbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline Differential FR-4 Stripline
V:100 mV / DIV, H:200 ps / DIV V:100 mV / DIV, H:500 ps / DIV
Figure 10. Supply Current as a Function of a Number of Outputs Used
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DS10BR254
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SNLS260D –DECEMBER 2007–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com 12-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS10BR254TSQ/NOPB ACTIVE WQFN RTA 40 250 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 1BR254SQ
DS10BR254TSQX/NOPB ACTIVE WQFN RTA 40 2500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 1BR254SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Jun-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS10BR254TSQ/NOPB WQFN RTA 40 250 178.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1
DS10BR254TSQX/NOPB WQFN RTA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS10BR254TSQ/NOPB WQFN RTA 40 250 210.0 185.0 35.0
DS10BR254TSQX/NOPB WQFN RTA 40 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 2
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TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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