[AK4128A] AK4128A 8ch 216kHz / 24-Bit Asynchronous SRC GENERAL DESCRIPTION The AK4128A is an 8ch digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. The AK4128A has an internal Oscillator and does not need any external master clocks. It contributes simplifying a system configuration. The AK4128A supports master mode and TDM data interface, enabling simultaneous input of asynchronous stereo data. The AK4128A is suitable for the application interfacing to different sample rates such as multi-channel high-end Car Audio Systems and DVD recorders. FEATURES 8 channels input/output Asynchronous Sample Rate Converter Input Sample Rate Range (FSI): 8kHz 216kHz Output Sample Rate Range (FSO): 8kHz 216kHz Input to Output Sample Rate Ratio: 1/6 to 6 THD+N: 130dB Dynamic Range: 140dB (A-weighted) I/F format: MSB justified, LSB justified and I2S compatible and TDM Oscillator for Internal Operation Clock Clock for Master mode: 128/256/384/512/768fso On-chip X'tal oscillator Digital De-emphasis Filter (32kHz, 44.1kHz and 48kHz) Soft Mute Function SRC Bypass mode (Master/Slave) P Interface: IC bus Power Supply: AVDD, DVDD1-4: 3.0 3.6V (typ. 3.3V) Ta = 20 85C (AK4128AEQ), 40 85C (AK4128AVQ) Package: 64LQFP MS1242-E-02 2014/03 -1- DITHER SMT1 SMT0 SMSEMI SMUTE VSS2-5 DVDD1-4 INAS DEM1 DEM0 IDIF2 IDIF1 IDIF0 [AK4128A] OLRCK OBICK SRC1 Bypass Input Serial Audio I/F IBICK1 ILRCK1 SDTI1 DEM FIR SRC SMUTE + Dither 0.5 LSB SRC DEM FIR + SMUTE SRC SRC Dither DEM FIR + SRC Dither DEM FIR SRC4 + SMUTE SRC SRC Dither IMCLK PDN PM1 PM2 Internal OSC uP I/F CAD0 SDTO3 0.5 LSB Bypass Input Serial Audio I/F IBICK4 ILRCK4 SDTI4 SDTO4 0.5 LSB UNLOCK Bypass X'tal Osc MCKO Clock Div SDA SCL XTO OMCLK/XTI SPB SDTO2 SRC3 SMUTE SRC ODIF1 ODIF0 Output Serial Audio I/F 0.5 LSB Bypass Input Serial Audio I/F IBICK3 ILRCK3 SDTI3 OBIT1 OBIT2 SRC2 Bypass Input Serial Audio I/F IBICK2 ILRCK2 SDTI2 SDTO1 Internal Regulator SRC CM2 CM1 CM0 REF AVDD VSS1 VD18 DITHER SMT1 SMT0 SMSEMI SMUTE VSS2-5 DVDD1-4 INAS DEM1 DEM0 IDIF2 IDIF1 IDIF0 Figure 1. AK4128A Block Diagram (Synchronous mode INAS pin = "L") OLRCK OBICK SRC1 Bypass Input Serial Audio I/F IBICK1 ILRCK1 SDTI1 DEM FIR SRC SMUTE SRC Dither + IBICK2 ILRCK2 SDTI2 DEM FIR SRC SMUTE SRC DEM FIR SRC 0.5LSB SRC + DEM FIR SRC SRC4 SMUTE SRC Dither IMCLK PDN PM1 PM2 Internal OSC uP I/F CAD0 X'tal Osc SDA SCL XTO OMCLK/XTI SPB SDTO3 0.5LSB Bypass Input Serial Audio I/F + SDTO4 0.5LSB UNLOCK Bypass Clock Div CM2 CM1 CM0 SDTO2 SRC3 SMUTE Dither IBICK4 ILRCK4 SDTI4 Output Serial Audio I/F + Bypass Input Serial Audio I/F ODIF1 ODIF0 SRC2 Dither IBICK3 ILRCK3 SDTI3 OBIT1 OBIT0 0.5LSB Bypass Input Serial Audio I/F SDTO1 MCKO SRC Internal Regulator REF AVDD VSS1 VD18 Figure 2. AK4128A Block Diagram (Asynchronous mode INAS pin = "H") MS1242-E-02 2014/03 -2- [AK4128A] Compatibility with AK4126 (1) Specifications Parameter Stereo Inputs Asynchronous Mode Internal Clock Bypass Mode AK4126 Not Available Synchronous Mode Only Internal PLL The PLL2-0 pins must be set according to the PLL reference clock. #61 pin: A pin for external devices of PLL filter. Not Available AK4128A Available The INAS pin controls synchronous and asynchronous modes. Internal Regulator + Internal Oscillator PLL reference clock select is not needed since internal oscillator generates the clock. #61 pin: A capacitor pin for the internal regulator. 192kHz Available Controlled by CM2-0 pins or BYPS bit. Available Controlled by CM2-0 pins 216kHz 64fs 256fs Not Available Not Available Not Available Available Available Available Controlled by IDIF2-0 pins or IDIF2-0 bits (Input) Controlled by TDM pin (Output) Individual Setting Available Individual setting is available by setting SMUTE4-1 bits in serial control mode. Individual Setting Available Individual setting is available by DEM41-40, 31-30, 21-20, 11-10 bits in serial control mode. Individual Setting Available Individual setting is available by IDIF42-40, 32-30, 22-20, 12-10 bits in serial control mode. Available Parallel and Serial control modes are selected by the SPB pin. FSI:FSO Ratio Change Detect Detects over-current/voltage of the 1.8V outputs. Master Mode for Output Ports Maximum FSI and FSO Maximum IBICK and OBICK Frequency X'tal Oscillator Master Clock Output TDM Mode Not Available Soft Mute All channels are controlled together. De-emphasis Filter All channels are controlled together. Audio Format for Input port. All channels are controlled together. I2C Not Available UNLOCK pin Detects PLL unlock. MS1242-E-02 2014/03 -3- [AK4128A] (2) Pins Pin# AK4126 AK4128A pin 1 2 7 14 15 16 17 18 32 33 42 47 48 49 51 54 55 56 57 58 59 61 NC TEST0 TST0 TST1 TST2 NC TST3 TST4 TST5 NC TST6 TEST4 NC NC TST8 PLL2 PLL1 PLL0 TST9 TST10 NC FILT IBICK2 IMCLK SDTI4 ILRCK3 IBICK3 ILRCK4 IBICK4 INAS PM2 TDM SDTO4 OMCLK/XTI XTO MCKO CAD0 TST1 SMSEMI TST2 SCL SDA SPB VD18 63 TST11 TST3 64 NC *: An external device is needed for the No 61 pin. ILRCK2 AK4126 AK4128A 6ch mode AK4126 compatible (PM2/1 pin = "LL") L L L L L L L L L L L L L L L L or H L or H L or H L L L * AK4126: "Open" AK4128A: "L" L AK4128A FILT VD18 R C2 1uF C1 Figure 3. AK4126 (Please refer to the AK4126 datasheet about external devices.) MS1242-E-02 Figure 4. AK4128A 2014/03 -4- [AK4128A] Ordering Guide 20 +85C 64pin LQFP (0.5mm pitch) 40 +85C 64pin LQFP (0.5mm pitch) Evaluation Board for AK4128A AK4128AEQ AK4128AVQ AKD4128A DVDD3 SDTO4 SDTO1 SDTO2 SDTO3 ODIF0 ODIF1 CM0 CM1 CM2 TDM 42 41 40 39 38 37 36 35 34 33 OBICK 45 VSS4 OLRCK 46 43 OMCLK/XTI 47 44 XTO 48 Pin Layout MCKO 49 32 PM2 TST0 50 31 OBIT1 CAD0 51 30 OBIT0 DVDD4 52 29 PM1 VSS5 53 28 DEM1 TST1 54 27 DEM0 SMSEMI 55 26 SMT1 TST2 56 25 SMT0 SCL 57 24 PDN SDA 58 23 DITHER Top View SPB 59 22 SMUTE AVDD 60 21 VSS3 VD18 61 20 DVDD2 VSS1 62 19 UNLOCK TST3 63 18 INAS 17 IBICK4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IMCLK ILRCK1 IBICK1 DVDD1 VSS2 SDTI4 SDTI1 SDTI2 SDTI3 IDIF0 IDIF1 IDIF2 ILRCK3 IBICK3 ILRCK4 64 IBICK2 ILRCK2 MS1242-E-02 2014/03 -5- [AK4128A] PIN / FUNCTION No. Pin Name I/O 1 IBICK2 I 2 3 4 5 6 7 8 9 10 11 12 13 IMCLK ILRCK1 IBICK1 DVDD1 VSS2 SDTI4 SDTI1 SDTI2 SDTI3 IDIF0 IDIF1 IDIF2 I I I I I I I I I I 14 ILRCK3 I 15 IBICK3 I 16 ILRCK4 I 17 IBICK4 I 18 INAS I 19 UNLOCK O 20 21 22 23 DVDD2 VSS3 SMUTE DITHER I I 24 PDN I 25 26 27 28 29 30 31 32 SMT0 SMT1 DEM0 DEM1 PM1 OBIT0 OBIT1 PM2 I I I I I I I I 33 TDM I Function Audio Serial Data Clock #2 Pin When the INAS pin = "L", this pin should be connected to VSS2-5. Master Clock Input Pin for Input PORT Input Channel Clock #1 Pin Audio Serial Data Clock #1 Pin Digital Power Supply Pin, 3.0 3.6V Digital Ground Pin Audio Serial Data Input #4 Pin Audio Serial Data Input #1 Pin Audio Serial Data Input #2 Pin Audio Serial Data Input #3 Pin Audio Interface Format #0 Pin for Input PORT (Note 2) Audio Interface Format #1 Pin for Input PORT (Note 2) Audio Interface Format #2 Pin for Input PORT (Note 2) Input Channel Clock #3 Pin When the INAS pin = "L", this pin should be connected to VSS2-5. Audio Serial Data Clock #3 Pin When the INAS pin = "L", this pin should be connected to VSS2-5. Input Channel Clock #4 Pin When the INAS pin = "L", this pin should be connected toVSS2-5. Audio Serial Data Clock #4 Pin When the INAS pin = "L", this pin should be connected to VSS2-5. Asynchronous Mode Select Pin. "L"(connected to the ground): Synchronous mode. "H"(connected to DVDD1-4) : Asynchronous mode. Unlock Status Pin When the PDN pin= "L", this pin outputs "H". Digital Power Supply Pin, 3.0 3.6V Digital Ground Pin Soft Mute Pin (Note 3) "H": Soft Mute, "L": Normal Operation Dither Enable Pin "H": Dither ON, "L": Dither OFF Power-Down Mode Pin "H": Power up, "L": Power down reset and initializes the control register. The AK4128A should be reset once by bringing PDN pin = "L" upon power-up. Soft Mute Timer Select #0 Pin Soft Mute Timer Select #1 Pin De-emphasis Control #0 Pin (Note 4) De-emphasis Control #1 Pin (Note 4) Channel Mode Select #1 Pin Bit Length Select #0 Pin for Output Data Bit Length Select #1 Pin for Output Data Channel Mode Select #2 Pin TDM Format Select Pin. "L"(connected to the ground): Stereo mode. "H"(connected to DVDD1-4) : TDM mode. MS1242-E-02 2014/03 -6- [AK4128A] No. 34 35 36 37 38 Pin Name CM2 CM1 CM0 ODIF1 ODIF0 I/O I I I I I 39 SDTO3 O 40 SDTO2 O 41 SDTO1 O 42 SDTO4 O 43 44 VSS4 DVDD3 - 45 OBICK I/ O 46 OLRCK I/ O 47 OMCLK/XTI I 48 XTO O 49 MCKO O 50 TST0 I 51 CAD0 I 52 53 54 DVDD4 VSS5 TST1 I 55 SMSEMI I 56 TST2 I 57 SCL I 58 SDA I/ O 59 SPB I Function Clock Select or Mode Select #2 Pin for Output PORT Clock Select or Mode Select #1 Pin for Output PORT Clock Select or Mode Select #0 Pin for Output PORT Audio Interface Format #1 Pin for Output PORT Audio Interface Format #0 Pin for Output PORT Audio Serial Data Output #3 Pin for Output PORT When the PDN pin = "L", the SDRO3 pin outputs "L". Audio Serial Data Output #2 Pin for Output PORT When the PDN pin = "L", the SDTO2 pin outputs "L". Audio Serial Data Output #1 Pin for Output PORT When the PDN pin = "L", the SDTO1 pin outputs "L". Audio Serial Data Output #4 Pin for Output PORT When the PDN pin = "L", the SDRO4 pin outputs "L". Digital Ground Pin Digital Power Supply Pin, 3.0 3.6V Audio Serial Data Clock Pin for Output PORT When the PDN pin = "L" in master mode, the OBOCK pin outputs "L". Output Channel Clock Pin for Output PORT When the PDN pin = "L" in master mode, the OBOCK pin outputs "L". External Master Clock Input / X'tal Input Pin X'tal Output Pin When the PDN pin = "L", XTO outputs Hi-z. Master Clock Output Pin When the PM2 pin = "H" and PDN pin = "L", the MCKO pin outputs "L". When the PM2 pin = "L" and PDN pin = "L", the MCKO pin outputs Hi-z. Test Pin. This pin should be connected to VSS2-5. Chip Address 0 pin This pin must be connected to VSS2-5 in parallel control mode (SPB pin = "L"). Digital Power Supply Pin, 3.0 3.6V Digital Ground Pin Test Pin. This pin should be connected to VSS2-5. Soft Mute Semi-auto Mode Setting Pin "H": Semi-auto, "L": Manual Mode Test Pin. This pin should be connected to VSS2-5. I2C Control Data Clock Pin, (when the SPB pin= "H") Since there is a protection diode between this pin and DVDD1-4, connect pulled-up resister to DVDD1-4 + 0.3V or less. This pin must be connected to the VSS2-5 in parallel control mode (PSB pin= "L"). I2C Control Data In/Out put Pin, (when the SPB pin= "H") Since there is a protection diode between this pin and DVDD1-4, connect pulled-up resister to DVDD1-4 + 0.3V or less. This pin must be connected to the VSS2-5 in parallel control mode (PSB pin= "L"). Parallel/Serial Control Mode Select Pin "H": Serial Control Mode, "L": Parallel Control Mode MS1242-E-02 2014/03 -7- [AK4128A] No. 60 Pin Name AVDD I/O - Function Analog Power Supply Pin, 3.0 3.6V Digital Power Output Pin, Typ 1.8V When the PDN pin= "L", the DV18 pin outputs "L". Current must not be taken 61 VD18 O from this pin. A 1F (30%; including the temperature characteristics) capacitor should be connected between this pin and DVSS. When this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin. 62 VSS1 Analog Ground Pin Test Pin. 63 TST3 I This pin should be connected to VSS2-5. Input Channel Clock #2 Pin 64 ILRCK2 I When INAS pin = "L", this pin should be connected to VSS2-5. Note: All input pins should not be left floating. DVDD1-4 must be connected to the same power supply. Note 1. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be changed when the PDN pin= "L". Note 2. In parallel control mode (SPB pin = "L"), IDIF2-0 pins control all SRC1~4 audio interface input formats. In serial control mode (SPB pin = "H"), the setting of IDIF2-0 pins is ignored. The IDIF[12:10] bits setting is reflected to SRC1, the IDIF[22:20] bits setting is reflected to SRC2, the IDIF[32:30] bits setting is reflected to SRC3, and the IDIF[42:40] bits setting is reflected to SRC4. Note 3. In parallel control mode (SPB pin = "L"), the SMUTE pin controls all SRC1~4 soft mute. In serial control mode (SPB pin = "H"), the SUMUTE pin setting is ignored. The SMUTE1 bit setting is reflected to SRC1, the SMUTE2 bit setting is reflected to SRC2, the SMUTE3 bit setting is reflected to SRC3, and the SMUTE4 bit setting is reflected to SRC4. Note 4. In parallel control mode (SPB pin= "L"), DEM1-0 pins control all SRC1~4 de-emphasis settings. In serial control mode (SPB pin= "H"), setting of DEM1-0 pins is ignored. DEM[11:10] bits setting is reflected to SRC1, DEM[21:20] bits setting is reflected to SRC2, DEM[31:30] bits setting is reflected to SRC3, and DEM[41:40] bits setting is reflected to SRC4. Handling of Unused Pins The unused I/O pins should be processed appropriately as below. Classification Digital Pin Name IBICK2, IMCLK, SDTI3-4, ILRCK3, IBICK3, ILRCK4, IBICK4, SMUTE, DITHER, OMCLK/XTI, ILRCK2, SDA, SCL, CAD0, TST0-3 UNLOCK, SDTO1-4, MCKO, XTO MS1242-E-02 Setting These pins must be connected to VSS2-5. These pins must be open. 2014/03 -8- [AK4128A] ABSOLUTE MAXIMUM RATINGS (VSS1-5=0V; Note 5) Parameter Symbol min max Unit Analog AVDD 0.3 4.2 V Power Supplies: Digital DVDD1-4 0.3 4.2 V Input Current, Any Pin Except Supplies IIN 10 mA Digital Input Voltage (Note 6) VIND 0.3 DVDD1-4+0.3 V AK4128AEQ Ta 20 85 C Ambient Temperature (Power applied) (Note 7) AK4128AVQ Ta 40 85 C Storage Temperature Tstg 65 150 C Note 5. All voltages with respect to ground. VSS1-5 must be connected to the same ground. Note 6. IMCLK, IBICK4-1, ILRCK4-1, IDIF2-0, INAS, SUMTE, DITHER, PDN, SMT1-0, DEM1-0, PM2-1, OBIT1-0, TDM, CM2-0, ODIF1-0, SDTO4-1, OBICK, OLRCK, OMCLK/XTI, CAD0, SMSEMI, SCL, SDA and SPB pins. Note 7. In case that wiring density is 100%. Note 8. DVDD1-4 pins must be connected to the same power supply. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1-5=0V; Note 5) Parameter Power Supplies: (Note 9) Symbol min typ max Unit Analog AVDD 3.0 3.3 3.6 V Digital DVDD1-4 3.0 3.3 3.6 V Difference AVDD - DVDD1-4 -0.3 0 +0.3 V Note 5. All voltages with respect to ground. VSS1-5 must be connected to the same ground. Note 8. DVDD1-4 pins must be connected to the same power supply. Note 9. The power up sequence between AVDD and DVDD1-4 is not critical but the PDN pin must be "L" until all power supplies are ON, then put the PDN pin to "H". WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1242-E-02 2014/03 -9- [AK4128A] SRC CHARACTERISTICS (Ta=25C; AVDD=DVDD1-4=3.3V; VSS1-5=0V; Signal Frequency = 1kHz; data = 24bit; Measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter Symbol min SRC Characteristics: Resolution Input Sample Rate FSI 8 Output Sample Rate FSO 8 THD+N (Input = 1kHz, 0dBFS, Note 10) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz Worst Case (FSO/FSI = 32kHz/176.4kHz) Dynamic Range (Input = 1kHz, 60dBFS, Note 10) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 48kHz/192kHz FSO/FSI = 192kHz/48kHz Worst Case (FSO/FSI = 48kHz/32kHz) 132 Dynamic Range (Input = 1kHz, 60dBFS, A-weighted, Note 10) FSO/FSI = 44.1kHz/48kHz Ratio between Input and Output Sample Rate FSO/FSI 1/6 Note 10. Measured by Audio Precision System Two Cascade. typ max Unit 24 216 216 Bits kHz kHz 130 124 133 124 - -91 dB dB dB dB dB 136 136 136 132 - - dB dB dB dB dB 140 6 dB - POWER CONSUMPTION (Ta= 25C; AVDD=DVDD1-4=3.0~3.6V; VSS1-5=0V; Signal Frequency=1kHz; data=24bit; Asynchronous Input mode (INAS pin = "H"), Output PORT: Master mode, OMCLK/XTI are input via a X'tal. PM2/1 pin = "H/L" 8ch mode, unless otherwise specified.) Parameter min typ max Unit Power Supplies Power Supply Current Normal operation (PDN pin = "H") AVDD+DVDD1-4 FSI=FSO=48kHz: AVDD=DVDD1-4=3.3V (Note 12) 42 mA FSI=FSO=192kHz: AVDD=DVDD1-4=3.3V (Note 13) 108 mA : AVDD=DVDD1-4=3.6V (Note 14) 109 164 mA Power down (PDN pin = "L") (Note 11) AVDD+DVDD1-4 10 100 A Note 11. All digital input pins are held to VSS2-5. Note 12. It is 41 [mA] (typ) when the OMCLK/XTI pin is supplied a 24.576MHz external clock and the output port is in slave mode. Note 13. It is 105 [mA] (typ) when the OMCLK/XTI pin is supplied a 24.576MHz external clock and the output port is in slave mode. Note 14. It is 106 [mA] (typ) when the OMCLK/XTI pin is supplied a 24.576MHz external clock and the output port is in slave mode. MS1242-E-02 2014/03 - 10 - [AK4128A] FILTER CHARACTERISTICS (Ta= 25C; AVDD=DVDD1-4=3.0 3.6V) Parameter Symbol min typ max Unit Digital Filter 0.4583FSI Passband 0.01dB 0.985 FSO/FSI 6.000 PB 0 kHz 0.4167FSI 0.905 FSO/FSI 0.985 PB 0 kHz 0.3195FSI 0.714 FSO/FSI 0.905 PB 0 kHz 0.2852FSI 0.656 FSO/FSI 0.714 PB 0 kHz 0.2182FSI 0.536 FSO/FSI 0.656 PB 0 kHz 0.2177FSI 0.492 FSO/FSI 0.536 PB 0 kHz 0.1948FSI 0.452 FSO/FSI 0.492 PB 0 kHz 0.1458FSI 0.357 FSO/FSI 0.452 PB 0 kHz 0.1302FSI 0.324 FSO/FSI 0.357 PB 0 kHz 0.0917FSI 0.246 FSO/FSI 0.324 PB 0 kHz 0.0826FSI 0.226 FSO/FSI 0.246 PB 0 kHz 0.0583FSI 0.1667 FSO/FSI 0.226 PB 0 kHz Stopband 0.985 FSO/FSI 6.000 SB 0.5417FSI kHz 0.905 FSO/FSI 0.985 SB 0.5021FSI kHz 0.714 FSO/FSI 0.905 SB 0.3965FSI kHz 0.656 FSO/FSI 0.714 SB 0.3643FSI kHz 0.536 FSO/FSI 0.656 SB 0.2974FSI kHz 0.492 FSO/FSI 0.536 SB 0.2813FSI kHz 0.452 FSO/FSI 0.492 SB 0.2604FSI kHz 0.357 FSO/FSI 0.452 SB 0.2116FSI kHz 0.324 FSO/FSI 0.357 SB 0.1969FSI kHz 0.246 FSO/FSI 0.324 SB 0.1573FSI kHz 0.226 FSO/FSI 0.246 SB 0.1471FSI kHz 0.1667 FSO/FSI 0.226 SB 0.1020FSI kHz Passband Ripple PR 0.01 dB Stopband 0.985 FSO/FSI 6.000 SA 121.2 dB Attenuation 0.905 FSO/FSI 0.985 SA 121.4 dB 0.714 FSO/FSI 0.905 SA 115.3 dB 0.656 FSO/FSI 0.714 SA 116.9 dB 0.536 FSO/FSI 0.656 SA 114.6 dB 0.492 FSO/FSI 0.536 SA 100.2 dB 0.452 FSO/FSI 0.492 SA 103.3 dB 0.357 FSO/FSI 0.452 SA 102.0 dB 0.324 FSO/FSI 0.357 SA 103.6 dB 0.246 FSO/FSI 0.324 SA 103.3 dB 0.226 FSO/FSI 0.246 SA 101.5 dB 0.1667 FSO/FSI 0.226 SA 73.2 dB Group Delay (Note 15) GD 64 1/fs Note 15. This value is the time from the rising edge of ILRCK after SDTI data is input to rising edge of OLRCK after the SDTI data is output, when OLRCK data corresponds with ILRCK data. MS1242-E-02 2014/03 - 11 - [AK4128A] DC CHARACTERISTICS (Ta= 25C; AVDD=DVDD1-4=3.0 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Except the SDA pin (Iout=400A) Low-Level Output Voltage Except the SDA pin (Iout=400A) SDA pin (Iout=3mA) Input Leakage Current Symbol VIH VIL min 70%DVDD1-4 - typ - max 30%DVDD1-4 Unit V V VOH DVDD1-4 0.4 - - V VOL VOL Iin - - - - 0.4 0.4 10 V V A SWITCHING CHARACTERISTICS (Ta= 25C; AVDD=DVDD1-4=3.0 3.6V; CL=20pF) Parameter Symbol min typ max Unit Master Clock Timing fXTAL 11.2896 24.576 MHz Crystal Oscillator Frequency IMCLK Input Frequency fECLK 1.024 36.864 MHz Duty dECLK 40 50 60 % OMCLK Input 128 FSO : fCLK 1.024 27.648 MHz Pulse Width Low tCLKL 13 ns Pulse Width High tCLKH 13 ns 256 FSO : fCLK 2.048 27.648 MHz Pulse Width Low tCLKL 13 ns Pulse Width High tCLKH 13 ns 384 FSO : fCLK 3.072 36.864 MHz Pulse Width Low tCLKL 10 ns Pulse Width High tCLKH 10 ns 512 FSO : fCLK 4.096 27.648 MHz Pulse Width Low tCLKL 13 ns Pulse Width High tCLKH 13 ns 768 FSO : fCLK 6.144 36.864 MHz Pulse Width Low tCLKL 10 ns Pulse Width High tCLKH 10 ns MCKO Output Frequency fMCK 1.024 36.864 MHz Duty (Note 16) dMCLK 40 50 60 % Note 16. This is a value of MCKO output duty when the master clock for output ports is supplied by a crystal oscillator. MS1242-E-02 2014/03 - 12 - [AK4128A] Input PORT LRCK for Stereo Mode (ILRCK1-4) Frequency Duty Cycle Slave Mode Output PORT LRCK for Stereo Mode (OLRCK) Frequency Slave mode Master mode OMCLK Input 128FSO mode Master mode OMCLK Input 256FSO mode Master mode OMCLK Input 384FSO mode Master mode OMCLK Input 512FSO mode Master mode OMCLK Input 768FSO mode Duty Cycle Slave Mode Master Mode Input PORT LRCK for TDM256 Mode (ILRCK1) Asynchronous Inputs Mode (INAS pin = "L") Frequency "H" time (slave mode) "L" time (slave mode) Output PORT LRCK for TDM256 Mode (OLRCK) Frequency "H" time (slave mode) "L" time (slave mode) "H" time (Master mode, TDM256 24bit MSB justified) "L" time (Master mode, TDM256 24bit I2S) Audio Interface Timing Input PORT ( Stereo Slave mode) IBICK1-4 Period (FSI= 8kHz 54kHz) (FSI=54kHz 108kHz) (FSI=108kHz 216kHz) IBICK1-4 Pulse Width Low Pulse Width High ILRCK1-4 Edge to IBICK1-4 ""(Note 17) IBICK1-4 "" to ILRCK1-4 Edge (Note 17) SDTI1-4 Hold Time from IBICK1-4 "" SDTI1-4 Setup Time to IBICK1-4 "" Input PORT (TDM256 slave mode) IBICK1 Period IBICK1 Pulse Width Low Pulse Width High ILRCK1 Edge to IBICK1 "" (Note 17) IBICK1 "" to ILRCK1 Edge (Note 17) SDTI1 Hold Time from IBICK1 "" SDTI1 Setup Time to IBICK1 "" Output PORT ( Stereo Slave mode) OBICK Period (FSO= 8kHz 54kHz) (FSO= 54kHz 108kHz) (FSO=108kHz 216kHz) OBICK Pulse Width Low Pulse Width High OLRCK Edge to OBICK "" (Note 17) OBICK "" to OLRCK Edge (Note 17) OLRCK to SDTO1-4 (MSB) (Except I2S mode) OBICK "" to SDTO1-4 FSI Duty 8 48 216 52 kHz % FSO FSO FSO FSO FSO FSO Duty Duty 8 8 8 8 8 8 48 216 216 108 96 54 48 52 kHz kHz kHz kHz kHz kHz % % FSI tLRH tLRL 8 1/256FSI 1/256 FSI 48 kHz ns ns FSO tLRH tLRL 8 1/256 FSO 1/256 FSO 48 kHz ns ns tLRH - 1/32 FSO - ns tLRL - 1/32 FSO - ns tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 1/256 FSI 1/128 FSI 1/64 FSI 27 27 15 15 15 15 ns ns ns ns ns ns ns ns ns tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 81 32 32 20 20 20 10 ns ns ns ns ns ns ns tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/256 FSO 1/128 FSO 1/64 FSO 27 27 20 20 ns ns ns ns ns ns ns ns ns MS1242-E-02 50 50 50 20 20 2014/03 - 13 - [AK4128A] Output PORT (TDM256 slave mode) OBICK Period tBCK 81 ns OBICK Pulse Width Low tBCKL 32 ns Pulse Width High tBCKH 32 ns OLRCK Edge to OBICK "" (Note 17) tLRB 20 ns OBICK "" to OLRCK Edge (Note 17) tBLR 20 ns OBICK "" to SDTO1 tBSD 20 ns Output PORT (Stereo Master mode) OBICK Frequency fBCK 64 FSO Hz OBICK Duty dBCK 50 % OBICK "" to OLRCK Edge tMBLR 20 20 ns OBICK "" to SDTO1-4 tBSD 20 20 ns Output PORT (TDM256 master mode) OBICK Frequency fBCK 256 FSO Hz OBICK Duty dBCK 50(Note 19) % OBICK "" to OLRCK Edge tMBLR 10 10 ns OBICK "" to SDTO1 tBSD 20 20 ns Reset Timing PDN Pulse Width (Note 18) tPD 150 ns Note 17. BICK rising edge must not occur at the same time as LRCK edge. Note 18. The AK4128A can be reset by bringing the PDN pin = "L". Note 19. When OMCLK=512FSO. If the OMCLK=256FSO, OMCLK clock is though and output from the OBICK pin. When OMCLK = 384FSO, dBCK= (tCLKH)/(tCLKH+1/fCLK) x100 [%] or (tCLKL)/(tCLKL+1/fCLK) x100 [%]. When OMCLK=768FSO, dBCK= (1/fCLK)/(3/fCLK) x100 [%]. OMCLK=384FSO 1/fCLK 1/fCLK tCLKH OMCLK pin tCLKL tCLKL tCLKH OBICK pin Ouput (TDM256 Master mode) tCLKL 1/fCLK 1/fCLK OMCLK=768FSO 1/fCLK 1/fCLK 1/fCLK OMCLK pin 1/fCLK OBICK pin Output (TDM256 Master mode) 3/fCLK 3/fCLK MS1242-E-02 2014/03 - 14 - [AK4128A] Parameter Symbol min typ Control Interface Timing (I2C Bus): SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time tHD:STA 0.6 (prior to first clock pulse) Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 20) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise tSP 0 Suppressed by Input Filter Capacitive load on bus Cb Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. MS1242-E-02 max Unit 400 - kHz s s 0.3 0.3 50 s s s s s s s s ns 400 pF 2014/03 - 15 - [AK4128A] Timing Diagram 1/fECLK VIH IMCLK(I) VIL tECLKH tECLKL dECLK = tECLKH (or tECLKL) x fECLK x 100 1/fCLK VIH OMCLK(I) VIL tCLKH tCLKL 1/fMCK 50%DVDD MCKO(O) tMCKH tMCKL dMCLK = tMCKH (or tMCKL) x fMCK x 100 Figure 5. IMCLK, OMCLK, MCKO Clock Timing *Stereo Mode and Slave Mode 1/FSI VIH LRCK1-4(I) VIL tLRCH tLRCL Duty = tLRCH (or tLRCL) x FSI x 100 tBCK VIH IBICK1-4(I) VIL tBCKH tBCKL *TDM256 Mode and Slave Mode 1/FSI VIH LRCK1(I) VIL tLRH tLRL tBCK VIH IBICK1(I) VIL tBCKH tBCKL Figure 6. ILRCK1-4, IBICK1-4 Clock Timing MS1242-E-02 2014/03 - 16 - [AK4128A] * Stereo Mode and Slave Mode 1/FSO VIH OLRCK(I) VIL tLRCH tLRCL Duty = tLRCH (or tLRCL) x FSO x 100 tBCK VIH OBICK(I) VIL tBCKH tBCKL * TDM256 Mode and Slave Mode 1/FSO VIH OLRCK(I) VIL tLRH tLRL tBCK VIH OBICK(I) VIL tBCKH tBCKL Figure 7. OLRCK, OBICK, Clock Timing (Slave Mode) * Stereo Mode and Master Mode 1/FSO 50%DVDD OLRCK(O) tLRCH tLRCL Duty = tLRCH (or tLRCL) x FSO x 100 1/ fBCK 50%DVDD OBICK(O) tBICKH tBICKL dBCK = tBICKH(or tBICKL) x fBCK x 100 * TDM256 Mode and Master Mode 1/FSO 50%DVDD OLRCK(O) 24bit MSB justified tLRH 1/FSO 50%DVDD OLRCK(O) 24bit I2S tLRL 1/ fBCK 50%DVDD OBICK(O) tBICKH tBICKL dBCK = tBICKH(or tBICKL) x fBCK x 100 Figure 8. OLRCK, OBICK, Clock Timing (Master Mode) MS1242-E-02 2014/03 - 17 - [AK4128A] VIH ILRCK 1 -4 VIL tBLR tLRB VIH IBICK 1- 4 VIL tSDS tSDH VIH SDTI 1 -4 VIL Figure 9. Input PORT Audio Interface Timing (Stereo Slave mode and TDM256 Slave Mode) VI H VI L O LRCK tBL R tLR B VI H VI L O BIC K tBS D tLR S SDT 1- 4 O 50 D VD % D Figure 10. Output PORT Audio Interface Timing (TDM256 Slave mode & Stereo Slave mode) MS1242-E-02 2014/03 - 18 - [AK4128A] OLRCK 50%DVDD tMBLR 50%DVDD OBICK tBSD 50%DVDD SDTO1-4 Figure 11. Output PORT Audio Interface Timing (TDM256 Master mode & Stereo Master mode) tPD PDN VIL Figure 12. Power Down Timing VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 13. I2C Bus Timing MS1242-E-02 2014/03 - 19 - [AK4128A] OPERATION OVERVIEW Synchronous and Asynchronous Modes Setting There are two modes of operation: asynchronous and synchronous modes. The AK4128A is set to Synchronous mode when the INAS pin is "L" and it is set to Asynchronous mode when the INAS pin is "H". INAS pin Mode Data LRCK BICK SDTI1 SDTI2 Synchro ILRCK1 IBICK1 L nous (Note 21) (Note 22) SDTI3 SDTI4 SDTI1 ILRCK1 IBICK1 SDTI2 ILRCK2 IBICK 2 Asynchr H onous SDTI3 ILRCK3 IBICK 3 SDTI4 ILRCK4 IBICK 4 Note 21. ILRCK2-4 pins must be connected to VSS2-5. Note 22. IBICK2-4 pins must be connected to VSS2-5. Table 1. Input Data Synchronous/Asynchronous Mode Setting Audio Interface Format for Input PORT The audio data format of input port is MSB first, 2's complement format. The SDTI1, SDTI2, SDTI3 and SDTI4 are latched on the rising edge of IBICK1, IBICK2, IBIXK3 and IBICK4 respectively. In parallel control mode (SPB pin= "L"), IDIF2-0 pins control all audio interface formats of SRC1~4. IDIF2-0 pins must be set during the PDN pin= "L". In serial control mode (SPB pin = "H"), setting of IDIF2-0 pins is ignored. IDIF[12:10] bits setting is reflected to SRC1, IDIF[22:20] bits setting is reflected to SRC2, IDIF[32:30] bits setting is reflected to SRC3, and IDIF[42:40] bits setting is reflected to SRC4. IDIF[12:10] bits should be changed after all SDTO1 output codes become zero during soft mute by SMUTE1 bit = "1" or the SMUTE pin = "H". IDIF[22:20] bits should be changed after all SDTO2 output codes become zero during soft mute by SMUTE2 bit = "1" or the SMUTE pin = "H". IDIF[32:30] bits should be changed after all SDTO3 output codes become zero during soft mute by SMUTE3 bit = "1" or the SMUTE pin = "H". IDIF[42:40] bits should be changed after all SDTO4 output codes become zero during soft mute by SMUTE4 bit = "1" or the SMUTE pin = "H". TDM mode (Mode 5/6) can be set in Synchronous Inputs mode (INAS pin = "L"). Serial data for 8channels should be input from the SDTI1 pin. In this mode, connect SDTI2-4 pins to VDD2-5 because there pins are ignored. Asynchronous Inputs mode (INAS pin = "H") does not support TDM mode. The AK4128A is not able to operate correctly because of SDTI1-4 data inputs are incorrect. TDM mode is must be OFF, when using the AK4128A in asynchronous inputs mode (INAS pin = "H"). The maximum input frequency of IBICK1-4 is 256FSI. MS1242-E-02 2014/03 - 20 - [AK4128A] Mode 0 1 2 3 4 5 6 IDIF2 Pin (Note 23) L L L IDIF1 Pin (Note 23) L L H IDIF0 Pin (Note 23) L H L SDTI1-4 Format ILRCK 1-4 IBICK 1-4 IBICK1-4 Freq 16bit, LSB justified 32FSI 20bit, LSB justified 40FSI 24bit, MSB justified 48FSI 24 or 16bit, I2S Compatible 48FSI Input Input L H H 16bit, I2S Compatible 32FSI H L L 24bit, LSB justified 48FSI H L H TDM 24bit, MSB justified 256FSI H H X TDM 24bit, I2S Compatible 256FSI Table 2. Input PORT Audio Interface Format (Parallel Control Mode, SPB pin= "L") (X= Don't care) Note 23. In serial control mode (SPB pin = "H"), setting of IDIF2-0 pins is ignored. IDIF[12:10] bits setting is reflected to SRC1, IDIF[22:20] bits setting is reflected to SRC2, IDIF[32:30] bits setting is reflected to SRC3, and IDIF[42:40] bits setting is reflected to SRC4. ILRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 IBICK(32fs) SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 0 1 2 3 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1 IBICK(64fs) SDTI(i) Don't Care 15 14 13 12 1 0 Don't Care 15 14 13 12 2 1 0 15:MSB, 0:LSB Lch Data Rch Data Figure 14. Mode 0 Timing (16bit, LSB justified) ILRCK 0 1 2 12 13 24 31 0 1 2 12 13 24 31 0 1 IBICK(64fs) SDTI(i) Don't Care 19 8 1 0 Don't Care 19 8 1 0 19:MSB, 0:LSB Lch Data Rch Data Figure 15. Mode 1 Timing (20bit, LSB justified) ILRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 IBICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 16. Mode 2 Timing (24bit, MSB justified) MS1242-E-02 2014/03 - 21 - [AK4128A] ILRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 IBICK(64fs) 23 22 SDTI(i) 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23:MSB, 0:LSB Lch Data Rch Data 2 Figure 17. Mode 3 Timing (24bit I S) ILRCK 0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1 IBICK(64fs) Don't Care SDTI(i) 23 8 1 0 Don't Care 23 8 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 18. Mode 4 Timing (24bit, LSB justified) Note: SDTI is identified as SDTI1, SDTI2, SDTI3 and SDTI4, ILRCK is identified as ILRCK1, ILRCK2, ILRCK3 and ILRCK4, IBICK is identified as IBICK1, IBICK2, IBICK3 and IBICK4. 256 IBICK ILRCK1(I) IBICK1 (I: 256FSI) SDTI1(I) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 I BICK 32 I BICK 32 I BICK Figure 19. Mode 5 Timing (TDM, 24bit, MSB justified, SDTI2-4: Don't care) 256 IBICK ILRCK1(I) IBICK1(I: 256FSI) SDTI1(I) 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 L1 R1 L2 R2 L3 R3 L4 R4 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 IBICK 32 IBICK 23 Figure 20. Mode 6 Timing (TDM, I2S, SDTI2-4: Don't care) MS1242-E-02 2014/03 - 22 - [AK4128A] System Clock for Output PORT The output ports work in master mode and slave mode. The CM2-0 pins select the master/slave mode. OMCLK/XTI FSO with CM2 CM1 CM0 Mode Master / Slave MCKO Output FSO pin pin pin Input X'tal 0 L L L Master 256FSO 256FSO 44.1~96kHz 8k108kHz 1 L L H Master 384FSO 384FSO 29.4~64kHz 8k96kHz 2 L H L Master 512FSO 512FSO 22.05~48kHz 8k54kHz 3 L H H Master 768FSO 768FSO 14.7~32kHz 8k48kHz OMCLK Input 4 H L L Slave Not used. (Note 24) 8k216kHz Clock 5 H L H Master 128FSO (Note 25) 128FSO 8k216kHz 88.2~192kHz 6 H H L Slave(Bypass) IMCLK Input Not used. (Note 24) 8k216kHz Clock 7 H H H Master(Bypass) Note 24. Use for a clock input or connect to VSS2-5 pin. In Mode 4, the MCKO pin outputs "L" if the OMCLK/XTI pin is connected to VSS2-5. When a clock is input to the OMCLK/XTI pin, the clock is through and output from the MCKO pin. In Mode 6-7, OMCLK/XTI input is ignored internally. Note 25. Output ports do not support TDM mode in this mode. Table 3. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = "L") In serial control mode (SPB pin = "H"), the BYPS bit selects SRC bypass mode and SRC mode. The default value of the BYPS bit is "0" (SRC mode). Mode CM2 pin CM1 pin CM0 pin BYPS bit Master / Slave 0 1 2 3 L L L L L L H H L H L H 0 0 0 0 Master Master Master Master OMCLK/XTI Input 256FSO 384FSO 512FSO 768FSO 4 H L L 0 Slave Not used. (Note 26) MCKO Output 256FSO 384FSO 512FSO 768FSO OMCLK Input Clock 128FSO 8108kHz 896kHz 854kHz 8k~48kHz FSO with X'tal 44.1~96kHz 29.4~64kHz 22.05~48kHz 14.7~32kHz 8216kHz - FSO 5 H L H 0 Master 128FSO (Note 25) 8216kHz 88.2~192kHz 6 H H L 0 Slave (Bypass) 7 H H H 0 Master (Bypass) 8 L L L 1 Master (Bypass) 9 L L H 1 Master (Bypass) IMCLK 10 L H L 1 Master (Bypass) Not used. (Note 26) Input 8216kHz 11 L H H 1 Master (Bypass) Clock 12 H L L 1 Slave (Bypass) 13 H L H 1 Master (Bypass) 14 H H L 1 Slave (Bypass) 15 H H H 1 Master (Bypass) Note 26. Use for a clock input or connect to VSS2-5 pin. In Mode 4, the MCKO pin outputs "L" if the OMCLK/XTI pin is connected to VSS2-5. When a clock is input to the OMCLK/XTI pin, the clock is through and output from the MCKO pin. In Mode 6-15, OMCLK/XTI input is ignored internally. Table 4. Output PORT Master/Slave/ Bypass Mode Control (SPB pin = "H") MS1242-E-02 2014/03 - 23 - [AK4128A] (1) Master Mode The OLRCK pin and OBICK pin are output pins in master mode. Master clock is supplied from the OMCLK/XTI pin. The clock for the OMCLK/XTI pin can be generated by the following methods: Connect a crystal oscillator between the OMCLK/XTI and XTO pins, or input a clock to the OMCLK/XTI pin. In bypass mode, the MCKO pin outputs IMCLK data. a. X'tal The OMCLK/XTI pin is pulled down when the PDN pin= "L". XTI C 460k (typ) C XTO AK4128A Note: Refer to Table 5 for the capacitor and resistor values of the X'tal oscillator. Figure 21. X'tal Mode Nominal Frequency [MHz] 11.2896 12.288 24.576 Equivalent Series Resistance R1[] max 60 External Capacitance C[pF] max 15 Table 5. Equivalent Series Resistor and External Capacitor for External X'tal Oscillator In X'tal mode at 256FSO OMCLK input, FSO ranges from 44.1kHz to 96kHz. In X'tal mode at 384FSO OMCLK input, FSO ranges from 29.4kHz to 64kHz. In X'tal mode at 512FSO OMCLK input, FSO ranges from 22.05kHz to 48kHz. In X'tal mode at 768FSO OMCLK input, FSO ranges from 14.7kHz to 32kHz. In X'tal mode at 128FSO OMCLK input, FSO ranges from 88.2kHz to 192kHz. b. External Clcok - Note: Do not input the clock over DVDD1-4. XTI External Clock 460k (typ) XTO AK4128A Figure 22. External Clock (OMCLK) mode (2) Slave Mode The OLRCK pin and OBICK pin are input pins in slave mode. MS1242-E-02 2014/03 - 24 - [AK4128A] (3) SRC Bypass Mode SRC bypass mode can be set in Synchronous inputs mode (INAS pin = "L"). Asynchronous inputs mode (INAS pin = "H") does not supports SRC bypass mode, so that the data is not transferred correctly on SDTI1SDTO1, SDTI2SDTO2, SDTI3SDTO3 and SDTI4SDTO4 lines. In Asynchronous inputs mode (INAS pin = "H"), the AK4128A should be used in SRC mode. DITHER SMT1 SMT0 SMSEMI SMUTE VSS2-5 DVDD1-4 INAS DEM1 DEM0 IDIF2 IDIF1 IDIF0 When the AK4128A is in slave mode, SDTI1-4 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode (Table 2). The SDTI1-4 data are output from the OLRCK and OBICK pins in a format shown in Table 6 and Table 7. IBICK and OBICK must be synchronized but the phase is not critical. ILRCK and OLRCK must be synchronized but the phase is not critical. OLRCK OBICK SRC1 Bypass Input Serial Audio I/F IBICK1 ILRCK1 SDTI1 DEM FIR SRC SMUTE + Dither 0.5 LSB SRC Input Serial Audio I/F DEM FIR SRC SMUTE SRC Dither + DEM FIR SRC SMUTE SRC + DEM FIR SRC SRC4 SMUTE SRC Dither IMCLK PDN PM1 PM2 Internal OSC uP I/F CAD0 X'tal Osc SDA SCL XTO OMCLK/XTI SPB SDTO3 0.5 LSB Bypass Input Serial Audio I/F + SDTO4 0.5 LSB UNLOCK Bypass Clock Div CM2 CM1 CM0 SDTO2 SRC3 Dither IBICK4 ILRCK4 SDTI4 ODIF1 ODIF0 Output Serial Audio I/F 0.5 LSB Bypass Input Serial Audio I/F IBICK3 ILRCK3 SDTI3 OBIT1 OBIT2 SRC2 Bypass IBICK2 ILRCK2 SDTI2 SDTO1 MCKO SRC Internal Regulator REF AVDD VSS1 VD18 Figure 23. Bypass Mode in Slave Mode (Synchronous mode INAS pin = "L") MS1242-E-02 2014/03 - 25 - [AK4128A] DITHER SMT1 SMT0 SMSEMI SMUTE VSS2-5 DVDD1-4 INAS DEM1 DEM0 IDIF2 IDIF1 IDIF0 When the AK4128A is in master mode, SDTI1-4 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode (Table 2). The SDTI1-4 output data are output by the ILRCK1 and IBICK1 clocks in a format shown in Table 6 and Table 7. The ILRCK1 clock bypasses the SRC and it is output from the OLRCK pin. The IBICK1 clock bypasses the SRC and it is output from the OBICK pin. OLRCK OBICK SRC1 Bypass Input Serial Audio I/F IBICK1 ILRCK1 SDTI1 DEM FIR SRC SMUTE + Dither 0.5 LSB SRC IBICK2 ILRCK2 SDTI2 DEM FIR SRC SMUTE SRC Dither + DEM FIR SRC SRC + DEM FIR SRC SRC4 SMUTE SRC Dither IMCLK PDN PM1 PM2 Internal OSC uP I/F CAD0 X'tal Osc SDA SCL XTO OMCLK/XTI SPB SDTO3 0.5 LSB Bypass Input Serial Audio I/F + SDTO4 0.5 LSB UNLOCK Bypass Clock Div CM2 CM1 CM0 SDTO2 SRC3 SMUTE Dither IBICK4 ILRCK4 SDTI4 ODIF1 ODIF0 Output Serial Audio I/F 0.5 LSB Bypass Input Serial Audio I/F IBICK3 ILRCK3 SDTI3 OBIT1 OBIT2 SRC2 Bypass Input Serial Audio I/F SDTO1 MCKO SRC Internal Regulator REF AVDD VSS1 VD18 Figure 24. Bypass Mode in Master Mode (Synchronous mode INAS pin = "L") MS1242-E-02 2014/03 - 26 - [AK4128A] Audio Interface Format for Output PORT The ODIF1-0 pins and OBIT1-0 pins select the audio interface format for the output port. The audio data is MSB first, 2's complement format. The SDTO1-4 is clocked out on the falling edge of OBICK. Select the audio interface format for output port when the PDN pin = "L". If the AK4128A is in slave mode at bypass mode, IBICK1 and OBICK must be synchronized but the phase is not critical. ILRCK1 and OLRCK must be synchronized but the phase is not critical. The audio interface format of SDTO1, SDTO2, SDTO3 and SDTO4 are controlled together by ODIF1-0 pins, OBIT1-0 pins and TDM pin. Output ports become TDM mode when the TDM pin = "H". In TDM mode, the SDTI1 pin outputs serial data for 8channels and the SDTI2-4 pins output "L". Mode 0 1 2 3 4 5 6 7 Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDM pin TDM pin L L L L H H H H Master / Slave setting ODIF1 pin ODIF0 pin SDTO1-4 Format L L LSB justified L H Reserved H L MSB justified H H I2S Compatible L L Reserved L H Reserved H L TDM256 mode 24bit MSB justified H H TDM256 mode 24bit I2S Compatible Table 6. Output PORT Audio Interface Format 1 OBIT1 pin OBIT0 pin SDTO 1-4 L L H H L L H H L H L H L H L H 16bit 18bit 20bit 24bit 16bit 18bit 20bit 24bit Slave (CM2-0 = "HLL" or "HHL") * * Master (Not CM2-0 = "HLL"/"HHL") * * Slave (CM2-0 = "HLL" or "HHL") L Master (Not CM2-0 = "HLL"/"HHL") OBICK Frequency MSB justified, LSB I2S justified 32FSO 36FSO 64FSO 40FSO 48FSO OLRCK OBICK Input Input Output Output 64FSO TDM256 mode 24bit Input Input 256FSO TDM256 mode 24bit Output Output 256FSO H Table 7. Output PORT Audio Interface Format 2 (* The data length for 1channel is 24bit fixed in TDM mode. The OBIT1-0 pin settings are ignored. Connect these pins to VSS2-5.) MS1242-E-02 2014/03 - 27 - [AK4128A] OLRCK 0 1 8 9 10 11 12 13 14 15 16 17 20 21 22 23 29 30 31 0 1 8 9 10 11 12 13 14 15 16 17 20 21 22 23 29 30 31 0 1 2 OBICK(64fs) 15 14 11 10 9 8 2 1 0 15 14 11 10 9 8 2 1 0 17 16 15 14 11 10 9 8 2 1 0 17 16 15 14 11 10 9 8 2 1 0 19 18 17 16 15 14 11 10 9 8 2 1 0 19 18 17 16 15 14 11 10 9 8 2 1 0 11 10 9 8 2 1 0 23 22 21 20 19 18 17 16 15 14 11 10 9 8 2 1 0 SDTO(O) 15:MSB, 0:LSB SDTO(O) 17:MSB, 0:LSB SDTO(O) 19:MSB, 0:LSB SDTO(O) 23 22 21 20 19 18 17 16 15 14 23:MSB, 0:LSB Lch Data Rch Data Figure 25. Stereo Mode LSB justified Timing OLRCK 0 1 2 3 4 13 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2 3 4 13 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2 OBICK(64fs) SDTO(O) 15 14 13 12 2 1 0 15 14 13 12 2 1 0 15 14 17 16 15 14 4 3 2 1 0 17 16 19 18 17 16 6 5 4 3 2 1 0 19 18 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23 22 15:MSB, 0:LSB SDTO(O) 17 16 15 14 4 3 2 1 0 17:MSB, 0:LSB SDTO(O) 19 18 17 16 6 5 4 3 2 1 0 19:MSB, 0:LSB SDTO(O) 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 26. Stereo Mode MSB Justified Timing OLRCK 0 1 2 3 4 14 15 16 17 18 19 20 21 22 23 24 0 1 2 3 4 14 15 16 17 18 19 20 21 22 23 24 31 0 1 2 OBICK(64fs) SDTO(O) 15 14 13 12 2 1 0 15 14 13 12 2 1 0 15 17 16 15 14 4 3 2 1 0 17 19 18 17 16 6 5 4 3 2 1 0 19 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23 15:MSB, 0:LSB SDTO(O) 17 16 15 14 4 3 2 1 0 17:MSB, 0:LSB SDTO(O) 19 18 17 16 6 5 4 3 2 1 0 19:MSB, 0:LSB SDTO(O) 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0 23:MSB, 0:LSB Lch Data Rch Data 2 Figure 27. Stereo Mode I S Compatible Timing Note: SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4. MS1242-E-02 2014/03 - 28 - [AK4128A] 256 OBICK 1/ 32FSO OLRCK(O) OBICK(O) (256FSO) SDTO 1 (O) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 32OBICK 32OBICK 32OBICK 32OBICK 32OBICK 32OBICK Figure 28. TDM 256 mode 24bit MSB justified Timing at Master Mode. (SDTO2-4: "L" outputs) 256 OBICK min. 1/ 256FSO OLRCK(I) OBICK(I) (256FSO) SDTO 1 (O) 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 L1 R1 L2 R2 L3 R3 L4 R4 32 OBICK 32 OBICK 32 OBICK 32 OBICK 32 OBICK 32 OBICK 32 OBICK 32 OBICK Figure 29. TDM 256 mode 24bit MSB justified Timing at Slave Mode. (SDTO2-4: "L" outputs) 256 OBICK 1/32FSO OLRCK(O) OBICK (O: 256FSO) SDTO 1 (O) 23 0 23 0 23 L1 R1 32 OBICK 32 OBICK 0 23 0 23 0 23 0 23 L2 R2 L3 R3 32 OBICK 32 OBICK 32 OBICK 32 OBICK 2 Figure 30. TDM 256 mode 24bit I S Compatible Timing at Master Mode (SDTO2-4: "L" outputs) 256 OBICK min. 1/ 256FSO OLRCK(I) OBICK ( I: 256FSO) SDTO 1 (O) 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 L1 R1 L2 R2 L3 R3 L4 R4 32 OBICK 32 OBICK 32 OBICK 32 OBICK 32 OBICK 32 OBICK 32 OBICK 32 OBICK Figure 31. TDM 256 mode 24bit I2S Compatible Timing at Slave Mode (SDTO2-4: "L" outputs) MS1242-E-02 2014/03 - 29 - [AK4128A] 6/4channel Mode The AK4128A has 6-channel and 4-channel modes to reduce power supply current when not using all eight channels. When the PM2 and PM1 pins are set to "L/L", six channels (SDTI1 SDTO1, SDTI2 SDTO2 and SDTI3 SDTO3) are powered-up and the other two channels (SDTI4 SDTO4) are powered-down ("L" output). When the PM2 and PM1 pins are set to "L/H", four channels (SDTI1 SDTO1 and SDTI2 SDTO2) are powered-up and the other four channels (SDTI3 SDTO3 and SDTI4 SDTO4) are powered-down ("L" output). In 6-channel and 4-channel modes, the X'tal oscillator circuit and the MCKO output are powered-down and the XTO pin and MCKO pin output Hi-z. PM2 pin L L L L H H H H PM1 pin L L H H L L H H PDN pin L H L H L H L H Mode 6-channel mode 4-channel mode 8-channel mode Not available X'tal Oscillator XTI pin XTO pin MCKO pin Pull down to VSS2-5 (note) Hi-z Input Hi-z Pull down to VSS2-5 (note) Power-down Hi-z Input Power-down Pull down to VSS2-5 (note) Hi-z L Normal operation Input Output Normal operation Note: Pull down (460k typ.) to VSS2-5. Table 8. Channel Mode Setting Power-down Soft Mute Operation 1. Manual Mode The soft mute operation is performed in the digital domain of the SRC output. SRC1-4 soft mutes are controlled together by the SMUTE pin in parallel control mode (SPB pin = "L"). In serial control mode (SPB pin = "H"), setting of the SMUTE pin is ignored. SRC1 reflects SMUTE1 bit setting, SRC2 reflects SMUTE2 bit setting, SRC3 reflects SMUTE3 bit setting, and SRC4 reflects SMUTE4 bit setting. When the SMUTE pin goes "H" or SMUTE1-4 bits becomes "1", all the outputs data are attenuated by during 1024 OLRCK cycles (@ SMT1 pin = "L" and SMT0 pin = "L"). When the SMUTE pin goes "L" or SMUTE1-4 bits becomes "0"the mute is cancelled and the output attenuation gradually changes to 0dB during 1024 OLRCK cycles (@ SMT1 pin = "L" and SMT0 pin = "L"). If the soft mute is cancelled before attenuating to -, the attenuation is discontinued and returned to 0dB by the same cycles. The soft mute is effective for changing the signal source without stopping the signal transmission. Soft mute cycle is set by SMT1-0 pins. SMT1-0 pins must not be changed during soft mute transition. SMT1pin L L H H SMT0 pin Period FSO=48kHz FSO=96kHz L 1024/fso 21.3ms 10.7ms H 2048/fso 42.7ms 21.3ms L 4096/fso 85.3ms 42.7ms H 8192/fso 170.7ms 85.3ms Table 9. Soft Mute Cycle Setting (Parallel Mode) MS1242-E-02 FSO=192kHz 5.3ms 10.7ms 21.3ms 42.7ms 2014/03 - 30 - [AK4128A] SMUTE pin, SMUTE1-4 bit (1) 0dB (1) (2) Attenuation - All "0" code SDTO Note: SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4. (1) The soft mute cycle is selected by SMT1-0 pins. (Table 9) The output data is attenuated by during the soft mute cycle. (2) If the soft mute is cancelled before attenuating to , the attenuation is discontinued and returned to 0dB by the same clock cycles. Figure 32. Soft Mute Function (Manual Mode) 2. Semi-Auto Mode When power down of the AK4128A is released (PDN pin = "L" "H") with the SMSEMI pin= "H", the AK4128A enters semi-auto mode. In this mode, soft mute is cancelled automatically 4410/FSO after a rising edge of PDN (100ms @FSO=44.1kHz). The soft mute is ON after releasing power down if the SMUTE pin = "H". The SMSEMI pin must be set during the PDN pin = "L". PDN pin "L" Don't care SMUTE pin (1) 0dB Attenuation "L" (2) 4410/fso - SDTO All "0" code Note: SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4. (1) The output data is attenuated by during the soft mute cycle (Table 9) (2) When it is 0dB by a soft mute release after 4410/FSO, it is able to mute or release the mute by the soft mute cycle in Table 9. Figure 33. Soft Mute Function (Semi-Auto Mode) MS1242-E-02 2014/03 - 31 - [AK4128A] Dither The AK4128A includes a dither circuit. The dither circuit adds a dither signal after the lowest bit of all the output data set by the OBIT1-0 pins when the DITHER pin = "H", regardless of SRC and SRC bypass modes. If the output bit is 24bit length in SRC bypass mode, the output code does not change by the DITHER pin setting. De-emphasis Filter The AK4128A includes a digital de-emphasis filter (tc = 50/15s) by an IIR filter. This filter corresponds to three frequencies (32kHz, 44.1kHz and 48kHz). In parallel control mode (SPB pin = "L"), de-emphasis setting of SRC1-4 are controlled together by DEM1-0 pins. In serial control mode (PSB pin = "H"), the setting of DEM1-0 pins is ignored. SRC1 reflects the DEM[11:10] bits setting, SRC2 reflects the DEM[21:20] bits setting, SRC3 reflects the DEM[31:30] bits setting, and SRC4 reflects the DEM[41:40] bits setting. DEM11pin DEM10 pin Mode(SDTI1-4) L L 44.1kHz L H OFF H L 48kHz H H 32kHz Table 10. De-emphasis Filter Setting (Parallel Control Mode (SPB pin= "L")) DEM11bit DEM10 bit Mode(SDTI1) L L 44.1kHz L H OFF H L 48kHz H H 32kHz Table 11. De-emphasis Filter Setting for SDTI1 (Serial Control Mode (SPB pin = "H")) DEM21 bit DEM20 bit Mode(SDTI2) L L 44.1kHz L H OFF H L 48kHz H H 32kHz Table 12. De-emphasis Filter Setting for SDTI2 (Serial Control Mode (SPB pin= "H")) DEM31 bit DEM30 bit Mode(SDTI3) L L 44.1kHz L H OFF H L 48kHz H H 32kHz Table 13. De-emphasis Filter Setting for SDTI3 (Serial Control Mode (SPB pin = "H")) DEM41 bit DEM40 bit Mode(SDTI4) L L 44.1kHz L H OFF H L 48kHz H H 32kHz Table 14. De-emphasis Filter Setting for SDTI4 (Serial Control Mode (SPB pin = "H")) MS1242-E-02 2014/03 - 32 - [AK4128A] Regulator The AK4128A has an internal regulator which suppresses the voltage to 1.8V from DVDD1-4 voltage. The generated 1.8V power is used as power supply for internal circuit. When over-current is flowed to the regulator output, over-current detection circuit works. When over-voltage is flowed to the regulator output, over-voltage detection circuit works. The regulator block is powered-down and the AK4128A becomes reset state when over-current detection circuit or over-voltage detection circuit is operated. The AK4128A does not return to normal operation without a reset by the PDN pin when these detection circuits are worked. When over-current or over-voltage is detected, the PDN pin should be brought into "L" at once, and should be set to "H" again to recover normal operation. The UNLOCK pin indicate the internal status of the device, and outputs "L" in SRC normal operation, and outputs "H" when over-current or over-voltage are detected. System Reset Bringing the PDN pin = "L" sets the AK4128A power-down mode and initializes the digital filters. The AK4128A should be reset once by bringing the PDN pin = "L" upon power-up. When PDN pin = "L", the SDTO1-4 output is "L". It takes 23ms (max) for SDTO output enable after power-down state is released by a clock input. Until then, the SDTO1-4 outputs "L". The internal SRC circuit is powered-up on an edge of ILRCK1-4 after a power-up time period of the internal regulator. (SDTO is identified as SDTO1, SDTO2, TDTO3 and SDTO4. SDTI is identified as SDTI1, SDTI2, SDTI3 and SDTI4.) Case 1: System Reset with clock inputs External clocks (Input port) Don't care Input Clocks 1 Input Clocks 2 Don't care SDTI Don't care Input Data 1 Input Data 2 Don't care External clocks (Output port) Don't care Output Clocks 1 Output Clocks 2 Don't care PDN 23ms(max) (Internal state) Power-down SDTO4 "0" data SDTO3 "0" data SDTO2 "0" data SDTO1 "0" data (1) 23ms(max) Normal operation PD (1) Normal operation Power-down "0" data Normal data "0" data "0" data Normal data "0" data Normal data "0" data Normal data "0" data Normal data "0" data Normal data Normal data Normal data "0" data UNLOCK Figure 34. System Reset 1 MS1242-E-02 2014/03 - 33 - [AK4128A] Case 2: System Reset without clock inputs External clocks (Input port) (No Clock) SDTI External clocks (Output port) Input Clocks Don't care (Don't care) Input Data Don't care (Don't care) Output Clocks Don't care PDN 21ms(max) (Internal state) Power-down Internal Circuit Power-up Time ILRCK1-4 Input wait (2) Normal operation Power-down Normal data "0" data SDTO4 "0" data SDTO3 "0" data Normal data "0" data SDTO2 "0" data Normal data "0" data SDTO1 "0" data Normal data "0" data UNLOCK Figure 35. System Reset 2 Note 27. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be changed when the PDN pin= "L". Note 28. The UNLOCK pin outputs "H" when the PDN pin= "L". SRC data is output from SDTO1-4 pins, which corresponds to the each sampling frequency ratio detected SRC, after a rising edge "" of PDN if the internal regulator is in normal operation. In 8-channel mode, the UNLOCK pin outputs "L" when sampling frequency ratio detection is completed at all SRC's. The UNLOCK pin keeps outputting "H" if there is one SRC which does not finished sampling frequency ratio detection. Note 29. (1) is the total time of "Internal circuit power-up + FSO/FSI ratio detection + Clock detection + Internal circuit group delay". Note 30. (2) is the total time of "FSO/FSI ratio detection + Clock detection + Internal circuit group delay". MS1242-E-02 2014/03 - 34 - [AK4128A] Internal Reset Function for Clock Change Clock change timing is shown in Figure 36 and Figure 37. SDTO is identified as SDTO1, SDTO2, SDTO3 and SDTO4. When changing the clock, the AK4128A should be reset by the PDN pin in parallel control mode and it should be reset by the PDN pin or RSTN bit in serial control mode (Figure 36). SDTO means SDTO1-4 in this figure. External clocks (Input port or Output port) Clocks 1 Clocks 2 Don't care PDN pin max 23ms (Internal state) Normal operation Power-down SDTO Att.Level Normal operation Note 31 Normal data SMUTE (Note32, recommended) (3) Normal data 1024/FSO 1024/FSO 0dB -dB Note 31. The data on SDTO may cause a clicking noise. To prevent this, set "0" to the SDTI more than 1024/fs (GD) before the PDN pin changes to "L". It makes the data on SDTO remain as "0". Note 32. SMUTE can also remove the clicking noise (Note 31). Note 33. (3) is the total time of "Internal circuit power-up + FSO/FSI ratio detection + Internal circuit group delay". Figure 36. Clock Change Sequence in Parallel Control Mode (SPB pin = "L") External clocks (Input port or Output port) Clocks 1 Don't care Clocks 2 RSTN bit pin (Internal state) Normal operation SDTO Normal data Reset (Note 28) Note 34 (4) Normal operation Normal data 1024/FSO SMUTE (Note35,recommended) 1024/FSO Att.Level 0dB -dB Note 34. The data on SDTO may cause a clicking noise. To prevent this, set "0" to the SDTI from GD before the PDN pin changes to "L". It makes the data on SDTO remain as "0". Note 35. SMUTE can also remove the unknown data at Note 26 Note 36. The digital block except serial control interface and registers is powered-down. The internal oscillator and regulator are not powered-down. Note 37. (4) is the total time of "0.5/FSI+8/FSI(O)+156/FSO" or "1.5/FSI+8/FSI(O)+156/FSO". (FSI(O) is lower frequency between FSI and FSO). Figure 37. Clock Change Sequence in Serial Control Mode (SPB pin = "H") MS1242-E-02 2014/03 - 35 - [AK4128A] 1. When the frequency of ILRCKx (x=1, 2, 3, 4) at input port is changed without a reset by the PDN pin or RSTN bit. When the difference of internal oscillator (min. 59.4 MHz, typ. 73.5 MHz) clock number in one ILRCKx cycle between before an ILRCKx frequency change (FSO/FSI ratio is stabilized) and after the change is more than 100 for 8cycles, an internal reset is made automatically and sampling frequency ratio detection is executed again. SDTOx outputs "L" when the internal reset is made, and SRC data is output after "0.5/FSI+8/FSI(O)+156/FSO or 1.5/FSI+8/FSI(O)+156/FSO" (FSI(O) is lower frequency between FSI and FSO). If the difference of internal oscillator clock number in one ILRCKx cycle between before an ILRCKx frequency change and after the change is less than 100 or more than 100 but shorter than 8cycles, the internal reset is not executed. In both cases; when ILRCKx frequency is changed immediately without transition time or with transition time which is not long enough for an internal reset, it takes 5148/FSO (max. 643.5ms @FSO=8kHz) (Note 38)to output normal SRC data. Distorted data may be output until normal SRC output. When ILRCKx is stopped, an internal reset is executed automatically. It takes "0.5/FSI+8/FSI(O)+156/FSO or 1.5/FSI+8/FSI(O)+156/FSO" (FSI(O) is lower frequency between FSI and FSO) [s] to output normal SRC data after ILRCKx is input again. 2. When the frequency of OLRCK at output port is changed without a reset by the PDN pin or RSTN bit. When the difference of internal oscillator clock number in one OLRCK cycle between before an OLRCK frequency change (FSO/FSI ratio is stabilized) and after the change is more than 100 for 8cycles, an internal reset is made automatically and sampling frequency ratio detection is executed again. SDTOx (x=1, 2, 3, 4)outputs "L" when the internal reset is made, and SRC data is output after "0.5/FSI+8/FSI(O)+156/FSO or 1.5/FSI+8/FSI(O)+156/FSO" (FSI(O) is lower frequency between FSI and FSO). If the difference of internal oscillator clock number in one OLRCK cycle between before an OLRCK frequency change and after the change is less than 100 or more than 100 but shorter than 8cycles, the internal reset is not executed. It takes 5148/FSO (max. 643.5ms @FSO=8kHz) (Note 38) to output normal SRC data. Distorted data may be output until normal SRC output. When OLRCK is stopped, an internal reset is executed automatically. It takes "0.5/FSI+8/FSI(O)+156/FSO or 1.5/FSI+8/FSI(O)+156/FSO" (FSI(O) is lower frequency between FSI and FSO) [s] to output normal SRC data after ILRCKx is input again. Note 38. When FSO=8kHz and FSO/FSI ratio is changed from 1/6 to 1/5.99. It is 160.9ms when FSO=32kHz and FSO/fSI ratio is changed from 1/6 to 1/5.99. MS1242-E-02 2014/03 - 36 - [AK4128A] Internal Status Pin The UNLOCK pin indicates internal status of the device. This pin outputs "H" when the PDN pin = "L". SRC data is output from SDTO1-4 pins, which corresponds to the each sampling frequency ratio detected SRC, after a rising edge "" of PDN if the internal regulator is in normal operation. In 8-channel mode, the UNLOCK pin outputs "L" when sampling frequency ratio detection is completed at all SRC's (SRC1-4). The UNLOCK pin keeps outputting "H" if there is one SRC which does not finished sampling frequency ratio detection. In 6-channel mode, the UNLOCK pin outputs "L" when sampling frequency ratio detection is completed at SRC1-3. It keeps outputting "H" if there is one SRC which does not finish sampling frequency ratio detection. In 4-channel mode, the UNLOCK pin outputs "L" when sampling frequency ratio detection is completed at SRC1-2. It keeps outputting "H" if there is one SRC which does not finish sampling frequency ratio detection. When over-current/voltage is flowed at the internal regulator, the UNLCOK pin outputs "H". An OR'ed result of the flags between over-current/voltage detection at the internal regulator and SRC sampling frequency detection complete is output from this pin. Over-Current/Voltage Limit Flag ("L" Normal, "H" Over-Current/Voltage detect) SRC Sampling Frequency Ratio Complete Flag UNLOCK pin Figure 38. Internal Flags and UNLOCK pin Output In parallel control mode, if the AK4128A is set in SRC bypass mode by CM2-0 pins during the PDN pin = "L" and powered-up, the UNLOCK pin outputs "L" after the power-up time of the internal regulator (max. 1.4ms) from a rising edge "" of the PDN pin. In serial control mode, if BYPS bit is set to "1"while RSTN bit = "0", the UNLOCK pin immediately outputs "L" after the register writing. MS1242-E-02 2014/03 - 37 - [AK4128A] Serial Control Interface The AK4128A supports fast-mode I2C-bus system (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected to (DVDD1-4 + 0.3)V or less voltage. 1. Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4128A recognizes the START condition, the device interfaced to the bus waits of the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the master device. 1-1. Data validity The data on the SDA line must be stable during a HIGH period of the clock. The HIGH or LOW state of the data line can only be changed when the clock signal on the SCL line is LOW except for the START and the STOP condition. SCL SDA DATA LINE STABLE : DATA VALID CHANGE OF DATA ALLOWED Figure 39. Data Transfer 1-2. START and STOP condition A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from the START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences end by the STOP condition. S SCL SDA START CONDITION STOP CONDITION Figure 40. START and STOP conditions MS1242-E-02 2014/03 - 38 - [AK4128A] 1-3. ACKNOWLEDGE ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitter will release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the acknowledge clock pulse so that that it remains stable "L" during "H" period of this clock pulse. The AK4128A generates an acknowledge after each byte is received. In read mode, the slave, the AK4128A transmits eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue transmitting data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition. Clock pulse for acknowledge SCL FROM MASTER 1 8 9 DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER START CONDITION acknowledge Figure 41. Acknowledge on the I2C-bus 1-4. FIRST BYTE The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after a START condition. If the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down the SDA line. The first six bits of the slave address are fixed as "001001". The next (seventh) bit is CAD0 (device address bits). It is "0" when the CAD0 pin = "L", and "1" when the CAD pin = "H". This bit identifies the specific device on the bus. When the slave address is input, the matched device generates an acknowledge and executes a command. The eighth bit (R/W bit) of the first byte defines whether the master requests a write or read condition. A "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. 0 0 1 0 0 1 CAD0 R/W Figure 42. The First Byte MS1242-E-02 2014/03 - 39 - [AK4128A] 2. WRITE Operations Set R/W bit = "0" for the WRITE operation of the AK4128A. After receipt of a start condition and the first byte, the AK4128A generates an acknowledge, and awaits the second byte (register address). The second byte consists of the address for control registers of AK4128A. The format is MSB first, and first 6bits must be fixed to "0". 0 0 0 0 0 0 A1 A0 (*: Don't care) Figure 43. The Second Byte After receipt the second byte, the AK4128A generates an acknowledge, and awaits the third byte. Those data after the second byte contain control data. The format is MSB first, 8bits. D7 D6 D5 D4 D3 D2 D1 D0 Figure 44. Byte structure after the second byte The AK4128A is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4128A generates an acknowledge, and awaits the next data again. The master can transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 03H prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. S T A R T SDA Slave Address Register Address(n) Data(n) S T Data(n+x) O P Data(n+1) S P A C K A C K A C K A C K Figure 45. WRITE Operation MS1242-E-02 2014/03 - 40 - [AK4128A] 3. READ Operations Set R/W bit = "1" for the READ operation of the AK4128A. After transmission of the data, the master can read next address's data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 03H prior to generating a stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4128A supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 3-1. CURRENT ADDRESS READ The AK4128A contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address "n", the next CURRENT READ operation would access data from the address "n+1". After receipt of the slave address with R/W bit set to "1", the AK4128A generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge but generate the stop condition, the AK4128A discontinues transmission. S T A R T SDA Slave Address Data(n) Data(n+1) S Data(n+x) T O P Data(n+2) S P A C K A C K A C K A C K Figure 46. CURRENT ADDRESS READ 3-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start condition, slave address (R/W="0") and then the register address to read. After the register address's acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". Then the AK4128A generates an acknowledge, 1byte data and increments the internal address counter by one. If the master does not generate an acknowledge but generate the stop condition, the AK4128A discontinues transmission. S T A R T SDA Slave Address S T A R T Word Address(n) S Slave Address Data(n) S Data(n+x) T O P Data(n+1) S A C K P A C K A C K A C K A C K Figure 47. RANDOM READ MS1242-E-02 2014/03 - 41 - [AK4128A] Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Reset & Mute SMUTE4 SMUTE3 SMUTE2 SMUTE1 0 BYPS 0 RSTN 01H De-emphasis DEM41 DEM40 DEM31 DEM30 DEM21 DEM20 DEM11 DEM10 02H Input Audio Data Format 1 0 IDIF22 IDIF21 IDIF20 0 IDIF12 IDIF11 IDIF10 03H Input Audio Data Format 2 0 IDIF42 IDIF41 IDIF40 0 IDIF32 IDIF31 IDIF30 Note 39. All register values are initialized by the PDN pin = "L". Note 40. Writing to the address 00H ~ 03H are inhabited. The addresses defined as 0 must contain "0" data. BYPS bit and IDIF12-10, 22-20, 32-30, 42-40 bits should be written when RSTN bit = "0". Note 41. I2C access becomes valid after 1.4ms (max) from PDN pin "". Register Definitions Addr 00H Register Name Reset & Mute R/W Default D7 SMUTE4 R/W 0 D6 SMUTE3 R/W 0 D5 SMUTE2 R/W 0 D4 SMUTE1 R/W 0 D3 0 RD 0 D2 BYPS R/W 0 D1 0 RD 0 D0 RSTN R/W 1 RSTN: Digital Reset Control 0: Reset 1: Reset Release (default) When this bit is set to "0", some digital blocks of the AK4128A are powered-down. In this case SRC1-4 can not operate. Control register settings are not initialized because IC serial control interface and control register blocks are not powered-down. Control register writings are available. The internal oscillator for the clocks, the regulator and the reference voltage generation circuit are not powered-down. BYPS: Bypass Mode Control 0: SRC Mode (default) 1: SRC Bypass Mode Refer to Table 3. SMUTE1: SRC1 Soft Mute Control 0: Soft Mute Release (default) 1: Soft Mute In serial control mode (SPB pin= "H"), the SMUTE pin setting is ignored. SRC1 reflects the SMUTE1 bit setting. SMUTE2: SRC2 Soft Mute Control 0: Soft Mute Release (default) 1: Soft Mute In serial control mode (SPB pin= "H"), the SMUTE pin setting is ignored. SRC2 reflects the SMUTE2 bit setting. SMUTE3: SRC3 Soft Mute Control 0: Soft Mute Release (default) 1: Soft Mute In serial control mode (SPB pin= "H"), the SMUTE pin setting is ignored. SRC3 reflects the SMUTE3 bit setting. MS1242-E-02 2014/03 - 42 - [AK4128A] SMUTE4: SRC4 Soft Mute Control 0: Soft Mute Release (default) 1: Soft Mute In serial control mode (SPB pin= "H"), the SMUTE pin setting is ignored. SRC4 reflects the SMUTE4 bit setting. Addr 01H Register Name De-emphasis R/W Default D7 DEM41 R/W 0 D6 DEM40 R/W 1 D5 DEM31 R/W 0 D4 DEM30 R/W 1 D3 DEM21 R/W 0 D2 DEM20 R/W 1 D1 DEM11 R/W 0 D0 DEM10 R/W 1 DEM11/10: SRC1 De-emphasis Control Default: "01" De-emphasis=OFF DEM21/20: SRC2 De-emphasis Control Default: "01" De-emphasis=OFF DEM31/30: SRC3 De-emphasis Control Default: "01" De-emphasis=OFF DEM41/40: SRC4 De-emphasis Control Default: "01" De-emphasis=OFF In serial control mode (SPB pin= "H"), the setting of DEM1-0 pins is ignored. The DEM[11:10] bits setting is reflected to SRC1, the DEM[21:20] bits setting is reflected to SRC2, the DEM[31:30] bits setting is reflected to SRC3, and the DEM[41:40] bits setting is reflected to SRC4. Addr Register Name 02H Input Audio Data Format 1 D7 D6 D5 D4 D3 D2 D1 D0 0 IDIF22 IDIF21 IDIF20 0 IDIF12 IDIF11 IDIF10 R/W RD R/W R/W R/W RD R/W R/W R/W Default 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Addr Register Name 03H Input Audio Data Format 2 0 IDIF42 IDIF41 IDIF40 0 IDIF32 IDIF31 IDIF30 R/W RD R/W R/W R/W RD R/W R/W R/W Default 0 0 0 0 0 0 0 0 IDIF12/11/10: SRC1 Audio Data Interface Mode Select for Input Ports Default: "000" Mode 0 (Refer Table 2) IDIF22/21/20: SRC2 Audio Data Interface Mode Select for Input Ports Default: "000" Mode 0 (Refer Table 2) IDIF32/31/30: SRC3 Audio Data Interface Mode Select for Input Ports Default: "000" Mode 0 (Refer Table 2) IDIF42/41/40: SRC4 Audio Data Interface Mode Select for Input Ports Default: "000" Mode 0 (Refer Table 2) In serial control mode (SPB pin = "H"), the setting of IDIF2-0 pins is ignored. The IDIF[12:10] bits setting is reflected to SRC1, the IDIF[22:20] bits setting is reflected to SRC2, the IDIF[32:30] bits setting is reflected to SRC3, and the IDIF[42:40] bits setting is reflected to SRC4. MS1242-E-02 2014/03 - 43 - [AK4128A] SYSTEM DESIGN Figure 48 and Figure 49 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. Parallel Control Mode (SPB pin = "L"). Synchronous Mode (INAS pin = "L"). OMCLK/XTI Input = X'tal mode Input PORT: Slave mode, IBICK1 lock mode (64FSI), 24 bit MSB justified Output PORT: Slave mode, 24 bit MSB justified Dither = OFF, DEM=OFF, PM2/1 pin= "H/L" (8ch mode) C1= 0.1F C2=10F C3=1F 30% 3.3V + C2 C1 C C + C2 C3 FSI 64FSI VSS1 VD18 AVDD SPB SDA SCL 55 54 53 52 51 50 49 MCKO TST3 56 TST0 57 CAD0 58 DVDD4 59 TST1 60 VSS5 + 61 TST2 62 SMSEMI 63 ILRCK2 C1 64 1 IBICK2 XTO 48 2 IMCLK XTI/OMCLK 47 FSO 3 ILRCK1 OLRCK 46 4 IBICK1 OBICK 45 5 DVDD1 DVDD3 44 64FSO C1 DSP1 C1 6 VSS2 VSS4 43 7 SDTI4 DSP2 SDTO4 42 8 SDTI1 SDTO1 41 Top View 9 SDTI2 SDTO2 40 10 SDTI3 SDTO3 39 11 IDIF0 ODIF0 38 12 IDIF1 ODIF1 37 13 IDIF2 CM0 36 14 ILRCK3 CM1 35 UNLOCK DVDD2 VSS3 SMUTE DITHER PDN SMT0 SMT1 DEM0 DEM1 PM1 OBIT0 OBIT1 PM2 TDM 33 INAS CM2 34 16 ILRCK4 IBICK4 15 IBICK3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C1 + C2 uP Notes: - All digital input pins should be not left floating. - VSS1 -5 must be connected to the same ground plane. - DVDD1-4 pins must be connected to the same power supply. - Connect a 1F ( 30%; including temperature characteristics) capacitor between the VD18 pin and DVSS. When this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin. - Refer to Table 5 for the equivalent series resistance R1 and capacitance C values of the X'tal oscillator. Figure 48. Typical Connection Diagram (Parallel Control Mode) MS1242-E-02 2014/03 - 44 - [AK4128A] Serial Control Mode (SPB pin = "H"). Asynchronous Inputs Mode (INAS pin = "H"). OMCLK/XTI Input= 256FSO, X'tal Input PORT: Slave mode, IBICK1~4 lock mode (64FSI) Input Audio Interface Format can be set by registers. Output PORT: Master mode, 24 bit MSB justified. Dither = OFF, De-emphasis filter can be set by registers. PM2/1 pin= "H/L" (8ch mode) C1= 0.1F C2=10F C3=1F 30% 3.3V + C2 C1 C + C C2 C3 FSI DSP1 64FSI 57 56 55 TST3 VD18 AVDD SPB SDA SCL TST2 SMSEMI 54 53 52 51 50 TST0 58 49 MCKO 59 CAD0 60 DVDD4 61 TST1 62 VSS1 ILRCK2 DSP2 63 VSS5 C1 + 64 1 IBICK2 XTO 48 2 IMCLK XTI/OMCLK 47 FSO 3 ILRCK1 OLRCK 46 4 IBICK1 OBICK 45 5 DVDD1 DVDD3 44 64FSO C1 C1 6 VSS2 VSS4 43 DSP5 7 SDTI4 SDTO4 42 8 SDTI1 SDTO1 41 Top View 9 SDTI2 SDTO2 40 10 SDTI3 SDTO3 39 11 IDIF0 ODIF0 38 12 IDIF1 ODIF1 37 13 IDIF2 CM0 36 14 ILRCK3 CM1 35 DSP3 15 IBICK3 CM2 34 16 ILRCK4 TDM 33 IBICK4 INAS UNLOCK DVDD2 VSS3 SMUTE DITHER PDN SMT0 SMT1 DEM0 DEM1 PM1 OBIT0 OBIT1 PM2 DSP4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C1 + C2 uP Notes: - All digital input pins should be not left floating. - VSS1 -5 must be connected to the same ground plane. - DVDD1-4 pins must be connected to the same power supply. - Connect a 1F ( 30%; including temperature characteristics) capacitor between the VD18 pin and DVSS. When this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin. - Refer to Table 5 for the equivalent series resistance R1 and capacitance C values of the X'tal oscillator. Figure 49. Typical Connection Diagram (Serial Control Mode) MS1242-E-02 2014/03 - 45 - [AK4128A] 1. Grounding and Power Supply Decoupling The AK4128A requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD1-4 are supplied separately, the power up sequence is not critical. VSS1-5 must be connected to the same ground plane. Decoupling capacitors should be as near to the AK4128A as possible, with the small value ceramic capacitor being the nearest. 2. Jitter Tolerance Figure 50 shows the jitter tolerance to ILRCK1-4 and IBICK. The jitter quantity is defined by the jitter frequency and the jitter amplitude shown in Figure 50. When the jitter amplitude is 0.02Uipp or less, the AK4128A operates normally regardless of the jitter frequency. A Figure 50. Jitter Tolerance (1) Normal Operation (2) There is a possibility that the output data is lost. Note Y axis is the jitter amplitude of ILRCK1-4 just before THD+N degradation starts. 1UI (Unit Interval) is one cycle of IBICK. When FSI = 48kHz, 1[UIpp]=1/48kHz=20.8s MS1242-E-02 2014/03 - 46 - [AK4128A] 3. Digital Filter Response Example Table 15 shows the examples of digital filter response performed by the AK4128A. Ratio FSO/FSI [kHz] 4.000 1.000 0.919 0.725 0.667 0.544 0.500 0.500 0.459 0.363 0.333 0.250 0.250 0.230 0.167 0.181 0.167 0.181 192/48.0 48.0/48.0 44.1/48.0 32.0/44.1 32.0/48.0 48.0/88.2 48.0/96.0 44.1/88.2 44.1/96.0 32.0/88.2 32.0/96.0 48.0/192.0 44.1/176.4 44.1/192.0 32.0/192.0 32.0/176.4 8/48.0 8/44.1 Stopband Attenuation [dB] 22.000 26.000 121.2 22.000 26.000 121.2 20.000 24.100 121.4 14.088 17.487 115.3 13.688 17.488 116.9 19.250 26.232 114.6 20.900 27.000 100.2 19.202 24.806 100.2 18.700 25.000 103.3 12.863 18.665 102.0 12.500 18.900 103.6 17.600 30.200 104.0 16.170 27.746 104.0 15.860 28.240 103.3 11.200 19.600 73.2 10.278 17.987 73.2 2.800 4.900 73.2 2.5695 4.4968 73.2 Table 15. Digital Filter Example Passband [kHz] Stopband [kHz] Gain [dB] 0.01@ 20k 0.01@ 20k 0.01@ 20k 0.01@ 14.5k 0.19@ 14.5k 0.03@ 20k 0.01@ 20k 0.08@ 20k 0.23@ 20k 0.75@ 14.5k 1.07@ 14.5k 0.18@ 20k 1.34@ 20k 1.40@ 20k 2.97@ 14.5k 7.88@ 14.5k 2.97@ 3.625k 7.88@ 3.625k 2 4. I C bus Connection SCL and SDA pins should be connected to DVDD1-4 through the resistor based on I2C standard. As there is a protection between each pin and DVDD1-4, the pulled up voltage must be DVDD1-4 or lower (Figure 51). +3.3V DVDD1-4 AK4128A SDA pin VSS2-5 Figure 51. SDA pin output MS1242-E-02 2014/03 - 47 - [AK4128A] PACKAGE 64pin LQFP(Unit: mm) 12.00.3 Max 1.85 10.0 1.40 0.00~0.25 33 32 48 12.00.3 49 64 17 16 1 0.5 0.20.1 0.10~0.25 0.10 M 0~10 0.50.2 0.10 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy, Halogen (bromine and chlorine) free Cu Solder (Pb free) plate MS1242-E-02 2014/03 - 48 - [AK4128A] MARKING (AK4128AEQ) AKM AK4128AEQ XXXXXXX 1 XXXXXXX: Date code identifier MARKING (AK4128AVQ) AKM AK4128AVQ XXXXXXX 1 XXXXXXX: Date code identifier MS1242-E-02 2014/03 - 49 - [AK4128A] REVISION HISTORY Date (Y/M/D) 10/09/13 11/06/02 Revision 00 01 14/03/06 02 Reason First Edition Description Addition Error Correction Page Contents 4 Compatibility with AK4126 (2) Pins: No. 63-pin was added. SWITCHING CHARACTERISTICS Output PORT LRCK for TDM256 Mode (OLRCK) "H"/"L" time (Master Mode): 1/8FSO 1/32FSO Synchronous and Asynchronous Modes Setting Table 1: FSI pin INAS pin Audio Interface Format for Output PORT Figure 28 and 30 were changed. PACKAGE Package dimensions were changed. 13 20 29 Description Change 48 MS1242-E-02 2014/03 - 50 - [AK4128A] IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ("Product"), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. MS1242-E-02 2014/03 - 51 -