EVAL-ADM3050EEBZ - ANALOG DEVICES

5.7 kV rms, Signal Isolated,

Basic CAN FD Transceiver

Data Sheet

ADM3050E

Rev. B Document Feedback

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FEATURES

5.7 kV rms signal isolated CAN FD transceiver

1.7 V to 5.5 V supply and logic side levels

4.5 V to 5.5 V supply on bus side

ISO 11898-2:2016-compliant CAN FD

Data rates up to 12 Mbps for CAN FD

Low maximum loop propagation delay: 150 ns

Extended common-mode range: ±25 V

Bus fault protection (CANH, CANL): ±40 V

Passes EN 55022, Class B by 6 dB

Safety and regulatory approvals

VDE certificate of conformity, VDE V 0884-10 (pending)

UL: 5700 V rms for 1-minute duration per UL 1577 (pending)

CSA component acceptance 5A at 5.7 kV rms

IEC 60950, IEC 61010 (pending)

High common-mode transient immunity: >75 kV/µs

Industrial operating temperature range: −40°C to +125°C

APPLICATIONS

CANOpen, DeviceNet, and other CAN bus implementations

Industrial automation

Process control and building control

Transport and infrastructure

FUNCTIONAL BLOCK DIAGRAM

DOMINANT

TIMEOUT

CAN

TRANSCEIVER

CANH

CANL

RXD

TXD

GND

ADM3050E

THERMAL

SHUTDOWN

DIGITAL ISOLATOR

DD1

DD2

14971-001

Figure 1.

GENERAL DESCRIPTION

The ADM3050E is a 5.7 kV rms isolated controller area network

(CAN) physical layer transceiver with a high performance, basic

feature set. The ADM3050E fully meets the CAN flexible data

rate (CAN FD) ISO 11898-2:2016 requirements and is further

capable of supporting data rates as high as 12 Mbps.

The device employs Analog Devices, Inc., iCoupler® technology

to combine a 2-channel isolator and a CAN transceiver into a

single small outline integrated circuit (SOIC) surface-mount

package. The ADM3050E is a fully isolated solution for CAN and

CAN FD applications. The ADM3050E provides isolation

between the CAN controller and physical layer bus. Safety and

regulatory approvals (pending) for a 5.7 kV rms withstand voltage,

an 849 VPEAK working voltage, and a 12.8 kV surge test, ensure

that the ADM3050E meets application isolation requirements.

Low loop propagation delays and the extended common-mode

range of ±25 V support robust communication on longer bus

cables. Dominant timeout functionality protects against bus

lock up in a fault condition, and current limiting and thermal

shutdown features protect against output short circuits. The

CAN bus input and output pins are protected to ±40 V against

accidental connection to a +24 V bus supply. The device is fully

specified over the −40°C to +125°C industrial temperature

range.

ADM3050E Data Sheet

Rev. B | Page 2 of 19

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 5

Timing Diagrams .......................................................................... 5

Insulation and Safety Related Specifications ............................ 6

Package Characteristics ............................................................... 6

Regulatory Information ............................................................... 6

DIN V VDE V 0884-10 (VDE V 0884-10) Insulation

Characteristics (Pending) ............................................................ 7

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Operational Truth Table ............................................................ 11

Typical Performance Characteristics ........................................... 12

Test Circuits ..................................................................................... 14

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 16

CAN Transceiver Operation ..................................................... 16

Signal Isolation ........................................................................... 16

Integrated and Certified IEC Electromagnetic Compatibility

(EMC) Solution .......................................................................... 16

±40 V Miswire Protection ......................................................... 16

Dominant Timeout .................................................................... 16

Fail-Safe Features ........................................................................ 16

Thermal Shutdown .................................................................... 16

Applications Information .............................................................. 17

Radiated Emissions and PCB Layout ...................................... 17

PCB Layout ................................................................................. 17

Thermal Analysis ....................................................................... 17

Insulation Lifetime ..................................................................... 17

Surface Tracking ......................................................................... 17

Insulation Wear Out .................................................................. 17

Calculation and Use of Parameters Example .......................... 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

9/2019—Rev. A to Rev. B

Added 8-Lead SOIC_IC Package ..................................... Universal

Changes to Table 3 ............................................................................ 6

Added ADM3050EBRWZ Section ................................................. 6

Changes to ADM3050EBRWZ Section ......................................... 6

Added ADM3050EBRIZ Section and Table 6; Renumbered

Sequentially ....................................................................................... 7

Changes to Table 7 ............................................................................ 7

Added Table 8 .................................................................................... 8

Change to Figure 4 Caption ............................................................ 9

Added Figure 5; Renumbered Sequentially .................................. 9

Changes to Table 10 ........................................................................ 10

Added Figure 7 ................................................................................ 11

Added Figure 26 ............................................................................. 17

Updated Outline Dimensions ....................................................... 19

Changes to Ordering Guide .......................................................... 19

12/2018—Rev. 0 to Rev. A

Change to Features Section .............................................................. 1

Change to Falling Edge Loop Propagation Delay (TXD to RXD)

Parameter and Rising Edge Loop Propagation Delay (TXD to

RXD) Parameter, Table 2 .................................................................. 5

10/2018—Revision 0: Initial Version

Data Sheet ADM3050E

Rev. B | Page 3 of 19

SPECIFICATIONS

All voltages are relative to their respective ground, 1.7 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise

noted. Typical specifications are at VDD1 = VDD2 = 5 V and TA = 25°C, unless otherwise noted.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

SUPPLY CURRENT

Bus Side IDD2

Recessive State 5.3 7 mA TXD high, load resistance (RL) = 60 Ω

Dominant State 63 75 mA Limited by transmit dominant timeout

(tDT), see the Theory of Operation

section, RL = 60 Ω

73 mA Limited by tDT, RL = 60 Ω, 4.75 V ≤ VDD2 ≤

5.25 V

70% Dominant/30% Recessive Worst case, see the Theory of Operation

section, RL = 60 Ω

1 Mbps 45 58 mA

5 Mbps 49 60 mA

12 Mbps 58 65 mA

Logic Side

Coupler Current IDD1 5.5 mA TXD high, low, or switching

DRIVER

Differential Outputs See Figure 20

Recessive State Voltage TXD high, RL, and common-mode filter

capacitor (CF) open

CANH, CANL VCANL, VCANH 2.0 3.0 V

Differential Output VOD −500 +50 mV

Dominant State Voltage

TXD low, C

open

CANH VCANH 2.75 4.5 V 50 Ω ≤ RL ≤ 65 Ω

CANL VCANL 0.5 2.0 V 50 Ω ≤ RL ≤ 65 Ω

Differential Output VOD 1.5 3.0 V 50 Ω ≤ RL ≤ 65 Ω

1.4 3.3 V 45 Ω ≤ RL ≤ 70

1.5 5.0 V RL = 2240 Ω

Output Symmetry (VDD2 − VCANH to VCANL) VSYM −0.55 +0.55 V RL = 60 Ω, CF = 4.7 nF

Short-Circuit Current |ISC| RL open

Absolute

CANH 115 mA VCANH = −3 V

CANL 115 mA VCANL = 18 V

Steady State

CANH 115 mA VCANH = −24 V

CANL 115 mA VCANL = 24 V

Logic Input TXD

Input Voltage

High VIH 0.65 × VDD1 V

Low VIL 0.35 × VDD1 V

Complementary Metal-Oxide

Semiconductor (CMOS) Logic Input

Currents

|IIH|, |IIL| 10 µA Input high or low

RECEIVER

Differential Inputs

Differential Input Voltage Range VID See Figure 21, RXD capacitance (CRXD)

open, −25 V < VCANL, VCANH < +25 V

Recessive −1.0 +0.5 V

Dominant 0.9 5.0 V

Input Voltage Hysteresis VHYS 150 mV

ADM3050E Data Sheet

Rev. B | Page 4 of 19

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Unpowered Input Leakage Current |IIN (OFF)| 10 µA VCANH, VCANL = 5 V, VDD2 = 0 V

Input Resistance

CANH, CANL RINH, RINL 6 25 kΩ

Differential RDIFF 20 100 kΩ

Input Resistance Matching

−0.03

+0.03

= 2 × (R

INH

− R

INL

)/(R

INH

+ R

INL

)

CANH, CANL Input Capacitance CINH, CINL 35 pF

Differential Input Capacitance CDIFF 12 pF

Logic Output (RXD)

Output Voltage

Low VOL 0.2 0.4 V Output impedance (IOUT) = 2 mA

High VOH VDD1 − 0.2 V IOUT = −2 mA

Short-Circuit Current IOS 7 85 mA Output voltage (VOUT) = GND1 or VDD1

COMMON-MODE TRANSIENT IMMUNITY1 Common-mode voltage (VCM) ≥ 1 kV,

transient magnitude ≥ 800 V

Input High, Recessive |CMH| 75 100 kV/µs Input voltage (VIN) = VDD1 (TXD) or

CANH/CANL recessive

Input Low, Dominant |CML| 75 100 kV/µs VIN = 0 V (TXD) or CANH/CANL dominant

1 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining CANH/CANL recessive or RXD ≥ VDD1 − 0.2 V. |CML| is the maximum

common-mode voltage slew rate that can be sustained while maintaining CANH/CANL dominant or RXD ≤ 0.4 V. The common-mode voltage slew rates apply to both

rising and falling common-mode voltage edges.

Data Sheet ADM3050E

Rev. B | Page 5 of 19

TIMING SPECIFICATIONS

All voltages are relative to their respective ground, 1.7 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise

noted. Typical specifications are at VDD1 = VDD2 = 5 V and TA = 25°C, unless otherwise noted.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DRIVER See Figure 2 and Figure 20,

tBIT_TXD = 200 ns, RL = 60 Ω,

CL = 100 pF

Maximum Data Rate 12 Mbps

Propagation Delay from TXD to Bus (Recessive to Dominant) tTXD_DOM 35 60 ns

Propagation Delay from TXD to Bus (Dominant to Recessive) tTXD_REC 45 70 ns

Transmit Dominant Timeout tDT 1175 4000 µs TXD low, see Figure 3

RECEIVER See Figure 2 and Figure 22,

tBIT_TXD = 200 ns, RL = 60 Ω,

CL = 100 pF, CRXD = 15 pF

Falling Edge Loop Propagation Delay (TXD to RXD) tLOOP_FALL 150 ns

Rising Edge Loop Propagation Delay (TXD to RXD) tLOOP_RISE 150 ns

Loop Delay Symmetry (Minimum Recessive Bit Width) tBIT_RXD

2 Mbps 450 550 ns tBIT_TXD = 500 ns

5 Mbps 160 220 ns tBIT_TXD = 200 ns

8 Mbps 85 140 ns tBIT_TXD = 125 ns

12 Mbps 50 91.6 ns tBIT_TXD = 83.3 ns

TIMING DIAGRAMS

TXD 0.3V

DD1

0.3V

DD1

0.3V

DD1

0.7V

DD1

0.5V 0.9V

DD1

5 ×

BIT_TXD

TXD_REC

TXD_DOM

BIT_BUS

BIT_RXD

BIT_TXD

LOOP_FALL

LOOP_RISE

RXD

14971-002

0.7V

DD1

Figure 2. Transceiver Timing Diagram

TXD

tDT

14971-103

Figure 3. Dominant Timeout, tDT

ADM3050E Data Sheet

Rev. B | Page 6 of 19

INSULATION AND SAFETY RELATED SPECIFICATIONS

For additional information, see www.analog.com/icouplersafety.

Table 3.

Parameter Symbol

Value

Unit Test Conditions/Comments ADM3050EBRWZ ADM3050EBRIZ

Rated Dielectric Insulation

Voltage

5700 5700 V rms 1-minute duration

Minimum External Air Gap

(Clearance)

L (I01) 7.8 8.3 mm

min

Measured from input terminals to output

terminals, shortest distance through air

Minimum External Tracking

(Creepage)

L (I02) 7.8 8.3 mm

min

Measured from input terminals to output

terminals, shortest distance path along body

Minimum Clearance in the

Plane of the Printed

Circuit Board (PCB)

Clearance

L (PCB)

8.3

min

Measured from input terminals to output

terminals, shortest distance through air, line of

sight, in the PCB mounting plane

Minimum Internal Gap

(Internal Clearance)

25.5 25.5 µm

min

Insulation distance through insulation

Tracking Resistance

(Comparative Tracking

Index)

CTI >600 >600 V DIN IEC 112/VDE 0303 Part 1

Material Group I I Material group (DIN VDE 0110, 1/89, Table 1)

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Resistance (Input to Output)1 RI-O 1013 Ω

Capacitance (Input to Output)1 CI-O 1.1 pF f = 1 MHz

Input Capacitance2 CI 4.0 pF

1 The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.

2 Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

ADM3050EBRWZ

See Table 11 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross isolation waveforms

and insulation levels. The ADM3050EBRWZ is pending approval or approved by the organizations listed in Table 5.

Table 5.

UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)

UL1577 Component

Recognition Program1

Approved under CSA Component Acceptance

Notice 5A

DIN V VDE V 0884-10

(VDE V 0884-10):2006-122

Certified under CQC11-

471543-2012

Single Protection, 5700 V rms

Isolation Voltage

CSA 60950-1-07+A1+A2 and

IEC 60950-1, second edition, +A1+A2:

Reinforced insulation,

849 VPEAK, VIOTM = 8 kVPEAK

GB4943.1-2011

Basic insulation at 780 V rms (1103 VPEAK)

Basic insulation at 780 V

rms (1103 VPEAK)

Reinforced insulation at 390 V rms (552 VPEAK) Reinforced insulation at

390 V rms (552 VPEAK)

IEC 60601-1 Edition 3.1:

Basic insulation (1 MOPP), 490 V rms (686 VPEAK)

Reinforced insulation (2 MOPP), 238 V rms

(325 VPEAK)

CSA 61010-1-12 and IEC 61010-1 third edition:

Data Sheet ADM3050E

Rev. B | Page 7 of 19

UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)

Basic insulation at: 300 V rms mains, 780 V

secondary (1103 VPEAK)

Reinforced insulation at: 300 V rms mains, 390

V secondary (552 VPEAK)

File E214100 File 205078 File 2471900-4880-0001 File (pending)

1 In accordance with UL 1577, each ADM3050E is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec.

2 In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥ 1592 VPEAK for 1 sec (partial discharge detection limit = 5 pC).

The * marking branded on the component designates DIN V VDE V 0884-10 approval.

ADM3050EBRIZ

See Table 11 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross isolation waveforms

and insulation levels. The ADM3050EBRIZ is pending approval or approved by the organizations listed in Table 6.

Table 6.

UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending)

UL1577 Component

Recognition Program1

Approved under CSA Component

Acceptance Notice 5A

DIN V VDE V 0884-10

(VDE V 0884-10):2006-122

Certified under CQC11-

471543-2012

Single Protection, 5700 V rms

Isolation Voltage

CSA 60950-1-07+A1+A2 and

IEC 60950-1, second edition, +A1+A2:

Reinforced insulation,

849 VPEAK, VIOTM = 8 kVPEAK

GB4943.1-2011

Basic insulation at 780 V rms (1103 VPEAK)

Basic insulation at 780 V rms

(1103 VPEAK)

Reinforced insulation at 390 V rms (552 VPEAK) Reinforced insulation at

390 V rms (552 VPEAK)

IEC 60601-1 Edition 3.1:

Basic insulation (1 MOPP), 490 V rms

(686 VPEAK)

Reinforced insulation (2 MOPP), 238 V rms

(325 VPEAK)

CSA 61010-1-12 and IEC 61010-1 third edition:

Basic insulation at: 300 V rms mains, 780 V

secondary (1103 VPEAK)

Reinforced insulation at: 300 V rms mains,

390 V secondary (552 VPEAK)

File E214100 File 205078 File 2471900-4880-0001 File (pending)

1 In accordance with UL 1577, each ADM3050E is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec.

2 In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥ 1592 VPEAK for 1 sec (partial discharge detection limit = 5 pC).

The * marking branded on the component designates DIN V VDE V 0884-10 approval.

DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING)

These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance

of the safety data.

Table 7. ADM3050EBRWZ VDE Characteristics

Description Test Conditions/Comments Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV

For Rated Mains Voltage ≤ 300 V rms I to IV

For Rated Mains Voltage ≤ 600 V rms

I to IV

Climatic Classification

40/125/21

Pollution Degree per DIN VDE 0110, Table 1 2

Maximum Working Insulation Voltage

Reinforced VIORM 849 VPEAK

ADM3050E Data Sheet

Rev. B | Page 8 of 19

Description Test Conditions/Comments Symbol Characteristic Unit

Basic, DC Working Voltage See the Absolute Maximum Ratings section and Table 11

for the maximum continuous working voltage for ac bipolar,

ac unipolar, and dc voltages, basic and reinforced insulation,

and 50 year lifetime to 1% failure

VIORM(DC) 1500 VDC

Input to Output Test Voltage, Method B1

IORM

× 1.875 = V

pd (m)

, 100% production test, t

ini

= t

= 1 sec,

partial discharge < 5 pC

pd (m)

1592

PEAK

Input to Output Test Voltage, Method A Vpd (m)

After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,

partial discharge < 5 pC

1274 VPEAK

After Input and/or Safety Test Subgroup 2

and Subgroup 3

VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,

partial discharge < 5 pC

1019 VPEAK

Highest Allowable Overvoltage VIOTM 8000 VPEAK

Impulse 1.2 µs rise time, 50 µs, 50% fall time in air to the preferred

sequence

VIMPULSE 8000 VPEAK

Surge Isolation Voltage VPEAK

Basic

PEAK

= 12.8 kV, 1.2 µs rise time, 50 µs, and 50% fall time

IOSM

12000

PEAK

Reinforced VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, and 50% fall time VIOSM 8000 VPEAK

Safety Limiting Values Maximum value allowed in the event of a failure (see

Figure 4)

Maximum Junction Temperature TS 150 °C

Total Power Dissipation at 25°C PS 2.08 W

Insulation Resistance at T

Test voltage = 500 V

>10

Ω

Table 8. ADM3050EBRIZ VDE Characteristics

Description Test Conditions/Comments Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms I to IV

For Rated Mains Voltage ≤ 300 V rms I to IV

For Rated Mains Voltage ≤ 600 V rms I to IV

Climatic Classification

40/125/21

Pollution Degree per DIN VDE 0110, Table 1 2

Maximum Working Insulation Voltage

Reinforced VIORM 849 VPEAK

Basic, DC Working Voltage See the Absolute Maximum Ratings section and Table 11

for the maximum continuous working voltage for ac bipolar,

ac unipolar, and dc voltages, basic and reinforced insulation,

and 50 year lifetime to 1% failure

VIORM(DC) 1500 VDC

Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec,

partial discharge < 5 pC

Vpd (m) 1592 VPEAK

Input to Output Test Voltage, Method A Vpd (m)

After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,

partial discharge < 5 pC

1274 VPEAK

After Input and/or Safety Test Subgroup 2

and Subgroup 3

VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,

partial discharge < 5 pC

1019 VPEAK

Highest Allowable Overvoltage VIOTM 8000 VPEAK

Impulse 1.2 µs rise time, 50 µs, 50% fall time in air to the preferred

sequence

VIMPULSE 8000 VPEAK

Surge Isolation Voltage VPEAK

Basic VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, and 50% fall time VIOSM 12000 VPEAK

Reinforced VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, and 50% fall time VIOSM 8000 VPEAK

Safety Limiting Values Maximum value allowed in the event of a failure (see

Figure 4)

Maximum Junction Temperature TS 150 °C

Total Power Dissipation at 25°C PS 1.28 W

Insulation Resistance at TS Test voltage = 500 V RS >109 Ω

Data Sheet ADM3050E

Rev. B | Page 9 of 19

0.5

1.0

1.5

2.0

2.5

050 100 150 200

SAFE LIMITING POWER (W)

AMBIENT TEMPERATURE ( °C)

14971-104

Figure 4. ADM3050EBRWZ Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 (See the Thermal

Resistance Section for Additional Information)

0.2

0.4

0.8

1.2

0.6

1.0

1.4

050 100 150 200

SAFE LIMITING POWER (W)

AMBI E NT TE M P E RATURE (°C)

14971-205

Figure 5. ADM3050EBRIZ Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 (See the Thermal

Resistance Section for Additional Information)

ADM3050E Data Sheet

Rev. B | Page 10 of 19

ABSOLUTE MAXIMUM RATINGS

Pin voltages with respect to GND1/GND2 are on same side,

unless otherwise noted.

Table 9.

Parameter Rating

VDD1/VDD2 −0.5 V to +6 V

Logic Side Input and Output: TXD, RXD −0.5 V to VDD1 + 0.5 V

CANH, CANL −40 V to +40 V

Operating Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C

Maximum Junction Temperature (TJ) 150°C

Electrostatic Discharge (ESD),

IEC 61000-4-2, CANH/CANL

Across Isolation Barrier with Respect

to GND1

±8 kV

Contact Discharge with Respect to

GND2

±8 kV typical

Air Discharge with Respect to GND2 ±15 kV

Human Body Model (HBM), All Pins,

1.5 kΩ, 100 pF

±4 kV

Moisture Sensitivity Level (MSL) 3

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to PCB design and

operating environment. Careful attention to PCB thermal

design is required.

Table 10. Thermal Resistance

Package Type1 θJA Unit

RW-16 60 °C/W

RI-8-1

°C/W

1 The thermocouple is located at the center of the package underside, and the

test was conducted on a 4-layer board with thin traces. See the Thermal

Analysis section for the thermal model definitions.

ESD CAUTION

Table 11. Maximum Continuous Working Voltage1

Parameter Insulation Rating (20-Year Lifetime)2 VDE 0884-11 Lifetime Conditions Fulfilled

AC Voltage

Bipolar Waveform

Basic Insulation

849 V

PEAK

Lifetime limited by insulation lifetime per VDE-0884-11

Reinforced Insulation 707 VPEAK Lifetime limited by insulation lifetime per VDE-0884-11

Unipolar Waveform

Basic Insulation 1697 VPEAK Lifetime limited by insulation lifetime per VDE-0884-11

Reinforced Insulation 1275 VPEAK Lifetime limited by package creepage per IEC 60664-1

DC Voltage

Basic Insulation 1560 VPEAK Lifetime limited by package creepage per IEC 60664-1

Reinforced Insulation 780 VPEAK Lifetime limited by package creepage per IEC 60664-1

1 The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for

more details.

2 Insulation capability without regard to creepage limitations. Working voltage may be limited by the PCB creepage when considering rms voltages for components

soldered to a PCB (assumes Material Group I up to 1250 V rms), or by the SOIC_W package creepage of 7.8 mm, when considering rms voltages for Material Group II.

Data Sheet ADM3050E

Rev. B | Page 11 of 19

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADM3050E

TOP VIEW

(Not to Scale)

VDD1

GND1

TXD

RXD

GND1

VDD2

GND2

CANL

CANH

GND2

NOTES

1. NC = NO CONNECT. NO INTERNAL CONNECTION TO IC.

14971-004

Figure 6. 16-Lead SOIC_W Pin Configuration

DD1 1

TXD

RXD

GND

DD2

CANH

CANL

GND

14971-207

ADM3050E

(Not to Scale)

TOP VIEW

Figure 7. 8-Lead SOIC_IC Pin Configuration

Table 12. Pin Function Descriptions

Pin No.

Mnemonic Description

16-Lead

SOIC_W

8-Lead

SOIC_IC

1 1 VDD1 Power Supply, Logic Side, 1.7 V to 5.5 V. This pin requires a 0.1 μF decoupling capacitor.

2, 7, 8 4 GND1 Ground, Logic Side.

3 3 RXD Receiver Output Data.

4, 5, 11, 14 N/A1 NC No Connect. No internal connection to IC.

6 2 TXD Driver Input Data.

9, 10, 15 5 GND2 Ground, Bus Side.

12 6 CANL CAN Low Input and Output.

13 7 CANH CAN High Input and Output.

16 8 VDD2 Power Supply, Bus Side, 4.5 V to 5.5 V. This pin requires a 0.1 μF decoupling capacitor.

1 N/A means not applicable.

OPERATIONAL TRUTH TABLE

Table 13. Truth Table

VDD1 V

DD2 TXD Mode RXD CANH/CANL

On On Low Normal Low Dominant (limited by tDT)

On On High Normal High per bus Recessive and set by bus

Off On Don’t care Normal Indeterminate Recessive and set by bus

On Off Don’t care Transceiver off High High-Z

ADM3050E Data Sheet

Rev. B | Page 12 of 19

TYPICAL PERFORMANCE CHARACTERISTICS

1.5

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

0 1 23 4 5 6 78 9 10 11 12 13 14 15

SUPPLY CURREN T, I

DD1

(mA)

DATA RATE (Mb p s)

DD1

= 1.8V

DD1

= 2.5V

DD1

= 3.3V

DD1

= 5.0V

14971-106

Figure 8. Supply Current (IDD1) vs. Data Rate

01 2 345678 9 10 11 12 13 14 15

SUPPLY CURREN T, I

DD2

(mA)

DATA RATE (Mb p s)

DD2

= 4.5V

DD2

= 5V

DD2

= 5.5V

14971-107

Figure 9. Supply Current (IDD2) vs. Data Rate

100

110

120

130

140

150

160

170

180

–55 –35 –15 525 45 65 85 105 125

RECEIVER INPUT HYSTERESIS (mV)

TEMPERATURE (°C)

14971-108

Figure 10. Receiver Input Hysteresis vs. Temperature

–55 –35 –15 525 45 65 85 105 125

TXD_DOM

(n s)

TEMPERATURE (°C)

DD1

= 5.0V

DD1

= 3.3V

DD1

= 2.5V

DD1

= 1.8V

14971-109

Figure 11. tTXD_DOM vs. Temperature

–55 –35 –15 525 45 65 85 105 125

TEMPERAT URE ( °C)

TXD_REC

(n s)

DD1

= 1.8V

DD1

= 2.5V

DD1

= 3.3V

DD1

= 5.0V

14971-110

Figure 12. tTXD_REC vs. Temperature

–55 –35 –15 525 45 65 85 105 125

TEMPERAT URE ( °C)

LOOP_RISE

(n s)

100

105

110

115

120

125

130

135

DD1

= 1.8V

DD1

= 2.5V

DD1

= 3.3V

DD1

= 5.0V

14971-111

Figure 13. tLOOP_RISE vs. Temperature

Data Sheet ADM3050E

Rev. B | Page 13 of 19

–55 –35 –15 525 45 65 85 105 125

TEMPERAT URE ( °C)

LOOP_FALL (ns)

100

105

110

115

120

125

VDD1 = 1. 8V

VDD1 = 2. 5V

VDD1 = 3. 3V

VDD1 = 5. 0V

14971-112

Figure 14. tLOOP_FALL vs. Temperature

2.14

2.16

2.18

2.20

2.22

2.24

2.26

2.28

2.30

2.32

2.34

–55 –5 45 95

DIFFERENTIAL OUTPUT VOLTAGE (V)

TEMPERATURE (°C)

14971-113

Figure 15. Differential Output Voltage vs. Temperature, RL = 60 Ω

1.5

1.7

1.9

2.1

2.3

2.5

2.7

4.5 4.7 4.9 5.1 5.3 5.5

DIFFERENTIAL OUTPUT VOLTAGE (V)

SUPPLY VOLTAGE, V

DD2

(V)

14971-114

Figure 16. Differential Output Voltage vs. Supply Voltage (VDD2), RL = 60 Ω

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

–55 –35 –15 525 45 65 85 105 125

SUPPLY CURREN T, I

DD1

(mA)

TEMPERAT URE ( °C)

14971-115

DD1

= 1.8V

DD1

= 2.5V

DD1

= 3.3V

DD1

= 5.0V

Figure 17. Supply Current (IDD1) vs. Temperature

–55 –35 –15 525 45 65 85 105 125

TEMPERAT URE ( °C)

32.5

33.0

33.5

34.0

34.5

35.0

35.5

36.0

SUPPLY CURREN T, IDD2 ( mA)

14971-116

Figure 18. Supply Current (IDD2) vs. Temperature

2100

2200

2300

2400

2500

2600

2700

2800

2900

–55 –35 –15 525 45 65 85 105 125

DOMINANT TIMEOUT,

(µs)

TEMPERAT URE ( °C)

14971-117

Figure 19. Dominant Timeout (tDT) vs. Temperature

ADM3050E Data Sheet

Rev. B | Page 14 of 19

TEST CIRCUITS

TXD

GND1GND2

VOD VCANH

VCANL

14971-005

Figure 20. Driver Voltage Measurement

CRXD

RXD

GND1GND2

CANH

CANL

VID

14971-006

Figure 21. Receiver Voltage Measurement

RXD

GND

TXD CANH

CANL

NOTES

1. 1% T OL E RANCE FOR ALL RE S IST ORS AND CAP ACITORS.

14971-007

Figure 22. Switching Characteristics Measurements

DIFF

GND

CANH

CANL

14971-008

Figure 23. RDIFF and CDIFF Measured in Recessive State, Bus Disconnected

INH

INL

GND

CANH

CANL

14971-009

Figure 24. Input Resistance (RINx) and Input Capacitance (CINx) Measured in

Recessive State, Bus Disconnected

Data Sheet ADM3050E

Rev. B | Page 15 of 19

TERMINOLOGY

IDD1

IDD1 is the current drawn by the VDD1 pin.

IDD2

IDD2 is the current drawn by the VDD1 pin.

VOD and VID

VOD and VID are the differential voltages from the transmitter or

at the receiver on the CANH and CANL pins.

tTXD_DOM

tTXD_DOM is the propagation delay from a low signal on TXD to

transition the bus to a dominant state.

tTXD_REC

tTXD_REC is the propagation delay from a high signal on TXD to

transition the bus to a recessive state.

tLOOP_FALL

tLOOP_FALL is the propagation delay of a low signal on the TXD

pin to the bus dominant. tON_LOOP transitions low on the RXD pin.

tLOOP_RISE

tLOOP_RISE is the propagation delay of a high signal on TXD to the

bus recessive. tOFF_LOOP transitions high on the RXD pin.

tBIT_TXD

tBIT_TXD is the bit time at the TXD pin as transmitted by the CAN

controller. See Figure 2 for level definitions.

tBIT_BUS

tBIT_BUS is the bit time as transmitted by the transceiver to the

bus. When compared with a given tBIT_TXD, a measure of bit

symmetry from the TXD digital isolation channel and CAN

transceiver can be determined. See Figure 2 for level definitions.

tBIT_RXD

tBIT_RXD is the bit time on the RXD output pin, which can be

compared with tBIT_TXD for a round trip measure of pulse width

distortion through the TXD digital isolation channel, the CAN

transceiver, and back through the RXD isolation channel.

ADM3050E Data Sheet

Rev. B | Page 16 of 19

THEORY OF OPERATION

CAN TRANSCEIVER OPERATION

The ADM3050E facilitates communication between a CAN

controller and the CAN bus. The CAN controller and the

ADM3050E communicate with standard 1.8 V, 2.5 V, 3.3 V

or 5.0 V CMOS levels. The internal transceiver translates the

CMOS levels to and from the CAN bus.

The CAN bus has two states: dominant and recessive. The

recessive state is present on the bus when the differential voltage

between CANH and CANL is less than 0.5 V. In the recessive

state, both the CANH pin and CANL pin are set to high

impedance and are loosely biased to a single-ended voltage of

2.5 V. A dominant state is present on the bus when the differential

voltage between CANH and CANL is greater than 1.5 V. The

transceiver transmits a dominant state by driving the single-

ended voltage of the CANH line to 3.5 V and the CANL pin to

1.5 V. The recessive and dominant states correspond to CMOS

high and CMOS low, respectively, on the RXD pin and TXD pin.

A dominant state from another node overwrites a recessive state

on the bus. A CAN frame can be set for higher priority by using

a longer string of dominant bits to gain control of the CAN bus

during the arbitration phase. While transmitting, a CAN

transceiver also reads back the state of the bus. When a CAN

controller receives a dominant state while transmitting a

recessive state during arbitration, the CAN controller surrenders

the bus to the node still transmitting the dominant state. The

node that gains control during the arbitration phase reads back

only its own transmission. This interaction between recessive

and dominant states allows competing nodes to negotiate for

control of the bus while avoiding contention between nodes.

Industrial applications can have long cable runs. These long

runs may have differences in local earth potential. Different

sources may also power nodes. The ADM3050E transceiver

has a ±25 V common-mode range (CMR) that exceeds the

ISO11898-2 requirement and further increases the tolerance

to ground variation.

See the AN-1123 Application Note for additional information

on CAN.

SIGNAL ISOLATION

The ADM3050E device provides galvanic signal isolation

implemented on the logic side of the interface. The RXD and

TXD channels are isolated using a low propagation delay on/off

keying (OOK) architecture with iCoupler digital isolation

technology.

The low propagation delay isolation, quick transceiver

conversion speeds, and integrated form factor are critical for

longer cable lengths, higher data speeds, and reducing the total

solution board space. The ADM3050E isolated transceiver

reduces solution board space while increasing data transfer

rates over discrete optocoupler and transceiver solutions.

INTEGRATED AND CERTIFIED IEC ELECTROMAGNETIC

COMPATIBILITY (EMC) SOLUTION

Typically, designers must add protections against harsh operating

environments while also making the product as small as possible.

To re du ce the board space and the design efforts needed to meet

system level ESD standards, the ADM3050E isolated transceiver

has brought robust protection circuitry on-chip for the CANH

and CANL lines.

±40 V MISWIRE PROTECTION

High voltage miswire events commonly occur when the system

power supply is connected directly to the CANH and the CANL

bus lines during assembly. Supplies may also be shorted by

accidental damage to the field bus cables while the system is

operating. Accounting for inductive kick and switching effects,

the ADM3050E isolated transceiver CAN bus lines are protected

against these miswire or shorting events in systems with up to

nominal 24 V supplies. The CANH and CANL signal lines can

withstand a continuous supply short with respect to GND2 or

between the CAN bus lines without damage. This level of protection

applies when the device is either powered or unpowered.

DOMINANT TIMEOUT

The ADM3050E features a dominant timeout (tDT in Figure 3). A

TXD line shorted to ground, or malfunctioning CAN controller

are examples of how a single node can indefinitely prevent further

bus traffic. tDT limits how long the dominant state can transmit

to the CAN bus by the transceiver. The TXD function restores

when the line is presented with a logic low.

The tDT minimum also inherently creates a minimum data rate.

Under normal operation, the CAN protocol allows five consecutive

bits of the same polarity before stuffing a bit of opposite polarity

into the transmitting bit sequence. When an error is detected,

the CAN controller purposely violates the bit stuffing rules by

producing six consecutive dominant bits. At any given data rate,

the CAN controller must transmit as many as 11 consecutive

dominant bits to effectively limit the ADM3050E minimum

data rate to 9600 bps.

FAIL-SAFE FEATURES

In cases where the TXD input pin is allowed to float to prevent bus

traffic interruption, the TXD input channel has an internal pull-up

to the VDD1 pin. The pull-up holds the transceiver in the recessive state.

THERMAL SHUTDOWN

The integrated transceiver is designed with thermal shutdown

circuitry to protect the device from excessive power dissipation

during fault conditions. Shorting the driver outputs to a low

impedance source can result in high driver currents. The thermal

sensing circuitry detects the increase in die temperature under this

condition and disables the driver outputs. The circuitry disables the

driver outputs when the die temperature reaches 175°C. The

drivers are enabled after the die has cooled.

Data Sheet ADM3050E

Rev. B | Page 17 of 19

APPLICATIONS INFORMATION

RADIATED EMISSIONS AND PCB LAYOUT

The ADM3050E isolated CAN transceivers with integrated

dc-to-dc converters pass EN 55022, Class B by 6 dB on a simple

2-layer PCB design. Neither stitching capacitance nor high

voltage surface mount (SMT) safety capacitors are required to

meet this emission level.

PCB LAYOUT

The ADM3050E isolated CAN transceiver requires no external

interface circuitry for the logic interfaces. Power supply

bypassing is required at the logic input supply (VDD1), and the

shared CAN transceiver and digital isolator supply pin (VDD2).

The recommended bypass capacitor value is 0.1 μF. Note that

low effective series resistance (ESR) bypass capacitors are

required and must be placed as close to the chip pads as possible.

The total lead length between both ends of the capacitor and

the input power supply pin must not exceed 10 mm. Bypassing

between Pin 1, Pin 7, and Pin 8 and between Pin 16, Pin 10, and

Pin 9 must also be considered, unless the ground pair on each

package side is connected in close proximity to the package.

In applications involving high common-mode transients,

minimize board coupling across the isolation barrier. Design

the board layout so that any coupling that does occur equally

affects all pins on a given component side. Failure to ensure this

equal coupling can cause voltage differentials between pins

exceeding the absolute maximum ratings of the device, thereby

leading to latch-up or permanent damage.

ADM3050E

DD1

GND

TXD

RXD

GND

DD2

GND

CANL

CANH

GND

0.1µF0.1µF

14971-010

Figure 25. Recommended 16-Lead SOIC_W PCB Layout

0.1µF0.1µF

TXD

RXD

GND

DD1

DD2 8

CANH

CANL

GND

14971-226

ADM3050E

Figure 26. Recommended 8-Lead SOIC_IC PCB Layout

THERMAL ANALYSIS

The ADM3050E device consists of three internal die attached to a

split lead frame. For the purposes of thermal analysis, the die are

treated as a thermal unit, with the highest junction temperature

reflected in the θJA value from Table 10. The θJA value is based on

measurements taken with the devices mounted on a JEDEC

standard, 4-layer board with fine width traces and still air.

INSULATION LIFETIME

All insulation structures eventually break down when subjected

to voltage stress over a sufficiently long period of time. The rate

of insulation degradation is dependent on the characteristics of

the voltage waveform applied across the insulation as well as on

the materials and material interfaces.

The two types of insulation degradation of primary interest are

breakdown along surfaces exposed to the air and insulation

wear out. Surface breakdown is the phenomenon of surface

tracking and is the primary determinant of surface creepage

requirements in system level standards. Insulation wear out

is the phenomenon where charge injection or displacement

currents inside the insulation material cause long-term

insulation degradation.

SURFACE TRACKING

Surface tracking is addressed in electrical safety standards by

setting a minimum surface creepage based on the working

voltage, the environmental conditions, and the properties of the

insulation material. Safety agencies perform characterization

testing on the surface insulation of components, allowing the

components to be categorized in different material groups.

Lower material group ratings are more resistant to surface

tracking and can therefore provide adequate lifetime with

smaller creepage. The minimum creepage for a given working

voltage and material group is in each system level standard and

is based on the total rms voltage across the isolation, pollution

degree, and material group.

The material group and creepage for the ADM3050E isolator is

listed in Table 3 for both the 8-lead, increased creepage SOIC

package option and the 16-lead, wide body SOIC package option.

INSULATION WEAR OUT

The lifetime of insulation caused by wear out is determined by

its thickness, material properties, and the voltage stress applied.

It is important to verify that the product lifetime is adequate at

the application working voltage. The working voltage supported

by an isolator for wear out may not be the same as the working

voltage supported for tracking. The working voltage applicable

to tracking is specified in most standards.

Testing and modeling have shown that the primary driver of

long-term degradation is displacement current in the polyimide

insulation causing incremental damage. The stress on the

insulation can be broken down into broad categories, such as

dc stress, which causes very little wear out because there is no

displacement current, and an ac component time varying

voltage stress, which causes wear out.

ADM3050E Data Sheet

Rev. B | Page 18 of 19

The ratings in certification documents are usually based on

60 Hz sinusoidal stress because this reflects isolation from line

voltage. Many practical applications have combinations of 60 Hz

ac and dc across the barrier, as shown in Equation 1. Because

only the ac portion of the stress causes wear out, the equation

can be rearranged to solve for the ac rms voltage, as shown in

Equation 2. For insulation wear out with the polyimide materials

used in these products, the ac rms voltage determines the

product lifetime.

RMS AC RMS DC

VV V= +

(1)

DCRMSRMSAC VVV −=

(2)

where:

VRMS is the total rms working voltage.

VAC RMS is the time varying portion of the working voltage.

VDC is the dc offset of the working voltage.

CALCULATION AND USE OF PARAMETERS

EXAMPLE

The following example frequently arises in power conversion

applications. Assume that the line voltage on one side of the

isolation is 240 V ac rms and a 400 VDC bus voltage is present on

the other side of the isolation barrier. The isolator material is

polyimide. To establish the critical voltages in determining the

creepage, clearance, and lifetime of a device, see Figure 27 and

the following equations.

ISOLATION VOLTAGE

TIME

AC RMS

RMS

PEAK

14971-011

Figure 27. Critical Voltage Example

The working voltage across the barrier from Equation 1 is

RMS AC RMS DC

VV V= +

400240 +=

RMS

VRMS = 466 V

This VRMS value is the working voltage used together with the

material group and pollution degree when looking up the creepage

required by a system standard.

To determine if the lifetime is adequate, obtain the time varying

portion of the working voltage. To obtain the ac rms voltage,

use Equation 2.

DCRMSRMSAC

VVV −=

400466 −=

RMSAC

VAC RMS = 240 V rms

In this case, the ac rms voltage is simply the line voltage of

240 V rms. This calculation is more relevant when the waveform is

not sinusoidal. The value is compared to the limits for working

voltage in Table 11 for the expected lifetime, which is less than a

60 Hz sine wave, and is well within the limit for a 50-year

service life.

Note that the dc working voltage limit is set by the creepage of

the package as specified in IEC 60664-1. This value can differ

for specific system level standards.

Data Sheet ADM3050E

Rev. B | Page 19 of 19

OUTLINE DIMENSIONS

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

10.50 (0.4134)

10.10 (0.3976)

0.30 (0.0118)

0.10 (0.0039)

2.65 (0.1043)

2.35 (0.0925)

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

0.75(0.0295)

0.25(0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

OPLANARITY

0.10 0.33 (0.0130)

0.20 (0.0079)

0.51 (0.0201)

0.31 (0.0122)

SEATING

PLANE

8°

0°

16 9

1.27 (0.0500)

BSC

03-27-2007-B

Figure 28. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

09-17-2014-B

SEATING

PLANE

COPLANARITY

0.10

1.27 BSC

1.04

BSC

6.05

5.85

5.65

7.60

7.50

7.40

2.65

2.50

2.35

0.75

0.58

0.40

0.30

0.20

0.10

2.45

2.35

2.25

10.51

10.31

10.11

0.51

0.41

0.31

PIN 1

MARK

8°

0°

0.33

0.27

0.20

0.75

0.50

0.25

45°

Figure 29. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]

Wide Body

(RI-8-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description

Package

Option

ADM3050EBRWZ −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16

ADM3050EBRWZ-RL −40°C to +125°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16

ADM3050EBRIZ −40°C to +125°C 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-8-1

ADM3050EBRIZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] RI-8-1

EVAL-ADM3050EEBZ Evaluation Board

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D14971-0-9/19(B)