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Hitachi Single-Chip Microcomputer H8/3437 Series H8/3437 HD6473437, HD6433437 H8/3436 HD6433436 H8/3434 HD6473434, HD6433434 H8/3437W HD6433437W H8/3436W HD6433436W H8/3434W HD6433434W H8/3437F-ZTATTM HD64F3437 H8/3437SF-ZTATTM HD64F3437S H8/3434F-ZTATTM HD64F3434 Hardware Manual ADE-602-077F Rev. 7.0 3/14/03 Hitachi, Ltd. The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Preface The H8/3437 Series is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an H8/300 CPU featuring a 32-bit internal architecture as its core. On-chip peripheral functions include ROM, RAM, four kinds of timers, a serial communication interface (SCI), host interface (HIF), keyboard controller, D/A converter, A/D converter, and I/O ports, enabling the H8/3437 Series to be used as a microcontroller for embedding in high-speed control systems. Flash memory (F-ZTATTM*), PROM (ZTAT(R)*), and mask ROM are available as on-chip ROM, enabling users to respond quickly and flexibly to changing application specifications and the demands of the transition from initial to full-fledged volume production. Note: * F-ZTAT is a trademark of Hitachi, Ltd. ZTAT is a registered trademark of Hitachi, Ltd. Intended Readership: This manual is intended for users undertaking the design of an application system using a H8/3437 Series microcomputer. Readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers. Purpose: The purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the H8/3437 Series. Details of execution instructions can be found in the H8/300 Series Programming Manual, which should be read in conjunction with the present manual. Using this Manual: * For an overall understanding of the H8/3437 Series' functions Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system control functions, peripheral functions, and electrical characteristics. * For a detailed understanding of CPU functions Refer to the separate publication H8/300 Series Programming Manual. * For a detailed description of a register's function when the register name is known. Information on addresses, bit contents, and initialization is summarized in Appendix B, Internal I/O Register. Note on bit notation: Bits are shown in high-to-low order from left to right. Related Material: The latest information is available at our Web Site. Please make sure that you have the most up-to-date information available. http://www.hitachisemiconductor.com/ User's Manuals on the H8/3437 Series: Manual Title ADE No. H8/3437 Series Hardware Manual This manual H8/300 Series Programming Manual ADE-602-025 Users manuals for development tools: Manual Title ADE No. C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual ADE-702-247 Simulator Debugger Users Manual ADE-702-282 Hitachi Debugging Interface Users Manual ADE-702-161 Hitachi Embedded Workshop Users Manual ADE-702-201 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging Interface Users Manual ADE-702-231 Notes on S-Mask Model (Single-Power-Supply Specification) There are two versions of the H8/3437F with on-chip flash memory: a dual-power-supply version and a single-power-supply (S-mask) version. Points to be noted when using the H8/3437F singlepower-supply S-mask model are given below. 1. Notes on Voltage Application 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device. The flash memory programming power supply for the S-mask model (single-power-supply specification) is VCC. The programming power supply for the dual-power-supply model is the FVPP pin (12 V), but the single-power-supply model (S-mask model) does not have an FVPP pin. Also, in boot mode, 12 V has to be applied to the MD1 pin in the dual-power-supply model, but 12 V application is not necessary in the single-power-supply model (S-mask model). The maximum rating of the MD1 pin is VCC +0.3 V. Applying a voltage in excess of the maximum rating will permanently damage the device. Do not select the HN28F101 programmer setting for the S-mask model (single-power-supply specification). If this setting is made by mistake, 12 V will be applied to the STBY pin, possibly causing permanent damage to the device. When using a PROM programmer to program the on-chip flash memory in the S-mask model (single-power-supply specification), use a PROM programmer that supports Hitachi microcomputer devices with 64-kbyte on-chip flash memory. Also, only use the specified socket adapter. Using the wrong PROM programmer or socket adapter may damage the device. The following PROM programmers support the S-mask model (single-power-supply specification). DATA I/O: UNISITE, 2900, 3900, etc. Minato: 1892, 1891, 1890, etc. 2. Product Type Names and Markings Table 1 shows examples of product type names and markings for the H8/3437F (dual-powersupply specification) and H8/3437SF (single-power-supply specification), and the differences in flash memory programming power supply. Table 1 Differences in H8/3437F and H8/3437F S-Mask Model Markings Product type name Dual-Power-Supply Model: H8/3437F Single-Power-Supply Model: H8/3437F S-Mask Model HD64F3437F16/TF16 HD64F3437SF16/TF16 Sample markings H8/3437 8M3 HD 64F3437F16 H8/3437 8M3 HD S 64F3437F16 JAPAN JAPAN "S" is printed above the type name Flash memory programming power supply VPP power supply VCC power supply (12.0 V 0.6 V) (5.0 V 10%) 3. Differences in S-Mask Model Table 2 shows the differences between the H8/3437F (dual-power-supply specification) and H8/3437SF (single-power-supply specification). Table 2 Differences between H8/3437F and H8/3437F S-Mask Model Item Program/ erase voltage Dual-Power-Supply Model: H8/3437F Single-Power-Supply Model: H8/3437F S-Mask Model 12 V must be applied from off-chip 12 V application not required VPP (12.0 V 0.6 V) VCC single-power-supply programming VCC (5.0 V 10%) FV PP (FWE) pin function Dual function as FV PP power supply and STBY function No programming control pin Programming modes * * Writer mode On-board Boot mode User programming mode (See section 21 for the use of these modes) Writer mode (See section 21 for the use of these modes) Operating * modes allowing * on-board * programming Boot mode User programming mode On-board programming unit 1-byte-unit programming 32-byte-unit programming Programming with PROM programmer Select Hitachi stand-alone flash memory HN28F101 setting Special programming mode setting required. Use of PROM programmer that supports Hitachi microcomputer device types with 64-kbyte on-chip flash memory. (128-byte-unit fast page programming) Boot mode setting method Reset release after MD 1 = FVPP /STBY = 12 V application Pin Setting level MD1 MD0 0 0 P92 P91 P90 1 1 1 Reset release after above pin settings User program mode setting method FV PP = 12 V application Control bits set by software Item Dual-Power-Supply Model: H8/3437F Single-Power-Supply Model: H8/3437F S-Mask Model Programming mode timing RES RES MD0 MD1, MD1 tMDS tMDS MD1 12 V Min 0 s 12 V VPP P92, P91, P90 tMDS: 4tcyc (min.) tMDS: 4tcyc (min.) Prewrite processing Required before erasing Not required Programming processing Block corresponding to programming address must be set in EBR1/EBR2 registers before programming Settings at left not required EBR register configuration EBR1, EBR2 EBR2 Memory map (block configuration) SB0 (128 bytes) EB0 (1 kbyte) SB1 (128 bytes) EB1 (1 kbyte) SB2 (128 bytes) SB3 (128 bytes) EB2 (1 kbyte) SB4 (512 bytes) EB3 (1 kbyte) SB5 (1 kbyte) SB6 (1 kbyte) SB7 (1 kbyte) LB0 (4 kbytes) 60 kbytes EB4 (24 kbytes) 60 kbytes LB1(8 kbytes) LB2 (8 kbytes) LB3 (8 kbytes) LB4 (8 kbytes) EB5 (16 kbytes) LB5 (8 kbytes) EB6 (12 kbytes) LB6 (12 kbytes) LB7 (2 kbytes) Reset during operation Drive RES pin low for at least 10 system clock cycles (10o). (RES pulse width tRESW = min. 10tcyc) EB7 (2 kbytes) Drive RES pin low for at least 20 system clock cycles (20o). (RES pulse width tRESW = min. 20tcyc) Item MDCR Dual-Power-Supply Model: H8/3437F 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- Single-Power-Supply Model: H8/3437F S-Mask Model 1 0 MDS1 MDS0 7 EXPE 6 -- 5 -- 4 -- 3 -- 2 -- 1 0 MDS1 MDS0 Bit 7: Expanded mode enable (EXPE) WSCR 7 6 5 RAMS RAM0 CKDBL 4 -- 3 2 1 0 WMS1WMS0 WC1 WC0 7 -- 6 -- 5 4 3 2 1 0 CKDBL FLSHE WMS1 WMS0 WC1 WC0 Bit 4: Flash memory control register enable (FLSHE) FLMCR1 7 VPP 6 -- 5 -- 4 -- 3 EV 2 PV 1 E 0 P 7 6 FWE SWE 5 -- 4 -- 3 EV 2 PV 1 E 0 P Bit 7: Flash write enable (FWE) Bit 6: Software write enable (SWE) FLMCR2 -- 7 FLER 6 -- 5 -- 4 -- 3 -- 2 -- 1 ESU 0 PSU Bit 7: Flash memory error (FLER) Bit 1: Erase setup (ESU) Bit 0: Program setup (PSU) EBR1 EBR2 7 LB7 6 LB6 5 LB5 4 LB4 3 LB3 2 LB2 1 LB1 0 LB0 7 SB7 6 SB6 5 SB5 4 SB4 3 SB3 2 SB2 1 SB1 0 SB0 -- This address is not used. 7 EB7 6 EB6 5 EB5 4 EB4 3 EB3 2 EB2 1 EB1 0 EB0 Erase block register (EBR2) EB0 (1 kbyte): H'0000 to H'03FF EB1 (1 kbyte): H'0400 to H'07FF EB2 (1 kbyte): H'0800 to H'0BFF EB3 (1 kbyte): H'0C00 to H'0FFF EB4 (28 kbytes): H'1000 to H'7FFF EB5 (16 kbytes): H'8000 to H'BFFF EB6 (12 kbytes): H'C000 to H'EF7F EB7 (2 kbytes): H'EF00 to H'F77F Details concerning flash memory See section 20, ROM (Dual-PowerSupply 60-Kbyte Flash Memory Version) See section 21, ROM (Single-PowerSupply 60-Kbyte Flash Memory Version) Electrical characteristics See section 23, Electrical Characteristics See section 23, Electrical Characteristics Registers See Appendix B, Registers See Appendix B, Registers Table 3 shows differences in the development environments of the H8/3437F (dual-power-supply specification) and H8/3437SF (single-power-supply specification). Table 3 H8/3437F and H8/3437F S-Mask Model Development Environments Dual-Power-Supply Model: H8/3437F Item E6000 Emulator Hitachi emulator unit HS3008EPI60H User cable Single-Power-Supply Model: H8/3437F S-Mask Model Hitachi HS3008EPI60H Hitachi HS3437ECH61H Hitachi HS3437ECH61H Programming socket adapter Hitachi HS3434ESHF1H Minato DATA I/O Adapter board Hitachi HS0008EASF1H/2H Hitachi HS0008EASF3H Windows interface software Hitachi HS6400FWIW2SF Hitachi HS6400FWIW2SF Table 4 shows differences in the pin settings of the H8/3437F (dual-power-supply specification) and H8/3437SF (single-power-supply specification). Table 4 H8/3437F and H8/3437F S-Mask Model Pin Settings Item Dual-Power-Supply Model: H8/3437F Boot mode Single-Power-Supply Model: H8/3437F S-Mask Model H8/3437SF H8/3437F VCC (5 V) 12 V 8 FVPP/STBY 5 MD1 VSS (GND) User programming mode H8/3437F 12 V 8 FVPP/STBY 23 24 25 P92 P91 P90 5 6 MD1 MD0 There are no state transitions due to pin states. Transitions should be implemented by means of register settings by software. List of Items Revised or Added for This Version Section Page Notes on S-Mask Model (Single-Power-Supply Specification) 1.1 Overview 3 Item Description (see Manual for details) Table 1 Differences in H8/3437F and H8/3437F SMask Model Markings Single-Power-Supply Model: H8/3437F Smask model sample marking amended Table 1.1 Features "Other features" specifications amended. 4 H8/3434F-ZTAT ROM amended in "Series Lineup" specifications. Notes 1 and 3 deleted 1.3.1 Pin Arrangement 6 6.2.2 Oscillator Circuit (H8/3437SF) 95 to 99 12.3.2 Asynchronous Mode 264 Section 13 I 2C Bus Interface [Option] 283 13.4 Application Notes 311 to 315 Figure 1.2 Pin Arrangement (FP-100B, TFP-100B, Top View) Rotated 90 degrees to the left, so that pin 1 is at the bottom left. Added Figure 12.5 Sample Flowchart Flowchart amended. for Transmitting Serial Data Procedure 1 description added. Descriptions 1 and 3 deleted * Note on Issuance of Retransmission Start Condition Added * Note on Issuance of Stop Condition * Countermeasure * Additional Note * Precautions when Clearing the IRIC Flag when Using the Wait Function 15.6 Application Notes 354 Figure 15.10 Example of Analog Input Circuit Figure amended 18.3.2 Notes on Programming 373 (1) description added. 19.6.1 Writer Mode Setting 418 Description amended Section Page Item Description (see Manual for details) 21.1.7 Flash Memory Operating Modes 504 Figure 21.2 Flash Memory Related State Transitions "SWE" amended to "FLSHE". 505 Figure 21.3 Boot Mode Procedure 2 amended. 506 Figure 21.4 User Procedure 2 amended. Programming Mode (Example) 21.2.3 Erase Block Register 2 (EBR2) 511 Bit 7 * and Note description added. 21.3.1 Boot Mode 516 RAM Area Allocation in Boot Mode Description amended. 517 Figure 21.9 RAM Areas in Boot Mode Amended Notes on Use of Boot Mode 5 description amended. 21.4 to 21.4.4 520 to 524 Entire description amended. 21.5.1 Writer Mode Setting 528 * and Note description added. 21.5.3 Operation in Writer Mode 538 Figure 21.22 Status Read Mode Timing Waveforms Note amended Table 21.19 Status Read Mode Return Codes 21.6 Flash Memory 540 Programming and Erasing Precautions 541 (1) Program with the specified Description amended. voltage and timing Table 21.22 Area Accessed in FLSHE = 1 mode 2 Each Mode with FLSHE = 0 amended and FLSHE = 1 22.3.5 Application Note 23 Electrical Characteristics 2 description deleted. 553 to 604 Heading number amended 579 23.3 Electrical Characteristics (H8/3437SF Low-Voltage Version) B.2 Function 665 Entire description newly added. I 2C Bus Control Register Bit 2 to 0: I2C Transfer Rate Select Table amended and note added Contents Section 1 1.1 1.2 1.3 Overview............................................................................................................................ Block Diagram................................................................................................................... Pin Assignments and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Overview ........................................................................................................... CPU ..................................................................................................................... Overview............................................................................................................................ 2.1.1 Features ................................................................................................................ 2.1.2 Address Space ...................................................................................................... 2.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 2.2.1 General Registers.................................................................................................. 2.2.2 Control Registers.................................................................................................. 2.2.3 Initial Register Values .......................................................................................... Data Formats...................................................................................................................... 2.3.1 Data Formats in General Registers....................................................................... 2.3.2 Memory Data Formats.......................................................................................... Addressing Modes ............................................................................................................. 2.4.1 Addressing Mode.................................................................................................. 2.4.2 Calculation of Effective Address.......................................................................... Instruction Set.................................................................................................................... 2.5.1 Data Transfer Instructions .................................................................................... 2.5.2 Arithmetic Operations .......................................................................................... 2.5.3 Logic Operations .................................................................................................. 2.5.4 Shift Operations.................................................................................................... 2.5.5 Bit Manipulations ................................................................................................. 2.5.6 Branching Instructions.......................................................................................... 2.5.7 System Control Instructions ................................................................................. 2.5.8 Block Data Transfer Instruction ........................................................................... CPU States ......................................................................................................................... 2.6.1 Overview .............................................................................................................. 2.6.2 Program Execution State ...................................................................................... 2.6.3 Exception-Handling State .................................................................................... 2.6.4 Power-Down State................................................................................................ Access Timing and Bus Cycle........................................................................................... 2.7.1 Access to On-Chip Memory (RAM and ROM) ................................................... 2.7.2 Access to On-Chip Register Field and External Devices..................................... 1 1 5 6 6 7 19 19 19 20 20 21 21 21 22 23 24 25 26 26 28 32 34 36 37 37 39 44 46 47 49 49 50 50 51 51 51 53 i Section 3 3.1 3.2 3.3 3.4 MCU Operating Modes and Address Space ........................................... 57 Overview............................................................................................................................ 57 3.1.1 Mode Selection..................................................................................................... 57 3.1.2 Mode and System Control Registers .................................................................... 57 System Control Register (SYSCR).................................................................................... 58 Mode Control Register (MDCR) ....................................................................................... 60 Address Space Map in Each Operating Mode................................................................... 61 Section 4 4.1 4.2 4.3 4.4 Exception Handling........................................................................................ Overview............................................................................................................................ Reset .................................................................................................................................. 4.2.1 Overview .............................................................................................................. 4.2.2 Reset Sequence..................................................................................................... 4.2.3 Disabling of Interrupts after Reset ....................................................................... Interrupts............................................................................................................................ 4.3.1 Overview .............................................................................................................. 4.3.2 Interrupt-Related Registers .................................................................................. 4.3.3 External Interrupts................................................................................................ 4.3.4 Internal Interrupts ................................................................................................. 4.3.5 Interrupt Handling ................................................................................................ 4.3.6 Interrupt Response Time ...................................................................................... 4.3.7 Precaution ............................................................................................................. Note on Stack Handling..................................................................................................... 65 65 65 65 65 68 68 68 70 74 74 75 80 81 82 Section 5 5.1 5.2 5.3 Wait-State Controller .................................................................................... 83 Overview............................................................................................................................ 83 5.1.1 Features ................................................................................................................ 83 5.1.2 Block Diagram...................................................................................................... 83 5.1.3 Input/Output Pins.................................................................................................. 84 5.1.4 Register Configuration ......................................................................................... 84 Register Description .......................................................................................................... 84 5.2.1 Wait-State Control Register (WSCR) .................................................................. 84 Wait Modes........................................................................................................................ 86 Section 6 6.1 6.2 6.3 6.4 ii Clock Pulse Generator .................................................................................. Overview............................................................................................................................ 6.1.1 Block Diagram...................................................................................................... 6.1.2 Wait-State Control Register (WSCR) .................................................................. Oscillator Circuit ............................................................................................................... 6.2.1 Oscillator (Generic Device).................................................................................. 6.2.2 Oscillator Circuit (H8/3437S) .............................................................................. Duty Adjustment Circuit.................................................................................................... Prescaler ............................................................................................................................ 89 89 89 90 91 91 95 99 99 Section 7 I/O Ports ............................................................................................................ Overview............................................................................................................................ Port 1.................................................................................................................................. 7.2.1 Overview .............................................................................................................. 7.2.2 Register Configuration and Descriptions ............................................................. 7.2.3 Pin Functions in Each Mode ................................................................................ 7.2.4 Input Pull-Up Transistors ..................................................................................... 7.3 Port 2.................................................................................................................................. 7.3.1 Overview .............................................................................................................. 7.3.2 Register Configuration and Descriptions ............................................................. 7.3.3 Pin Functions in Each Mode ................................................................................ 7.3.4 Input Pull-Up Transistors ..................................................................................... 7.4 Port 3.................................................................................................................................. 7.4.1 Overview .............................................................................................................. 7.4.2 Register Configuration and Descriptions ............................................................. 7.4.3 Pin Functions in Each Mode ................................................................................ 7.4.4 Input Pull-Up Transistors ..................................................................................... 7.5 Port 4.................................................................................................................................. 7.5.1 Overview .............................................................................................................. 7.5.2 Register Configuration and Descriptions ............................................................. 7.5.3 Pin Functions........................................................................................................ 7.6 Port 5.................................................................................................................................. 7.6.1 Overview .............................................................................................................. 7.6.2 Register Configuration and Descriptions ............................................................. 7.6.3 Pin Functions........................................................................................................ 7.7 Port 6.................................................................................................................................. 7.7.1 Overview .............................................................................................................. 7.7.2 Register Configuration and Descriptions ............................................................. 7.7.3 Pin Functions........................................................................................................ 7.7.4 Input Pull-Up Transistors ..................................................................................... 7.8 Port 7.................................................................................................................................. 7.8.1 Overview .............................................................................................................. 7.8.2 Register Configuration and Descriptions ............................................................. 7.9 Port 8.................................................................................................................................. 7.9.1 Overview .............................................................................................................. 7.9.2 Register Configuration and Descriptions ............................................................. 7.9.3 Pin Functions........................................................................................................ 7.10 Port 9.................................................................................................................................. 7.10.1 Overview .............................................................................................................. 7.10.2 Register Configuration and Descriptions ............................................................. 7.10.3 Pin Functions........................................................................................................ 7.11 Port A................................................................................................................................. 7.11.1 Overview .............................................................................................................. 7.1 7.2 101 101 104 104 105 107 109 110 110 111 113 115 116 116 117 119 120 121 121 122 124 126 126 126 128 129 129 129 132 134 135 135 135 136 136 137 139 141 141 142 144 146 146 iii 7.11.2 Register Configuration and Descriptions ............................................................. 7.11.3 Pin Functions in Each Mode ................................................................................ 7.11.4 Input Pull-Up Transistors ..................................................................................... 7.12 Port B ................................................................................................................................. 7.12.1 Overview .............................................................................................................. 7.12.2 Register Configuration and Descriptions ............................................................. 7.12.3 Pin Functions in Each Mode ................................................................................ 7.12.4 Input Pull-Up Transistors ..................................................................................... 146 148 149 150 150 151 153 154 Section 8 155 155 155 156 157 158 159 159 159 160 162 164 166 168 170 173 173 175 176 176 179 179 180 181 182 183 8.1 8.2 8.3 8.4 8.5 8.6 8.7 16-Bit Free-Running Timer ......................................................................... Overview............................................................................................................................ 8.1.1 Features ................................................................................................................ 8.1.2 Block Diagram...................................................................................................... 8.1.3 Input and Output Pins........................................................................................... 8.1.4 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 8.2.1 Free-Running Counter (FRC)............................................................................... 8.2.2 Output Compare Registers A and B (OCRA and OCRB).................................... 8.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 8.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 8.2.5 Timer Control/Status Register (TCSR) ................................................................ 8.2.6 Timer Control Register (TCR) ............................................................................. 8.2.7 Timer Output Compare Control Register (TOCR) .............................................. CPU Interface .................................................................................................................... Operation ........................................................................................................................... 8.4.1 FRC Increment Timing ........................................................................................ 8.4.2 Output Compare Timing ...................................................................................... 8.4.3 FRC Clear Timing................................................................................................ 8.4.4 Input Capture Timing ........................................................................................... 8.4.5 Timing of Input Capture Flag (ICF) Setting ........................................................ 8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB) .......................... 8.4.7 Setting of FRC Overflow Flag (OVF).................................................................. Interrupts............................................................................................................................ Sample Application ........................................................................................................... Application Notes.............................................................................................................. Section 9 9.1 iv 8-Bit Timers ..................................................................................................... Overview............................................................................................................................ 9.1.1 Features ................................................................................................................ 9.1.2 Block Diagram...................................................................................................... 9.1.3 Input and Output Pins........................................................................................... 9.1.4 Register Configuration ......................................................................................... 189 189 189 190 191 191 9.2 9.3 9.4 9.5 9.6 Register Descriptions......................................................................................................... 9.2.1 Timer Counter (TCNT) ........................................................................................ 9.2.2 Time Constant Registers A and B (TCORA and TCORB).................................. 9.2.3 Timer Control Register (TCR) ............................................................................. 9.2.4 Timer Control/Status Register (TCSR) ................................................................ 9.2.5 Serial/Timer Control Register (STCR) ................................................................ Operation ........................................................................................................................... 9.3.1 TCNT Increment Timing...................................................................................... 9.3.2 Compare-Match Timing ....................................................................................... 9.3.3 External Reset of TCNT....................................................................................... 9.3.4 Setting of TCSR Overflow Flag (OVF) ............................................................... Interrupts............................................................................................................................ Sample Application ........................................................................................................... Application Notes.............................................................................................................. 9.6.1 Contention between TCNT Write and Clear........................................................ 9.6.2 Contention between TCNT Write and Increment ................................................ 9.6.3 Contention between TCOR Write and Compare-Match ...................................... 9.6.4 Contention between Compare-Match A and Compare-Match B ......................... 9.6.5 Increment Caused by Changing of Internal Clock Source ................................... 192 192 192 193 196 198 199 199 201 203 203 204 204 205 205 206 207 208 208 Section 10 PWM Timers.................................................................................................... 211 10.1 Overview............................................................................................................................ 10.1.1 Features ................................................................................................................ 10.1.2 Block Diagram...................................................................................................... 10.1.3 Input and Output Pins........................................................................................... 10.1.4 Register Configuration ......................................................................................... 10.2 Register Descriptions......................................................................................................... 10.2.1 Timer Counter (TCNT) ........................................................................................ 10.2.2 Duty Register (DTR) ............................................................................................ 10.2.3 Timer Control Register (TCR) ............................................................................. 10.3 Operation ........................................................................................................................... 10.3.1 Timer Increment ................................................................................................... 10.3.2 PWM Operation.................................................................................................... 10.4 Application Notes.............................................................................................................. 211 211 212 212 213 213 213 214 215 217 217 218 219 Section 11 Watchdog Timer ............................................................................................. 221 11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Output Pin ............................................................................................................ 11.1.4 Register Configuration ......................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 Timer Counter (TCNT) ........................................................................................ 221 221 222 222 223 223 223 v 11.2.2 Timer Control/Status Register (TCSR) ................................................................ 11.2.3 System Control Register (SYSCR) ...................................................................... 11.2.4 Register Access .................................................................................................... 11.3 Operation ........................................................................................................................... 11.3.1 Watchdog Timer Mode ........................................................................................ 11.3.2 Interval Timer Mode ............................................................................................ 11.3.3 Setting the Overflow Flag .................................................................................... 11.3.4 RESO Signal Output Timing................................................................................ 11.4 Application Notes.............................................................................................................. 11.4.1 Contention between TCNT Write and Increment ................................................ 11.4.2 Changing the Clock Select Bits (CKS2 to CKS0)................................................ 11.4.3 Recovery from Software Standby Mode .............................................................. 11.4.4 Switching between Watchdog Timer Mode and Interval Timer Mode................ 11.4.5 System Reset by RESO Signal............................................................................. 11.4.6 Detection of Program Runaway ........................................................................... 224 226 226 227 227 228 228 229 230 230 230 230 231 231 231 Section 12 Serial Communication Interface ................................................................ 233 12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Input and Output Pins........................................................................................... 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 Receive Shift Register (RSR)............................................................................... 12.2.2 Receive Data Register (RDR) .............................................................................. 12.2.3 Transmit Shift Register (TSR).............................................................................. 12.2.4 Transmit Data Register (TDR) ............................................................................. 12.2.5 Serial Mode Register (SMR)................................................................................ 12.2.6 Serial Control Register (SCR).............................................................................. 12.2.7 Serial Status Register (SSR)................................................................................. 12.2.8 Bit Rate Register (BRR)....................................................................................... 12.2.9 Serial/Timer Control Register (STCR) ................................................................ 12.3 Operation ........................................................................................................................... 12.3.1 Overview .............................................................................................................. 12.3.2 Asynchronous Mode ............................................................................................ 12.3.3 Synchronous Mode............................................................................................... 12.4 Interrupts............................................................................................................................ 12.5 Application Notes.............................................................................................................. 233 233 234 235 236 237 237 237 237 238 238 240 243 246 257 258 258 260 273 279 279 Section 13 I2 C Bus Interface [Option] ........................................................................... 283 13.1 Overview............................................................................................................................ 283 13.1.1 Features ................................................................................................................ 283 13.1.2 Block Diagram...................................................................................................... 285 vi 13.1.3 Input/Output Pins.................................................................................................. 13.1.4 Register Configuration ......................................................................................... 13.2 Register Descriptions......................................................................................................... 13.2.1 I2C Bus Data Register (ICDR).............................................................................. 13.2.2 Slave Address Register (SAR) ............................................................................. 13.2.3 I2C Bus Mode Register (ICMR) ........................................................................... 13.2.4 I2C Bus Control Register (ICCR) ......................................................................... 13.2.5 I2C Bus Status Register (ICSR)............................................................................ 13.2.6 Serial/Timer Control Register (STCR) ................................................................ 13.3 Operation ........................................................................................................................... 13.3.1 I2C Bus Data Format............................................................................................. 13.3.2 Master Transmit Operation .................................................................................. 13.3.3 Master Receive Operation .................................................................................... 13.3.4 Slave Transmit Operation..................................................................................... 13.3.5 Slave Receive Operation ...................................................................................... 13.3.6 IRIC Set Timing and SCL Control....................................................................... 13.3.7 Noise Canceler...................................................................................................... 13.3.8 Sample Flowcharts ............................................................................................... 13.4 Application Notes.............................................................................................................. 286 286 287 287 287 288 289 292 296 297 297 298 300 302 304 305 306 307 311 Section 14 Host Interface ................................................................................................... 317 14.1 Overview............................................................................................................................ 14.1.1 Block Diagram...................................................................................................... 14.1.2 Input and Output Pins........................................................................................... 14.1.3 Register Configuration ......................................................................................... 14.2 Register Descriptions......................................................................................................... 14.2.1 System Control Register (SYSCR) ...................................................................... 14.2.2 Host Interface Control Register (HICR) .............................................................. 14.2.3 Input Data Register 1 (IDR1) ............................................................................... 14.2.4 Output Data Register 1 (ODR1) ........................................................................... 14.2.5 Status Register 1 (STR1)...................................................................................... 14.2.6 Input Data Register 2 (IDR2) ............................................................................... 14.2.7 Output Data Register 2 (ODR2) ........................................................................... 14.2.8 Status Register 2 (STR2)...................................................................................... 14.2.9 Serial/Timer Control Register (STCR) ................................................................ 14.3 Operation ........................................................................................................................... 14.3.1 Host Interface Operation ...................................................................................... 14.3.2 Control States ....................................................................................................... 14.3.3 A20 Gate ................................................................................................................ 14.4 Interrupts............................................................................................................................ 14.4.1 IBF1, IBF2............................................................................................................ 14.4.2 HIRQ11, HIRQ1, and HIRQ12 ................................................................................ 14.5 Application Note................................................................................................................ 317 318 319 320 321 321 321 322 323 323 324 325 325 327 328 328 328 329 332 332 332 333 vii Section 15 A/D Converter ................................................................................................. 335 15.1 Overview............................................................................................................................ 15.1.1 Features ................................................................................................................ 15.1.2 Block Diagram...................................................................................................... 15.1.3 Input Pins.............................................................................................................. 15.1.4 Register Configuration ......................................................................................... 15.2 Register Descriptions......................................................................................................... 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 15.2.2 A/D Control/Status Register (ADCSR)................................................................ 15.2.3 A/D Control Register (ADCR)............................................................................. 15.3 CPU Interface .................................................................................................................... 15.4 Operation ........................................................................................................................... 15.4.1 Single Mode (SCAN = 0) ..................................................................................... 15.4.2 Scan Mode (SCAN = 1) ....................................................................................... 15.4.3 Input Sampling and A/D Conversion Time.......................................................... 15.4.4 External Trigger Input Timing ............................................................................. 15.5 Interrupts............................................................................................................................ 15.6 Application Notes.............................................................................................................. 335 335 336 337 338 339 339 340 342 342 344 344 346 348 349 350 350 Section 16 D/A Converter ................................................................................................. 355 16.1 Overview............................................................................................................................ 16.1.1 Features ................................................................................................................ 16.1.2 Block Diagram...................................................................................................... 16.1.3 Input and Output Pins........................................................................................... 16.1.4 Register Configuration............................................................................................ 16.2 Register Descriptions......................................................................................................... 16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 16.2.2 D/A Control Register (DACR)............................................................................. 16.3 Operation ........................................................................................................................... 355 355 356 357 357 358 358 358 360 Section 17 RAM ................................................................................................................... 361 17.1 Overview............................................................................................................................ 17.1.1 Block Diagram...................................................................................................... 17.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR) ....................... 17.2 Operation ........................................................................................................................... 17.2.1 Expanded Modes (Modes 1 and 2)....................................................................... 17.2.2 Single-Chip Mode (Mode 3) ................................................................................ 361 361 362 362 362 362 Section 18 ROM (Mask ROM Version/ZTAT Version).......................................... 363 18.1 Overview............................................................................................................................ 18.1.1 Block Diagram...................................................................................................... 18.2 Writer Mode (H8/3437, H8/3434)..................................................................................... 18.2.1 Writer Mode Setup ............................................................................................... viii 363 364 364 364 18.2.2 Socket Adapter Pin Assignments and Memory Map ........................................... 18.3 PROM Programming ......................................................................................................... 18.3.1 Programming and Verification ............................................................................. 18.3.2 Notes on Programming......................................................................................... 18.3.3 Reliability of Programmed Data .......................................................................... 365 368 368 373 374 Section 19 ROM (32-kbyte Dual-Power-Supply Flash Memory Version) ........ 375 19.1 Flash Memory Overview ................................................................................................... 19.1.1 Flash Memory Operating Principle ...................................................................... 19.1.2 Mode Programming and Flash Memory Address Space...................................... 19.1.3 Features ................................................................................................................ 19.1.4 Block Diagram...................................................................................................... 19.1.5 Input/Output Pins.................................................................................................. 19.1.6 Register Configuration ......................................................................................... 19.2 Flash Memory Register Descriptions ................................................................................ 19.2.1 Flash Memory Control Register (FLMCR).......................................................... 19.2.2 Erase Block Register 1 (EBR1)............................................................................ 19.2.3 Erase Block Register 2 (EBR2)............................................................................ 19.2.4 Wait-State Control Register (WSCR) .................................................................. 19.3 On-Board Programming Modes ........................................................................................ 19.3.1 Boot Mode............................................................................................................ 19.3.2 User Programming Mode ..................................................................................... 19.4 Programming and Erasing Flash Memory......................................................................... 19.4.1 Program Mode...................................................................................................... 19.4.2 Program-Verify Mode .......................................................................................... 19.4.3 Programming Flowchart and Sample Program .................................................... 19.4.4 Erase Mode........................................................................................................... 19.4.5 Erase-Verify Mode ............................................................................................... 19.4.6 Erasing Flowchart and Sample Program .............................................................. 19.4.7 Prewrite Verify Mode........................................................................................... 19.4.8 Protect Modes....................................................................................................... 19.4.9 Interrupt Handling during Flash Memory Programming and Erasing ................. 19.5 Flash Memory Emulation by RAM ................................................................................... 19.6 Flash Memory Writer Mode (H8/3434F) .......................................................................... 19.6.1 Writer Mode Setting ............................................................................................. 19.6.2 Socket Adapter and Memory Map ....................................................................... 19.6.3 Operation in Writer Mode .................................................................................... 19.7 Flash Memory Programming and Erasing Precautions ..................................................... 375 375 376 376 377 378 378 379 379 380 381 382 385 386 392 394 394 395 396 398 398 399 412 412 413 415 418 418 418 420 428 Section 20 ROM (60-kbyte Dual-Power-Supply Flash Memory Version) ........ 437 20.1 Flash Memory Overview ................................................................................................... 437 20.1.1 Flash Memory Operating Principle ...................................................................... 437 20.1.2 Mode Programming and Flash Memory Address Space...................................... 438 ix 20.2 20.3 20.4 20.5 20.6 20.7 20.1.3 Features ................................................................................................................ 20.1.4 Block Diagram...................................................................................................... 20.1.5 Input/Output Pins.................................................................................................. 20.1.6 Register Configuration ......................................................................................... Flash Memory Register Descriptions ................................................................................ 20.2.1 Flash Memory Control Register (FLMCR).......................................................... 20.2.2 Erase Block Register 1 (EBR1)............................................................................ 20.2.3 Erase Block Register 2 (EBR2)............................................................................ 20.2.4 Wait-State Control Register (WSCR) .................................................................. On-Board Programming Modes ........................................................................................ 20.3.1 Boot Mode............................................................................................................ 20.3.2 User Programming Mode ..................................................................................... Programming and Erasing Flash Memory......................................................................... 20.4.1 Program Mode...................................................................................................... 20.4.2 Program-Verify Mode .......................................................................................... 20.4.3 Programming Flowchart and Sample Program .................................................... 20.4.4 Erase Mode........................................................................................................... 20.4.5 Erase-Verify Mode ............................................................................................... 20.4.6 Erasing Flowchart and Sample Program .............................................................. 20.4.7 Prewrite Verify Mode........................................................................................... 20.4.8 Protect Modes....................................................................................................... 20.4.9 Interrupt Handling during Flash Memory Programming and Erasing ................. Flash Memory Emulation by RAM ................................................................................... Flash Memory Writer Mode (H8/3437F) .......................................................................... 20.6.1 Writer Mode Setting ............................................................................................. 20.6.2 Socket Adapter and Memory Map ....................................................................... 20.6.3 Operation in Writer Mode .................................................................................... Flash Memory Programming and Erasing Precautions ..................................................... 438 439 440 440 441 441 442 443 444 447 448 454 456 456 457 458 460 460 461 474 474 475 477 480 480 480 482 490 Section 21 ROM (60-kbyte Single-Power-Supply Flash Memory Version) ..... 499 21.1 Flash Memory Overview ................................................................................................... 21.1.1 Mode Pin Settings and ROM Space ..................................................................... 21.1.2 Features ................................................................................................................ 21.1.3 Block Diagram...................................................................................................... 21.1.4 Input/Output Pins.................................................................................................. 21.1.5 Register Configuration ......................................................................................... 21.1.6 Mode Control Register (MDCR).......................................................................... 21.1.7 Flash Memory Operating Modes.......................................................................... 21.2 Flash Memory Register Descriptions ................................................................................ 21.2.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 21.2.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 21.2.3 Erase Block Register 2 (EBR2)............................................................................ 21.2.4 Wait-State Control Register (WSCR) .................................................................. x 499 499 500 501 502 502 503 504 508 508 510 511 512 21.3 On-Board Programming Modes ........................................................................................ 21.3.1 Boot Mode............................................................................................................ 21.3.2 User Programming Mode ..................................................................................... 21.4 Programming/Erasing Flash Memory................................................................................ 21.4.1 Program Mode...................................................................................................... 21.4.2 Program-Verify Mode .......................................................................................... 21.4.3 Erase Mode........................................................................................................... 21.4.4 Erase-Verify Mode ............................................................................................... 21.4.5 Protect Modes....................................................................................................... 21.4.6 Interrupt Handling during Flash Memory Programming and Erasing ................. 21.5 Flash Memory Writer Mode (H8/3437SF)........................................................................ 21.5.1 Writer Mode Setting ............................................................................................. 21.5.2 Socket Adapter and Memory Map ....................................................................... 21.5.3 Operation in Writer Mode .................................................................................... 21.6 Flash Memory Programming and Erasing Precautions ..................................................... 513 513 519 520 520 521 523 523 525 527 528 528 528 529 540 Section 22 Power-Down State.......................................................................................... 543 22.1 Overview............................................................................................................................ 22.1.1 System Control Register (SYSCR) ...................................................................... 22.2 Sleep Mode........................................................................................................................ 22.2.1 Transition to Sleep Mode ..................................................................................... 22.2.2 Exit from Sleep Mode .......................................................................................... 22.3 Software Standby Mode .................................................................................................... 22.3.1 Transition to Software Standby Mode.................................................................. 22.3.2 Exit from Software Standby Mode....................................................................... 22.3.3 Clock Settling Time for Exit from Software Standby Mode................................ 22.3.4 Sample Application of Software Standby Mode.................................................. 22.3.5 Application Note .................................................................................................. 22.4 Hardware Standby Mode ................................................................................................... 22.4.1 Transition to Hardware Standby Mode ................................................................ 22.4.2 Recovery from Hardware Standby Mode............................................................. 22.4.3 Timing Relationships............................................................................................ 543 544 546 546 546 547 547 547 548 549 550 551 551 551 552 Section 23 Electrical Specifications ............................................................................... 553 23.1 Absolute Maximum Ratings.............................................................................................. 23.2 Electrical Characteristics ................................................................................................... 23.2.1 DC Characteristics................................................................................................ 23.2.2 AC Characteristics................................................................................................ 23.2.3 A/D Converter Characteristics ............................................................................. 23.2.4 D/A Converter Characteristics ............................................................................. 23.2.5 Flash Memory Characteristics (H8/3437SF Only)............................................... 23.3 Absolute Maximum Ratings (H8/3437SF Low-Voltage Version).................................... 23.4 Electrical Characteristics (H8/3437SF Low-Voltage Version) ......................................... 553 554 554 567 575 576 577 579 580 xi 23.4.1 DC Characteristics................................................................................................ 23.4.2 AC Characteristics................................................................................................ 23.4.3 A/D Converter Characteristics ............................................................................. 23.4.4 D/A Converter Characteristics ............................................................................. 23.4.5 Flash Memory Characteristics.............................................................................. 23.5 MCU Operational Timing.................................................................................................. 23.5.1 Bus Timing ........................................................................................................... 23.5.2 Control Signal Timing.......................................................................................... 23.5.3 16-Bit Free-Running Timer Timing ..................................................................... 23.5.4 8-Bit Timer Timing .............................................................................................. 23.5.5 Pulse Width Modulation Timer Timing ............................................................... 23.5.6 Serial Communication Interface Timing.............................................................. 23.5.7 I/O Port Timing .................................................................................................... 23.5.8 Host Interface Timing .......................................................................................... 23.5.9 I2C Bus Timing (Option) ...................................................................................... 23.5.10 Reset Output Timing ............................................................................................ 23.5.11 External Clock Output Timing ............................................................................. 580 585 591 592 593 595 595 596 598 599 600 601 602 602 603 604 604 Appendix A CPU Instruction Set ................................................................................... 605 A.1 A.2 A.3 Instruction Set List ............................................................................................................ 605 Operation Code Map.......................................................................................................... 613 Number of States Required for Execution......................................................................... 615 Appendix B Internal I/O Register .................................................................................. 621 B.1 B.2 Addresses........................................................................................................................... 621 Function ............................................................................................................................. 626 Appendix C I/O Port Block Diagrams .......................................................................... 684 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 Port 1 Block Diagram........................................................................................................ Port 2 Block Diagram........................................................................................................ Port 3 Block Diagram........................................................................................................ Port 4 Block Diagrams ...................................................................................................... Port 5 Block Diagrams ...................................................................................................... Port 6 Block Diagrams ...................................................................................................... Port 7 Block Diagrams ...................................................................................................... Port 8 Block Diagrams ...................................................................................................... Port 9 Block Diagrams ...................................................................................................... Port A Block Diagram ....................................................................................................... Port B Block Diagram ....................................................................................................... 684 685 686 687 691 694 698 699 705 711 712 Appendix D Port States in Each Processing State ..................................................... 713 xii Appendix E Timing of Transition to and Recovery from Hardware Standby Mode ............................................................... 715 Appendix F Option Lists .................................................................................................. 716 Appendix G Product Code Lineup ................................................................................. 718 Appendix H Package Dimensions .................................................................................. 720 xiii xiv Section 1 Overview 1.1 Overview The H8/3437 Series of single-chip microcomputers features an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 CPU is a high-speed processor with an architecture featuring powerful bitmanipulation instructions, ideally suited for realtime control applications. The on-chip supporting modules implement peripheral functions needed in system configurations. These include ROM, RAM, four types of timers (a 16-bit free-running timer, 8-bit timers, PWM timers, and a watchdog timer), a serial communication interface (SCI), an I2C bus interface [option], a host interface (HIF), an A/D converter, a D/A converter, and I/O ports. The H8/3437 Series can operate in single-chip mode or in two expanded modes, depending on the requirements of the application. Besides the mask-ROM versions of the H8/3437 Series, there are ZTATTM*1 versions with on-chip PROM, and an F-ZTATTM*2 version with on-chip flash memory. The F-ZTATTM version can be programmed or reprogrammed on-board in application systems. Notes: *1 ZTATTM (zero turn-around time) is a trademark of Hitachi, Ltd. *2 F-ZTATTM (flexible-ZTAT) is a trademark of Hitachi, Ltd. The guaranteed voltage range is different for the F-ZTAT LH version. VCC LH Version General Version 3.0 V to 5.5 V 2.7 V to 5.5 V AVCC Table 1.1 lists the features of the H8/3437 Series. 1 Table 1.1 Features Item Specification CPU Two-way general register configuration * Eight 16-bit registers, or * Sixteen 8-bit registers High-speed operation * Maximum clock rate (o clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V * 8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns (12 MHz), 200 ns (10 MHz) * 8 x 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) * 16 / 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) Streamlined, concise instruction set * Instruction length: 2 or 4 bytes * Register-register arithmetic and logic operations * MOV instruction for data transfer between registers and memory Instruction set features * Multiply instruction (8 bits x 8 bits) * Divide instruction (16 bits / 8 bits) * Bit-accumulator instructions * Register-indirect specification of bit positions Memory * * * H8/3437: 60-kbyte ROM; 2-kbyte RAM H8/3436: 48-kbyte ROM; 2-kbyte RAM H8/3434: 32-kbyte ROM; 1-kbyte RAM 16-bit free-running timer (1 channel) * * * One 16-bit free-running counter (can also count external events) Two output-compare lines Four input capture lines (can be buffered) 8-bit timer (2 channels) Each channel has * One 8-bit up-counter (can also count external events) * Two time constant registers PWM timer (2 channels) * * Duty cycle can be set from 0 to 100% Resolution: 1/250 Watchdog timer (WDT) (1 channel) * * Overflow can generate a reset or NMI interrupt Also usable as interval timer 2 Item Specification Serial communication * interface (SCI) * (2 channels) * Asynchronous or synchronous mode (selectable) Full duplex: can transmit and receive simultaneously On-chip baud rate generator I 2C bus interface (1 channel) [option] * * Conforms to Philips I2C bus interface Includes single master mode and slave mode Host interface (HIF) * * * * 8-bit host interface port Three host interrupt requests (HIRQ 1, HIRQ11, HIRQ12) Regular and fast A 20 gate output Two register sets, each with two data registers and a status register Keyboard controller * Controls a matrix-scan keyboard by providing a keyboard scan function with wake-up interrupts and sense ports A/D converter * * * * 10-bit resolution Eight channels: single or scan mode (selectable) Start of A/D conversion can be externally triggered Sample-and-hold function D/A converter * * 8-bit resolution Two channels I/O ports * * 74 input/output lines (16 of which can drive LEDs) 8 input-only lines Interrupts * * Nine external interrupt lines: NMI, IRQ0 to IRQ7 26 on-chip interrupt sources Wait control * Three selectable wait modes Operating modes * * * Expanded mode with on-chip ROM disabled (mode 1) Expanded mode with on-chip ROM disabled (mode 1) Single-chip mode (mode 3) Power-down modes * * * Sleep mode Software standby mode Hardware standby mode Other features * On-chip clock pulse generator 3 Item Specification Series lineup Part Number Product Name 5-V Version (16 MHz) 4-V Version (12 MHz) 3-V Version (10 MHz) Package ROM H8/3437 F-ZTAT HD64F3437F16 HD64F3437F16 HD64F3437FLH16 100-pin QFP (FP-100B) Flash memory HD64F3437FLH16 H8/3437 ZTAT H8/3437 H8/3436 H8/3434 F-ZTAT H8/3434 ZTAT H8/3434 100-pin TQFP (TFP-100B) (dual-powersupply product) HD64F3437TF16 HD64F3437TF16 HD64F3437TFLH16 HD64F3437TFLH16 HD64F3437SF16 HD64F3437SF16 100-pin QFP (FP-100B) Flash memory (single-power- HD64F3437STF16 HD64F3437STF16 100-pin TQFP (TFP-100B) supply product) HD6473437F16 HD6473437F16 100-pin QFP (FP-100B) PROM HD6473437TF16 HD6473437TF16 100-pin TQFP (TFP-100B) HD6433437F16 HD6433437F12 HD6433437VF10 100-pin QFP (FP-100B) HD6433437TF16 HD6433437TF12 HD6433437VTF10 100-pin TQFP (TFP-100B) HD6433436F16 HD6433436F12 HD6433436VF10 100-pin QFP (FP-100B) HD6433436TF16 HD6433436TF12 HD6433436VTF10 100-pin TQFP (TFP-100B) HD64F3434F16 HD64F3434F16 HD64F3434FLH16 HD64F3434FLH16 100-pin QFP (FP-100B) HD64F3434TF16 HD64F3434TF16 HD64F3434TFLH16 HD64F3434TFLH16 100-pin TQFP (TFP-100B) HD6473434F16 HD6473434F16 100-pin QFP (FP-100B) HD6473434TF16 HD6473434TF16 100-pin TQFP (TFP-100B) HD6433434F16 HD6433434F12 HD6433434VF10 100-pin QFP (FP-100B) HD6433434TF16 HD6433434TF12 HD6433434VTF10 100-pin TQFP (TFP-100B) Mask ROM Mask ROM Flash memory (dual-powersupply product) PROM Mask ROM The I2C bus interface is an available option. Please note the following points regarding this option. In mask ROM versions, chips featuring the I 2C bus interface include a W in the part number. Example: HD6433437WTF, HD6433434WF, etc. 4 1.2 Block Diagram PWM timer (2 channels) 8-bit D/A converter (2 channels) Port 7 P30/D0/HDB0 P31/D1/HDB1 P32/D2/HDB2 P33/D3/HDB3 P34/D4/HDB4 P35/D5/HDB5 P36/D6/HDB6 P37/D7/HDB7 P80/HA0 P81/GA20 P82/CS1 P83/IOR P84/TxD1/IRQ3/IOW P85/RxD1/IRQ4/CS2 P86/SCK1/IRQ5/SCL Port 5 P50/TxD0 P51/RxD0 P52/SCK0 Port 1 Port 4 Port B 10-bit A/D converter (8 channels) Port 9 8-bit timer (2 channels) P90/ADTRG/ECS2/IRQ2 P91/IRQ1/EIOW P92/IRQ0 P93/RD P94/WR P95/AS P96/o P97/WAIT/SDA Port 3 16-bit free-running timer Serial communication interface (2 channels) 2 I C bus interface (1 channel) [option] PB0/XDB0 PB1/XDB1 PB2/XDB2 PB3/XDB3 PB4/XDB4 PB5/XDB5 PB6/XDB6 PB7/XDB7 Port 8 Host interface Address bus RESO RES STBY NMI MD0 MD1 VCCB VCC VCC VSS VSS VSS VSS Data bus (high) XTAL EXTAL Clock pulse generator Watchdog timer P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVref AVCC AVSS KEYIN0/P60/FTCI KEYIN1/P61/FTOA KEYIN2/P62/FTIA KEYIN3/P63/FTIB KEYIN4/P64/FTIC KEYIN5/P65/FTID KEYIN6/P66/FTOB/IRQ6 KEYIN7/P67/IRQ7 ROM (flash memory, RAM PROM, or H8/3437: 2 kbytes mask ROM) H8/3437: 60 kbytes H8/3436: 2 kbytes H8/3436: 48 kbytes H8/3434: 1 kbyte H8/3434: 32 kbytes Port 2 P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 Data bus (low) Port 6 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 CPU H8/300 P40/TMCI0 P41/TMO0 P42/TMRI0 HIRQ11/P43/TMCI1 HIRQ1/P44/TMO1 HIRQ12/P45/TMRI1 P46/PW0 P47/PW1 PA0/KEYIN8 PA1/KEYIN9 PA2/KEYIN10 PA3/KEYIN11 PA4/KEYIN12 PA5/KEYIN13 PA6/KEYIN14 PA7/KEYIN15 Port A Figure 1.1 shows a block diagram of the H8/3437 Series. Memory Sizes ROM RAM H8/3437 60 kbytes 2 kbytes H8/3436 48 kbytes 2 kbytes H8/3434 32 kbytes 1 kbyte Figure 1.1 Block Diagram 5 1.3 Pin Assignments and Functions 1.3.1 Pin Arrangement 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 76 50 77 49 78 48 79 47 80 46 81 45 82 44 83 43 84 42 85 41 86 40 87 39 FP-100B, TFP-100B (top view) 88 89 38 37 25 24 23 22 21 20 19 18 17 16 15 14 P41/TMO0 P40/TMCI0 PA0/KEYIN8 PA1/KEYIN9 AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC AVref P67/KEYIN7/IRQ7 P66/KEYIN6/IRQ6/FTOB P65/KEYIN5/FTID P64/KEYIN4/FTIC PA2/KEYIN10 PA3/KEYIN11 P63/KEYIN3/FTIB P62/KEYIN2/FTIA P61/KEYIN1/FTOA P60/KEYIN0/FTCI RES XTAL EXTAL VCCB MD1 MD0 NMI FVPP*/STBY VCC KEYIN15/PA7 KEYIN14/PA6 SCK0/P52 RxD0/P51 TxD0/P50 VSS SDA/WAIT/P97 o/P96 AS/P95 WR/P94 KEYIN13/PA5 KEYIN12/PA4 RD/P93 IRQ0/P92 EIOW/IRQ1/P91 ADTRG/ECS2/IRQ2/P90 13 26 12 27 100 11 28 99 10 29 98 9 30 97 8 31 96 7 32 95 6 33 94 5 34 93 4 35 92 3 36 91 2 90 1 A3/P13 A2/P12 A1/P11 A0/P10 XDB3/PB3 XDB2/PB2 D0/HDB0/P30 D1/HDB1/P31 D2/HDB2/P32 D3/HDB3/P33 D4/HDB4/P34 D5/HDB5/P35 D6/HDB6/P36 D7/HDB7/P37 XDB1/PB1 XDB0/PB0 VSS HA0/P80 GA20/P81 CS1/P82 IOR/P83 IOW/TxD1/IRQ3/P84 CS2/RxD1/IRQ4/P85 SCL/SCK1/IRQ5/P86 RESO 74 75 P14/A4 P15/A5 P16/A6 P17/A7 VSS VSS PB4/XDB4 PB5/XDB5 P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 VCC PB6/XDB6 PB7/XDB7 P47/PW1 P46/PW0 P45/TMRI1/HIRQ12 P44/TMO1/HIRQ1 P43/TMCI1/HIRQ11 P42/TMRI0 Figure 1.2 shows the pin arrangement of the FP-100B and TFP-100B packages. Note: * In the S-mask model (single-power-supply model), pin 8 functions only as the STBY pin. Figure 1.2 Pin Arrangement (FP-100B, TFP-100B, Top View) 6 1.3.2 Pin Functions Pin Assignments in Each Operating Mode: Table 1.2 lists the assignments of the pins of the FP-100B and TFP-100B packages in each operating mode. Table 1.2 Pin Assignments in Each Operating Mode FP-100B, TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 1 RES RES RES RES VPP RES 2 XTAL XTAL XTAL XTAL NC XTAL 3 EXTAL EXTAL EXTAL EXTAL NC EXTAL 4 VCCB VCCB VCCB VCCB VCC VCC 5 MD1 MD1 MD1 MD1 VSS VSS 6 MD0 MD0 MD0 MD0 VSS VSS 7 NMI NMI NMI NMI EA9 FA 9 8 STBY STBY/FVPP STBY/FVPP STBY/FVPP VSS FV PP 9 VCC VCC VCC VCC VCC VCC 10 PA7/KEYIN15 PA7/KEYIN15 PA7/KEYIN15 PA7/KEYIN15 NC NC 11 PA6/KEYIN14 PA6/KEYIN14 PA6/KEYIN14 PA6/KEYIN14 NC NC 12 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 NC NC 13 P51/RxD0 P51/RxD0 P51/RxD0 P51/RxD0 NC NC 14 P50/TxD0 P50/TxD0 P50/TxD0 P50/TxD0 NC NC 15 VSS VSS VSS VSS VSS VSS 16 P97/WAIT/SDA P97/WAIT/SDA P97/SDA P97/SDA NC VCC 17 o o P96/o P96/o NC NC 18 AS AS P95 P95 NC FA 16 19 WR WR P94 P94 NC FA 15 20 PA5/KEYIN13 PA5/KEYIN13 PA5/KEYIN13 PA5/KEYIN13 NC NC 21 PA4/KEYIN12 PA4/KEYIN12 PA4/KEYIN12 PA4/KEYIN12 NC NC 22 RD RD P93 P93 NC WE 23 P92/IRQ0 P92/IRQ0 P92/IRQ0 P92/IRQ0 PGM VSS Pin No. Expanded Modes Single-Chip Mode Mode 3 7 Pin No. FP-100B, TFP-100B Expanded Modes Single-Chip Mode Mode 3 Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 24 P91/IRQ1 when HIF is disabled or STAC bit is 0 in STCR; EIOW/IRQ1 when HIF is enabled and STAC bit is 1 in STCR EA15 VCC 25 P90/IRQ2/ADTRG when HIF is disabled or STAC bit is 0 in STCR; ECS2/IRQ2 when HIF is enabled and STAC bit is 1 in STCR EA16 VCC 26 P60/FTCI/ KEYIN0 P60/FTCI/ KEYIN0 P60/FTCI/ KEYIN0 P60/FTCI/ KEYIN0 NC NC 27 P61/FTOA/ KEYIN1 P61/FTOA/ KEYIN1 P61/FTOA/ KEYIN1 P61/FTOA/ KEYIN1 NC NC 28 P62/FTIA/ KEYIN2 P62/FTIA/ KEYIN2 P62/FTIA/ KEYIN2 P62/FTIA/ KEYIN2 NC NC 29 P63/FTIB/ KEYIN3 P63/FTIB/ KEYIN3 P63/FTIB/ KEYIN3 P63/FTIB/ KEYIN3 VCC VCC 30 PA3/KEYIN11 PA3/KEYIN11 PA3/KEYIN11 PA3/KEYIN11 NC NC 31 PA2/KEYIN10 PA2/KEYIN10 PA2/KEYIN10 PA2/KEYIN10 NC NC 32 P64/FTIC/ KEYIN4 P64/FTIC/ KEYIN4 P64/FTIC/ KEYIN4 P64/FTIC/ KEYIN4 VCC VCC 33 P65/FTID/ KEYIN5 P65/FTID/ KEYIN5 P65/FTID/ KEYIN5 P65/FTID/ KEYIN5 NC NC 34 P66/FTOB/ IRQ6/KEYIN6 P66/FTOB/ IRQ6/KEYIN6 P66/FTOB/ IRQ6/KEYIN6 P66/FTOB/ IRQ6/KEYIN6 NC NC 35 P67/IRQ7/ KEYIN7 P67/IRQ7/ KEYIN7 P67/IRQ7/ KEYIN7 P67/IRQ7/ KEYIN7 NC VSS 36 AVref AVref AVref AVref VCC VSS 37 AVCC AVCC AVCC AVCC VCC VCC 38 P70/AN0 P70/AN0 P70/AN0 P70/AN0 NC NC 39 P71/AN1 P71/AN1 P71/AN1 P71/AN1 NC NC 40 P72/AN2 P72/AN2 P72/AN2 P72/AN2 NC NC 41 P73/AN3 P73/AN3 P73/AN3 P73/AN3 NC NC 42 P74/AN4 P74/AN4 P74/AN4 P74/AN4 NC NC 43 P75/AN5 P75/AN5 P75/AN5 P75/AN5 NC NC 44 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 NC NC 8 FP-100B, TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 45 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 NC NC 46 AVSS AVSS AVSS AVSS VSS VSS 47 PA1/KEYIN9 PA1/KEYIN9 PA1/KEYIN9 PA1/KEYIN9 NC NC 48 PA0/KEYIN8 PA0/KEYIN8 PA0/KEYIN8 PA0/KEYIN8 NC NC 49 P40/TMCI0 P40/TMCI0 P40/TMCI0 P40/TMCI0 NC NC 50 P41/TMO0 P41/TMO0 P41/TMO0 P41/TMO0 NC NC 51 P42/TMRI0 P42/TMRI0 P42/TMRI0 P42/TMRI0 NC NC 52 P43/TMCI1/ HIRQ11*1 P43/TMCI1/ HIRQ11*1 P43/TMCI1 HIRQ11/TMCI1 NC NC 53 P44/TMO1/ HIRQ1*1 P44/TMO1/ HIRQ1*1 P44/TMO1 HIRQ1/TMO1 NC NC 54 P45/TMRI1/ HIRQ12*1 P45/TMRI1/ HIRQ12*1 P45/TMRI1 HIRQ12/TMRI1 NC NC 55 P46/PW0 P46/PW0 P46/PW0 P46/PW0 NC NC 56 P47/PW1 Pin No. Expanded Modes Single-Chip Mode Mode 3 P47/PW1 P47/PW1 P47/PW1 NC NC PB7/XDB7 *2 PB7 PB7 NC NC PB6/XDB6 *2 PB6 PB6 NC NC PB7/XDB7 *2 58 PB6/XDB6 *2 59 VCC VCC VCC VCC VCC VCC 60 A15 P27/A 15 P27 P27 CE CE 61 A14 P26/A 14 P26 P26 EA14 FA 14 62 A13 P25/A 13 P25 P25 EA13 FA 13 63 A12 P24/A 12 P24 P24 EA12 FA 12 64 A11 P23/A 11 P23 P23 EA11 FA 11 65 A10 P22/A 10 P22 P22 EA10 FA 10 66 A9 P21/A 9 P21 P21 OE OE 67 A8 57 P20/A 8 PB5/XDB5 *2 69 PB4/XDB4 *2 70 VSS 68 P20 P20 EA8 FA 8 PB5/XDB5 *2 PB5 PB5 NC NC PB4/XDB4 *2 PB4 PB4 NC NC VSS VSS VSS VSS VSS 9 FP-100B, TFP-100B Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 71 VSS VSS VSS VSS VSS VSS 72 A7 P17/A 7 P17 P17 EA7 FA 7 73 A6 P16/A 6 P16 P16 EA6 FA 6 74 A5 P15/A 5 P15 P15 EA5 FA 5 75 A4 P14/A 4 P14 P14 EA4 FA 4 76 A3 P13/A 3 P13 P13 EA3 FA 3 77 A2 P12/A 2 P12 P12 EA2 FA 2 78 A1 P11/A 1 P11 P11 EA1 FA 1 79 A0 Pin No. Expanded Modes Single-Chip Mode Mode 3 P10/A 0 P10 P10 EA0 FA 0 PB3/XDB3 *2 PB3 PB3 NC NC PB2/XDB2 *2 PB2 PB2 NC NC PB3/XDB3 *2 81 PB2/XDB2 *2 82 D0 D0 P30 HDB0 EO0 FO0 83 D1 D1 P31 HDB1 EO1 FO1 84 D2 D2 P32 HDB2 EO2 FO2 85 D3 D3 P33 HDB3 EO3 FO3 86 D4 D4 P34 HDB4 EO4 FO4 87 D5 D5 P35 HDB5 EO5 FO5 88 D6 D6 P36 HDB6 EO6 FO6 89 D7 80 D7 PB1/XDB1 *2 91 PB0/XDB0 *2 92 VSS 90 93 94 95 96 10 P80/HA0 P37 HDB7 EO7 FO7 PB1/XDB1 *2 PB1 PB1 NC NC PB0/XDB0 *2 PB0 PB0 NC NC VSS VSS VSS VSS P80 HA 0 NC NC VSS *1 P81/GA 20 P82/CS 1 *1 *1 *1 P83/IOR P80/HA0 *1 P81/GA 20 P82/CS 1 *1 P81 P81/GA 20 NC NC *1 P82 CS 1 NC NC *1 P83 IOR NC NC P83/IOR Pin No. FP-100B, TFP-100B Expanded Modes Single-Chip Mode Mode 3 Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 97 P84/IRQ3/TxD1 when HIF is disabled or STAC bit is 1 in STCR; IOW/IRQ3 when HIF is enabled and STAC bit is 0 in STCR NC NC 98 P85/IRQ4/RxD1 when HIF is disabled or STAC bit is 1 in STCR; CS 2/IRQ4 when HIF is enabled and STAC bit is 0 in STCR NC NC 99 P86/SCK1/ IRQ5/SCL P86/SCK1/ IRQ5/SCL P86/SCK1/ IRQ5/SCL P86/SCK1/ IRQ5/SCL NC NC 100 RESO RESO RESO RESO NC NC Note: Pins marked NC should be left unconnected. For details on writer mode, refer to 18.2, Writer Mode, 19.6, Flash Memory Writer Mode (H8/3434F), 20.6, Flash Memory Writer Mode (H8/3437F) and 21.5, Flash Memory Writer Mode (H8/3437SF). In this chip, except for the S-mask model (single-power-supply specification), the same pin is used for STBY and FVPP . When this pin is driven low, a transition is made to hardware standby mode. This occurs not only in the normal operating modes (modes 1, 2, and 3), but also when programming flash memory with a PROM writer. When using a PROM programmer to program dual-power-supply flash memory, therefore, the PROM programmer specifications should provide for this pin to be held at the VCC level except when programming (FVPP = 12 V). *1 Differs as in mode 3, depending on whether the host interface is enabled or disabled. *2 XDB 7 to XDB6 can only be used when the host interface is enabled. 11 Pin Functions: Table 1.3 gives a concise description of the function of each pin. Table 1.3 Pin Functions Pin No. Type Symbol FP-100B, TFP-100B I/O Name and Function Power VCC 9, 59 I Power: Connected to the power supply. Connect both VCC pins to the system power supply. VCCB 4 I I/O buffer power supply: Power supply for input/output buffers at pins P8 6, P97, and PA4 to PA 7. VSS 15, 70, 71, 92 I Ground: Connected to ground (0 V). Connect all V SS pins to system ground (0 V). XTAL 2 I Crystal: Connected to a crystal oscillator. The crystal frequency should be the same as the desired system clock frequency. If an external clock is input at the EXTAL pin, a reverse-phase clock should be input at the XTAL pin. EXTAL 3 I External crystal: Connected to a crystal oscillator or external clock. The frequency of the external clock should be the same as the desired system clock frequency. See section 6.2, Oscillator Circuit, for examples of connections to a crystal and external clock. o 17 O System clock: Supplies the system clock to peripheral devices. RES 1 I Reset: A low input causes the chip to reset. RESO 100 O Reset output: Outputs a reset signal to external devices. STBY 8 I Standby: A transition to the hardware standby mode (a power-down state) occurs when a low input is received at the STBY pin. Address bus A15 to A 0 60 to 67, 72 to 79 O Address bus: Address output pins. Data bus D7 to D0 89 to 82 I/O Data bus: 8-bit bidirectional data bus. Clock System control 12 Pin No. Type Symbol FP-100B, TFP-100B I/O Name and Function Bus control WAIT 16 I Wait: Requests the CPU to insert wait states into the bus cycle when an external address is accessed. RD 22 O Read: Goes low to indicate that the CPU is reading an external address. WR 19 O Write: Goes low to indicate that the CPU is writing to an external address. AS 18 O Address strobe: Goes low to indicate that there is a valid address on the address bus. NMI 7 I Nonmaskable interrupt: Highest-priority interrupt request. The NMIEG bit in the system control register (SYSCR) determines whether the interrupt is recognized at the rising or falling edge of the NMI input. IRQ0 to IRQ7 23 to 25, 97 to 99, 34, 35 I Interrupt request 0 to 7: Maskable interrupt request pins. MD1 MD0 5 6 I Mode: Input pins for setting the MCU mode operating mode according to the table below. Interrupt signals Operating mode control MD1 MD0 Mode Description 0 0 Mode 0 Illegal setting * 0 1 Mode 1 Expanded mode with on-chip ROM disabled 1 0 Mode 2 Expanded mode with on-chip ROM enabled 1 1 Mode 3 Single-chip mode Note: * In the H8/3437SF (S-mask model, single-power-supply on-chip flash memory version), the settings MD1 = MD0 = 0 are used when boot mode is set. For details, see section 21.3, On-Board Programming Modes. Do not change the mode pin settings while the chip is operating. 13 Pin No. Type Symbol FP-100B, TFP-100B 16-bit freerunning timer (FRT) FTOA FTOB I/O Name and Function 27 34 O FRT output compare A and B: Output pins controlled by comparators A and B of the free-running timer. FTCI 26 I FRT counter clock input: Input pin for an external clock signal for the free-running timer. FTIA to FTID 28, 29, 32, 33 I FRT input capture A to D: Input capture pins for the free-running timer. TMO0 TMO1 50 53 O 8-bit timer output (channels 0 and 1): Compare-match output pins for the 8-bit timers. TMCI0 TMCI1 49 52 I 8-bit timer counter clock input (channels 0 and 1): External clock input pins for the 8bit timer counters. TMRI0 TMRI1 51 54 I 8-bit timer counter reset input (channels 0 and 1): A high input at these pins resets the 8-bit timer counters. PWM timer PW0 PW1 55 56 O PWM timer output (channels 0 and 1): Pulse-width modulation timer output pins. Serial communication interface (SCI) TxD0 TxD1 14 97 O Transmit data (channels 0 and 1): Data output pins for the serial communication interface. RxD0 RxD1 13 98 I Receive data (channels 0 and 1): Data input pins for the serial communication interface. SCK 0 SCK 1 12 99 I/O Serial clock (channels 0 and 1): Input/output pins for the serial clock. HDB0 to HDB7 82 to 89 I/O Host interface data bus: 8-bit bidirectional bus by which a host processor accesses the host interface. CS 1, CS 2 95, 98 I Chip select 1 and 2: Input pins for selecting host interface channels 1 and 2. IOR 96 I I/O read: Read strobe input pin for the host interface. IOW 97 I I/O write: Write strobe input pin for the host interface. 8-bit timer Host interface (HIF) 14 Pin No. Type Symbol FP-100B, TFP-100B I/O Name and Function Host interface (HIF) HA 0 93 I Command/data: Input pin indicating data access or command access. GA20 94 O Gate A20 : A 20 gate control signal output pin. HIRQ1 HIRQ11 HIRQ12 53 52 54 O Host interrupts 1, 11, and 12: Output pins for interrupt request signals to the host processor. Keyboard control KEYIN0 to KEYIN15 26 to 29, 32 to 35, 48, 47, 31, 30, 21, 20, 11, 10 I Keyboard input: Input pins from a matrix keyboard. (Keyboard scan signals are normally output from P1 0 to P1 7 and P20 to P27, allowing a maximum 16 x 16 key matrix. The number of keys can be further increased by use of other output ports.) Host interface (expanded modes) XDB 0 to XDB 7 91, 90, 81, 80, 69, 68, 58, 57 I/O Host interface data bus: 8-bit bidirectional bus by which a host processor accesses the host interface. Host interface (if enabled when STAC bit is 1 in STCR) ECS 2 25 I Host chip select 2: Input pin for selecting host interface channel 2. EIOW 24 I I/O write: Write strobe input pin for the host interface. A/D converter AN 7 to AN 0 38 to 45 I Analog input: Analog signal input pins for the A/D converter. ADTRG 25 I A/D trigger: External trigger input for starting the A/D converter. D/A converter DA 0 DA 1 44 45 O Analog output: Analog signal output pins for the D/A converter. A/D and D/A converters AVCC 37 I Analog reference voltage: Reference voltage pin for the A/D and D/A converters. If the A/D and D/A converters are not used, connect AVCC to the system power supply. AVSS 46 I Analog ground: Ground pin for the A/D and D/A converters. Connect to system ground (0 V). AVref 36 I Analog reference voltage: Analog reference voltage input pins for A/D and D/A converters. 15 Pin No. FP-100B, TFP-100B I/O Name and Function Flash memory FV PP [H8/3434, H8/3437 F-ZTAT] 8 I Programming power supply for on-board programming: Connect to a flash memory programming power supply (+12 V) I 2C bus interface [option] SCL 99 I/O I 2C clock I/O: Input/output pin for I2C clock. Power is supplied by I/O buffer power supply V CCB. Features a bus drive function. SDA 16 I/O I 2C data I/O: Input/output pin for I2C data. Power is supplied by I/O buffer power supply V CCB. Features a bus drive function. P17 to P1 0 72 to 79 I/O Port 1: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 1 data direction register (P1DDR). P27 to P2 0 60 to 67 I/O Port 2: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 2 data direction register (P2DDR). P37 to P3 0 89 to 82 I/O Port 3: An 8-bit input/output port with programmable MOS input pull-ups. The direction of each bit can be selected in the port 3 data direction register (P3DDR). P47 to P4 0 56 to 49 I/O Port 4: An 8-bit input/output port. The direction of each bit can be selected in the port 4 data direction register (P4DDR). P52 to P5 0 12 to 14 I/O Port 5: A 3-bit input/output port. The direction of each bit can be selected in the port 5 data direction register (P5DDR). P67 to P6 0 35 to 32, 29 to 26 I/O Port 6: An 8-bit input/output port with programming MOS input pull-ups. The direction of each bit can be selected in the port 6 data direction register (P6DDR). P77 to P7 0 45 to 38 I Port 7: An 8-bit input port. P86 to P8 0 99 to 93 I/O Port 8: A 7-bit input/output port. The direction of each bit can be selected in the port 8 data direction register (P8DDR). P86 is powered by I/O buffer power supply V CCB. Type I/O ports 16 Symbol Pin No. Type Symbol I/O ports P97 to P9 0 FP-100B, TFP-100B I/O Name and Function I/O Port 9: An 8-bit input/output port. The direction of each bit (except for P9 6) can be selected in the port 9 data direction register (P9DDR). P97 is powered by I/O buffer power supply V CCB. PA7 to PA 0 10, 11, 20, 21, 30, 31, 47, 48 I/O Port A: An 8-bit input/output port with programming MOS input pull-ups. The direction of each bit can be selected in the port A data direction register (PADDR). PA7 to PA4 are powered by I/O buffer power supply V CCB. Features a bus drive function. PB7 to PB 0 57, 58, 68, 69, 80, 81, 90, 91 I/O Port B: An 8-bit input/output port with programming MOS input pull-ups. The direction of each bit can be selected in the port B data direction register (PBDDR). 16 to 19, 22 to 25 Note: In this chip, except for the S-mask model (single-power-supply specification), the same pin is used for STBY and FVPP . When this pin is driven low, a transition is made to hardware standby mode. This occurs not only in the normal operating modes (modes 1, 2, and 3), but also when programming flash memory with a PROM writer. When using a PROM programmer to program dual-power-supply flash memory, therefore, the PROM programmer specifications should provide for this pin to be held at the VCC level except when programming (FVPP = 12 V). 17 18 Section 2 CPU 2.1 Overview The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 Features The main features of the H8/300 CPU are listed below. * Two-way register configuration Sixteen 8-bit general registers, or Eight 16-bit general registers * Instruction set with 57 basic instructions, including: Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment or pre-decrement (@Rn+ or @-Rn) Absolute address (@aa:8 or @aa:16) Immediate (#xx:8 or #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8) * Maximum 64-kbyte address space * High-speed operation All frequently-used instructions are executed in two to four states * Maximum clock rate (o clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V 8- or 16-bit register-register add or subtract: 125 ns (16 MHz), 167 ns (12 MHz), 200 ns (10 MHz) 8 x 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) 16 / 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) * Power-down mode SLEEP instruction 19 2.1.2 Address Space The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code and data combined. The memory map differs depending on the mode (mode 1, 2, or 3). For details, see section 3.4, Address Space Map in Each Operating Mode. 2.1.3 Register Configuration Figure 2.1 shows the internal register structure of the H8/300 CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 0 7 0 R0H R0L R1H R1L R2H R2L R3H R3L R4H R4L R5H R5L R6H R6L R7H (SP) SP: Stack pointer R7L Control registers 15 0 PC 7 6 5 4 3 2 1 0 CCR I U H U N Z V C PC: Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit Figure 2.1 CPU Registers 20 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers (R0H to R7H and R0L to R7L). R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As indicated in figure 2.2, R7 (SP) points to the top of the stack. Unused area SP (R7) Stack area Figure 2.2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the PC is ignored (always regarded as 0). (2) Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt mask bit (I). Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked. This bit is set to 1 automatically by a reset and at the start of interrupt handling. Bit 6--User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). 21 Bit 5--Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise. Similarly, it is set to 1 when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow out of bit 11, and cleared to 0 otherwise. It is used implicitly in the DAA and DAS instructions. Bit 4--User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 3--Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): This flag is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. Bit 1--Overflow Flag (V): This flag is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): This flag is used by: * Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result * Shift and rotate instructions, to store the value shifted out of the most significant or least significant bit * Bit manipulation and bit load instructions, as a bit accumulator The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in conditional branching instructions (BCC). For the action of each instruction on the flag bits, see the H8/300 Series Programming Manual. 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt mask bit (I) in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer and CCR should be initialized by software, by the first instruction executed after a reset. 22 2.3 Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. * All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. * The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. * The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. 23 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. Data Format 7 1-bit data RnH 7 0 6 5 4 3 2 1 0 Don't care 7 1-bit data Byte data Byte data Word data Don't care RnL RnH Rn 0 MSB LSB Don't care RnH 6 5 2 1 0 7 0 MSB LSB 0 MSB LSB 4 3 Upper digit 0 Lower digit Don't care Don't care RnL 4 Upper digit Legend: RnH: Upper digit of general register RnL: Lower digit of general register MSB: Most significant bit LSB: Least significant bit Figure 2.3 Register Data Formats 24 3 Don't care 7 4-bit BCD data 4 15 7 4-bit BCD data 7 7 RnL 0 0 3 Lower digit 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, no address error occurs but the access is performed at the preceding even address. This rule affects MOV.W instructions and branching instructions, and implies that only even addresses should be stored in the vector table. Data Type Address Data Format 7 1-bit data Address n 7 Byte data Address n MSB Even address MSB Word data Odd address Byte data (CCR) on stack Word data on stack 0 6 5 4 3 2 1 0 LSB Upper 8 bits Lower 8 bits LSB Even address MSB CCR LSB Odd address MSB CCR* LSB Even address MSB Odd address LSB Note: * Ignored on return Legend: CCR: Condition code register Figure 2.4 Memory Data Formats When the stack is addressed by register R7, it must always be accessed a word at a time. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. 25 2.4 Addressing Modes 2.4.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Addressing Mode Symbol (1) Register direct Rn (2) Register indirect @Rn (3) Register indirect with displacement @(d:16, Rn) (4) Register indirect with post-increment @Rn+ Register indirect with pre-decrement @-Rn (5) Absolute address @aa:8 or @aa:16 (6) Immediate #xx:8 or #xx:16 (7) Program-counter-relative @(d:8, PC) (8) Memory indirect @@aa:8 (1) Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. In most cases the general register is accessed as an 8-bit register. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. (2) Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) Register Indirect with Displacement--@(d:16, Rn): This mode, which is used only in MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. For the MOV.W instruction, the resulting address must be even. (4) Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with Post-Increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. The size of the increment is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. 26 * Register Indirect with Pre-Decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. The size of the decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. (5) Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx. The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to 65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. (6) Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) Program-Counter-Relative--@(d:8, PC): This mode is used to generate branch addresses in the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-extended value to the program counter contents. The result must be an even number. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to 255). The word located at this address contains the branch address. The upper 8 bits of the absolute address are 0 (H'00), thus the branch address is limited to values from 0 to 255 (H'0000 to H'00FF). Note that some of the addresses in this range are also used in the vector table. Refer to section 3.4, Address Space Map in Each Operating Mode. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information. 27 2.4.2 Calculation of Effective Address Table 2.2 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also use immediate addressing (6). The MOV instruction uses all the addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute (5) addressing to identify a byte operand, and 3-bit immediate addressing to identify a bit within the byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to identify the bit. 28 Table 2.2 Effective Address Calculation No. Addressing Mode and Instruction Format 1 Register direct, Rn Effective Address Calculation Effective Address 3 0 regm 15 87 op 2 43 regm regn Operands are contained in registers regm and regn 15 0 16-bit register contents 76 op 3 43 15 0 15 0 15 0 15 0 0 reg Register indirect with displacement, @(d:16, Rn) 15 0 16-bit register contents 15 0 regn 0 Register indirect, @Rn 15 3 76 op 43 0 reg disp disp 4 Register indirect with post-increment, @Rn+ 15 76 op 43 15 0 16-bit register contents 0 reg 1 or 2* Register indirect with pre-decrement, @-Rn 15 0 16-bit register contents 15 76 op 43 0 reg 1 or 2* Note: * 1 for a byte operand, 2 for a word operand 29 No. 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address Absolute address @aa:8 15 87 op 15 87 0 H'FF 0 abs @aa:16 15 15 0 0 op abs 6 Immediate #xx:8 Operand is 1- or 2-byte immediate data 15 87 op 0 IMM #xx:16 15 0 op IMM 7 15 PC-relative @(d:8, PC) 0 PC contents 15 15 87 op 30 0 disp Sign extension disp 0 No. Addressing Mode and Instruction Format 8 Memory indirect, @@aa:8 15 87 op Effective Address Calculation Effective Address 0 abs 15 87 0 H'00 15 0 Memory contents (16 bits) Legend: reg: General register op: Operation code disp: Displacement IMM: Immediate data abs: Absolute address 31 2.5 Instruction Set The H8/300 CPU has 57 types of instructions, which are classified by function in table 2.3. Table 2.3 Instruction Classification Function Instructions Types *3 *3 *1 *1 Data transfer MOV, MOVTPE , MOVFPE , PUSH , POP 3 Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG 14 Logic operations AND, OR, XOR, NOT 4 Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 14 Branch Bcc*2, JMP, BSR, JSR, RTS 5 System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8 Block data transfer EEPMOV 1 Total 57 Notes: *1 PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. *2 Bcc is a conditional branch instruction in which cc represents a condition code. *3 Not supported by the H8/3437 Series. 32 The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. Operation Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand SP Stack pointer PC Program counter CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR #imm Immediate data #xx:3 3-bit immediate data #xx:8 8-bit immediate data #xx:16 16-bit immediate data disp Displacement + Addition - Subtraction x Multiplication / Division AND logical OR logical Exclusive OR logical Move Not 33 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. MOVTPE B Not supported by the H8/3437 Series. MOVFPE B Not supported by the H8/3437 Series. PUSH W Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. Note: * Size: Operand size B: Byte W: Word 34 15 8 7 op 0 rm 15 8 rn 0 rm 15 8 RmRn 7 op rn @RmRn 7 op MOV 0 rm rn @(d:16, Rm)Rn disp 15 8 7 op rm 15 8 op 0 7 rn 15 @Rm+Rn, or Rn@-Rm rn 0 abs 8 @aa:8Rn 7 0 op rn @aa:16Rn abs 15 8 op 7 rn 15 0 IMM 8 #xx:8Rn 7 0 op rn #xx:16Rn IMM 15 8 7 op 0 rn MOVFPE, MOVTPE abs 15 8 op 7 0 rn POP, PUSH Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer Instruction Codes 35 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. See figure 2.6 in section 2.5.4, Shift Operations, for their object codes. Table 2.5 Arithmetic Instructions Instruction Size* Function ADD B/W Rd Rs Rd, Rd + #imm Rd SUB ADDX Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. B SUBX INC Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. B DEC ADDS W Rd #imm Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. B DAS MULXU Rd #1 Rd Increments or decrements a general register. SUBS DAA Rd Rs C Rd, Rd #imm C Rd Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR. B Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. DIVXU B Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. CMP B/W Rd - Rs, Rd - #imm Compares data in a general register with data in another general register or with immediate data. Word data can be compared only between two general registers. NEG B 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register. Note: * Size: Operand size B: Byte W: Word 36 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. See figure 2.6 in section 2.5.4, Shift Operations, for their object codes. Table 2.6 Logic Operation Instructions Instruction Size* Function AND B Rd Rs Rd, Rd #imm Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B Rd Rs Rd, Rd #imm Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B Rd Rs Rd, Rd #imm Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT B (Rd) (Rd) Obtains the one's complement (logical complement) of general register contents. Note: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2.7 describes the eight shift instructions. Figure 2.6 shows the object code formats of the arithmetic, logic, and shift instructions. Table 2.7 Shift Instructions Instruction Size* Function SHAL B Rd shift Rd SHAR SHLL Performs an arithmetic shift operation on general register contents. B SHLR ROTL Performs a logical shift operation on general register contents. B ROTR ROTXL Rd shift Rd Rd rotate Rd Rotates general register contents. B ROTXR Rd rotate through carry Rd Rotates general register contents through the C (carry) bit. Note: * Size: Operand size B: Byte 37 15 8 7 op 0 rm 15 8 7 0 op 15 7 op 0 rm 8 op rn 7 MULXU, DIVXU 0 rn ADD, ADDX, SUBX, CMP (#xx:8) IMM 15 8 7 op 0 rm 15 8 op ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT rn 8 15 ADD, SUB, CMP, ADDX, SUBX (Rm) rn 7 rn 15 AND, OR, XOR (Rm) 0 IMM 8 op rn AND, OR, XOR (#xx:8) 7 0 rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Legend: Operation field op: rm, rn: Register field IMM: Immediate data Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes 38 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 (<bit no.> of <EAd>) Sets a specified bit in a general register or memory to 1. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BCLR B 0 (<bit no.> of <EAd>) Clears a specified bit in a general register or memory to 0. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BNOT B (<bit no.> of <EAd>) (<bit no.> of <EAd>) Inverts a specified bit in a general register or memory. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BTST B (<bit no.> of <EAd>) Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly. The bit is specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BAND B C (<bit no.> of <EAd>) C ANDs the C flag with a specified bit in a general register or memory. C [ (<bit no.> of <EAd>)] C BIAND ANDs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BOR B C (<bit no.> of <EAd>) C ORs the C flag with a specified bit in a general register or memory. C [ (<bit no.> of <EAd>)] C BIOR ORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BXOR B C (<bit no.> of <EAd>) C XORs the C flag with a specified bit in a general register or memory. Note: * Size: Operand size B: Byte 39 Instruction Size* Function BIXOR B C [(<bit no.> of <EAd>)] C XORs the C flag with the inverse of a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. BLD (<bit no.> of <EAd>) C B Copies a specified bit in a general register or memory to the C flag. (<bit no.> of <EAd>) C BILD Copies the inverse of a specified bit in a general register or memory to the C flag. The bit number is specified by 3-bit immediate data. BST C (<bit no.> of <EAd>) B Copies the C flag to a specified bit in a general register or memory. C (<bit no.> of <EAd>) BIST Copies the inverse of the C flag to a specified bit in a general register or memory. The bit number is specified by 3-bit immediate data. Note: * Size: Operand size B: Byte Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are readmodify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied to registers with write-only bits and to the I/O port registers. Step Description 1 Read Read one data byte at the specified address 2 Modify Modify one bit in the data byte 3 Write Write the modified data byte back to the specified address Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under the following conditions. P4 7: Input pin, low P4 6: Input pin, high P4 5 - P4 0: Output pins, low The intended purpose of this BCLR instruction is to switch P40 from output to input. 40 Before Execution of BCLR Instruction P47 P46 P45 P44 P43 P42 P41 P40 Input/output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low DDR 0 0 1 1 1 1 1 1 DR 1 0 0 0 0 0 0 0 Execution of BCLR Instruction BCLR ; clear bit 0 in data direction register #0, @P4DDR After Execution of BCLR Instruction P47 P46 P45 P44 P43 P42 P41 P40 Input/output Output Output Output Output Output Output Output Input Pin state Low High Low Low Low Low Low High DDR 1 1 1 1 1 1 1 0 DR 1 0 0 0 0 0 0 0 Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction. As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR are set to 1, making P4 7 and P46 output pins. 41 BSET, BCLR, BNOT, BTST 15 8 7 op 0 IMM 15 8 7 op 0 rm 15 8 Operand: register direct (Rn) Bit no.: immediate (#xx:3) rn Operand: register direct (Rn) Bit no.: register direct (Rm) rn 7 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit no.: op rn 0 0 0 0 Operand: register indirect (@Rn) op rm 0 0 0 0 Bit no.: op op 15 8 15 8 7 0 7 abs IMM 15 8 0 Operand: absolute (@aa:8) 0 0 7 0 Bit no.: immediate (#xx:3) 0 op abs op register direct (Rm) 0 op op immediate (#xx:3) rm 0 Operand: absolute (@aa:8) 0 0 0 Bit no.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 op 0 IMM 15 8 7 op op 15 8 Operand: register direct (Rn) Bit no.: immediate (#xx:3) rn 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit no.: 7 0 op abs op IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit no.: Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes 42 immediate (#xx:3) immediate (#xx:3) BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 op 0 IMM 15 8 7 op op 15 8 Operand: register direct (Rn) Bit no.: immediate (#xx:3) rn 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit no.: 7 0 op abs op immediate (#xx:3) IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit no.: immediate (#xx:3) Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont) 43 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function Bcc -- Branches if condition cc is true. Mnemonic cc field Description Condition BRA (BT) 0000 Always (true) Always BRN (BF) 0001 Never (false) Never BHI 0010 High CZ=0 BLS 0011 Low or same CZ=1 BCC (BHS) 0100 Carry clear (High or same) C=0 BCS (BLO) 0101 Carry set (low) C=1 BNE 0110 Not equal Z=0 BEQ 0111 Equal Z=1 BVC 1000 Overflow clear V=0 BVS 1001 Overflow set V=1 BPL 1010 Plus N=0 BMI 1011 Minus N=1 BGE 1100 Greater or equal NV=0 BLT 1101 Less than NV=1 BGT 1110 Greater than Z (N V) = 0 BLE 1111 Less or equal Z (N V) = 1 JMP -- Branches unconditionally to a specified address. JSR -- Branches to a subroutine at a specified address. BSR -- Branches to a subroutine at a specified displacement from the current address. RTS -- Returns from a subroutine. 44 15 8 op 7 0 cc 15 disp 8 7 op 0 rm 15 Bcc 8 0 0 0 7 0 JMP (@Rm) 0 op JMP (@aa:16) abs 15 8 7 0 op abs 15 8 JMP (@@aa:8) 7 0 op disp 15 8 7 op 0 rm 15 BSR 8 0 0 0 7 0 JSR (@Rm) 0 op JSR (@aa:16) abs 15 8 7 op 0 abs 15 8 7 op JSR (@@aa:8) 0 RTS Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes 45 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* Function RTE -- Returns from an exception-handling routine. SLEEP -- Causes a transition to the power-down state. LDC B Rs CCR, #imm CCR Moves immediate data or general register contents to the condition code register. STC CCR Rd B Copies the condition code register to a specified general register. ANDC CCR #imm CCR B Logically ANDs the condition code register with immediate data. ORC CCR #imm CCR B Logically ORs the condition code register with immediate data. XORC CCR #imm CCR B Logically exclusive-ORs the condition code register with immediate data. NOP PC + 2 PC -- Only increments the program counter. Note: * Size: Operand size B: Byte 15 8 7 0 op 15 8 RTE, SLEEP, NOP 7 0 op 15 rn 8 op 7 LDC, STC (Rn) 0 IMM ANDC, ORC, XORC, LDC (#xx:8) Legend: op: Operation field rn: Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 46 2.5.8 Block Data Transfer Instruction Table 2.11 describes the EEPMOV instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction/EEPROM Write Operation Instruction Size Function EEPMOV -- if R4L 0 then repeat @R5+ @R6+ R4L - 1 R4L until R4L = 0 else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: size of block (bytes) R5: starting source address R6: starting destination address Execution of the next instruction starts as soon as the block transfer is completed. 15 8 7 0 op op Legend: op: Operation field Figure 2.10 Block Data Transfer Instruction/EEPROM Write Operation Code 47 Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L R6 + R4L 2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R5 + R4L R6 H'FFFF Not allowed 48 R6 + R4L 2.6 CPU States 2.6.1 Overview The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: sleep mode, software standby mode, and hardware standby mode. Figure 2.11 summarizes these states, and figure 2.12 shows a map of the state transitions. State Program execution state The CPU executes successive program instructions. Exception-handling state A transient state triggered by a reset or interrupt. The CPU executes a hardware sequence that includes loading the program counter from the vector table. Sleep mode Power-down state A state in which some or all of the chip functions are stopped to conserve power. Software standby mode Hardware standby mode Figure 2.11 Operating States 49 Exception handling request Program execution state Exception handing Exceptionhandling state RES = 1 Reset state Interrupt request NMI, IRQ0 to IRQ2 or IRQ6 STBY = 1, RES = 0 SLEEP instruction with SSBY bit set SLEEP instruction Sleep mode Software standby mode Hardware standby mode Power-down state Notes: 1. A transition to the reset state occurs when RES goes low, except when the chip is in the hardware standby mode. 2. A transition from any state to the hardware standby mode occurs when STBY goes low. Figure 2.12 State Transitions 2.6.2 Program Execution State In this state the CPU executes program instructions. 2.6.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU is reset or interrupted and changes its normal processing flow. In interrupt exception handling, the CPU references the stack pointer (R7) and saves the program counter and condition code register on the stack. For further details see section 4, Exception Handling. 50 2.6.4 Power-Down State The power-down state includes three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to function. Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized, but the contents of the on-chip RAM and CPU registers remain unchanged as long as a specified voltage is supplied. I/O port outputs also remain unchanged. Hardware Standby Mode: Is entered when the input at the STBY pin goes low. All chip functions halt, including I/O port output. The on-chip supporting modules are initialized, but onchip RAM contents are held. See section 22, Power-Down State, for further information. 2.7 Access Timing and Bus Cycle The CPU is driven by the system clock (o). The period from one rising edge of the system clock to the next is referred to as a "state." Memory access is performed in a two- or three-state bus cycle. On-chip memory, on-chip supporting modules, and external devices are accessed in different bus cycles as described below. 2.7.1 Access to On-Chip Memory (RAM and ROM) On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or word data can be accessed, via a 16-bit data bus. Figure 2.13 shows the on-chip memory access cycle. Figure 2.14 shows the associated pin states. 51 Bus cycle T2 state T1 state o Address Internal address bus Internal read signal Read data Internal data bus (read) Internal write signal Internal data bus (write) Write data Figure 2.13 On-Chip Memory Access Cycle Bus cycle T2 state T1 state o Address bus Address AS: High RD: High WR: High Data bus: high impedance state Figure 2.14 Pin States during On-Chip Memory Access Cycle 52 2.7.2 Access to On-Chip Register Field and External Devices The on-chip supporting module registers and external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes requires two consecutive cycles (six states). Figure 2.15 shows the access cycle for the on-chip register field. Figure 2.16 shows the associated pin states. Figures 2.17 (a) and (b) show the read and write access timing for external devices. Bus cycle T1 state T2 state T3 state o Internal address bus Address Internal read signal Internal data bus (read) Read data Internal write signal Internal data bus (write) Write data Figure 2.15 On-Chip Register Field Access Cycle 53 Bus cycle T1 state T2 state T3 state o Address Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 2.16 Pin States during On-Chip Register Field Access Cycle Read cycle T1 state T2 state T3 state o Address bus Address AS RD WR: High Data bus Read data Figure 2.17 (a) External Device Access Timing (Read) 54 Write cycle T1 state T2 state T3 state o Address bus Address AS RD: High WR Data bus Write data Figure 2.17 (b) External Device Access Timing (Write) 55 56 Section 3 MCU Operating Modes and Address Space 3.1 Overview 3.1.1 Mode Selection The H8/3437 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD1 and MD 0). See table 3.1. Table 3.1 Operating Modes Mode MD1 MD0 Address Space On-Chip ROM On-Chip RAM Mode 0 Low Low -- -- -- Mode 1 Low High Expanded Disabled Enabled* Mode 2 High Low Expanded Enabled Enabled* Mode 3 High High Single-chip Enabled Enabled Note: * If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory can be accessed instead. Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices. The maximum address space supported by these externally expanded modes is 64 kbytes. In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are used. All ports are available for general-purpose input and output. Mode 0 is inoperative in the H8/3437 Series. Avoid setting the mode pins to mode 0, and do not change the mode pin settings while the chip is operating. 3.1.2 Mode and System Control Registers Table 3.2 lists the registers related to the chip's operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins MD1 and MD 0. Table 3.2 Mode and System Control Registers Name Abbreviation Read/Write Address System control register SYSCR R/W H'FFC4 Mode control register MDCR R H'FFC5 57 3.2 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R R/W R/W R/W The system control register (SYSCR) is an 8-bit register that controls the operation of the chip. Bit 7--Software Standby (SSBY): Enables transition to the software standby mode. For details, see section 22, Power-Down State. On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1. It can be cleared by writing 0. Bit 7: SSBY Description 0 The SLEEP instruction causes a transition to sleep mode. 1 The SLEEP instruction causes a transition to software standby mode. (Initial value) Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip supporting modules continue to stand by. These bits should be set according to the clock frequency so that the settling time is at least 8 ms. For specific settings, see section 22.3.3, Clock Settling Time for Exit from Software Standby Mode. * ZTAT and Mask ROM Versions Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description 0 0 0 Settling time = 8,192 states 1 Settling time = 16,384 states 0 Settling time = 32,768 states 1 Settling time = 65,536 states 0 -- Settling time = 131,072 states 1 -- Unused 1 1 58 (Initial value) * F-ZTAT Version Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description 0 0 0 Settling time = 8,192 states 1 Settling time = 16,384 states 0 Settling time = 32,768 states 1 Settling time = 65,536 states 0 Settling time = 131,072 states 1 Settling time = 1,024 states -- Unused 1 1 0 1 (Initial value) Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted. If a period exceeding op/1,024 (e.g. op/2,048) is specified when selecting the 8-bit timer, PWM timer, or watchdog timer clock, the counter in the timer will not count up normally when 1,024 states is specified for the settling time. To avoid this problem, set the STS value just before the transition to software standby mode (before executing the SLEEP instruction), and re-set the value of STS2 to STS0 to a value from 000 to 100 directly after software standby mode is cleared by an interrupt. Bit 3--External Reset (XRST): Indicates the source of a reset. A reset can be generated by input of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used. XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. Bit 3: XRST Description 0 Reset was caused by watchdog timer overflow. 1 Reset was caused by external input. (Initial value) Bit 2--NMI Edge (NMIEG): Selects the valid edge of the NMI input. Bit 2: NMIEG Description 0 An interrupt is requested on the falling edge of the NMI input. 1 An interrupt is requested on the rising edge of the NMI input. (Initial value) Bit 1--Host Interface Enable (HIE): Enables or disables the host interface function. When enabled, the host interface processes host-slave data transfers, operating in slave mode. Bit 1: HIE Description 0 The host interface is disabled. 1 The host interface is enabled (slave mode). (Initial value) 59 Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by a reset, but is not initialized in the software standby mode. Bit 0: RAME Description 0 The on-chip RAM is disabled. 1 The on-chip RAM is enabled. 3.3 (Initial value) Mode Control Register (MDCR) Bit 7 *1 EXPE Initial value Read/Write *2 -- *2 R/W 6 5 4 3 2 1 0 -- -- -- -- -- MDS1 MDS0 *2 1 1 0 0 1 -- -- -- -- -- -- R --* 2 R Notes: *1 H8/3437SF (S-mask model, single-power-supply on-chip flash memory version) only. Otherwise, this is a reserved bit that is always read as 1. *2 Determined by the mode pins (MD1 and MD0). The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the chip. Bit 7--Expanded Mode Enable (EXPE): Functions only in the H8/3437SF (S-mask model, single-power-supply on-chip flash memory version). For details, see section 21.1.6, Mode Control Register (MDCR). In models other than the H8/3437SF, this is a reserved bit that cannot be modified and is always read as 1. Bits 6 and 5--Reserved: These bits cannot be modified and are always read as 1. Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 0. Bit 2--Reserved: This bit cannot be modified and is always read as 1. Bits 1 and 0--Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the mode pins (MD1 and MD0), thereby indicating the current operating mode of the chip. MDS1 corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode control register is read, the levels at the mode pins (MD1 and MD 0) are latched in these bits. 60 3.4 Address Space Map in Each Operating Mode Figures 3.1 and 3.2 show memory maps of the H8/3437, H8/3436, and H8/3434 in modes 1, 2, and 3. Mode 1 Expanded Mode without On-Chip ROM H'0000 Mode 2 Expanded Mode with On-Chip ROM H'0000 Mode 3 Single-Chip Mode H'0000 Vector table Vector table H'004B H'004C H'004B H'004C Vector table H'004B H'004C On-chip ROM 61,312 bytes On-chip ROM 63,360 bytes External address space H'EF7F H'EF80 External address space H'F77F H'F780 H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'FF7F H'FF80 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF On-chip RAM, 2,048 bytes H'FF7F H'FF88 On-chip register field H'FFFF Note: * External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0. Figure 3.1 H8/3437 Address Space Map 61 Mode 1 Expanded Mode without On-Chip ROM H'0000 Mode 2 Expanded Mode with On-Chip ROM H'0000 Vector table Mode 3 Single-Chip Mode H'0000 Vector table H'004B H'004C H'004B H'004C Vector table H'004B H'004C On-chip ROM 49,152 bytes On-chip ROM 49,152 bytes External address space H'BFFF H'C000 H'BFFF H'C000 Reserved*1 Reserved*1 H'EF7F H'EF80 External address space H'F77F H'F780 H'F77F H'F780 On-chip RAM *2 , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip RAM *2 , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF On-chip RAM 2,048 bytes H'FF7F H'FF88 On-chip register field H'FFFF Notes: *1 Do not access reserved areas. *2 External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0. Figure 3.2 H8/3436 Address Space Map 62 Mode 1 Expanded Mode without On-Chip ROM H'0000 Mode 2 Expanded Mode with On-Chip ROM H'0000 Vector table Mode 3 Single-Chip Mode H'0000 Vector table H'004B H'004C H'004B H'004C Vector table H'004B H'004C On-chip ROM 32,768 bytes On-chip ROM 32,768 bytes External address space H'7FFF H'8000 H'7FFF H'8000 Reserved*1 Reserved*1 H'EF7F H'EF80 External address space H'F77F H'F780 Reserved*1, *2 H'FB7F H'FB80 H'F77F H'F780 H'F77F H'F780 On-chip RAM *2 , 1,024 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF Reserved*1, *2 H'FB7F H'FB80 On-chip RAM *2 , 1,024 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF Reserved*1 H'FB80 H'FF7F On-chip RAM 1,024 bytes H'FF88 On-chip register field H'FFFF Notes: *1 Do not access reserved areas. *2 External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0. Figure 3.3 H8/3434 Address Space Map 63 64 Section 4 Exception Handling 4.1 Overview The H8/3437 Series recognizes two kinds of exceptions: interrupts and the reset. Table 4.1 indicates their priority and the timing of their hardware exception-handling sequence. Table 4.1 Hardware Exception-Handling Sequences and Priority Priority Type of Exception Detection Timing Timing of Exception-Handling Sequence High Reset Synchronized with clock The hardware exception-handling sequence begins as soon as RES changes from low to high. Interrupt End of instruction execution* When an interrupt is requested, the hardware exception-handling sequence begins at the end of the current instruction, or at the end of the current hardware exception-handling sequence. Low Note: * Not detected after ANDC, ORC, XORC, and LDC instructions. 4.2 Reset 4.2.1 Overview A reset has the highest exception-handling priority. When the RES pin goes low or when there is a watchdog timer reset (when the reset option is selected for watchdog timer overflow), all current processing stops and the chip enters the reset state. The internal state of the CPU and the registers of the on-chip supporting modules are initialized. The reset exception-handling sequence starts when RES returns from low to high, or at the end of a watchdog reset pulse. 4.2.2 Reset Sequence The reset state begins when RES goes low or a watchdog reset is generated. To ensure correct resetting, at power-on the RES pin should be held low for at least 20 ms. In a reset during operation, the RES pin should be held low for at least 10 system clock cycles. The watchdog reset pulse width is always 518 system clocks. For the pin states during a reset, see appendix D, Pin States. 65 The following sequence is carried out when reset exception handling begins. 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit in the condition code register (CCR) is set to 1. 2. The CPU loads the program counter with the first word in the vector table (stored at addresses H'0000 and H'0001) and starts program execution. The RES pin should be held low when power is switched off, as well as when power is switched on. Figure 4.1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4.2 indicates the timing in mode 1. Vector fetch Internal Instruction processing prefetch RES/watchdog timer reset (internal) o Internal address bus (1) (2) Internal read signal Internal write signal Internal data bus (16 bits) (2) (3) (1) Reset vector address (H'0000) (2) Starting address of program (3) First instruction of program Figure 4.1 Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM) 66 Figure 4.2 Reset Sequence (Mode 1) 67 D7 to D0 (8 bits) WR RD A15 to A0 o (1), (3) (2), (4) (5), (7) (6), (8) RES/watchdog timer reset (internal) (4) (3) (6) (5) (8) (7) Instruction prefetch Reset vector address: (1) = H'0000, (3) = H'0001 Starting address of program (contents of reset vector): (2) = upper byte, (4) = lower byte Starting address of program: (5) = (2) (4), (7) = (2) (4) + 1 First instruction of program: (6) = first byte, (8) = second byte (2) (1) Vector fetch Internal processing 4.2.3 Disabling of Interrupts after Reset After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program crash. To prevent this, all interrupts, including NMI, are disabled immediately after a reset. The first program instruction is therefore always executed. This instruction should initialize the stack pointer (example: MOV.W #xx:16, SP). After reset exception handling, in order to initialize the contents of CCR, a CCR manipulation instruction can be executed before an instruction to initialize the stack pointer. Immediately after execution of a CCR manipulation instruction, all interrupts including NMI are disabled. Use the next instruction to initialize the stack pointer. 4.3 Interrupts 4.3.1 Overview The interrupt sources include nine external sources from 23 input pins (NMI, IRQ0 to IRQ7, and KEYIN0 to KEYIN15), and 26 internal sources in the on-chip supporting modules. Table 4.2 lists the interrupt sources in priority order and gives their vector addresses. When two or more interrupts are requested, the interrupt with highest priority is served first. The features of these interrupts are: * NMI has the highest priority and is always accepted. All internal and external interrupts except NMI can be masked by the I bit in the CCR. When the I bit is set to 1, interrupts other than NMI are not accepted. * IRQ0 to IRQ7 can be sensed on the falling edge of the input signal, or level-sensed. The type of sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the rising or falling edge can be selected. * All interrupts are individually vectored. The software interrupt-handling routine does not have to determine what type of interrupt has occurred. * IRQ6 is multiplexed with 16 external sources (KEYIN0 to KEYIN15). KEYIN0 to KEYIN15 can be masked individually by user software. * The watchdog timer can generate either an NMI or overflow interrupt, depending on the needs of the application. For details, see section 11, Watchdog Timer. 68 Table 4.2 Interrupts Interrupt source No. Vector Table Address Priority NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 3 4 5 6 7 8 9 10 11 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 High 16-bit free-running timer ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) 12 13 14 15 16 17 18 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 8-bit timer 0 CMI0A (Compare-match A) CMI0B (Compare-match B) OVI0 (Overflow) 19 20 21 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B 8-bit timer 1 CMI1A (Compare-match A) CMI1B (Compare-match B) OVI1 (Overflow) 22 23 24 H'002C to H'002D H'002E to H'002F H'0030 to H'0031 Host interface IBF1 (IDR1 receive end) IBF2 (IDR2 receive end) 25 26 H'0032 to H'0033 H'0034 to H'0035 Serial communication interface 0 ERI0 (Receive error) RXI0 (Receive end) TXI0 (TDR empty) TEI0 (TSR empty) 27 28 29 30 H'0036 to H'0037 H'0038 to H'0039 H'003A to H'003B H'003C to H'003D Serial communication interface 1 ERI1 (Receive error) RXI1 (Receive end) TXI1 (TDR empty) TEI1 (TSR empty) 31 32 33 34 H'003E to H'003F H'0040 to H'0041 H'0042 to H'0043 H'0044 to H'0045 A/D converter ADI (Conversion end) 35 H'0046 to H'0047 Watchdog timer WOVF (WDT overflow) 36 H'0048 to H'0049 IICI (Transfer end) 37 H'004A to H'004B 2 I C bus interface Low Notes: 1. H'0000 and H'0001 contain the reset vector. 2. H'0002 to H'0005 are reserved in the H8/3437 Series and are not available to the user. 69 4.3.2 Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask registers (KMIMR and KMIMRA). Table 4.3 Registers Read by Interrupt Controller Name Abbreviation Read/Write Address System control register SYSCR R/W H'FFC4 IRQ sense control register ISCR R/W H'FFC6 IRQ enable register IER R/W H'FFC7 Keyboard matrix interrupt mask register KMIMR R/W H'FFF1 Keyboard matrix interrupt mask register A KMIMRA R/W H'FFF3 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R R/W R/W R/W The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register. Bit 2--NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the falling or rising edge of the NMI input signal. Bit 2: NMIEG Description 0 An interrupt is generated on the falling edge of NMI. 1 An interrupt is generated on the rising edge of NMI. (Initial state) See section 3.2, System Control Register, for information on the other SYSCR bits. IRQ Sense Control Register (ISCR) Bit 7 6 5 4 3 2 1 0 IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 70 Bits 7 to 0--IRQ7 to IRQ0 Sense Control (IRQ7SC to IRQ0SC): These bits determine whether IRQ7 to IRQ0 are level-sensed or sensed on the falling edge. Bits 7 to 0: IRQ7SC to IRQ0SC Description 0 An interrupt is generated when IRQ7 to IRQ0 inputs are low. (Initial state) 1 An interrupt is generated by the falling edge of the IRQ7 to IRQ0 inputs. IRQ Enable Register (IER) Bit Initial value R/W 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 to 0--IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable the IRQ7 to IRQ0 interrupts individually. Bits 7 to 0: IRQ7E to IRQ0E Description 0 IRQ7 to IRQ 0 interrupt requests are disabled. 1 IRQ7 to IRQ 0 interrupt requests are enabled. (Initial state) When edge sensing is selected (by setting bits IRQ7SC to IRQ0SC to 1), it is possible for an interrupt-handling routine to be executed even though the corresponding enable bit (IRQ7E to IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit (IRQ7E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is cleared to 0 while the request is still pending, the request will remain pending, although new requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the interrupt-handling routine can be executed even though the enable bit is now 0. If execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically when execution jumps to an interrupt vector. 2. Clear the desired bits from IRQ7E to IRQ0E to 0 to disable new interrupt requests. 3. Clear the corresponding IRQ7SC to IRQ0SC bits to 0, then set them to 1 again. Pending IRQn interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0. 71 Keyboard Matrix Interrupt Mask Register (KMIMR) To control interrupts from a 16 x 16 matrix keyboard at key-sense input pins KEYIN0 to KEYIN15, there are two keyboard matrix interrupt mask registers, KMIMR and KMIMRA. Bits KMIMR7 to KMIMR0 in KMIMR correspond to key-sense inputs KEYIN7 to KEYIN0. Bits KMIMR15 to KMIMR8 in KMIMRA correspond to key-sense inputs KEYIN15 to KEYIN8. Initially, the KMIMR6 bit that corresponds to the IRQ6/KEYIN6 pin is in the interrupt-enabled state, and the other interrupt mask bits are in the interrupt-disabled state. KMIMR is an 8-bit readable/writable register used in keyboard matrix scanning and sensing. This register initializes to a state in which only the input at the IRQ6 pin is enabled. To enable keysense input interrupts from two or more pins during keyboard scanning and sensing, clear the corresponding mask bits to 0. Bit 7 6 5 4 3 2 1 0 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value 1 0 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 to 0--Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control key-sense input interrupt requests KEYIN7 to KEYIN0. Bits 7 to 0: KMIMR7 to KMIMR0 Description 0 Key-sense input interrupt request is enabled. 1 Key-sense input interrupt request is disabled. (Initial value)* Note: * Except KMIMR6, which is initially 0. Bit 7 6 5 4 3 2 KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 1 0 KMIMR9 KMIMR8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 to 0--Keyboard Matrix Interrupt Mask (KMIMR15 to KMIMR8): These bits control key-sense input interrupt requests KEYIN15 to KEYIN8. Bits 7 to 0: KMIMR15 to KMIMR8 Description 0 Key-sense input interrupt request is enabled. 1 Key-sense input interrupt request is disabled. 72 (Initial value) Figure 4.3 shows the relationship between the IRQ6 interrupt, KMIMR, and KMIMRA. KMIMR0 (1) P60/KEYIN0 .. .. .. .. IRQ6 internal signal KMIMR6 (0) P66/KEYIN6/IRQ6 Edge/level select and enable/ disable control KMIMR7 (1) P67/KEYIN7 IRQ6E KMIMR8 (1) PA0/KEYIN8 .. .. IRQ6 interrupt IRQ6SC .. .. KMIMR15 (1) PA7/KEYIN15 Initial values are given in parentheses Figure 4.3 KMIMR, KMIMRA, and IRQ6 Interrupt 73 4.3.3 External Interrupts The nine external interrupts are NMI and IRQ0 to IRQ7. NMI, IRQ 0, IRQ1, IRQ2, and IRQ6 can be used to recover from software standby mode. NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected by the NMIEG bit in the system control register. The NMI vector number is 3. In the NMI hardware exception-handling sequence the I bit in the CCR is set to 1. IRQ0 to IRQ7: These interrupt signals are level-sensed or sensed on the falling edge of the input, as selected by ISCR bits IRQ0SC to IRQ7SC. These interrupts can be masked collectively by the I bit in the CCR, and can be enabled and disabled individually by setting and clearing bits IRQ0E to IRQ7E in the IRQ enable register. The IRQ6 input signal can be logically ORed internally with the key sense input signals. When KEYIN0 to KEYIN15 pins (P6 0 to P67 and PA0 to PA7) are used for key sense input, the corresponding KMIMR bits should be cleared to 0 to enable the corresponding key sense input interrupts. KMIMR bits corresponding to unused key sense inputs should be set to 1 to disable the interrupts. All 16 key sense interrupts are combined into a single IRQ6 interrupt. When one of these interrupts is accepted, the I bit is set to 1. IRQ0 to IRQ7 have interrupt vector numbers 4 to 11. They are prioritized in order from IRQ 7 (low) to IRQ0 (high). For details, see table 4.2. Interrupts IRQ 0 to IRQ7 do not depend on whether pins IRQ0 to IRQ7 are input or output pins. When using external interrupts IRQ0 to IRQ7, clear the corresponding DDR bits to 0 to set these pins to the input state, and do not use these pins as input or output pins for the timers, serial communication interface, I2C bus interface, host interface, or A/D converter. 4.3.4 Internal Interrupts Twenty-six internal interrupts can be requested by the on-chip supporting modules. Each interrupt source has its own vector number, so the interrupt-handling routine does not have to determine which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to 1. When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except NMI). The vector numbers are 12 to 37. For the priority order, see table 4.2. 74 4.3.5 Interrupt Handling Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the CPU to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. Figure 4.4 shows a block diagram of the interrupt controller. Interrupt controller NMI interrupt IRQ0 flag IRQ0E CPU * Interrupt request IRQ0 interrupt Priority decision Vector number IRIC IEIC IICI interrupt I (CCR) Note: * For edge-sensed interrupts, these AND gates change to the circuit shown below. IRQ0 edge IRQ0E IRQ0 flag S Q IRQ0 interrupt Figure 4.4 Block Diagram of Interrupt Controller The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected for a watchdog timer overflow) all have corresponding enable bits. When the enable bit is cleared to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These interrupts can also all be masked by setting the CPU's interrupt mask bit (I) to 1. Accordingly, these interrupts are accepted only when their enable bit is set to 1 and the I bit is cleared to 0. The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware standby mode. 75 When an NMI or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the CPU and indicates the corresponding vector number. (When two or more interrupts are requested, the interrupt controller selects the vector number of the interrupt with the highest priority.) When notified of an interrupt request, at the end of the current instruction or current hardware exception-handling sequence, the CPU starts the hardware exception-handling sequence for the interrupt and latches the vector number. Figure 4.5 is a flowchart of the interrupt (and reset) operations. Figure 4.7 shows the interrupt timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM and the stack is in on-chip RAM. 1. An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the enable bit of that interrupt is set to 1. 2. The interrupt controller checks the I bit in CCR and accepts the interrupt request if the I bit is cleared to 0. If the I bit is set to 1 only NMI requests are accepted; other interrupt requests remain pending. 3. Among all accepted interrupt requests, the interrupt controller selects the request with the highest priority and passes it to the CPU. Other interrupt requests remain pending. 4. When it receives the interrupt request, the CPU waits until completion of the current instruction or hardware exception-handling sequence, then starts the hardware exceptionhandling sequence for the interrupt and latches the interrupt vector number. 5. In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the stack. See figure 4.6. The stacked PC indicates the address of the first instruction that will be executed on return from the software interrupt-handling routine. 6. Next the I bit in CCR is set to 1, masking all further interrupts except NMI. 7. The vector address corresponding to the vector number is generated, the vector table entry at this vector address is loaded into the program counter, and execution branches to the software interrupt-handling routine at the address indicated by that entry. 76 Program execution Interrupt requested? No Yes Yes NMI? No No Pending I = 0? Yes IRQ0? No Yes IRQ1? No Yes IICI? Yes Latch vector no. Save PC Save CCR Reset I1 Read vector address Branch to software interrupt-handling routine Figure 4.5 Hardware Interrupt-Handling Sequence 77 SP - 4 SP(R7) CCR SP - 3 SP + 1 CCR* SP - 2 SP + 2 PC (upper byte) SP - 1 SP + 3 PC (lower byte) SP (R7) Stack area Before interrupt is accepted SP + 4 Pushed onto stack Even address After interrupt is accepted PC: Program counter CCR: Condition code register SP: Stack pointer Notes: 1. The PC contains the address of the first instruction executed after return. 2. Registers must be saved and restored by word access at an even address. * Ignored on return. Figure 4.6 Usage of Stack in Interrupt Handling The CCR is comprised of one byte, but when it is saved to the stack, it is treated as one word of data. During interrupt processing, two identical bytes of CCR data are saved to the stack to create one word of data. When the RTE instruction is executed to restore the value from the stack, the byte located at the even address is loaded into CCR, and the byte located at the odd address is ignored. 78 Interrupt accepted Interrupt priority decision. Wait for Instruction Internal end of instruction. prefetch processing Instruction prefetch (first instruction of Internal interrupt-handling process- routine) ing Vector fetch Stack Interrupt request signal o Internal address bus (1) (3) (5) (8) (6) (9) Internal read signal Internal write signal Internal 16-bit data bus (1) (2) (4) (3) (5) (6) (7) (8) (9) (10) (2) (4) (1) (7) (9) (10) Instruction prefetch address (Pushed on stack. Instruction is executed on return from interrupt-handling routine.) Instruction code (Not executed) Instruction prefetch address (Not executed) SP-2 SP-4 CCR Address of vector table entry Vector table entry (address of first instruction of interrupt-handling routine) First instruction of interrupt-handling routine Figure 4.7 Timing of Interrupt Sequence 79 4.3.6 Interrupt Response Time Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since on-chip memory is accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip ROM and the stack in on-chip RAM. Table 4.4 Number of States before Interrupt Service Number of States No. Reason for Wait On-Chip Memory *3 External Memory 1 Interrupt priority decision 2 2*3 2 Wait for completion of current instruction*1 1 to 13 5 to 17 *2 3 Save PC and CCR 4 12*2 4 Fetch vector 2 6*2 5 Fetch instruction 4 12*2 6 Internal processing 4 4 Total 17 to 29 41 to 53 *2 Notes: *1 These values do not apply if the current instruction is EEPMOV. *2 If wait states are inserted in external memory access, add the number of wait states. *3 1 for internal interrupts. 80 4.3.7 Precaution Note that the following type of contention can occur in interrupt handling. When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR or MOV instruction, for example, and the interrupt is requested during execution of that instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution of the instruction, the hardware exception-handling sequence is executed for the interrupt. If a higher-priority interrupt is requested at the same time, however, the hardware exception-handling sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored. Similar considerations apply when an interrupt request flag is cleared to 0. Figure 4.8 shows an example in which the OCIAE bit is cleared to 0. CPU write cycle to TIER OCIA interrupt handling o Internal address bus TIER address Internal write signal OCIAE OCFA OCIA interrupt signal Figure 4.8 Contention between Interrupt and Disabling Instruction The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt mask bit (I) is set to 1. 81 4.4 Note on Stack Handling In word access, the least significant bit of the address is always assumed to be 0. The stack is always accessed by word access. Care should be taken to keep an even value in the stack pointer (general register R7). Use the PUSH and POP (or MOV.W Rn, @-SP and MOV.W @SP+, Rn) instructions to push and pop registers on the stack. Setting the stack pointer to an odd value can cause programs to crash. Figure 4.9 shows an example of damage caused when the stack pointer contains an odd address. PCH SP PCL SP R1L H'FECC PCL H'FECD H'FECF SP BSR instruction H'FECF set in SP PCH: PCL: R1L: SP: MOV.B R1L, @-R7 PC is improperly stored beyond top of stack PCH is lost Upper byte of program counter Lower byte of program counter General register Stack pointer Figure 4.9 Example of Damage Caused by Setting an Odd Address in R7 82 Section 5 Wait-State Controller 5.1 Overview The H8/3437 Series has an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 5.1.1 Features Features of the wait-state controller are listed below. * Three selectable wait modes: programmable wait mode, pin auto-wait mode, and pin wait mode * Automatic insertion of zero to three wait states 5.1.2 Block Diagram WAIT Wait-state controller (WSC) WSCR Internal data bus Figure 5.1 shows a block diagram of the wait-state controller. Wait request signal Legend: WSCR: Wait-state control register Figure 5.1 Block Diagram of Wait-State Controller 83 5.1.3 Input/Output Pins Table 5.1 summarizes the wait-state controller's input pin. Table 5.1 Wait-State Controller Pins Name Abbreviation I/O Function Wait WAIT Input Wait request signal for access to external addresses 5.1.4 Register Configuration Table 5.2 summarizes the wait-state controller's register. Table 5.2 Register Configuration Address Name Abbreviation R/W Initial Value H'FFC2 Wait-state control register WSCR R/W H'08 5.2 Register Description 5.2.1 Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. It also controls RAM area setting for dual-powersupply flash memory, selection/non-selection of single-power-supply flash memory control registers, and frequency division of the clock signals supplied to the supporting modules. Bit 7 6 *1 RAMS 5 *1 RAM0 4 *2 CKDBL FLSHE 3 2 1 0 WMS1 WMS0 WC1 WC0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Notes: *1 These bits are valid only in the H8/3437F and H8/3434F (dual-power-supply on-chip flash memory versions). *2 This bit is valid only in the H8/3437SF (S-mask model, single-power-supply on-chip flash memory version). WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. 84 Bit 7--RAM Select (RAMS) Bit 6--RAM Area Select (RAM0) Bits 7 and 6 select a RAM area for emulation of dual-power-supply flash memory updates. For details, see the flash memory description in section 19, 20, ROM. Bit 5--Clock Double (CKDBL): Controls frequency division of clock signals supplied to supporting modules. For details, see section 6, Clock Pulse Generator. Bit 4--Flash Memory Control Register Enable (FLSHE): Controls selection/non-selection of single-power-supply flash memory control registers. For details, see the description of flash memory in section 21, ROM. In models other than the H8/3437SF, this bit is reserved, but it can be written and read; its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode. Bit 3: WMS1 Bit 2: WMS0 Description 0 0 Programmable wait mode 1 No wait states inserted by wait-state controller 0 Pin wait mode 1 Pin auto-wait mode 1 (Initial value) Bits 1 and 0--Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external address areas. Bit 1: WC1 Bit 0: WC0 Description 0 0 No wait states inserted by wait-state controller 1 1 state inserted 0 2 states inserted 1 3 states inserted 1 (Initial value) 85 5.3 Wait Modes Programmable Wait Mode: The number of wait states (TW ) selected by bits WC1 and WC0 are inserted in all accesses to external addresses. Figure 5.2 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). T1 T2 TW T3 o Address bus External address AS RD Read access Read data Data bus WR Write access Data bus Write data Figure 5.2 Programmable Wait Mode 86 Pin Wait Mode: In all accesses to external addresses, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (o) in the last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high. Pin wait mode is useful for inserting four or more wait states, or for inserting different numbers of wait states for different external devices. Figure 5.3 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait state is inserted by WAIT input. T1 Inserted by wait count Inserted by WAIT signal TW TW T2 o * T3 * WAIT pin Address bus External address AS Read access RD Read data Data bus WR Write access Data bus Write data Note: * Arrows indicate time of sampling of the WAIT pin. Figure 5.3 Pin Wait Mode 87 Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (o) in the T2 state, the number of wait states (TW ) selected by bits WC1 and WC0 are inserted. No additional wait states are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the WAIT pin. Figure 5.4 shows the timing when the wait count is 1. T1 o T2 T3 T1 T2 * TW T3 * WAIT Address bus External address External address AS RD Read access Read data Read data Data bus WR Write access Data bus Write data Note: * Arrows indicate time of sampling of the WAIT pin. Figure 5.4 Pin Auto-Wait Mode 88 Write data Section 6 Clock Pulse Generator 6.1 Overview The H8/3437 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a duty adjustment circuit, and a divider and a prescaler that generates clock signals for the on-chip supporting modules. 6.1.1 Block Diagram Figure 6.1 shows a block diagram of the clock pulse generator. XTAL EXTAL Oscillator circuit Duty adjustment circuit o (system clock) oP (for supporting modules) Prescaler Frequency divider (1/2) CKDBL oP/2 to oP/4096 Figure 6.1 Block Diagram of Clock Pulse Generator Input an external clock signal to the EXTAL pin, or connect a crystal resonator to the XTAL and EXTAL pins. The system clock frequency (o) will be the same as the input frequency. This same system clock frequency (oP) can be supplied to timers and other supporting modules, or it can be divided by two. The selection is made by software, by controlling the CKDBL bit. 89 6.1.2 Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait state controller wait settings, RAM area setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply flash memory control registers. WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7 6 *1 RAMS 5 *1 RAM0 4 *2 CKDBL FLSHE 3 2 1 0 WMS1 WMS0 WC1 WC0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Notes: *1 These bits are valid only in the H8/3437F and H8/3434F (dual-power-supply on-chip flash memory versions). *2 This bit is valid only in the H8/3437SF (S-mask model, single-power-supply on-chip flash memory version). Bit 7--RAM Select (RAMS) Bit 6--RAM Area Select (RAM0) Bits 7 and 6 select a RAM area for emulation of dual-power-supply flash memory updates. For details, see the flash memory description in section 19, 20, ROM. Bit 5--Clock Double (CKDBL): Controls the frequency division of clock signals supplied to supporting modules. Bit 5: CKDBL Description 0 The undivided system clock (o) is supplied as the clock (o P) for supporting modules. (Initial value) 1 The system clock (o) is divided by two and supplied as the clock (o P) for supporting modules. Bit 4--Flash Memory Control Register Enable (FLSHE): Controls selection/non-selection of single-power-supply flash memory control registers. For details, see the description of flash memory in section 21, ROM. In models other than the H8/3437SF, this bit is reserved, but it can be written and read; its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1/0) Bits 1 and 0--Wait Count 1 and 0 (WC1/0) These bits control wait-state insertion. For details, see section 5, Wait-State Controller. 90 6.2 Oscillator Circuit 6.2.1 Oscillator (Generic Device) If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. Connecting an External Crystal Circuit Configuration: An external crystal can be connected as in the example in figure 6.2. Table 6.1 indicates the appropriate damping resistance Rd. An AT-cut parallel resonance crystal should be used. CL1 EXTAL XTAL Rd CL1 = C L2 = 10 pF to 22 pF CL2 Figure 6.2 Connection of Crystal Oscillator (Example) Table 6.1 Damping Resistance Frequency (MHz) 2 4 8 10 12 16 Rd max () 1k 500 200 0 0 0 Crystal Oscillator: Figure 6.3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 6.2. 91 CL L Rs XTAL EXTAL C0 AT-cut parallel resonating crystal Figure 6.3 Equivalent Circuit of External Crystal Table 6.2 External Crystal Parameters Frequency (MHz) 2 4 8 10 12 16 Rs max () 500 120 80 70 60 50 C0 (pF) 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max 7 pF max Use a crystal with the same frequency as the desired system clock frequency (o). Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 6.4. The crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Not allowed Signal A Signal B CL2 XTAL EXTAL CL1 Figure 6.4 Notes on Board Design around External Crystal 92 Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6.5. In example (b) in figure 6.5, the external clock signal should be kept high during standby. If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF. EXTAL XTAL External clock input Open (a) Connections with XTAL pin left open EXTAL External clock input 74HC04 XTAL (b) Connections with inverted clock input at XTAL pin Figure 6.5 External Clock Input (Example) 93 External Clock Input: The external clock signal should have the same frequency as the desired system clock (o). Clock timing parameters are given in table 6.3 and figure 6.6. Table 6.3 Clock Timing VCC = 2.7 to 5.5 V VCC = 4.0 to 5.5 V VCC = 5.0 V 10% Min Max Min Max Min Max Unit Test Conditions Low pulse t EXL width of external clock input 40 -- 30 -- 20 -- ns High pulse t EXH width of external clock input 40 -- 30 -- 20 -- ns External clock rise time t EXr -- 10 -- 10 -- 5 ns External clock fall time t EXf -- 10 -- 10 -- 5 ns Clock pulse width low t CL 0.3 0.7 0.3 0.7 0.3 0.7 t cyc 0.4 0.6 0.4 0.6 0.4 0.6 t cyc o 5 MHz Figure o < 5 MHz 23.7 Clock pulse width high t CH 0.3 0.7 0.3 0.7 0.3 0.7 t cyc o 5 MHz 0.4 0.6 0.4 0.6 0.4 0.6 t cyc o < 5 MHz Item Symbol tEXH Figure 6.6 tEXL EXTAL VCC x 0.5 tEXr tEXt Figure 6.6 External Clock Input Timing Table 6.4 lists the external clock output stabilization delay time. Figure 6.7 shows the timing for the external clock output stabilization delay time. The oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (t DEXT). As clock signal output is not confirmed during the tDEXT period, the reset signal should be driven low and the reset state maintained during this time. 94 Table 6.4 External Clock Output Stabilization Delay Time Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, VSS = AVSS = 0 V Item Symbol Min Max Unit Notes External clock output stabilization delay time t DEXT* 500 -- s Figure 6.7 Note: * t DEXT includes a 10 tcyc RES pulse width (t RESW). VCC STBY 2.7 V VIH EXTAL o (internal and external) RES tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW). Figure 6.7 External Clock Output Stabilization Delay Time 6.2.2 Oscillator Circuit (H8/3437S) If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. Connecting an External Crystal Circuit Configuration: An external crystal can be connected as in the example in figure 6.8. Table 6.5 indicates the appropriate damping resistance Rd. An AT-cut parallel resonance crystal should be used. 95 CL1 EXTAL XTAL Rd CL1 = C L2 = 10 pF to 22 pF CL2 Figure 6.8 Connection of Crystal Oscillator (Example) Table 6.5 Damping Resistance Frequency (MHz) 2 4 8 10 Rd max () 1k 500 200 0 Crystal Oscillator: Figure 6.9 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 6.6. CL L Rs XTAL EXTAL C0 AT-cut parallel resonating crystal Figure 6.9 Equivalent Circuit of External Crystal Table 6.6 External Crystal Parameters Frequency (MHz) 2 4 8 10 Rs max () 500 120 80 70 C0 (pF) 7 pF max 7 pF max 7 pF max 7 pF max Use a crystal with the same frequency as the desired system clock frequency (o). Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 6.10. The crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. 96 Not allowed Signal A Signal B CL2 XTAL EXTAL CL1 Figure 6.10 Notes on Board Design around External Crystal Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6.11. In example (b) in figure 6.11, the external clock signal should be kept high during standby. If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF. EXTAL XTAL External clock input Open (a) Connections with XTAL pin left open EXTAL External clock input 74HC04 XTAL (b) Connections with inverted clock input at XTAL pin Figure 6.11 External Clock Input (Example) 97 External Clock Input: The external clock signal should have the same frequency as the desired system clock (o). Clock timing parameters are given in table 6.7 and figure 6.12. Table 6.7 Clock Timing VCC = 3.0 to 5.5 V Item Symbol Min Max Unit Test Conditions Low pulse width of external clock input t EXL 40 -- ns Figure 6.12 High pulse width of external clock input t EXH 40 -- ns External clock rise time t EXr -- 10 ns External clock fall time t EXf -- 10 ns Clock pulse width low t CL 0.3 0.7 t cyc o 5 MHz 0.4 0.6 t cyc o < 5 MHz Clock pulse width high t CH 0.3 0.7 t cyc o 5 MHz 0.4 0.6 t cyc o < 5 MHz tEXH Figure 23.7 tEXL EXTAL VCC x 0.5 tEXr tEXt Figure 6.12 External Clock Input Timing Table 6.8 lists the external clock output stabilization delay time. Figure 6.13 shows the timing for the external clock output stabilization delay time. The oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (t DEXT). As clock signal output is not confirmed during the tDEXT period, the reset signal should be driven low and the reset state maintained during this time. 98 Table 6.8 External Clock Output Stabilization Delay Time Conditions: VCC = 3.0 to 5.5 V, AVCC = 2.7 to 5.5 V, VSS = AVSS = 0 V Item Symbol Min Max Unit Notes External clock output stabilization delay time t DEXT* 500 -- s Figure 6.13 Note: * t DEXT includes a 10 tcyc RES pulse width (t RESW). VCC STBY 3.0 V VIH EXTAL o (internal and external) RES tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW). Figure 6.13 External Clock Output Stabilization Delay Time 6.3 Duty Adjustment Circuit When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle of the signal from the oscillator circuit to generate the system clock (o). 6.4 Prescaler The clock for the on-chip supporting modules (oP) has either the same frequency as the system clock (o) or this frequency divided by two, depending on the CKDBL bit. The prescaler divides the frequency of oP to generate internal clock signals with frequencies from oP/2 to oP/4096. 99 100 Section 7 I/O Ports 7.1 Overview The H8/3437 Series has eight 8-bit input/output ports, one 7-bit input/output port, and one 3-bit input/output port, and are 8-bit input port. Table 7.1 lists the functions of each port in each operating mode. As table 7.1 indicates, the port pins are multiplexed, and the pin functions differ depending on the operating mode. Each port has a data direction register (DDR) that selects input or output, and a data register (DR) that stores output data. If bit manipulation instructions will be executed on the port data direction registers, see "Notes on Bit Manipulation Instructions" in section 2.5.5, Bit Manipulations. Ports 1, 2, 3, 4, 6, 9, A, and B can drive one TTL load and a 90-pF capacitive load. Ports 5 and 8 can drive one TTL load and a 30-pF capacitive load. Ports 1 and 2 can drive LEDs (with 10-mA current sink). Ports 1 to 6, 8, 9, A, and B can drive a darlington transistor. Ports 1 to 3, 6, A, and B have built-in MOS pull-up transistors. For block diagrams of the ports, see appendix C, I/O Port Block Diagrams. Pins P86 in port 8, P97 in port 9, and PA4, PA5, PA6, and PA7 in port A can be driven to operate as bus buffers. For details, see section 13, I 2C Bus Interface. 101 Table 7.1 Port Functions Expanded Modes Single-Chip Mode Port Description Pins Mode 1 Mode 2 Mode 3 Port 1 * 8-bit I/O port P17 to P10/A 7 to A0 Lower address output (A7 to A0) Lower address output (A7 to A0) or general input General input/output P27 to P20/A 15 to A8 Upper address output (A15 to A8) Upper address output (A15 to A8) or general input General input/output P37 to P30/ D7 to D0/ HDB7 to HDB0 Data bus (D7 to D0) Data bus (D7 to D0) HIF data bus (HDB 7 to HDB0) or general input/ output P47/PW1 PWM timer 0/1 output (PW0, PW1), or general input/output * Can drive LEDs * Built-in input pull-ups Port 2 * 8-bit I/O port * Can drive LEDs * Built-in input pull-ups Port 3 * 8-bit I/O port * Built-in input pull-ups * HIF data bus Port 4 * 8-bit I/O port P46/PW0 P45/TMRI1/HIRQ12 P44/TMO1/HIRQ1 P43/TMCI1/HIRQ11 P42/TMRI0 P41/TMO0 8-bit timer 1 input/output (TMCI 1, TMO1, TMRI1), host processor interrupt request output from HIF (HIRQ11 , HIRQ1, HIRQ12), or general input/output 8-bit timer 0 input/output (TMCI 0, TMO0, TMRI0) or general input/output P40/TMCI0 Port 5 * 3-bit I/O port P52/SCK 0 P51/RxD0 Serial communication interface 0 input/output (TxD 0, RxD 0, SCK0) or general input/output P50/TxD0 Port 6 * 8-bit I/O port * Built-in input pull-ups * Key-sense interrupt inputs P67/KEYIN7/IRQ7 16-bit free-running timer input/output (FTCI, FTOA, P66/KEYIN6/FTOB/IRQ6 FTIA, FTIB, FTIC, FTID, FTOB), key-sense interrupt input (KEYIN7 to KEYIN0), external interrupt input (IRQ7, P65/KEYIN5/FTID IRQ6), or general input/output P64/KEYIN4/FTIC P63/KEYIN3/FTIB P62/KEYIN2/FTIA P61/KEYIN1/FTOA P60/KEYIN0/FTCI Port 7 102 * 8-bit I/O port P76/AN6/DA0 P77/AN7/DA1 Analog input to A/D converter (AN 7, AN 6), analog output from D/A converter (DA1, DA 0), or general input P75 to P70/ AN5 to AN0 Analog input to A/D converter (AN 5 to AN0) or general input Expanded Modes Port Description Pins Mode 1 Port 8 * 7-bit I/O port P86/IRQ5/SCK 1/SCL * Can drive a bus line (P86) P85/IRQ4/RxD1/CS2 Serial communication interface 1 input/output (TxD 1, RxD 1, SCK1), HIF control input (CS2, IOW), I2C clock input/output (SCL), external interrupt input (IRQ5 to IRQ3), or general input/output P84/IRQ3/TxD1/IOW P83/IOR P82/CS1 Mode 2 Single-Chip Mode Mode 3 HIF control input/output (HA0, GA20 , CS1, IOR), or general input/output P81/GA20 P80/HA0 Port 9 * 8-bit I/O port P97/WAIT/SDA Expanded data bus control input (WAIT), I2C data input/output (SDA), or general input/output I2C data input/output (SDA) or general input/ output P96/o System clock (o) output o output or general input P95/AS Expanded data bus control output (RD, WR, AS) * Can drive a bus line (P97) P94/WR System clock (o) output General input/output P93/RD P92/IRQ0 P91/IRQ1/EIOW P90/IRQ2/ECS2/ADTRG Port A * 8-bit I/O port * Built-in input pull-ups HIF control input (ECS2, EIOW), trigger input to A/D converter (ADTRG), external interrupt input (IRQ2 to IRQ0), or general input/output PA 7 to PA0/ KEYIN15 to KEYIN8 Key-sense interrupt input (KEYIN15 to KEYIN8) or general input/output PB 7 to PB0/ XDB7 to XDB0 HIF data bus (XDB7 to XDB 0) or general input/output * Key-sense interrupt inputs * Can drive bus lines (PA4, PA5, PA 6, PA7) Port B * 8-bit I/O port * HIF data bus General input/output * Built-in input pull-up MOS 103 7.2 Port 1 7.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7.1. The pin functions differ depending on the operating mode. Port 1 has built-in, programmable MOS input pull-up transistors that can be used in modes 2 and 3. Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and darlington transistors. Port 1 Port 1 pins Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) Pin configuration in mode 2 (expanded mode with on-chip ROM enabled) P17/A7 A7 (output) A7 (output)/P17 (input) P16/A6 A6 (output) A6 (output)/P16 (input) P15/A5 A5 (output) A5 (output)/P15 (input) P14/A4 A4 (output) A4 (output)/P14 (input) P13/A3 A3 (output) A3 (output)/P13 (input) P12/A2 A2 (output) A2 (output)/P12 (input) P11/A1 A1 (output) A1 (output)/P11 (input) P10/A0 A0 (output) A0 (output)/P10 (input) Pin configuration in mode 3 (single-chip mode) P17 (input/output) P16 (input/output) P15 (input/output) P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 7.1 Port 1 Pin Configuration 104 7.2.2 Register Configuration and Descriptions Table 7.2 summarizes the port 1 registers. Table 7.2 Port 1 Registers Name Abbreviation Read/Write Initial Value Address Port 1 data direction register P1DDR W H'FF (mode 1) H'FFB0 H'00 (modes 2 and 3) Port 1 data register P1DR R/W H'00 H'FFB2 Port 1 input pull-up control register P1PCR R/W H'00 H'FFAC Port 1 Data Direction Register (P1DDR) Bit 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Mode 1 Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Modes 2 and 3 P1DDR controls the input/output direction of each pin in port 1. Mode 1: The P1DDR values are fixed at 1. Port 1 consists of lower address output pins. P1DDR values cannot be modified and are always read as 1. In hardware standby mode, the address bus is in the high-impedance state. Mode 2: A pin in port 1 is used for address output if the corresponding P1DDR bit is set to 1, and for general input if this bit is cleared to 0. Mode 3: A pin in port 1 is used for general output if the corresponding P1DDR bit is set to 1, and for general input if this bit is cleared to 0. In modes 2 and 3, P1DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P1DDR bit is set to 1, the corresponding pin remains in the output state. 105 Port 1 Data Register (P1DR) Bit 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit register that stores data for pins P17 to P10. When a P1DDR bit is set to 1, if port 1 is read, the value in P1DR is obtained directly, regardless of the actual pin state. When a P1DDR bit is cleared to 0, if port 1 is read the pin state is obtained. P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 1 Input Pull-Up Control Register (P1PCR) Bit 7 P17PCR 6 5 P16PCR P15PCR 4 3 P14PCR P13PCR 2 1 P12PCR P11PCR 0 P10PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. If a P1DDR bit is cleared to 0 (designating input) and the corresponding P1PCR bit is set to 1, the input pull-up transistor is turned on. P1PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 106 7.2.3 Pin Functions in Each Mode Port 1 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 is automatically used for lower address output (A7 to A0). Figure 7.2 shows the pin functions in mode 1. A7 (output) A6 (output) A5 (output) Port 1 A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 7.2 Pin Functions in Mode 1 (Port 1) 107 Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address output pins and general input pins. Each pin becomes a lower address output pin if its P1DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To be used for address output, their P1DDR bits must be set to 1. Figure 7.3 shows the pin functions in mode 2. Port 1 When P1DDR = 1 When P1DDR = 0 A7 (output) P17 (input) A6 (output) P16 (input) A5 (output) P15 (input) A4 (output) P14 (input) A3 (output) P13 (input) A2 (output) P12 (input) A1 (output) P11 (input) A0 (output) P10 (input) Figure 7.3 Pin Functions in Mode 2 (Port 1) Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P1DDR bit is cleared to 0 and a general output pin when this bit is set to 1. Figure 7.4 shows the pin functions in mode 3. P17 (input/output) P16 (input/output) P15 (input/output) Port 1 P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 7.4 Pin Functions in Mode 3 (Port 1) 108 7.2.4 Input Pull-Up Transistors Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P1PCR bit to 1 and clear the corresponding P1DDR bit to 0. P1PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7.3 indicates the states of the input pull-up transistors in each operating mode. Table 7.3 States of Input Pull-Up Transistors (Port 1) Mode Reset Hardware Standby Software Standby Other Operating Modes 1 Off Off Off Off 2 Off Off On/off On/off 3 Off Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P1PCR = 1 and P1DDR = 0, but off otherwise. 109 7.3 Port 2 7.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7.5. The pin functions differ depending on the operating mode. Port 2 has built-in, programmable MOS input pull-up transistors that can be used in modes 2 and 3. Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and darlington transistors. Port 2 Port 2 pins Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) Pin configuration in mode 2 (expanded mode with on-chip ROM enabled) P27/A15 A15 (output) A15 (output)/P27 (input) P26/A14 A14 (output) A14 (output)/P26 (input) P25/A13 A13 (output) A13 (output)/P25 (input) P24/A12 A12 (output) A12 (output)/P24 (input) P23/A11 A11 (output) A11 (output)/P23 (input) P22/A10 A10 (output) A10 (output)/P22 (input) P21/A9 A9 (output) A9 (output)/P21 (input) P20/A8 A8 (output) A8 (output)/P20 (input) Pin configuration in mode 3 (single-chip mode) P27 (input/output) P26 (input/output) P25 (input/output) P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 7.5 Port 2 Pin Configuration 110 7.3.2 Register Configuration and Descriptions Table 7.4 summarizes the port 2 registers. Table 7.4 Port 2 Registers Name Abbreviation Read/Write Initial Value Address Port 2 data direction register P2DDR W H'FF (mode 1) H'FFB1 H'00 (modes 2 and 3) Port 2 data register P2DR R/W H'00 H'FFB3 Port 2 input pull-up control register P2PCR R/W H'00 H'FFAD Port 2 Data Direction Register (P2DDR) Bit 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Mode 1 Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Modes 2 and 3 P2DDR controls the input/output direction of each pin in port 2. Mode 1: The P2DDR values are fixed at 1. Port 2 consists of upper address output pins. P2DDR values cannot be modified and are always read as 1. In hardware standby mode, the address bus is in the high-impedance state. Mode 2: A pin in port 2 is used for address output if the corresponding P2DDR bit is set to 1, and for general input if this bit is cleared to 0. Mode 3: A pin in port 2 is used for general output if the corresponding P2DDR bit is set to 1, and for general input if this bit is cleared to 0. In modes 2 and 3, P2DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P2DDR bit is set to 1, the corresponding pin remains in the output state. 111 Port 2 Data Register (P2DR) Bit 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P2DR is an 8-bit register that stores data for pins P27 to P20. When a P2DDR bit is set to 1, if port 2 is read, the value in P2DR is obtained directly, regardless of the actual pin state. When a P2DDR bit is cleared to 0, if port 2 is read the pin state is obtained. P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 2 Input Pull-Up Control Register (P2PCR) Bit 7 P27PCR 6 5 P26PCR P25PCR 4 3 P24PCR P23PCR 2 1 P22PCR P21PCR 0 P10PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. If a P2DDR bit is cleared to 0 (designating input) and the corresponding P2PCR bit is set to 1, the input pull-up transistor is turned on. P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 112 7.3.3 Pin Functions in Each Mode Port 2 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 is automatically used for upper address output (A15 to A8). Figure 7.6 shows the pin functions in mode 1. A15 (output) A14 (output) A13 (output) Port 2 A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Figure 7.6 Pin Functions in Mode 1 (Port 2) 113 Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address output pins and general input pins. Each pin becomes an upper address output pin if its P2DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To be used for address output, their P2DDR bits must be set to 1. Figure 7.7 shows the pin functions in mode 2. Port 2 When P2DDR = 1 When P2DDR = 0 A15 (output) P27 (input) A14 (output) P26 (input) A13 (output) P25 (input) A12 (output) P24 (input) A11 (output) P23 (input) A10 (output) P22 (input) A9 (output) P21 (input) A8 (output) P20 (input) Figure 7.7 Pin Functions in Mode 2 (Port 2) Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0, and a general output pin when this bit is set to 1. Figure 7.8 shows the pin functions in mode 3. P27 (input/output) P26 (input/output) P25 (input/output) Port 2 P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 7.8 Pin Functions in Mode 3 (Port 2) 114 7.3.4 Input Pull-Up Transistors Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P2PCR bit to 1 and clear the corresponding P2DDR bit to 0. P2PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7.5 indicates the states of the input pull-up transistors in each operating mode. Table 7.5 States of Input Pull-Up Transistors (Port 2) Mode Reset Hardware Standby Software Standby Other Operating Modes 1 Off Off Off Off 2 Off Off On/off On/off 3 Off Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0, but off otherwise. 115 7.4 Port 3 7.4.1 Overview Port 3 is an 8-bit input/output port that is multiplexed with the data bus and host interface data bus. Figure 7.9 shows the pin configuration of port 3. The pin functions differ depending on the operating mode. Port 3 has built-in, programmable MOS input pull-up transistors that can be used in mode 3. Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor. Port 3 Port 3 pins Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) P37/D7/HDB7 D7 (input/output) P36/D6/HDB6 D6 (input/output) P35/D5/HDB5 D5 (input/output) P34/D4/HDB4 D4 (input/output) P33/D3/HDB3 D3 (input/output) P32/D2/HDB2 D2 (input/output) P31/D1/HDB1 D1 (input/output) P30/D0/HDB0 D0 (input/output) Pin configuration in mode 3 (single-chip mode) Master mode Slave mode P37 (input/output) HDB7 (input/output) P36 (input/output) HDB6 (input/output) P35 (input/output) HDB5 (input/output) P34 (input/output) HDB4 (input/output) P33 (input/output) HDB3 (input/output) P32 (input/output) HDB2 (input/output) P31 (input/output) HDB1 (input/output) P30 (input/output) HDB0 (input/output) Figure 7.9 Port 3 Pin Configuration 116 7.4.2 Register Configuration and Descriptions Table 7.6 summarizes the port 3 registers. Table 7.6 Port 3 Registers Name Abbreviation Read/Write Initial Value Address Port 3 data direction register P3DDR W H'00 H'FFB4 Port 3 data register P3DR R/W H'00 H'FFB6 Port 3 input pull-up control register P3PCR R/W H'00 H'FFAE Port 3 Data Direction Register (P3DDR) Bit 7 6 5 4 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P3DDR is an 8-bit register that controls the input/output direction of each pin in port 3. P3DDR is a write-only register. Read data is invalid. If read, all bits always read 1. Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), the input/output directions designated by P3DDR are ignored. Port 3 automatically consists of the input/output pins of the 8-bit data bus (D7 to D0). The data bus is in the high-impedance state during reset, and during hardware and software standby. Mode 3: A pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1, and for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in the output state. 117 Port 3 Data Register (P3DR) Bit 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P3DR is an 8-bit register that stores data for pins P37 to P30. When a P3DDR bit is set to 1, if port 3 is read, the value in P3DR is obtained directly, regardless of the actual pin state. When a P3DDR bit is cleared to 0, if port 3 is read the pin state is obtained. P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 3 Input Pull-Up Control Register (P3PCR) Bit 7 P37PCR 6 5 P36PCR P35PCR 4 3 P34PCR P33PCR 2 1 P32PCR P31PCR 0 P30PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P3PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. If a P3DDR bit is cleared to 0 (designating input) and the corresponding P3PCR bit is set to 1, the input pull-up transistor is turned on. P3PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. The input pull-ups cannot be used in slave mode (when the host interface is enabled). 118 7.4.3 Pin Functions in Each Mode Port 3 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), port 3 is automatically used for the input/output pins of the data bus (D7 to D0). Figure 7.10 shows the pin functions in modes 1 and 2. Modes 1 and 2 D7 (input/output) D6 (input/output) D5 (input/output) Port 3 D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Figure 7.10 Pin Functions in Modes 1 and 2 (Port 3) 119 Mode 3: In mode 3 (single-chip mode), when the host interface enable bit (HIE) is cleared to 0 in the system control register (SYSCR), port 3 is a general-purpose input/output port. A pin becomes an output pin when its P3DDR bit is set to 1, and an input pin when this bit is cleared to 0. When the HIE bit is set to 1, selecting slave mode, port 3 becomes the host interface data bus (HDB7 to HDB0). For details, see section 14, Host Interface. Figure 7.11 shows the pin functions in mode 3. P37 (input/output)/HDB7 (input/output) P36 (input/output)/HDB6 (input/output) P35 (input/output)/HDB5 (input/output) Port 3 P34 (input/output)/HDB4 (input/output) P33 (input/output)/HDB3 (input/output) P32 (input/output)/HDB2 (input/output) P31 (input/output)/HDB1 (input/output) P30 (input/output)/HDB0 (input/output) Figure 7.11 Pin Functions in Mode 3 (Port 3) 7.4.4 Input Pull-Up Transistors Port 3 has built-in programmable input pull-up transistors that are available in mode 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 3, set the corresponding P3PCR bit to 1 and clear the corresponding P3DDR bit to 0. P3PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7.7 indicates the states of the input pull-up transistors in each operating mode. Table 7.7 States of Input Pull-Up Transistors (Port 3) Mode Reset Hardware Standby Software Standby Other Operating Modes 1 Off Off Off Off 2 Off Off Off Off 3 Off Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P3PCR = 1 and P3DDR = 0, but off otherwise. 120 7.5 Port 4 7.5.1 Overview Port 4 is an 8-bit input/output port that is multiplexed with input/output pins (TMRI0, TMRI1, TMCI0, TMCI1, TMO0, TMO1) of 8-bit timers 0 and 1 and output pins (PW0, PW1) of PWM timers 0 and 1. In slave mode, P43 to P45 output host interrupt requests. Pins not used by timers or for host interrupt requests are available for general input/output. Figure 7.12 shows the pin configuration of port 4. Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor. Port 4 pins P47/PW1 P46/PW0 P45/TMRI1/HIRQ12 Port 4 P44/TMO1/HIRQ1 P43/TMCI1/HIRQ11 P42/TMRI0 P41/TMO0 P40/TMCI0 Pin configuration in modes 1 to 3 Master mode Slave mode P47 (input/output)/PW1 (output) P47 (input/output)/PW1 (output) P46 (input/output)/PW0 (output) P46 (input/output)/PW0 (output) P45 (input/output)/TMRI1 (input) HIRQ12 (output)/TMRI1 (input) P44 (input/output)/TMO1 (output) HIRQ1 (output)/TMO1 (output) P43 (input/output)/TMCI1 (input) HIRQ11 (output)/TMCI1 (input) P42 (input/output)/TMRI0 (input) P42 (input/output)/TMRI0 (input) P41 (input/output)/TMO0 (output) P41 (input/output)/TMO0 (output) P40 (input/output)/TMCI0 (input) P40 (input/output)/TMCI0 (input) Figure 7.12 Port 4 Pin Configuration 121 7.5.2 Register Configuration and Descriptions Table 7.8 summarizes the port 4 registers. Table 7.8 Port 4 Registers Name Abbreviation Read/Write Initial Value Address Port 4 data direction register P4DDR W H'00 H'FFB5 Port 4 data register P4DR R/W H'00 H'FFB7 Port 4 Data Direction Register (P4DDR) Bit 7 6 5 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P4DDR is an 8-bit register that controls the input/output direction of each pin in port 4. A pin functions as an output pin if the corresponding P4DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P4DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P4DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 4 is being used by an on-chip supporting module (for example, for 8-bit timer output), the on-chip supporting module will be initialized, so the pin will revert to general-purpose input/output, controlled by P4DDR and P4DR. 122 Port 4 Data Register (P4DR) Bit 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P4DR is an 8-bit register that stores data for pins P47 to P40. When a P4DDR bit is set to 1, if port 4 is read, the value in P4DR is obtained directly, regardless of the actual pin state. When a P4DDR bit is cleared to 0, if port 4 is read the pin state is obtained. This also applies to pins used by onchip supporting modules. P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 123 7.5.3 Pin Functions Port 4 has different pin functions depending on whether the chip is or is not operating in slave mode. Table 7.9 indicates the pin functions of port 4. Table 7.9 Port 4 Pin Functions Pin Pin Functions and Selection Method P47/PW1 Bit OE in TCR of PWM timer 1 and bit P47DDR select the pin function as follows OE P47DDR Pin function P46/PW0 0 0 1 P47 input P47 output 0 1 PW1 output Bit OE in TCR of PWM timer 0 and bit P46DDR select the pin function as follows OE P46DDR Pin function P45/TMRI1/ HIRQ12 1 0 1 0 1 0 P46 input P46 output 1 PW0 output Bit P45DDR and the operating mode select the pin function as follows P45DDR 0 Operating mode -- Not slave mode Slave mode P45 input P45 output HIRQ12 output Pin function 1 TMRI1 input* Note: * TMRI1 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 1 P44/TMO1/ HIRQ1 Bits OS3 to OS0 in TCSR of 8-bit timer 1, bit P4 4DDR, and the operating mode select the pin function as follows OS3 to 0 Not all 0 P44DDR 0 Operating mode -- Not slave mode Slave mode -- P44 input P44 output HIRQ1 output TMO1 output Pin function 124 All 0 1 -- Pin Pin Functions and Selection Method P43/TMCI1/ HIRQ11 Bit P43DDR and the operating mode select the pin function as follows P43DDR 0 Operating mode -- Not slave mode Slave mode P43 input P43 output HIRQ11 output Pin function 1 TMCI1 input* Note: * TMCI1 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1 select an external clock source P42/TMRI0 P42DDR Pin function 0 1 P42 input P42 output TMRI0 input* Note: * TMRI0 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 0 P41/TMO0 Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit P4 1DDR select the pin function as follows OS3 to 0 P41DDR Pin function All 0 Not all 0 0 1 0 P41 input P41 output 1 TMO0 output P40/TMCI0 P40DDR Pin function 0 1 P40 input P40 output TMCI0 input* Note: * TMCI0 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0 select an external clock source 125 7.6 Port 5 7.6.1 Overview Port 5 is a 3-bit input/output port that is multiplexed with input/output pins (TxD 0, RxD0, SCK0) of serial communication interface 0. The port 5 pin functions are the same in all operating modes. Figure 7.13 shows the pin configuration of port 5. Pins in port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor. Port 5 pins P52 (input/output)/SCK0 (input/output) Port 5 P51 (input/output)/RxD0 (input) P50 (input/output)/TxD0 (output) Figure 7.13 Port 5 Pin Configuration 7.6.2 Register Configuration and Descriptions Table 7.10 summarizes the port 5 registers. Table 7.10 Port 5 Registers Name Abbreviation Read/Write Initial Value Address Port 5 data direction register P5DDR W H'F8 H'FFB8 Port 5 data register P5DR R/W H'F8 H'FFBA 126 Port 5 Data Direction Register (P5DDR) Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- Initial value 1 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- W W W P52DDR P51DDR P50DDR P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P5DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P5DDR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P5DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI will be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR and P5DR. Port 5 Data Register (P5DR) Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- P52 P51 P50 Initial value 1 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- R/W R/W R/W P5DR is an 8-bit register that stores data for pins P52 to P50. Bits 7 to 3 are reserved. They cannot be modified, and are always read as 1. When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless of the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is obtained. This also applies to pins used as SCI pins. P5DR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 127 7.6.3 Pin Functions Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI0 input/output pins. Table 7.11 indicates the pin functions of port 5. Table 7.11 Port 5 Pin Functions Pin Pin Functions and Selection Method P52/SCK0 Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0, and bit P52DDR select the pin function as follows CKE1 0 C/A 0 CKE0 P52DDR Pin function P51/RxD0 0 -- 1 -- -- 1 -- -- -- P52 input P52 output SCK 0 output SCK 0 output SCK 0 input Bit RE in SCR of SCI0 and bit P51DDR select the pin function as follows P51DDR Pin function 0 1 0 1 -- P51 input P51 output RxD0 input Bit TE in SCR of SCI0 and bit P50DDR select the pin function as follows TE P50DDR Pin function 128 1 0 RE P50/TxD0 1 0 1 0 1 -- P50 input P50 output TxD0 output 7.7 Port 6 7.7.1 Overview Port 6 is an 8-bit input/output port that is multiplexed with input/output pins (FTOA, FTOB, FTIA to FTID, FTCI) of the 16-bit free-running timer (FRT), with key-sense input pins, and with IRQ6 and IRQ7 input pins. The port 6 pin functions are the same in all operating modes. Figure 7.14 shows the pin configuration of port 6. Port 6 has built-in, programmable MOS input pull-up transistors. Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor. Port 6 pins P67 (input/output)/IRQ7 (input)/KEYIN7 (input) P66 (input/output)/FTOB (output)/IRQ6 (input)/KEYIN6 (input) P65 (input/output)/FTID (input)/KEYIN5 (input) Port 6 P64 (input/output)/FTIC (input)/KEYIN4 (input) P63 (input/output)/FTIB (input)/KEYIN3 (input) P62 (input/output)/FTIA (input)/KEYIN2 (input) P61 (input/output)/FTOA (output)/KEYIN1 (input) P60 (input/output)/FTCI (input)/KEYIN0 (input) Figure 7.14 Port 6 Pin Configuration 7.7.2 Register Configuration and Descriptions Table 7.12 summarizes the port 6 registers. Table 7.12 Port 6 Registers Name Abbreviation Read/Write Initial Value Address Port 6 data direction register P6DDR W H'00 H'FFB9 Port 6 data register P6DR R/W H'00 H'FFBB Port 6 input pull-up control register KMPCR R/W H'00 H'FFF2 129 Port 6 Data Direction Register (P6DDR) Bit 7 6 5 4 3 2 1 0 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W P6DDR is an 8-bit register that controls the input/output direction of each pin in port 6. A pin functions as an output pin if the corresponding P6DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P6DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P6DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P6DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 6 is being used by the free-running timer, the timer will be initialized, so the pin will revert to general-purpose input/output, controlled by P6DDR and P6DR. Port 6 Data Register (P6DR) Bit 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P6DR is an 8-bit register that stores data for pins P67 to P60. When a P6DDR bit is set to 1, if port 6 is read, the value in P6DR is obtained directly, regardless of the actual pin state. When a P6DDR bit is cleared to 0, if port 6 is read the pin state is obtained. This also applies to pins used as FRT pins. P6DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 130 Port 6 Input Pull-Up Control Register (KMPCR) Bit 7 6 5 4 3 2 1 0 KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W KMPCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 6. If a P6DDR bit is cleared to 0 (designating input) and the corresponding KMPCR bit is set to 1, the input pull-up transistor is turned on. KMPCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 131 7.7.3 Pin Functions Port 6 has the same pin functions in all operating modes. The pins are multiplexed with FRT input/output, IRQ6 and IRQ7 input, and key-sense input. Table 7.13 indicates the pin functions of port 6. Table 7.13 Port 6 Pin Functions Pin Pin Functions and Selection Method P67/IRQ7/ KEYIN7 P67DDR 0 Pin function 1 P67 input P67 output IRQ7 input* or KEYIN7 input Note: * IRQ7 input is usable when bit IRQ7E is set to 1 in IER P66/FTOB/ IRQ6/KEYIN6 Bit OEB in TOCR of the FRT and bit P6 6DDR select the pin function as follows OEB P66DDR Pin function 0 1 0 1 P66 input P66 output 0 1 FTOB output IRQ6 input* or KEYIN6 input Note: * IRQ6 input is usable when bit IRQ6E is set to 1 in IER P65/FTID/ KEYIN5 P65DDR Pin function 0 1 P65 input P65 output FTID input or KEYIN5 input P64/FTIC/ KEYIN4 P64DDR Pin function 0 1 P64 input P64 output FTIC input or KEYIN4 input 132 Pin Pin Functions and Selection Method P63/FTIB/ KEYIN3 P63DDR Pin function 0 1 P63 input P63 output FTIB input or KEYIN3 input P62/FTIA/ KEYIN2 P62DDR Pin function 0 1 P62 input P62 output FTIA input or KEYIN2 input P61/FTOA/ KEYIN1 Bit OEA in TOCR of the FRT and bit P6 1DDR select the pin function as follows OEA P61DDR Pin function 0 1 0 1 0 P61 input P61 output 1 FTOA output KEYIN1 input P60/FTCI/ KEYIN0 P60DDR Pin function 0 1 P60 input P60 output FTCI input* or KEYIN0 input Note: * FTCI input is usable when bits CKS1 to CKS0 in TCR of the FRT select an external clock source 133 7.7.4 Input Pull-Up Transistors Port 6 has built-in programmable input pull-up transistors. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up, set the corresponding KMPCR bit to 1 and clear the corresponding P6DDR bit to 0. KMPCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7.14 indicates the states of the input pull-up transistors in each operating mode. Table 7.14 States of Input Pull-Up Transistors (Port 6) Mode Reset Hardware Standby Software Standby Other Operating Modes 1 Off Off On/off On/off 2 Off Off On/off On/off 3 Off Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if KMPCR = 1 and P6DDR = 0, but off otherwise. 134 7.8 Port 7 7.8.1 Overview Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter and analog output pins for the D/A converter. The pin functions are the same in all modes. Figure 7.15 shows the pin configuration of port 7. Port 7 pins P77 (input)/AN7 (input)/DA1 (output) P76 (input)/AN6 (input)/DA0 (output) P75 (input)/AN5 (input) P74 (input)/AN4 (input) Port 7 P73 (input)/AN3 (input) P72 (input)/AN2 (input) P71 (input)/AN1 (input) P70 (input)/AN0 (input) Figure 7.15 Port 7 Pin Configuration 7.8.2 Register Configuration and Descriptions Table 7.15 summarizes the port 7 registers. Port 7 is an input port, so there is no data direction register. Table 7.15 Port 7 Register Name Abbreviation Read/Write Initial Value Address Port 7 input data register P7PIN R Undetermined H'FFBE Note: The port 7 input data register (P7PIN) has the same address as the port B data direction register (PBDDR). 135 Port 7 Input Data Register (P7PIN) Bit 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 Initial value --* --* --* --* --* --* --* --* Read/Write R R R R R R R R Note: * Depends on the levels of pins P77 to P7 0. When P7PIN is read, the pin states are always read. P7PIN is a read-only register and cannot be written to. Write access results in writing to PBDDR. 7.9 Port 8 7.9.1 Overview Port 8 is a 7-bit input/output port that is multiplexed with host interface (HIF) input pins (HA0, GA20, CS1, IOR, IOW, CS2), with input/output pins (TxD1, RxD1, SCK1) of serial communication interface 1, with the I2C clock input/output pin (SCL), and with interrupt input pins (IRQ5 to IRQ3). Figure 7.16 shows the pin configuration of port 8. The configuration of the pin functions of pins P8 5 and P84 will depend on the value of bit STAC in STCR. Pins P86 and P83 to P80 are unaffected by bit STAC. Pins in port 8 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington transistor. Pin P86 can be driven as a bus buffer, as shown in section 13, I2C Bus Interface. 136 Port 8 Port 8 pins Pin configuration in master mode, or when STAC bit is 1 P86/SCK1/IRQ5/SCL P86 (input/output)/IRQ5 (input)/SCK1 (input/output)/SCL (output) P85/RxD1/IRQ4/CS2 P85 (input/output)/IRQ4 (input)/RxD1 (input) P84/TxD1/IRQ3/IOW P84 (input/output)/IRQ3 (input)/TxD1 (output) P83/IOR P83 (input/output) P82/CS1 P82 (input/output) P81/GA20 P81 (input/output) P80/HA0 P80 (input/output) Pin configuration in slave mode When STAC bit is 0 P86 (input/output)/IRQ5 (input)/SCK1 (input/output)/SCL (input/output) IRQ4 (input)/CS2 (input) IRQ3 (input)/IOW (input) IOR (input) CS1 (input) P81 (input/output)/GA20 (output) HA0 (input) Figure 7.16 Port 8 Pin Configuration 7.9.2 Register Configuration and Descriptions Table 7.16 summarizes the port 8 registers. Table 7.16 Port 8 Registers Name Abbreviation Read/Write Initial Value Address Port 8 data direction register P8DDR W H'80 H'FFBD Port 8 data register P8DR R/W H'80 H'FFBF Note: The port 8 data direction register (P8DDR) has the same address as the port B input data register (PBPIN). 137 Port 8 Data Direction Register (P8DDR) Bit 7 -- 6 5 4 3 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value 1 0 0 0 0 0 0 0 Read/Write -- W W W W W W W P8DDR is an 8-bit register that controls the input/output direction of each pin in port 8. A pin functions as an output pin if the corresponding P8DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P8DDR is a write-only register. Read data is invalid. If read, all bits always read 1. Bit 7 is a reserved bit that always reads 1. P8DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode P8DDR retains its existing values, so if a transition to software standby mode occurs while a P8DDR bit is set to 1, the corresponding pin remains in the output state. Port 8 Data Register (P8DR) Bit 7 6 5 4 3 2 1 0 -- P86 P85 P84 P83 P82 P81 P80 Initial value 1 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W P8DR is an 8-bit register that stores data for pins P86 to P80. Bit 7 is a reserved bit that always reads 1. When a P8DDR bit is set to 1, if port 8 is read, the value in P8DR is obtained directly, regardless of the actual pin state. When a P8DDR bit is cleared to 0, if port 8 is read the pin state is obtained. This also applies to pins used by on-chip supporting modules. P8DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 138 7.9.3 Pin Functions Pins P86 to P80 are multiplexed with HIF input/output, SCI1 input/output, I2C clock input/output, and IRQ5 to IRQ3 input. Table 7.17 indicates the functions of pins P86 to P80. Table 7.17 Port 8 Pin Functions Pin Pin Functions and Selection Method P86/IRQ5/ SCK 1/SCL Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, bit ICE in ICCR, and bit P8 6DDR select the pin function as follows ICE 0 CKE1 0 C/A Pin function 1 -- 1 -- -- 1 -- -- -- 0 CKE0 P86DDR 1 0 0 1 -- -- -- -- P86 input P86 output SCK 1 output SCK 1 output SCK 1 intput SCL input/ output IRQ5 input* Note: * IRQ5 input is usable when bit IRQ5E is set to 1 in IER P85/IRQ4/ CS 2/RxD1 Bit RE in SCR of SCI1, bit STAC in STCR, bit P8 5DDR, and the operating mode select the pin function as follows Operating mode Slave mode Not slave mode STAC 0 RE -- P85DDR -- 0 1 -- 0 1 -- CS 2 input P85 input P85 output RxD1 input P85 input P85 output RxD1 input Pin function 1 0 -- 1 0 1 IRQ4 input* Note: * IRQ4 input is usable when bit IRQ4E is set to 1 in IER 139 Pin Pin Functions and Selection Method P84/IRQ3/ IOW/TxD1 Bit TE in SCR of SCI1, bit STAC in STCR, bit P8 4DDR, and the operating mode select the pin function as follows Operating mode Slave mode Not slave mode STAC 0 TE -- P84DDR -- 0 1 -- 0 1 -- IOW input P84 input P84 output TxD1 output P84 input P84 output TxD1 output Pin function 1 0 -- 1 0 1 IRQ3 input* Note: * IRQ3 input is usable when bit IRQ3E is set to 1 in IER P83/IOR Bit P83DDR and the operating mode select the pin function as follows Operating mode Slave mode P83DDR Pin function P82/CS 1 -- 0 1 IOR input P83 input P83 output Bit P82DDR and the operating mode select the pin function as follows Operating mode Slave mode P82DDR Pin function P81/GA 20 0 1 CS 1 input P82 input P82 output Bit P81DDR and the operating mode select the pin function as follows P81DDR 0 FGA20E -- Pin function 1 0 1 -- P81 input Not slave mode P81 output Slave mode GA20 output Bit P80DDR and the operating mode select the pin function as follows Operating mode P80DDR Pin function 140 Not slave mode -- Operating mode P80/HA0 Not slave mode Slave mode Not slave mode -- 0 1 HA 0 input P80 input P80 output 7.10 Port 9 7.10.1 Overview Port 9 is an 8-bit input/output port that is multiplexed with interrupt input pins (IRQ0 to IRQ2), input/output pins for bus control signals (RD, WR, AS, WAIT), an input pin (ADTRG) for the A/D converter, an output pin (o) for the system clock, host interface (HIF) input pins (ECS2, EIOW), and the I2C data input/output pin (SDA). Figure 7.17 shows the pin configuration of port 9. The functions of pins P91 and P90 are configured according to bit STAC in STCR. Pins P97 to P9 2 are unaffected by bit STAC. Pins in port 9 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor. Pin P97 can be driven as a bus buffer, as shown in section 13, I2C Bus Interface. Port 9 Port 9 pins Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) P97/WAIT/SDA P97 (input/output)/WAIT (input)/SDA (input/output) P96/o o (output) P95/AS AS (output) P94/WR WR (output) P93/RD RD (output) P92/IRQ0 P92 (input/output)/IRQ0 (input) Pin configuration in mode 3 (single-chip mode) P97 (input/output)/SDA (input/output) P96 (input)/o (output) P95 (input/output) P94 (input/output) P93 (input/output) P92 (input/output)/IRQ0 (input) Figure 7.17 Port 9 Pin Configuration 141 Port 9 Pin configuration in master mode, or when STAC bit is 0 P91/IRQ1/EIOW P91 (input/output)/IRQ1 (input) P90/IRQ2/ADTRG/ECS2 P90 (input/output)/IRQ2 (input)/ADTRG (input) Pin configuration in slave mode when STAC bit is 1 IRQ1 (input)/EIOW (input) IRQ2 (input)/ECS2 (input) Figure 7.17 Port 9 Pin Configuration (cont) 7.10.2 Register Configuration and Descriptions Table 7.18 summarizes the port 9 registers. Table 7.18 Port 9 Registers Name Abbreviation Read/Write Initial Value Port 9 data direction register P9DDR W H'40 (modes 1 and 2) H'FFC0 H'00 (mode 3) Port 9 data register P9DR R/W*1 Undetermined *2 Notes: *1 Bit 6 is read-only. *2 Bit 6 is undetermined. Other bits are initially 0. 142 Address H'FFC1 Port 9 Data Direction Register (P9DDR) Bit 7 6 5 4 3 2 1 0 P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Modes 1 and 2 Initial value 0 1 0 0 0 0 0 0 Read/Write W -- W W W W W W Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Mode 3 P9DDR is an 8-bit register that controls the input/output direction of each pin in port 9. A pin functions as an output pin if the corresponding P9DDR bit is set to 1, and as an input pin if this bit is cleared to 0. In modes 1 and 2, P96DDR is fixed at 1 and cannot be modified. P9DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P9DDR is initialized by a reset and in hardware standby mode. The initial value is H'40 in modes 1 and 2, and H'00 in mode 3. In software standby mode P9DDR retains its existing values, so if a transition to software standby mode occurs while a P9DDR bit is set to 1, the corresponding pin remains in the output state. Port 9 Data Register (P9DR) Bit 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Initial value 0 --* 0 0 0 0 0 0 Read/Write R/W R R/W R/W R/W R/W R/W R/W Note: * Determined by the level at pin P9 6. P9DR is an 8-bit register that stores data for pins P97 to P90. When a P9DDR bit is set to 1, if port 9 is read, the value in P9DR is obtained directly, regardless of the actual pin state, except for P96. When a P9DDR bit is cleared to 0, if port 9 is read the pin state is obtained. This also applies to pins used by on-chip supporting modules and for bus control signals. P96 always returns the pin state. P9DR pins other than P96 are initialized to 0 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 143 7.10.3 Pin Functions Port 9 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode 3. The pins are multiplexed with IRQ0 to IRQ2 input, bus control signal input/output, A/D converter input, system clock (o) output, host interface input (ECS2, EIOW), and I 2C data input/output (SDA). Table 7.19 indicates the pin functions of port 9. Table 7.19 Port 9 Pin Functions P97/WAIT/SDA Bit ICE in ICCR, bit P97DDR, the wait mode as determined by WSCR, and the operating mode select the pin function as follows Operating mode Wait mode -- 0 1 -- 0 1 -- WAIT input P97 input P97 output SDA input/ output P97 input P97 output SDA input/ output 1 0 1 Bit P96DDR and the operating mode select the pin function as follows Modes 1 and 2 Mode 3 P96DDR Always 1 0 1 Pin function o output P96 input o output Bit P95DDR and the operating mode select the pin function as follows P95DDR Pin function Modes 1 and 2 Mode 3 -- 0 1 AS output P95 input P95 output Bit P94DDR and the operating mode select the pin function as follows Operating mode P94DDR Pin function 144 0 -- P97DDR Operating mode P94/WR WAIT not used -- Operating mode P95/AS WAIT used Mode 3 ICE Pin function P96/o Modes 1 and 2 Modes 1 and 2 Mode 3 -- 0 1 WR output P94 input P94 output Pin Pin Functions and Selection Method P93/RD Bit P93DDR and the operating mode select the pin function as follows Operating mode Modes 1 and 2 P93DDR Pin function Mode 3 -- 0 1 RD output P93 input P93 output P92/IRQ0 P92DDR Pin function 0 1 P92 input P92 output IRQ0 input* Note: * IRQ0 input can be used when bit IRQ0E is set to 1 in IER P91/IRQ1/ EIOW Bit STAC in STCR, bit P9 1DDR, and the operating mode select the pin function as follows Operating mode Slave mode STAC P91DDR Pin function 0 Not slave mode 1 -- 0 1 -- 0 1 P91 input P91 output EIOW input P91 input P91 output IRQ1 input* Note: * IRQ1 input can be used when bit IRQ1E is set to 1 in IER P90/IRQ2/ ADTRG/ECS 2 Bit STAC in STCR, bit P9 0DDR, and the operating mode select the pin function as follows Operating mode Slave mode STAC P90DDR Pin function 0 1 0 P90 input Not slave mode 1 -- P90 output ECS 2 input IRQ2 input and ADTRG input*2 *1 IRQ2 input *1 -- 0 1 P90 input P90 output IRQ2 input*1 and ADTRG input*2 Notes: *1 IRQ2 input can be used when bit IRQ2E is set to 1 in IER *2 ADTRG input can be used when bit TRGE is set to 1 in ADCR 145 7.11 Port A 7.11.1 Overview Port A is an 8-bit input/output port that is multiplexed with key-sense input pins. The port A pin functions are the same in all operating modes. Figure 7.18 shows the pin configuration of port A. Port A has built-in, programming MOS input pull-up transistors. Pins in port A can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor. Pins PA4, PA5, PA6, and PA7 can be driven as bus buffers, as shown in section 13, I2C Bus Interface. Port A pins PA7 (input/output)/KEYIN15 (input) PA6 (input/output)/KEYIN14 (input) PA5 (input/output)/KEYIN13 (input) PA4 (input/output)/KEYIN12 (input) Port A PA3 (input/output)/KEYIN11 (input) PA2 (input/output)/KEYIN10 (input) PA1 (input/output)/KEYIN9 (input) PA0 (input/output)/KEYIN8 (input) Figure 7.18 Port A Pin Configuration 7.11.2 Register Configuration and Descriptions Table 7.20 summarizes the port A registers. Table 7.20 Port A Registers Name Abbreviation Read/Write Initial Value Address Port A data direction register PADDR W H'00 H'FFAB Port A output data register PAODR R/W H'00 H'FFAA Port A input data register PAPIN R Undetermined H'FFAB Note: The data direction register (PADDR) and input data register (PAPIN) have the same address. 146 Port A Data Direction Register (PADDR) Bit 7 6 5 4 3 2 1 0 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PADDR is an 8-bit register that controls the input/output direction of each pin in port A. A pin functions as an output pin if the corresponding PADDR bit is set to 1, and as an input pin if this bit is cleared to 0. PADDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a PADDR bit is set to 1, the corresponding pin remains in the output state. Port A Output Data Register (PAODR) Bit 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PAODR is an 8-bit register that stores data for pins PA7 to PA 0. PAODR can always be written to and read, regardless of the PADDR settings. PAODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port A Input Data Register (PAPIN) Bit 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Initial value --* --* --* --* --* --* --* --* Read/Write R R R R R R R R Note: * Depends on the levels of pins PA 7 to PA 0. When PAPIN is read, the pin states are always read. 147 7.11.3 Pin Functions in Each Mode Port A has the same pin functions in all operating modes. Table 7.21 indicates the pin functions of port A. Table 7.21 Port A Pin Functions Pin Pin Functions and Selection Method PA7/KEYIN15 PA7DDR Pin function 0 1 PA7 input PA7 output KEYIN15 input This pin is driven as a bus buffer when bit IICS is set to 1 in STCR PA6/KEYIN14 PA6DDR Pin function 0 1 PA6 input PA6 output KEYIN14 input This pin is driven as a bus buffer when bit IICS is set to 1 in STCR PA5/KEYIN13 PA5DDR Pin function 0 1 PA5 input PA5 output KEYIN13 input This pin is driven as a bus buffer when bit IICS is set to 1 in STCR PA4/KEYIN12 PA4DDR Pin function 0 1 PA4 input PA4 output KEYIN12 input This pin is driven as a bus buffer when bit IICS is set to 1 in STCR PA3/KEYIN11 PA3DDR Pin function 0 1 PA3 input PA3 output KEYIN11 input 148 Pin Pin Functions and Selection Method PA2/KEYIN10 PA2DDR Pin function 0 1 PA2 input PA2 output KEYIN10 input PA1/KEYIN9 PA1DDR Pin function 0 1 PA1 input PA1 output KEYIN9 input PA0/KEYIN8 PA0DDR Pin function 0 1 PA0 input PA0 output KEYIN8 input 7.11.4 Input Pull-Up Transistors Port A has built-in programmable input pull-up transistors that are available in all modes. An input pull-up transistor is turned on if 1 is written in the corresponding PAODR bit while the corresponding PADDR bit is cleared to 0. The input pull-ups are turned off by a reset and in hardware standby mode. Table 7.22 indicates the states of the input pull-up transistors in each operating mode. Table 7.22 States of Input Pull-Up Transistors (Port A) Mode Reset Hardware Standby Software Standby Other Operating Modes 1 Off Off On/off On/off 2 Off Off On/off On/off 3 Off Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if PAODR = 1 and PADDR = 0, but off otherwise. 149 7.12 Port B 7.12.1 Overview Port B is an 8-bit input/output port that is multiplexed with the host interface data bus. The pin functions differ depending on the operating mode. Figure 7.19 shows the pin configuration of port B. Port B has program-controllable built-in MOS input pull-up transistors. Pins in port B can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington transistor. Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) Port B Port B pins Master mode Slave mode PB7/XDB7 PB7 (input/output) XDB7 (input/output) PB6/XDB6 PB6 (input/output) XDB6 (input/output) PB5/XDB5 PB5 (input/output) XDB5 (input/output) PB4/XDB4 PB4 (input/output) XDB4 (input/output) PB3/XDB3 PB3 (input/output) XDB3 (input/output) PB2/XDB2 PB2 (input/output) XDB2 (input/output) PB1/XDB1 PB1 (input/output) XDB1 (input/output) PB0/XDB0 PB0 (input/output) XDB0 (input/output) Pin configuration in mode 3 (single-chip mode) PB7 (input/output) PB6 (input/output) PB5 (input/output) PB4 (input/output) PB3 (input/output) PB2 (input/output) PB1 (input/output) PB0 (input/output) Figure 7.19 Port B Pin Configuration 150 7.12.2 Register Configuration and Descriptions Table 7.23 summarizes the port B registers. Table 7.23 Port B Registers Name Abbreviation Read/Write Initial Value Address Port B data direction register PBDDR W H'00 H'FFBE Port B output data register PBODR R/W H'00 H'FFBC Port B input data register PBPIN R Undetermind H'FFBD Note: The port B data direction register (PBDDR) and port 7 input data register 7 (P7PIN) have the same address. Port B Data Direction Register (PBDDR) Bit 7 6 5 4 3 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W PBDDR is an 8-bit register that controls the input/output direction of each pin in port B. A pin functions as an output pin if the corresponding PBDDR bit is set to 1, and as an input pin if this bit is cleared to 0. PBDDR is a write-only register. Read data is invalid. If read, the values of the port 7 data input register (P7PIN) are returned, indicating the pin levels of port 7. PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a PBDDR bit is set to 1, the corresponding pin remains in the output state. 151 Port B Output Data Register (PBODR) Bit 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PBODR is an 8-bit register that stores data for pins PB7 to PB0. PBODR can always be written to and read, regardless of the PBDDR settings. PBODR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port B Input Data Register (PBPIN) Bit 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value --* --* --* --* --* --* --* --* Read/Write R R R R R R R R Note: * Depends on the levels of pins PB 7 to PB 0. When PBPIN is read, the pin states are always read. 152 7.12.3 Pin Functions in Each Mode Port B has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), when the host interface enable bit (HIE) is cleared to 0 in the system control register (SYSCR), port B is a general-purpose input/output port. When the HIE bit is set to 1, selecting slave mode, port B becomes the host interface data bus (XDB7 to XDB0). PBODR and PBDDR should be cleared to H'00 in slave mode. For details, see section 14, Host Interface. Figure 7.20 shows the pin functions in modes 1 and 2. PB7 (input/output)/XDB7 (input/output) PB6 (input/output)/XDB6 (input/output) PB5 (input/output)/XDB5 (input/output) Port B PB4 (input/output)/XDB4 (input/output) PB3 (input/output)/XDB3 (input/output) PB2 (input/output)/XDB2 (input/output) PB1 (input/output)/XDB1 (input/output) PB0 (input/output)/XDB0 (input/output) Figure 7.20 Pin Functions in Modes 1 and 2 (Port B) 153 Pin Functions in Mode 3: In mode 3 (single-chip mode), each pin can be designated for general input or output. A pin becomes an output pin when its PBDDR bit is set to 1, and an input pin when this bit is cleared to 0. Figure 7.21 shows the pin functions in mode 3. Mode 3 PB7 (input/output) PB6 (input/output) PB5 (input/output) Port B PB4 (input/output) PB3 (input/output) PB2 (input/output) PB1 (input/output) PB0 (input/output) Figure 7.21 Pin Functions in Mode 3 (Port B) 7.12.4 Input Pull-Up Transistors Port B has built-in programmable input pull-up transistors that are available in mode 3. The pullup for each bit can be turned on and off individually. An input pull-up transistor is turned on in mode 3 if 1 is written in the corresponding PBODR bit while the corresponding PBDDR bit is cleared to 0. The input pull-ups are turned off by a reset and in hardware standby mode. In software standby mode, the previous state is maintained. Table 7.24 indicates the states of the input pull-up transistors in each operating mode. Table 7.24 States of Input Pull-Up Transistors (Port B) Mode Reset Hardware Standby Software Standby Other Operating Modes 1 Off Off On/off On/off 2 Off Off On/off On/off 3 Off Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if PBDR = 1 and PBDDR = 0, but off otherwise. 154 Section 8 16-Bit Free-Running Timer 8.1 Overview The H8/3437 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit freerunning counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 8.1.1 Features The features of the free-running timer module are listed below. * Selection of four clock sources The free-running counter can be driven by an internal clock source (oP/2, oP/8, or oP/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each comparator can generate an independent waveform. * Four input capture channels The current count can be captured on the rising or falling edge (selectable) of an input signal. The four input capture registers can be used separately, or in a buffer mode. * Counter can be cleared under program control The free-running counters can be cleared on compare-match A. * Seven independent interrupts Compare-match A and B, input capture A to D, and overflow interrupts are requested independently. 155 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the free-running timer. Internal clock sources oP/2 oP/8 oP/32 External clock source FTCI Clock select Clock OCRA (H/L) Comparematch A Comparator A FTOA Overflow FTOB Clear Comparator B OCRB (H/L) Control logic Capture FTIA ICRA (H/L) ICRB (H/L) FTIB Internal data bus Module data bus Comparematch B Bus interface FRC (H/L) ICRC (H/L) FTIC ICRD (H/L) FTID TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Legend: FRC: OCRA, B: ICRA, B, C, D: TCSR: Interrupt signals Free-running counter (16 bits) Output compare register A, B (16 bits) Input capture register A, B, C, D (16 bits) Timer control/status register (8 bits) TIER: Timer interrupt enable register (8 bits) TCR: Timer control register (8 bits) TOCR: Timer output compare control register (8 bits) Figure 8.1 Block Diagram of 16-Bit Free-Running Timer 156 8.1.3 Input and Output Pins Table 8.1 lists the input and output pins of the free-running timer module. Table 8.1 Input and Output Pins of Free-Running Timer Module Name Abbreviation I/O Function Counter clock input FTCI Input Input of external free-running counter clock signal Output compare A FTOA Output Output controlled by comparator A Output compare B FTOB Output Output controlled by comparator B Input capture A FTIA Input Trigger for capturing current count into input capture register A Input capture B FTIB Input Trigger for capturing current count into input capture register B Input capture C FTIC Input Trigger for capturing current count into input capture register C Input capture D FTID Input Trigger for capturing current count into input capture register D 157 8.1.4 Register Configuration Table 8.2 lists the registers of the free-running timer module. Table 8.2 Register Configuration Name Abbreviation R/W Timer interrupt enable register TIER R/W *1 Initial Value Address H'01 H'FF90 Timer control/status register TCSR R/(W) H'00 H'FF91 Free-running counter (high) FRC (H) R/W H'00 H'FF92 FRC (L) R/W H'00 H'FF93 OCRA/B (H) R/W H'FF H'FF94*2 Output compare register A/B (low)*2 OCRA/B (L) R/W H'FF H'FF95*2 Timer control register TCR R/W H'00 H'FF96 Timer output compare control register TOCR R/W H'E0 H'FF97 Input capture register A (high) ICRA (H) R H'00 H'FF98 Input capture register A (low) ICRA (L) R H'00 H'FF99 Input capture register B (high) ICRB (H) R H'00 H'FF9A Input capture register B (low) ICRB (L) R H'00 H'FF9B Input capture register C (high) ICRC (H) R H'00 H'FF9C Input capture register C (low) ICRC (L) R H'00 H'FF9D Input capture register D (high) ICRD (H) R H'00 H'FF9E Input capture register D (low) ICRD (L) R H'00 H'FF9F Free-running counter (low) Output compare register A/B (high) *2 Notes: *1 Software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits. *2 OCRA and OCRB share the same addresses. Access is controlled by the OCRS bit in TOCR. 158 8.2 Register Descriptions 8.2.1 Free-Running Counter (FRC) Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the timer control register (TCR). When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. Because FRC is a 16-bit register, a temporary register (TEMP) is used when FRC is written or read. See section 8.3, CPU Interface, for details. FRC is initialized to H'0000 by a reset and in the standby modes. 8.2.2 Output Compare Registers A and B (OCRA and OCRB) Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR). In addition, if the output enable bit (OEA or OEB) in the timer output compare control register (TOCR) is set to 1, when the output compare register and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCRA and OCRB share the same address. They are differentiated by the OCRS bit in TOCR. A temporary register (TEMP) is used for write access, as explained in section 8.3, CPU Interface. OCRA and OCRB are initialized to H'FFFF by a reset and in the standby modes. 159 8.2.3 Input Capture Registers A to D (ICRA to ICRD) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R There are four input capture registers A to D, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected, the current FRC value is copied to the corresponding input capture register (ICRA to ICRD).* At the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in the timer control register (TCR). Note: * The FRC contents are transferred to the input capture register regardless of the value of the input capture flag (ICFA/B/C/D). Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in TCR is set to 1, ICRC is used as a buffer register for ICRA as shown in figure 8.2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and the new FRC count is copied into ICRA. BUFEA IEDGA IEDGC FTIA Edge detect and capture signal generating circuit ICRC BUFEA: IEDGA: IEDGC: ICRC: ICRA: FRC: ICRA Buffer enable A Input edge select A Input edge select C Input capture register C Input capture register A Free-running counter Figure 8.2 Input Capture Buffering (Example) 160 FRC Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB. When input capture is buffered, if the two input edge bits are set to different values (IEDGA IEDGC or IEDGB IEDGD), then input capture is triggered on both the rising and falling edges of the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA = IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge. See table 8.3. Table 8.3 Buffered Input Capture Edge Selection (Example) IEDGA IEDGC Input Capture Edge 0 0 Captured on falling edge of input capture A (FTIA) 1 Captured on both rising and falling edges of input capture A (FTIA) 1 (Initial value) 0 1 Captured on rising edge of input capture A (FTIA) Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when they are read. See section 8.3, CPU Interface, for details. To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods (1.5*o). When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. The input capture registers are initialized to H'0000 by a reset and in the standby modes. 161 8.2.4 Timer Interrupt Enable Register (TIER) Bit 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE -- Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W -- TIER is an 8-bit readable/writable register that enables and disables interrupts. TIER is initialized to H'01 by a reset and in the standby modes. Bit 7--Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register (TCSR) is set to 1. Bit 7: ICIAE Description 0 Input capture interrupt request A (ICIA) is disabled. 1 Input capture interrupt request A (ICIA) is enabled. (Initial value) Bit 6--Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. Bit 6: ICIBE Description 0 Input capture interrupt request B (ICIB) is disabled. 1 Input capture interrupt request B (ICIB) is enabled. (Initial value) Bit 5--Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. Bit 5: ICICE Description 0 Input capture interrupt request C (ICIC) is disabled. 1 Input capture interrupt request C (ICIC) is enabled. (Initial value) Bit 4--Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1. Bit 4: ICIDE Description 0 Input capture interrupt request D (ICID) is disabled. 1 Input capture interrupt request D (ICID) is enabled. 162 (Initial value) Bit 3--Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. Bit 3: OCIAE Description 0 Output compare interrupt request A (OCIA) is disabled. 1 Output compare interrupt request A (OCIA) is enabled. (Initial value) Bit 2--Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. Bit 2: OCIBE Description 0 Output compare interrupt request B (OCIB) is disabled. 1 Output compare interrupt request B (OCIB) is enabled. (Initial value) Bit 1--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a freerunning timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. Bit 1: OVIE Description 0 Timer overflow interrupt request (FOVI) is disabled. 1 Timer overflow interrupt request (FOVI) is enabled. (Initial value) Bit 0--Reserved: This bit cannot be modified and is always read as 1. 163 8.2.5 Timer Control/Status Register (TCSR) Bit 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/W Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits. TCSR is an 8-bit readable and partially writable register that contains the seven interrupt flags and specifies whether to clear the counter on compare-match A (when the FRC and OCRA values match). TCSR is initialized to H'00 by a reset and in the standby modes. Timing is described in section 8.4, Operation. Bit 7--Input Capture Flag A (ICFA): This status bit is set to 1 to flag an input capture A event. If BUFEA = 0, ICFA indicates that the FRC value has been copied to ICRA. If BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been copied to ICRA. ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 7: ICFA Description 0 To clear ICFA, the CPU must read ICFA after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when an FTIA input signal causes the FRC value to be copied to ICRA. Bit 6--Input Capture Flag B (ICFB): This status bit is set to 1 to flag an input capture B event. If BUFEB = 0, ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been copied to ICRB. ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 6: ICFB Description 0 To clear ICFB, the CPU must read ICFB after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when an FTIB input signal causes the FRC value to be copied to ICRB. 164 Bit 5--Input Capture Flag C (ICFC): This status bit is set to 1 to flag input of a rising or falling edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC count in ICRC. When BUFEA = 1, however, the FRC count is not captured, so ICFC becomes simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a generalpurpose interrupt signal (which can be enabled or disabled by the ICICE bit). ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5: ICFC Description 0 To clear ICFC, the CPU must read ICFC after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when an FTIC input signal is received. Bit 4--Input Capture Flag D (ICFD): This status bit is set to 1 to flag input of a rising or falling edge of FTID as selected by the IEDGD bit. When BUFEB = 0, this indicates capture of the FRC count in ICRD. When BUFEB = 1, however, the FRC count is not captured, so ICFD becomes simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a generalpurpose interrupt signal (which can be enabled or disabled by the ICIDE bit). ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 4: ICFD Description 0 To clear ICFD, the CPU must read ICFD after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when an FTID input signal is received. Bit 3--Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches the OCRA value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 3: OCFA Description 0 To clear OCFA, the CPU must read OCFA after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when FRC = OCRA. 165 Bit 2--Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 2: OCFB Description 0 To clear OCFB, the CPU must read OCFB after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when FRC = OCRB. Bit 1--Timer Overflow Flag (OVF): This status flag is set to 1 when FRC overflows (changes from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 1: OVF Description 0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when FRC changes from H'FFFF to H'0000. Bit 0--Counter Clear A (CCLRA): This bit selects whether to clear FRC at compare-match A (when the FRC and OCRA values match). Bit 0: CCLRA Description 0 The FRC is not cleared. 1 The FRC is cleared at compare-match A. 8.2.6 (Initial value) Timer Control Register (TCR) Bit 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. TCR is initialized to H'00 by a reset and in the standby modes. 166 Bit 7--Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input capture A signal (FTIA). Bit 7: IEDGA Description 0 Input capture A events are recognized on the falling edge of FTIA. (Initial value) 1 Input capture A events are recognized on the rising edge of FTIA. Bit 6--Input Edge Select B (IEDGB): This bit selects the rising or falling edge of the input capture B signal (FTIB). Bit 6: IEDGB Description 0 Input capture B events are recognized on the falling edge of FTIB. (Initial value) 1 Input capture B events are recognized on the rising edge of FTIB. Bit 5--Input Edge Select C (IEDGC): This bit selects the rising or falling edge of the input capture C signal (FTIC). Bit 5: IEDGC Description 0 Input capture C events are recognized on the falling edge of FTIC. (Initial value) 1 Input capture C events are recognized on the rising edge of FTIC. Bit 4--Input Edge Select D (IEDGD): This bit selects the rising or falling edge of the input capture D signal (FTID). Bit 4: IEDGD Description 0 Input capture D events are recognized on the falling edge of FTID. (Initial value) 1 Input capture D events are recognized on the rising edge of FTID. Bit 3--Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for ICRA. Bit 3: BUFEA Description 0 ICRC is used for input capture C. 1 ICRC is used as a buffer register for input capture A. (Initial value) 167 Bit 2--Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for ICRB. Bit 2: BUFEB Description 0 ICRD is used for input capture D. 1 ICRD is used as a buffer register for input capture B. (Initial value) Bits 1 and 0--Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for FRC. External clock pulses are counted on the rising edge of signals input to pin FTCI. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 oP/2 internal clock source 1 oP/8 internal clock source 0 oP/32 internal clock source 1 External clock source (rising edge) 1 8.2.7 (Initial value) Timer Output Compare Control Register (TOCR) Bit 7 6 5 4 3 2 1 0 -- -- -- OCRS OEA OEB OLVLA OLVLB Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W TOCR is an 8-bit readable/writable register that enables output from the output compare pins, selects the output levels, and switches access between output compare registers A and B. TOCR is initialized to H'E0 by a reset and in the standby modes. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bit 4--Output Compare Register Select (OCRS): OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. This bit does not affect the operation of OCRA or OCRB. Bit 4: OCRS Description 0 OCRA is selected. 1 OCRB is selected. 168 (Initial value) Bit 3--Output Enable A (OEA): This bit enables or disables output of the output compare A signal (FTOA). Bit 3: OEA Description 0 Output compare A output is disabled. 1 Output compare A output is enabled. (Initial value) Bit 2--Output Enable B (OEB): This bit enables or disables output of the output compare B signal (FTOB). Bit 2: OEB Description 0 Output compare B output is disabled. 1 Output compare B output is enabled. (Initial value) Bit 1--Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match. Bit 1: OLVLA Description 0 A 0 logic level is output for compare-match A. 1 A 1 logic level is output for compare-match A. (Initial value) Bit 0--Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin when the FRC and OCRB values match. Bit 0: OLVLB Description 0 A 0 logic level is output for compare-match B. 1 A 1 logic level is output for compare-match B. (Initial value) 169 8.3 CPU Interface The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows: * Register Write When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously. * Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. Programs that access these registers should normally use word access. Equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. Figure 8.3 shows the data flow when FRC is accessed. The other registers are accessed in the same way. As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes directly, without using TEMP. Coding Examples To write the contents of general register R0 to OCRA: To transfer the contents of ICRA to general register R0: 170 MOV.W MOV.W R0, @OCRA @ICRA, R0 (1) Upper byte write Module data bus Bus interface CPU writes data H'AA TEMP [H'AA] FRCH [ ] FRCL [ ] (2) Lower byte write CPU writes data H'55 Module data bus Bus interface TEMP [H'AA] FRCH [H'AA] FRCL [H'55] Figure 8.3 (a) Write Access to FRC (when CPU Writes H'AA55) 171 (1) Upper byte read Module data bus Bus interface CPU reads data H'AA TEMP [H'55] FRCH [H'AA] FRCL [H'55] (2) Lower byte read CPU reads data H'55 Module data bus Bus interface TEMP [H'55] FRCH [ ] FRCL [ ] Figure 8.3 (b) Read Access to FRC (when FRC Contains H'AA55) 172 8.4 Operation 8.4.1 FRC Increment Timing FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. The clock source is selected by bits CKS0 and CKS1 in TCR. Internal Clock: The internal clock sources (oP/2, oP/8, oP/32) are created from the system clock (o) by a prescaler. FRC increments on a pulse generated from the falling edge of the prescaler output. See figure 8.4. o Internal clock FRC clock pulse FRC N-1 N N+1 Figure 8.4 Increment Timing for Internal Clock Source 173 External Clock: If external clock input is selected, FRC increments on the rising edge of the FTCI clock signal. Figure 8.5 shows the increment timing. The pulse width of the external clock signal must be at least 1.5 system clock (o) periods. The counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. o External clock FRC clock pulse FRC N N+1 Figure 8.5 Increment Timing for External Clock Source 174 8.4.2 Output Compare Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 8.6 shows the timing of this operation for compare-match A. o FRC N N+1 OCRA N N+1 N N Internal comparematch A signal Clear* OLVLA FTOA Note: * Cleared by software Figure 8.6 Timing of Output Compare A 175 8.4.3 FRC Clear Timing If the CCLRA bit in TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure 8.7 shows the timing of this operation. o Internal comparematch A signal FRC N H'0000 Figure 8.7 Clearing of FRC by Compare-Match A 8.4.4 Input Capture Timing Input Capture Timing: An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding IEDGx bit in TCR. Figure 8.8 shows the usual input capture timing when the rising edge is selected (IEDGx = 1). o Input data FTI pin Internal input capture signal Figure 8.8 Input Capture Timing (Usual Case) If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one state. Figure 8.9 shows the timing for this case. 176 ICR upper byte read cycle T1 T2 T3 o Input at FTI pin Internal input capture signal Figure 8.9 Input Capture Timing (1-State Delay Due to ICRA/B/C/D Read) Buffered Input Capture Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 8.10 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. o FTIA Internal input capture signal FRC n ICRA M ICRC m n+1 N N+1 n n N M M n Figure 8.10 Buffered Input Capture with Both Edges Selected 177 When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if the upper byte of either of the two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives, input capture is delayed by one system clock (o). Figure 8.11 shows the timing when BUFEA = 1. Read cycle: CPU reads upper byte of ICRA or ICRC T1 T2 T3 o Input at FTIA pin Internal input capture signal Figure 8.11 Input Capture Timing (1-State Delay, Buffer Mode) 178 8.4.5 Timing of Input Capture Flag (ICF) Setting The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. Figure 8.12 shows the timing of this operation. o Internal input capture signal ICF FRC ICR N N Figure 8.12 Setting of Input Capture Flag 8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB) The output compare flags are set to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 8.13 shows the timing of the setting of the output compare flags. 179 o FRC N N+1 N OCRA or OCRB Internal comparematch signal OCFA or OCFB Figure 8.13 Setting of Output Compare Flags 8.4.7 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 8.14 shows the timing of this operation. o FRC H'FFFF H'0000 Internal overflow signal OVF Figure 8.14 Setting of Overflow Flag (OVF) 180 8.5 Interrupts The free-running timer can request seven interrupts (three types): input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 8.4 lists information about these interrupts. Table 8.4 Free-Running Timer Interrupts Interrupt Description Priority ICIA Requested by ICFA High ICIB Requested by ICFB ICIC Requested by ICFC ICID Requested by ICFD OCIA Requested by OCFA OCIB Requested by OCFB FOVI Requested by OVF Low 181 8.6 Sample Application In the example below, the free-running timer is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: 1. The CCLRA bit in TCSR is set to 1. 2. Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TOCR (OLVLA or OLVLB). FRC H'FFFF Clear counter OCRA OCRB H'0000 FTOA FTOB Figure 8.15 Square-Wave Output (Example) 182 8.7 Application Notes Application programmers should note that the following types of contention can occur in the freerunning timer. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. Figure 8.16 shows this type of contention. Write cycle: CPU write to lower byte of FRC T1 T2 T3 o Internal address bus FRC address Internal write signal FRC clear signal FRC N H'0000 Figure 8.16 FRC Write-Clear Contention 183 Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and FRC is not incremented. Figure 8.17 shows this type of contention. Write cycle: CPU write to lower byte of FRC T1 T2 T3 o Internal address bus FRC address Internal write signal FRC clock pulse FRC N M Write data Figure 8.17 FRC Write-Increment Contention 184 Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the compare-match signal is inhibited. Figure 8.18 shows this type of contention. Write cycle: CPU write to lower byte of OCRA or OCRB T1 T2 T3 o Internal address bus OCR address Internal write signal FRC N OCRA or OCRB N N+1 M Write data Compare-match A or B signal Inhibited Figure 8.18 Contention between OCR Write and Compare-Match 185 Increment Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 8.5. The pulse that increments FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 8.5, the changeover generates a falling edge that triggers the FRC increment clock pulse. Switching between an internal and external clock source can also cause FRC to increment. Table 8.5 Effect of Changing Internal Clock Sources No. Description 1 Low low: CKS1 and CKS0 are rewritten while both clock sources are low. Timing Old clock source New clock source FRC clock pulse FRC N+1 N CKS rewrite 2 Low high: CKS1 and CKS0 are rewritten while old clock source is low and new clock source is high. Old clock source New clock source FRC clock pulse FRC N N+1 N+2 CKS rewrite 186 No. Description 3 High low: CKS1 and CKS0 are rewritten while old clock source is high and new clock source is low. Timing Old clock source New clock source * FRC clock pulse FRC N N+1 N+2 CKS rewrite 4 High high: CKS1 and CKS0 are rewritten while both clock sources are high. Old clock source New clock source FRC clock pulse FRC N N+1 N+2 CKS rewrite Note: * The switching of clock sources is regarded as a falling edge that increments FRC. 187 188 Section 9 8-Bit Timers 9.1 Overview The H8/3437 Series includes an 8-bit timer module with two channels (numbered 0 and 1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One of the many applications of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle. 9.1.1 Features The features of the 8-bit timer module are listed below. * Selection of seven clock sources The counters can be driven by one of six internal clock signals or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two time constants The timer output signal in each channel is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty cycle, or PWM waveforms. * Three independent interrupts Compare-match A and B and overflow interrupts can be requested independently. 189 9.1.2 Block Diagram Figure 9.1 shows a block diagram of one channel in the 8-bit timer module. External clock source Internal clock sources Channel 0 oP/2 oP/8 oP/32 oP/64 oP/256 oP/1024 TMCI Clock select Clock Channel 1 oP/2 oP/8 oP/64 oP/128 oP/1024 oP/2048 TCORA Compare-match A TMO TCNT Clear Comparator B Control logic Compare-match B Module data bus Overflow TMRI TCORB TCSR TCR CMIA CMIB OVI Interrupt signals TCR: TCSR: TCORA: TCORB: TCNT: Timer control register (8 bits) Timer control status register (8 bits) Time constant register A (8 bits) Time constant register B (8 bits) Timer counter Figure 9.1 Block Diagram of 8-Bit Timer (1 Channel) 190 Bus interface Comparator A Internal data bus 9.1.3 Input and Output Pins Table 9.1 lists the input and output pins of the 8-bit timer. Table 9.1 Input and Output Pins of 8-Bit Timer Abbreviation* Name Channel 0 Channel 1 I/O Function Timer output TMO0 TMO1 Output Output controlled by compare-match Timer clock input TMCI0 TMCI1 Input External clock source for the counter Timer reset input TMRI0 TMRI1 Input External reset signal for the counter Note: * In this manual, the channel subscript has been deleted, and only TMO TMCI, and TMRI are used. 9.1.4 Register Configuration Table 9.2 lists the registers of the 8-bit timer module. Each channel has an independent set of registers. Table 9.2 8-Bit Timer Registers Channel Name Abbreviation R/W Initial Value Address 0 Timer control register TCR R/W H'00 H'FFC8 Timer control/status register TCSR R/(W)* H'10 H'FFC9 Time constant register A TCORA R/W H'FF H'FFCA Time constant register B TCORB R/W H'FF H'FFCB Timer counter TCNT R/W H'00 H'FFCC Timer control register TCR R/W H'00 H'FFD0 Timer control/status register TCSR R/(W)* H'10 H'FFD1 Time constant register A TCORA R/W H'FF H'FFD2 Time constant register B TCORB R/W H'FF H'FFD3 Timer counter TCNT R/W H'00 H'FFD4 Serial/timer control register STCR R/W H'00 H'FFC3 1 0, 1 Note: * Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits. 191 9.2 Register Descriptions 9.2.1 Timer Counter (TCNT) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer control register (TCR). The CPU can always read or write the timer counter. The timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer control register select the method of clearing. When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. The timer counters are initialized to H'00 by a reset and in the standby modes. 9.2.2 Time Constant Registers A and B (TCORA and TCORB) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with the constants written in these registers (except during the T3 state of a write cycle to TCORA or TCORB). When a match is detected, the corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register (TCSR). The timer output signal is controlled by these compare-match signals as specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR). TCORA and TCORB are initialized to H'FF by a reset and in the standby modes. 192 9.2.3 Timer Control Register (TCR) Bit 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCR is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. TCR is initialized to H'00 by a reset and in the standby modes. For timing diagrams, see section 9.3, Operation. Bit 7--Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer control/status register (TCSR) is set to 1. Bit 7: CMIEB Description 0 Compare-match interrupt request B (CMIB) is disabled. 1 Compare-match interrupt request B (CMIB) is enabled. (Initial value) Bit 6--Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in TCSR is set to 1. Bit 6: CMIEA Description 0 Compare-match interrupt request A (CMIA) is disabled. 1 Compare-match interrupt request A (CMIA) is enabled. (Initial value) 193 Bit 5--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in TCSR is set to 1. Bit 5: OVIE Description 0 The timer overflow interrupt request (OVI) is disabled. 1 The timer overflow interrupt request (OVI) is enabled. (Initial value) Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer counter is cleared: by compare-match A or B or by an external reset input (TMRI). Bit 4: CCLR1 Bit 3: CCLR0 Description 0 0 Not cleared. 1 Cleared on compare-match A. 0 Cleared on compare-match B. 1 Cleared on rising edge of external reset input signal. 1 194 (Initial value) Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the timer counter. Six internal clock sources, derived by prescaling the system clock, are available for each timer channel. For internal clock sources the counter is incremented on the falling edge of the internal clock. For an external clock source, these bits can select whether to increment the counter on the rising or falling edge of the clock input (TMCI), or on both edges. TCR STCR Channel Bit 2: Bit 1: Bit 0: CKS2 CKS1 CKS0 Bit 1: Bit 0: ICKS1 ICKS0 Description 0 0 -- 0 0 1 1 0 1 1 0 1 1 0 0 1 0 0 1 No clock source (timer stopped) (Initial value) 0 oP/8 internal clock, counted on falling edge 1 oP/2 internal clock, counted on falling edge 0 oP/64 internal clock, counted on falling edge 1 oP/32 internal clock, counted on falling edge 0 oP/1024 internal clock, counted on falling edge 1 oP/256 internal clock, counted on falling edge -- No clock source (timer stopped) 1 External clock source, counted on rising edge 0 External clock source, counted on falling edge 1 External clock source, counted on both rising and falling edges 0 -- 1 0 oP/8 internal clock, counted on falling edge 1 oP/2 internal clock, counted on falling edge 0 oP/64 internal clock, counted on falling edge 1 oP/128 internal clock, counted on falling edge 0 oP/1024 internal clock, counted on falling edge 1 oP/2048 internal clock, counted on falling edge -- No clock source (timer stopped) 0 1 1 -- 0 -- No clock source (timer stopped) (Initial value) 1 External clock source, counted on rising edge 0 External clock source, counted on falling edge 1 External clock source, counted on both rising and falling edges 195 9.2.4 Timer Control/Status Register (TCSR) Bit 7 6 5 4 3 2 1 0 CMFB CMFA OVF -- OS3 OS2 OS1 OS0 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* -- R/W R/W R/W R/W Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. TCSR is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal. TCSR is initialized to H'10 by a reset and in the standby modes. Bit 7--Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count matches the time constant set in TCORB. CMFB must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 7: CMFB Description 0 To clear CMFB, the CPU must read CMFB after it has been set to 1 then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when TCNT = TCORB. Bit 6--Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count matches the time constant set in TCORA. CMFA must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 6: CMFA Description 0 To clear CMFA, the CPU must read CMFA after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when TCNT = TCORA. Bit 5--Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows (changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5: OVF Description 0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when TCNT changes from H'FF to H'00. 196 Bit 4--Reserved: This bit is always read as 1. It cannot be written. Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of TCOR-TCNT compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on the output level. If compare-match A and B occur simultaneously, any conflict is resolved according to the following priority order: toggle > 1 output > 0 output. When all four output select bits are cleared to 0 the timer output signal is disabled. After a reset, the timer output is 0 until the first compare-match event. Bit 3: OS3 Bit 2: OS2 Description 0 0 No change when compare-match B occurs. 1 Output changes to 0 when compare-match B occurs. 0 Output changes to 1 when compare-match B occurs. 1 Output inverts (toggles) when compare-match B occurs. Bit 1: OS1 Bit 0: OS0 Description 0 0 No change when compare-match A occurs. 1 Output changes to 0 when compare-match A occurs. 0 Output changes to 1 when compare-match A occurs. 1 Output inverts (toggles) when compare-match A occurs. 1 1 (Initial value) (Initial value) 197 9.2.5 Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICD IICX IICE STAC MPE ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls the I 2C bus interface and host interface, controls the operating mode of the serial communication interface, and selects internal clock sources for the timer counters. STCR is initialized to H'00 by a reset. Bits 7 to 4--I2C Control (IICS, IICD, IICX, IICE): These bits control operation of the I2C bus interface. For details, see section 13, I2C Bus Interface. Bit 3--Slave Input Switch (STAC): Controls the switching of the host interface input pins. For details, see section 14, Host Interface. Bit 2--Multiprocessor Enable (MPE): Controls the operating mode of serial communication interfaces 0 and 1. For details, see section 12, Serial Communication Interface. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits and bits CKS2 to CKS0 in the TCR select clock sources for the timer counters. For details, see section 9.2.3, Timer Control Register. 198 9.3 Operation 9.3.1 TCNT Increment Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Internal clock sources are created from the system clock by a prescaler. The counter increments on an internal TCNT clock pulse generated from the falling edge of the prescaler output, as shown in figure 9.2. Bits CKS2 to CKS0 of TCR and bits ICKS1 and ICKS0 of STCR can select one of the six internal clocks. o Internal clock TCNT clock pulse TCNT N-1 N N+1 Figure 9.2 Count Timing for Internal Clock Input 199 External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. Figure 9.3 shows incrementation on both edges of the external clock signal. The external clock pulse width must be at least 1.5 system clock (o) periods for incrementation on a single edge, and at least 2.5 system clock periods for incrementation on both edges. The counter will not increment correctly if the pulse width is shorter than these values. o External clock source (TMCI) TCNT clock pulse TCNT N-1 N Figure 9.3 Count Timing for External Clock Input 200 N+1 9.3.2 Compare-Match Timing Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in TCORA or TCORB. The compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 9.4 shows the timing of the setting of the compare-match flags. o TCNT TCOR N N+1 N Internal comparematch signal CMF Figure 9.4 Setting of Compare-Match Flags 201 Output Timing: When a compare-match event occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 9.5 shows the timing when the output is set to toggle on compare-match A. o Internal comparematch A signal Timer output (TMO) Figure 9.5 Timing of Timer Output Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 9.6 shows the timing of this operation. o Internal comparematch signal TCNT N Figure 9.6 Timing of Compare-Match Clear 202 H'00 9.3.3 External Reset of TCNT When the CCLR1 and CCLR0 bits in TCR are both set to 1, the timer counter is cleared on the rising edge of an external reset input. Figure 9.7 shows the timing of this operation. The timer reset pulse width must be at least 1.5 system clock (o) periods. o External reset input (TMRI) Internal clear pulse TCNT N-1 N H'00 Figure 9.7 Timing of External Reset 9.3.4 Setting of TCSR Overflow Flag (OVF) The overflow flag (OVF) is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 9.8 shows the timing of this operation. o TCNT H'FF H'00 Internal overflow signal OVF Figure 9.8 Setting of Overflow Flag (OVF) 203 9.4 Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt can be enabled or disabled by an enable bit in TCR. Independent signals are sent to the interrupt controller for each interrupt. Table 9.3 lists information about these interrupts. Table 9.3 8-Bit Timer Interrupts Interrupt Description Priority CMIA Requested by CMFA High CMIB Requested by CMFB OVI Requested by OVF 9.5 Low Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: 1. In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. 2. In TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-match A and to 0 on compare-match B. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF Clear counter TCORA TCORB H'00 TMO pin Figure 9.9 Example of Pulse Output 204 9.6 Application Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. 9.6.1 Contention between TCNT Write and Clear If an internal counter clear signal is generated during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. Figure 9.10 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 9.10 TCNT Write-Clear Contention 205 9.6.2 Contention between TCNT Write and Increment If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 9.11 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus TCNT address Internal write signal TCNT clock pulse TNCT N M Write data Figure 9.11 TCNT Write-Increment Contention 206 9.6.3 Contention between TCOR Write and Compare-Match If a compare-match occurs during the T3 state of a write cycle to TCOR, the write takes priority and the compare-match signal is inhibited. Figure 9.12 shows this type of contention. Write cycle: CPU writes to TCOR T1 T2 T3 o Internal address bus TCOR address Internal write signal TCNT N TCOR N N+1 M TCOR write data Compare-match A or B signal Inhibited Figure 9.12 Contention between TCOR Write and Compare-Match 207 9.6.4 Contention between Compare-Match A and Compare-Match B If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by following the priority order in table 9.4. Table 9.4 Priority of Timer Output Output Selection Priority Toggle High 1 output 0 output No change 9.6.5 Low Increment Caused by Changing of Internal Clock Source When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten, as shown in table 9.5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 9.5, the changeover generates a falling edge that triggers the TCNT clock pulse and increments the timer counter. Switching between an internal and external clock source can also cause the timer counter to increment. 208 Table 9.5 Effect of Changing Internal Clock Sources No. Description 1 Low low Timing *1 Old clock source New clock source TCNT clock pulse TCNT N+1 N CKS rewrite 2 Low high *2 Old clock source New clock source TCNT clock pulse TCNT N N+1 N+2 CKS rewrite 209 No. Description 3 High low Timing *3 Old clock source New clock source *4 TCNT clock pulse TCNT N N+1 N+2 CKS rewrite 4 High high Old clock source New clock source TCNT clock pulse TCNT N N+1 N+2 CKS rewrite Notes: *1 Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition from the stopped state to low. *2 Including a transition from the stopped state to high. *3 Including a transition from high to the stopped state. *4 The switching of clock sources is regarded as a falling edge, and therefore a TCNT clock pulse is generated and TCNT is incremented. 210 Section 10 PWM Timers 10.1 Overview The H8/3437 Series has an on-chip pulse-width modulation (PWM) timer module with two independent channels (PWM0 and PWM1). Both channels are functionally identical. Each PWM channel generates a rectangular output pulse with a duty cycle of 0 to 100%. The duty cycle is specified in an 8-bit duty register (DTR). 10.1.1 Features The PWM timer module has the following features: * Selection of eight clock sources * Duty cycles from 0 to 100% with 1/250 resolution * Output with positive or negative logic and software enable/disable control 211 10.1.2 Block Diagram Figure 10.1 shows a block diagram of one PWM timer channel. Compare-match Comparator TCNT Bus interface Output control Pulse Module data bus DTR Internal data bus TCR Clock Clock select Timer control register (8 bits) TCR: Duty register (8 bits) DTR: TCNT: Timer counter (8 bits) oP/2 oP/8 oP/32 oP/128 oP/256 oP/1024 oP/2048 oP/4096 Internal clock sources Figure 10.1 Block Diagram of PWM Timer 10.1.3 Input and Output Pins Table 10.1 lists the output pins of the PWM timer module. There are no input pins. Table 10.1 Output Pins of PWM Timer Module Name Abbreviation I/O Function PWM0 output PW0 Output Pulse output from PWM timer channel 0. PWM1 output PW1 Output Pulse output from PWM timer channel 1. 212 10.1.4 Register Configuration The PWM timer module has three registers for each channel as listed in table 10.2. Table 10.2 PWM Timer Registers Address Name Abbreviation R/W Initial Value Timer control register TCR R/W H'38 H'FFA0 H'FFA4 Duty register DTR R/W H'FF H'FFA1 H'FFA5 Timer counter TCNT R/W H'00 H'FFA2 H'FFA6 10.2 Register Descriptions 10.2.1 Timer Counter (TCNT) PWM0 PWM1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCNT is an 8-bit readable/writable up-counter. When the output enable bit (OE) is set to 1 in TCR, TCNT starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0). After counting from H'00 to H'F9, the count repeats from H'00. When TCNT changes from H'00 to to H'01, the PWM output is placed in the 1 state, unless the DTR value is H'00, in which case the duty cycle is 0% and the PWM output remains in the 0 state. TCNT is initialized to H'00 at a reset and in the standby modes, and when the OE bit is cleared to 0. 213 10.2.2 Duty Register (DTR) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W DTR is an 8-bit readable/writable register that specifies the duty cycle of the output pulse. Any duty cycle from 0% to 100% can be output by setting the corresponding value in DTR. The resolution is 1/250. Writing 0 (H'00) in DTR gives a 0% duty cycle. Writing 125 (H'7D) gives a 50% duty cycle. Writing 250 (H'FA) gives a 100% duty cycle. The DTR and TCNT values are always compared. When the values match, the PWM output is placed in the 0 state. DTR is double-buffered. A new value written in DTR does not become valid until after the timer count changes from H'F9 to H'00. While the OE bit is cleared to 0 in TCR, however, new values written in DTR become valid immediately. When DTR is read, the value read is the currently valid value. DTR is initialized to H'FF by a reset and in the standby modes. 214 10.2.3 Timer Control Register (TCR) Bit 7 6 5 4 3 2 1 0 OE OS -- -- -- CKS2 CKS1 CKS0 Initial value 0 0 1 1 1 0 0 0 Read/Write R/W R/W -- -- -- R/W R/W R/W TCR is an 8-bit readable/writable register that selects the clock input to TCNT and controls PWM output. TCR is initialized to H'38 by a reset and in standby mode. Bit 7--Output Enable (OE): This bit enables the timer counter and the PWM output. Bit 7: OE Description 0 PWM output is disabled. TCNT is cleared to H'00 and stopped. 1 PWM output is enabled. TCNT runs. (Initial value) Bit 6--Output Select (OS): This bit selects positive or negative logic for the PWM output. Bit 6: OS Description 0 Positive logic; positive-going PWM pulse, 1 = high 1 Negative logic; negative-going PWM pulse, 1 = low (Initial value) Bits 5 to 3--Reserved: These bits cannot be modified and are always read as 1. 215 Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight internal clock sources obtained by dividing the supporting-module clock (oP ). Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Description 0 0 0 oP/2 1 oP/8 0 oP/32 1 oP/128 0 oP/256 1 oP/1024 0 oP/2048 1 oP/4096 1 1 0 1 (Initial value) From the clock source frequency, the resolution, period, and frequency of the PWM output can be calculated as follows. Resolution = 1/clock source frequency PWM period = resolution x 250 PWM frequency = 1/PWM period If the oP clock frequency is 10 MHz, then the resolution, period, and frequency of the PWM output for each clock source are as shown in table 10.3. Table 10.3 PWM Timer Parameters for 10 MHz System Clock Internal Clock Frequency Resolution PWM Period PWM Frequency oP/2 200 ns 50 s 20 kHz oP/8 800 ns 200 s 5 kHz oP/32 3.2 s 800 s 1.25 kHz oP/128 12.8 s 3.2 ms 312.5 Hz oP/256 25.6 s 6.4 ms 156.3 Hz oP/1024 102.4 s 25.6 ms 39.1 Hz oP/2048 204.8 s 51.2 ms 19.5 Hz oP/4096 409.6 s 102.4 ms 9.8 Hz 216 10.3 Operation 10.3.1 Timer Increment The PWM clock source is created by dividing the system clock (o). The timer counter increments on a TCNT clock pulse generated from the falling edge of the prescaler output as shown in figure 10.2. o Prescaler output TCNT clock pulse TCNT N-1 N N+1 Figure 10.2 TCNT Increment Timing 217 218 Figure 10.3 PWM Timing (e)* (a)* N written in DTR H'FF (a) H'00 (b) (b) H'01 N (c) N (c) PWM 1 cycle M written in DTR H'02 N-1 H'F9 N+1 Note: * Used for port 4 input/output: state depends on values in data register and data direction register. (OS = 1) PWM output (OS = 0) DTR TCNT OE TCNT clock pulses o (d) M (d) H'00 H'01 10.3.2 PWM Operation Figure 10.3 is a timing chart of the PWM operation. Positive Logic (OS = 0): 1. When (OE = 0)--(a) in Figure 10.3 The timer count is held at H'00 and PWM output is inhibited. [Pin 46 (for PW0) or pin 47 (for PW1) is used for port 4 input/output, and its state depends on the corresponding port 4 data register and data direction register.] Any value (such as N in figure 10.3) written in the DTR becomes valid immediately. 2. When (OE = 1) a. The timer counter begins incrementing. The PWM output goes high when TCNT changes from H'00 to H'01, unless DTR = H'00. [(b) in figure 10.3] b. When the count passes the DTR value, the PWM output goes low. [(c) in figure 10.3] c. If the DTR value is changed (by writing the data "M" in figure 10.3), the new value becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 10.3] Negative Logic (OS = 1)--(e) in Figure 10.3: The operation is the same except that high and low are reversed in the PWM output. [(e) in figure 10.3] 10.4 Application Notes Some notes on the use of the PWM timer module are given below. 1. Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS) should be made before the output enable bit (OE) is set to 1. 2. If the DTR value is H'00, the duty cycle is 0% and PWM output remains constant at 0. If the DTR value is H'FA to H'FF, the duty cycle is 100% and PWM output remains constant at 1. (For positive logic, 0 is low and 1 is high. For negative logic, 0 is high and 1 is low.) 219 220 Section 11 Watchdog Timer 11.1 Overview The H8/3437 Series has an on-chip watchdog timer (WDT) that can monitor system operation by resetting the CPU or generating a nonmaskable interrupt if a system crash allows the timer count to overflow. When this watchdog function is not needed, the watchdog timer module can be used as an interval timer. In interval timer mode, it requests an WOVF interrupt at each counter overflow. 11.1.1 Features WDT features are shown below. * Selection of eight counter input clocks * Switchable between watchdog timer mode and interval timer mode * Timer counter overflow generates an internal reset or internal interrupt: Selection of internal reset or internal interrupt generation in watchdog timer mode WOVF interrupt request in interval timer mode * RESO output in watchdog timer mode Low-level signal output from RESO pin when counter overflows in watchdog timer mode (when internal reset is selected) 221 11.1.2 Block Diagram Figure 11.1 is a block diagram of the watchdog timer. Internal reset or NMI (watchdog timer mode) WOVF interrupt request signal (interval timer mode) System interrupt control Overflow Internal data bus TCNT Read/write control TCSR RESO pin Internal clock source Clock Clock select TCNT: Timer counter TCSR: Timer control/status register oP/2 oP/32 oP/64 oP/128 oP/256 oP/512 oP/2048 oP/4096 Figure 11.1 Block Diagram of Watchdog Timer 11.1.3 Output Pin Table 11.1 Output Pin of Watchdog Timer Name Abbreviation I/O Function Reset out output pin RESO Output Counter overflow signal output in watchdog timer mode 222 11.1.4 Register Configuration Table 11.2 lists information on the watchdog timer registers. Table 11.2 Register Configuration Addresses Name Abbreviation R/W Initial Value Timer control/status register TCSR R/(W)* H'10 H'FFA8 H'FFA8 Timer counter TCNT R/W H'00 H'FFA8 H'FFA9 Write Read Note: * Software can write a 0 to clear the status flag bits, but cannot write 1. 11.2 Register Descriptions 11.2.1 Timer Counter (TCNT) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count overflows (changes from H'FF to H'00), an overflow flag (OVF) in TCSR is set to 1. TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. Note: TCNT is more difficult to write to than other registers. See Section 11.2.4, Register Access, for details. 223 11.2.2 Timer Control/Status Register (TCSR) Bit 7 6 5 4 3 2 1 0 OVF WT/IT TME -- RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)* R/W R/W -- R/W R/W R/W R/W Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and performs other functions. (TCSR is write-protected by a password. See section 11.2.3, Register Access, for details.) Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are initialized to 0 by a reset, but retain their values in the standby modes. Bit 7--Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed. Bit 7: OVF Description 0 To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit (Initial value) 1 Set to 1 when TCNT changes from H'FF to H'00 Bit 6--Timer Mode Select (WT/IT): Selects whether to operate in watchdog timer mode or interval timer mode. When TCNT overflows, an WOVF interrupt request is sent to the CPU in interval timer mode. For watchdog timer mode, a reset or NMI interrupt is requested. Bit 6: WT/IT Description 0 Interval timer mode (WOVF request) 1 Watchdog timer mode (reset or NMI request) (Initial value) Bit 5--Timer Enable (TME): Enables or disables the timer. Bit 5: TME Description 0 TCNT is initialized to H'00 and stopped 1 TCNT runs and requests a reset or an interrupt when it overflows 224 (Initial value) Bit 4--Reserved: This bit cannot be modified and is always read as 1. Bit 3: Reset or NMI Select (RST/NMI): Selects either an internal reset or the NMI function at watchdog timer overflow. Bit 3: RST/NMI Description 0 NMI function enabled 1 Reset function enabled (Initial value) Bits 2-0--Clock Select (CKS2-CKS0): These bits select one of eight clock sources obtained by dividing the system clock (o). The overflow interval is the time from when the watchdog timer counter begins counting from H'00 until an overflow occurs. In interval timer mode, OVF interrupts are requested at this interval. Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source Overflow Interval (oP = 10 MHz) 0 0 0 oP/2 51.2 s 1 oP/32 819.2 s 0 oP/64 1.6 ms 1 oP/128 3.3 ms 0 oP/256 6.6 ms 1 oP/512 13.1 ms 0 oP/2048 52.4 ms 1 oP/4096 104.9 ms 1 1 0 1 (Initial value) 225 11.2.3 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R R/W R/W R/W Only bit 3 is described here. For details of other bits, see section 3.2., System Control Register (SYSCR), and descriptions of the relevant modules. Bit 3--External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by an internal reset due to watchdog timer overflow when the RST/NMI bit is 1. Bit 3: XRST Description 0 A reset is generated by an internal reset due to watchdog timer overflow 1 A reset is generated by external reset input 11.2.4 (Initial value) Register Access The watchdog timer's TCNT and TCSR registers are more difficult to write to than other registers. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: Word access is required. Byte data transfer instructions cannot be used for write access. The TCNT and TCSR registers have the same write address. The write data must be contained in the lower byte of a word written at this address. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). See figure 11.2. The result of the access depicted in figure 11.2 is to transfer the write data from the lower byte to TCNT or TCSR. 15 Writing to TCNT H'FFA8 8 7 H'5A 15 Writing to TCSR H'FFA8 0 Write data 8 7 H'A5 0 Write data Figure 11.2 Writing to TCNT and TCSR 226 Reading TCNT and TCSR: The read addresses are H'FFA8 for TCSR and H'FFA9 for TCNT, as indicated in table 11.3. These two registers are read like other registers. Byte access instructions can be used. Table 11.3 Read Addresses of TCNT and TCSR Read Address Register H'FFA8 TCSR H'FFA9 TCNT 11.3 Operation 11.3.1 Watchdog Timer Mode The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in TCSR. Thereafter, software should periodically rewrite the contents of the timer counter (normally by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count to overflow, the entire chip is reset for 518 system clocks (518 o), or an NMI interrupt is requested. Figure 11.3 shows the operation. NMI requests from the watchdog timer have the same vector as NMI requests from the NMI pin. Avoid simultaneous handling of watchdog timer NMI requests and NMI requests from pin NMI. A reset from the watchdog timer has the same vector as an external reset from the RES pin. The reset source can be determined by the XRST bit in SYSCR. WDT overflow H'FF WT/IT = 1 TME = 1 TCNT count Time t H'00 OVF = 1 WT/IT = 1 TME = 1 H'00 written to TCNT Reset 518 o H'00 written to TCNT Figure 11.3 Operation in Watchdog Timer Mode 227 11.3.2 Interval Timer Mode Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1. In interval timer mode, an WOVF request is generated each time the timer count overflows. This function can be used to generate WOVF requests at regular intervals. See figure 11.4. H'FF TCNT count Time t H'00 WT/IT = 0 TME = 1 OVF request OVF request OVF request OVF request OVF request Figure 11.4 Operation in Interval Timer Mode 11.3.3 Setting the Overflow Flag The WOVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module requests an internal reset, NMI, or OVF interrupt. The timing is shown in figure 11.5. o TCNT H'FF H'00 Internal overflow signal OVF Figure 11.5 Setting the OVF Bit 228 11.3.4 RESO Signal Output Timing When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/NMI bit is 1 at this time, an internal reset signal is generated for the entire chip. At the same time a lowlevel signal is output from the RESO pin. The timing is shown in figure 11.6. o TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal Internal reset signal 132 states 518 states Figure 11.6 RESO Signal Output Timing 229 11.4 Application Notes 11.4.1 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. See figure 11.7. Write cycle (CPU writes to TCNT) T1 T2 T3 o Internal address bus TCNT address Internal write signal TCNT clock pulse TCNT N M Counter write data Figure 11.7 TCNT Write-Increment Contention 11.4.2 Changing the Clock Select Bits (CKS2 to CKS0) Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the clock select bits. If the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly. 11.4.3 Recovery from Software Standby Mode TCSR bits, except bits 0-2, and the TCNT counter are reset when the chip recovers from software standby mode. Re-initialize the watchdog timer as necessary to resume normal operation. 230 11.4.4 Switching between Watchdog Timer Mode and Interval Timer Mode If a switch is made between watchdog timer mode and interval timer mode while the WDT is operating, correct operation may not be performed. The WDT must be stopped (by clearing the TME bit to 0) before changing the timer mode. 11.4.5 System Reset by RESO Signal If the RESO output signal is input to the chip's RES pin, the chip will not be initialized correctly. Ensure that the RESO signal is not logically input to the chip's RES pin. When resetting the entire system with the RESO signal, use a circuit such as that shown in figure 11.8. H8/3437 Series chip Reset input Reset signal to entire chip RES RESO Figure 11.8 Sample Circuit for System Reset by RESO Signal 11.4.6 Detection of Program Runaway The following points should be noted when using the microcomputer's on-chip watchdog timer to detect program runaway. During program runaway, instructions other than the usual instructions may be executed. If an instruction reserved for system use is executed as a result of runaway, the watchdog timer may sometimes stop, preventing detection of the runaway. This problem can be avoided by making the following settings in the program. 1. Set code H'0004 in ROM address H'0002. 2. Set code H'56F0 in ROM address H'0004. As system reserved addresses may be used by an emulator, the above settings should only be made for the actual chip. 231 232 Section 12 Serial Communication Interface 12.1 Overview The H8/3437 Series includes two serial communication interface channels (SCI0 and SCI1) for transferring serial data to and from other chips. Either synchronous or asynchronous communication can be selected. 12.1.1 Features The features of the on-chip serial communication interface are: * Asynchronous mode The H8/3437 Series can communicate with a UART (Universal Asynchronous Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip that employs standard asynchronous serial communication. It also has a multiprocessor communication function for communication with other processors. Twelve data formats are available. Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Error detection: Parity, overrun, and framing errors * * * * Break detection: When a framing error occurs, the break condition can be detected by reading the level of the RxD line directly. Synchronous mode The SCI can communicate with chips able to perform clocked synchronous data transfer. Data length: 8 bits Error detection: Overrun errors Full duplex communication The transmitting and receiving sections are independent, so each channel can transmit and receive simultaneously. Both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. Built-in baud rate generator Any specified bit rate can be generated. Internal or external clock source The SCI can operate on an internal clock signal from the baud rate generator, or an external clock signal input at the SCK0 or SCK1 pin. 233 * Four interrupts TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested independently. 12.1.2 Block Diagram Bus interface Figure 12.1 shows a block diagram of one serial communication interface channel. Module data bus RDR TDR SSR BRR SCR SMR RxD TxD RSR TSR Communication control Parity generate Internal data bus Internal clock o oP/4 oP/16 oP/64 Baud rate generator Clock Parity check External clock source SCK RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR: Receive shift register (8 bits) Receive data register (8 bits) Transmit shift register (8 bits) Transmit data register (8 bits) Serial mode register (8 bits) Serial control register (8 bits) Serial status register (8 bits) Bit rate register (8 bits) TEI TXI RXI ERI Interrupt signals Figure 12.1 Block Diagram of Serial Communication Interface 234 12.1.3 Input and Output Pins Table 12.1 lists the input and output pins used by the SCI module. Table 12.1 SCI Input/Output Pins Channel Name Abbreviation I/O Function 0 Serial clock input/output SCK0 Input/output SCI0 clock input and output Receive data input RxD0 Input SCI0 receive data input Transmit data output TxD0 Output SCI0 transmit data output Serial clock input/output SCK1 Input/output SCI1 clock input and output Receive data input RxD1 Input SCI1 receive data input Transmit data output TxD1 Output SCI1 transmit data output 1 Note: In this manual, the channel subscript has been deleted, and only SCK, RxD, and TxD are used. 235 12.1.4 Register Configuration Table 12.2 lists the SCI registers. These registers specify the operating mode (synchronous or asynchronous), data format and bit rate, and control the transmit and receive sections. Table 12.2 SCI Registers Channel 0 Name -- -- --* 1 Receive data register RDR R H'00 H'FFDD Transmit shift register TSR Transmit data register TDR *1 *1 Address RSR *1 *3 -- -- --* 1 R/W H'FF H'FFDB H'00 H'FFD8 H'00 H'FFDA H'84 H'FFDC H'FF H'FFD9 Serial mode register SMR R/W Serial control register SCR R/W Bit rate register 0 and 1 Initial Value R/W Receive shift register Serial status register 1 Abbreviation SSR R/(W) *3 BRR *1 *2 R/W *1 *1 Receive shift register RSR -- -- --* 1 Receive data register RDR R H'00 H'FF8D *1 *1 Transmit shift register TSR -- -- --* 1 Transmit data register TDR R/W H'FF H'FF8B Serial mode register SMR R/W H'00 H'FF88 Serial control register SCR R/W H'00 H'FF8A H'84 H'FF8C *2 Serial status register SSR R/(W) Bit rate register BRR R/W H'FF H'FF89 Serial/timer control register STCR R/W H'00 H'FFC3 Notes: *1 Cannot be read or written to. *2 Software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits. *3 SMR and BRR have the same addresses as I 2C bus interface registers ICCR and ICSR. For the access switching method and other details, see section 13, I2C Bus Interface. 236 12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- RSR is a shift register that converts incoming serial data to parallel data. When one data character has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write RSR directly. 12.2.2 Receive Data Register (RDR) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R RDR stores received data. As each character is received, it is transferred from RSR to RDR, enabling RSR to receive the next character. This double-buffering allows the SCI to receive data continuously. RDR is a read-only register. RDR is initialized to H'00 by a reset and in the standby modes. 12.2.3 Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- TSR is a shift register that converts parallel data to serial transmit data. When transmission of one character is completed, the next character is moved from the transmit data register (TDR) to TSR and transmission of that character begins. If the TDRE bit is still set to 1, however, nothing is transferred to TSR. The CPU cannot read or write TSR directly. 237 12.2.4 Transmit Data Register (TDR) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TDR is an 8-bit readable/writable register that holds the next data to be transmitted. When TSR becomes empty, the data written in TDR is transferred to TSR. Continuous data transmission is possible by writing the next data in TDR while the current data is being transmitted from TSR. TDR is initialized to H'FF by a reset and in the standby modes. 12.2.5 Serial Mode Register (SMR) Bit 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit readable/writable register that controls the communication format and selects the clock source of the on-chip baud rate generator. It is initialized to H'00 by a reset and in the standby modes. For further information on the SMR settings and communication formats, see tables 12.7 and 12.9 in section 12.3, Operation. Bit 7--Communication Mode (C/A): This bit selects asynchronous or synchronous communication mode. Bit 7: C/A Description 0 Asynchronous communication 1 Synchronous communication (Initial value) Bit 6--Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode. Bit 6: CHR Description 0 8 bits per character 1 7 bits per character (Bits 0 to 6 of TDR and RDR are used for transmitting and receiving, respectively.) 238 (Initial value) Bit 5--Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It is ignored in synchronous mode, and when a multiprocessor format is used. Bit 5: PE Description 0 Transmit: No parity bit is added. (Initial value) Receive: Parity is not checked. 1 Transmit: A parity bit is added. Receive: Parity is checked. Bit 4--Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character to make the total number of 1's even. Odd parity means that the total number of 1's is made odd. This bit is ignored when PE = 0, or when a multiprocessor format is used. It is also ignored in synchronous mode. Bit 4: O/E Description 0 Even parity 1 Odd parity (Initial value) Bit 3--Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in synchronous mode. Bit 3: STOP Description 0 One stop bit (Initial value) Transmit: One stop bit is added. Receive: One stop bit is checked to detect framing errors. 1 Two stop bits Transmit: Two stop bits are added. Receive: The first stop bit is checked to detect framing errors. If the second stop bit is a space (0), it is regarded as the next start bit. 239 Bit 2--Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous communication. When multiprocessor format is selected, the parity settings of the parity enable bit (PE) and parity mode bit (O/E) are ignored. The MP bit is ignored in synchronous communication. The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to 1. When the MPE bit is cleared to 0, the multiprocessor communication function is disabled regardless of the setting of the MP bit. Bit 2: MP Description 0 Multiprocessor communication function is disabled. 1 Multiprocessor communication function is enabled. (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the clock source of the on-chip baud rate generator. Bit 1: CKS1 Bit 0: CKS0 Description 0 0 o clock 1 oP/4 clock 0 oP/16 clock 1 oP/64 clock 1 12.2.6 (Initial value) Serial Control Register (SCR) Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'00 by a reset and in the standby modes. Bit 7--Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to 1. Bit 7: TIE Description 0 The TDR-empty interrupt request (TXI) is disabled. 1 The TDR-empty interrupt request (TXI) is enabled. 240 (Initial value) Bit 6--Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt (RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER), framing error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1. Bit 6: RIE Description 0 The receive-end interrupt (RXI) and receive-error (ERI) requests are disabled. (Initial value) 1 The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled. Bit 5--Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TxD pin is automatically used for output. When the transmit function is disabled, the TxD pin can be used as a general-purpose I/O port. Bit 5: TE Description 0 The transmit function is disabled. (Initial value) The TxD pin can be used for general-purpose I/O. 1 The transmit function is enabled. The TxD pin is used for output. Bit 4--Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RxD pin is automatically used for input. When the receive function is disabled, the RxD pin is available as a general-purpose I/O port. Bit 4: RE Description 0 The receive function is disabled. The RxD pin can be used for general-purpose I/O. (Initial value) 1 The receive function is enabled. The RxD pin is used for input. Bit 3--Multiprocessor Interrupt Enable (MPIE): When serial data is received in a multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receiveerror interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or disables the transfer of received data from RSR to RDR, and enables or disables setting of the RDRF, FER, PER, and ORER bits in the serial status register (SSR). The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode. Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this condition data is received regardless of the value of the multiprocessor bit in the receive data. 241 Setting the MPIE bit to 1 enables the multiprocessor receive interrupt function. In this condition, if the multiprocessor bit in the receive data is 0, the receive-end interrupt (RXI) and receive-error interrupt (ERI) are disabled, the receive data is not transferred from RSR to RDR, and the RDRF, FER, PER, and ORER bits in the serial status register (SSR) are not set. If the multiprocessor bit is 1, however, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0, the receive data is transferred from RSR to RDR, the FER, PER, and ORER bits can be set, and the receive-end and receive-error interrupts are enabled. Bit 3: MPIE Description 0 The multiprocessor receive interrupt function is disabled. (Normal receive operation) 1 The multiprocessor receive interrupt function is enabled. During the interval before data with the multiprocessor bit set to 1 is received, the receive interrupt request (RXI) and receive-error interrupt request (ERI) are disabled, the RDRF, FER, PER, and ORER bits are not set in the serial status register (SSR), and no data is transferred from the RSR to the RDR. The MPIE bit is cleared at the following times: (Initial value) 1. When 0 is written in MPIE. 2. When data with the multiprocessor bit set to 1 is received. Bit 2--Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set to 1. Bit 2: TEIE Description 0 The TSR-empty interrupt request (TEI) is disabled. 1 The TSR-empty interrupt request (TEI) is enabled. (Initial value) Bit 1--Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud rate generator. When the external clock source is selected, the SCK pin is automatically used for input of the external clock signal. Bit 1: CKE1 Description 0 Internal clock source When C/A = 1, the serial clock signal is output at the SCK pin. When C/A = 0, output depends on the CKE0 bit. 1 242 External clock source. The SCK pin is used for input. (Initial value) Bit 0--Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode, this bit enables or disables serial clock output at the SCK pin. This bit is ignored when the external clock is selected, or when synchronous mode is selected. For further information on the communication format and clock source selection, see table 12.8 in section 12.3, Operation. Bit 0: CKE0 Description 0 The SCK pin is not used by the SCI (and is available as a general-purpose I/O port). (Initial value) 1 The SCK pin is used for serial clock output. 12.2.7 Serial Status Register (SSR) Bit 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits. SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 by a reset and in the standby modes. Bit 7--Transmit Data Register Empty (TDRE): This bit indicates when transmit data can safely be written in TDR. Bit 7: TDRE Description 0 To clear TDRE, the CPU must read TDRE after it has been set to 1, then write a 0 in this bit. 1 This bit is set to 1 at the following times: (Initial value) 1. When TDR contents are transferred to TSR. 2. When the TE bit in SCR is cleared to 0. 243 Bit 6--Receive Data Register Full (RDRF): This bit indicates when one character has been received and transferred to RDR. Bit 6: RDRF Description 0 To clear RDRF, the CPU must read RDRF after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when one character is received without error and transferred from RSR to RDR. Bit 5--Overrun Error (ORER): This bit indicates an overrun error during reception. Bit 5: ORER Description 0 To clear ORER, the CPU must read ORER after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = 1). Bit 4--Framing Error (FER): This bit indicates a framing error during data reception in asynchronous mode. It has no meaning in synchronous mode. Bit 4: FER Description 0 To clear FER, the CPU must read FER after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 if a framing error occurs (stop bit = 0). Bit 3--Parity Error (PER): This bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. This bit has no meaning in the synchronous mode, or when a communication format without parity bits is used. Bit 3: PER Description 0 To clear PER, the CPU must read PER after it has been set to 1, then write a 0 in this bit. (Initial value) 1 This bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the O/E bit in SMR). 244 Bit 2--Transmit End (TEND): This bit indicates that the serial communication interface has stopped transmitting because there was no valid data in TDR when the last bit of the current character was transmitted. The TEND bit is also set to 1 when the TE bit in the serial control register (SCR) is cleared to 0. The TEND bit is a read-only bit and cannot be modified directly. To use the TEI interrupt, first start transmitting data, which clears TEND to 0, then set TEIE to 1. Bit 2: TEND Description 0 To clear TEND, the CPU must read TDRE after TDRE has been set to 1, then write a 0 in TDRE 1 This bit is set to 1 when: (Initial value) 1. TE = 0 2. TDRE = 1 at the end of transmission of a character Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode. This bit retains its previous value in synchronous mode, when a multiprocessor format is not used, or when the RE bit is cleared to 0 even if a multiprocessor format is used. MPB can be read but not written. Bit 1: MPB Description 0 Multiprocessor bit = 0 in receive data. 1 Multiprocessor bit = 1 in receive data. (Initial value) Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted in transmit data when a multiprocessor format is used in asynchronous communication mode. The MPBT bit is double-buffered in the same way as TSR and TDR. The MPBT bit has no effect in synchronous mode, or when a multiprocessor format is not used. Bit 0: MPBT Description 0 Multiprocessor bit = 0 in transmit data. (Initial value) Multiprocessor bit = 1 in transmit data. 245 12.2.8 Bit Rate Register (BRR) Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR, determines the bit rate output by the baud rate generator. BRR is initialized to H'FF by a reset and in the standby modes. Tables 12.3 to 12.6 show examples of BRR settings. 246 Table 12.3 Examples of BRR Settings in Asynchronous Mode (When oP = o) o (MHz) 2 2.097152 Bit Rate (bits/s) n N Error (%) n N Error (%) 110 1 141 +0.03 1 148 -0.04 150 1 103 +0.16 1 108 +0.21 300 0 207 +0.16 0 217 +0.21 600 0 103 +0.16 0 108 +0.21 1200 0 51 +0.16 0 54 -0.70 2400 0 25 +0.16 0 26 +1.14 4800 0 12 +0.16 0 13 -2.48 9600 -- -- -- 0 6 -2.48 19200 -- -- -- -- -- -- 31250 0 1 0 -- -- -- 38400 -- -- -- -- -- -- o (MHz) 2.4576 3 3.6864 4 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 174 -0.26 2 52 +0.50 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 -2.34 0 23 0 0 25 +0.16 9600 0 7 0 0 9 -2.34 0 11 0 0 12 +0.16 19200 0 3 0 0 4 -2.34 0 5 0 -- -- -- 31250 -- -- -- 0 2 0 -- -- -- 0 3 0 38400 0 1 0 -- -- -- 0 2 0 -- -- -- Note: If possible, the error should be within 1%. 247 o (MHz) 4.9152 5 6 6.144 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 86 +0.31 2 88 -0.25 2 106 -0.44 2 108 +0.08 150 1 255 0 2 64 +0.16 2 77 0 2 79 0 300 1 127 0 1 129 +0.16 1 155 0 1 159 0 600 0 255 0 1 64 +0.16 1 77 0 1 79 0 1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0 2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0 4800 0 31 0 0 32 -1.36 0 38 +0.16 0 39 0 9600 0 15 0 0 15 +1.73 0 19 -2.34 0 19 0 19200 0 7 0 0 7 +1.73 0 9 -2.34 0 4 0 31250 0 4 -1.70 0 4 0 0 5 0 0 5 +2.40 38400 0 3 0 0 3 +1.73 0 4 -2.34 0 4 0 o (MHz) 7.3728 8 9.8304 10 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 130 -0.07 2 141 +0.03 2 174 -0.26 3 43 +0.88 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16 4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16 9600 0 23 0 0 25 +0.16 0 31 0 0 32 -1.36 19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73 31250 -- -- -- 0 7 0 0 9 -1.70 0 9 0 38400 0 5 0 -- -- -- 0 7 0 0 7 +1.73 Note: If possible, the error should be within 1%. 248 o (MHz) 12 12.288 14.7456 16 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 212 +0.03 2 217 +0.08 3 64 +0.76 3 70 +0.03 150 2 155 +0.16 2 159 0 2 191 0 2 207 +0.16 300 2 77 +0.16 2 79 0 2 95 0 2 103 +0.16 600 1 155 +0.16 1 159 0 1 191 0 1 207 +0.16 1200 1 77 +0.16 1 79 0 1 95 0 1 103 +0.16 2400 0 155 +0.16 0 159 0 0 191 0 0 207 +0.16 4800 0 77 +0.16 0 79 0 0 95 0 0 103 +0.16 9600 0 38 +0.16 0 39 0 0 47 0 0 51 +0.16 19200 0 19 -2.34 0 19 0 0 23 0 0 25 +0.16 31250 0 11 0 0 11 +2.4 0 14 -1.7 0 15 0 38400 0 9 -2.34 0 9 0 0 11 0 0 12 +0.16 Note: If possible, the error should be within 1%. 249 Table 12.4 Examples of BRR Settings in Asynchronous Mode (When oP = o/2) o (MHz) 2 2.097152 Bit Rate (bits/s) n N Error (%) n N Error (%) 110 1 70 0.03 1 73 0.64 150 1 51 0.16 1 54 -0.70 300 0 207 0.16 0 217 0.21 600 0 103 0.16 0 108 0.21 1200 0 51 0.16 0 54 -0.70 2400 0 25 0.16 0 26 1.14 4800 0 12 0.16 0 13 -2.48 9600 -- -- -- 0 6 -2.48 19200 -- -- -- -- -- -- 31250 0 1 0 -- -- -- 38400 -- -- -- -- -- -- o (MHz) 2.4576 3 3.6864 4 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 86 0.31 1 106 -0.44 1 130 -0.07 1 141 0.03 150 1 63 0 1 77 0.16 1 95 0 1 103 0.16 300 0 255 0 1 38 0.16 1 47 0 1 51 0.16 600 0 127 0 0 155 0.16 0 191 0 0 207 0.16 1200 0 63 0 0 77 0.16 0 95 0 0 103 0.16 2400 0 31 0 0 38 0.16 0 47 0 0 51 0.16 4800 0 15 0 0 19 -2.34 0 23 0 0 25 0.16 9600 0 7 0 0 9 -2.34 0 11 0 0 12 0.16 19200 0 3 0 0 4 -2.34 0 5 0 -- -- -- 31250 -- -- -- 0 2 0 -- -- -- 0 3 0 38400 0 1 0 -- -- -- 0 2 0 0 2 8.51 250 o (MHz) 4.9152 5 6 6.144 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 174 -0.26 1 177 -0.25 1 212 0.03 1 217 0.08 150 1 127 0 1 129 0.16 1 155 0.16 1 159 0 300 1 63 0 1 64 0.16 1 77 0.16 1 79 0 600 0 255 0 1 32 1.36 1 38 0.16 1 39 0 1200 0 127 0 0 129 0.16 0 155 0.16 0 159 0 2400 0 63 0 0 64 0.16 0 77 0.16 0 79 0 4800 0 31 0 0 32 -1.36 0 38 0.16 0 39 0 9600 0 15 0 0 15 1.73 0 19 -2.34 0 19 0 19200 0 7 0 0 7 1.73 0 9 -2.34 0 9 0 31250 0 4 -1.70 0 4 0 0 5 0 0 5 2.40 38400 0 3 0 0 3 1.73 0 4 -2.34 0 4 0 o (MHz) 7.3728 8 9.8304 10 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 -0.25 150 1 191 0 1 207 0.16 1 255 0 2 64 0.16 300 1 95 0 1 103 0.16 1 127 0 1 129 0.16 600 1 47 0 1 51 0.16 1 63 0 1 64 0.16 1200 0 191 0 0 207 0.16 0 255 0 1 32 1.36 2400 0 95 0 0 103 0.16 0 127 0 0 129 0.16 4800 0 47 0 0 51 0.16 0 63 0 0 64 0.16 9600 0 23 0 0 25 0.16 0 31 0 0 32 -1.36 19200 0 11 0 0 12 0.16 0 15 0 0 15 1.73 31250 -- -- -- 0 7 0 0 9 -1.70 0 9 0 38400 0 5 0 -- -- -- 0 7 0 0 7 1.73 251 o (MHz) 12 12.288 14.7456 16 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 -0.44 2 108 0.08 2 130 -0.07 2 141 0.03 150 2 77 0.16 2 79 0 2 95 0 2 103 0.16 300 1 155 0.16 1 159 0 1 191 0 1 207 0.16 600 1 77 0.16 1 79 0 1 95 0 1 103 0.16 1200 1 38 0.16 1 39 0 1 47 0 1 51 0.16 2400 0 155 0.16 0 159 0 0 191 0 0 207 0.16 4800 0 77 0.16 0 79 0 0 95 0 0 103 0.16 9600 0 38 0.16 0 39 0 0 47 0 0 51 0.16 19200 0 19 -2.34 0 19 0 0 23 0 0 25 0.16 31250 0 11 0 0 11 2.40 0 14 -1.70 0 15 0 38400 0 9 -2.34 0 9 0 0 11 0 0 12 0.16 Legend: Blank: No setting is available --: A setting is available, but error occurs. 252 Note: If possible, the error should be within 1%. B= B: N: F: n: F 64 x 22n-1 x 106 x (N + 1) N= F 64 x 22n-1 xB x 106 - 1 Bit rate (bits/second) Baud rate generator BRR value (0 N 255) oP (MHz) when n 0, or o (MHz) when n = 0 Baud rate generator input clock (n = 0, 1, 2, 3) The meaning of n is given below. SMR WSCR n CKS1 CKS0 CKDBL Clock 0 0 0 0 o 1 0 1 0 o/4 2 1 0 0 o/16 3 1 1 0 o/64 0 0 0 1 o 1 0 1 1 o/8 2 1 0 1 o/32 3 1 1 1 o/128 The bit rate error can be calculated with the formula below. Error (%) = F x 106 (N + 1) x B x 64 x 22n-1 - 1 x 100 253 Table 12.5 Examples of BRR Settings in Synchronous Mode (When oP = o) o (MHz) 2 4 5 8 10 16 Bit Rate (bits/s) n N n N n N n N n N n N 100 -- -- -- -- -- -- -- -- -- -- -- -- 250 2 124 2 249 -- -- 3 124 -- -- 3 249 500 1 249 2 124 -- -- 2 249 -- -- 3 124 1k 1 124 1 249 -- -- 2 124 -- -- 2 249 2.5 k 0 199 1 99 1 124 1 199 1 249 2 99 5k 0 99 0 199 0 249 1 99 1 124 1 199 10 k 0 49 0 99 0 124 0 199 0 249 1 99 25 k 0 19 0 39 0 49 0 79 0 99 0 159 50 k 0 9 0 19 0 24 0 39 0 49 0 79 100 k 0 4 0 9 -- -- 0 19 0 24 0 39 250 k 0 1 0 3 0 4 0 7 0 9 0 15 500 k 0 0* 0 1 -- -- 0 3 0 4 0 7 0 0* -- -- 0 1 -- -- 0 3 0 0* -- -- 0 0* 1M 2.5 M 4M Legend: Blank: No setting is available --: A setting is available, but error occurs. *: Continuous transfer is not possible 254 Table 12.6 Examples of BRR Settings in Synchronous Mode (When oP = o/2) o (MHz) 2 4 5 8 10 16 Bit Rate (bits/s) n N n N n N n N n N n N 100 -- -- -- -- -- -- -- -- -- -- -- -- 250 1 249 2 124 -- -- 2 249 -- -- 3 124 500 1 124 1 249 -- -- 2 124 -- -- 2 249 1k -- -- 1 124 -- -- 1 249 -- -- 2 124 2.5 k 0 199 1 49 -- -- 1 99 1 124 1 199 5k 0 99 0 199 0 249 1 49 -- -- 1 99 10 k 0 49 0 99 0 124 0 199 0 249 1 49 25 k 0 19 0 39 0 49 0 79 0 99 0 159 50 k 0 9 0 19 0 24 0 39 0 49 0 79 100 k 0 4 0 9 -- -- 0 19 0 24 0 39 250 k 0 1 0 3 0 4 0 7 0 9 0 15 500 k 0 0* 0 1 -- -- 0 3 0 4 0 7 0 0* -- -- 0 1 -- -- 0 3 -- -- 0 0* -- -- -- -- 0 0* 1M 2.5 M 4M Legend: Blank: No setting is available --: A setting is available, but error occurs. *: Continuous transfer is not possible 255 B= B: N: F: n: F 8x 22n-1 x 106 x (N + 1) F 8x 22n-1 xB Bit rate (bits/second) Baud rate generator BRR value (0 N 255) oP (MHz) when n 0, or o (MHz) when n = 0 Baud rate generator input clock (n = 0, 1, 2, 3) The meaning of n is given below. SMR 256 N= WSCR n CKS1 CKS0 CKDBL Clock 0 0 0 0 o 1 0 1 0 o/4 2 1 0 0 o/16 3 1 1 0 o/64 0 0 0 1 o 1 0 1 1 o/8 2 1 0 1 o/32 3 1 1 1 o/128 x 106 - 1 12.2.9 Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICD IICX IICE STAC MPE ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset. Bits 7 to 4--I2C Control (IICS, IICD, IICX, IICE): These bits control operation of the I2C bus interface. For details, refer to section 13, I2C Bus Interface. Bit 3--Slave Input Switch (STAC): Controls the input pin of the host interface. For details, section 14, Host Interface. Bit 2--Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication function on channels SCI0 and SCI1. Bit 2: MPE Description 0 The multiprocessor communication function is disabled, regardless of the setting of the MP bit in SMR. (Initial value) 1 The multiprocessor communication function is enabled. The multi-processor format can be selected by setting the MP bit in SMR to 1. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit Timers. 257 12.3 Operation 12.3.1 Overview The SCI supports serial data transfer in two modes. In asynchronous mode each character is synchronized individually. In synchronous mode communication is synchronized with a clock signal. The selection of asynchronous or synchronous mode and the communication format depend on SMR settings as indicated in table 12.7. The clock source depends on the settings of the C/A bit in the SMR and the CKE1 and CKE0 bits in SCR as indicated in table 12.8. Asynchronous Mode * Data length: 7 or 8 bits can be selected. * A parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be selected. (These selections determine the communication format and character length.) * Framing errors (FER), parity errors (PER), and overrun errors (ORER) can be detected in receive data, and the line-break condition can be detected. * SCI clock source: An internal or external clock source can be selected. * Internal clock: The SCI is clocked by the on-chip baud rate generator and can output a clock signal at the bit-rate frequency. * External clock: The external clock frequency must be 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode * * * * Communication format: The data length is 8 bits. Overrun errors (ORER) can be detected in receive data. SCI clock source: An internal or external clock source can be selected. Internal clock: The SCI is clocked by the on-chip baud rate generator and outputs a serial clock signal to external devices. * External clock: The on-chip baud rate generator is not used. The SCI operates on the input serial clock. 258 Table 12.7 Communication Formats Used by SCI SMR Settings Communication Format Bit 7: C/A Bit 6: CHR Bit 2: MP Bit 5: PE Bit 3: STOP 0 0 0 0 0 1 1 Mode Asynchronous mode MultiData processor Parity Length Bit Bit Stop Bit Length 8 bits 1 bit None None 2 bits 0 Present 1 bit 1 1 0 2 bits 0 7 bits None 1 1 2 bits 0 Present 1 bit 1 0 1 -- 0 1 1 0 2 bits Asynchronous 8 bits mode (multiprocessor format) 7 bits Present None -- -- -- -- 1 bit 2 bits 1 bit 1 1 1 bit 2 bits Synchronous mode 8 bits None None Table 12.8 SCI Clock Source Selection SMR SCR Serial Transmit/Receive Clock Bit 7: C/A Bit 1: CKE1 Bit 0: CKE0 Mode Clock Source SCK Pin Function 0 0 0 Async Internal Input/output port (not used by SCI) 1 1 Serial clock output at bit rate 0 External Serial clock input at 16 x bit rate Internal Serial clock output External Serial clock input 1 1 0 0 Sync 1 1 0 1 259 12.3.2 Asynchronous Mode In asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer. Figure 12.2 shows the general format of one character sent or received in asynchronous mode. The communication channel is normally held in the mark state (high). Character transmission or reception starts with a transition to the space state (low). The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity or multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame. In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). Start bit 1 bit D0 D1 Dn 7 or 8 bits Parity or multiprocessor bit Stop bit 0 or 1 bit 1 or 2 bits One unit of data (one character or frame) Figure 12.2 Data Format in Asynchronous Mode 260 Idle state (mark) Data Format Table 12.9 lists the data formats that can be sent and received in asynchronous mode. Twelve formats can be selected by bits in the serial mode register (SMR). Table 12.9 Data Formats in Asynchronous Mode SMR Bits CHR PE MP STOP 1 0 0 0 0 S 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 -- 1 0 S 8-bit data MPB STOP 0 -- 1 1 S 8-bit data MPB STOP STOP 1 -- 1 0 S 7-bit data MPB STOP 1 -- 1 1 S 7-bit data MPB STOP STOP Notes: SMR: S: STOP: P: MPB: 2 3 4 5 6 7 8 9 10 11 12 Serial mode register Start bit Stop bit Parity bit Multiprocessor bit 261 Clock In asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the SCK pin. The selection is made by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR). Refer to table 12.8. If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate. If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the center of the transmit data bits. Figure 12.3 shows the phase relationship between the output clock and transmit data. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 One frame Figure 12.3 Phase Relationship between Clock Output and Transmit Data (Asynchronous Mode) Transmitting and Receiving Data SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI following the procedure in figure 12.4. Note: When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. 262 Initialization 1. Select interrupts and the clock source in the serial control register (SCR). Leave TE and RE cleared to 0. If clock output is selected, in asynchronous mode, clock output starts immediately after the setting is made in SCR. Clear TE and RE bits to 0 in SCR 2. Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to 0) Select the communication format in the serial mode register (SMR). 3. Write the value corresponding to the bit rate in the bit rate register (BRR). This step is not necessary when an external clock is used. 2 Select communication format in SMR 4. 3 Set value in BRR Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR). Setting TE or RE enables the SCI to use the TxD or RxD pin. Also set the RIE, TIE, TEIE, and MPIE bits as necessary to enable interrupts. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit). 1 1 bit interval elapsed? No Yes 4 Set TE or RE to 1 in SCR, and set RIE, TIE, TEIE, and MPIE as necessary Start transmitting or receiving Figure 12.4 Sample Flowchart for SCI Initialization 263 Transmitting Serial Data: Follow the procedure in figure 12.5 for transmitting serial data. 1 Initialize 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. After the TE bit is set to 1, one frame of 1s is output, then transmission is possible. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. If a multiprocessor format is selected, after writing the transmit data write 0 or 1 in the multiprocessor bit transfer (MPBT) in SSR. Transition of the TDRE bit from 0 to 1 can be reported by an interrupt. Start transmitting 2 Read TDRE bit in SSR No TDRE = 1? Yes Write transmit data in TDR If using multiprocessor format, select MPBT value in SSR Clear TDRE bit to 0 Serial transmission 3 End of transmission? No Yes 3. (a) To continue transmitting serial data: read the TDRE bit to check whether it is safe to write; if TDRE = 1, write data in TDR, then clear TDRE to 0. (b) To end serial transmission: end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1. This can be reported by a TEI interrupt. 4. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear TE to 0 in SCR. Read TEND bit in SSR TEND = 1? No Yes 4 Output break signal? No Yes Set DR = 0, DDR = 1 Clear TE bit in SCR to 0 End Figure 12.5 Sample Flowchart for Transmitting Serial Data 264 In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the TIE bit (TDR-empty interrupt enable) is set to 1 in SCR, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. Serial transmit data are transmitted in the following order from the TxD pin: a. Start bit: One 0 bit is output. b. Transmit data: Seven or eight bits are output, LSB first. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: One or two 1 bits (stop bits) are output. e. Mark state: Output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, after loading new data from TDR into TSR and transmitting the stop bit, the SCI begins serial transmission of the next frame. If TDRE is 1, after setting the TEND bit to 1 in SSR and transmitting the stop bit, the SCI continues 1-level output in the mark state, and if the TEIE bit (TSR-empty interrupt enable) in SCR is set to 1, the SCI generates a TEI interrupt request (TSR-empty interrupt). Figure 12.6 shows an example of SCI transmit operation in asynchronous mode. 265 1 Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 1 1 Idle state (mark) TDRE TEND TXI TXI interrupt handler TXI request writes data in TDR and request clears TDRE to 0 1 frame Figure 12.6 Example of SCI Transmit Operation (8-Bit Data with Parity and One Stop Bit) 266 TEI request Receiving Serial Data: Follow the procedure in figure 12.7 for receiving serial data. 1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving 2 2. To continue receiving serial data: read RDR and clear RDRF to 0 before the stop bit of the current frame is received. Read ORER, PER, and FER in SSR PER RER ORER = 1? Yes No 3 4 Read RDRF bit in SSR RDRF = 1? 3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. Error handling No Yes Read receive data from RDR, and clear RDRF bit to 0 in SSR Finished receiving? 4. Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER bits in SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Transmitting and receiving cannot resume if ORER, PER, or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. No Yes Clear RE to 0 in SCR End Start error handling FER = 1? No Discriminate and process error, and clear flags Yes Break? Yes No Clear RE to 0 in SCR End Return Figure 12.7 Sample Flowchart for Receiving Serial Data 267 In receiving, the SCI operates as follows. 1. The SCI monitors the receive data line and synchronizes internally when it detects a start bit. 2. Receive data is shifted into RSR in order from LSB to MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 12.10. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is set to 1 and the RIE bit in SCR is also set to 1, the SCI requests an ERI (receive-error) interrupt. Table 12.10 Receive Error Conditions and SCI Operation Receive Error Abbreviation Condition Data Transfer Overrun error ORER Receiving of next data ends while RDRF is still set to 1 in SSR Receive data not loaded from RSR into RDR Framing error FER Stop bit is 0 Receive data loaded from RSR into RDR Parity error PER Parity of receive data differs from even/odd parity setting in SMR Receive data loaded from RSR into RDR 268 Figure 12.8 shows an example of SCI receive operation in asynchronous mode. 1 Start bit 0 Parity Stop Start bit bit bit Data D0 D1 D7 0/1 1 0 Parity Stop bit bit Data D0 D1 D7 0/1 0 1 Idle state (mark) RDRF FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0 Framing error, ERI request Figure 12.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. After receiving data with the multiprocessor bit set to 1, the receiving processor with an ID matching the received data continues to receive further incoming data. Multiple processors can send and receive data in this way. Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 12.9. 269 Transmitting processor Serial communication line Receiving processor A Receiving processor B Receiving processor C Receiving processor D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 (MPB = 1) ID-sending cycle: receiving processor address H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID MPB: Multiprocessor bit Figure 12.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) 270 Transmitting Multiprocessor Serial Data: See figures 12.5 and 12.6. Receiving Multiprocessor Serial Data: Follow the procedure in figure 12.10 for receiving multiprocessor serial data. 1 2 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving 2. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. 3. SCI status check and ID check: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and compare with the processor's own ID. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 4. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR) and write 0 in the RDRF bit. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. 5. Receive error handling and break detection: if a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume while ORER or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. Set MPIE bit to 1 in SCR Read ORER and FER bits in SSR FER ORER = 1? Yes No 3 Read RDRF bit in SSR No RDRF = 1? Yes Read receive data from RDR Own ID? No Yes Read ORER and FER bits in SSR FER + ORER = 1? Yes No 4 Read RDRF bit in SSR RDRF = 1? No Start error handling Yes Read receive data from RDR 5 Error handling Finished receiving? No FER = 1? No Clear RE to 0 in SCR Discriminate and process error, and clear flags End Return Yes Yes Break? Yes No Clear RE bit to 0 in SCR End Figure 12.10 Sample Flowchart for Receiving Multiprocessor Serial Data 271 Figure 12.11 shows an example of an SCI receive operation using a multiprocessor format (8-bit data with multiprocessor bit and one stop bit). 1 Start bit 0 Stop Start MPB bit bit Data (ID1) D0 D1 D7 1 1 0 Data (Data1) D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark) MPIE RDRF RDR value ID1 MPB detection MPIE = 0 RXI request RXI handler reads RDR data and clears RDRF to 0 Not own ID, so MPIE is set to 1 again No RXI request, RDR not updated (Multiprocessor interrupt) (a) Own ID does not match data 1 Start bit 0 Stop Start MPB bit bit Data (ID2) D0 D1 D7 1 1 0 Data (Data2) D0 D1 Stop MPB bit D7 0 1 1 Idle state (mark) MPIE RDRF RDR value ID2 MPB detection MPIE = 0 RXI request RXI handler reads Own ID, so receiving RDR data and clears continues, with data RDRF to 0 received at each RXI (Multiprocessor interrupt) (b) Own ID matches data Figure 12.11 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 272 Data 2 MPIE set to 1 again 12.3.3 Synchronous Mode Overview In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 12.12 shows the general format in synchronous serial communication. One unit (character or frame) of serial data * * Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Don't care Don't care Note: * High except in continuous transmitting or receiving Figure 12.12 Data Format in Synchronous Communication In synchronous serial communication, each data bit is sent on the communication line from one falling edge of the serial clock to the next. Data is received in synchronization with the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register (SCR). See table 12.8. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains at the high level. 273 Transmitting and Receiving Data SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See figure 12.4. When switching from asynchronous mode to synchronous mode, check that the ORER, FER, and PER bits are cleared to 0. Transmitting and receiving cannot begin if ORER, FER, or PER is set to 1. Transmitting Serial Data: Follow the procedure in figure 12.13 for transmitting serial data. 1 Initialize Start transmitting 2 Read TDRE bit in SSR No TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Transition of the TDRE bit from 0 to 1 can be reported by a TXI interrupt. 3. (a) To continue transmitting serial data: read the TDRE bit to check whether it is safe to write; if TDRE = 1, write data in TDR, then clear TDRE to 0. (b) To end serial transmission: end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1. This can be reported by a TEI interrupt. Serial transmission 3 End of transmission? No Yes Read TEND bit in SSR TEND = 1? No Yes Clear TE bit to 0 in SCR End Figure 12.13 Sample Flowchart for Serial Transmitting 274 In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). 2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to 1, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of the TDRE bit to 0. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the output in the MSB state. If the TEIE bit (transmit-end interrupt enable) in SCR is set to 1, a TEI interrupt (TSR-empty interrupt) is requested at this time. 4. After the end of serial transmission, the SCK pin is held at the high level. Figure 12.14 shows an example of SCI transmit operation. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI request TXI interrupt TXI handler writes request data in TDR and clears TDRE to 0 TEI request 1 frame Figure 12.14 Example of SCI Transmit Operation 275 Receiving Serial Data: Follow the procedure in figure 12.15 for receiving serial data. When switching from asynchronous mode to synchronous mode, be sure to check that PER and FER are cleared to 0. If PER or FER is set to 1 the RDRF bit will not be set and both transmitting and receiving will be disabled. 1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. Start receiving 2. Receive error handling: if a receive error occurs, read the ORER bit in SSR then, after executing the necessary error handling, clear ORER to 0. Neither transmitting nor receiving can resume while ORER remains set to 1. When clock output mode is selected, receiving can be halted temporarily by receiving one dummy byte and causing an overrun error. When preparations to receive the next data are completed, clear the ORER bit to 0. This causes receiving to resume, so return to the step marked 2 in the flowchart. Read ORER bit in SSR Yes ORER = 1? No 3 2 Error handling Read RDRF in SSR RDRF = 1? 3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. 4. To continue receiving serial data: read RDR and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. No Yes 4 Read receive data from RDR, and clear RDRF bit to 0 in SSR Finished receiving? No Yes Clear RE to 0 in SCR End Start error handling Overrun error handling Clear ORER to 0 in SSR Return Figure 12.15 Sample Flowchart for Serial Receiving 276 In receiving, the SCI operates as follows. 1. If an external clock is selected, data is input in synchronization with the input clock. If clock output is selected, as soon as the RE bit is set to 1 the SCI begins outputting the serial clock and inputting data. If clock output is stopped because the ORER bit is set to 1, output of the serial clock and input of data resume as soon as the ORER bit is cleared to 0. 2. Receive data is shifted into RSR in order from LSB to MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 12.10. Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF bit is not set to 1. Be sure to clear the error flag. 3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and the RIE bit in SCR is set to 1, the SCI requests an ERI (receive-error) interrupt. When clock output mode is selected, clock output stops when the RE bit is cleared to 0 or the ORER bit is set to 1. To prevent clock count errors, it is safest to receive one dummy byte and generate an overrun error. Figure 12.16 shows an example of SCI receive operation. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI request RXI interrupt handler reads data in RDR and clears RDRF to 0 RXI request Overrun error, ERI request 1 frame Figure 12.16 Example of SCI Receive Operation 277 Transmitting and Receiving Serial Data Simultaneously: Follow the procedure in figure 12.17 for transmitting and receiving serial data simultaneously. If clock output mode is selected, output of the serial clock begins simultaneously with serial transmission. 1. SCI initialization: the transmit data output function of the TxD pin and receive data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. 2. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Transition of the TDRE bit from 0 to 1 can be reported by a TXI interrupt. 3. SCI status check and receive data read: read the serial status register (SSR), check that the RDRF bit is 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. 4. Receive error handling: if a receive error occurs, read the ORER bit in SSR then, after executing the necessary error handling, clear ORER to 0. Neither transmitting nor receiving can resume while ORER remains set to 1. Initialize 1 Start 2 Read TDRE bit in SSR No TDRE = 1? Yes 3 Write transmit data in TDR and clear TDRE bit to 0 in SSR Read ORER bit in SSR ORER = 1? Yes No 4 Error handling Read RDRF bit in SSR No 5. RDRF = 1? Yes 5 Read receive data from RDR and clear RDRF bit to 0 in SSR End of transmitting and receiving? To continue transmitting and receiving serial data: read RDR and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit and check that it is set to 1, indicating that it is safe to write; then write data in TDR and clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. No Yes Clear TE and RE bits to 0 in SCR End Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set TE and RE to 1 simultaneously using an MOV instruction. Do not use a BEST instruction for this purpose. Figure 12.17 Sample Flowchart for Serial Transmitting and Receiving 278 12.4 Interrupts The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 12.11 indicates the source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources: overrun error, framing error, and parity error. The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates that the SCI has stopped transmitting data. Table 12.11 SCI Interrupt Sources Interrupt Description Priority ERI Receive-error interrupt (ORER, FER, or PER) High RXI Receive-end interrupt (RDRF) TXI TDR-empty interrupt (TDRE) TEI TSR-empty interrupt (TEND) 12.5 Low Application Notes Application programmers should note the following features of the SCI. TDR Write: The TDRE bit in SSR is simply a flag that indicates that the TDR contents have been transferred to TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new byte is written in TDR while the TDRE bit is 0, before the old TDR contents have been moved into TSR, the old byte will be lost. Software should check that the TDRE bit is set to 1 before writing to TDR. Multiple Receive Errors: Table 12.12 lists the values of flag bits in the SSR when multiple receive errors occur, and indicates whether the RSR contents are transferred to RDR. 279 Table 12.12 SSR Bit States and Data Transfer when Multiple Receive Errors Occur SSR Bits Receive Error RDRF ORER FER PER RSR RDR*2 Overrun error 1*1 1 0 0 No Framing error 0 0 1 0 Yes Parity error 0 Overrun and framing errors 0 0 1 Yes *1 1 1 0 No *1 1 Overrun and parity errors 1 1 0 1 No Framing and parity errors 0 0 1 1 Yes 1 1 1 No Overrun, framing, and parity errors *1 1 Notes: *1 Set to 1 before the overrun error occurs. *2 Yes: The RSR contents are transferred to RDR. No: The RSR contents are not transferred to RDR. Line Break Detection: When the RxD pin receives a continuous stream of 0's in asynchronous mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value H'00 is transferred from RSR to RDR. Software can detect the line-break state as a framing error accompanied by H'00 data in RDR. The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will occur. Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is detected by sampling the RxD input on the falling edge of this clock. After the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 12.18. It follows that the receive margin can be calculated as in equation (1). When the absolute frequency deviation of the clock signal is 0 and the clock duty cycle is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). This is a theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%. 280 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1 2 3 4 5 6 7 8 9 10 11 12 1314 15 16 1 2 3 4 5 Basic clock -7.5 pulses Receive data Start bit +7.5 pulses D0 D1 Sync sampling Data sampling Figure 12.18 Sampling Timing (Asynchronous Mode) M = {(0.5 - 1/2N) - (D - 0.5)/N - (L - 0.5)F} x 100 [%] M: N: D: L: F: ................................... (1) Receive margin Ratio of basic clock to bit rate (N=16) Duty factor of clock--ratio of high pulse width to low width (0.5 to 1.0) Frame length (9 to 12) Absolute clock frequency deviation When D = 0.5 and F = 0 M = (0.5 -1/2 x 16) x 100 [%] = 46.875% ......................................................... (2) 281 282 Section 13 I2 C Bus Interface [Option] An I2C bus interface is available as an option. Observe the following notes when using this option. For mask-ROM versions, products that use this option have a "W" added to the product number. Examples: HD6433437WTF, HD6433434WF 13.1 Overview The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. The I2C bus interface uses only one data line (SDA) and one clock line (SCL) to transfer data, so it can save board and connector space. Figure 13.1 shows typical I2C bus interface connections. 13.1.1 * * * * * * * * * * * Features Conforms to Philips I2C bus interface Start and stop conditions generated automatically Selectable acknowledge output level when receiving Auto-loading of acknowledge bit when transmitting Selection of eight internal clocks (in master mode) Selection of acknowledgement mode, or serial mode without acknowledge bit Wait function: A wait can be inserted in acknowledgement mode by holding the SCL pin low after a data transfer, before acknowledgement of the transfer. Three interrupt sources Data transfer end In slave receive mode: slave address matched, or general call address received In master transmit mode: bus arbitration lost Direct bus drive (pins SCL and SDA) In addition to pins SCL and SCA, four general port pins (PA4 to PA 7) can also drive the bus Pins P86/SCK1/SCL, P97/WAIT/SDA, and PA4/KEYIN12 to PA 7/KEYIN15 (total of 6 pins) are all powered by bus power supply VCCB, separate from VCC. When the bus drive function is selected, all output is NMOS output. 283 VCCB VCC VCC VCCB SCL SCL SDA SDA SCL in SDA out (Master) SCL in H8/3437 SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) SCL in SCL SDA SDA in SCL SDA SCL out (Slave 2) Figure 13.1 I2C Bus Interface Connection Example (When the H8/3437 is the Master Chip) 284 13.1.2 Block Diagram Figure 13.2 shows a block diagram of the I2C bus interface. STCR oP PS ICCR SCL Clock control Noise canceler Bus state decision circuit ICSR Arbitration decision circuit Output data control circuit SDA Noise canceler Internal data bus ICMR ICDR Address comparator Legend: ICCR: I2C bus control register ICMR: I2C bus mode register ICSR: I2C bus status register ICDR: I2C bus data register SAR: Slave address register PS: Prescaler STCR: Serial timer control register SAR Interrupt generator Interrupt request Figure 13.2 Block Diagram of I2C Bus Interface 285 13.1.3 Input/Output Pins Table 13.1 summarizes the input/output pins used by the I2C bus interface. Table 13.1 Wait-State Controller Pins Name Abbreviation I/O Function Serial clock SCL Input/output Serial clock input/output Serial data SDA Input/output Serial data input/output 13.1.4 Register Configuration Table 13.2 summarizes the registers of the I2C bus interface. Table 13.2 Register Configuration Name Abbreviation R/W Initial Value Address*2 I 2C bus control register ICCR R/W H'00 H'FFD8 2 ICSR R/W H'30 H'FFD9 2 ICDR R/W -- H'FFDE 2 I C bus mode register ICMR R/W H'38 H'FFDF*1 Slave address register SAR R/W H'00 H'FFDF*1 Serial timer control register STCR R/W H'00 H'FFC3 I C bus status register I C bus data register Notes: *1 The register that can be written or read depends on the ICE bit in the I 2C bus control register. The slave address register can be accessed when ICE = 0. The I2C bus mode register can be accessed when ICE = 1. *2 The addresses assigned to the I2C bus interface registers are also assigned to other registers. The accessible registers are selected with bit IICE in the serial/timer control register (STCR). 286 13.2 Register Descriptions 13.2.1 I2C Bus Data Register (ICDR) Bit 7 6 5 4 3 2 1 0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value -- -- -- -- -- -- -- -- Read/Write R/W R/W R/W R/W R/W R/W R/W R/W ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. Transmitting is started by writing data in ICDR. Receiving is started by reading data from ICDR. ICDR is also used as a shift register, so it must not be written or read until data has been completely transmitted or received. Read or write access while data is being transmitted or received may result in incorrect data. The ICDR value following a reset and in hardware standby mode is undetermined. 13.2.2 Slave Address Register (SAR) Bit 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SAR is an 8-bit readable/writable register that stores the slave address and selects the communication format. When the chip is in slave mode (and the addressing format is selected), if the upper 7 bits of SAR match the upper 7 bits of the first byte received after a start condition, the chip operates as the slave device specified by the master device. SAR is assigned to the same address as ICMR. SAR can be written and read only when the ICE bit is cleared to 0 in ICCR. SAR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 1--Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0, differing from the addresses of other slave devices connected to the I2C bus. 287 Bit 0--Format Select (FS): Selects whether to use the addressing format or non-addressing format in slave mode. The addressing format is used to recognize slave addresses. Bit 0: FS Description 0 Addressing format, slave addresses recognized 1 Non-addressing format 13.2.3 (Initial value) I2C Bus Mode Register (ICMR) Bit 7 6 5 4 3 2 1 0 MLS WAIT -- -- -- BC2 BC1 BC0 Initial value 0 0 1 1 1 0 0 0 Read/Write R/W R/W -- -- -- R/W R/W R/W ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs wait control, and selects the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and read only when the ICE bit is set to 1 in ICCR. ICMR is initialized to H'38 by a reset and in hardware standby mode. Bit 7--MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or LSB-first. Bit 7: MLS Description 0 MSB-first 1 LSB-first (Initial value) Bit 6--Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data and the acknowledge bit, in acknowledgement mode. When WAIT is set to 1, after the fall of the clock for the final data bit, a wait state begins (with SCL staying at the low level). When bit IRIC is cleared in ICSR, the wait ends and the acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted. Bit 6: WAIT Description 0 Data and acknowledge transferred consecutively 1 Wait inserted between data and acknowledge 288 (Initial value) Bits 5 to 3--Reserved: These bits cannot be modified and are always read as 1. Bits 2 to 0--Bit Counter (BC2 to BC0): BC2 to BC0 specify the number of bits to be transferred next. When the ACK bit is cleared to 0 in ICCR (acknowledgement mode), the data is transferred with one additional acknowledge bit. BC2 to BC0 settings should be made during an interval between transfer frames. If BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 by a reset and when a start condition is detected. The value returns to 000 at the end of a data transfer, including the acknowledge. Bits/Frame Bit 2: BC2 Bit 1: BC1 Bit 0: BC0 Serial Mode Acknowledgement Mode 0 0 0 8 9 1 1 2 0 2 3 1 3 4 0 4 5 1 5 6 0 6 7 1 7 8 1 1 0 1 13.2.4 (Initial value) I2C Bus Control Register (ICCR) Bit 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACK CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W ICCR is an 8-bit readable/writable register that enables or disables the I2C bus interface, enables or disables interrupts, and selects master or slave mode, transmit or receive, acknowledgement or serial mode, and the clock frequency. ICCR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--I2C Bus Interface Enable (ICE): Selects whether or not to use the I2C bus interface. When ICE is set to 1, the SCL and SDA signals are assigned to input/output pins and transfer operations are enabled. When ICE is cleared to 0, the interface module is disabled. 289 The SAR register can be accessed when ICE is 0. The ICMR register can be accessed when ICE is 1. Bit 7: ICE Description 0 Interface module disabled, with SCL and SDA signals in high-impedance state (Initial value) 1 Interface module enabled for transfer operations (pins SCL and SDA are driving the bus*) Note: * Pin SDA is multiplexed with the WAIT input pin. In expanded mode, WAIT input has priority for this pin. Bit 6--I2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C bus interface to the CPU. Bit 6: IEIC Description 0 Interrupts disabled 1 Interrupts enabled (Initial value) Bit 5--Master/Slave Select (MST) Bit 4--Transmit/Receive Select (TRS) MST selects whether the I2C bus interface operates in master mode or slave mode. TRS selects whether the I2C bus interface operates in transmit mode or receive mode. In master mode, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. In slave receive mode with the addressing format (FS = 0), hardware automatically selects transmit or receive mode according to the R/W bit in the first byte after a start condition. MST and TRS select the operating mode as follows. Bit 5: MST Bit 4: TRS Operating Mode 0 0 Slave receive mode 1 Slave transmit mode 0 Master receive mode 1 Master transmit mode 1 290 (Initial value) Bit 3--Acknowledgement Mode Select (ACK): Selects acknowledgement mode or serial mode. In acknowledgement mode (ACK = 0), data is transferred in frames consisting of the number of data bits selected by BC2 to BC0 in ICMR, plus an extra acknowledge bit. In serial mode (ACK = 1), the number of data bits selected by BC2 to BC0 in ICMR is transferred as one frame. Bit 3: ACK Description 0 Acknowledgement mode 1 Serial mode (Initial value) Bits 2 to 0--Serial Clock Select (CKS2 to CKS0): These bits, together with the ICCX bit in the STCR register, select the serial clock frequency in master mode. They should be set according to the required transfer rate. Transfer Rate* (STCR) Bit 2: IICX CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock oP = 5 MHz oP = 8 MHz oP = 10 MHz oP = 16 MHz 0 0 0 oP/28 179 kHz 286 kHz 357 kHz 571 kHz 1 oP/40 125 kHz 200 kHz 250 kHz 400 kHz 0 oP/48 104 kHz 167 kHz 208 kHz 333 kHz 1 oP/64 78.1 kHz 125 kHz 156 kHz 250 kHz 0 oP/80 62.5 kHz 100 kHz 125 kHz 200 kHz 1 oP/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 0 oP/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 1 oP/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 0 oP/56 89.3 kHz 143 kHz 179 kHz 286 kHz 1 oP/80 62.5 kHz 100 kHz 125 kHz 200 kHz 0 oP/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 1 oP/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 0 oP/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 1 oP/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 0 oP/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 1 oP/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 0 1 1 0 1 1 0 0 1 1 0 1 Note: * oP = o. The shaded setting exceeds the maximum transfer rate in the standard I2C bus specifications. 291 13.2.5 I2C Bus Status Register (ICSR) Bit 7 6 5 4 3 2 1 0 BBSY IRIC SCP -- AL AAS ADZ ACKB Initial value 0 0 1 1 0 0 0 0 Read/Write R/W R/(W)* W -- R/(W)* R/(W)* R/(W)* R/W Note: * Only 0 can be written, to clear the flag. ICSR is an 8-bit readable/writable register with flags that indicate the status of the I2C bus interface. It is also used for issuing start and stop conditions, and recognizing and controlling acknowledge data. ICSR is initialized to H'30 by a reset and in hardware standby mode. Bit 7--Bus Busy (BBSY): This bit can be read to check whether the I2C bus (SCL and SDA) is busy or free. In master mode this bit is also used in issuing start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0. To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, use a MOV instruction to write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode. Bit 7: BBSY Description 0 Bus is free This bit is cleared when a stop condition is detected. 1 Bus is busy This bit is set when a start condition is detected. 292 (Initial value) Bit 6--I2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, and when bus arbitration is lost in master transmit mode. IRIC is set at different timings depending on the ACK bit in ICCR and WAIT bit in ICMR. See the item on IRIC Set Timing and SCL Control in section 13.3.6 IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC. Bit 6: IRIC Description 0 Waiting for transfer, or transfer in progress (Initial value) To clear this bit, the CPU must read IRIC when IRIC = 1, then write 0 in IRIC 1 Interrupt requested This bit is set to 1 at the following times: Master mode * End of data transfer * When bus arbitration is lost Slave mode (when FS = 0) * When the slave address is matched, and whenever a data transfer ends at the timing of a retransmit start condition after address matching or a stop condition is detected * When a general call address is detected, and whenever a data transfer ends at the timing of a retransmit start condition after address detection or a stop condition is detected Slave mode (when FS = 1) * End of data transfer Bit 5--Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A start condition for retransmit is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP. This bit always reads 1. Written data is not stored. Bit 5: SCP Description 0 Writing 0 issues a start or stop condition, in combination with BBSY 1 Reading always results in 1 (Initial value) Writing is ignored Bit 4--Reserved: This bit cannot be modified and is always read as 1. 293 Bit 3--Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The I2C bus interface monitors the bus. When two or more master devices attempt to seize the bus at nearly the same time, if the I 2C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. At the same time, it sets the IRIC bit in ICSR to generate an interrupt request. AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 3: AL Description 0 Bus arbitration won (Initial value) This bit is cleared to 0 at the following times: * When ICDR data is written (transmit mode) or read (receive mode) * When AL is read while AL = 1, then 0 is written in AL 1 Arbitration lost This bit is set to 1 at the following times: * If the internal SDA signal and bus line disagree at the rise of SCL in master transmit mode * If the internal SCL is high at the fall of SCL in master transmit mode Bit 2--Slave Address Recognition Flag (AAS): When the addressing format is selected (FS = 0) in slave receive mode, this flag is set to 1 if the first byte following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected. AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 2: AAS Description 0 Slave address or general call address not recognized (Initial value) This bit is cleared to 0 at the following times: * When ICDR data is written (transmit mode) or read (receive mode) * When AAS is read while AAS = 1, then 0 is written in AAS 1 Slave address or general call address recognized This bit is set to 1 at the following times: * When the slave address or general call address is detected in slave receive mode 294 Bit 1--General Call Address Recognition Flag (ADZ): When the addressing format is selected (FS = 0) in slave receive mode, this flag is set to 1 if the first byte following a start condition is the general call address (H'00). ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive mode. Bit 1: ADZ Description 0 General call address not recognized (Initial value) This bit is cleared to 0 at the following times: * When ICDR data is written (transmit mode) or read (receive mode) * When ADZ is read while ADZ = 1, then 0 is written in ADZ 1 General call address recognized This bit is set to 1 when the general call address is detected in slave receive mode Bit 0--Acknowledge Bit (ACKB): Stores acknowledge data in acknowledgement mode. In transmit mode, after the receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In receive mode, after data has been received, the acknowledge data set in this bit is sent to the transmitting device. When this bit is read, if TRS = 1, the value loaded from the bus line is read. If TRS = 0, the value set by internal software is read. Bit 0: ACKB Description 0 Receive mode: 0 is output at acknowledge output timing (Initial value) Transmit mode: indicates that the receiving device has acknowledged the data 1 Receive mode: 1 is output at acknowledge output timing Transmit mode: indicates that the receiving device has not acknowledged the data 295 13.2.6 Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICD IICX IICE STAC MPE ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--I2C Extra Buffer Select (IICS): Makes bits 7 to 4 of port A into output buffers similar to SCL and SDA. Used when an I2C bus interface is implemented by software alone. Bit 7: IICS Description 0 PA7 to PA 4 are normal input/output pins 1 PA7 to PA 4 are input/output pins that can drive the bus (Initial value) Bit 6--I2C Extra Buffer Reserve (IICD): This bit is reserved, but it can be written and read. Its initial value is 0. Bit 5--I2C Transfer Rate Select (IICX): This bit, in combination with bits CKS2 to CKS0 in ICCR, selects the transfer rate in master mode. For details regarding the transfer rate, refer to section 13.2.4, I2C Bus Control Register (ICCR). Bit 4--I2C Master Enable (IICE): Controls CPU access to the data and control registers (ICCR, ICSR, ICDR, ICMR/SAR) of the I 2C bus interface. Bit 4: IICE Description 0 CPU access to I 2C bus interface data and control registers is disabled (Initial value) 1 CPU access to I 2C bus interface data and control registers is enabled Bit 3--Slave Input Switch (STAC): Switches host interface input pins. For details, see section 14, Host Interface. Bit 2--Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication function on channels SCI0 and SCI1. For details, see section 12, Serial Communication Interface. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits select the clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit Timers. 296 13.3 Operation 13.3.1 I2C Bus Data Format The I2C bus interface has three data formats: two addressing formats, shown as (a) and (b) in figure 13.3, and a non-addressing format, shown as (c) in figure 13.4. The first byte following a start condition always consists of 8 bits. Figure 13.5 shows the I2C bus timing. (a) Addressing format (FS = 0) S SLA R/W A 1 1 7 1 DATA n A A/A P 1 1 1 n: Bit count (n = 1 to 8) m: Frame count (m 1) m 1 (b) Addressing format (retransmit start condition, FS = 0) S SLA R/W 7 1 1 A DATA A/A n1 1 S 1 SLA 1 m1 1 R/W 7 A 1 DATA n2 1 A/A P 1 1 m2 1 n1 and n2: Bit count (n1 and n2 = 1 to 8) m1 and m2: Frame count (m1 and m2 1) Figure 13.3 I2C Bus Data Formats (Addressing Formats) (c) Non-addressing format (FS = 1) S 1 DATA A 8 1 1 DATA n A A/A P 1 1 1 m n: Bit count (n = 1 to 8) m: Frame count (m 1) Figure 13.4 I2C Bus Data Format (Non-Addressing Format) Legend: S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address, by which the master device selects a slave device. R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. 297 A: Acknowledge. The receiving device (the slave in master transmit mode, or the master in master receive mode) drives SDA low to acknowledge a transfer. If transfers need not be acknowledged, set the ACK bit to 1 in ICCR to keep the interface from generating the acknowledge signal and its clock pulse. DATA: Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or LSB-first format is selected by bit MLS in ICMR. P: Stop condition. The master device drives SDA from low to high while SCL is high. SDA SCL S 1-7 8 9 SLA R/W A 1-7 DATA 8 9 A 1-7 DATA 8 9 A/A P Figure 13.5 I2C Bus Timing 13.3.2 Master Transmit Operation In master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The transmit procedure and operations in master transmit mode are described below. 1. Set bits MLS and WAIT in ICMR and bits ACK and CKS2 to CKS0 in ICCR according to the operating mode. Set bit ICE in ICCR to 1. 2. Read BBSY in ICSR, check that the bus is free, then set MST and TRS to 1 in ICCR to select master transmit mode. After that, write 1 in BBSY and 0 in SCP. This generates a start condition by causing a high-to-low transition of SDA while SCL is high. 3. Write data in ICDR. The master device outputs the written data together with a sequence of transmit clock pulses at the timing shown in figure 13.6. If FS is 0 in SAR, the first byte following the start condition contains a 7-bit slave address and indicates the transmit/receive direction. The selected slave device (the device with the matching slave address) drives SDA low at the ninth transmit clock pulse to acknowledge the data. 4. When one byte of data has been transmitted, IRIC is set to 1 in ICSR at the rise of the ninth transmit clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. After one frame has been transferred, SCL is automatically brought to the low level in synchronization with the internal clock and held low. 298 5. Software clears IRIC to 0 in ICSR. 6. To continue transmitting, write the next transmit data in ICDR. Transmission of the next byte will begin in synchronization with the internal clock. Steps 4 to 6 can be repeated to transmit data continuously. To end the transmission, write 0 in BBSY and 0 in SCP in ICSR. This generates a stop condition by causing a low-to-high transition of SDA while SCL is high. SCL SDA (master output) 1 2 3 Bit 7 Bit 6 Bit 5 4 5 Bit 4 Bit 3 6 Bit 2 Bit 1 SDA (slave output) 8 9 Bit 0 1 Bit 7 A Interrupt request IRIC User processing 7 2. Write BBSY = 1 and SCP = 0 3. Write to ICDR 5. Clear IRIC 6. Write to ICDR Figure 13.6 Timing in Master Transmit Mode (MLS = WAIT = ACK = 0) 299 13.3.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits the data. The receive procedure and operations in master receive mode are described below. See also figure 13.7. 1. Clear TRS to 0 in ICCR to switch from transmit mode to receive mode. 2. Read ICDR to start receiving. When ICDR is read, a receive clock is output in synchronization with the internal clock, and data is received. At the ninth clock pulse the master device drives SDA low to acknowledge the data. 3. When one byte of data has been received, IRIC is set to 1 in ICSR at the rise of the ninth receive clock pulse. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. After one frame has been transferred, SCL is automatically brought to the low level in synchronization with the internal clock and held low. 4. Software clears IRIC to 0 in ICSR. 5. When ICDR is read, receiving of the next data starts in synchronization with the internal clock. Steps 3 to 5 can be repeated to receive data continuously. To stop receiving, set TRS to 1, read ICDR, then write write 0 in BBSY and 0 in SCP in ICSR. This generates a stop condition by causing a low-to-high transition of SDA while SCL is high. If it is not necessary to acknowledge each byte of data, set ACKB to 1 in ICSR before receiving starts. 300 Master transmit mode SCL SDA (slave output) Master receive mode 9 1 A Bit 7 2 3 Bit 6 Bit 5 4 5 Bit 4 Bit 3 6 7 Bit 2 Bit 1 8 1 Bit 0 SDA (master output) IRIC 9 A Interrupt request Interrupt request User processing 2. Read ICDR 4. Clear IRIC 5. Read ICDR Figure 13.7 Timing in Master Receive Mode (MLS = WAIT = ACK = ACKB = 0) 301 13.3.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the transmit clock and returns an acknowledge signal. The transmit procedure and operations in slave transmit mode are described below. 1. Set bits MLS and WAIT in ICMR and bits MST, TRS, ACK, and CKS2 to CKS0 in ICCR according to the operating mode. Set bit ICE in ICCR to 1, establishing slave receive mode. 2. After the slave device detects a start condition, if the first byte matches its slave address, at the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the same time, IRIC is set to 1 in ICSR, generating an interrupt. If the eighth data bit (R/W) is 1, the TRS bit is set to 1 in ICCR, automatically causing a transition to slave transmit mode. The slave device holds SCL low from the fall of the transmit clock until data is written in ICDR. 3. Software clears IRIC to 0 in ICSR. 4. Write data in ICDR. The slave device outputs the written data serially in step with the clock output by the master device, with the timing shown in figure 13.8. 5. When one byte of data has been transmitted, at the rise of the ninth transmit clock pulse IRIC is set to 1 in ICSR. If IEIC is set to 1 in ICCR, a CPU interrupt is requested. The slave device holds SCL low from the fall of the transmit clock until data is written in ICDR. The master device drives SDA low at the ninth clock pulse to acknowledge the data. The acknowledge signal is stored in ACKB in ICSR, and can be used to check whether the transfer was carried out normally. 6. Software clears IRIC to 0 in ICSR. 7. To continue transmitting, write the next transmit data in ICDR. Steps 5 to 7 can be repeated to transmit continuously. To end the transmission, write H'FF in ICDR. When a stop condition is detected (a low-to-high transition of SDA while SCL is high), BBSY will be cleared to 0 in ICSR. 302 Slave receive mode SCL (master output) 8 Slave transmit mode 9 1 A Bit 7 2 3 4 5 6 7 8 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 SCL (slave output) SDA (slave output) SDA (master R/W output) IRIC User processing Bit 7 A Interrupt request Interrupt request 3. Clear IRIC 4. Write to ICDR 6. Clear IRIC 7. Write to ICDR Figure 13.8 Timing in Slave Transmit Mode (MLS = WAIT = ACK = 0) 303 13.3.5 Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The receive procedure and operations in slave receive mode are described below. See also figure 13.9. 1. Set bits MLS and WAIT in ICMR and bits MST, TRS, and ACK in ICCR according to the operating mode. Set bit ICE in ICCR to 1, establishing slave receive mode. 2. A start condition output by the master device sets BBSY to 1 in ICSR. 3. After the slave device detects the start condition, if the first byte matches its slave address, at the ninth clock pulse the slave device drives SDA low to acknowledge the transfer. At the same time, IRIC is set to 1 in ICSR. If IEIC is 1 in ICCR, a CPU interrupt is requested. The slave device holds SCL low from the fall of the receive clock until it has read the data in ICDR. 4. Software clears IRIC to 0 in ICSR. 5. When ICDR is read, receiving of the next data starts. Steps 4 and 5 can be repeated to receive data continuously. When a stop condition is detected (a low-to-high transition of SDA while SCL is high), BBSY is cleared to 0 in ICSR. Start condition SCL (master output) 1 2 3 4 5 6 7 8 9 1 SCL (slave output) SDA (master output Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 SDA (slave output) A Interrupt request IRIC User processing 4. Clear IRIC Figure 13.9 Timing in Slave Receive Mode (MLS = WAIT = ACK = ACKB = 0) 304 5. Read ICDR 13.3.6 IRIC Set Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR and ACK bit in ICCR. SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figure 13.10 shows the IRIC set timing and SCL control. (a) When WAIT = 0 and ACK = 0 SCL SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) (b) When WAIT = 1 and ACK = 0 SCL SDA 7 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Note: The ICDR write (transmit) or read (receive) following the clearing of IRIC should be executed after the rise of SCL (ninth clock pulse). (c) When ACK = 1 SCL SDA 7 1 8 IRIC User processing Clear IRIC Write to ICDR (transmit) or read ICDR (receive) Figure 13.10 IRIC Set Timing and SCL Control 305 13.3.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 13.11 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. Sampling clock C SCL or SDA input signal D C Q Latch D Q Latch Match detector t Sampling clock t: System clock Figure 13.11 Block Diagram of Noise Canceler 306 Internal SCL or SDA signal 13.3.8 Sample Flowcharts Figures 13.12 to 13.15 show typical flowcharts for using the I2C bus interface in each mode. Start Initialize Read BBSY in ICSR No 1 BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR 2 Write BBSY = 1 and SCP = 0 in ICSR 3 4 Write transmit data in ICDR 1. Test the status of the SCL and SDA lines. 2. Select master transmit mode. 3. Generate a start condition. 4. Set transmit data for the first byte (slave address + R/W). 5. Wait for 1 byte to be transmitted. 6. Test for acknowledgement by the designated slave device. 7. Set transmit data for the second and subsequent bytes. 8. Wait for 1 byte to be transmitted. 9. Test for end of transfer. 10. Generate a stop condition. Read IRIC in ICSR 5 No IRIC = 1? Yes Clear IRIC in ICSR Read ACKB in ICSR ACKB = 0? 6 No Yes Transmit mode? No Master receive mode Yes Write transmit data in ICDR Read IRIC in ICSR No 7 8 IRIC = 1? Yes Clear IRIC in ICSR Read ACKB in ICSR 9 No End of transmission (ACKB = 1)? Yes Write BBSY = 0 and SCP = 0 in ICSR 10 End Figure 13.12 Flowchart for Master Transmit Mode (Example) 307 Master receive mode Set TRS = 0 in ICCR 1 Set ACKB = 0 in ICSR 2 1. Select receive mode. 2. Set acknowledgement data. 3. Start receiving. The first read is a dummy read. Last receive? 4. Wait for 1 byte to be received. Yes 5. Set acknowledgement data for the last receive. No Read ICDR Read IRIC in ICSR No 6. Start the last receive. 3 7. Wait for 1 byte to be received. 8. Select transmit mode. 4 IRIC = 1? Yes 9. Read the last receive data (if ICDR is read without selecting transmit mode, receive operations will resume). 10. Generate a stop condition. Clear IRIC in ICSR No Set ACKB = 1 in ICSR 5 Read ICDR 6 Read IRIC in ICSR 7 IRIC = 1? Yes Clear IRIC in ICSR Set TRS = 1 in ICCR 8 Read ICDR 9 Write BBSY = 0 and SCP = 0 in ICSR 10 End Figure 13.13 Flowchart for Master Receive Mode (Example) 308 Slave transmit mode Write transmit data in ICDR 1 2. Wait for 1 byte to be transmitted. Read IRIC in ICSR No 1. Set transmit data for the second and subsequent bytes. 2 3. Test for end of transfer. 4. Select slave receive mode. IRIC = 1? 5. Dummy read (to release the SCL line). Yes Clear IRIC in ICSR Read ACKB in ICSR No End of transmission (ACKB = 1?) 3 Yes Write TRS = 0 in ICCR 4 Read ICDR 5 End Figure 13.14 Flowchart for Slave Transmit Mode (Example) 309 Start Initialize Set MST = 0 and TRS = 0 in ICCR 1 Write ACKB = 0 in ICSR Read IRIC in ICSR 2 No IRIC = 1? Yes Clear IRIC in ICSR Read AAS and ADZ in ICSR AAS = 1 and ADZ = 0? No General call address processing * Description omitted Yes Read TRS in ICCR No TRS = 0? Slave transmit mode Yes Last receive? No Read ICDR Yes 3 Read IRIC in ICSR No 4 IRIC = 1? Yes Clear IRIC in ICSR No Set ACKB = 1 in ICSR 5 Read ICDR 6 Read IRIC in ICSR 7 1. Select slave receive mode. 2. Wait for the first byte to be received. 3. Start receiving. The first read is a dummy read. 4. Wait for the transfer to end. 5. Set acknowledgement data for the last receive. 6. Start the last receive. 7. Wait for the transfer to end. 8. Read the last receive data. IRIC = 1? Yes Clear IRIC in ICSR Read ICDR 8 End Figure 13.15 Flowchart for Slave Receive Mode (Example) 310 13.4 Application Notes * In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions, after issuing the instruction that generates the start condition, read the relevant ports, check that SCL and SDA are both low, then issue the instruction that generates the stop condition. * Either of the following two conditions will start the next transfer. Pay attention to these conditions when reading or writing to ICDR. Write access to ICDR when ICE = 1 and TRS = 1 Read access to ICDR when ICE = 1 and TRS = 0 * The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance and load capacitance so that the SCL rise time falls below the values given in the table below. CKDBL IICX tcyc Display 0 0 7.5tcyc 0 1 1 0 1 1 17.5tcyc 37.5tcyc Time Display o = 5 MHz o = 8 MHz o = 10 MHz o = 16 MHz Normal mode 1000 ns 937 ns 750 ns 486 ns High-speed mode 300 ns 300 ns 300 ns 300 ns Normal mode 1000 ns 1000 ns 1000 ns 1000 ns High-speed mode 300 ns 300 ns 300 ns 300 ns Normal mode 1000 ns 1000 ns 1000 ns 1000 ns High-speed mode 300 ns 300 ns 300 ns 300 ns * Note on Issuance of Retransmission Start Condition When issuing a retransmission start condition, the condition must be issued after the SCL clock falls during the acknowledge bit reception period. After the end of the acknowledge bit, the next data should be written to ICDR after SCL goes high. Figure 13.16 shows the recommended program flow for issuing a retransmission start condition. A timing chart for the flowchart in figure 13.16 is shown in figure 13.17. 311 Read IRIC in ICSR (1) Confirm completion of 1byte transmission IRIC = 1? (2) Confirm that SCL is low Clear IRIC in ICSR (3) Issue retransmission start condition No Retransmission? Other operation (5) Write transmit data Yes Note: "Read SCL" means reading DR for the SCL pin. Read SCL No (4) Confirm that SCL is high SCL = 0? Yes Write 1 to BBSY and 0 to SCP in ICSR Read SCL No SCL = 1? Yes Write data to ICDR Figure 13.16 Recommended Program Flow for Retransmission Start Condition Issuance SCL 9 SDA ACK Bit 7 IRIC (1) IRIC check (2) SCL low level determination (4) SCL high level determination (5) Transmit data setting (3) Retransmission start condition issuance Figure 13.17 Timing Chart for Retransmission Start Condition Issuance 312 * Note on Issuance of Stop Condition If the rise of SCL is weakened by external pull-up resistance R and bus load capacitance C in master mode, or if SCL is pulled to the low level by a slave device, the timing at which SCL is lowered by the internal bit synchronization circuit may be delayed by 1t SCL. If, in this case, SCL is identified as being low at the bit synchronization circuit sampling timing, and a stop condition issuing instruction is executed before the reference SCL clock next falls, as in figure 13.18, SDA will change from high to low to high while SCL remains high. As a result, a stop condition will be issued before the end of the 9th clock. Bit synchronization circuit sampling timing Reference clock SCL output 9 High interval secured Stop condition Normal operation SDA output SCL output 9 9th clock not ended Stop condition Erroneous operation SDA output VIH SCL identified as low SCL Bus line VIH SDA IRIC Stop condition issuing instruction execution timing Erroneous operation Normal operation Figure 13.18 Stop Condition Erroneous Operation Timing 313 * Countermeasure Figure 13.19 shows the recommended program flow. Read IRIC in ICSR No IRIC = 1? Yes Write data to ICDR Read ACKB in ICSR Yes Transmit data present? No ACKB = 1? Yes No Read SCL No SCL = 0? Yes Write 0 to BBSY and 0 to SCP in ICSR Figure 13.19 Recommended Program Flow * Additional Note When switching from master receive mode to master transmit mode, ensure that TRS is set to 1 before the last receive data is latched by reading ICDR. * Precautions when Clearing the IRIC Flag when Using the Wait Function If the SCL rise time exceeds the specified duration when using the wait function in the I2C bus interface's master mode, or if there is a slave device that keeps SCL low and applies a wait state, read SCL and clear the IRIC flag only after determining that SCL has gone low, as shown below. If the IRIC flag is cleared to 0 when WAIT is set to 1 and while the SCL high level duration is being extended, the SDA value may change before SCL falls, erroneously resulting in a start or stop condition. 314 SCL VIH SCL high level duration maintained SCL low level detected SDA IRIC SCL determined to be low level IRIC cleared Figure 13.20 IRIC Flag Clear Timing when WAIT = 1 Note that the clock may not be output properly during the next master send if receive data (ICDR data) is read during the time between when the instruction to issue a stop condition is executed (writing 0 to BBSY and SCP in ISSR) and when the stop condition is actually generated. In addition, overwriting of IIC control bits in order to change the send or receive operation mode or to change settings, such as for example clearing the MST bit after completion of master send or receive, should always be performed during the period indicated as (a) in Figure 13.21 below (after confirming that the BBSY bit in the ICCR register has been cleared to 0). Stop condition Start condition (a) SDA Bit 0 A SCL 8 9 Internal clock BBSY bit Master receive mode ICDR read F prohibited duration Execution of issue Stop condition generated stop condition instruction (BBSY = 0 read) (BBSY = 0 and SCP = 0 written) Start condition issued Figure 13.21 Precautions when Reading Master Receive Data 315 316 Section 14 Host Interface 14.1 Overview The H8/3437 Series has an on-chip host interface (HIF) that provides a dual-channel parallel interface between the on-chip CPU and a host processor. The host interface is available only when the HIE bit is set to 1 in SYSCR. This mode is called slave mode, because it is designed for a master-slave communication system in which the H8/3437-Series chip is slaved to a host processor. The host interface consists of four 1-byte data registers, two 1-byte status registers, a 1-byte control register, fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via five control signals from the host processor (CS1, CS2 or ECS2, HA0, IOR, and IOW or EIOW), four output signals to the host processor (GA 20, HIRQ1, HIRQ11, and HIRQ12), and an 8bit bidirectional command/data bus (HDB7 to HDB0, or XDB7 to XDB0). The CS1 and CS2 (or ECS2) signals select one of the two interface channels. Note: If one of the two interface channels will not be used, tie the unused CS pin to VCC. For example, if interface channel 1 (IDR1, ODR1, STR1) is not used, tie CS1 to VCC. 317 14.1.1 Block Diagram Figure 14.1 is a block diagram of the host interface. (Internal interrupt signals) IBF2 CS1 ECS2/CS2 IOR EIOW/IOW HA0 HDB7-HDB0/ XDB7-XDB0 Control logic IDR1 IDR2 ODR2 STR2 HICR Port 4 Port 8 Internal data bus Legend: IDR1: Input data register 1 IDR2: Input data register 2 ODR1: Output data register 1 ODR2: Output data register 2 STR1: Status register 1 STR2: Status register 2 HICR: Host interface control register Figure 14.1 Host Interface Block Diagram 318 STR1 Bus interface Module data bus Fast A20 gate control Host data bus ODR1 Host interrupt request HIRQ1 HIRQ11 HIRQ12 GA20 IBF1 14.1.2 Input and Output Pins Table 14.1 lists the input and output pins of the host interface module. Table 14.1 H/F Input/Output Pins Name Abbreviation Port I/O Function I/O read IOR P83 Input Host interface read signal I/O write* IOW P84 Input Host interface write signal EIOW P91 Chip select 1 CS 1 P82 Input Host interface chip select signal for IDR1, ODR1, STR1 Chip select 2* CS 2 P85 Input ECS 2 P90 Host interface chip select signal for IDR2, ODR2, STR2 HA 0 P80 Input Host interface address select signal Command/data In host read access, this signal selects the status registers (STR1, STR2) or data registers (ODR1, ODR2). In host write access to the data registers (IDR1, IDR2), this signal indicates whether the host is writing a command or data. Data bus HDB7-HDB0 P37-P30 I/O Host interface data bus (single-chip mode) XDB 7-XDB 0 PB7-PB0 I/O Host interface data bus (expanded modes) Host interrupt 1 HIRQ1 P44 Output Interrupt output 1 to host Host interrupt 11 HIRQ11 P43 Output Interrupt output 11 to host Host interrupt 12 HIRQ12 P45 Output Interrupt output 12 to host Gate A20 GA20 P81 Output A20 gate control signal output Note: * Selection between IOW and EIOW, and between CS 2 and ECS 2, is by the STAC bit in STCR. IOW and CS 2 are used when STAC is 0. EIOW and ECS 2 are used when STAC is 1. In this manual, both are referred to as IOW and CS2. 319 14.1.3 Register Configuration Table 14.2 lists the host interface registers. Table 14.2 HIF Registers Host Initial Value Master Address *4 Slave Address*3 CS 1 CS 2 HA0 R/W Name Abbreviation Slave *1 System control register SYSCR R/W -- H'09 H'FFC4 -- -- -- Host interface control register HICR R/W -- H'F8 H'FFF0 -- -- -- Input data register 1 IDR1 R W -- H'FFF4 0 1 0/1 *5 Output data register 1 ODR1 R/W R -- H'FFF5 0 1 0 R H'00 H'FFF6 0 1 1 W -- H'FFFC 1 0 0/1 *5 R -- H'FFFD 1 0 0 R H'00 H'FFFE 1 0 1 -- H'00 H'FFC3 -- -- -- Status register 1 STR1 R/(W) Input data register 2 IDR2 R Output data register 2 ODR2 R/W Status register 2 STR2 R/(W) Serial/timer control register STCR R/W Notes: *1 *2 *3 *4 *5 320 *2 *2 Bit 3 is a read-only bit. The user-defined bits (bits 7 to 4) are read/write accessible from the slave processor. Address when accessed from the slave processor. Pin inputs used in access from the host processor. The HA 0 input discriminates between writing of commands and data. 14.2 Register Descriptions 14.2.1 System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R R/W R/W R/W SYSCR is an 8-bit read/write register which controls chip operations. Host interface functions are enabled or disabled by the HIE bit of SYSCR. See section 3.2, System Control Register, for information on other SYSCR bits. SYSCR is initialized to H'09 by an external reset and in hardware standby mode. Bit 1--Host Interface Enable (HIE): Enables or disables the host interface. When enabled, the host interface handles host-slave data transfers, operating in slave mode. Bit 1: HIE Description 0 The host interface is disabled 1 The host interface is enabled (slave mode) 14.2.2 (Initial value) Host Interface Control Register (HICR) Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- IBFIE2 IBFIE1 FGA20E Initial value 1 1 1 1 1 0 0 0 Slave Read/Write -- -- -- -- -- R/W R/W R/W Host Read/Write -- -- -- -- -- -- -- -- HICR is an 8-bit read/write register which controls host interface interrupts and the fast A20 gate function. HICR is initialized to H'F8 by a reset and in hardware standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. 321 Bit 2--Input Buffer Full Interrupt Enable 2 (IBFIE2): Enables or disables the IBF2 interrupt to the slave CPU. Bit 2: IBFIE2 Description 0 IDR2 input buffer full interrupt is disabled 1 IDR2 input buffer full interrupt is enabled (Initial value) Bit 1-- Input Buffer Full Interrupt Enable 1 (IBFIE1): Enables or disables the IBF1 interrupt to the slave CPU. Bit 1: IBFIE1 Description 0 IDR1 input buffer full interrupt is disabled 1 IDR1 input buffer full interrupt is enabled (Initial value) Bit 0--Fast Gate A20 Enable (FGA20E): Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, a regular-speed A20 gate signal can be implemented by using software to manipulate the P81 output. Bit 0: FGA20E Description 0 Disables fast A20 gate function 1 Enables fast A20 gate function 14.2.3 (Initial value) Input Data Register 1 (IDR1) Bit 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Initial value -- -- -- -- -- -- -- -- Slave Read/Write R R R R R R R R Host Read/Write W W W W W W W W IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. When CS1 is low, information on the host data bus is written into IDR1 at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STR1 to indicate whether the written information is a command or data. The initial values of IDR1 after a reset or standby are undetermined. 322 14.2.4 Output Data Register 1 (ODR1) Bit Initial value 7 6 5 4 3 2 1 0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 -- -- -- -- -- -- -- -- Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Host Read/Write R R R R R R R R ODR1 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the host processor. The ODR1 contents are output on the host data bus when HA0 is low, CS1 is low, and IOR is low. The initial values of ODR1 after a reset or standby are undetermined. 14.2.5 Status Register 1 (STR1) Bit 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF 0 0 0 0 0 0 0 0 Slave Read/Write R/W R/W R/W R/W R R/W R R Host Read/Write R R R R R R R R Initial value STR1 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors. STR1 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4 and Bit 2--Defined by User (DBU): The user can use these bits as necessary. Bit 3--Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR1, and indicates whether IDR1 contains data or a command. Bit 3: C/D Description 0 Contents of IDR1 are data 1 Contents of IDR1 are a command (Initial value) 323 Bit 1--Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR1. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR1. Bit 1: IBF Description 0 This bit is cleared when the slave processor reads IDR1 1 This bit is set when the host processor writes to IDR1 (Initial value) Bit 0--Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to 0 when the host processor reads ODR1. Bit 0: OBF Description 0 This bit is cleared when the host processor reads ODR1 1 This bit is set when the slave processor writes to ODR1 (Initial value) Table 14.3 shows the conditions for setting and clearing the STR1 flags. Table 14.3 Set/Clear Timing for STR1 Flags Flag Setting Condition Clearing Condition C/D Rising edge of host's write signal (IOW) when HA 0 is high Rising edge of host's write signal (IOW) when HA 0 is low IBF Rising edge of host's write signal (IOW) when writing to IDR1 Falling edge of slave's internal read signal (RD) when reading IDR1 OBF Falling edge of slave's internal write signal (WR) when writing to ODR1 Rising edge of host's read signal (IOR) when reading ODR1 14.2.6 Input Data Register 2 (IDR2) Bit 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Initial value -- -- -- -- -- -- -- -- Slave Read/Write R R R R R R R R Host Read/Write W W W W W W W W IDR2 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the host processor. When CS2 is low, information on the host data bus is written into IDR2 at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STR2 to indicate whether the written information is a command or data. The initial values of IDR2 after a reset or standby are undetermined. 324 14.2.7 Output Data Register 2 (ODR2) Bit Initial value 7 6 5 4 3 2 1 0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 -- -- -- -- -- -- -- -- Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Host Read/Write R R R R R R R R ODR2 is an 8-bit read/write register to the slave processor, and an 8-bit read-only register to the host processor. The ODR2 contents are output on the host data bus when HA0 is low, CS2 is low, and IOR is low. The initial values of ODR2 after a reset or standby are undetermined. 14.2.8 Status Register 2 (STR2) Bit 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF 0 0 0 0 0 0 0 0 Slave Read/Write R/W R/W R/W R/W R R/W R R Host Read/Write R R R R R R R R Initial value STR2 is an 8-bit register that indicates status information during host interface processing. Bits 3, 1, and 0 are read-only bits to both the host and slave processors. STR2 is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4 and Bit 2--Defined by User (DBU): The user can use these bits as necessary. Bit 3--Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR2, and indicates whether IDR2 contains data or a command. Bit 3: C/D Description 0 Contents of IDR2 are data 1 Contents of IDR2 are a command (Initial value) 325 Bit 1--Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads IDR2. Bit 1: IBF Description 0 This bit is cleared when the slave processor reads IDR2 1 This bit is set when the host processor writes to IDR2 (Initial value) Bit 0--Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to 0 when the host processor reads ODR2. Bit 0: OBF Description 0 This bit is cleared when the host processor reads ODR2 1 This bit is set when the slave processor writes to ODR2 (Initial value) Table 14.4 shows the conditions for setting and clearing the STR2 flags. Table 14.4 Set/Clear Timing for STR2 Flags Flag Setting Condition Clearing Condition C/D Rising edge of host's write signal (IOW) when HA 0 is high Rising edge of host's write signal (IOW) when HA 0 is low IBF Rising edge of host's write signal (IOW) when writing to IDR2 Falling edge of slave's internal read signal (RD) when reading IDR2 OBF Falling edge of slave's internal write signal (WR) when writing to ODR2 Rising edge of host's read signal (IOR) when reading ODR2 326 14.2.9 Serial/Timer Control Register (STCR) Bit 7 6 5 4 3 2 1 0 IICS IICD IICX IICE STAC MPE ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W STCR is an 8-bit readable/writable register that controls the I 2C bus interface and host interface, controls the SCI operating mode, and selects the TCNT clock source in the 8-bit timers. STCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 4--I2C Control (IICS, IICD, IICX, IICE): These bits are used to control the I2C bus interface. For details, see section 13, I2C Bus Interface. Bit 3--Slave Input Switch (STAC): Controls switching of host interface input pins. Settings of this bit are valid only when the host interface is enabled (slave mode). Bit 3: STAC Description 0 In port 8, P85 switches over to CS 2, and P8 4 to IOW 1 In port 9, P91 switches over to EIOW, and P9 0 to ECS 2 (Initial value) Bit 2--Multiprocessor Enable (MPE): Controls the operating mode of SCI0 and SCI1. For details, see section 12, Serial Communication Interface. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): Together with bits CKS2 to CKS0 in TCR, these bits select timer counter clock inputs. For details, see section 9, 8-Bit Timers. 327 14.3 Operation 14.3.1 Host Interface Operation The host interface is activated by setting the HIE bit (bit 1) to 1 in SYSCR, establishing slave mode. Activation of the host interface (entry to slave mode) appropriates the related I/O lines in port 3 or B (data), port 8 or 9 (control) and port 4 (host interrupt requests) for interface use. For host interface read/write timing diagrams, see section 23.3.8, Host Interface Timing. 14.3.2 Control States Table 14.5 indicates the slave operations carried out in response to host interface signals from the host processor. Table 14.5 Host Interface Operation CS 2 CS 1 IOR IOW HA0 Slave Operation 1 0 0 0 0 Prohibited 1 Prohibited 0 Data read from output data register 1 (ODR1) 1 Status read from status register 1 (STR1) 0 Data write to input data register 1 (IDR1) 1 Command write to input data register 1 (IDR1) 0 Idle state 1 Idle state 0 Prohibited 1 Prohibited 0 Data read from output data register 2 (ODR2) 1 Status read from status register 2 (STR2) 0 Data write to input data register 2 (IDR2) 1 Command write to input data register 2 (IDR2) 0 Idle state 1 Idle state 1 1 0 1 0 1 0 0 1 1 0 1 328 14.3.3 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086*-family CPU. In slave mode, a regular-speed A20 gate signal can be output under software control, or a fast A20 gate signal can be output under hardware control. Fast A20 gate output is enabled by setting the FGA20E bit (bit 0) to 1 in HICR (H'FFF0). Note: * Intel microprocessor. Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. If the data follows an H'D1 command, software copies bit 1 of the data and outputs it at the gate A20 pin (P8 1/GA20). Fast A20 Gate Operation: When the FGA20E bit is set to 1, P81/GA20 is used for output of a fast A20 gate signal. Bit P81DDR must be set to 1 to assign this pin for output. The initial output from this pin will be a logic 1, which is the initial DR value. Afterward, the host processor can manipulate the output from this pin by sending commands and data. This function is available only when register IDR1 is accessed using CS1. Slave logic decodes the commands input from the host processor. When an H'D1 host command is detected, bit 1 of the data following the host command is output from the GA20 output pin. This operation does not depend on software or interrupts, and is faster than the regular processing using interrupts. Table 14.6 lists the conditions that set and clear GA20 (P81). Figure 14.2 describes the GA20 output in flowchart form. Table 14.7 indicates the GA20 output signal values. Table 14.6 GA20 (P81) Set/Clear Timing Pin Name Setting Condition Clearing Condition GA20 (P8 1) Rising edge of the host's write signal (IOW) when bit 1 of the written data is 1 and the data follows an H'D1 host command Rising edge of the host's write signal (IOW) when bit 1 of the written data is 0 and the data follows an H'D1 host command 329 Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of P81/GA20 Figure 14.2 GA20 Output 330 Table 14.7 Fast A20 Gate Output Signal HA0 Data/Command Internal CPU Interrupt Flag GA20 (PB1) Remarks 1 H'D1 command 0 Q Turn-on sequence *1 0 "1" data 0 1 1 H'FF command 0 Q (1) 1 H'D1 command 0 Q *2 0 "0" data 0 0 1 H'FF command 0 Q (0) 1 H'D1 command 0 Q *1 0 "1" data 0 1 1/0 Command other than H'FF and H'D1 1 Q (1) 1 H'D1 command 0 Q *2 0 "0" data 0 0 1/0 Command other than H'FF and H'D1 1 Q (0) 1 H'D1 command 0 Q 1 Command other than H'D1 1 Q 1 H'D1 command 0 Q 1 H'D1 command 0 Q 1 H'D1 command 0 Q 0 Any data 0 1/0 1 H'D1 command 0 Q (1/0) Turn-off sequence Short turn-on sequence Short turn-off sequence Cancelled sequence Retriggered sequence Consecutively executed sequences Notes: *1 Arbitrary data with bit 1 set to 1. *2 Arbitrary data with bit 1 cleared to 0. 331 14.4 Interrupts 14.4.1 IBF1, IBF2 The host interface can request two interrupts to the slave CPU: IBF1 and IBF2. They are input buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is enabled when the corresponding enable bit is set (table 14.8). Table 14.8 Input Buffer Full Interrupts Interrupt Description IBF1 Requested when IBFIE1 is set to 1 and IDR1 is full IBF2 Requested when IBFIE2 is set to 1 and IDR2 is full 14.4.2 HIRQ 11, HIRQ 1, and HIRQ12 In slave mode (when HIE = 1 in SYSCR), three bits in the port 4 data register (P4DR) can be used as host interrupt request latches. These three P4DR bits are cleared to 0 by the host processor's read signal (IOR). If CS1 and HA0 are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared to 0. If CS2 and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to 0. To generate a host interrupt request, normally on-chip software writes 1 to the corresponding bit. In processing the interrupt, the host's interrupt-handling routine reads the output data register (ODR1 or ODR2), and this clears the host interrupt latch to 0. Table 14.9 indicates how these bits are set and cleared. Figure 14.3 shows the processing in flowchart form. Table 14.9 Host Interrupt Set/Clear Conditions Host Interrupt Signal Setting Condition Clearing Condition HIRQ11 (P4 3) Slave CPU reads 0 from P4DR bit 3, then writes 1 Slave CPU writes 0 in P4DR bit 3, or host reads output data register 2 HIRQ1 (P4 4) Slave CPU reads 0 from P4DR bit 4, then writes 1 Slave CPU writes 0 in P4DR bit 4, or host reads output data register 1 HIRQ12 (P4 5) Slave CPU reads 0 from P4DR bit 5, then writes 1 Slave CPU writes 0 in P4DR bit 5, or host reads output data register 1 332 Slave CPU Master CPU Write to ODR Write 1 to P4DR No HIRQ output high Interrupt initiation HIRQ output low ODR read P4DR = 0? Yes No All bytes transferred? Yes Hardware operations Software operations Figure 14.3 HIRQ Output Flowchart 14.5 Application Note The host interface provides buffering of asynchronous data from the host and slave processors, but an interface protocol must be followed to implement necessary functions and avoid data contention. For example, if the host and slave processors try to access the same input or output data register simultaneously, the data will be corrupted. Interrupts can be used to design a simple and effective protocol. 333 334 Section 15 A/D Converter 15.1 Overview The H8/3437 Series includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. 15.1.1 Features A/D converter features are listed below. * 10-bit resolution * Eight input channels * Selectable analog conversion voltage range The analog voltage conversion range can be programmed by input of an analog reference voltage at the AVref pin. * High-speed conversion Conversion time: minimum 8.4 s per channel (with 16-MHz system clock) * Two conversion modes Single mode: A/D conversion of one channel Scan mode: continuous conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * A/D conversion can be externally triggered * A/D interrupt requested at end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. 335 15.1.2 Block Diagram Figure 15.1 shows a block diagram of the A/D converter. Internal data bus AVSS AN 0 AN 5 ADCR ADCSR ADDRD - AN 2 AN 4 ADDRC + AN 1 AN 3 ADDRB 10-bit D/A ADDRA AVref Successiveapproximations register AVCC Bus interface Module data bus Analog multiplexer oP/8 Comparator Control circuit Sample-andhold circuit oP/16 AN 6 AN 7 ADI interrupt signal ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 15.1 A/D Converter Block Diagram 336 15.1.3 Input Pins Table 15.1 lists the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN 0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. AVref is the A/D conversion reference voltage. Table 15.1 A/D Converter Pins Pin Name Abbreviation I/O Function Analog power supply pin AVCC Input Analog power supply Analog ground pin AVSS Input Analog ground and reference voltage Reference voltage pin AVref Input Analog reference voltage Analog input pin 0 AN 0 Input Group 0 analog inputs Analog input pin 1 AN 1 Input Analog input pin 2 AN 2 Input Analog input pin 3 AN 3 Input Analog input pin 4 AN 4 Input Analog input pin 5 AN 5 Input Analog input pin 6 AN 6 Input Analog input pin 7 AN 7 Input A/D external trigger input pin ADTRG Input Group 1 analog inputs External trigger input for starting A/D conversion 337 15.1.4 Register Configuration Table 15.2 summarizes the A/D converter's registers. Table 15.2 A/D Converter Registers Name Abbreviation R/W Initial Value Address A/D data register A (high) ADDRAH R H'00 H'FFE0 A/D data register A (low) ADDRAL R H'00 H'FFE1 A/D data register B (high) ADDRBH R H'00 H'FFE2 A/D data register B (low) ADDRBL R H'00 H'FFE3 A/D data register C (high) ADDRCH R H'00 H'FFE4 A/D data register C (low) ADDRCL R H'00 H'FFE5 A/D data register D (high) ADDRDH R H'00 H'FFE6 A/D data register D (low) ADDRDL R H'00 H'FFE7 A/D control/status register ADCSR R/(W)* H'00 H'FFE8 A/D control register ADCR R/W H'7F H'FFE9 Note: * Only 0 can be written in bit 7, to clear the flag. 338 15.2 Register Descriptions 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit 15 ADDRn 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R Bits 15 to 6--A/D Conversion Data (AD9 to AD0): 10-bit data giving an A/D conversion result. Bits 5 to 0--Reserved: These bits cannot be modified and are always read as 0. The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D data register are reserved bits that always read 0. Table 15.3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 15.3 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 Group 1 A/D Data Register AN 0 AN 4 ADDRA AN 1 AN 5 ADDRB AN 2 AN 6 ADDRC AN 3 AN 7 ADDRD 339 15.2.2 A/D Control/Status Register (ADCSR) Bit 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written, to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7: ADF Description 0 Clearing condition: Cleared by reading ADF while ADF = 1, then writing 0 in ADF 1 Setting conditions: 1. Single mode: A/D conversion ends 2. Scan mode: A/D conversion ends in all selected channels (Initial value) Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6: ADIE Description 0 A/D end interrupt request (ADI) is disabled 1 A/D end interrupt request (ADI) is enabled (Initial value) Bit 5--A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. Bit 5: ADST Description 0 A/D conversion is stopped 1 1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends 2. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode 340 (Initial value) Bit 4--Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 15.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4: SCAN Description 0 Single mode 1 Scan mode (Initial value) Bit 3--Clock Select (CKS): Selects the A/D conversion time. When oP = o/2, the conversion time doubles. Clear the ADST bit to 0 before switching the conversion time. Bit 3: CKS Description 0 Conversion time = 266 states (maximum) (when oP = o) 1 Conversion time = 134 states (maximum) (when oP = o) (Initial value) Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Group Selection Channel Selection Description CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN 0 (initial value) AN 0 1 AN 1 AN 0, AN 1 0 AN 2 AN 0 to AN2 1 AN 3 AN 0 to AN3 0 AN 4 AN 4 1 AN 5 AN 4, AN 5 0 AN 6 AN 4 to AN6 1 AN 7 AN 4 to AN7 1 1 0 1 341 15.2.3 A/D Control Register (ADCR) Bit 7 6 5 4 3 2 1 0 TRGE -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7--Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion. Bit 7: TRGE Description 0 A/D conversion cannot be externally triggered 1 Enables start of A/D conversion by the external trigger input (ADTRG). (A/D conversion can be started either by an external trigger or by software.) (Initial value) Bits 6 to 0--Reserved: These bits cannot be modified, and are always read as 1. 15.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15.2 shows the data flow for access to an A/D data register. 342 Upper-byte read Module data bus CPU (H'AA) Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower-byte read CPU (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 15.2 A/D Data Register Access Operation (Reading H'AA40) 343 15.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. When the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 in the ADF flag. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. 344 Figure 15.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 345 Note: * Vertical arrows ( ) indicate instructions executed by software. ADDRD ADDRC ADDRB A/D conversion result (2) A/D conversion result (1) Idle Clear * Read conversion result A/D conversion (2) Set * Read conversion result Idle State of channel 3 (AN 3) ADDRA Idle State of channel 2 (AN 2) Idle Clear * State of channel 1 (AN 1) A/D conversion (1) Set * Idle Idle A/D conversion starts State of channel 0 (AN 0) ADF ADST ADIE Set * 15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 15.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN 1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 346 Figure 15.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 347 Idle Idle Idle A/D conversion (1) Transfer Idle A/D conversion (3) Idle Idle Clear*1 Idle A/D conversion result (3) A/D conversion result (2) A/D conversion result (4) Idle A/D conversion (5) *2 A/D conversion time A/D conversion (4) A/D conversion result (1) A/D conversion (2) Idle Notes: *1 Vertical arrows ( ) indicate instructions executed by software. *2 Data currently being converted is ignored. ADDRD ADDRC ADDRB ADDRA State of channel 3 (AN 3) State of channel 2 (AN 2) State of channel 1 (AN 1) State of channel 0 (AN 0) ADF ADST Set *1 Continuous A/D conversion Clear* 1 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15.5 shows the A/D conversion timing. Table 15.4 indicates the A/D conversion time. As indicated in figure 15.5, the A/D conversion time includes t D and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15.4. In scan mode, the values given in table 15.4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1 (when oP = o). (1) o Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1): ADCSR write cycle (2): ADCSR address tD : Synchronization delay t SPL : Input sampling time t CONV : A/D conversion time Figure 15.5 A/D Conversion Timing 348 Table 15.4 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Symbol Min Typ Max Min Typ Max Synchronization delay tD 10 -- 17 6 -- 9 Input sampling time* t SPL -- 80 -- -- 40 -- A/D conversion time* t CONV 259 -- 266 131 -- 134 Note: Values in the table are numbers of states. * Values for when o P = o. When oP = o/2, values are double those given in the table. 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 15.6 shows the timing. o ADTRG Internal trigger signal ADST A/D conversion Figure 15.6 External Trigger Input Timing 349 15.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 15.6 Application Notes When using the A/D converter, note the following points. Setting Ranges of Analog Power Supply and Other Pins: 1. Analog Input Voltage Range During A/D conversion, the voltages input to the analog input pins ANn should be in the range AVSS ANn AVref . (n = 0 to 7) 2. AVCC and AVSS Input Voltages AVSS should be equal to VSS. If the A/D converter is not used, the values should be AVCC = VCC and AVSS = VSS 3. AVref Input Range The analog reference voltage input at the AVref pin should be in the range AVref AVCC. If the A/D converter is not used, the value should be AVref = VCC. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS ). The analog ground (AVSS ) should be connected to a stable digital ground (VSS) at one point on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) or analog reference power supply pin (AVref) should be connected between AVCC and AVSS as shown in figure 15.7. Also, the bypass capacitors connected to AVCC, AVref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. If a filter capacitor is connected as shown in figure 15.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance 350 (Rin ), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC AVref 100 Rin* 2 *1 AN0 to AN7 *1 0.1 F Notes: AVSS Figures are reference values. *1 10 F 0.01 F *2 Rin: Input impedance Figure 15.7 Example of Analog Input Protection Circuit A/D Conversion Precision Definitions: The H8/3437 Series A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15.9). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 15.9). 351 * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15.8). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Digital output H'3FF Ideal A/D conversion characteristic H'3FE H'3FD H'004 H'003 H'002 Quantization error H'001 H'000 2 1 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 15.8 A/D Conversion Precision Definitions (1) 352 Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 15.9 A/D Conversion Precision Definitions (2) 353 Permissible Signal Source Impedance: H8S/2148 Series and H8S/2144 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sampleand-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. But since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/sec or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS . Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8/3437 Series chip Sensor output impedance, up to 10 k A/D converter equivalent circuit 10 k Sensor input Low-pass filter C, up to 0.1 F Cin = 15 pF Note: Figures are reference values. Figure 15.10 Example of Analog Input Circuit 354 20 pF Section 16 D/A Converter 16.1 Overview The H8/3437 Series has an on-chip D/A converter module with two channels. 16.1.1 Features Features of the D/A converter module are listed below. * * * * Eight-bit resolution Two-channel output Maximum conversion time: 10 s (with 20-pF load capacitance) Output voltage: 0 V to AVref 355 16.1.2 Block Diagram Module data bus AVref DACR 8-bit D/A DADR1 DA0 DADR0 AVCC DA1 AVSS Control circuit DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 16.1 D/A Converter Block Diagram 356 Bus interface Figure 16.1 shows a block diagram of the D/A converter. Internal data bus 16.1.3 Input and Output Pins Table 16.1 lists the input and output pins used by the D/A converter module. Table 16.1 Input and Output Pins of D/A Converter Module Name Abbreviation I/O Function Reference voltage pin AVref Input Reference voltage for analog circuits Analog supply voltage AVCC Input Power supply for analog circuits Analog ground AVSS Input Ground and reference voltage for analog circuits Analog output 0 DA 0 Output Analog output channel 0 Analog output 1 DA 1 Output Analog output channel 1 16.1.4 Register Configuration Table 16.2 lists the three registers of the D/A converter module. Table 16.2 D/A Converter Registers Name Abbreviation R/W Initial Value Address D/A data register 0 DADR0 R/W H'00 H'FFF8 D/A data register 1 DADR1 R/W H'00 H'FFF9 D/A control register DACR R/W H'1F H'FFFA 357 16.2 Register Descriptions 16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W D/A data registers 0 and 1 (DADR0 and DADR1) are 8-bit readable and writable registers that store data to be converted. When analog output is enabled, the value in the D/A data register is converted and output continuously at the analog output pin. The D/A data registers are initialized to H'00 by a reset and in the standby modes. 16.2.2 D/A Control Register (DACR) Bit 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE -- -- -- -- -- Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W -- -- -- -- -- DACR is an 8-bit readable and writable register that controls the operation of the D/A converter module. DACR is initialized to H'1F by a reset and in the standby modes. Bit 7--D/A Output Enable 1 (DAOE1): Controls analog output from the D/A converter. Bit 7: DAOE1 Description 0 Analog output at DA 1 is disabled. 1 D/A conversion is enabled on channel 1. Analog output is enabled at DA 1. 358 Bit 6--D/A Output Enable 0 (DAOE0): Controls analog output from the D/A converter. Bit 6: DAOE0 Description 0 Analog output at DA 0 is disabled. 1 D/A conversion is enabled on channel 0. Analog output is enabled at DA 0. Bit 5--D/A Enable (DAE): Controls D/A conversion, in combination with bits DAOE0 and DAOE1. D/A conversion is controlled independently on channels 0 and 1 when DAE = 0. Channels 0 and 1 are controlled together when DAE = 1. The decision to output the converted results is always controlled independently by DAOE0 and DAOE1. Bit 7: DAOE1 Bit 6: DAOE0 Bit 5: DAE D/A Conversion 0 0 -- Disabled on channels 0 and 1. 1 0 Enabled on channel 0. Disabled on channel 1. 1 0 1 Enabled on channels 0 and 1. 0 Disabled on channel 0. Enabled on channel 1. 1 1 Enabled on channels 0 and 1. -- Enabled on channels 0 and 1. When the DAE bit is set to 1, analog power supply current drain is the same as during A/D and D/A conversion, even if the DAOE0 and DAOE1 bits in DACR and the ADST bit in ADSCR are cleared to 0. Bits 4 to 0--Reserved: These bits cannot be modified and are always read as 1. 359 16.3 Operation The D/A converter module has two built-in D/A converter circuits that can operate independently. D/A conversion is performed continuously whenever enabled by the D/A control register. When a new value is written in DADR0 or DADR1, conversion of the new value begins immediately. The converted result is output by setting the DAOE0 or DAOE1 bit to 1. An example of conversion on channel 0 is given next. Figure 16.2 shows the timing. 1. Software writes the data to be converted in DADR0. 2. D/A conversion begins when the DAOE0 bit in DACR is set to 1. After a conversion delay, analog output appears at the DA0 pin. The output value is AVref x (DADR0 value)/256. This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0. 3. If a new value is written in DADR0, conversion begins immediately. Output of the converted result begins after the conversion delay time. 4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle o Address Conversion data (1) DADR0 Conversion data (2) DAOE0 Conversion result (2) Conversion result (1) DA0 High-impedance state t DCONV t DCONV tDCONV: D/A conversion time Figure 16.2 D/A Conversion (Example) 360 Section 17 RAM 17.1 Overview The H8/3437 and H8/3436 have 2 kbytes of on-chip static RAM. The H8/3434 has 1 kbyte. The RAM is connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution. The on-chip RAM is assigned to addresses H'F780 to H'FF7F in the address space of the H8/3437 and H8/3436, and addresses H'FB80 to H'FF7F in the address space of the H8/3434. The RAME bit in the system control register (SYSCR) can enable or disable the on-chip RAM. 17.1.1 Block Diagram Figure 17.1 is a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'F780 H'F781 H'F782 H'F783 On-chip RAM H'FF7E Even address H'FF7F Odd address Figure 17.1 Block Diagram of On-Chip RAM (H8/3437) 361 17.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR) Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R R/W R/W R/W The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. See section 3.2, System Control Register (SYSCR), for the other SYSCR bits. Bit 0--RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is initialized to 1 on the rising edge of the RES signal. The RAME bit is not initialized in software standby mode. Bit 0: RAME Description 0 On-chip RAM is disabled. 1 On-chip RAM is enabled. 17.2 Operation 17.2.1 Expanded Modes (Modes 1 and 2) (Initial value) If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3437 and H8/3436 and addresses H'FB80 to H'FF7F in the H8/3434 are directed to the on-chip RAM. If the RAME bit is cleared to 0, accesses to these addresses are directed to the external data bus. 17.2.2 Single-Chip Mode (Mode 3) If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3437 and H8/3436 and addresses H'FB80 to H'FF7F in the H8/3434 are directed to the on-chip RAM. If the RAME bit is cleared to 0, the on-chip RAM data cannot be accessed. Attempted write access has no effect. Attempted read access always results in H'FF data being read. Notes: 1. When V CC VRAM , on-chip RAM values can be retained by using the specified method. See section 21.4.1 and Appendix E for details. 2. On-chip RAM values are not guaranteed if power is turned off, then on again, in any state. 3. When specific bits in RAM are used as control bits, initial values must be set after powering on. 362 Section 18 ROM (Mask ROM Version/ZTAT Version) 18.1 Overview The size of the on-chip ROM is 60 kbytes in the H8/3437, 48 kbytes in the H8/3436, and 32 kbytes in the H8/3434. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer. The on-chip ROM is enabled or disabled depending on the inputs at the mode pins (MD1 and MD0). See table 18.1. Table 18.1 On-Chip ROM Usage in Each MCU Mode Mode Pins Mode MD1 MD0 On-Chip ROM Mode 1 (expanded mode) 0 1 Disabled (external addresses) Mode 2 (expanded mode) 1 0 Enabled Mode 3 (single-chip mode) 1 1 Enabled The PROM versions (H8/3437 ZTAT and H8/3434 ZTAT) and flash-memory version (H8/3437 F-ZTAT and H8/3434 F-ZTAT ) can be set to writer mode and programmed with a generalpurpose PROM programmer. In the H8/3437, the accessible ROM addresses are H'0000 to H'EF7F (61,312 bytes) in mode 2, and H'0000 to H'F77F (63,360 bytes) in mode 3. For details, see section 3, MCU Operating Modes and Address Space. 363 18.1.1 Block Diagram Figure 18.1 is a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0001 H'0002 H'0003 On-chip ROM H'F77E Even address H'F77F Odd address Figure 18.1 Block Diagram of On-Chip ROM (H8/3437 Single-Chip Mode) 18.2 Writer Mode (H8/3437, H8/3434) 18.2.1 Writer Mode Setup In writer mode the PROM versions of the H8/3437 and H8/3434 suspend the usual microcomputer functions to allow the on-chip PROM to be programmed. The programming method is the same as for the HN27C101. To select writer mode, apply the signal inputs listed in table 18.2. Table 18.2 Selection of Writer Mode Pin Input Mode pin MD1 Low Mode pin MD 0 Low STBY pin Low Pins P63 and P64 High 364 18.2.2 Socket Adapter Pin Assignments and Memory Map The H8/3437 and H8/3434 can be programmed with a general-purpose PROM programmer by using a socket adapter to change the pin-out to 32 pins. See table 18.3. The same socket adapter can be used for both the H8/3437 and H8/3434. Figure 18.2 shows the socket adapter pin assignments. Table 18.3 Socket Adapter Package Socket Adapter 100-pin QFP HS3437ESHS1H 100-pin TQFP HS3437ESNS1H The PROM size is 60 kbytes for the H8/3437 and 32 kbytes for the H8/3434. Figures 18.3 and 18.4 show memory maps of the H8/3437 and H8/3434 in writer mode. H'FF data should be specified for unused address areas in the on-chip PROM. When programming with a PROM programmer, limit the program address range to H'0000 to H'F77F for the H8/3437 and H'0000 to H'7FFF for the H8/3434. Specify H'FF data for addresses H'F780 and above (H8/3437) or H'8000 and above (H8/3434). If these addresses are programmed by mistake, it may become impossible to program or verify the PROM data. The same problem may occur if an attempt is made to program the chip in page programming mode. Note that the PROM versions are one-time programmable (OTP) microcomputers, packaged in plastic packages, and cannot be reprogrammed. 365 H8/3437, H8/3434 EPROM Socket FP-100B, TFP-100B Pin Pin HN27C101 (32 pins) 1 RES V PP 1 7 NMI EA 9 26 82 P3 0 EO 0 13 83 P3 1 EO 1 14 84 P3 2 EO 2 15 85 P3 3 EO 3 17 86 P3 4 EO 4 18 87 P3 5 EO 5 19 88 P3 6 EO 6 20 89 P3 7 EO 7 21 79 P1 0 EA 0 12 78 P1 1 EA 1 11 77 P1 2 EA 2 10 76 P1 3 EA 3 9 75 P1 4 EA 4 8 74 P1 5 EA 5 7 73 P1 6 EA 6 6 72 P1 7 EA 7 5 67 P2 0 EA 8 27 66 P2 1 OE 24 65 P2 2 EA 10 23 64 P2 3 EA 11 25 63 P2 4 EA 12 4 62 P2 5 EA 13 28 61 P2 6 EA 14 29 60 P2 7 CE 22 25 P9 0 EA 16 2 24 P9 1 EA 15 3 23 P9 2 PGM 31 29 P6 3 VCC 32 32 P6 4 37 AV CC 36 AVref VSS 16 4 VCCB 9 VCC 59 VCC 6 MD0 5 MD1 8 STBY 46 AV SS 15 VSS 70 VSS 71 VSS 92 VSS Legend: VPP: EO7 to EO0: EA16 to EA0: OE: CE: PGM: Programming power supply (12.5 V) Data input/output Address input Output enable Chip enable Program enable Note: All pins not listed in this figure should be left open. Figure 18.2 Socket Adapter Pin Assignments 366 Address in MCU mode Address in writer mode H'0000 H'0000 On-chip PROM H'F77F H'F77F Undetermined value output* H'1FFFF Note: * If this address area is read in writer mode, the output data is not guaranteed. Figure 18.3 H8/3437 Memory Map in Writer Mode Address in MCU mode Address in writer mode H'0000 H'0000 On-chip PROM H'7FFF H'7FFF Undetermined value output* H'1FFFF Note: * If this address area is read in writer mode, the output data is not guaranteed. Figure 18.4 H8/3434 Memory Map in Writer Mode 367 18.3 PROM Programming The write, verify, and other sub-modes of the writer mode are selected as shown in table 18.4. Table 18.4 Selection of Sub-Modes in Writer Mode Sub-Mode CE OE PGM VPP VCC EO7 to EO0 EA 16 to EA0 Write Low High Low VPP VCC Data input Address input Verify Low Low High VPP VCC Data output Address input Programming inhibited Low Low High High Low High Low High Low High Low High VPP VCC High impedance Address input The H8/3437 and H8/3434 PROM have the same standard read/write specifications as the HN27C101 EPROM. Page programming is not supported, however, so do not select page programming mode. PROM programmers that provide only page programming cannot be used. When selecting a PROM programmer, check that it supports a byte-at-a-time high-speed programming mode. Be sure to set the address range to H'0000 to H'F77F for the H8/3437, and to H'0000 to H'7FFF for the H8/3434. 18.3.1 Programming and Verification An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure programs data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. It leaves the data H'FF in unused addresses. Figure 18.5 shows the basic high-speed programming flowchart. Tables 18.5 and 18.6 list the electrical characteristics of the chip in writer mode. Figure 18.6 shows a program/verify timing chart. 368 Start Set program/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n + 1 n Program tPW = 0.2 ms 5% No Yes n < 25? No Address + 1 address Verify OK? Yes Program tOPW = 0.2n ms Last address? No Yes Set read mode VCC = 5.0 V 0.25 V, VPP = VCC Error No go Read all addresses Go End Figure 18.5 High-Speed Programming Flowchart 369 Table 18.5 DC Characteristics (when VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Typ Max Unit Test Conditions Input high voltage EO7-EO0, EA16 -EA0, OE, CE, PGM VIH 2.4 -- VCC + 0.3 V Input low voltage EO7 - EO0, EA16 - EA0, OE, CE, PGM VIL -0.3 -- 0.8 V Output high voltage EO7-EO0 VOH 2.4 -- -- V I OH = -200 A Output low voltage EO7-EO0 VOL -- -- 0.45 V I OL = 1.6 mA Input leakage EO7 - EO0, current EA16 - EA0, OE, CE, PGM |ILI| -- -- 2 A Vin = 5.25 V/0.5 V VCC current I CC -- -- 40 mA VPP current I PP -- -- 40 mA 370 Table 18.6 AC Characteristics (when VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Item Symbol Min Typ Max Unit Test Conditions Address setup time t AS 2 -- -- s See figure 18.6* OE setup time t OES 2 -- -- s Data setup time t DS 2 -- -- s Address hold time t AH 0 -- -- s Data hold time t DH 2 -- -- s Data output disable time t DF -- -- 130 ns VPP setup time t VPS 2 -- -- s Program pulse width t PW 0.19 0.20 0.21 ms OE pulse width for overwrite-programming t OPW 0.19 -- 5.25 ms VCC setup time t VCS 2 -- -- s CE setup time t CES 2 -- -- s Data output delay time t OE 0 -- 150 ns Note: * Input pulse level: 0.8 V to 2.2 V Input rise/fall time 20 ns Timing reference levels: input--1.0 V, 2.0 V; output--0.8 V, 2.0 V 371 Write Verify Address tAH tAS Data Input data tDS VPP VCC Output data tDH tDF VPP VCC tVPS VCC + 1 VCC tVCS CE tCES PGM tPW OE tOES tOE tOPW Figure 18.6 PROM Program/Verify Timing 372 18.3.2 Notes on Programming (1) A PROM programmer that does not allow start address setting cannot be used. If such a PROM programmer is used, it will not be possible to perform verification at addresses H'10002, H'10003, H'10004, and so on. Therefore a PROM programmer that allows address setting must be used. (2) Program with the specified voltages and timing. The programming voltage (VPP) is 12.5 V. Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be particularly careful about the PROM programmer's overshoot characteristics. If the PROM programmer is set to HN27C101 specifications, VPP will be 12.5 V. (3) Before writing data, check that the socket adapter and chip are correctly mounted in the PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM programmer, socket adapter, and chip are not correctly aligned. (4) Don't touch the socket adapter or chip while writing. Touching either of these can cause contact faults and write errors. (5) Page programming is not supported. Do not select page programming mode. (6) The H8/3437 PROM size is 60 kbytes. The H8/3434 PROM size is 32 kbytes. Set the address range to H'0000 to H'F77F for the H8/3437, and to H'0000 to H'7FFF for the H8/3434. When programming, specify H'FF data for unused address areas (H'F780 to H'1FFFF in the H8/3437, H'8000 to H'1FFFF in the H8/3434). 373 18.3.3 Reliability of Programmed Data An effective way to assure the data holding characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 18.7 shows the recommended screening procedure. Write and verify program Bake with power off 125 to 150C, 24 to 48Hr Read and check program Mount Figure 18.7 Recommended Screening Procedure If a series of write errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. 374 Section 19 ROM (32-kbyte Dual-Power-Supply Flash Memory Version) 19.1 Flash Memory Overview 19.1.1 Flash Memory Operating Principle Table 19.1 illustrates the principle of operation of the H8/3434F's on-chip flash memory. Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a programmed memory cell is therefore higher than that of an erased cell. Cells are erased by grounding the gate and applying a high voltage to the source, causing the electrons stored in the floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like an EPROM cell, by driving the gate to the high level and detecting the drain current, which depends on the threshold voltage. Erasing must be done carefully, because if a memory cell is overerased, its threshold voltage may become negative, causing the cell to operate incorrectly. Section 19.4.6 shows an optimal erase control flowchart and sample program. Table 19.1 Principle of Memory Cell Operation Program Memory cell Memory array Erase Vg = VPP Vs = VPP Vd Vd Read 0V Open Vg Open Vd Open Vd 0V VPP 0V VCC 0V VPP 0V 0V 0V 0V 375 19.1.2 Mode Programming and Flash Memory Address Space As its on-chip ROM, the H8/3434F has 32 kbytes of flash memory. The flash memory is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states. The H8/3434F's flash memory is assigned to addresses H'0000 to H'7FFF. The mode pins enable either on-chip flash memory or external memory to be selected for this area. Table 19.2 summarizes the mode pin settings and usage of the memory area. Table 19.2 Mode Pin Settings and Flash Memory Area Mode Pin Setting Mode MD1 MD0 Memory Area Usage Mode 0 0 0 Illegal setting Mode 1 0 1 External memory area Mode 2 1 0 On-chip flash memory area Mode 3 1 1 On-chip flash memory area 19.1.3 Features Features of the flash memory are listed below. * Five flash memory operating modes The flash memory has five operating modes: program mode, program-verify mode, erase mode, erase-verify mode, and prewrite-verify mode. * Block erase designation Blocks to be erased in the flash memory address space can be selected by bit settings. The address space includes a large-block area (four blocks with sizes from 4 kbytes to 8 kbytes) and a small-block area (eight blocks with sizes from 128 bytes to 1 kbyte). * Program and erase time Programming one byte of flash memory typically takes 50 s. Erasing all blocks (32 kbytes) typically takes 1 s. * Erase-program cycles Flash memory contents can be erased and reprogrammed up to 100 times. * On-board programming modes These modes can be used to program, erase, and verify flash memory contents. There are two modes: boot mode and user programming mode. 376 * Automatic bit-rate alignment In boot-mode data transfer, the H8/3434F aligns its bit rate automatically to the host bit rate (maximum 9600 bps). * Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. * Writer mode As an alternative to on-board programming, the flash memory can be programmed and erased in writer mode, using a general-purpose PROM programmer. Program, erase, verify, and other specifications are the same as for HN28F101 standard flash memory. 19.1.4 Block Diagram Figure 19.1 shows a block diagram of the flash memory. 8 Internal data bus (upper) 8 Internal data bus (lower) FLMCR Bus interface and control section EBR1 H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 On-chip flash memory (32 kbytes) H'7FFC H'7FFD H'7FFE H'7FFF EBR2 Upper byte (even address) Operating mode MD1 MD0 Lower byte (odd address) Legend: FLMCR: Flash memory control register EBR1: Erase block register 1 EBR2: Erase block register 2 Figure 19.1 Flash Memory Block Diagram 377 19.1.5 Input/Output Pins Flash memory is controlled by the pins listed in table 19.3. Table 19.3 Flash Memory Pins Pin Name Abbreviation Input/Output Function Programming power FV PP Power supply Apply 12.0 V Mode 1 MD1 Input H8/3434F operating mode setting Mode 0 MD0 Input H8/3434F operating mode setting Transmit data TxD1 Output SCI1 transmit data output Receive data RxD1 Input SCI1 receive data input The transmit data and receive data pins are used in boot mode. 19.1.6 Register Configuration The flash memory is controlled by the registers listed in table 19.4. Table 19.4 Flash Memory Registers Name Abbreviation Flash memory control register Erase block register 1 FLMCR EBR1 Erase block register 2 *1 Wait-state control register R/W *2 R/W *2 R/W *2 Initial Value Address *2 H'FF80 *2 H'FF82 *2 H'00 H'F0 EBR2 R/W H'00 H'FF83 WSCR R/W H'08 H'FFC2 Notes: *1 The wait-state control register controls the insertion of wait states by the wait-state controller, frequency division of clock signals for the on-chip supporting modules by the clock pulse generator, and emulation of flash-memory updates by RAM in on-board programming mode. *2 In modes 2 and 3 (on-chip flash memory enabled), the initial value is H'00 for FLMCR and EBR2, and H'F0 for EBR1. In mode 1 (on-chip flash memory disabled), these registers cannot be modified and always read H'FF. Registers FLMCR, EBR1, and EBR2 are only valid when writing to or erasing flash memory, and can only be accessed while 12 V is being applied to the FV PP pin. When 12 V is not applied to the FVPP pin, in mode 2 addresses H'FF80 to H'FF83 are external address space, and in mode 3 these addresses cannot be modified and always read H'FF. 378 19.2 Flash Memory Register Descriptions 19.2.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register that controls the flash memory operating modes. Transitions to program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this register. FLMCR is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP. When 12 V is applied to the FVPP pin, a reset or entry to a standby mode initializes FLMCR to H'80. Bit 7 6 5 4 3 2 1 0 VPP -- -- -- EV PV E P Initial value* 0 0 0 0 0 0 0 0 Read/Write R -- -- -- R/W* R/W* R/W* R/W* Note: * The initial value is H'00 in modes 2 and 3 (on-chip flash memory enabled). In mode 1 (onchip flash memory disabled), this register cannot be modified and always reads H'FF. For information on accessing this register, refer to in section 19.7, Flash Memory Programming and Erasing Precautions (11). Bit 7--Programming Power (VPP): This status flag indicates that 12 V is applied to the FVPP pin. Refer to section 19.7, Flash Memory Programming and Erasing Precautions (5), for details on use. Bit 7: VPP Description 0 Cleared when 12 V is not applied to FVPP 1 Set when 12 V is applied to FVPP (Initial value) Bits 6 to 4--Reserved: Read-only bits, always read as 0. Bit 3--Erase-Verify Mode (EV): *1 Selects transition to or exit from erase-verify mode. Bit 3: EV Description 0 Exit from erase-verify mode 1 Transition to erase-verify mode (Initial value) Bit 2--Program-Verify Mode (PV):*1 Selects transition to or exit from program-verify mode. Bit 2: PV Description 0 Exit from program-verify mode 1 Transition to program-verify mode (Initial value) 379 Bit 1--Erase Mode (E):*1, *2 Selects transition to or exit from erase mode. Bit 1: E Description 0 Exit from erase mode 1 Transition to erase mode (Initial value) Bit 0--Program Mode (P):*1, *2 Selects transition to or exit from program mode. Bit 0: P Description 0 Exit from program mode 1 Transition to program mode (Initial value) Notes: *1 Do not set two or more of these bits simultaneously. Do not release or shut off the VCC or VPP power supply when these bits are set. *2 Set the P or E bit according to the instructions given in section 19.4, Programming and Erasing Flash Memory. Set the watchdog timer beforehand to make sure that these bits do not remain set for longer than the specified times. For notes on use, see section 19.7, Flash Memory Programming and Erasing Precautions. 19.2.2 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that designates large flash-memory blocks for programming and erasure. EBR1 is initialized to H'F0 by a reset, in the standby modes, and when 12 V is not applied to FVPP pin. When a bit in EBR1 is set to 1, the corresponding block is selected and can be programmed and erased. Figure 19.2 and table 19.6 show details of a block map. Bit 7 6 5 4 3 2 1 0 -- -- -- -- LB3 LB2 LB1 LB0 Initial value* 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W* R/W* R/W* R/W* Note: * The initial value is H'F0 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip ROM disabled), this register cannot be modified and always reads H'FF. For information on accessing this register, refer to in section 19.7, Flash Memory Programming and Erasing Precautions (11). 380 Bits 7 to 4--Reserved: These bits cannot be modified, and are always read as 1. Bits 3 to 0--Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be programmed and erased. Bits 3 to 0: LB3 to LB0 Description 0 Block (LB3 to LB0) is not selected 1 Block (LB3 to LB0) is selected 19.2.3 (Initial value) Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that designates small flash-memory blocks for programming and erasure. EBR2 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP pin. When a bit in EBR2 is set to 1, the corresponding block is selected and can be programmed and erased. Figure 19.2 and table 19.6 show a block map. Bit 7 6 5 4 3 2 1 0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Initial value* 0 0 0 0 0 0 0 0 Read/Write R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * The initial value is H'00 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip ROM disabled), this register cannot be modified and always reads H'FF. For information on accessing this register, refer to in section 19.7, Flash Memory Programming and Erasing Precautions (11). Bits 7 to 0--Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be programmed and erased. Bits 7 to 0: SB7 to SB0 Description 0 Block (SB7 to SB0) is not selected 1 Block (SB7 to SB0) is selected (Initial value) 381 19.2.4 Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that enables flash-memory updates to be emulated in RAM. It also controls frequency division of clock signals supplied to the on-chip supporting modules and insertion of wait states by the wait-state controller. WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7 6 5 4 3 2 1 0 RAMS RAM0 CKDBL -- WMS1 WMS0 WC1 WC0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6--RAM Select and RAM0 (RAMS and RAM0): These bits are used to reassign an area to RAM (see table 19.5). These bits are write-enabled and their initial value is 0. They are initialized by a reset and in hardware standby mode. They are not initialized in software standby mode. If only one of bits 7 and 6 is set, part of the RAM area can be overlapped onto the small-block flash memory area. In that case, access is to RAM, not flash memory, and all flash memory blocks are write/erase-protected (emulation protect*1). In this state, the mode cannot be changed to program or erase mode, even if the P bit or E bit in the flash memory control register (FLMCR) is set (although verify mode can be selected). Therefore, clear both of bits 7 and 6 before programming or erasing the flash memory area. If both of bits 7 and 6 are set, part of the RAM area can be overlapped onto the small-block flash memory area, but this overlapping begins only when an interrupt signal is input while 12 V is being applied to the FVPP pin. Up until that point, flash memory is accessed. Use this setting for interrupt handling while flash memory is being programmed or erased.*2 Table 19.5 RAM Area Reassignment*3 Bit 7: RAMS Bit 6: RAM0 RAM Area ROM Area 0 0 None -- 1 H'FC80 to H'FCFF H'0080 to H'00FF 0 H'FC80 to H'FD7F H'0080 to H'017F 1 H'FC00 to H'FC7F H'0000 to H'007F 1 382 Bit 5--Clock Double (CKDBL): Controls frequency division of clock signals supplied to the onchip supporting modules. For details, see section 6, Clock Pulse Generator. Bit 4--Reserved: This bit is reserved, but it can be written and read. Its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1, WMS0) Bits 1 and 0--Wait Count 1 and 0 (WC1, WC0) These bits control insertion of wait states by the wait-state controller. For details, see section 5, Wait-State Controller. Notes: *1 For details on emulation protect, see section 19.4.8, Protect Modes. *2 For details on interrupt handling during programming and erasing of flash memory, see section 19.4.9, Interrupt Handling during Flash Memory Programming and Erasing. *3 RAM area that overlaps flash memory. 383 Small block area (4 kbytes) Large block area (28 kbytes) H'0000 H'0000 SB7 to SB0 4 kbytes H'0FFF H'1000 SB0 128 bytes SB1 128 bytes SB2 128 bytes H'01FF SB3 128 bytes H'0200 SB4 512 bytes LB0 4 kbytes H'03FF H'0400 H'1FFF H'2000 LB1 8 kbytes SB5 1 kbyte H'07FF H'0800 H'3FFF H'4000 LB2 8 kbytes SB6 1 kbyte H'0BFF H'0C00 H'5FFF H'6000 SB7 1 kbyte LB3 8 kbytes H'7FFF Figure 19.2 Erase Block Map 384 H'0FFF Table 19.6 Erase Blocks and Corresponding Bits Register Bit Block Address Size EBR1 0 LB0 H'1000 to H'1FFF 4 kbytes 1 LB1 H'2000 to H'3FFF 8 kbytes 2 LB2 H'4000 to H'5FFF 8 kbytes 3 LB3 H'6000 to H'7FFF 8 kbytes 0 SB0 H'0000 to H'007F 128 bytes 1 SB1 H'0080 to H'00FF 128 bytes 2 SB2 H'0100 to H'017F 128 bytes 3 SB3 H'0180 to H'01FF 128 bytes 4 SB4 H'0200 to H'03FF 512 bytes 5 SB5 H'0400 to H'07FF 1 kbyte 6 SB6 H'0800 to H'0BFF 1 kbyte 7 SB7 H'0C00 to H'0FFF 1 kbyte EBR2 19.3 On-Board Programming Modes When an on-board programming mode is selected, the on-chip flash memory can be programmed, erased, and verified. There are two on-board programming modes: boot mode, and user programming mode. These modes are selected by inputs at the mode pins (MD1 and MD 0) and FVPP pin. Table 19.7 indicates how to select the on-board programming modes. For details on applying voltage V PP , refer to section 19.7, Flash Memory Programming and Erasing Precautions (5). Table 19.7 On-Board Programming Mode Selection Mode Selections Boot mode User programming mode FV PP MD1 MD0 Notes 12 V* 12 V* 0 0: VIL Mode 3 12 V* 1 1: VIH Mode 2 1 0 Mode 3 1 1 Mode 2 Note: * For details on the timing of 12 V application, see notes 6 to 8 in the Notes on Use of Boot Mode at the end of this section. In boot mode, the mode control register (MDCR) can be used to monitor the mode (mode 2 or 3) in the same way as in normal mode. Example: Set the mode pins for mode 2 boot mode (MD 1 = 12 V, MD0 = 0 V). If the mode select bits of MDCR are now read, they will indicate mode 2 (MDS1 = 1, MDS0 = 0). 385 19.3.1 Boot Mode To use boot mode, a user program for programming and erasing the flash memory must be provided in advance on the host machine (which may be a personal computer). Serial communication interface channel 1 is used in asynchronous mode. If the H8/3434F is placed in boot mode, after it comes out of reset, a built-in boot program is activated. This program starts by measuring the low period of data transmitted from the host and setting the bit rate register (BRR) accordingly. The H8/3434F's built-in serial communication interface (SCI) can then be used to download the user program from the host machine. The user program is stored in on-chip RAM. After the program has been stored, execution branches to address H'FBE0 in the on-chip RAM, and the program stored on RAM is executed to program and erase the flash memory. H8/3434F Receive data to be programmed HOST Transmit verification data RxD1 SCI TxD1 Figure 19.3 Boot-Mode System Configuration 386 Boot-Mode Execution Procedure: Figure 19.4 shows the boot-mode execution procedure. Start 1. Program the H8/3434F pins for boot mode, and start the H8/3434F from a reset. 1 Program H8/3434F pins for boot mode, and reset 2. Set the host's data format to 8 bits + 1 stop bit, select the desired bit rate (2400, 4800, or 9600 bps), and transmit H'00 data continuously. 2 Host transmits H'00 data continuously at desired bit rate 3 H8/3434F measures low period of H'00 data transmitted from host H8/3434F computes bit rate and sets bit rate register 4 After completing bit-rate alignment, H8/3434F sends one H'00 data byte to host to indicate that alignment is completed 5 Host checks that this byte, indicating completion of bit-rate alignment, is received normally, then transmits one H'55 byte 6 After receiving H'55, H8/3434F sends part of the boot program to RAM H8/3434F branches to the RAM boot area (H'FC00 to H'FF2F), then checks the data in the user area of flash memory 7 No All data = H'FF? Yes Erase all flash memory blocks*3 After checking that all data in flash memory is H'FF, H8/3434F transmits one H'AA data byte to host 8 H8/3434F receives two bytes indicating byte length (N) of program to be downloaded to on-chip RAM*1 H8/3434F transfers one user program byte to RAM*2 9 H8/3434F calculates number of bytes left to be transferred (N = N - 1) All bytes transferred? (N = 0?) No Yes After transferring the user program to RAM, H8/3434F transmits one H'AA data byte to host 10 H8/3434F branches to H'FBE0 in RAM area and executes user program downloaded into RAM 3. The H8/3434F repeatedly measures the low period of the RxD1 pin and calculates the host's asynchronouscommunication bit rate. 4. When SCI bit-rate alignment is completed, the H8/3434F transmits one H'00 data byte to indicate completion of alignment. 5. The host should receive the byte transmitted from the H8/3434F to indicate that bit-rate alignment is completed, check that this byte is received normally, then transmit one H'55 byte. 6. After receiving H'55, H8/3434F sends part of the boot program to H'FB80 to H'FBDF and H'FC00 to H'FF2F of RAM. 7. After branching to the boot program area (H'FC00 to H'FF2F) in RAM, the H8/3434F checks whether the flash memory already contains any programmed data. If so, all blocks are erased. 8. After the H8/3434F transmits one H'AA data byte, the host transmits the byte length of the user program to be transferred to the H8/3434F. The byte length must be sent as two-byte data, upper byte first and lower byte second. After that, the host proceeds to transmit the user program. As verification, the H8/3434F echoes each byte of the received byte-length data and user program back to the host. 9. The H8/3434F stores the received user program in on-chip RAM in a 910-byte area from H'FBE0 to H'FF6D. 10. After transmitting one H'AA data byte, the H8/3434F branches to address H'FBE0 in on-chip RAM and executes the user program stored in the area from H'FBE0 to H'FF6D. Notes: *1 The user can use 910 bytes of RAM. The number of bytes transferred must not exceed 910 bytes. Be sure to transmit the byte length in two bytes, upper byte first and lower byte second. For example, if the byte length of the program to be transferred is 256 bytes (H'0100), transmit H'01 as the upper byte, followed by H'00 as the lower byte. *2 The part of the user program that controls the flash memory should be coded according to the flash memory program/erase algorithms given later. *3 If a memory cell malfunctions and cannot be erased, the H8/3434F transmits one H'FF byte to report an erase error, halts erasing, and halts further operations. Figure 19.4 Boot Mode Flowchart 387 Automatic Alignment of SCI Bit Rate Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit This low period (9 bits) is measured (H'00 data) High for at least 1 bit Figure 19.5 Measurement of Low Period in Data Transmitted from Host When started in boot mode, the H8/3434F measures the low period in asynchronous SCI data transmitted from the host (figure 19.5). The data format is eight data bits, one stop bit, and no parity bit. From the measured low period (9 bits), the H8/3434F computes the host's bit rate. After aligning its own bit rate, the H8/3434F sends the host 1 byte of H'00 data to indicate that bit-rate alignment is completed. The host should check that this alignment-completed indication is received normally and send one byte of H'55 back to the H8/3434F. If the alignment-completed indication is not received normally, the H8/3434F should be reset, then restarted in boot mode to measure the low period again. There may be some alignment error between the host's and H8/3434F's bit rates, depending on the host's bit rate and the H8/3434F's system clock frequency. To have the SCI operate normally, set the host's bit rate to 2400, 4800, or 9600 bps *1. Table 19.8 lists typical host bit rates and indicates the clock-frequency ranges over which the H8/3434F can align its bit rate automatically. Boot mode should be used within these frequency ranges*2. Table 19.8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by H8/3434F Host Bit Rate*1 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by H8/3434F 9600 bps 8 MHz to 16 MHz 4800 bps 4 MHz to 16 MHz 2400 bps 2 MHz to 16 MHz Notes: *1 Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be used. *2 Although the H8/3434F may also perform automatic bit-rate alignment with bit rate and system clock combinations other than those shown in table 19.8, there will be a slight difference between the bit rates of the host and the H8/3434F, and subsequent transfer will not be performed normally. Therefore, only a combination of bit rate and system clock frequency within one of the ranges shown in table 19.8 can be used for boot mode execution. 388 RAM Area Allocation in Boot Mode: In boot mode, the 96 bytes from H'FB80 to H'FBDF and the 18 bytes from H'FF6E to H'FF7F are reserved for use by the boot program, as shown in figure 19.6. The user program is transferred into the area from H'FBE0 to H'FF6D (910 bytes). The boot program area can be used after the transition to execution of the user program transferred into RAM. If a stack area is needed, set it within the user program. H'FB80 Boot program area* (96 bytes) H'FBE0 User program transfer area (910 bytes) H'FF6E H'FF7F Boot program area* (18 bytes) Note: * This area cannot be used until the H8/3434F starts to execute the user program transferred to RAM (until it has branched to H'FBE0 in RAM). Note that even after the branch to the user program, the boot program area (H'FB80 to H'FBDF, H'FF6E to H'FF7F) still contains the boot program. Note also that 16 bytes (H'FB80 to H'FB8F) of this area cannot be used if an interrupt handling routine is executed within the boot program. For details see section 19.4.9, Interrupt Handling during Flash Memory Programming and Erasing. Figure 19.6 RAM Areas in Boot Mode 389 Notes on Use of Boot Mode 1. When the H8/3434F comes out of reset in boot mode, it measures the low period of the input at the SCI's RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100 states for the H8/3434F to get ready to measure the low period of the RxD 1 input. 2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF), all flash memory blocks are erased. Boot mode is for use when user programming mode is unavailable, e.g. the first time on-board programming is performed, or if the update program activated in user programming mode is accidentally erased. 3. Interrupts cannot be used while the flash memory is being programmed or erased. 4. The RxD1 and TxD1 pins should be pulled up on-board. 5. Before branching to the user program (at address H'FBE0 in the RAM area), the H8/3434F terminates transmit and receive operations by the on-chip SCI (by clearing the RE and TE bits of the serial control register to 0 in channel 1), but the auto-aligned bit rate remains set in bit rate register BRR. The transmit data output pin (TxD1) is in the high output state (in port 8, the bits P8 4 DDR of the port 8 data direction register and P84 DR of the port 8 data register are set to 1). At this time, the values of general registers in the CPU are undetermined. Thus these registers should be initialized immediately after branching to the user program. Especially in the case of the stack pointer, which is used implicitly in subroutine calls, the stack area used by the user program should be specified. There are no other changes to the initialized values of other registers. 6. Boot mode can be entered by starting from a reset after 12 V is applied to the MD1 and FVPP pins according to the mode setting conditions listed in table 19.7. Note the following points when turning the VPP power on. When reset is released (at the rise from low to high), the H8/3434F checks for 12-V input at the MD1 and FVPP pins. If it detects that these pins are programmed for boot mode, it saves that status internally. The threshold point of this voltage-level check is in the range from approximately VCC + 2 V to 11.4 V, so boot mode will be entered even if the applied voltage is insufficient for programming or erasure (11.4 V to 12.6 V). When the boot program is executed, the VPP power supply must therefore be stabilized within the range of 11.4 V to 12.6 V before the branch to the RAM area occurs. See figure 19.20. Make sure that the programming voltage VPP does not exceed 12.6 V during the transition to boot mode (at the reset release timing) and does not go outside the range of 12 V 0.6 V while in boot mode. Boot mode will not be executed correctly if these limits are exceeded. In 390 addition, make sure that VPP is not released or shut off while the boot program is executing or the flash memory is being programmed or erased.*1 Boot mode can be released by driving the reset pin low, waiting at least ten system clock cycles, then releasing the application of 12 V to the MD1 and FVPP pins and releasing the reset. The settings of external pins must not change during operation in boot mode. During boot mode, if input of 12 V to the MD1 pin stops but no reset input occurs at the RES pin, the boot mode state is maintained within the chip and boot mode continues (but do not stop applying 12 V to the FV PP pin during boot mode*1). If a watchdog timer reset occurs during boot mode, this does not release the internal mode state, but the internal boot program is restarted. Therefore, to change from boot mode to another mode, the boot-mode state within the chip must be released by a reset input at the RES pin before the mode transition can take place. 7. If the input level of the MD 1 pin is changed during a reset (e.g., from 0 V to 5 V then to 12 V while the input to the RES pin is low), the resultant switch in the microcontroller's operating mode will affect the bus control output signals (AS, RD, and WR) and the status of ports that can be used for address output*2. Therefore, either set these pins so that they do not output signals during the reset, or make sure that their output signals do not collide with other signals outside the microcontroller. 8. When applying 12 V to the MD1 and FVPP pins, make sure that peak overshoot does not exceed the rated limit of 13 V. Also, be sure to connect a decoupling capacitor to the FV PP and MD 1 pins. Notes: *1 For details on applying, releasing, and shutting off V PP , see note (5) in section 19.7, Flash Memory Programming and Erasing Precautions. *2 These ports output low-level address signals if the mode pins are set to mode 1 during the reset. In all other modes, these ports are in the high-impedance state. The bus control output signals are high if the mode pins are set for mode 1 or 2 during the reset. In mode 3, they are at high impedance. 391 19.3.2 User Programming Mode When set to user programming mode, the H8/3434F can erase and program its flash memory by executing a user program. On-board updates of the on-chip flash memory can be carried out by providing on-board circuits for supplying VPP and data, and storing an update program in part of the program area. To select user programming mode, select a mode that enables the on-chip ROM (mode 2 or 3) and apply 12 V to the FVPP pin, either during a reset, or after the reset has ended (been released) but while flash memory is not being accessed. In user programming mode, the on-chip supporting modules operate as they normally would in mode 2 or 3, except for the flash memory. However, hardware standby mode cannot be set while 12 V is applied to the FV PP pin. The flash memory cannot be read while it is being programmed or erased, so the update program must either be stored in external memory, or transferred temporarily to the RAM area and executed in RAM. 392 User Programming Mode Execution Procedure (Example)*: Figure 19.7 shows the execution procedure for user programming mode when the on-board update routine is executed in RAM. Note: * Do not apply 12 V to the FVPP pin during normal operation. To prevent flash memory from being accidentally programmed or erased due to program runaway etc., apply 12 V to FVPP only when programming or erasing flash memory. Overprogramming or overerasing due to program runaway can cause memory cells to malfunction. While 12 V is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing. For details on applying, releasing, and shutting off VPP, see section 19.7, Flash Memory Programming and Erasing Precautions (5). 1 Set MD1 and MD0 to 10 or 11 (apply VIH to VCC to MD1) Start from reset 2 Branch to flash memory on-board update program 3 Transfer on-board update routine into RAM 4 Branch to flash memory on-board update routine in RAM 5 FVPP = 12 V (user programming mode) 6 Execute flash memory on-board update routine in RAM (update flash memory) 7 Release FVPP (exit user programming mode) 8 Branch to application program in flash memory* Procedure The flash memory on-board update program is written in flash memory ahead of time by the user. 1. Set MD1 and MD0 of the H8/3434F to 10 or 11, and start from a reset. 2. Branch to the flash memory on-board update program in flash memory. 3. Transfer the on-board update routine into RAM. 4. Branch to the on-board update routine that was transferred into RAM. 5. Apply 12 V to the FVPP pin, to enter user programming mode. 6. Execute the flash memory on-board update routine in RAM, to perform an on-board update of the flash memory. 7. Change the voltage at the FVPP pin from 12 V to VCC, to exit user programming mode. 8. After the on-board update of flash memory ends, execution branches to an application program in flash memory. Note: * After the update is finished, when input of 12 V to the FVPP pin is released, the flash memory read setup time (tFRS) must elapse before any program in flash memory is executed. This is the required setup time from when the FVPP pin reaches the (VCC + 2 V) level after 12 V is released until flash memory can be read. Figure 19.7 User Programming Mode Operation (Example) 393 19.4 Programming and Erasing Flash Memory The H8/3434F's on-chip flash memory is programmed and erased by software, using the CPU. The flash memory can operate in program mode, erase mode, program-verify mode, erase-verify mode, or prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV, and EV bits in the flash memory control register (FLMCR). The flash memory cannot be read while being programmed or erased. The program that controls the programming and erasing of the flash memory must be stored and executed in on-chip RAM or in external memory. A description of each mode is given below, with recommended flowcharts and sample programs for programming and erasing. For details on programming and erasing, refer to section 19.7, Flash Memory Programming and Erasing Precautions. 19.4.1 Program Mode To write data into the flash memory, follow the programming algorithm shown in figure 19.8. This programming algorithm can write data without subjecting the device to voltage stress or impairing the reliability of programmed data. To program data, first specify the area to be written in flash memory with erase block registers EBR1 and EBR2, then write the data to the address to be programmed, as in writing to RAM. The flash memory latches the address and data in an address latch and data latch. Next set the P bit in FLMCR, selecting program mode. The programming duration is the time during which the P bit is set. A software timer should be used to provide a programming duration of about 10 to 20 s. The value of N, the number of attempts, should be set so that the total programming time does not exceed 1 ms. Programming for too long a time, due to program runaway for example, can cause device damage. Before selecting program mode, set up the watchdog timer so as to prevent overprogramming. 394 19.4.2 Program-Verify Mode In program-verify mode, after data has been programmed in program mode, the data is read to check that it has been programmed correctly. After the programming time has elapsed, exit programming mode (clear the P bit to 0) and select program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is applied to the memory cells at the latched address. If the flash memory is read in this state, the data at the latched address will be read. After selecting program-verify mode, wait 4 s or more before reading, then compare the programmed data with the verify data. If they agree, exit program-verify mode and program the next address. If they do not agree, select program mode again and repeat the same program and program-verify sequence. Do not repeat the program and program-verify sequence more than 50 times* for the same bit. Note: * Keep the total programming time under 1 ms for each bit. 395 19.4.3 Programming Flowchart and Sample Program Flowchart for Programming One Byte Start Set erase block register (set bit of block to be programmed to 1) Write data to flash memory (flash memory latches write address and data)*1 n=1 Enable watchdog timer*2 Select program mode (P bit = 1 in FLMCR) Notes: *1 Write the data to be programmed with a byte transfer instruction. *2 Set the timer overflow interval to the shortest value (CKS2, CKS1, CKS0 all cleared to 0). *3 Read the memory data to be verified with a byte transfer instruction. *4 x: 10 to 20 s tVS1: 4 s or more N: 50 (set N so that total programming time does not exceed 1 ms) Wait (x) s*4 Clear P bit End of programming Disable watchdog timer Select program-verify mode (PV bit = 1 in FLMCR) Wait (tVS1) s*4 No go Verify*3 (read memory) OK Clear PV bit Clear PV bit End of verification Clear erase block register (clear bit of programmed block to 0) End (1-byte data programmed) n N?*4 No Yes Programming error Figure 19.8 Programming Flowchart 396 n+1n Sample Program for Programming One Byte: This program uses the following registers. R0H: R1H: R1L: R3: R4: Specifies blocks to be erased. Stores data to be programmed. Stores data to be read. Stores address to be programmed. Valid addresses are H'0000 to H'7FFF. Sets program and program-verify timing loop counters, and also stores register setting value. R5: Sets program timing loop counter. R6L: Used for program-verify fail count. Arbitrary data can be programmed at an arbitrary address by setting the address in R3 and the data in R1H. The setting of #a and #b values depends on the clock frequency. Set #a and #b values according to tables 19.9 (1) and (2). FLMCR: EBR1: EBR2: TCSR: .EQU .EQU .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFA8 PRGM: .ALIGN MOV.B MOV.B 2 #H'**, R0H, MOV.B MOV.W MOV.B INC MOV.W MOV.W MOV.W BSET SUBS MOV.W BNE BCLR MOV.W MOV.W #H'00, #H'a, R1H, R6L #H'A578, R4, R5, #0, #1, R4, LOOP1 #0, #H'A500, R4, R6L R5 @R3 MOV.B BSET DEC BNE MOV.B CMP.B BEQ BCLR #H'b , #2, R4H LOOP2 @R3, R1H, PVOK #2, R4H ; Set program-verify loop counter @FLMCR:8 ; Set PV bit PRGMS: LOOP1: LOOP2: R0H ; @EBR*:8 ; Set EBR * ; ; ; ; ; ; ; Program-verify fail counter Set program loop counter Dummy write Program-verify fail counter + 1 R6L R4 @TCSR Start watchdog timer R4 Set program loop counter @FLMCR:8 ; Set P bit R4 ; R4 ; ; Wait loop @FLMCR:8 ; Clear P bit R4 ; @TCSR ; Stop watchdog timer ; ; ; ; ; Wait loop Read programmed address Compare programmed data with read data Program-verify decision @FLMCR:8 ; Clear PV bit R1L R1L 397 PVOK: CMP.B BEQ BRA #H'32, NGEND PRGMS BCLR MOV.B MOV.B #2, #H'00, R6L, R6L ; Program-verify executed 50 times? ; If program-verify executed 50 times, branch to NGEND ; Program again @FLMCR:8 ; Clear PV bit R6L ; @EBR*:8 ; Clear EBR* One byte programmed NGEND: 19.4.4 Programming error Erase Mode To erase the flash memory, follow the erasing flowchart shown in figure 19.9. This erasing flow can erase data without subjecting the device to voltage stress or impairing the reliability of programmed data. To erase flash memory, before starting to erase, first place all memory data in all blocks to be erased in the programmed state (program all memory data to H'00). If all memory data is not in the programmed state, follow the sequence described later (figure 19.10) to program the memory data to zero. Select the flash memory areas to be erased with erase block registers 1 and 2 (EBR1 and EBR2). Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during which the E bit is set. To prevent overerasing, use a software timer to divide the erase time into repeated 10 ms intervals, and perform erase operations a maximum of 3000 times so that the total erase time does not exceed 30 seconds. Overerasing, due to program runaway for example, can give memory cells a negative threshold voltage and cause them to operate incorrectly. Before selecting erase mode, set up the watchdog timer so as to prevent overerasing. 19.4.5 Erase-Verify Mode In erase-verify mode, after data has been erased, it is read to check that it has been erased correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0) and select eraseverify mode (set the EV bit to 1). Before reading data in erase-verify mode, write H'FF dummy data to the address to be read. This dummy write applies an erase-verify voltage to the memory cells at the latched address. If the flash memory is read in this state, the data at the latched address will be read. After the dummy write, wait 2 s or more before reading. When performing the initial dummy write, wait 4 s or more after selecting erase-verify mode. If the read data has been successfully erased, perform an erase-verify (dummy write, wait 2 s or more, then read) for the next address. If the read data has not been erased, select erase mode again and repeat the same erase and erase-verify sequence through the last address, until all memory data has been erased to 1. Do not repeat the erase and erase-verify sequence more than 3000 times, however. 398 19.4.6 Erasing Flowchart and Sample Program Flowchart for Erasing One Block Start Set erase block register (set bit of block to be erased to 1) Write 0 data in all addresses to be erased (prewrite)*1 n=1 Enable watchdog timer*2 Select erase mode (E bit = 1 in FLMCR) Wait (x) ms*5 Clear E bit Disable watchdog timer Set top address in block as verify address Select erase-verify mode (EV bit = 1 in FLMCR) Wait (tVS1) s*5 Notes: *1 Program all addresses to be erased by following the prewrite flowchart. *2 Set the watchdog timer overflow interval to the value indicated in table 19.10. *3 For the erase-verify dummy write, Erasing ends write H'FF with a byte transfer instruction. *4 Read the data to be verified with a byte transfer instruction. When erasing two or more blocks, clear the bits of erased blocks in the erase block registers, so that only unerased blocks will be erased again. *5 x: 10 ms tVS1: 4 s or more tVS2: 2 s or more N: 3000 Dummy write to verify address*3 (flash memory latches address) Wait (tVS2) s*5 Verify*4 (read data H'FF?) OK No Address + 1 address No go Clear EV bit Last address? Yes n N?*5 Clear EV bit Yes Erase-verify ends No n+1n Clear erase block register (clear bit of erased block to 0) End of block erase Erase error Figure 19.9 Erasing Flowchart 399 Prewrite Flowchart Start Set erase block register (set bit of block to be programmed to 1) Set start address*5 n=1 Write H'00 to flash memory (Flash memory latches write address and write data)*1 Address + 1 address Notes: *1 Use a byte transfer instruction. *2 Set the timer overflow interval to the shortest value (CKS2, CKS1, CKS0 all cleared to 0). *3 In prewrite-verify mode P, E, PV, and EV are all cleared to 0 and 12 V is applied to FVPP. Read the data with a byte transfer instruction. *4 x: 10 to 20 s End of programming tVS1: 4 s or more N: 50 (set N so that total programming time does not exceed 1 ms) *5 Start and last addresses shall be top and last addresses of the block to be erased. Enable watchdog timer*2 Select program mode ( P bit = 1 in FLMCR) Wait (x) s*4 Clear P bit Disable watchdog timer Wait (tVS1) s*4 Prewrite verify*3 (read data = H'00?) No go OK n N?*4 No Yes n+1n Programming error No Last address?*5 Yes Clear erase block register (clear bit of programmed block to 0) End of prewrite Figure 19.10 Prewrite Flowchart 400 Sample Block-Erase Program: This program uses the following registers. R0: R1H: R2: R3: R4: Specifies block to be erased, and also stores address used in prewrite and erase-verify. Stores data to be read, and also used for dummy write. Stores last address of block to be erased. Stores address used in prewrite and erase-verify. Sets timing loop counters for prewrite, prewrite-verify, erase, and erase-verify, and also stores register setting value. R5: Sets prewrite and erase timing loop counters. R6L: Used for prewrite-verify and erase-verify fail count. The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a, #b, #c, #d, and #e values according tables 19.9 (1) and (2), and 19.10. Erase block registers (EBR1 and EBR2) should be set according to sections 19.2.2 and 19.2.3. #BLKSTR and #BLKEND are the top and last addresses of the block to be erased. Set #BLKSTR and #BLKEND according to figure 19.2. 401 FLMCR: EBR1: EBR2: TCSR: .EQU .EQU .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFA8 .ALIGN MOV.B MOV.B 2 #H'**, ROH, ROH ; @EBR*:8 ; Set EBR* ; #BLKSTR is top address of block to be erased. ; #BLKEND is last address of block to be erased. #BLKSTR, #BLKEND, #1, R0 R2 R2 ; Top address of block to be erased ; Last address of block to be erased ; Last address of block to be erased + 1 R2 MOV.W MOV.B MOV.W INC MOV.B MOV.B MOV.W MOV.W MOV.W BSET SUBS MOV.W BNE BCLR MOV.W MOV.W R0, #H'00, #H'a, R6L #H'00 R1H, #H'A578, R4, R5, #0, #1, R4, LOOPR1 #0, #H'A500, R4, R3 R6L R5 ; ; ; ; ; ; ; ; ; MOV.B DEC BNE MOV.B BEQ CMP.B BEQ BRA #H'c, R4H LOOPR2 @R3, PWVFOK #H'32, ABEND1 PREWRS R4H MOV.W MOV.W ADDS ; Execute prewrite PREWRT: PREWRS: LOOPR1: LOOPR2: ABEND1: Programming error PWVFOK: ADDS CMP.W BNE 402 #1, R2, PREWRT R1H @R3 R4 @TCSR R4 @FLMCR:8 R4 ; R4 ; Top address of block to be erased Prewrite-verify fail counter Set prewrite loop counter Prewrite-verify fail counter + 1 R6L Write H'00 Start watchdog timer Set prewrite loop counter ; Set P bit ; Wait loop @FLMCR:8 ; Clear P bit R4 ; @TCSR ; Stop watchdog timer R1H R6L R3 R3 ; ; ; ; ; ; ; ; Set prewrite-verify loop counter Wait loop Read data = H'00? If read data = H'00 branch to PWVFOK Prewrite-verify executed 50 times? If prewrite-verify executed 50 times, branch to ABEND1 Prewrite again ; Address + 1 R3 ; Last address? ; If not last address, prewrite next address ;Execute erase ERASES: MOV.W MOV.W ERASE: ADDS MOV.W MOV.W MOV.W BSET LOOPE: NOP NOP NOP NOP SUBS MOV.W BNE BCLR MOV.W MOV.W #H'0000, #H'd, #1, #H'e, R4, R5, #1, R6 ; R5 ; R6 ; R4 ; @TCSR ; R4 ; @FLMCR:8 Erase-verify fail counter Set erase loop count Erase-verify fail counter + 1 R6 #1, R4, LOOPE #1, #H'A500, R4, R4 R4 MOV.W MOV.B BSET DEC BNE MOV.B MOV.B MOV.B DEC BNE MOV.B CMP.B BNE CMP.W BNE BRA R0, #H'b, #3, R4H LOOPEV #H'FF, R1H, #H'c, R4H LOOPDW @R3+, #H'FF, RERASE R2, EVR2 OKEND R3 ; Top address of block to be erased R4H ; Set erase-verify loop counter @FLMCR:8 ; Set EV bit RERASE: BCLR SUBS #3, #1, @FLMCR:8 ; Clear EV bit R3 ; Erase-verify address - 1 R3 BRER: MOV.W CMP.W BNE BRA #H'0BB8, R4, ERASE ABEND2 R4 R6 OKEND: BCLR MOV.B MOV.B #3, #H'00, R6L, @FLMCR:8 ; Clear EV bit R6L ; @EBR*:8 ; Clear EBR* Start watchdog timer Set erase loop counter ; Set E bit ; ; ; Wait loop @FLMCR:8 ; Clear E bit R4 ; @TCSR ; Stop watchdog timer ; Execute erase-verify LOOPEV: EVR2: LOOPDW: R1H @R3 R4H R1H R1H R3 ; ; ; ; ; ; ; ; ; ; ; Wait loop Dummy write Set erase-verify loop counter Wait loop Read Read data = H'FF? If read data H'FF, branch to RERASE Last address of block? ; ; Erase-verify executed 3000 times? ; If erase-verify not executed 3000 times, erase again ; If erase-verify executed 3000 times, branch to ABEND2 One block erased ABEND2: Erase error 403 Flowchart for Erasing Multiple Blocks Start Notes: *1 Program all addresses to be erased by following the prewrite flowchart. *2 Set the watchdog timer overflow interval to the value indicated in table 19.10. *3 For the erase-verify dummy write, write H'FF with a byte transfer instruction. *4 Read the data to be verified with a byte transfer instruction. When erasing two or more blocks, clear the bits of erased blocks in the erase block register, so that only unerased blocks will be erased again. *5 X: 10 ms tVS1: 4 s or more tVS2: 2 s or more N: 3000 Set erase block registers (set bits of blocks to be erased to 1) Write 0 data to all addresses to be erased (prewrite)*1 n=1 Enable watchdog timer*2 Select erase mode (E bit = 1 in FLMCR) Wait (X) ms*5 Erasing ends Clear E bit Disable watchdog timer Select erase-verify mode (EV bit = 1 in FLMCR) Wait (tVS1) s*5 Set top address of block as verify address Dummy write to verify address*3 (flash memory latches address) Erase-verify next block Wait (tVS2) s*5 Verify*4 (read data H'FF?) Erase-verify next block No go OK No Address + 1 address Last address in block? Yes All erased blocks verified? No Yes Clear EBR bit of erased block No All erased blocks verified? Yes Clear EV bit All blocks erased? (EBR1 = EBR2 = 0?) Yes End of erase No n N?*5 Yes Erase error Figure 19.11 Multiple-Block Erase Flowchart 404 No n+1n Sample Multiple-Block Erase Program: This program uses the following registers. R0: Specifies blocks to be erased (set as explained below), and also stores address used in prewrite and erase-verify. R1H: Used to test bits 8 to 11 of R0 stores register read data, and also used for dummy write. R1L: Used to test bits 0 to 11 of R0. R2: Specifies address where address used in prewrite and erase-verify is stored. R3: Stores address used in prewrite and erase-verify. R4: Stores last address of block to be erased. R5: Sets prewrite and erase timing loop counters. R6L: Used for prewrite-verify and erase-verify fail count. Arbitrary blocks can be erased by setting bits in R0. Write R0 with a word transfer instruction. A bit map of R0 and a sample setting for erasing specific blocks are shown next. Bit 15 14 13 12 R0 -- -- -- -- 11 10 9 8 7 6 5 4 3 2 1 0 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Corresponds to EBR1 Corresponds to EBR2 Note: Clear bits 15, 14, 13, and 12 to 0. Example: to erase blocks LB2, SB7, and SB0 Bit 15 14 13 12 R0 -- -- -- -- 11 10 9 8 7 6 0 0 0 4 3 2 1 0 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Corresponds to EBR1 Setting 5 0 0 1 Corresponds to EBR2 0 0 1 0 0 0 0 0 0 1 R0 is set as follows: MOV.W MOV.W #H'0481,R0 R0, @EBR1 The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a, #b, #c, #d, and #e values according to tables 19.9 (1), (2), and 19.10. 405 Notes: 1. In this sample program, the stack pointer (SP) is set at address H'FF80. As the stack area, on-chip RAM addresses H'FF7E and H'FF7F are used. Therefore, when executing this sample program, addresses H'FF7E and H'FF7F should not be used. In addition, the on-chip RAM should not be disabled. 2. In this sample program, the program written in a ROM area (including external space) is transferred into the RAM area and executed in the RAM to which the program is transferred. #RAMSTR in the program is the starting destination address in RAM to which the program is transferred. #RAMSTR must be set to an even number. 3. When executing this sample program in the on-chip ROM area or external space, #RAMSTR should be set to #START. FLMCR: EBR1: EBR2: TCSR: STACK: .RQU .EQU .EQU .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFA8 H'FF80 .ALIGN MOV.W 2 #STACK, SP ; Set stack pointer ; Set the bits in R0 following the description on the previous page. This program is a sample program to erase ; all blocks. MOV.W #H'0FFF, R0 ; Select blocks to be erased (R0: EBR1/EBR2) MOV.W R0, @EBR1 ; Set EBR1/EBR2 START: ; #RAMSTR is starting destination address to which program is transferred in RAM. ; Set #RAMSTR to even number. MOV.W #RAMSTR, R2 ; Starting transfer destination address (RAM) MOV.W #ERVADR, R3 ; ADD.W R3, R2 ; #RAMSTR + #ERVADR R2 MOV.W #START, R3 ; SUB.W R3, R2 ; Address of data area used in RAM PRETST: EBR2PW: PWADD1: 406 MOV.B CMP.B BEQ CMP.B BMI MOV.B SUBX BTST BNE BRA BTST BNE INC MOV.W BRA #H'00, #H'0C, ERASES #H'08, EBR2PW R1L, #H'08, R1H, PREWRT PWADD1 R1L, PREWRT R1L @R2+, PRETST R1L R1L R1L R1H R1H R0H R0L R3 : ; ; ; ; ; ; ; ; ; ; ; ; ; ; Used to test R1L bit in R0 R1L = H'0C? If finished checking all R0 bits, branch to ERASES Test EBR1 if R1L 8, or EBR2 if R1L < 8 R1L - 8 R1H Test R1H bit in EBR1 (R0H) If R1H bit in EBR1 (R0H) is 1, branch to PREWRT If R1H bit in EBR1 (R0H) is 0, branch to PWADD1 Test R1L bit in EBR2 (R0L) If R1L bit in EBR2 (R0H) is 1, branch to PREWRT R1L + 1 R1L Dummy-increment R2 ; Execute prewrite PREWRT: PREW: PREWRS: LOOPR1: LOOPR2: @R2+, #H'00, #H'a, R6L #H'00 R1H, #H'A578, R4, R5, #0, #1, R4, LOOPR1 #0, #H'A500, R4, R3 R6L R5 MOV.B DEC BNE MOV.B BEQ CMP.B BEQ BRA #H'c, R4H LOOPR2 @R3, PWVFOK #H'32, ABEND1 PREWRS R4H ABEND1: Programming error PWVFOK: ADDS MOV.W CMP.W BNE INC BRA PWADD2: ; ; ; ; R1H ; @R3 ; R4 ; @TCSR ; R4 ; MOV.W MOV.B MOV.W INC MOV.B MOV.B MOV.W MOV.W MOV.W BSET SUBS MOV.W BNE BCLR MOV.W MOV.W Prewrite starting address Prewrite-verify fail counter Prewrite-verify loop counter Prewrite-verify fail counter + 1 R6L Write H'00 Start watchdog timer Set prewrite loop counter @FLMCR:8 ; Set P bit R4 ; R4 ; ; Wait loop @FLMCR:8 ; Clear P bit R4 ; @TCSR ; Stop watchdog timer R1H R6L ; ; ; ; ; ; ; ; Set prewrite-verify loop counter ; ; ; ; ; ; Address + 1 R3 Top address of next block Last address? If not last address, prewrite next address Used to test R1L+1 bit in R0 Branch to PRETST Wait loop Read data = H'00? If read data = H'00 branch to PWVFOK Prewrite-verify executed 50 times? If prewrite-verify executed 50 times, branch to ABEND1 Prewrite again #1, @R2, R4, PREW R1L PRETST R3 R4 R3 #H'0000, #H'd, #1, #H'e, R4, R5, #1, R6 ; Erase-verify fail counter R5 ; Set erase loop count R6 ; Erase-verify fail counter + 1 R6 R4 ; @TCSR ; Start watchdog timer R4 ; Set erase loop counter @FLMCR:8 ; Set E bit #1, R4, LOOPE #1, #H'A500, R4, R4 R4 ; Execute erase ERASES: ERASE: LOOPE: MOV.W MOV.W ADDS MOV.W MOV.W MOV.W BSET NOP NOP NOP NOP SUBS MOV.W BNE BCLR MOV.W MOV.W ; ; ; Wait loop @FLMCR:8 ; Clear E bit R4 ; @TCSR ; Stop watchdog timer 407 ; Execute erase-verify EVR: ; Starting transfer destination address (RAM) ; ; #RAMSTR + #ERVADR R2 ; ; Address of data area used in RAM MOV.W MOV.W ADD.W MOV.W SUB.W #RAMSTR, #ERVADR, R3, #START, R3, R2 R3 R2 R3 R2 MOV.B MOV.B BSET DEC BNE CMP.B BEQ CMP.B BMI MOV.B SUBX BTST BNE BRA BTST BNE INC MOV.W BRA #H'00, #H'b, #3, R4H LOOPEV #H'0C, HANTEI #H'08, EBR2EV R1L, #H'08, R1H, ERSEVF ADD01 R1L, ERSEVF R1L @R2+, EBRTST R1L ; Used to test R1L bit in R0 R4H ; Set erase-verify loop counter @FLMCR:8 ; Set EV bit ERASE1: BRA ERASE ERSEVF: EVR2: MOV.W MOV.B MOV.B MOV.B DEC BNE MOV.B CMP.B BNE MOV.W CMP.W BNE @R2+, #H'FF, R1H, #H'c, R4H LOOPEP @R3+, #H'FF, BLKAD @R2, R4, EVR2 R3 R1H @R3 R4H CMP.B BMI MOV.B SUBX BCLR BRA BCLR INC BRA #H'08, SBCLR R1L, #H'08, R1H, BLKAD R1L, R1L EBRTST R1L BCLR MOV.W BEQ #3, R0, EOWARI @FLMCR:8 @EBR1 ; LOOPEV: EBRTST: EBR2EV: ADD01: LOOPEP: SBCLR: BLKAD: HANTEI: 408 R1L R1L R1H R1H R0H R0L R3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Wait loop R1L = H'0C? If finished checking all R0 bits, branch to HANTEI Test EBR1 if R1L 8, or EBR2 if R1L < 8 R1L - 8 R1H Test R1H bit in EBR1 (R0H) If R1H bit in EBR1 (R0H) is 1, branch to ERSEVF If R1H bit in EBR1 (R0H) is 0, branch to ADD01 Test R1L bit in EBR2 (R0L) If R1L bit in EBR2 (R0H) is 1, branch to ERSEVF R1L + 1 R1L Dummy-increment R2 ; Branch to ERASE via Erase 1 R1H R1H R4 R3 R1H R1H R0H R0L ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Top address of block to be erase-verified Dummy write Set erase-verify loop counter Wait loop Read Read data = H'FF? If read data H'FF branch to BLKAD Top address of next block Last address of block? Test EBR1 if R1L 8, or EBR2 if R1L < 8 R1L - 8 R1H Clear R1H bit in EBR1 (R0H) Clear R1L bit in EBR2 (R0L) R1L + 1 R1L ; Clear EV bit ; If EBR1/EBR2 is all 0, erasing ended normally BRER: MOV.W CMP.W BNE BRA #H'0BB8, R4, ERASE1 ABEND2 R4 R6 ; ; Erase-verify executed 3000 times? ; If erase-verify not executed 3000 times, erase again ; If erase-verify executed 3000 times, branch to ABEND2 ;------< Block address table used in erase-verify> ------ ERVADR: EOWARI: ABEND2: .ALIGN .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W 2 H'0000 H'0080 H'0100 H'0180 H'0200 H'0400 H'0800 H'0C00 H'1000 H'2000 H'4000 H'6000 H'8000 ; ; ; ; ; ; ; ; ; ; ; ; ; SB0 SB1 SB2 SB3 SB4 SB5 SB6 SB7 LB0 LB1 LB2 LB3 FLASH END Erase end Erase error Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings: The setting of #a, #b, #c, #d, and #e values in the programs depends on the clock frequency. Tables 19.9 (1) and (2) indicate sample loop counter settings for typical clock frequencies. However, #e is set according to table 19.10. As a software loop is used, calculated values including percent errors may not be the same as actual values. Therefore, the values are set so that the total programming time and total erase time do not exceed 1 ms and 30 s, respectively. The maximum number of writes in the program, N, is set to 50. Programming and erasing in accordance with the flowcharts is achieved by setting #a, #b, #c, and #d in the programs as shown in tables 19.9 (1) and (2). #e should be set as shown in table 19.10. Wait state insertion is inhibited in these programs. If wait states are to be used, the setting should be made after the program ends. The setting value for the watchdog timer (WDT) overflow time is calculated based on the number of instructions between starting and stopping of the WDT, including the write time and erase time. Therefore, no other instructions should be added between starting and stopping of the WDT in this program example. 409 Table 19.9 (1) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with Program Running in the On-Chip Memory (RAM) Clock Frequency f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz Variable Time Setting Counter Counter Counter Counter Setting Value Setting Value Setting Value Setting Value a(f) Programming time 20 s H'0028 H'0019 H'0014 H'0005 b(f) tvs1 4 s H'0B H'07 H'06 H'02 c (f) tvs2 2 s H'06 H'04 H'03 H'01 d(f) Erase time 10 ms H'2710 H'186A H'1388 H'04E2 Table 19.9 (2) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with Program Running in the External Device Clock Frequency f = 16 MHz f = 10 MHz f = 8 MHz f = 2 MHz Variable Time Setting Counter Counter Counter Counter Setting Value Setting Value Setting Value Setting Value a(f) Programming time 20 s H'000D H'0008 H'0006 H'0001 b(f) tvs1 4 s H'04 H'03 H'02 H'01 c (f) tvs2 2 s H'02 H'02 H'01 H'01 d(f) Erase time 10 ms H'0D05 H'0823 H'0682 H'01A0 410 Formula: When using a clock frequency not shown in tables 19.9 (1) and (2), follow the formula below. The calculation is based on a clock frequency of 10 MHz. After calculating a(f) and d(f) in the decimal system, omit the first decimal figures, and convert them to the hexadecimal system, so that a(f) and d(f) are set to 20 s or less and 10 ms or less, respectively. After calculating b(f) and c(f) in the decimal system, raise the first decimal figures, and convert them to the hexadecimal system, so that b(f) and c(f) are set to 4 s or more and 2 s or more, respectively. a (f) to d (f) = Clock frequency f [MHz] 10 x a (f = 10) to d (f = 10) Examples for a program running in on-chip memory (RAM) at a clock frequency of 12 MHz: a (f) = 12 10 x 25 = 30 = H'001E b (f) = 12 10 x 7 = 8.4 9 = H'09 c (f) = 12 10 x 4 = 4.8 5 = H'05 d (f) = 12 10 x 6250 = 7500 7500 = H'1D4C Table 19.10 30 Watchdog Timer Overflow Interval Settings (#e Setting Value According to Clock Frequency) Variable Clock Frequency [MHz] e (f) 10 MHz frequency 16 MHz H'A57F 2 MHz frequency < 10 MHz H'A57E 411 19.4.7 Prewrite Verify Mode Prewrite-verify mode is a verify mode used when programming all bits to equalize their threshold voltages before erasing them. Program all flash memory to H'00 by writing H'00 using the prewrite algorithm shown in figure 19.10. H'00 should also be written when using RAM for flash memory emulation (when prewriting a RAM area). (This also applies when using RAM to emulate flash memory erasing with an emulator or other support tool.) After the necessary programming time has elapsed, exit program mode (by clearing the P bit to 0) and select prewrite-verify mode (leave the P, E, PV, and EV bits all cleared to 0). In prewrite-verify mode, a prewrite-verify voltage is applied to the memory cells at the read address. If the flash memory is read in this state, the data at the read address will be read. After selecting prewrite-verify mode, wait 4 s or more before reading. Note: For a sample prewriting program, see the prewrite subroutine in the sample erasing program. 19.4.8 Protect Modes Flash memory can be protected from programming and erasing by software or hardware methods. These two protection modes are described below. Software Protection: Prevents transitions to program mode and erase mode even if the P or E bit is set in the flash memory control register (FLMCR). Details are as follows. Function Protection Description Program Erase Verify*1 Block protect Individual blocks can be protected from erasing and programming by the erase block registers (EBR1 and EBR2). If H'F0 is set in EBR1 and H'00 in EBR2, all blocks are protected from erasing and programming. Disabled Disabled Enabled Emulation protect *2 When the RAMS or RAM0 bit, but not both, is set in the wait-state control register (WSCR), all blocks are protected from programming and erasing. Disabled Disabled*3 Enabled Notes: *1 Three modes: program-verify, erase-verify, and prewrite-verify. *2 Except in RAM areas overlapped onto flash memory. *3 All blocks are erase-disabled. It is not possible to specify individual blocks. 412 Hardware Protection: Suspends or disables the programming and erasing of flash memory, and resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2). Details of hardware protection are as follows. Function Verify*1 Protection Description Program Erase Programing voltage (V PP ) protect When 12 V is not applied to the FVPP pin, FLMCR, EBR1, and EBR2 are initialized, disabling programming and erasing. To obtain this protection, VPP should not exceed VCC.*3 Disabled Disabled*2 Disabled Reset and standby protect Disabled When a reset occurs (including a watchdog timer reset) or standby mode is entered, FLMCR, EBR1, and EBR2 are initialized, disabling programming and erasing. Note that RES input does not ensure a reset unless the RES pin is held low for at least 20 ms at powerup (to enable the oscillator to settle), or at least ten system clock cycles (10o) during operation. Disabled*2 Disabled Interrupt protect To prevent damage to the flash memory, if interrupt input occurs while flash memory is being programmed or erased, programming or erasing is aborted immediately. The settings in FLMCR, EBR1, and EBR2 are retained. This type of protection can be cleared only by a reset. Disabled Disabled*2 Enabled Notes: *1 Three modes: program-verify, erase-verify, and prewrite-verify. *2 All blocks are erase-disabled. It is not possible to specify individual blocks. *3 For details, see section 19.7, Flash Memory Programming and Erasing Precautions. 19.4.9 Interrupt Handling during Flash Memory Programming and Erasing If an interrupt occurs*1 while flash memory is being programmed or erased (while the P or E bit of FLMCR is set), the following operating states can occur. * If an interrupt is generated during programming or erasing, programming or erasing is aborted to protect the flash memory. Since memory cell values after a forced interrupt are indeterminate, the system will not operate correctly after such an interrupt. * Program runaway may result because the vector table could not be read correctly in interrupt exception handling during programming or erasure*2. 413 For NMI interrupts while flash memory is being programmed or erased, these malfunction and runaway problems can be prevented by using the RAM overlap function with the settings described below. 1. Do not store the NMI interrupt-handling routine*3 in the flash memory area (H'0000 to H'7FFF). Store it elsewhere (in RAM, for example). 2. Set the NMI interrupt vector in address H'FC06 in RAM (corresponding to H'0006 in flash memory). 3. After the above settings, set both the RAMS and RAM0 bits to 1 in WSCR. *4 Due to the setting of step 3, if an interrupt signal is input while 12 V is applied to the FVPP pin, the RAM overlap function is enabled and part of the RAM (H'FC00 to H'FC7F) is overlapped onto the small-block area of flash memory (H'0000 to H'007F). As a result, when an interrupt is input, the vector is read from RAM, not flash memory, so the interrupt is handled normally even if flash memory is being programmed or erased. This can prevent malfunction and runaway. Notes: *1 When the interrupt mask bit (I) of the condition control register (CCR) is set to 1, all interrupts except NMI are masked. For details see (2) in section 2.2.2, Control Registers. *2 The vector table might not be read correctly for one of the following reasons: * If flash memory is read while it is being programmed or erased (while the P or E bit of FLMCR is set), the correct value cannot be read. * If no value has been written for the NMI entry in the vector table yet, NMI exception handling will not be executed correctly. *3 This routine should be programmed so as to prevent microcontroller runaway. *4 For details on WSCR settings, see section 19.2.4, Wait-State Control Register. Notes on Interrupt Handling in Boot Mode: In boot mode, the settings described above concerning NMI interrupts are carried out, and NMI interrupt handling (but not other interrupt handling) is enabled while the boot program is executing. Note the following points concerning the user program. * If interrupt handling is required Load the NMI vector (H'FB80) into address H'FC06 in RAM (the 38th byte of the transferred user program should be H'FB80). The interrupt handling routine used by the boot program is stored in addresses H'FB80 to H'FB8F in RAM. Make sure that the user program does not overwrite this area. * If interrupt handling is not required Since the RAMS and RAM0 bits remain set to 1 in WSCR, make sure that the user program disables the RAM overlap by clearing the RAMS and RAM0 bits both to 0. 414 19.5 Flash Memory Emulation by RAM Erasing and programming flash memory takes time, which can make it difficult to tune parameters and other data in real time. If necessary, real-time updates of flash memory can be emulated by overlapping the small-block flash-memory area with part of the RAM (H'FC00 to H'FD7F). This RAM reassignment is performed using bits 7 and 6 of the wait-state control register (WSCR). After a flash memory area has been overlapped by RAM, the RAM area can be accessed from two address areas: the overlapped flash memory area, and the original RAM area (H'FC00 to H'FD7F). Table 19.11 indicates how to reassign RAM. Wait-State Control Register (WSCR)*2 Bit 7 6 5 4 3 2 1 0 RAMS RAM0 CKDBL -- WMS1 WMS0 WC1 WC0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W *1 Notes: *1 WSCR is initialized by a reset and in hardware standby mode. It is not initialized in software standby mode. *2 For details of WSCR settings, see section 19.2.4, Wait-State Control Register (WSCR). Table 19.11 RAM Area Selection Bit 7: RAMS Bit 6: RAMO RAM Area ROM Area 0 0 None -- 1 H'FC80 to H'FCFF H'0080 to H'00FF 0 H'FC80 to H'FD7F H'0080 to H'017F 1 H'FC00 to H'FC7F H'0000 to H'007F 1 415 Example of Emulation of Real-Time Flash-Memory Update H'0000 Small-block area (SB1) Overlapped RAM H'007F H'0080 H'00FF H'0100 Flash memory address space H'7FFF H'FB80 Overlapped RAM H'FC80 H'FCFF On-chip RAM area H'FF7F Procedure 1. Overlap part of RAM (H'FC80 to H'FCFF) onto the area requiring real-time update (SB1). (Set WSCR bits 7 and 6 to 01.) 2. Perform real-time updates in the overlapping RAM. 3. After finalization of the update data, clear the RAM overlap (by clearing the RAMS and RAM0 bits). 4. Read the data written in RAM addresses H'FC80 to H'FCFF out externally, then program the flash memory area, using this data as part of the program data. Figure 19.12 Example of RAM Overlap 416 Notes on Use of RAM Emulation Function * Notes on Applying, Releasing, and Shutting Off the Programming Voltage (VPP) Care is necessary to avoid errors in programming and erasing when applying, releasing, and shutting off VPP, just as in the on-board programming modes. In particular, even if the emulation function is being used, make sure that the watchdog timer is set when the P or E bit of the flash memory control register (FLMCR) has been set, to prevent errors in programming and erasing due to program runaway while VPP is applied. For details see section 19.7, Flash Memory Programming and Erasing Precautions (5). 417 19.6 Flash Memory Writer Mode (H8/3434F) 19.6.1 Writer Mode Setting The on-chip flash memory of the H8/3434F can be programmed and erased not only in the onboard programming modes but also in writer mode, using a PROM programmer. 19.6.2 Socket Adapter and Memory Map Programs can be written and verified by attaching a special 100-pin/32-pin socket adapter to the PROM programmer. Table 19.12 gives ordering information for the socket adapter. Figure 19.13 shows a memory map in writer mode. Figure 19.14 shows the socket adapter pin interconnections. Table 19.12 Socket Adapter Microcontroller Package Socket Adapter HD64F3434F16 100-pin QFP HS3434ESHF1H HD64F3434TF16 100-pin TQFP HS3434ESNF1H MCU mode H'0000 H8/3434F Writer mode H'0000 On-chip ROM area H'7FFF H'7FFF 1 output H'1FFFF Figure 19.13 Memory Map in Writer Mode 418 H8/3434F Pin No. Pin Name Socket Adapter FP-100B, TFP-100B HN28F101 (32 Pins) Pin Name Pin No. 8 STBY/FVPP VPP 1 7 NMI FA 9 26 18 P95 FA 16 2 19 P94 FA 15 3 22 P93 WE 31 82 P30 FO 0 13 83 P31 FO 1 14 84 P32 FO 2 15 85 P33 FO 3 17 86 P34 FO 4 18 87 P35 FO 5 19 88 P36 FO 6 20 89 P37 FO 7 21 79 P10 FA 0 12 78 P11 FA 1 11 77 P12 FA 2 10 76 P13 FA 3 9 75 P14 FA 4 8 74 P15 FA 5 7 73 P16 FA 6 6 72 P17 FA 7 5 67 P20 FA 8 27 66 P21 OE 24 65 P22 FA 10 23 64 P23 FA 11 25 63 P24 FA 12 4 62 P25 FA 13 28 61 P26 FA 14 29 60 P27 CE 22 P91, P90, P63, VCC 32 P64, P97 VSS 16 24, 25, 29, 32, 16 5, 6, 23,35 MD1, MD0, P92, P67 36, 37 AVref, AVCC 4, 9, 59 VCCB, VCC 46 AVSS 15, 70, 71, 92 VSS 1 RES 2, 3 Other pins Power-on reset circuit XTAL, EXTAL Legend: VPP: FO7 to FO0: FA16 to FA0: OE: CE: WE: Programming power supply Data input/output Address input Output enable Chip enable Write enable Oscillator circuit NC (OPEN) Figure 19.14 Wiring of Socket Adapter 419 19.6.3 Operation in Writer Mode The program/erase/verify specifications in writer mode are the same as for the standard HN28F101 flash memory. However, since the H8/3434F does not support product name recognition mode, the programmer cannot be automatically set with the device name. Table 19.13 indicates how to select the various operating modes. Table 19.13 Operating Mode Selection in Writer Mode Pins FV PP VCC CE OE WE D7 to D0 A16 to A0 Read VCC VCC L L H Data output Address input Output disable VCC VCC L H H High impedance Standby VCC VCC H X X High impedance Read VPP VCC L L H Data output Output disable VPP VCC L H H High impedance Standby VPP VCC H X X High impedance Write VPP VCC L H L Data input Mode Read Command write Note: Be sure to set the FV PP pin to VCC in these states. If it is set to 0 V, hardware standby mode will be entered, even when in writer mode, resulting in incorrect operation. Legend: L: Low level H: High level VPP level VPP : VCC: VCC level X: Don't care 420 Table 19.14 Writer Mode Commands 1st Cycle 2nd Cycle Command Cycles Mode Address Data Mode Address Data Memory read 1 Write X H'00 Read RA Dout Erase setup/erase 2 Write X H'20 Write X H'20 Erase-verify 2 Write EA H'A0 Read X EVD Auto-erase setup/ auto-erase 2 Write X H'30 Write X H'30 Program setup/ program 2 Write X H'40 Write PA PD Program-verify 2 Write X H'C0 Read X PVD Reset 2 Write X H'FF Write X H'FF PA: EA: RA: PD: PVD: EVD: Program address Erase-verify address Read address Program data Program-verify output data Erase-verify output data 421 High-Speed, High-Reliability Programming: Unused areas of the H8/3434F flash memory contain H'FF data (initial value). The H8/3434F flash memory uses a high-speed, high-reliability programming procedure. This procedure provides enhanced programming speed without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. Figure 19.15 shows the basic high-speed, high-reliability programming flowchart. Tables 19.15 and 19.16 list the electrical characteristics during programming. Start Set VPP = 12.0 V 0.6 V Address = 0 n=0 n+1n Program setup command Program command Wait (25 s) Program-verify command Wait (6 s) Address + 1 address Verification? No go Go No n = 20? No Last address? Yes Yes Set VPP = VCC End Fail Figure 19.15 High-Speed, High-Reliability Programming 422 High-Speed, High-Reliability Erasing: The H8/3434F flash memory uses a high-speed, highreliability erasing procedure. This procedure provides enhanced erasing speed without subjecting the device to voltage stress and without sacrificing data reliability. Figure 19.16 shows the basic high-speed, high-reliability erasing flowchart. Tables 19.15 and 19.16 list the electrical characteristics during erasing. Start Program all bits to 0* Address = 0 n=0 n+1n Erase setup/erase command Wait (10 ms) Erase-verify command Wait (6 s) Address + 1 address Verification? No go Go No n = 3000? No Last address? Yes Yes End Fail Note: * Follow the high-speed, high-reliability programming flowchart in programming all bits. If some bits are already programmed to 0, program only the bits that have not yet been programmed. Figure 19.16 High-Speed, High-Reliability Erasing 423 Table 19.15 DC Characteristics in Writer Mode (Conditions: VCC = 5.0 V 10%, V PP = 12.0 V 0.6 V, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Typ Max Unit Test Conditions Input high voltage FO7 to FO0, FA 16 to FA0, OE, CE, WE VIH 2.2 -- VCC + 0.3 V Input low voltage FO7 to FO0, FA 16 to FA0, OE, CE, WE VIL -0.3 -- 0.8 V Output high voltage FO7 to FO0 VOH 2.4 -- -- V I OH = -200 A Output low voltage FO7 to FO0 VOL -- -- 0.45 V I OL = 1.6 mA Input leakage current FO7 to FO0, FA 16 to FA0, OE, CE, WE | ILI | -- -- 2 A Vin = 0 to VCC VCC current Read I CC -- 40 80 mA Program I CC -- 40 80 mA Erase I CC -- 40 80 mA Read I PP -- -- 10 A VPP = 5.0 V -- 10 20 mA VPP = 12.6 V FV PP current 424 Program I PP -- 20 40 mA VPP = 12.6 V Erase I PP -- 20 40 mA VPP = 12.6 V Table 19.16 AC Characteristics in Writer Mode (Conditions: VCC = 5.0 V 10%, V PP = 12.0 V 0.6 V, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Typ Max Unit Test Conditions Command write cycle t CWC 120 -- -- ns Address setup time t AS 0 -- -- ns Address hold time t AH 60 -- -- ns Figure 19.17 Figure 19.18* Figure 19.19 Data setup time t DS 50 -- -- ns Data hold time t DH 10 -- -- ns CE setup time t CES 0 -- -- ns CE hold time t CEH 0 -- -- ns VPP setup time t VPS 100 -- -- ns VPP hold time t VPH 100 -- -- ns WE programming pulse width t WEP 70 -- -- ns WE programming pulse high time t WEH 40 -- -- ns OE setup time before command write t OEWS 0 -- -- ns OE setup time before verify t OERS 6 -- -- s Verify access time t VA -- -- 500 ns OE setup time before status polling t OEPS 120 -- -- ns Status polling access time t SPA -- -- 120 ns Program wait time t PPW 25 -- -- ns Erase wait time t ET 9 -- 11 ms Output disable time t DF 0 -- 40 ns Total auto-erase time t AET 0.5 -- 30 s Note: CE, OE, and WE should be high during transitions of VPP from 5 V to 12 V and from 12 V to 5 V. * Input pulse level: 0.45 V to 2.4 V Input rise time and fall time 10 ns Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output 425 Auto-erase setup VCC VPP Auto-erase and status polling 5.0 V 12 V 5.0 V tVPS tVPH Address CE tCEH OE tCES tOEWS tWEP WE tDS I/O7 tOEPS tCWC tCES tCEH tWEH tDH Command input tCES tAET tWEP tDH tDS tSPA Command input Status polling I/O0 to I/O6 Command input Command input Figure 19.17 Auto-Erase Timing 426 tDF Program setup VCC Program Program-verify 5.0 V 12 V VPP 5.0 V tVPS tVPH Address Valid address tAH tAS CE tCEH tCES OE tOEWS tWEP tCWC tCEH tWEH tDH WE tDS tCES tCES tPPW tWEP tDH tDS tCEH tWEP tOERS tDH tDS tVA tDF I/O7 Command input Data input Command input Valid data output I/O0 to I/O6 Command input Data input Command input Valid data output Note: Program-verify data output values may be intermediate between 1 and 0 before programming has been completed. Figure 19.18 High-Speed, High-Reliability Programming Timing 427 Erase setup VCC Erase Erase-verify 5.0 V 12 V VPP 5.0 V tVPS tVPH Address Valid address tAS tAH CE OE tOEWS tCES tWEP WE tCES tCEH tDS I/O0 to I/O7 Command input tDH tCEH tCES tCEH tCWC tET tWEP tOERS tWEP tVA tWEH tDS tDH Command input tDS tDH Command input tDF Valid data output Note: Erase-verify data output values may be intermediate between 1 and 0 before erasing has been completed. Figure 19.19 Erase Timing 19.7 Flash Memory Programming and Erasing Precautions Read these precautions before using writer mode, on-board programming mode, or flash memory emulation by RAM. (1) Program with the specified voltages and timing. The rated programming voltage (VPP) of the flash memory is 12.0 V. If the PROM programmer is set to Hitachi HN28F101 specifications, VPP will be 12.0 V. Applying voltages in excess of the rating can permanently damage the device. Take particular care to ensure that the PROM programmer peak overshoot does not exceed the rated limit of 13 V. (2) Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (3) Don't touch the socket adapter or chip while programming. Touching either of these can cause contact faults and write errors. 428 (4) Set H'FF as the PROM programmer buffer data for addresses H'8000 to H'1FFFF. The H8/3434F PROM size is 32 kbytes. Addresses H'8000 to H'1FFFF always read H'FF, so if H'FF is not specified as programmer data, a verify error will occur. (5) Notes on applying, releasing, and shutting off the programming voltage (VPP) Note: In this section, the application, release, and shutting-off of VPP are defined as follows. Application: A rise in voltage from VCC to 12 V 0.6 V. Release: A drop in voltage from 12 V 0.6 V to VCC. Shut-off: No applied voltage (floating). * Apply the programming voltage (V PP ) after the rise of VCC, and release VPP before shutting off VCC. To prevent unintended programming or erasing of flash memory, in these power-on and power-off timings, the application, release, and shutting-off of VPP must take place when the microcontroller is in a stable operating condition as defined below. Stable operating condition The VCC voltage must be stabilized within the rated voltage range (VCC = 2.7 V to 5.5 V)* If VPP is applied, released, or shut off while the microcontroller's V CC voltage is not within the rated voltage range (VCC = 2.7 to 5.5 V)*, since microcontroller operation is unstable, the flash memory may be programmed or erased by mistake. This can occur even if VCC = 0 V. To prevent changes in the VCC power supply when V PP is applied, be sure that the power supply is adequately decoupled with inserting bypass capacitors. Note: * In the LH version, V CC = 3.0 V to 5.5 V. Clock oscillation must be stabilized (the oscillation settling time must have elapsed), and oscillation must not be stopped When turning on VCC power, hold the RES pin low during the oscillation settling time (tOSC1 = 20 ms), and do not apply VPP until after this time. The microcontroller must be in the reset state, or in a state in which a reset has ended normally (reset has been released) and flash memory is not being accessed Apply or release VPP either in the reset state, or when the CPU is not accessing flash memory (when a program in on-chip RAM or external memory is executing). Flash memory cannot be read normally at the instant when VPP is applied or released. Do not read flash memory while VPP is being applied or released. For a reset during operation, apply or release VPP only after the RES pin has been held low for at least ten system clock cycles (10o). 429 The P and E bits must be cleared in the flash memory control register (FLMCR) When applying or releasing V PP , make sure that the P or E bit is not set by mistake. No program runaway When V PP is applied, program execution must be supervised, e.g. by the watchdog timer. These power-on and power-off timing requirements should also be satisfied in the event of a power failure and in recovery from a power failure. If these requirements are not satisfied, overprogramming or overerasing may occur due to program runaway etc., which could cause memory cells to malfunction. * The VPP flag is set and cleared by a threshold decision on the voltage applied to the FVPP pin. The threshold level is between approximately VCC + 2 V to 11.4 V. When this flag is set, it becomes possible to write to the flash memory control register (FLMCR) and the erase block registers (EBR1 and EBR2), even though the VPP voltage may not yet have reached the programming voltage range of 12.0 0.6 V. Do not actually program or erase the flash memory until VPP has reached the programming voltage range. The programming voltage range for programming and erasing flash memory is 12.0 0.6 V (11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range. When not programming or erasing the flash memory, ensure that the VPP voltage does not exceed the VCC voltage. This will prevent unintended programming and erasing. In this chip, the same pin is used for STBY and FVPP. When this pin is driven low, a transition is made to hardware standby mode. This happens not only in the normal operating modes (modes 1, 2, and 3), but also when programming the flash memory with a PROM programmer. When programming with a PROM programmer, therefore, use a programmer which sets this pin to the VCC level when not programming (FVPP =12 V). 430 tOSC1 o 2.7 to 5.5 V* 0 s min 0 s min VCC 12 0.6 V VCC + 2 V to 11.4 V VPP 0 s min 0 to VCCV VCCV Boot mode Timing at which boot program branches to RAM area 12 0.6 V VPP 0 to VCCV VCCV User program mode RES Min 10o (when RES is low) Periods during which the VPP flag is being set or cleared and flash memory must not be accessed Note: * In the LH version, VCC = 3.0 V to 5.5 V. Figure 19.20 VPP Power-On and Power-Off Timing (6) Do not apply 12 V to the FVPP pin during normal operation. To prevent accidental programming or erasing due to microcontroller program runaway etc., apply 12 V to the VPP pin only when the flash memory is programmed or erased, or when flash memory is emulated by RAM. Overprogramming or overerasing due to program runaway can cause memory cells to malfunction. Avoid system configurations in which 12 V is always applied to the FVPP pin. While 12 V is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing. 431 (7) Design a current margin into the programming voltage (VPP) power supply. Ensure that VPP will not depart from 12.0 0.6 V (11.4 V to 12.6 V) during programming or erasing. Programming and erasing may become impossible outside this range. (8) Ensure that peak overshoot does not exceed the rated value at the FV PP and MD1 pins. Connect decoupling capacitors as close to the FVPP and MD 1 pins as possible. Also connect decoupling capacitors to the MD1 pin in the same way when boot mode is used. FVPP 12 V 1.0 F 0.01 F H8/3434F MD1 12 V 1.0 F 0.01 F Note: Also connect decoupling capacitors to the MD1 pin in the same way when boot mode is used. Figure 19.21 VPP Power Supply Circuit Design (Example) (9) Use the recommended algorithms for programming and erasing flash memory. These algorithms are designed to program and erase without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. Before setting the program (P) or erase (E) bit in the flash memory control register (FLMCR), set the watchdog timer to ensure that the P or E bit does not remain set for more than the specified time. (10) For details on interrupt handling while flash memory is being programmed or erased, see the notes on NMI interrupt handling in section 19.4.9, Interrupt Handling during Flash Memory Programming and Erasing. 432 (11) Cautions on Accessing Flash Memory Control Registers 1. Flash memory control register access state in each operating mode The H8/3434F has flash memory control registers located at addresses H'FF80 (FLMCR), H'FF82 (EBR1), and H'FF83 (EBR2). These registers can only be accessed when 12 V is applied to the flash memory program power supply pin, FVPP. Table 19.17 shows the area accessed for the above addresses in each mode, when 12 V is and is not applied to FVPP. Table 19.17 Area Accessed in Each Mode with 12V Applied and Not Applied to FVPP Mode 1 Mode 2 Mode 3 12 V applied to FV PP Reserved area (always H'FF) Flash memory control register (initial value H'80) Flash memory control register (initial value H'80) 12 V not applied to FV PP External address space External address space Reserved area (always H'FF) 2. When a flash memory control register is accessed in mode 2 (expanded mode with on-chip ROM enabled) When a flash memory control register is accessed in mode 2, it can be read or written to if 12 V is being applied to FV PP , but if not, external address space will be accessed. It is therefore essential to confirm that 12 V is being applied to the FVPP pin before accessing these registers. 3. To check for 12 V application/non-application in mode 3 (single-chip mode) When address H'FF80 is accessed in mode 3, if 12 V is being applied to FVPP , FLMCR is read/written to, and its initial value after reset is H'80. When 12 V is not being applied to FV PP , FLMCR is a reserved area that cannot be modified and always reads H'FF. Since bit 7 (corresponding to the VPP bit) is set to 1 at this time regardless of whether 12 V is applied to FVPP , application or release of 12 V to FVPP cannot be determined simply from the 0 or 1 status of this bit. A byte data comparison is necessary to check whether 12V is being applied. The relevant coding is shown below. . . . LABEL1: MOV.B CMP.B BEQ . . . @H'FF80, R1L #H'FF, R1L LABEL1 Sample program for detection of 12 V application to FVPP (mode 3) 433 Table 19.18 DC Characteristics of Flash Memory Conditions: VCC = 2.7 V to 5.5 V*2, AVCC = 2.7 V to 5.5 V*2, AVref = 2.7 V to AVCC*2, VSS = AVSS = 0 V, V PP = 12.0 0.6 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions High-voltage (12 V) threshold level *1 FV PP , MD1 VH VCC + 2 -- 11.4 V FV PP current During read I PP -- -- 10 A VPP = 2.7 to 5.5 V -- 10 20 mA VPP = 12.6 V During programming -- 20 40 mA During erasure -- 20 40 mA Notes: *1 The listed voltages describe the threshold level at which high-voltage application is recognized. In boot mode and while flash memory is being programmed or erased, the applied voltage should be 12.0 V 0.6 V. *2 In the LH version, VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC. 434 Table 19.19 AC Characteristics of Flash Memory Conditions: VCC = 2.7 V to 5.5 V*5, AVCC = 2.7 V to 5.5 V*5, AVref = 2.7 V to AVCC*5, VSS = AVSS = 0 V, V PP = 12.0 0.6 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item *1, *2 Programming time *1, *3 Erase time Number of writing/erasing count Symbol Min Typ Max Unit tP -- 50 1000 s tE -- 1 30 s NWEC -- -- 100 Times Verify setup time 1 *1 t VS1 4 -- -- s Verify setup time 2 *1 t VS2 2 -- -- s t FRS 50 -- -- s 100 -- -- Flash memory read setup time*4 Test Conditions VCC 4.5 V VCC < 4.5 V Notes: *1 Set the times following the programming/erasing algorithm shown in section 19. *2 The programming time is the time during which a byte is programmed or the P bit in the flash memory control register (FLMCR) is set. It does not include the program-verify time. *3 The erase time is the time during which all 32-kbyte blocks are erased or the E bit in the flash memory control register (FLMCR) is set . It does not include the prewrite time before erasure or erase-verify time. *4 After power-on when using an external colck source, after return from standby mode, or after switching the programming voltage (VPP ) from 12 V to VCC, make sure that this read setup time has elapsed before reading flash memory. When VPP is released, the flash memory read setup time is defined as the period from when the FV PP pin has reached VCC + 2 V until flash memory can be read. *5 In the LH version, VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC. 435 436 Section 20 ROM (60-kbyte Dual-Power-Supply Flash Memory Version) 20.1 Flash Memory Overview 20.1.1 Flash Memory Operating Principle Table 20.1 illustrates the principle of operation of the H8/3437F's on-chip flash memory. Like EPROM, flash memory is programmed by applying a high gate-to-drain voltage that draws hot electrons generated in the vicinity of the drain into a floating gate. The threshold voltage of a programmed memory cell is therefore higher than that of an erased cell. Cells are erased by grounding the gate and applying a high voltage to the source, causing the electrons stored in the floating gate to tunnel out. After erasure, the threshold voltage drops. A memory cell is read like an EPROM cell, by driving the gate to the high level and detecting the drain current, which depends on the threshold voltage. Erasing must be done carefully, because if a memory cell is overerased, its threshold voltage may become negative, causing the cell to operate incorrectly. Section 20.4.6 shows an optimal erase control flowchart and sample program. Table 20.1 Principle of Memory Cell Operation Program Memory cell Memory array Erase Vg = VPP Read Vs = VPP Vg Open Vd Vd Vd 0V Open Open Vd 0V VPP 0V VCC 0V VPP 0V 0V 0V 0V 437 20.1.2 Mode Programming and Flash Memory Address Space As its on-chip ROM, the H8/3437F has 60 kbytes of flash memory. The flash memory is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states. The H8/3437F's flash memory is assigned to addresses H'0000 to H'EF7F in mode 2, and addresses H'0000 to H'F77F in mode 3. The mode pins enable either on-chip flash memory or external memory to be selected for this area. Table 20.2 summarizes the mode pin settings and usage of the memory area. Table 20.2 Mode Pin Settings and Flash Memory Area Mode Pin Setting Mode MD1 MD0 Memory Area Usage Mode 0 0 0 Illegal setting Mode 1 0 1 External memory area Mode 2 1 0 On-chip flash memory area (H'0000 to H'EF7F) Mode 3 1 1 On-chip flash memory area (H'0000 to H'F77F) 20.1.3 Features Features of the flash memory are listed below. * Five flash memory operating modes The flash memory has five operating modes: program mode, program-verify mode, erase mode, erase-verify mode, and prewrite-verify mode. * Block erase designation Blocks to be erased in the flash memory address space can be selected by bit settings. The address space includes a large-block area (eight blocks with sizes from 2 kbytes to 12 kbytes) and a small-block area (eight blocks with sizes from 128 bytes to 1 kbyte). * Program and erase time Programming one byte of flash memory typically takes 50 s. Erasing all blocks (60 kbytes) typically takes 1 s. * Erase-program cycles Flash memory contents can be erased and reprogrammed up to 100 times. * On-board programming modes These modes can be used to program, erase, and verify flash memory contents. There are two modes: boot mode and user programming mode. 438 * Automatic bit-rate alignment In boot-mode data transfer, the H8/3437F aligns its bit rate automatically to the host bit rate (maximum 9600 bps). * Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. * Writer mode As an alternative to on-board programming, the flash memory can be programmed and erased in writer mode, using a general-purpose PROM programmer. Program, erase, verify, and other specifications are the same as for HN28F101 standard flash memory. 20.1.4 Block Diagram Figure 20.1 shows a block diagram of the flash memory. 8 Internal data bus (upper) 8 Internal data bus (lower) FLMCR Bus interface and control section EBR1 H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 On-chip flash memory (60 kbytes) H'F77C H'F77D H'F77E H'F77F EBR2 Upper byte (even address) Operating mode MD1 MD0 Lower byte (odd address) Legend: FLMCR: Flash memory control register EBR1: Erase block register 1 EBR2: Erase block register 2 Figure 20.1 Flash Memory Block Diagram 439 20.1.5 Input/Output Pins Flash memory is controlled by the pins listed in table 20.3. Table 20.3 Flash Memory Pins Pin Name Abbreviation Input/Output Function Programming power FV PP Power supply Apply 12.0 V Mode 1 MD1 Input H8/3437F operating mode setting Mode 0 MD0 Input H8/3437F operating mode setting Transmit data TxD1 Output SCI1 transmit data output Receive data RxD1 Input SCI1 receive data input The transmit data and receive data pins are used in boot mode. 20.1.6 Register Configuration The flash memory is controlled by the registers listed in table 20.4. Table 20.4 Flash Memory Registers Name Abbreviation Flash memory control register Erase block register 1 FLMCR EBR1 Erase block register 2 *1 Wait-state control register R/W *2 R/W *2 R/W *2 Initial Value Address *2 FF80 *2 FF82 *2 H'00 H'00 EBR2 R/W H'00 FF83 WSCR R/W H'08 FFC2 Notes: *1 The wait-state control register controls the insertion of wait states by the wait-state controller, frequency division of clock signals for the on-chip supporting modules by the clock pulse generator, and emulation of flash-memory updates by RAM in on-board programming mode. *2 In modes 2 and 3 (on-chip flash memory enabled), the initial value is H'00 for FLMCR, EBR1 and EBR2. In mode 1 (on-chip flash memory disabled), these registers cannot be modified and always read H'FF. Registers FLMCR, EBR1, and EBR2 are only valid when writing to or erasing flash memory, and can only be accessed while 12 V is being applied to the FV PP pin. When 12 V is not applied to the FVPP pin, in mode 2 addresses H'FF80 to H'FF83 are external address space, and in mode 3 these addresses cannot be modified and always read H'FF. 440 20.2 Flash Memory Register Descriptions 20.2.1 Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register that controls the flash memory operating modes. Transitions to program mode, erase mode, program-verify mode, and erase-verify mode are made by setting bits in this register. FLMCR is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP. When 12 V is applied to the FVPP pin, a reset or entry to a standby mode initializes FLMCR to H'80. Bit 7 6 5 4 3 2 1 0 VPP -- -- -- EV PV E P Initial value* 0 0 0 0 0 0 0 0 Read/Write R -- -- -- R/W* R/W* R/W* R/W* Note: * The initial value is H'00 in modes 2 and 3 (on-chip flash memory enabled). In mode 1 (onchip flash memory disabled), this register cannot be modified and always reads H'FF. For information on accessing this register, refer to in section 20.7, Flash Memory Programming and Erasing Precautions (11). Bit 7--Programming Power (VPP): This status flag indicates that 12 V is applied to the FVPP pin. Refer to section 20.7, Flash Memory Programming and Erasing Precautions (5), for details on use. Bit 7: VPP Description 0 Cleared when 12 V is not applied to FVPP 1 Set when 12 V is applied to FVPP (Initial value) Bits 6 to 4--Reserved: Read-only bits, always read as 0. Bit 3--Erase-Verify Mode (EV): *1 Selects transition to or exit from erase-verify mode. Bit 3: EV Description 0 Exit from erase-verify mode 1 Transition to erase-verify mode (Initial value) Bit 2--Program-Verify Mode (PV):*1 Selects transition to or exit from program-verify mode. Bit 2: PV Description 0 Exit from program-verify mode 1 Transition to program-verify mode (Initial value) 441 Bit 1--Erase Mode (E):*1, *2 Selects transition to or exit from erase mode. Bit 1: E Description 0 Exit from erase mode 1 Transition to erase mode (Initial value) Bit 0--Program Mode (P):*1, *2 Selects transition to or exit from program mode. Bit 0: P Description 0 Exit from program mode 1 Transition to program mode (Initial value) Notes: *1 Do not set two or more of these bits simultaneously. Do not release or shut off the VCC or VPP power supply when these bits are set. *2 Set the P or E bit according to the instructions given in section 20.4, Programming and Erasing Flash Memory. Set the watchdog timer beforehand to make sure that these bits do not remain set for longer than the specified times. For notes on use, see section 20.7, Flash Memory Programming and Erasing Precautions. 20.2.2 Erase Block Register 1 (EBR1) EBR1 is an 8-bit register that designates large flash-memory blocks for programming and erasure. EBR1 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP pin. When a bit in EBR1 is set to 1, the corresponding block is selected and can be programmed and erased. Figure 20.2 and table 20.6 show details of a block map. Bit *1 Initial value Read/Write 7 6 5 4 3 2 1 0 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 0 0 0 0 0 0 0 0 *1, *2 R/W *1 R/W *1 R/W *1 R/W *1 R/W *1 R/W *1 R/W R/W*1 Notes: *1 The initial value is H'00 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip ROM disabled), this register cannot be modified and always reads H'FF. *2 This bit cannot be modified mode 2. For information on accessing this register, refer to in section 20.7, Flash Memory Programming and Erasing Precautions (11). 442 Bits 7 to 0--Large Block 7 to 0 (LB7 to LB0): These bits select large blocks (LB7 to LB0) to be programmed and erased. Bits 7 to 0: LB7 to LB0 Description 0 Block (LB7 to LB0) is not selected 1 Block (LB7 to LB0) is selected 20.2.3 (Initial value) Erase Block Register 2 (EBR2) EBR2 is an 8-bit register that designates small flash-memory blocks for programming and erasure. EBR2 is initialized to H'00 by a reset, in the standby modes, and when 12 V is not applied to FVPP pin. When a bit in EBR2 is set to 1, the corresponding block is selected and can be programmed and erased. Figure 20.2 and table 20.6 show a block map. Bit 7 6 5 4 3 2 1 0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Initial value* 0 0 0 0 0 0 0 0 Read/Write R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* Note: * The initial value is H'00 in modes 2 and 3 (on-chip ROM enabled). In mode 1 (on-chip ROM disabled), this register cannot be modified and always reads H'FF. For information on accessing this register, refer to in section 20.7, Flash Memory Programming and Erasing Precautions (11). Bits 7 to 0--Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be programmed and erased. Bits 7 to 0: SB7 to SB0 Description 0 Block (SB7 to SB0) is not selected 1 Block (SB7 to SB0) is selected (Initial value) 443 20.2.4 Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that enables flash-memory updates to be emulated in RAM. It also controls frequency division of clock signals supplied to the on-chip supporting modules and insertion of wait states by the wait-state controller. WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7 6 5 4 3 2 1 0 RAMS RAM0 CKDBL -- WMS1 WMS0 WC1 WC0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6--RAM Select and RAM0 (RAMS and RAM0): These bits are used to reassign an area to RAM (see table 20.5). These bits are write-enabled and their initial value is 0. They are initialized by a reset and in hardware standby mode. They are not initialized in software standby mode. If only one of bits 7 and 6 is set, part of the RAM area can be overlapped onto the small-block flash memory area. In that case, access is to RAM, not flash memory, and all flash memory blocks are write/erase-protected (emulation protect*1). In this state, the mode cannot be changed to program or erase mode, even if the P bit or E bit in the flash memory control register (FLMCR) is set (although verify mode can be selected). Therefore, clear both of bits 7 and 6 before programming or erasing the flash memory area. If both of bits 7 and 6 are set, part of the RAM area can be overlapped onto the small-block flash memory area, but this overlapping begins only when an interrupt signal is input while 12 V is being applied to the FVPP pin. Up until that point, flash memory is accessed. Use this setting for interrupt handling while flash memory is being programmed or erased.*2 Table 20.5 RAM Area Reassignment*3 Bit 7: RAMS Bit 6: RAM0 RAM Area ROM Area 0 0 None -- 1 H'F880 to H'F8FF H'0080 to H'00FF 0 H'F880 to H'F97F H'0080 to H'017F 1 H'F800 to H'F87F H'0000 to H'007F 1 444 Bit 5--Clock Double (CKDBL): Controls frequency division of clock signals supplied to the onchip supporting modules. For details, see section 6, Clock Pulse Generator. Bit 4--Reserved: This bit is reserved, but it can be written and read. Its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1, WMS0) Bits 1 and 0--Wait Count 1 and 0 (WC1, WC0) These bits control insertion of wait states by the wait-state controller. For details, see section 5, Wait-State Controller. Notes: *1 For details on emulation protect, see section 20.4.8, Protect Modes. *2 For details on interrupt handling during programming and erasing of flash memory, see section 20.4.9, Interrupt Handling during Flash Memory Programming and Erasing. *3 RAM area that overlaps flash memory. 445 Small block area (4 kbytes) Large block area (58 kbytes) H'0000 H'0000 SB7 to SB0 4 kbytes H'0FFF H'1000 SB0 128 bytes SB1 128 bytes SB2 128 bytes H'01FF SB3 128 bytes H'0200 LB0 4 kbytes H'1FFF H'2000 SB4 512 bytes H'03FF H'0400 LB1 8 kbytes H'3FFF H'4000 SB5 1 kbyte H'07FF H'0800 LB2 8 kbytes H'5FFF H'6000 SB6 1 kbyte H'0BFF H'0C00 SB7 1 kbyte LB3 8 kbytes H'7FFF H'8000 H'0FFF LB4 8 kbytes H'9FFF H'A000 LB5 8 kbytes H'BFFF H'C000 LB6 12 kbytes H'EF7F H'EF80 H'F77F LB7 2 kbytes Figure 20.2 Erase Block Map 446 Table 20.6 Erase Blocks and Corresponding Bits Register Bit Block Address Size EBR1 0 LB0 H'1000 to H'1FFF 4 kbytes 1 LB1 H'2000 to H'3FFF 8 kbytes 2 LB2 H'4000 to H'5FFF 8 kbytes 3 LB3 H'6000 to H'7FFF 8 kbytes 4 LB4 H'8000 to H'9FFF 8 kbytes 5 LB5 H'A000 to H'BFFF 8 kbytes 6 LB6 H'C000 to H'EF7F 12 kbytes 7 LB7 H'EF80 to H'F77F 2 kbytes 0 SB0 H'0000 to H'007F 128 bytes 1 SB1 H'0080 to H'00FF 128 bytes 2 SB2 H'0100 to H'017F 128 bytes 3 SB3 H'0180 to H'01FF 128 bytes 4 SB4 H'0200 to H'03FF 512 bytes 5 SB5 H'0400 to H'07FF 1 kbyte 6 SB6 H'0800 to H'0BFF 1 kbyte 7 SB7 H'0C00 to H'0FFF 1 kbyte EBR2 20.3 On-Board Programming Modes When an on-board programming mode is selected, the on-chip flash memory can be programmed, erased, and verified. There are two on-board programming modes: boot mode, and user programming mode. These modes are selected by inputs at the mode pins (MD1 and MD 0) and FVPP pin. Table 20.7 indicates how to select the on-board programming modes. For details on applying voltage V PP , refer to section 20.7, Flash Memory Programming and Erasing Precautions (5). 447 Table 20.7 On-Board Programming Mode Selection Mode Selections Boot mode FV PP MD1 MD0 Notes 12 V* 12 V* 0 0: VIL Mode 3 12 V* 1 1: VIH Mode 2 1 0 Mode 3 1 1 Mode 2 User programming mode Note: * For details on the timing of 12 V application, see notes 6 to 8 in the Notes on Use of Boot Mode at the end of this section. In boot mode, the mode control register (MDCR) can be used to monitor the mode (mode 2 or 3) in the same way as in normal mode. Example: Set the mode pins for mode 2 boot mode (MD 1 = 12 V, MD0 = 0 V). If the mode select bits of MDCR are now read, they will indicate mode 2 (MDS1 = 1, MDS0 = 0). 20.3.1 Boot Mode To use boot mode, a user program for programming and erasing the flash memory must be provided in advance on the host machine (which may be a personal computer). Serial communication interface channel 1 is used in asynchronous mode. If the H8/3437F is placed in boot mode, after it comes out of reset, a built-in boot program is activated. This program starts by measuring the low period of data transmitted from the host and setting the bit rate register (BRR) accordingly. The H8/3437F's built-in serial communication interface (SCI) can then be used to download the user program from the host machine. The user program is stored in on-chip RAM. After the program has been stored, execution branches to address H'F7E0 in the on-chip RAM, and the program stored on RAM is executed to program and erase the flash memory. H8/3437F Receive data to be programmed HOST Transmit verification data RxD1 SCI TxD1 Figure 20.3 Boot-Mode System Configuration 448 Boot-Mode Execution Procedure: Figure 20.4 shows the boot-mode execution procedure. Start 1. Program the H8/3437F pins for boot mode, and start the H8/3437F from a reset. 1 Program H8/3437F pins for boot mode, and reset 2. Set the host's data format to 8 bits + 1 stop bit, select the desired bit rate (2400, 4800, or 9600 bps), and transmit H'00 data continuously. 2 Host transmits H'00 data continuously at desired bit rate 3 H8/3437F measures low period of H'00 data transmitted from host H8/3437F computes bit rate and sets bit rate register 4 After completing bit-rate alignment, H8/3437F sends one H'00 data byte to host to indicate that alignment is completed 5 Host checks that this byte, indicating completion of bit-rate alignment, is received normally, then transmits one H'55 byte 6 After receiving H'55, H8/3437F sends part of the boot program to RAM H8/3437F branches to the RAM boot area (H'F800 to H'FF2F), then checks the data in the user area of flash memory 7 All data = H'FF?*4 Yes No Erase all flash memory blocks*3, *4 After checking that all data in flash memory is H'FF, H8/3437F transmits one H'AA data byte to host 8 H8/3437F receives two bytes indicating byte length (N) of program to be downloaded to on-chip RAM*1 H8/3437F transfers one user program byte to RAM*2 9 H8/3437F calculates number of bytes left to be transferred (N = N - 1) All bytes transferred? (N = 0?) No Yes After transferring the user program to RAM, H8/3437F transmits one H'AA data byte to host 10 H8/3437F branches to H'F7E0 in RAM area and executes user program downloaded into RAM 3. The H8/3437F repeatedly measures the low period of the RxD1 pin and calculates the host's asynchronouscommunication bit rate. 4. When SCI bit-rate alignment is completed, the H8/3437F transmits one H'00 data byte to indicate completion of alignment. 5. The host should receive the byte transmitted from the H8/3437F to indicate that bit-rate alignment is completed, check that this byte is received normally, then transmit one H'55 byte. 6. After receiving H'55, H8/3437F sends part of the boot program to H'F780 to H'F7DF and H'F800 to H'FF2F of RAM. 7. After branching to the boot program area (H'F800 to H'FF2F) in RAM, the H8/3437F checks whether the flash memory already contains any programmed data. If so, all blocks are erased. 8. After the H8/3437F transmits one H'AA data byte, the host transmits the byte length of the user program to be transferred to the H8/3437F. The byte length must be sent as two-byte data, upper byte first and lower byte second. After that, the host proceeds to transmit the user program. As verification, the H8/3437F echoes each byte of the received byte-length data and user program back to the host. 9. The H8/3437F stores the received user program in on-chip RAM in a 1934-byte area from H'F7E0 to H'FF6D. 10. After transmitting one H'AA data byte, the H8/3437F branches to address H'F7E0 in on-chip RAM and executes the user program stored in the area from H'F7E0 to H'FF6D. Notes: *1 The user can use 1934 bytes of RAM. The number of bytes transferred must not exceed 1934 bytes. Be sure to transmit the byte length in two bytes, upper byte first and lower byte second. For example, if the byte length of the program to be transferred is 256 bytes (H'0100), transmit H'01 as the upper byte, followed by H'00 as the lower byte. *2 The part of the user program that controls the flash memory should be coded according to the flash memory write/erase algorithms given later. *3 If a memory cell malfunctions and cannot be erased, the H8/3437F transmits one H'FF byte to report an erase error, halts erasing, and halts further operations. *4 H'0000 to H'EF7F in mode 2 and H'0000 to H'F77F in mode 3. Figure 20.4 Boot Mode Flowchart 449 Automatic Alignment of SCI Bit Rate Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit This low period (9 bits) is measured (H'00 data) High for at least 1 bit Figure 20.5 Measurement of Low Period in Data Transmitted from Host When started in boot mode, the H8/3437F measures the low period in asynchronous SCI data transmitted from the host (figure 20.5). The data format is eight data bits, one stop bit, and no parity bit. From the measured low period (9 bits), the H8/3437F computes the host's bit rate. After aligning its own bit rate, the H8/3437F sends the host 1 byte of H'00 data to indicate that bit-rate alignment is completed. The host should check that this alignment-completed indication is received normally and send one byte of H'55 back to the H8/3437F. If the alignment-completed indication is not received normally, the H8/3437F should be reset, then restarted in boot mode to measure the low period again. There may be some alignment error between the host's and H8/3437F's bit rates, depending on the host's bit rate and the H8/3437F's system clock frequency. To have the SCI operate normally, set the host's bit rate to 2400, 4800, or 9600 bps *1. Table 20.8 lists typical host bit rates and indicates the clock-frequency ranges over which the H8/3437F can align its bit rate automatically. Boot mode should be used within these frequency ranges*2. Table 20.8 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by H8/3437F Host Bit Rate*1 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by H8/3437F 9600 bps 8 MHz to 16 MHz 4800 bps 4 MHz to 16 MHz 2400 bps 2 MHz to 16 MHz Notes: *1 Use a host bit rate setting of 2400, 4800, or 9600 bps only. No other setting should be used. *2 Although the H8/3437F may also perform automatic bit-rate alignment with bit rate and system clock combinations other than those shown in table 20.8, there will be a slight difference between the bit rates of the host and the H8/3437F, and subsequent transfer will not be performed normally. Therefore, only a combination of bit rate and system clock frequency within one of the ranges shown in table 20.8 can be used for boot mode execution. 450 RAM Area Allocation in Boot Mode: In boot mode, the 96 bytes from H'F780 to H'F7DF and the 18 bytes from H'FF6E to H'FF7F are reserved for use by the boot program, as shown in figure 20.6. The user program is transferred into the area from H'F7E0 to H'FF6D (1934 bytes). The boot program area can be used after the transition to execution of the user program transferred into RAM. If a stack area is needed, set it within the user program. H'F780 Boot program area* (96 bytes) H'F7E0 User program transfer area (1934 bytes) H'FF6E H'FF7F Boot program area* (18 bytes) Note: * This area cannot be used until the H8/3437F starts to execute the user program transferred to RAM (until it has branched to H'F7E0 in RAM). Note that even after the branch to the user program, the boot program area (H'F780 to H'F7DF, H'FF6E to H'FF7F) still contains the boot program. Note also that 16 bytes (H'F780 to H'F78F) of this area cannot be used if an interrupt handling routine is executed within the boot program. For details see section 20.4.9, Interrupt Handling during Flash Memory Programming and Erasing. Figure 20.6 RAM Areas in Boot Mode 451 Notes on Use of Boot Mode 1. When the H8/3437F comes out of reset in boot mode, it measures the low period of the input at the SCI's RxD1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100 states for the H8/3437F to get ready to measure the low period of the RxD 1 input. 2. In boot mode, if any data has been programmed into the flash memory (if all data*3 is not H'FF), all flash memory blocks are erased. Boot mode is for use when user programming mode is unavailable, e.g. the first time on-board programming is performed, or if the update program activated in user programming mode is accidentally erased. 3. Interrupts cannot be used while the flash memory is being programmed or erased. 4. The RxD1 and TxD1 pins should be pulled up on-board. 5. Before branching to the user program (at address H'F7E0 in the RAM area), the H8/3437F terminates transmit and receive operations by the on-chip SCI (by clearing the RE and TE bits of the serial control register to 0 in channel 1), but the auto-aligned bit rate remains set in bit rate register BRR. The transmit data output pin (TxD1) is in the high output state (in port 8, the bits P8 4 DDR of the port 8 data direction register and P84 DR of the port 8 data register are set to 1). At this time, the values of general registers in the CPU are undetermined. Thus these registers should be initialized immediately after branching to the user program. Especially in the case of the stack pointer, which is used implicitly in subroutine calls, the stack area used by the user program should be specified. There are no other changes to the initialized values of other registers. 6. Boot mode can be entered by starting from a reset after 12 V is applied to the MD1 and FVPP pins according to the mode setting conditions listed in table 20.7. Note the following points when turning the VPP power on. When reset is released (at the rise from low to high), the H8/3437F checks for 12-V input at the MD1 and FVPP pins. If it detects that these pins are programmed for boot mode, it saves that status internally. The threshold point of this voltage-level check is in the range from approximately VCC + 2 V to 11.4 V, so boot mode will be entered even if the applied voltage is insufficient for programming or erasure (11.4 V to 12.6 V). When the boot program is executed, the VPP power supply must therefore be stabilized within the range of 11.4 V to 12.6 V before the branch to the RAM area occurs. See figure 20.20. Make sure that the programming voltage VPP does not exceed 12.6 V during the transition to boot mode (at the reset release timing) and does not go outside the range of 12 V 0.6 V while in boot mode. Boot mode will not be executed correctly if these limits are exceeded. In 452 addition, make sure that VPP is not released or shut off while the boot program is executing or the flash memory is being programmed or erased.*1 Boot mode can be released by driving the reset pin low, waiting at least ten system clock cycles, then releasing the application of 12 V to the MD1 and FVPP pins and releasing the reset. The settings of external pins must not change during operation in boot mode. During boot mode, if input of 12 V to the MD1 pin stops but no reset input occurs at the RES pin, the boot mode state is maintained within the chip and boot mode continues (but do not stop applying 12 V to the FV PP pin during boot mode*1). If a watchdog timer reset occurs during boot mode, this does not release the internal mode state, but the internal boot program is restarted. Therefore, to change from boot mode to another mode, the boot-mode state within the chip must be released by a reset input at the RES pin before the mode transition can take place. 7. If the input level of the MD 1 pin is changed during a reset (e.g., from 0 V to 5 V then to 12 V while the input to the RES pin is low), the resultant switch in the microcontroller's operating mode will affect the bus control output signals (AS, RD, and WR) and the status of ports that can be used for address output*2. Threfore, either set these pins so that they do not output signals during the reset, or make sure that their output signals do not collide with other signals outside the microcontroller. 8. When applying 12 V to the MD1 and FVPP pins, make sure that peak overshoot does not exceed the rated limit of 13 V. Also, b sure to connect a decoupling capacitor to the FVPP and MD 1 pins. Note: *1 For details on applying, releasing, and shutting off V PP , see note (5) in section 20.7, Flash Memory Programming and Erasing Precautions. *2 These ports output low-level address signals if the mode pins are set to mode 1 during the reset. In all other modes, these ports are in the high-impedance state. The bus control output signals are high if the mode pins are set for mode 1 or 2 during the reset. In mode 3, they are at high impedance. *3 H'0000 to H'EF7F in mode 2 and H'0000 to H'F77F in mode 3. 453 20.3.2 User Programming Mode When set to user programming mode, the H8/3437F can erase and program its flash memory by executing a user program. On-board updates of the on-chip flash memory can be carried out by providing on-board circuits for supplying VPP and data, and storing an update program in part of the program area. To select user programming mode, select a mode that enables the on-chip ROM (mode 2 or 3) and apply 12 V to the FVPP pin, either during a reset, or after the reset has ended (been released) but while flash memory is not being accessed. In user programming mode, the on-chip supporting modules operate as they normally would in mode 2 or 3, except for the flash memory. However, hardware standby mode cannot be set while 12 V is applied to the FV PP pin. The flash memory cannot be read while it is being programmed or erased, so the update program must either be stored in external memory, or transferred temporarily to the RAM area and executed in RAM. 454 User Programming Mode Execution Procedure (Example)*: Figure 20.7 shows the execution procedure for user programming mode when the on-board update routine is executed in RAM. Note: * Do not apply 12 V to the FVPP pin during normal operation. To prevent flash memory from being accidentally programmed or erased due to program runaway etc., apply 12 V to FVPP only when programming or erasing flash memory. Overprogramming or overerasing due to program runaway can cause memory cells to malfunction. While 12 V is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing. For details on applying, releasing, and shutting off VPP, see section 20.7, Flash Memory Programming and Erasing Precautions (5). 1 Set MD1 and MD0 to 10 or 11 (apply VIH to VCC to MD1) Start from reset 2 Branch to flash memory on-board update program 3 Transfer on-board update routine into RAM 4 Branch to flash memory on-board update routine in RAM 5 FVPP = 12 V (user programming mode) 6 Execute flash memory on-board update routine in RAM (update flash memory) 7 Release FVPP (exit user programming mode) 8 Branch to application program in flash memory* Procedure The flash memory on-board update program is written in flash memory ahead of time by the user. 1. Set MD1 and MD0 of the H8/3437F to 10 or 11, and start from a reset. 2. Branch to the flash memory on-board update program in flash memory. 3. Transfer the on-board update routine into RAM. 4. Branch to the on-board update routine that was transferred into RAM. 5. Apply 12 V to the FVPP pin, to enter user programming mode. 6. Execute the flash memory on-board update routine in RAM, to perform an on-board update of the flash memory. 7. Change the voltage at the FVPP pin from 12 V to VCC, to exit user programming mode. 8. After the on-board update of flash memory ends, execution branches to an application program in flash memory. Note: * After the update is finished, when input of 12 V to the FVPP pin is released, the flash memory read setup time (tFRS) must elapse before any program in flash memory is executed. This is the required setup time from when the FVPP pin reaches the (VCC + 2 V) level after 12 V is released until flash memory can be read. Figure 20.7 User Programming Mode Operation (Example) 455 20.4 Programming and Erasing Flash Memory The H8/3437F's on-chip flash memory is programmed and erased by software, using the CPU. The flash memory can operate in program mode, erase mode, program-verify mode, erase-verify mode, or prewrite-verify mode. Transitions to these modes can be made by setting the P, E, PV, and EV bits in the flash memory control register (FLMCR). The flash memory cannot be read while being programmed or erased. The program that controls the programming and erasing of the flash memory must be stored and executed in on-chip RAM or in external memory. A description of each mode is given below, with recommended flowcharts and sample programs for programming and erasing. For details on programming and erasing, refer to section 20.7, Flash Memory Programming and Erasing Precautions. 20.4.1 Program Mode To write data into the flash memory, follow the programming algorithm shown in figure 20.8. This programming algorithm can write data without subjecting the device to voltage stress or impairing the reliability of programmed data. To program data, first specify the area to be written in flash memory with erase block registers EBR1 and EBR2, then write the data to the address to be programmed, as in writing to RAM. The flash memory latches the address and data in an address latch and data latch. Next set the P bit in FLMCR, selecting program mode. The programming duration is the time during which the P bit is set. The total programming time does not exceed 1 ms. Programming for too long a time, due to program runaway for example, can cause device damage. Before selecting program mode, set up the watchdog timer so as to prevent overprogramming. For details of the programming method, refer to section 20.4.3, Programming Flowchart and Sample Programs. 456 20.4.2 Program-Verify Mode In program-verify mode, after data has been programmed in program mode, the data is read to check that it has been programmed correctly. After the programming time has elapsed, exit programming mode (clear the P bit to 0) and select program-verify mode (set the PV bit to 1). In program-verify mode, a program-verify voltage is applied to the memory cells at the latched address. If the flash memory is read in this state, the data at the latched address will be read. After selecting program-verify mode, wait 4 s or more before reading, then compare the programmed data with the verify data. If they agree, exit program-verify mode and program the next address. If they do not agree, select program mode again and repeat the same program and program-verify sequence. Do not repeat the program and program-verify sequence more than 6 times* for the same bit. Note: * Keep the total programming time under 1 ms for each bit. 457 20.4.3 Programming Flowchart and Sample Program Flowchart for Programming One Byte Start Set erase block register (set bit of block to be programmed to 1) Write data to flash memory (flash memory latches write address and data)*1 n=1 Enable watchdog timer*2 Select program mode (P bit = 1 in FLMCR) Wait (x) s*4 Clear P bit End of programming Disable watchdog timer Select program-verify mode (PV bit = 1 in FLMCR) Wait (tvs1) s*5 Notes: *1 Write the data to be programmed with a byte transfer instruction. *2 Set the timer overflow interval as follows. CKS2 = 0, CKS1 = 0, CKS0 = 1 *3 Read the memory data to be verified with a byte transfer instruction. *4 Programming time x, which is determined by the initial time x 2n-1 (n = 1, 2, 3, 4, 5, 6), increases in proportion to n. Thus, set the initial time to 15.8 s or less to make total programming time 1 ms or less. *5 tVS1: 4 s or more N: 6 (set N so that total programming time does not exceed 1 ms) No go Verify*3 (read memory) OK Clear PV bit Clear PV bit End of verification Clear erase block register (clear bit of programmed block to 0) End (1-byte data programmed) n N?*5 No n+1n Yes Programming error Figure 20.8 Programming Flowchart 458 Double programming time (x x 2x) Sample Program for Programming One Byte: This program uses the following registers. R0H: R1H: R1L: R3: Specifies blocks to be erased. Stores data to be programmed. Stores data to be read. Stores address to be programmed. Valid address specifications are H'0000 to H'EF7F in mode 2, and H'0000 to H'F77F in mode 3. R4: Sets program and program-verify timing loop counters, and also stores register setting value. R5: Sets program timing loop counter. R6L: Used for program-verify fail count. Arbitrary data can be programmed at an arbitrary address by setting the address in R3 and the data in R1H. The setting of #a and #b values depends on the clock frequency. Set #a and #b values according to tables 20.9 (1) and (2). FLMCR: EBR1: EBR2: TCSR: .EQU .EQU .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFA8 PRGM: .ALIGN MOV.B MOV.B 2 #H'**, R0H, MOV.B MOV.W MOV.B INC MOV.W MOV.W MOV.W BSET SUBS MOV.W BNE BCLR MOV.W MOV.W #H'00, #H'a, R1H, R6L #H'A579, R4, R5, #0, #1, R4, LOOP1 #0, #H'A500, R4, R6L R5 @R3 MOV.B BSET DEC BNE MOV.B CMP.B BEQ BCLR #H'b , #2, R4H LOOP2 @R3, R1H, PVOK #2, R4H ; Set program-verify loop counter @FLMCR:8 ; Set PV bit PRGMS: LOOP1: LOOP2: R0H ; @EBR*:8 ; Set EBR * ; ; ; ; ; ; ; Program-verify fail counter Set program loop counter Dummy write Program-verify fail counter + 1 R6L R4 @TCSR Start watchdog timer R4 Set program loop counter @FLMCR:8 ; Set P bit R4 ; R4 ; ; Wait loop @FLMCR:8 ; Clear P bit R4 ; @TCSR ; Stop watchdog timer ; ; ; ; ; Wait loop Read programmed address Compare programmed data with read data Program-verify decision @FLMCR:8 ; Clear PV bit R1L R1L 459 PVOK: ; ; ; ; Program-verify executed 6 times? If program-verify executed 6 times, branch to NGEND Programming time x 2 Program again CMP.B BEQ ADD.W BRA #H'06, NGEND R5, PRGMS R6L BCLR MOV.B MOV.B #2, #H'00, R6L, @FLMCR:8 R6L ; @EBR*:8 ; R5 ; Clear PV bit Clear EBR* One byte programmed NGEND: 20.4.4 Programming error Erase Mode To erase the flash memory, follow the erasing algorithm shown in figure 20.9. This erasing algorithm can erase data without subjecting the device to voltage stress or impairing the reliability of programmed data. To erase flash memory, before starting to erase, first place all memory data in all blocks to be erased in the programmed state (program all memory data to H'00). If all memory data is not in the programmed state, follow the sequence described later to program the memory data to zero. Select the flash memory areas to be erased with erase block registers 1 and 2 (EBR1 and EBR2). Next set the E bit in FLMCR, selecting erase mode. The erase time is the time during which the E bit is set. To prevent overerasing, use a software timer to divide the time for a single erase, and ensure that the total time does not exceed 30 seconds. For the time for a single erase, refer to section 20.4.6, Erase Flowchart and Sample Programs. Overerasing, due to program runaway for example, can give memory cells a negative threshold voltage and cause them to operate incorrectly. Before selecting erase mode, set up the watchdog timer so as to prevent overerasing. 20.4.5 Erase-Verify Mode In erase-verify mode, after data has been erased, it is read to check that it has been erased correctly. After the erase time has elapsed, exit erase mode (clear the E bit to 0) and select eraseverify mode (set the EV bit to 1). Before reading data in erase-verify mode, write H'FF dummy data to the address to be read. This dummy write applies an erase-verify voltage to the memory cells at the latched address. If the flash memory is read in this state, the data at the latched address will be read. After the dummy write, wait 2 s or more before reading. When performing the initial dummy write, wait 4 s or more after selecting erase-verify mode. If the read data has been successfully erased, perform an erase-verify (dummy write, wait 2 s or more, then read) for the next address. If the read data has not been erased, select erase mode again and repeat the same erase and erase-verify sequence through the last address, until all memory data has been erased to 1. Do not repeat the erase and erase-verify sequence more than 602 times, however. 460 20.4.6 Erasing Flowchart and Sample Program Flowchart for Erasing One Block Start Set erase block register (set bit of block to be erased to 1) Write 0 data in all addresses to be erased (prewrite)*1 n=1 Enable watchdog timer*2 Select erase mode (E bit = 1 in FLMCR) Wait (x) ms*5 Clear E bit Erasing ends Disable watchdog timer Set top address in block as verify address Select erase-verify mode (EV bit = 1 in FLMCR) Wait (tvs1) s*6 Dummy write to verify address*3 (flash memory latches address) Wait (tvs2) s*6 Address + 1 address Verify*4 (read data=H'FF?) OK No Notes: *1 Program all addresses to be erased by following the prewrite flowchart. *2 Set the watchdog timer overflow interval to the value indicated in table 20.10. *3 For the erase-verify dummy write, write H'FF with a byte transfer instruction. *4 Read the data to be verified with a byte transfer instruction. When erasing two or more blocks, clear the bits of erased blocks in the erase block registers, so that only unerased blocks will be erased again. *5 The erase time x is successively incremented by the initial set value x 2n-1 (n = 1, 2, 3, 4). After fourth erasing, the erase time is fixed. An initial value of 6.25 ms or less should be set, and the time for one erasure should be 50 ms or less. *6 tVS1: 4 s or more tVS2: 2 s or more N: 602 (Set N so that total erase time does not exceed 30s.) No go Clear EV bit Last address? Yes n N?*6 Clear EV bit Yes Clear erase block register (clear bit of erased block to 0) End of block erase Erase-verify ends No n+1n n > 4? Erase error Yes No Double erase time (x x 2x) Figure 20.9 Erasing Flowchart 461 Prewrite Flowchart Start Set erase block register (set bit block to be programmed to 1) Set start address*6 n=1 Write H'00 to flash memory (flash memory latches write address and write data)*1 Enable watchdog timer*2 Select program mode (P bit = 1 in FLMCR) Wait (x) s*4 Clear P bit Disable watchdog timer Wait (tvs1) s*5 Prewrite verify*3 (read data = H'00?) Notes: *1 Use a byte transfer instruction. *2 Set the timer overflow interval as follows. CKS2 = 0, CKS1 = 0, CKS0 = 1 *3 In prewrite-verify mode P, E, PV, and EV are all cleared to 0 and 12 V is applied to FVPP. Read the data with a byte transfer instruction. *4 Programming time x, which is determined by the inital time x 2n-1 (n = 1, 2, 3, 4, 5, 6), increases in proportion to n. Thus, set the initial time to 15.8 s or less to make total End of programming time 1 ms or less. programming *5 tVS1: 4 s or more N: 6 (set N so that total programming time does not exceed 1 ms) *6 Start and last addresses shall be top and last addresses of the block to be erased. No go n N?*5 No n+1n OK Yes Double programming time (x x 2x) Programming error Last address?*6 No Yes Clear erase block register (clear bit of programmed block to 0) End of prewrite Figure 20.10 Prewrite Flowchart 462 Address + 1Address Sample Block-Erase Program: This program uses the following registers. R0: R1H: R2: R3: R4: Specifies block to be erased, and also stores address used in prewrite and erase-verify. Stores data to be read, and also used for dummy write. Stores last address of block to be erased. Stores address used in prewrite and erase-verify. Sets timing loop counters for prewrite, prewrite-verify, erase, and erase-verify, and also stores register setting value. R5: Sets prewrite and erase timing loop counters. R6L: Used for prewrite-verify and erase-verify fail count. The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a, #b, #c, #d, and #e values according tables 20.9 (1) and (2), and 20.10. Erase block registers (EBR1 and EBR2) should be set according to sections 20.2.2 and 20.2.3. #BLKSTR and #BLKEND are the top and last addresses of the block to be erased. Set #BLKSTR and #BLKEND according to figure 20.2. 463 FLMCR: EBR1: EBR2: TCSR: .EQU .EQU .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFA8 .ALIGN MOV.B MOV.B 2 #H'**, ROH, ROH ; @EBR*:8 ; Set EBR* ; #BLKSTR is top address of block to be erased. ; #BLKEND is last address of block to be erased. #BLKSTR, #BLKEND, #1, R0 R2 R2 ; Top address of block to be erased ; Last address of block to be erased ; Last address of block to be erased + 1 R2 MOV.W MOV.B MOV.W INC MOV.B MOV.B MOV.W MOV.W MOV.W BSET SUBS MOV.W BNE BCLR MOV.W MOV.W R0, #H'00, #H'a, R6L #H'00 R1H, #H'A579, R4, R5, #0, #1, R4, LOOPR1 #0, #H'A500, R4, R3 R6L R5 ; ; ; ; ; ; ; ; ; MOV.B DEC BNE MOV.B BEQ CMP.B BEQ ADD.W BRA #H'c, R4H LOOPR2 @R3, PWVFOK #H'06, ABEND1 R5 PREWRS R4H MOV.W MOV.W ADDS ; Execute prewrite PREWRT: PREWRS: LOOPR1: LOOPR2: ABEND1: Programming error PWVFOK: ADDS CMP.W BNE ;Execute erase ERASES: MOV.W MOV.W 464 R1H @R3 R4 @TCSR R4 @FLMCR:8 R4 ; R4 ; Top address of block to be erased Prewrite-verify fail counter Set prewrite loop counter Prewrite-verify fail counter + 1 R6L Write H'00 Start watchdog timer Set prewrite loop counter ; Set P bit ; Wait loop @FLMCR:8 ; Clear P bit R4 ; @TCSR ; Stop watchdog timer R1H R6L R5 ; ; ; ; ; ; ; ; ; Set prewrite-verify loop counter Wait loop Read data = H'00? If read data = H'00 branch to PWVFOK Prewrite-verify executed 6 times? If prewrite-verify executed 6 times, branch to ABEND1 Programming time x 2 Prewrite again #1, R2, PREWRT R3 R3 ; Address + 1 R3 ; Last address? ; If not last address, prewrite next address #H'0000, #H'd, R6 R5 ; Erase-verify fail counter ; Set erase loop count ERASE: LOOPE: Erase-verify fail counter + 1 R6 #1, #H'e, R4, R5, #1, R6 ; R4 ; @TCSR ; R4 ; @FLMCR:8 #1, R4, LOOPE #1, #H'A500, R4, R4 R4 MOV.W MOV.B BSET DEC BNE MOV.B MOV.B MOV.B DEC BNE MOV.B CMP.B BNE CMP.W BNE BRA R0, #H'b, #3, R4H LOOPEV #H'FF, R1H, #H'c, R4H LOOPDW @R3+, #H'FF, RERASE R2, EVR2 OKEND R3 ; Top address of block to be erased R4H ; Set erase-verify loop counter @FLMCR:8 ; Set EV bit BCLR SUBS #3, #1, @FLMCR:8 ; Clear EV bit R3 ; Erase-verify address - 1 R3 MOV.W CMP.W BPL ADD.W MOV.W CMP.W BNE BRA #H'0004, R4 BRER R5, #H'025A, R4, ERASE ABEND2 R4 R6 BCLR MOV.B MOV.B #3, #H'00, R6L, @FLMCR:8 ; Clear EV bit R6L ; @EBR*:8 ; Clear EBR* ADDS MOV.W MOV.W MOV.W BSET NOP NOP NOP NOP SUBS MOV.W BNE BCLR MOV.W MOV.W Start watchdog timer Set erase loop counter ; Set E bit ; ; ; Wait loop @FLMCR:8 ; Clear E bit R4 ; @TCSR ; Stop watchdog timer ; Execute erase-verify LOOPEV: EVR2: LOOPDW: RERASE: BRER: OKEND: R1H @R3 R4H R1H R1H R3 R5 R4 R6 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Wait loop Dummy write Set erase-verify loop counter Wait loop Read Read data = H'FF? If read data H'FF, branch to RERASE Last address of block? Erase-verify fail count executed 4 times? If R64, branch to BRER (branch until R6 is 4 to 602) If R6<4, Erase time x 2 (execute when R6 is 1, 2, or 3) Erase-verify executed 602 times? If erase-verify not executed 602 times, erase again If erase-verify executed 602 times, branch to ABEND2 One block erased ABEND2: Erase error 465 Flowchart for Erasing Multiple Blocks Start Set erase block registers (set bits of block to be erased to 1) Write 0 data to all addresses to be erased (prewrite)*1 n=1 Enable watchdog timer*2 Select erase mode (E bit = 1 in FLMCR) Wait (x)ms*5 Erasing ends Clear E bit Disable watchdog timer Select erase-verify mode (EV bit = 1 in FLMCR) Notes: *1 Program all addresses to be erased by following the prewrite flowchart. *2 Set the watchdog timer overflow interval to the value indicated in table 20.10. *3 For the erase-verify dummy write, write H'FF with a byte transfer instruction. *4 Read the data to be verified with a byte transfer instruction. When erasing two or more blocks, clear the bits of erased blocks in the erase block register, so that only unerased blocks will be erased again. *5 The erase time x is successively incremented by the initial set value x 2n-1 (n = 1, 2, 3, 4). After fourth erasing, the erase time is fixed. An initial value of 6.25 ms or less should be set, and the time for one erasure should be 50 ms or less. *6 tVS1: 4 s or more tVS2: 2 s or more N: 602 (Set N so that total erase time does not exceed 30s.) Wait (tvs1) s*6 Erase-verify next block Set top address of block as verify address Dummy write to verify address *3 (flash memory latches address) Wait (tvs2) s*6 Verify*4 (read data = H'FF?) Address + 1 Address Erase-verify next block No go OK No Last address in block? Yes All erased blocks verified? No Yes Clear EBR bit of erased block No All erased blocks verified? Yes n 4? Clear EV bit All blocks erased? (EBR1 = EBR2 = 0?) Yes End of erase No Double Erase time (x x 2x) No n N?*6 Yes Erase error Figure 20.11 Multiple-Block Erase Flowchart 466 Yes No n+1n Sample Multiple-Block Erase Program: This program uses the following registers. R0: Specifies blocks to be erased (set as explained below), and also stores address used in prewrite and erase-verify. R1H: Used to test bits 8 to 15 of R0 stores register read data, and also used for dummy write. R1L: Used to test bits 0 to 15 of R0. R2: Specifies address where address used in prewrite and erase-verify is stored. R3: Stores address used in prewrite and erase-verify. R4: Stores last address of block to be erased. R5: Sets prewrite and erase timing loop counters. R6L: Used for prewrite-verify and erase-verify fail count. Arbitrary blocks can be erased by setting bits in R0. Write R0 with a word transfer instruction. A bit map of R0 and a sample setting for erasing specific blocks are shown next. Bit R0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Corresponds to EBR1 Corresponds to EBR2 Example: to erase blocks LB2, SB7, and SB0 Bit R0 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Corresponds to EBR1 Setting 5 0 0 0 0 0 1 Corresponds to EBR2 0 0 1 0 0 0 0 0 0 1 R0 is set as follows: MOV.W MOV.W #H'0481,R0 R0, @EBR1 The setting of #a, #b, #c, #d, and #e values in the program depends on the clock frequency. Set #a, #b, #c, #d, and #e values according to tables 20.9 (1), (2), and 20.10. 467 Notes: 1. In this sample program, the stack pointer (SP) is set at address FF80. As the stack area, on-chip RAM addresses FF7E and FF7F are used. Therefore, when executing this sample program, addresses FF7E and FF7F should not be used. In addition, the on-chip RAM should not be disabled. 2. In this sample program, the program written in a ROM area (including external space) is transferred into the RAM area and executed in the RAM to which the program is transferred. #RAMSTR in the program is the starting destination address in RAM to which the program is transferred. #RAMSTR must be set to an even number. 3. When executing this sample program in the on-chip ROM area or external space, #RAMSTR should be set to #START. FLMCR: EBR1: EBR2: TCSR: STACK: .RQU .EQU .EQU .EQU .EQU H'FF80 H'FF82 H'FF83 H'FFA8 H'FF80 .ALIGN MOV.W 2 #STACK, SP ; Set stack pointer ; Set the bits in R0 following the description on the previous page. This program is a sample program to erase ; all blocks. MOV.W #H'FFFF, R0 ; Select blocks to be erased (R0: EBR1/EBR2) MOV.W R0, @EBR1 ; Set EBR1/EBR2 START: ; #RAMSTR is starting destination address to which program is transferred in RAM. ; Set #RAMSTR to even number. MOV.W #RAMSTR, R2 ; Starting transfer destination address (RAM) MOV.W #ERVADR, R3 ; ADD.W R3, R2 ; #RAMSTR + #ERVADR R2 MOV.W #START, R3 ; SUB.W R3, R2 ; Address of data area used in RAM PRETST: EBR2PW: PWADD1: 468 MOV.B CMP.B BEQ CMP.B BMI MOV.B SUBX BTST BNE BRA BTST BNE INC MOV.W BRA #H'00, #H'10, ERASES #H'08, EBR2PW R1L, #H'08, R1H, PREWRT PWADD1 R1L, PREWRT R1L @R2+, PRETST R1L R1L R1L R1H R1H R0H R0L R3 : ; ; ; ; ; ; ; ; ; ; ; ; ; ; Used to test R1L bit in R0 R1L = H'10? If finished checking all R0 bits, branch to ERASES Test EBR1 if R1L 8, or EBR2 if R1L < 8 R1L - 8 R1H Test R1H bit in EBR1 (R0H) If R1H bit in EBR1 (R0H) is 1, branch to PREWRT If R1H bit in EBR1 (R0H) is 0, branch to PWADD1 Test R1L bit in EBR2 (R0L) If R1L bit in EBR2 (R0H) is 1, branch to PREWRT R1L + 1 R1L Dummy-increment R2 ; Execute prewrite PREWRT: PREW: PREWRS: LOOPR1: LOOPR2: @R2+, #H'00, #H'a, R6L #H'00 R1H, #H'A579, R4, R5, #0, #1, R4, LOOPR1 #0, #H'A500, R4, R3 R6L R5 MOV.B DEC BNE MOV.B BEQ CMP.B BEQ ADD.W BRA #H'c, R4H LOOPR2 @R3, PWVFOK #H'06, ABEND1 R5, PREWRS R4H ABEND1: Programming error PWVFOK: ADDS MOV.W CMP.W BNE INC BRA PWADD2: ; ; ; ; R1H ; @R3 ; R4 ; @TCSR ; R4 ; MOV.W MOV.B MOV.W INC MOV.B MOV.B MOV.W MOV.W MOV.W BSET SUBS MOV.W BNE BCLR MOV.W MOV.W Prewrite starting address Prewrite-verify fail counter Prewrite-verify loop counter Prewrite-verify fail counter + 1 R6L Write H'00 Start watchdog timer Set prewrite loop counter @FLMCR:8 ; Set P bit R4 ; R4 ; ; Wait loop @FLMCR:8 ; Clear P bit R4 ; @TCSR ; Stop watchdog timer R1H R6L R5 ; ; ; ; ; ; ; ; ; Set prewrite-verify loop counter ; ; ; ; ; ; Address + 1 R3 Top address of next block Last address? If not last address, prewrite next address Used to test R1L+1 bit in R0 Branch to PRETST Wait loop Read data = H'00? If read data = H'00 branch to PWVFOK Prewrite-verify executed 6 times? If prewrite-verify executed 6 times, branch to ABEND1 Programming time x 2 Prewrite again #1, @R2, R4, PREW R1L PRETST R3 R4 R3 #H'0000, #H'd, #1, #H'e, R4, R5, #1, R6 ; Erase-verify fail counter R5 ; Set erase loop count R6 ; Erase-verify fail counter + 1 R6 R4 ; @TCSR ; Start watchdog timer R4 ; Set erase loop counter @FLMCR:8 ; Set E bit #1, R4, LOOPE #1, #H'A500, R4, R4 R4 ; Execute erase ERASES: ERASE: LOOPE: MOV.W MOV.W ADDS MOV.W MOV.W MOV.W BSET NOP NOP NOP NOP SUBS MOV.W BNE BCLR MOV.W MOV.W ; ; ; Wait loop @FLMCR:8 ; Clear E bit R4 ; @TCSR ; Stop watchdog timer 469 ; Execute erase-verify EVR: ; Starting transfer destination address (RAM) ; ; #RAMSTR + #ERVADR R2 ; ; Address of data area used in RAM MOV.W MOV.W ADD.W MOV.W SUB.W #RAMSTR, #ERVADR, R3, #START, R3, R2 R3 R2 R3 R2 MOV.B MOV.B BSET DEC BNE CMP.B BEQ CMP.B BMI MOV.B SUBX BTST BNE BRA BTST BNE INC MOV.W BRA #H'00, #H'b, #3, R4H LOOPEV #H'10, HANTEI #H'08, EBR2EV R1L, #H'08, R1H, ERSEVF ADD01 R1L, ERSEVF R1L @R2+, EBRTST R1L ; Used to test R1L bit in R0 R4H ; Set erase-verify loop counter @FLMCR:8 ; Set EV bit ERASE1: BRA ERASE ERSEVF: EVR2: MOV.W MOV.B MOV.B MOV.B DEC BNE MOV.B CMP.B BNE MOV.W CMP.W BNE @R2+, #H'FF, R1H, #H'c, R4H LOOPEP @R3+, #H'FF, BLKAD @R2, R4, EVR2 R3 R1H @R3 R4H CMP.B BMI MOV.B SUBX BCLR BRA BCLR INC BRA #H'08, SBCLR R1L, #H'08, R1H, BLKAD R1L, R1L EBRTST R1L LOOPEV: EBRTST: EBR2EV: ADD01: LOOPEP: SBCLR: BLKAD: 470 R1L R1L R1H R1H R0H R0L R3 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Wait loop R1L = H'10? If finished checking all R0 bits, branch to HANTEI Test EBR1 if R1L 8, or EBR2 if R1L < 8 R1L - 8 R1H Test R1H bit in EBR1 (R0H) If R1H bit in EBR1 (R0H) is 1, branch to ERSEVF If R1H bit in EBR1 (R0H) is 0, branch to ADD01 Test R1L bit in EBR2 (R0L) If R1L bit in EBR2 (R0H) is 1, branch to ERSEVF R1L + 1 R1L Dummy-increment R2 ; Branch to ERASE via Erase 1 R1H R1H R4 R3 R1H R1H R0H R0L ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Top address of block to be erase-verified Dummy write Set erase-verify loop counter Wait loop Read Read data = H'FF? If read data H'FF branch to BLKAD Top address of next block Last address of block? Test EBR1 if R1L 8, or EBR2 if R1L < 8 R1L - 8 R1H Clear R1H bit in EBR1 (R0H) Clear R1L bit in EBR2 (R0L) R1L + 1 R1L HANTEI: BRER: BCLR MOV.W BEQ #3, R0, EOWARI @FLMCR:8 @EBR1 ; MOV.W CMP.W BPL ADD.W MOV.W CMP.W BNE BRA #H'0004, R4, BRER R5, #H'025A, R4, ERASE1 ABEND2 R4 R6 ; Clear EV bit ; If EBR1/EBR2 is all 0, erasing ended normally R5 R4 R6 ; ; ; ; ; ; ; ; Erase-verify fail count executed 4 times? If R64, branch to BRER (branch until R6 is 4 to 602) If R6<4, Erase time x 2 (execute when R6 is 1, 2, or 3) Erase-verify executed 602 times? If erase-verify not executed 602 times, erase again If erase-verify executed 602 times, branch to ABEND2 ;------< Block address table used in erase-verify> ------ ERVADR: EOWARI: ABEND2: .ALIGN .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W .DATA.W 2 H'0000 H'0080 H'0100 H'0180 H'0200 H'0400 H'0800 H'0C00 H'1000 H'2000 H'4000 H'6000 H'8000 H'A000 H'C000 H'EF80 H'F780 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; SB0 SB1 SB2 SB3 SB4 SB5 SB6 SB7 LB0 LB1 LB2 LB3 LB4 LB5 LB6 LB7 FLASH END Erase end Erase error Loop Counter Values in Programs and Watchdog Timer Overflow Interval Settings: The setting of #a, #b, #c, #d, and #e values in the programs depends on the clock frequency. Tables 20.9 (1) and (2) indicate sample loop counter settings for typical clock frequencies. However, #e is set according to table 20.10. As a software loop is used, calculated values including percent errors may not be the same as actual values. Therefore, the values are set so that the total programming time and total erase time do not exceed 1 ms and 30 s, respectively. The maximum number of writes in the program, N, is set to 6. 471 Programming and erasing in accordance with the flowcharts is achieved by setting #a, #b, #c, and #d in the programs as shown in tables 20.9 (1) and (2). #e should be set as shown in table 20.10. Wait state insertion is inhibited in these programs. If wait states are to be used, the setting should be made after the program ends. The setting value for the watchdog timer (WDT) overflow time is calculated based on the number of instructions between starting and stopping of the WDT, including the write time and erase time. Therefore, no other instructions should be added between starting and stopping of the WDT in this program example. Table 20.9 (1) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with Program Running in the On-Chip Memory (RAM) Clock Frequency f = 16 MHz Variable Time Setting a(f) Programming time 15.8 s (initial setting value) b(f) tvs1 c (f) tvs2 d(f) Erase time 6.25 ms (initial setting value) f = 10 MHz f = 8 MHz f = 2 MHz Counter Counter Counter Counter Setting Value Setting Value Setting Value Setting Value H'001F H'0013 H'000F H'0003 4 s H'0B H'07 H'06 H'02 2 s H'06 H'04 H'03 H'01 H'1869 H'0F42 H'0C34 H'030D Table 20.9 (2) #a, #b, #c, and #d Setting Values for Typical Clock Frequencies with Program Running in the External Device Clock Frequency f = 16 MHz Variable Time Setting a(f) Programming time 15.8 s (initial setting value) b(f) tvs1 c (f) tvs2 d(f) Erase time 6.25 ms (initial setting value) 472 f = 10 MHz f = 8 MHz f = 2 MHz Counter Counter Counter Counter Setting Value Setting Value Setting Value Setting Value H'000A H'0006 H'0005 H'0001 4 s H'04 H'03 H'02 H'01 2 s H'02 H'02 H'01 H'01 H'0823 H'0516 H'0411 H'0104 Formula: When using a clock frequency not shown in tables 20.9 (1) and (2), follow the formula below. The calculation is based on a clock frequency of 10 MHz. After calculating a(f) and d(f) in the decimal system, omit the first decimal figures, and convert them to the hexadecimal system, so that a(f) and d(f) are set to 15.8 s or less and 6.25 ms or less, respectively. After calculating b(f) and c(f) in the decimal system, raise the first decimal figures, and convert them to the hexadecimal system, so that b(f) and c(f) are set to 4 s or more and 2 s or more, respectively. a (f) to d (f) = Clock frequency f [MHz] 10 x a (f = 10) to d (f = 10) Examples for a program running in on-chip memory (RAM) at a clock frequency of 12 MHz: a (f) = 12 10 x 19 = 22.8 22 = H'0016 b (f) = 12 10 x 7 = 8.4 9 = H'09 c (f) = 12 10 x 4 = 4.8 5 = H'05 d (f) = 12 10 x 3906 = 4687.2 4687 = H'124F Table 20.10 Watchdog Timer Overflow Interval Settings (#e Setting Value According to Clock Frequency) Variable Clock Frequency [MHz] e (f) 10 MHz frequency 16 MHz H'A57F 2 MHz frequency < 10 MHz H'A57E 473 20.4.7 Prewrite Verify Mode Prewrite-verify mode is a verify mode used when programming all bits to equalize their threshold voltages before erasing them. To program all bits, follow the prewrite algorithm shown in figure 20.10. The procedure is to program all flash memory data to H'00 by using H'00 write data. H'00 should also be written when using RAM for flash memory emulation (when prewriting a RAM area). (This also applies when using RAM to emulate flash memory erasing with an emulator or other support tool.) After the necessary programming time has elapsed, exit program mode (by clearing the P bit to 0) and select prewrite-verify mode (leave the P, E, PV, and EV bits all cleared to 0). In prewrite-verify mode, a prewrite-verify voltage is applied to the memory cells at the read address. If the flash memory is read in this state, the data at the read address will be read. After selecting prewrite-verify mode, wait 4 s or more before reading. Note: For a sample prewriting program, see the prewrite subroutine in the sample erasing program. 20.4.8 Protect Modes Flash memory can be protected from programming and erasing by software or hardware methods. These two protection modes are described below. Software Protection: Prevents transitions to program mode and erase mode even if the P or E bit is set in the flash memory control register (FLMCR). Details are as follows. Function Protection Description Program Block protect Individual blocks can be protected from erasing Disabled and programming by the erase block registers (EBR1 and EBR2). If H'00 is set in EBR1 and EBR2, all blocks are protected from erasing and programming. Emulation protect *2 When the RAMS or RAM0 bit, but not both, is set in the wait-state control register (WSCR), all blocks are protected from programming and erasing Disabled Erase Verify*1 Disabled Enabled Disabled*3 Enabled Notes: *1 Three modes: program-verify, erase-verify, and prewrite-verify. *2 Except in RAM areas overlapped onto flash memory. *3 All blocks are erase-disabled. It is not possible to specify individual blocks. 474 Hardware Protection: Suspends or disables the programming and erasing of flash memory, and resets the flash memory control register (FLMCR) and erase block registers (EBR1 and EBR2). Details of hardware protection are as follows. Function Verify*1 Protection Description Program Erase Programing voltage (V PP ) protect When 12 V is not applied to the FVPP pin, FLMCR, EBR1, and EBR2 are initialized, disabling programming and erasing. To obtain this protection, VPP should not exceed VCC.*3 Disabled Disabled*2 Disabled Reset and standby protect Disabled When a reset occurs (including a watchdog timer reset) or standby mode is entered, FLMCR, EBR1, and EBR2 are initialized, disabling programming and erasing. Note that RES input does not ensure a reset unless the RES pin is held low for at least 20 ms at powerup (to enable the oscillator to settle), or at least ten system clock cycles (10o) during operation. Disabled*2 Disabled Interrupt protect To prevent damage to the flash memory, if interrupt input occurs while flash memory is being programmed or erased, programming or erasing is aborted immediately. The settings in FLMCR, EBR1, and EBR2 are retained. This type of protection can be cleared only by a reset. Disabled Disabled*2 Enabled Notes: *1 Three modes: program-verify, erase-verify, and prewrite-verify. *2 All blocks are erase-disabled. It is not possible to specify individual blocks. *3 For details, see section 20.7, Flash Memory Programming and Erasing Precautions. 20.4.9 Interrupt Handling during Flash Memory Programming and Erasing If an interrupt occurs*1 while flash memory is being programmed or erased (while the P or E bit of FLMCR is set), the following operating states can occur. * If an interrupt is generated during programming or erasing, programming or erasing is aborted to protect the flash memory. Since memory cell values after a forced interrupt are indeterminate, the system will not operate correctly after such an interrupt. * Program runaway may result because the vector table could not be read correctly in interrupt exception handling during programming or erasure*2. 475 For NMI interrupts while flash memory is being programmed or erased, these malfunction and runaway problems can be prevented by using the RAM overlap function with the settings described below. 1. Do not store the NMI interrupt-handling routine*3 in the flash memory area (neither H'0000 to H'EF7F in mode 2 nor H'0000 to H'F77F in mode 3). Store it elsewhere (in RAM, for example). 2. Set the NMI interrupt vector in address H'F806 in RAM (corresponding to H'0006 in flash memory). 3. After the above settings, set both the RAMS and RAM0 bits to 1 in WSCR.*4 Due to the setting of step 3, if an interrupt signal is input while 12 V is applied to the FVPP pin, the RAM overlap function is enabled and part of the RAM (H'F800 to H'F87F) is overlapped onto the small-block area of flash memory (H'0000 to H'007F). As a result, when an interrupt is input, the vector is read from RAM, not flash memory, so the interrupt is handled normally even if flash memory is being programmed or erased. This can prevent malfunction and runaway. Notes: *1 When the interrupt mask bit (I) of the condition control register (CCR) is set to 1, all interrupts except NMI are masked. For details see (2) in section 2.2.2, Control Registers. *2 The vector table might not be read correctly for one of the following reasons: * If flash memory is read while it is being programmed or erased (while the P or E bit of FLMCR is set), the correct value cannot be read. * If no value has been written for the NMI entry in the vector table yet, NMI exception handling will not be executed correctly. *3 This routine should be programmed so as to prevent microcontroller runaway. *4 For details on WSCR settings, see section 20.2.4, Wait-State Control Register. Notes on Interrupt Handling in Boot Mode: In boot mode, the settings described above concerning NMI interrupts are carried out, and NMI interrupt handling (but not other interrupt handling) is enabled while the boot program is executing. Note the following points concerning the user program. * If interrupt handling is required Load the NMI vector (H'F780) into address H'F806 in RAM (the 38th byte of the transferred user program should be H'F780). The interrupt handling routine used by the boot program is stored in addresses H'F780 to H'F78F in RAM. Make sure that the user program does not overwrite this area. * If interrupt handling is not required Since the RAMS and RAM0 bits remain set to 1 in WSCR, make sure that the user program disables the RAM overlap by clearing the RAMS and RAM0 bits both to 0. 476 20.5 Flash Memory Emulation by RAM Erasing and programming flash memory takes time, which can make it difficult to tune parameters and other data in real time. If necessary, real-time updates of flash memory can be emulated by overlapping the small-block flash-memory area with part of the RAM (H'F800 to H'F97F). This RAM reassignment is performed using bits 7 and 6 of the wait-state control register (WSCR). See figure 20.11. After a flash memory area has been overlapped by RAM, the RAM area can be accessed from two address areas: the overlapped flash memory area, and the original RAM area (H'F800 to H'F97F). Table 20.11 indicates how to reassign RAM. Wait-State Control Register (WSCR)*2 Bit 7 6 5 4 3 2 1 0 RAMS RAM0 CKDBL -- WMS1 WMS0 WC1 WC0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W *1 Notes: *1 WSCR is initialized by a reset and in hardware standby mode. It is not initialized in software standby mode. *2 For details of WSCR settings, see section 20.2.4, Wait-State Control Register (WSCR). Table 20.11 RAM Area Selection Bit 7: RAMS Bit 6: RAM0 RAM Area ROM Area 0 0 None -- 1 H'F880 to H'F8FF H'0080 to H'00FF 0 H'F880 to H'F97F H'0080 to H'017F 1 H'F800 to H'F87F H'0000 to H'007F 1 477 Example of Emulation of Real-Time Flash-Memory Update H'0000 Small-block area (SB1) Overlapped RAM H'007F H'0080 H'00FF H'0100 Flash memory address space H'F77F H'F780 Overlapped RAM H'F880 H'F8FF On-chip RAM area H'FF7F Procedure 1. Overlap part of RAM (H'F880 to H'F8FF) onto the area requiring real-time update (SB1). (Set WSCR bits 7 and 6 to 01.) 2. Perform real-time updates in the overlapping RAM. 3. After finalization of the update data, clear the RAM overlap (by clearing the RAMS and RAM0 bits). 4. Read the data written in RAM addresses H'F880 to H'F8FF out externally, then program the flash memory area, using this data as part of the program data. Figure 20.12 Example of RAM Overlap 478 Notes on Use of RAM Emulation Function * Notes on Applying, Releasing, and Shutting Off the Programming Voltage (VPP) Care is necessary to avoid errors in programming and erasing when applying, releasing, and shutting off VPP, just as in the on-board programming modes. In particular, even if the emulation function is being used, make sure that the watchdog timer is set when the P or E bit of the flash memory control register (FLMCR) has been set, to prevent errors in programming and erasing due to program runaway while VPP is applied. For details see section 20.7, Flash Memory Programming and Erasing Precautions (5). 479 20.6 Flash Memory Writer Mode (H8/3437F) 20.6.1 Writer Mode Setting The on-chip flash memory of the H8/3437F can be programmed and erased not only in the onboard programming modes but also in writer mode, using a general-purpose PROM programmer. 20.6.2 Socket Adapter and Memory Map Programs can be written and verified by attaching a special 100-pin/32-pin socket adapter to the PROM programmer. Table 20.12 gives ordering information for the socket adapter. Figure 20.13 shows a memory map in writer mode. Figure 20.14 shows the socket adapter pin interconnections. Table 20.12 Socket Adapter Microcontroller Package Socket Adapter HD64F3437F16 100-pin QFP HS3434ESHF1H HD64F3437TF16 100-pin TQFP HS3434ESNF1H MCU mode H'0000 H8/3437F Writer mode H'0000 On-chip ROM area H'F77F H'F77F 1 output H'1FFFF Figure 20.13 Memory Map in Writer Mode 480 H8/3437F Pin No. Pin Name Socket Adapter FP-100B, TFP-100B HN28F101 (32 Pins) Pin Name Pin No. 8 STBY/FVPP VPP 1 7 NMI FA 9 26 18 P95 FA 16 2 19 P94 FA 15 3 22 P93 WE 31 82 P30 FO 0 13 83 P31 FO 1 14 84 P32 FO 2 15 85 P33 FO 3 17 86 P34 FO 4 18 87 P35 FO 5 19 88 P36 FO 6 20 89 P37 FO 7 21 79 P10 FA 0 12 78 P11 FA 1 11 77 P12 FA 2 10 76 P13 FA 3 9 75 P14 FA 4 8 74 P15 FA 5 7 73 P16 FA 6 6 72 P17 FA 7 5 67 P20 FA 8 27 66 P21 OE 24 65 P22 FA 10 23 64 P23 FA 11 25 63 P24 FA 12 4 62 P25 FA 13 28 61 P26 FA 14 29 60 P27 CE 22 P91, P90, P63, VCC 32 P64, P97 VSS 16 24, 25, 29, 32, 16 5, 6, 23,35 MD1, MD0, P92, P67 36, 37 AVref, AVCC 4, 9, 59 VCCB, VCC 46 AVSS 15, 70, 71, 92 VSS 1 RES 2, 3 Other pins XTAL, EXTAL Power-on reset circuit Legend: VPP: FO7 to FO0: FA16 to FA0: OE: CE: WE: Programming power supply Data input/output Address input Output enable Chip enable Write enable Oscillator circuit NC (OPEN) Figure 20.14 Wiring of Socket Adapter 481 20.6.3 Operation in Writer Mode The program/erase/verify specifications in writer mode are the same as for the standard HN28F101 flash memory. However, since the H8/3437F does not support product name recognition mode, the programmer cannot be automatically set with the device name. Table 20.13 indicates how to select the various operating modes. Table 20.13 Operating Mode Selection in Writer Mode Pins FV PP VCC CE OE WE D7 to D0 A16 to A0 Read VCC VCC L L H Data output Address input Output disable VCC VCC L H H High impedance Standby VCC VCC H X X High impedance Read VPP VCC L L H Data output Output disable VPP VCC L H H High impedance Standby VPP VCC H X X High impedance Write VPP VCC L H L Data input Mode Read Command write Note: * Be sure to set the FV PP pin to VCC in these states. If it is set to 0 V, hardware standby mode will be entered, even when in writer mode, resulting in incorrect operation. Legend: L: Low level H: High level VPP level VPP : VCC: VCC level X: Don't care 482 Table 20.14 Writer Mode Commands 1st Cycle 2nd Cycle Command Cycles Mode Address Data Mode Address Data Memory read 1 Write X H'00 Read RA Dout Erase setup/erase 2 Write X H'20 Write X H'20 Erase-verify 2 Write EA H'A0 Read X EVD Auto-erase setup/ auto-erase 2 Write X H'30 Write X H'30 Program setup/ program 2 Write X H'40 Write PA PD Program-verify 2 Write X H'C0 Read X PVD Reset 2 Write X H'FF Write X H'FF PA: EA: RA: PD: PVD: EVD: Program address Erase-verify address Read address Program data Program-verify output data Erase-verify output data 483 High-Speed, High-Reliability Programming: Unused areas of the H8/3437F flash memory contain H'FF data (initial value). The H8/3437F flash memory uses a high-speed, high-reliability programming procedure. This procedure provides enhanced programming speed without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. Figure 20.15 shows the basic high-speed, high-reliability programming flowchart. Tables 20.15 and 20.16 list the electrical characteristics during programming. Start Set VPP = 12.0 V 0.6 V Address = 0 n=0 n+1n Program setup command Program command Wait (25 s) Program-verify command Wait (6 s) Address + 1 address Verification? No go Go No n = 20? No Last address? Yes Yes Set VPP = VCC End Fail Figure 20.15 High-Speed, High-Reliability Programming 484 High-Speed, High-Reliability Erasing: The H8/3437F flash memory uses a high-speed, highreliability erasing procedure. This procedure provides enhanced erasing speed without subjecting the device to voltage stress and without sacrificing data reliability. Figure 20.16 shows the basic high-speed, high-reliability erasing flowchart. Tables 20.15 and 20.16 list the electrical characteristics during erasing. Start Program all bits to 0* Address = 0 n=0 n+1n Erase setup/erase command Wait (10 ms) Erase-verify command Wait (6 s) Address + 1 address Verification? No go Go No n = 3000? No Last address? Yes Yes End Fail Note: * Follow the high-speed, high-reliability programming flowchart in programming all bits. If some bits are already programmed to 0, program only the bits that have not yet been programmed. Figure 20.16 High-Speed, High-Reliability Erasing 485 Table 20.15 DC Characteristics in Writer Mode (Conditions: VCC = 5.0 V 10%, V PP = 12.0 V 0.6 V, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Typ Max Unit Test Conditions Input high voltage FO7 to FO0, FA 16 to FA0, OE, CE, WE VIH 2.2 -- VCC + 0.3 V Input low voltage FO7 to FO0, FA 16 to FA0, OE, CE, WE VIL -0.3 -- 0.8 V Output high voltage FO7 to FO0 VOH 2.4 -- -- V I OH = -200 A Output low voltage FO7 to FO0 VOL -- -- 0.45 V I OL = 1.6 mA Input leakage current FO7 to FO0, FA 16 to FA0, OE, CE, WE | ILI | -- -- 2 A Vin = 0 to VCC VCC current Read I CC -- 40 80 mA Program I CC -- 40 80 mA Erase I CC -- 40 80 mA Read I PP -- -- 10 A VPP = 2.7 V to 5.5 V -- 10 20 mA VPP = 12.6 V FV PP current 486 Program I PP -- 20 40 mA VPP = 12.6 V Erase I PP -- 20 40 mA VPP = 12.6 V Table 20.16 AC Characteristics in Writer Mode (Conditions: VCC = 5.0 V 10%, V PP = 12.0 V 0.6 V, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Typ Max Unit Test Conditions Command write cycle t CWC 120 -- -- ns Address setup time t AS 0 -- -- ns Address hold time t AH 60 -- -- ns Figure 20.17 Figure 20.18* Figure 20.19 Data setup time t DS 50 -- -- ns Data hold time t DH 10 -- -- ns CE setup time t CES 0 -- -- ns CE hold time t CEH 0 -- -- ns VPP setup time t VPS 100 -- -- ns VPP hold time t VPH 100 -- -- ns WE programming pulse width t WEP 70 -- -- ns WE programming pulse high time t WEH 40 -- -- ns OE setup time before command write t OEWS 0 -- -- ns OE setup time before verify t OERS 6 -- -- s Verify access time t VA -- -- 500 ns OE setup time before status polling t OEPS 120 -- -- ns Status polling access time t SPA -- -- 120 ns Program wait time t PPW 25 -- -- ns Erase wait time t ET 9 -- 11 ms Output disable time t DF 0 -- 40 ns Total auto-erase time t AET 0.5 -- 30 s Note: CE, OE, and WE should be high during transitions of VPP from 5 V to 12 V and from 12 V to 5 V. * Input pulse level: 0.45 V to 2.4 V Input rise time and fall time 10 ns Timing reference levels: 0.8 V and 2.0 V for input; 0.8 V and 2.0 V for output 487 Auto-erase setup VCC VPP Auto-erase and status polling 5.0 V 12 V 5.0 V tVPS tVPH Address CE tCEH OE tCES tOEWS tWEP WE tDS I/O7 tOEPS tCWC tCES tCEH tWEH tDH Command input tCES tAET tWEP tDH tDS tSPA Command input Status polling I/O0 to I/O6 Command input Command input Figure 20.17 Auto-Erase Timing 488 tDF Program setup VCC Program Program-verify 5.0 V 12 V VPP 5.0 V tVPS tVPH Address Valid address tAH tAS CE tCEH tCES OE tOEWS tWEP tCWC tCEH tWEH tDH WE tDS tCES tCES tPPW tWEP tDH tDS tCEH tWEP tOERS tDH tDS tVA tDF I/O7 Command input Data input Command input Valid data output I/O0 to I/O6 Command input Data input Command input Valid data output Note: Program-verify data output values may be intermediate between 1 and 0 before programming has been completed. Figure 20.18 High-Speed, High-Reliability Programming Timing 489 Erase setup VCC Erase Erase-verify 5.0 V 12 V VPP 5.0 V tVPS tVPH Address Valid address tAS tAH CE OE tOEWS tCES tWEP WE tCES tCEH tDS I/O0 to I/O7 Command input tDH tCEH tCES tCEH tCWC tET tWEP tOERS tWEP tVA tWEH tDS tDH Command input tDS tDH Command input tDF Valid data output Note: Erase-verify data output values may be intermediate between 1 and 0 before erasing has been completed. Figure 20.19 Erase Timing 20.7 Flash Memory Programming and Erasing Precautions Read these precautions before using writer mode, on-board programming mode, or flash memory emulation by RAM. (1) Program with the specified voltages and timing. The rated programming voltage (VPP) of the flash memory is 12.0 V. If the PROM programmer is set to Hitachi HN28F101 specifications, VPP will be 12.0 V. Applying voltages in excess of the rating can permanently damage the device. Take particular care to ensure that the PROM programmer peak overshoot does not exceed the rated limit of 13 V. (2) Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (3) Don't touch the socket adapter or chip while programming. Touching either of these can cause contact faults and write errors. 490 (4) Set H'FF as the PROM programmer buffer data for addresses H'F780 to H'1FFFF. The H8/3437F PROM size is 60 kbytes. Addresses H'F780 to H'1FFFF always read H'FF, so if H'FF is not specified as programmer data, a verify error will occur. (5) Notes on applying, releasing, and shutting off the programming voltage (VPP) Note: In this section, the application, release, and shutting-off of VPP are defined as follows. Application: A rise in voltage from VCC to 12 V 0.6 V. Release: A drop in voltage from 12 V 0.6 V to VCC. Shut-off: No applied voltage (floating). * Apply the programming voltage (V PP ) after the rise of VCC, and release VPP before shutting off VCC. To prevent unintended programming or erasing of flash memory, in these power-on and power-off timings, the application, release, and shutting-off of VPP must take place when the microcontroller is in a stable operating condition as defined below. Stable operating condition The VCC voltage must be stabilized within the rated voltage range (VCC = 2.7 V to 5.5 V)* If VPP is applied, released, or shut off while the microcontroller's V CC voltage is not within the rated voltage range (VCC = 2.7 to 5.5 V)*, since microcontroller operation is unstable, the flash memory may be programmed or erased by mistake. This can occur even if VCC = 0 V. To prevent changes in the VCC power supply when V PP is applied, be sure that the power supply is adequately decoupled with inserting bypass capacitors. Note: * In the LH version, V CC = 3.0 V to 5.5 V. Clock oscillation must be stabilized (the oscillation settling time must have elapsed), and oscillation must not be stopped When turning on VCC power, hold the RES pin low during the oscillation settling time (tOSC1 = 20 ms), and do not apply VPP until after this time. The microcontroller must be in the reset state, or in a state in which a reset has ended normally (reset has been released) and flash memory is not being accessed Apply or release VPP either in the reset state, or when the CPU is not accessing flash memory (when a program in on-chip RAM or external memory is executing). Flash memory cannot be read normally at the instant when VPP is applied or released. Do not read flash memory while VPP is being applied or released. For a reset during operation, apply or release VPP only after the RES pin has been held low for at least ten system clock cycles (10o). 491 The P and E bits must be cleared in the flash memory control register (FLMCR) When applying or releasing V PP , make sure that the P or E bit is not set by mistake. No program runaway When V PP is applied, program execution must be supervised, e.g. by the watchdog timer. These power-on and power-off timing requirements should also be satisfied in the event of a power failure and in recovery from a power failure. If these requirements are not satisfied, overprogramming or overerasing may occur due to program runaway etc., which could cause memory cells to malfunction. * The VPP flag is set and cleared by a threshold decision on the voltage applied to the FVPP pin. The threshold level is between approximately VCC + 2 V to 11.4 V. When this flag is set, it becomes possible to write to the flash memory control register (FLMCR) and the erase block registers (EBR1 and EBR2), even though the VPP voltage may not yet have reached the programming voltage range of 12.0 0.6 V. Do not actually program or erase the flash memory until VPP has reached the programming voltage range. The programming voltage range for programming and erasing flash memory is 12.0 0.6 V (11.4 V to 12.6 V). Programming and erasing cannot be performed correctly outside this range. When not programming or erasing the flash memory, ensure that the VPP voltage does not exceed the VCC voltage. This will prevent unintended programming and erasing. In this chip, the same pin is used for STBY and FVPP. When this pin is driven low, a transition is made to hardware standby mode. This happens not only in the normal operating modes (modes 1, 2, and 3), but also when programming the flash memory with a PROM programmer. When programming with a PROM programmer, therefore, use a programmer which sets this pin to the VCC level when not programming (FVPP =12 V). Note: Here, V PP application, release, and cutoff are defined as follows: Application: Raising the voltage from VCC to 120.6 V. Release: Dropping the voltage from 120.6 V to VCC. Cutoff: Halting voltage application (setting the floating state). 492 tOSC1 o 2.7 to 5.5 V* 0 s min 0 s min VCC 12 0.6 V VCC + 2 V to 11.4 V VPP 0 s min 0 to VCCV VCCV Boot mode Timing at which boot program branches to RAM area 12 0.6 V VPP 0 to VCCV VCCV User program mode RES Min 10o (when RES is low) Periods during which the VPP flag is being set or cleared and flash memory must not be accessed Note: * In the LH version, VCC = 3.0 V to 5.5 V. Figure 20.20 VPP Power-On and Power-Off Timing (6) Do not apply 12 V to the FVPP pin during normal operation. To prevent accidental programming or erasing due to microcontroller program runaway etc., apply 12 V to the VPP pin only when the flash memory is programmed or erased, or when flash memory is emulated by RAM. Overprogramming or overerasing due to program runaway can cause memory cells to malfunction. Avoid system configurations in which 12 V is always applied to the FVPP pin. While 12 V is applied, the watchdog timer should be running and enabled to halt runaway program execution, so that program runaway will not lead to overprogramming or overerasing. 493 (7) Design a current margin into the programming voltage (VPP) power supply. Ensure that VPP will not depart from 12.0 0.6 V (11.4 V to 12.6 V) during programming or erasing. Programming and erasing may become impossible outside this range. (8) Ensure that peak overshoot does not exceed the rated value at the FV PP and MD1 pins. Connect decoupling capacitors as close to the FVPP and MD 1 pins as possible. Also connect decoupling capacitors to the MD1 pin in the same way when boot mode is used. FVPP 12 V 1.0 F 0.01 F H8/3437F MD1 12 V 1.0 F 0.01 F Note: Also connect decoupling capacitors to the MD1 pin in the same way when boot mode is used. Figure 20.21 VPP Power Supply Circuit Design (Example) (9) Use the recommended algorithms for programming and erasing flash memory. These algorithms are designed to program and erase without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. Before setting the program (P) or erase (E) bit in the flash memory control register (FLMCR), set the watchdog timer to ensure that the P or E bit does not remain set for more than the specified time. (10) For details on interrupt handling while flash memory is being programmed or erased, see the notes on NMI interrupt handling in section 20.4.9, Interrupt Handling during Flash Memory Programming and Erasing. (11) Cautions on Accessing Flash Memory Control Registers 1. Flash memory control register access state in each operating mode The H8/3437F has flash memory control registers located at addresses H'FF80 (FLMCR), H'FF82 (EBR1), and H'FF83 (EBR2). These registers can only be accessed when 12 V is applied to the flash memory program power supply pin, FVPP. 494 Table 20.17 shows the area accessed for the above addresses in each mode, when 12 V is and is not applied to FVPP. Table 20.17 Area Accessed in Each Mode with 12V Applied and Not Applied to FVPP Mode 1 Mode 2 Mode 3 12 V applied to FV PP Reserved area (always H'FF) Flash memory control register (initial value H'80) Flash memory control register (initial value H'80) 12 V not applied to FV PP External address space External address space Reserved area (always H'FF) 2. When a flash memory control register is accessed in mode 2 (expanded mode with on-chip ROM enabled) When a flash memory control register is accessed in mode 2, it can be read or written to if 12 V is being applied to FV PP , but if not, external address space will be accessed. It is therefore essential to confirm that 12 V is being applied to the FVPP pin before accessing these registers. 3. To check for 12 V application/non-application in mode 3 (single-chip mode) When address H'FF80 is accessed in mode 3, if 12 V is being applied to FVPP , FLMCR is read/written to, and its initial value after reset is H'80. When 12 V is not being applied to FV PP , FLMCR is a reserved area that cannot be modified and always reads H'FF. Since bit 7 (corresponding to the VPP bit) is set to 1 at this time regardless of whether 12 V is applied to FVPP , application or release of 12 V to FVPP cannot be determined simply from the 0 or 1 status of this bit. A byte data comparison is necessary to check whether 12V is being applied. The relevant coding is shown below. . . . LABEL1: MOV.B CMP.B BEQ . . . @H'FF80, R1L #H'FF, R1L LABEL1 Sample program for detection of 12 V application to FVPP (mode 3) 495 Table 20.18 DC Characteristics of Flash Memory Conditions: VCC = 2.7 V to 5.5 V*2, AVCC = 2.7 V to 5.5 V*2, AVref = 2.7 V to AVCC*2, VSS = AVSS = 0 V, V PP = 12.0 0.6 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min Typ Max Unit Test Conditions High-voltage (12 V) threshold level *1 FV PP , MD1 VH VCC + 2 -- 11.4 V FV PP current During read I PP -- -- 10 A VPP = 2.7 to 5.5 V -- 10 20 mA VPP = 12.6 V During programming -- 20 40 mA During erasure -- 20 40 mA Notes: *1 The listed voltages describe the threshold level at which high-voltage application is recognized. In boot mode and while flash memory is being programmed or erased, the applied voltage should be 12.0 V 0.6 V. *2 In the LH version, VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC. 496 Table 20.19 AC Characteristics of Flash Memory Conditions: VCC = 2.7 V to 5.5 V*5, AVCC = 2.7 V to 5.5 V*5, AVref = 2.7 V to AVCC*5, VSS = AVSS = 0 V, V PP = 12.0 0.6 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item *1, *2 Programming time *1, *3 Erase time Number of writ ing/ eras ing count Symbol Min Typ Max Unit tP -- 50 1000 s tE -- 1 30 s NWEC -- -- 100 Times Verify setup time 1 *1 t VS1 4 -- -- s Verify setup time 2 *1 t VS2 2 -- -- s t FRS 50 -- -- s 100 -- -- Flash memory read setup time*4 Test Conditions VCC 4.5 V VCC < 4.5 V Notes: *1 Set the times following the programming/erasing algorithm shown in section 20. *2 The programming time is the time during which a byte is programmed or the P bit in the flash memory control register (FLMCR) is set. It does not include the program-verify time. *3 The erase time is the time during which all 60-kbyte blocks are erased or the E bit in the flash memory control register (FLMCR) is set . It does not include the prewrite time before erasure or erase-verify time. *4 After power-on when using an external colck source, after return from standby mode, or after switching the programming voltage (VPP ) from 12 V to VCC, make sure that this read setup time has elapsed before reading flash memory. When VPP is released, the flash memory read setup time is defined as the period from when the FV PP pin has reached VCC + 2 V until flash memory can be read. *5 In the LH version, VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC. 497 498 Section 21 ROM (60-kbyte Single-Power-Supply Flash Memory Version) 21.1 Flash Memory Overview 21.1.1 Mode Pin Settings and ROM Space The H8/3437SF has 60 kbytes of on-chip flash memory. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. Enabling and disabling of the on-chip ROM is performed by the mode pins (MD1 and MD2) and the EXPE bit in MDCR. The H8/3437SF flash memory can be programmed and erased on-board as well as with a PROM programmer. Table 21.1 Mode Pin Settings and ROM Space Operating Mode Mode Pin Settings MCU Operating Mode Description MD1 MD0 On-Chip ROM Mode 1 Expanded mode with on-chip ROM disabled 0 1 Disabled Mode 2 Expanded mode with on-chip ROM enabled 1 0 Enabled Mode 3 Single-chip mode 1 Enabled 499 21.1.2 Features Features of the flash memory are listed below. * Four flash memory operating modes The flash memory has four operating modes: program mode, program-verify mode, erase mode, and erase-verify mode. * Programming and erasing 32 bytes are programmed at a time. Erasing is performed in block units. To erase multiple blocks, individual blocks must be erased sequentially. In block erasing, 1-kbyte, 28-kbyte, 16kbyte, 12-kbyte, and 2-kbyte blocks can be set arbitrarily. * Program and erase times The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time for one block is 100 ms (typ.). * Erase-program cycles Flash memory contents can be erased and reprogrammed up to 100 times. * On-board programming modes These modes can be used to program, erase, and verify flash memory contents. There are two modes: boot mode and user programming mode. * Automatic bit rate alignment In boot-mode data transfer, the H8/3437SF aligns its bit rate automatically to the host bit rate. * Protect modes There are three modes that enable flash memory to be protected from program, erase, and verify operations: hardware protect mode, software protect mode, and error protect mode. * Writer mode As an alternative to on-board programming, the flash memory can be programmed and erased in writer mode, using a general-purpose PROM programmer. 500 21.1.3 Block Diagram Figure 21.1 shows a block diagram of the flash memory. 8 Internal data bus (upper) 8 Internal data bus (lower) FLMCR1 Bus interface and control section FLMCR2 EBR2 H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 Operating mode MD1 MD0 On-chip flash memory (60 kbytes) H'F77C H'F77D H'F77E H'F77F Upper byte (even address) Lower byte (odd address) Legend: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR2: Erase block register 2 Figure 21.1 Flash Memory Block Diagram 501 21.1.4 Input/Output Pins Flash memory is controlled by the pins listed in table 21.2. Table 21.2 Flash Memory Pins Pin Name Abbreviation Input/ Output Function Reset RES Input Reset Mode 1 MD1 Input H8/3437SF operating mode setting Mode 0 MD0 Input H8/3437SF operating mode setting Port 92 P92 Input H8/3437SF operating mode setting when MD1 = MD0 = 0 Port 91 P91 Input H8/3437SF operating mode setting when MD1 = MD0 = 0 Port 90 P90 Input H8/3437SF operating mode setting when MD1 = MD0 = 0 Transmit data TxD1 Output SCI1 transmit data output Receive data RxD1 Input SCI1 receive data input The transmit data and receive data pins are used in boot mode. 21.1.5 Register Configuration The flash memory is controlled by the registers listed in table 21.3. Table 21.3 Flash Memory Registers Name Abbreviation Flash memory control register 1 Flash memory control register 2 Erase block register 2 *1 Wait-state control register FLMCR1 FLMCR2 R/W *2 R/W *2 R/W *2 Initial Value Address H'80 H'FF80 *3 H'FF81 *3 H'00 EBR2 R/W H'00 H'FF83 WSCR R/W H'08 H'FFC2 Notes: *1 The wait-state control register is used to control the insertion of wait states by the waitstate controller and frequency division of clock signals for the on-chip supporting modules by the clock pulse generator. Selection of the respective registers (or FLMCR1, FLMCR2, and EBR2) is performed by means of the FLSHE bit in the wait state control register (WSCR). *2 In modes in which the on-chip flash memory is disabled, these registers cannot be modified and return H'00 if read. *3 Initialized to H'00 when the SWE bit is not set in FLMCR1. 502 21.1.6 Mode Control Register (MDCR) Register Configuration: The operating mode of the H8/3437SF is controlled by the mode pins and the mode control register (MDCR). Table 21.4 shows the MDCR register configuration. Table 21.4 Register Configuration Name Abbreviation R/W Initial Value Address Mode control register MDCR R/W Undefined (Depends on operating mode) H'FFC5 Mode Control Register (MDCR) Bit 7 *1 EXPE Initial value Read/Write *2 -- *2 R/W 6 5 4 3 2 1 0 -- -- -- -- -- MDS1 MDS0 *2 1 1 0 0 1 -- -- -- -- -- -- R --* 2 R Notes: *1 H8/3437SF (S-mask model, single-power-supply on-chip flash memory version) only. Otherwise, this is a reserved bit that is always read as 1. *2 Determined by the mode pins (MD1 and MD0). MDCR is an 8-bit register used to set the operating mode of the H8/3437SF and to monitor the current operating mode. Bit 7--Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, this bit is fixed at 1 and cannot be modified. In modes 2 and 3, this bit has a fixed initial value of 0 and cannot be modified. This bit can be read and written only in boot mode. Bit 7: EXPE Description 0 Single-chip mode is selected 1 Expanded mode is selected (writable in boot mode only) Bits 6 and 5--Reserved: These bits cannot be modified and are always read as 1. Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 0. Bit 2--Reserved: This bit cannot be modified and is always read as 1. 503 Bits 1 and 0--Mode Select 1 and 0 (MDS1, MDS0): These bits indicate the input levels at mode pins MD1 and MD0 (the current operating mode). Bits MDS1 and MDS0 correspond to pins MD1 and MD0, respectively. MDS1 and MDS0 are read-only bits, and cannot be modified. The mode pin (MD1 and MD 0) input levels are latched into these bits when MDCR is read. 21.1.7 Flash Memory Operating Modes Mode Transition Diagram: When the mode pins are set in the reset state and a reset start is effected, the microcontroller enters one of the operating modes as shown in figure 21.2. In user mode, the flash memory can be read but cannot be programmed or erased. Modes in which the flash memory can be programmed and erased are boot mode, user programming mode, and writer mode. Reset state MD1 = 1 User mode with on-chip ROM enabled RES = 0 RES = 0 *2 RES = 0 FLSHE = 1 FLSHE = 0 *1 RES = 0 Writer mode User programming mode Boot mode On-board programming mode Notes: Transitions between user mode and user programming mode should only be made when the CPU is not accessing the flash memory. *1 MD0 = MD1 = 0, P92 = P91 = P90 = 1 *2 MD0 = MD1 = 0, P92 = 0, P91 = P90 = 1 Figure 21.2 Flash Memory Related State Transitions 504 On-Board Programming Modes * Boot Mode 2. SCI communication check When boot mode is entered, the boot program in the H8/3437SF (already incorporated in the chip) is started, an SCI communication check is carried out, and the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. ; ;; ;; ; 1. Initial state The flash memory is in the erased state when shipped. The procedure for rewriting an old version of an application program or data is described here. The user should prepare an on-board update routine and the new application program beforehand in the host. Host Host On-board update routine On-board update routine New application program New application program H8/3437SF H8/3437SF SCI Boot program Flash memory SCI Boot program Flash memory RAM RAM Boot program area Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. 4. Writing new application program The on-board update routine in the host to RAM is transferred to RAM by SCI communication and executed, and the new application program in the host is written into the flash memory. Host Host On-board update routine New application program H8/3437SF H8/3437SF SCI Boot program Flash memory Flash memory RAM RAM On-board update routine Boot program area Flash memory erase SCI Boot program New application program : Program execution state Figure 21.3 Boot Mode 505 * User programming mode 1. Initial state (1) The program that will transfer the on-board update routine to on-chip RAM should be written into the flash memory by the user beforehand. (2) The on-board update routine should be prepared in the host or in the flash memory. Host 2. On-board update routine transfer The transfer program in the flash memory is executed, and the on-board update routine is transferred to RAM. Host On-board update routine New application program New application program H8/3437SF H8/3437SF SCI Boot program Flash memory SCI Boot program Flash memory RAM Transfer program Transfer program Application program (old version) Application program (old version) RAM ; ;; ; On-board update routine 3. Flash memory initialization The update routine in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host Host New application program H8/3437SF H8/3437SF SCI Boot program Flash memory RAM Transfer program Flash memory RAM Transfer program On-board update routine On-board update routine Flash memory erase SCI Boot program New application program : Program execution state Figure 21.4 User Programming Mode (Example) 506 Differences between Boot Mode and User Programming Mode Boot Mode User Programming Mode Total erase Yes Yes Block erase No Yes On-board update routine* Program/program-verify Erase/erase-verify Program/program-verify Note: * To be provided by the user, in accordance with the recommended algorithm. Block Configuration: The flash memory is divided into one 2-kbyte block, one 12-kbyte block, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks. Address H'00000 1 kbyte 1 kbyte 1 kbyte 1 kbyte 28 kbytes 60 kbytes 16 kbytes 12 kbytes Address H'F77F 2 kbytes Figure 21.5 Flash Memory Blocks 507 21.2 Flash Memory Register Descriptions 21.2.1 Flash Memory Control Register 1 (FLMCR1) Bit 7 6 5 4 3 2 1 0 FWE SWE -- -- EV PV E P Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W -- -- R/W R/W R/W R/W Note: The FLSHE bit in WSCR must be set to 1 in order for this register to be accessed. FLMCR1 is an 8-bit register that controls the flash memory operating modes. Program-verify mode or erase-verify mode is entered by setting SWE to 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit in FLMCR2, and finally setting the P bit. Erase mode is entered by setting SWE to 1, then setting the ESU bit in FLMCR2, and finally setting the E bit. FLMCR1 is initialized to H'80 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes to bits EV and PV in FLMCR1 are enabled only when SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when SWE = 1 and PSU = 1. Bit 7--Flash Write Enable (FWE): Controls programming and erasing of on-chip flash memory. In the H8/3437SF, this bit cannot be modified and is always read as 1. Bit 6--Software Write Enable (SWE): Enables or disables the flash memory. This bit should be set before setting bits ESU, PSU, EV, PV, E, P, and EB7 to EB0, and should not be cleared at the same time as these bits. Bit 6: SWE Description 0 Writes disabled 1 Writes enabled Bits 6 to 4--Reserved: These bits cannot be modified and are always read as 0. 508 (Initial value) Bit 3--Erase-Verify Mode (EV): Selects transition to or exit from erase-verify mode. (Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time.) Bit 3: EV Description 0 Exit from erase-verify mode 1 Transition to erase-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 2--Program-Verify Mode (PV): Selects transition to or exit from program-verify mode. (Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time.) Bit 2: PV Description 0 Exit from program-verify mode 1 Transition to program-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 1--Erase Mode (E): Selects transition to or exit from erase mode. (Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time.) Bit 1: E Description 0 Exit from erase mode 1 Transition to erase mode (Initial value) [Setting condition] When SWE = 1 and ESU = 1 Bit 0--Program Mode (P): Selects transition to or exit from program mode. (Do not set the SWE, ESU, PSU, EV, PV, or E bit at the same time.) Bit 0: P Description 0 Exit from program mode 1 Transition to program mode (Initial value) [Setting condition] When SWE = 1 and PSU = 1 509 21.2.2 Flash Memory Control Register 2 (FLMCR2) Bit 7 6 5 4 3 2 1 0 FLER -- -- -- -- -- ESU PSU Initial value 0 0 0 0 0 0 0 0 Read/Write R -- -- -- -- -- R/W R/W Note: The FLSHE bit in WSCR must be set to 1 in order for this register to be accessed. FLMCR2 is an 8-bit register used for monitoring of flash memory program/erase protection (error protection) and flash memory program/erase mode setup. FLMCR2 is initialized to H'00 by a reset and in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, hardware protect mode, and software protect mode. When on-chip flash memory is disabled, a read will return H'00. Bit 7--Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the errorprotection state. Bit 7: FLER Description 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing conditions] Reset, hardware standby mode, subactive mode, subsleep mode, watch mode (Initial value) 1 An error occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See Error Protection in section 21.4.5 Bits 6 to 2--Reserved: These bits cannot be modified and are always read as 0. 510 Bit 1--Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit in FLMCR1. (Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.) Bit 1: ESU Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When SWE = 1 Bit 0--Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before setting the P bit in FLMCR1. (Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.) Bit 0: PSU Description 0 Program setup cleared 1 Program setup (Initial value) [Setting condition] When SWE = 1 21.2.3 Erase Block Register 2 (EBR2) Bit 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W* R/W R/W R/W R/W R/W R/W R/W Note: The FLSHE bit in WSCR must be set to 1 in order for this register to be accessed. * Writes to bit 7 are invalid in mode 2. EBR2 is an 8-bit register that designates flash-memory erase blocks for erasure. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set to 1, the corresponding block can be erased. Other blocks are erase-protected. Only one bit should be set in EBR2; do not set two or more bits. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. The flash memory block configuration is shown in table 21.5. 511 Table 21.5 Flash Memory Erase Blocks Block (Size) 60-Kbyte Version Addresses EB0 (1 kbyte) H'0000-H'03FF EB1 (1 kbyte) H'0400-H'07FF EB2 (1 kbyte) H'0800-H'0BFF EB3 (1 kbyte) H'0C00-H'0FFF EB4 (28 kbytes) H'1000-H'7FFF EB5 (16 kbytes) H'8000-H'BFFF EB6 (12 kbytes) H'C000-H'EF7F EB7 (2 kbytes) H'EF80-H'F77F 21.2.4 Wait-State Control Register (WSCR) Bit 7 6 5 4 3 2 1 0 -- -- CKDBL FLSHE WMS1 WMS0 WC1 WC0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait state controller wait settings, RAM area setting for dual-power-supply flash memory, and selection/non-selection of single-power-supply flash memory control registers. WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 and 6--Reserved: These bits are reserved, but can be written and read. Their initial value is 0. Bit 5--Clock Double (CKDBL): Controls frequency division of clock signals supplied to the onchip supporting modules. For details, see section 6, Clock Pulse Generator. 512 Bit 4--Flash Memory Control Register Enable (FLSHE): When the FLSHE bit is set to 1, the flash memory control registers can be read and written to. When FLSHE is cleared to 0, the flash memory control registers are unselected. In this case, the contents of the flash memory contents are retained. Bit 4: FLSHE Description 0 Flash memory control registers are in unselected state 1 Flash memory control registers are in selected state (Initial value) Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1, WMS0) Bits 1 and 0--Wait Count 1 and 0 (WC1, WC0) These bits control insertion of wait states by the wait-state controller. For details, see section 5, Wait-State Controller. 21.3 On-Board Programming Modes When an on-board programming mode is selected, the on-chip flash memory can be programmed, erased, and verified. There are two on-board programming modes: boot mode and user programming mode. Table 21.6 indicates how to select the on-board programming modes. User programming mode operation can be performed by setting control bits with software. A state transition diagram for flash memory related modes is shown in figure 21.2. Table 21.6 On-Board Programming Mode Selection Mode Selection MD1 MD0 P92 P91 P90 Boot mode 0 0 1 1 1 User programming mode 1 0 -- -- -- 21.3.1 1 Boot Mode To use boot mode, a user program for programming and erasing the flash memory must be provided in advance on the host machine (which may be a personal computer). Serial communication interface (SCI) channel 1 is used in asynchronous mode. When a reset state is executed after the H8/3437SF pins have been set to boot mode, the built-in boot program is activated, and the on-board update routine provided in the host is transferred sequentially to the H8/3437SF using the serial communication interface (SCI). The H8/3437SF writes the on-board update routine received via the SCI to the on-board update routine area in the on-chip RAM. After the transfer is completed, execution branches to the first address of the on- 513 board update routine area, and the on-board update routine execution state is entered (flash memory programming is performed). Therefore, a routine conforming to the programming algorithm described later must be provided in the on-board update routine transferred from the host. Figure 21.6 shows the system configuration in boot mode, and figure 21.7 shows the boot mode execution procedure. H8/3437SF Flash memory Host Reception of programming data Transmission of verification data RxD1 SCI1 TxD1 On-chip RAM Figure 21.6 Boot-Mode System Configuration Boot-Mode Execution Procedure: Figure 21.7 shows the boot-mode execution procedure. 514 Start Program H8/3437SF pins for boot mode, and reset Host transmits H'00 data continuously at desired bit rate H8/3437SF measures low period of H'00 data transmitted from host H8/3437SF computes bit rate and sets bit rate register After completing bit-rate alignment, H8/3437SF sends one H'00 data byte to host to indicate that alignment is completed Host checks that this byte, indicating completion of bit-rate alignment, is received normally, then transmits one H'55 byte. After receiving H'55, H8/3437SF sends part of the boot program to RAM After checking that all data in flash memory has been erased, H8/3437SF transmits one H'AA data byte to host Check flash memory data, and if data has already been written, erase all blocks Host transmits byte length (N) of user program in two bytes, upper byte followed by lower byte H8/3437SF transmits received byte length to host as verification data (echo-back) n=1 Host transmits user program sequentially, in byte units H8/3437SF transmits received user program to host as verification data (echo-back) n+1n Transfer received on-board update routine to on-chip RAM n = N? No Yes End of transfer Transmit one H'AA data byte to host, and execute on-board update routine transferred to on-chip RAM Note: If a memory cell malfunctions and cannot be erased, the H8/3437SF transmits one H'FF byte to report an erase error, halts erasing, and halts further operations. Figure 21.7 Boot Mode Flowchart 515 Automatic Alignment of SCI Bit Rate Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit This low period (9 bits) is measured (H'00 data) High for at least 1 bit Figure 21.8 Measurement of Low Period in Data Transmitted from Host When started in boot mode, the H8/3437SF measures the low period in asynchronous SCI data (H'00) transmitted from the host. The data format is eight data bits, one stop bit, and no parity bit. From the measured low period (9 bits), the H8/3437SF computes the host's bit rate. After aligning its own bit rate, the H8/3437SF sends the host one byte of H'00 data to indicate that bit-rate alignment is completed. The host should check that this alignment-completed indication is received normally and send one H'55 byte back to the H8/3437SF. If the alignment-completed indication is not received normally, the H8/3437F should be reset, then restarted in boot mode to measure the low period again. There may be some alignment error between the host's and H8/3437SF's bit rates, depending on the host's transmission bit rate and the H8/3437SF's system clock frequency (fOSC). To have the SCI operate normally, set the host's transfer bit rate to 2400, 4800, or 9600 bps. Table 21.7 lists typical host transfer bit rates and indicates the system clock frequency ranges over which the H8/3437SF can align its bit rate automatically. Boot mode should be used within these frequency ranges. Table 21.7 System Clock Frequencies Permitting Automatic Bit-Rate Alignment by H8/3437SF Host Bit Rate System Clock Frequencies (fOSC) Permitting Automatic Bit-Rate Alignment by H8/3437SF 9600 bps 8 MHz to 16 MHz 4800 bps 4 MHz to 16 MHz 2400 bps 2 MHz to 16 MHz RAM Area Allocation in Boot Mode: In boot mode, the 128 bytes from H'FF00 to H'FF7F are reserved for use by the boot program, as shown in figure 21.9. The user program is transferred into the area from H'F780 to H'FDFF (1664 bytes). The boot program area can be used after the transition to execution of the user program transferred into RAM. If a stack area is needed, set it within the user program. 516 H'F780 User program transfer area (1664 bytes) H'FDFF H'FF00 Boot program area* (128 bytes) H'FF7F Note: * This area cannot be used until the H8/3437SF starts to execute the user program transferred to RAM. Note that even after the branch to the user program, the boot program area still contains the boot program. Figure 21.9 RAM Areas in Boot Mode Notes on Use of Boot Mode 1. When the H8/3437SF comes out of reset in boot mode, it measures the low period of the input at the SCI's RxD 1 pin. The reset should end with RxD1 high. After the reset ends, it takes about 100 states for the H8/3437SF to get ready to measure the low period of the RxD1 input. 2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF), all flash memory blocks are erased. Boot mode is for use when user programming mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user programming mode is accidentally erased. 3. Interrupts cannot be used while the flash memory is being programmed or erased. 4. The RxD1 and TxD1 pins should be pulled up on-board. 5. Before branching to the user program (at address H'E880 in the RAM area), the H8/3437SF terminates transmit and receive operations by the on-chip SCI (by clearing the RE and TE bits of serial control register SCR to 0 in channel 1), but the auto-aligned bit rate remains set in bit rate register BRR. The transmit data output pin (TxD1) is in the high output state (in port 8, bits P8 4DDR of the port 8 data direction register and P84DR of the port 8 data register are set to 1). 517 At this time, the values of general registers in the CPU are undetermined. Thus these registers should be initialized immediately after branching to the user program. Especially in the case of the stack pointer (SP), which is used implicitly in subroutine calls, etc., the stack area used by the user program should be specified. There are no other changes to the initialized values of other registers. 6. Boot mode can be entered by starting from a reset after pin settings are made according to the mode setting conditions listed in table 21.6. In the H8/3437SF, P92, P91, and P90 can be used as I/O ports if boot mode selection is detected when reset is released*1. Boot mode can be released by driving the reset pin low, waiting at least 20 system clock cycles, then setting the mode pins and releasing the reset *1. Boot mode can also be released if a watchdog timer overflow reset occurs. The mode pin input levels must not be changed during boot mode. 7. If the input level of a mode pin is changed during a reset (e.g., from low to high), the resultant switch in the microcontroller's operating mode will affect the bus control output signals (AS, RD, and WR) and the status of ports that can be used for address output*2. Therefore, either set these pins so that they do not output signals during the reset, or make sure that their output signals do not collide with other signals output the microcontroller. Notes: *1 Mode pin input must satisfy the mode programming setup time (tMDS = 4 states) with respect to the reset release timing. *2 These ports output low-level address signals if the mode pins are set to mode 1 during the reset. In all other modes, these ports are in the high-impedance state. The bus control output signals are high if the mode pins are set for mode 1 or 2 during the reset. In mode 3, they are at high impedance. RES tMDS MD0, MD1 P92 P91 P90 tMDS: 4tCYC (min.) Figure 21.10 Programming Mode Timing 518 21.3.2 User Programming Mode When set to user programming mode, the H8/3437SF can erase and program its flash memory by executing a user program. On-board updates of the on-chip flash memory can be carried out by providing an on-board circuit for supplying programming data, and storing an update program in part of the program area. To select user programming mode, start up in a mode that enables the on-chip flash memory (mode 2 or 3). In user programming mode, the on-chip supporting modules operate as they normally would in mode 2 or 3, except for the flash memory. The flash memory cannot be read while the SWE bit is set to 1 in order to perform programming or erasing, so the update program must be executed in on-chip RAM or external memory. User Programming Mode Execution Procedure (Example): Figure 21.11 shows the execution procedure for user programming mode when the on-board update routine is executed in RAM. The transfer program (and on-board update program as required) is written in flash memory ahead of time by the user. Set MD1 and MD0 to 10 or 11 Start from reset Transfer on-board update routine into RAM Branch to flash memory on-board update routine in RAM Execute flash memory on-board update routine (update flash memory) Branch to application program in flash memory Note: Start the watchdog timer to prevent over-erasing due to program runaway, etc. Figure 21.11 User Programming Mode Operation (Example) 519 21.4 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, EV, PV, E, and P bits in FLMCR1, and the ESU and PSU bits in FLMCR2, is executed by a program in flash memory. 2. Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. 21.4.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 21.12 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a time. For the wait times (x, y, z, , , , , ) after setting/clearing individual bits in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of writes (N), see Flash Memory Characteristics in section 23, Electrical Characteristics. Following the elapse of (x) s or more after the SWE bit is set to 1 in flash memory control register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z + + ) s as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) s. 520 21.4.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared, then the PSU bit in FLMCR2 is cleared at least () s later). The watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to programverify mode by setting the PV bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and a bit generation operation is performed for reprogram data (see figure 21.12) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit programverify mode, wait for at least () s, then clear the SWE bit in FLMCR1. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. 521 Start Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. Set SWE bit in FLMCR1 Wait (x) s *5 Store 32-byte program data in program data area and reprogram data area *4 n=1 m=0 Write 32-byte data in RAM reprogram data area consecutively to flash memory *1 nn+1 Enable WDT Set PSU bit in FLMCR2 Wait (y) s Set P bit in FLMCR1 Wait (z) s Clear P bit in FLMCR1 Wait () s *5 Start of programming *5 End of programming *5 Clear PSU bit in FLMCR2 Wait () s *5 Disable WDT Set PV bit in FLMCR1 Wait () s *5 Notes: *1 Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. *2 Verify data is read in 16-bit (word) units. *3 If a bit for which programming has been completed in the 32-byte programming loop fails the following verify phase, additional programming is performed for that bit. *4 An area for storing program data (32 bytes) and reprogram data (32 bytes) must be provided in RAM. The contents of the latter are rewritten as programming progresses. *5 See section 23, Flash Memory Characteristics, for the values of x, y, z, , , , , , and N. H'FF dummy write to verify address Wait () s *5 Read verify data *2 Increment address Program data = verify data? OK Reprogram data computation Transfer reprogram data to reprogram data area NG NG m=1 Program Data 0 Verify Data 0 Reprogram Data 1 0 1 0 Programming incomplete; reprogram 1 0 1 -- 1 1 1 Still in erased state; no action Comments Reprogramming is not performed if program data and verify data match *3 RAM *4 Program data storage area (32 bytes) End of 32-byte data verification? OK Clear PV bit in FLMCR1 Wait () s m = 0? OK Reprogram data storage area (32 bytes) *5 NG n N? *5 NG OK Clear SWE bit in FLMCR1 Clear SWE bit in FLMCR1 End of programming Programming failure Figure 21.12 Program/Program-Verify Flowchart 522 21.4.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 21.13. The wait times (x, y, z, , , , , ) after setting/clearing individual bits in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of erases (N), see Flash Memory Characteristics in section 23, Electrical Characteristics. To perform data or program erasure, make a 1 bit setting for the flash memory area to be erased in erase block register 2 (EBR2) at least (x) s after setting the SWE bit to 1 in flash memory control register 1 (FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. Set a value greater than (y + z + + ) ms as the WDT overflow period. After this, preparation for erase mode (erase setup) is carried out by setting the ESU bit in FLMCR2, and after the elapse of (y) s or more, the operating mode is switched to erase mode by setting the E bit in FLMCR1. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 21.4.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the erase time, erase mode is exited (the E bit in FLMCR1 is cleared, then the ESU bit in FLMCR2 is cleared at least () s later), the watchdog timer is cleared after the elapse of () s or more, and the operating mode is switched to erase-verify mode by setting the EV bit in FLMCR1. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. If the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. If the read data has not been erased, set erase mode again, and repeat the erase/erase-verify sequence in the same way. However, ensure that the erase/eraseverify sequence is not repeated more than (N) times. When verification is completed, exit eraseverify mode, and wait for at least () s. If erasure has been completed on all the erase blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, make a 1 bit setting in EBR2 for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. 523 Start *1 Set SWE bit in FLMCR1 Wait (x) s *5 n=1 Set EBR1, EBR2 *3 Enable WDT Set ESU bit in FLMCR2 Wait (y) s *5 Start of erase Set E bit in FLMCR1 Wait (z) ms *5 Clear E bit in FLMCR1 nn+1 Halt erase Wait () s *5 Clear ESU bit in FLMCR2 Wait () s *5 Disable WDT Set EV bit in FLMCR1 Wait () s *5 Set block start address to verify address H'FF dummy write to verify address Increment address Wait () s *5 Read verify data *2 Verify data = all 1? NG OK NG Last address of block? OK Clear EV bit in FLMCR1 Wait () s NG Notes: *1 *2 *3 *4 *5 *4 End of erasing of all erase blocks? OK Clear EV bit in FLMCR1 *5 Wait () s *5 *5 n N? Clear SWE bit in FLMCR1 OK Clear SWE bit in FLMCR1 End of erasing Erase failure NG Preprogramming (setting erase block data to all 0) is not necessary. Verify data is read in 16-bit (W) units. Set only one bit in EBR2. More than one bit cannot be set. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially. See section 23, Electrical Characteristics, Flash Memory Characteristics, for the values of x, y, z, , , , , , and N. Figure 21.13 Erase/Erase-Verify Flowchart (Single-Block Erase) 524 21.4.5 Protect Modes There are three modes for protecting flash memory from programming and erasing: software protection, hardware protection, and error protection. These protection modes are described below. Software Protection: Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), and setting erase block register 2 (EBR2). Software protection prevents transitions to program mode and erase mode even if the P or E bit is set in FLMCR1. Details of software protection are shown in table 21.8. Table 21.8 Software Protection Functions Item Description Program Erase SWE bit protect Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. (Execute in on-chip RAM or external memory.) Yes Yes Block protect Individual blocks can be protected from erasing and programming by erase block register 2 (EBR2). If H'00 is set in EBR2, all blocks are protected from erasing and programming. -- Yes Hardware Protection: Hardware protection refers to a state in which programming and erasing of flash memory is forcibly suspended or disabled. At this time, the flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block register 2 (EBR2) settings are reset. Details of hardware protection are shown in table 21.9. Table 21.9 Hardware Protection Functions Item Description Program Reset and standby protect When a reset occurs (including a watchdog timer Yes reset) or standby mode is entered, FLMCR1, FLMCR2, and EBR2 are initialized, disabling programming and erasing. Note that RES input does not ensure a reset unless the RES pin is held low until the oscillator settles at power-up, or for a period equivalent to the RES pulse width specified in the AC characteristics during operation. Erase Yes 525 Error Protection: In error protection, an error is detected when microcontroller runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the microcontroller malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. FLER bit setting conditions are as follows: 1. When flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. Immediately after the start of exception handling (excluding a reset) during programming/erasing 3. When a SLEEP instruction (including software standby) is executed during programming/erasing 4. When the bus is released during programming/erasing Error protection is released only by a power-on reset. Figure 21.14 shows the flash memory state transition diagram. 526 Program mode Erase mode RES = 0 or STBY = 0 RD VF PR ER FLER = 0 RD VF PR ER FLER = 0 Error occurrence (software standby mode) Error occurrence Reset or hardware standby (hardware protection) Error protect mode RES = 0 or STBY = 0 Software standby mode RD VF PR ER FLER = 1 Software standby mode release RES = 0 or STBY = 0 FLMCR1, FLMCR2, EBR2 initialized Error protect mode (standby) RD VF PR ER FLER = 1 FLMCR1, FLMCR2 (except FLER bit), EBR2 initialized RD: VF: PR: ER: Memory read possible Verify-read possible Programming possible Erasing possible RD: VF: PR: ER: Memory read not possible Verify-read not possible Programming not possible Erasing not possible Figure 21.14 Flash Memory State Transitions 21.4.6 Interrupt Handling during Flash Memory Programming and Erasing All interrupts, including NMI input, should be disabled when flash memory is being programmed or erased (while the P or E bit is set in FLMCR1) and while the boot program is executing in boot mode*1, to give priority to the program or erase operation. There are three reasons for this: 1. Interrupt occurrence during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. In the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly*2, possibly resulting in microcontroller runaway. 3. If an interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. For these reasons, there are conditions for disabling interrupts in the on-board programming modes alone, as an exception to the general rule. However, this provision does not guarantee normal erasing and programming or microcontroller operation. All requests, including NMI, must therefore be disabled inside and outside the microcontroller when flash memory is programmed or erased. Interrupts are also disabled in the error protection state while the P or E bit setting in FLMCR1 is held. 527 Notes: *1 Interrupt requests must be disabled inside and outside the microcontroller until programming by the update program has been completed. *2 The vector may not be read correctly in this case for the following two reasons: * If flash memory is read while being programmed or erased (while the P or E bit is set in FLMCR1), correct read data will not be obtained (undetermined values will be returned). * If a value has not yet been written in the interrupt vector table, interrupt exception handling will not be executed correctly. 21.5 Flash Memory Writer Mode (H8/3437SF) 21.5.1 Writer Mode Setting Programs and data can be written and erased in writer mode as well as in the on-board programming modes. In writer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Hitachi microcomputer device type* with 64-kbyte on-chip flash memory*. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type. In auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. Note: * The H8/3437 should be used with the PROM programmer programming voltage set to 5.0 V. Table 21.10 Writer Mode Pin Settings Pin Names Settings Mode pins: MD 1, MD0 Low level input to MD1 and MD0 STBY pin High level input (hardware standby mode not entered) RES pin Power-on reset circuit XTAL and EXTAL pins Oscillator circuit Other setting pins: P9 7, P92, P91, P90, P67 Low level input to P92 and P67, high level input to P9 7, P91, and P9 0 21.5.2 Socket Adapter and Memory Map In writer mode, a socket adapter for the relevant kind of package is attached to the PROM programmer. Socket adapters are available for all PROM programmer manufacturers supporting the Hitachi microcomputer device type with 64-kbyte on-chip flash memory. 528 Figure 21.15 shows the memory map in writer mode, and table 21.10 shows writer mode pin settings. For pin names in writer mode, see section 1.3.2, Pin Functions in Each Operating Mode. MCU mode H8/3437SF H'0000 Writer mode H'0000 On-chip ROM area H'F77F H'F77F Undetermined values output H'1FFFF Figure 21.15 Memory Map in Writer Mode 21.5.3 Operation in Writer Mode Table 21.11 shows how to select the various operating modes when using writer mode, and table 21.12 lists the commands used in writer mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the FO6 signal. In status read mode, error information is output if an error occurs. 529 Table 21.11 Operating Mode Selection in Writer Mode Pins Mode CE OE WE FO7-FO0 FA17-FA0 Read L L H Data output Ain*2 Output disable L H H High impedance X Command write L H L Data input Ain*2 Chip disable *1 H X X High impedance X Notes: *1 Chip disable is not a standby state; internally, it is an operation state. *2 Ain indicates that there is also address input in auto-program mode. Table 21.12 Writer Mode Commands 1st Cycle 2nd Cycle Command Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write WA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. In memory read mode, the number of cycles depends on the number of address write cycles (n). 530 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3. Once memory read mode has been entered, consecutive reads can be performed. 4. After powering up, memory read mode is entered. Table 21.13 AC Characteristics in Memory Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Command write cycle t nxtc 20 s CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Programming pulse width t wep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns Command write Unit Notes Memory read mode Address Address stable tces tceh CE OE Max tnxtc tf twep tr WE tds Data tdh Data Data Note: Data is latched at the rising edge of WE. Figure 21.16 Timing Waveforms for Memory Read after Command Write 531 Table 21.14 AC Characteristics in Transition from Memory Read Mode to Another Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Command write cycle t nxtc 20 s CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Programming pulse width t wep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns Unit Notes Other mode command write Memory read mode Address Max Address stable tnxtc tces tceh CE OE tf twep tr WE tds Data Data tdh H'XX Note: Do not enable WE and OE simultaneously. Figure 21.17 Timing Waveforms for Transition from Memory Read Mode to Another Mode 532 Table 21.15 AC Characteristics in Memory Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Access time Max Unit t acc 20 s CE output delay time t ce 150 ns OE output delay time t oe 150 ns Output disable delay time t df 100 ns Data output hold time t oh Address Min 5 Address stable Notes ns Address stable CE VIL OE VIL WE tacc tacc toh toh Data Data VIH Data Figure 21.18 Timing Waveforms for CE and OE Enable State Read Address Address stable Address stable tce tce CE toe toe OE WE Data VIH tacc tacc toh Data tdf toh tdf Data Figure 21.19 Timing Waveforms for CE and OE Clocked Read 533 Auto-Program Mode * AC Characteristics Table 21.16 AC Characteristics in Auto-Program Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Command write cycle t nxtc 20 s CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Programming pulse width t wep 70 ns Status polling start time t wsts 1 ms Status polling access time t spa Address setup time t as 0 ns Address hold time t ah 60 ns Memory write time t write 1 WE rise time WE fall time Address Max Unit 150 Notes ns 3000 ms tr 30 ns tf 30 ns Address stable tces tceh tnxtc tnxtc CE OE tf twep tr tas tah twsts tspa WE tds tdh Data transfer 1 byte ... 128 bytes twrite Programming operation end identification signal FO7 Programming normal end identification signal FO6 Programming wait Data H'40 Data Data Figure 21.20 Auto-Program Mode Timing Waveforms 534 FO0 to FO5 = 0 * Notes on Use of Auto-Program Mode 1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. 2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. The lower 8 bits of the transfer address must be H'00 or H'80. If a value other than a valid address is input, processing will switch to a memory write operation but a write error will be flagged. 4. Memory address transfer is performed in the second cycle (figure 21.19). Do not perform transfer after the second cycle. 5. Do not perform a command write during a programming operation. 6. Perform one auto-programming operation for a 128-byte block for each address. Characteristics are not guaranteed for two or more programming operations. 7. Confirm normal end of auto-programming by checking FO6. Alternatively, status read mode can also be used for this purpose (in FO7 status polling, the pin is the auto-program operation end identification pin). 8. Status polling FO6 and FO7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. 535 Auto-Erase Mode * AC Characteristics Table 21.17 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Max Unit Command write cycle t nxtc 20 s CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Programming pulse width t wep 70 ns Status polling start time t ests 1 ms Status polling access time t spa Memory erase time t erase WE rise time WE fall time 150 ns 40000 ms tr 30 ns tf 30 ns 100 Notes Address tces tnxtc tceh tnxtc CE OE tf twep tests tr tspa WE tds tdh terase (100 to 40000 ms) FO7 Erase end identification signal FO6 Data CLin DLin H'20 H'20 Erase normal end confirmation signal FO0 to FO5 = 0 Figure 21.21 Auto-Erase Mode Timing Waveforms 536 * Notes on Use of Erase-Program Mode 1. Auto-erase mode supports only total memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking FO6. Alternatively, status read mode can also be used for this purpose (in FO7 status polling, the pin is the auto-erase operation end identification pin). 4. Status polling FO6 and FO7 pin information is retained until the next command write. As long as the next command write has not been performed, reading is possible by enabling CE and OE. Status Read Mode 1. Status read mode is used to identify what kind of abnormal end has occurred. This mode should be used if an abnormal end occurs in auto-program or auto-erase mode. 2. The return code is retained until a command write for a mode other than status read mode is executed. Table 21.18 AC Characteristics in Status Read Mode (Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C) Item Symbol Min Max Unit Command write cycle t nxtc 20 s CE hold time t ceh 0 ns CE setup time t ces 0 ns Data hold time t dh 50 ns Data setup time t ds 50 ns Programming pulse width t wep 70 ns OE output delay time t oe 150 ns Disable delay time t df 100 ns CE output delay time t ce 150 ns WE rise time tr 30 ns WE fall time tf 30 ns Notes 537 Address tces tnxtc tceh tces tnxtc tceh tnxtc CE tce OE tf twep tr tf twep tr toe WE tds tdh tds H'71 Data tdf tdh H'71 Note: FO2 and FO3 are undefined. Figure 21.22 Status Read Mode Timing Waveforms Table 21.19 Status Read Mode Return Codes Pin FO7 FO6 Attribute Normal end Command identification error Initial value 0 Indications FO5 FO4 FO3 FO2 FO1 Programming Erase error error -- -- Programming Valid or erase address count error exceeded 0 0 0 0 0 0 Normal end: 0 Command error: 1 Programming Erase error: 1 error: 1 -- -- Count exceeded: 1 Abnormal end: 1 Otherwise: Otherwise: 0 0 Valid address error: 1 0 Otherwise: 0 Otherwise: 0 FO0 Otherwise: 0 Note: FO2 and FO3 are undefined. Status Polling 1. In FO7 status polling, FO7 is a flag that indicates the operating status in auto-program or autoerase mode. 2. In FO6 status polling, FO6 is a flag that indicates a normal or abnormal end in auto-program or auto-erase mode. Table 21.20 Status Polling Output Truth Table Pin Internal Operation in Progress Abnormal End -- Normal End FO7 0 1 0 1 FO6 0 0 1 1 FO0-FO5 0 0 0 0 538 Writer Mode Transition Time: Commands cannot be accepted during the oscillation settling period or the writer mode setup period. After the writer mode setup time, a transition is made to memory read mode. Table 21.21 Stipulated Transition Times to Command Wait State Item Symbol Min Standby release (oscillation settling time) t osc1 10 ms Writer mode setup time t bmv 10 ms VCC hold time t dwn 0 ms VCC tosc1 Max Unit tdwn tbmv Memory read mode RES Notes Auto-program mode Auto-erase mode Command wait state Command acceptance Command wait state Normal/ abnormal end identification Figure 21.23 Oscillation Settling Time, Boot Program Transfer Time, and Power-Down Sequence Cautions on Memory Programming 1. When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. 2. When performing programming using writer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out autoprogramming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. Auto-programming should be performed once only on the same address block. 539 21.6 Flash Memory Programming and Erasing Precautions Read these precautions before using writer mode, on-board programming mode, or flash memory emulation by RAM. (1) Program with the specified voltage and timing. When using a PROM programmer to reprogram the on-chip flash memory in the single-powersupply model (S-mask model), use a PROM programmer that supports the Hitachi microcomputer device type with 64-kbyte on-chip flash memory (5.0 V programming voltage), do not set the programmer to the HN28F101 3.3 V programming voltage and only use the specified socket adapter. Failure to observe these precautions may result in damage to the device. (2) Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can occur if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (3) Don't touch the socket adapter or chip while programming. Touching either of these can cause contact faults and write errors. (4) Set H'FF as the PROM programmer buffer data for addresses H'F780 to H'1FFFF. The H8/3437SF PROM size is 60 kbytes. Addresses H'F780 to H'1FFFF always read H'FF, so if H'FF is not specified as programmer data, a block error will occur. (5) Use the recommended algorithms for programming and erasing flash memory. These algorithms are designed to program and erase without subjecting the device to voltage stress and without sacrificing the reliability of programmed data. Before setting the program (P) or erase (E) bit in flash memory control register 1 (FLMCR1), set the watchdog timer to ensure that the P or E bit does not remain set for more than the specified time. (6) For details on interrupt handling while flash memory is being programmed or erased, see section 21.4.6, Interrupt Handling during Flash Memory Programming and Erasing. (7) Cautions on Accessing Flash Memory Control Registers 1. Flash memory control register access state in each operating mode The H8/3437SF has flash memory control registers located at addresses H'FF80 (FLMCR1), H'FF81 (FLMCR2), and H'FF83 (EBR2). These registers can only be accessed when the FLSHE bit is set to 1 in the wait-state control register (WSCR). Table 21.22 shows the area accessed for the above addresses in each mode, when FLSHE = 0 and when FLSHE = 1. 540 Table 21.22 Area Accessed in Each Mode with FLSHE = 0 and FLSHE = 1 FLSHE = 1 Mode 1 Mode 2 Mode 3 Reserved area (always H'FF) Flash memory control register initial values FLLMCR1 = H'80 FLMCR2 = H'00 EBR2 = H'00 FLSHE = 0 External address space External address space Reserved area (always H'FF) 2. When a flash memory control register is accessed in mode 2 (expanded mode with on-chip ROM enabled) When a flash memory control register is accessed in mode 2, it can be read or written to if FLSHE = 1, but if FLSHE = 0, external address space will be accessed. It is therefore essential to confirm that FLSHE is set to 1 before accessing these registers. 3. To check whether FLSHE = 0 or 1 in mode 3 (single-chip mode) When address H'FF80 is accessed in mode 3, if FLSHE = 1, FLMCR1 is read/written to, and its initial value after a reset is H'80. When FLSHE = 0, however, this address is a reserved area that cannot be modified and always reads H'FF. 541 542 Section 22 Power-Down State 22.1 Overview The H8/3437 Series has a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. The power-down state includes three modes: 1. Sleep mode 2. Software standby mode 3. Hardware standby mode Table 22.1 lists the conditions for entering and leaving the power-down modes. It also indicates the status of the CPU, on-chip supporting modules, etc. in each power-down mode. Table 22.1 Power-Down State Mode Sleep mode Software standby mode Entering Procedure Clock CPU CPU Reg's. Sup. Mod. RAM I/O Ports Exiting Methods Execute SLEEP instruction Run Halt Held Run Held Held * Interrupt Set SSBY bit in SYSCR to 1, then execute SLEEP instruction Halt * RES * STBY Halt Held Halt and Held initialized Held * NMI * IRQ0-IRQ2 IRQ6 (incl. KEYIN0- KEYIN15 ) * RES * STBY Hardware Set STBY standby pin to low mode level Halt Halt Not held Halt and Held initialized High impedance state * STBY and RES Notes: 1. SYSCR: System control register 2. SSBY: Software standby bit 543 22.1.1 System Control Register (SYSCR) Four of the eight bits in the system control register (SYSCR) control the power-down state. These are bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0). See table 22.2. Table 22.2 System Control Register Name Abbreviation R/W Initial Value Address System control register SYSCR R/W H'09 H'FFC4 Bit 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R R/W R/W R/W Bit 7--Software Standby (SSBY): This bit enables or disables the transition to software standby mode. On recovery from the software standby mode by an external interrupt, SSBY remains set to 1. To clear this bit, software must write a 0. Bit 7: SSBY Description 0 The SLEEP instruction causes a transition to sleep mode. 1 The SLEEP instruction causes a transition to software standby mode. 544 (Initial value) Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from software standby mode by an external interrupt. During the selected time, the clock oscillator runs but the CPU and on-chip supporting modules remain in standby. Set bits STS2 to STS0 according to the clock frequency to obtain a settling time of at least 8 ms. See table 22.3. * ZTAT and Mask ROM Versions Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description 0 0 0 Settling time = 8,192 states 1 Settling time = 16,384 states 0 Settling time = 32,768 states 1 Settling time = 65,536 states 0 -- Settling time = 131,072 states 1 -- Unused 1 1 (Initial value) * F-ZTAT Version Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description 0 0 0 Settling time = 8,192 states 1 Settling time = 16,384 states 0 Settling time = 32,768 states 1 Settling time = 65,536 states 0 Settling time = 131,072 states 1 Settling time = 1,024 states -- Unused 1 1 0 1 (Initial value) Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted. If a period exceeding op/1,024 (e.g. op/2,048) is specified when selecting the 8-bit timer, PWM timer, or watchdog timer clock, the counter in the timer will not count up normally when 1,024 states is specified for the settling time. To avoid this problem, set the STS value just before the transition to software standby mode (before executing the SLEEP instruction), and re-set the value of STS2 to STS0 to a value from 000 to 100 directly after software standby mode is cleared by an interrupt. 545 22.2 Sleep Mode 22.2.1 Transition to Sleep Mode When the SSBY bit in the system control register is cleared to 0, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The on-chip supporting modules continue to operate normally. 22.2.2 Exit from Sleep Mode The chip exits sleep mode when it receives an internal or external interrupt request, or a low input at the RES or STBY pin. Exit by Interrupt: An interrupt releases sleep mode and starts the CPU's interrupt-handling sequence. If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module's control register, the interrupt cannot be requested, so it cannot wake the chip up. Similarly, the CPU cannot be awakened by an interrupt other than NMI if the I (interrupt mask) bit is set when the SLEEP instruction is executed. Exit by RES Pin: When the RES pin goes low, the chip exits from sleep mode to the reset state. Exit by STBY Pin: When the STBY pin goes low, the chip exits from sleep mode to hardware standby mode. 546 22.3 Software Standby Mode 22.3.1 Transition to Software Standby Mode To enter software standby mode, set the standby bit (SSBY) in the system control register (SYSCR) to 1, then execute the SLEEP instruction. In software standby mode, the system clock stops and chip functions halt, including both CPU functions and the functions of the on-chip supporting modules. Power consumption is reduced to an extremely low level. The on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained, the contents of the CPU registers and on-chip RAM remain unchanged. 22.3.2 Exit from Software Standby Mode The chip can be brought out of software standby mode by an RES input, STBY input, or external interrupt input at the NMI pin, IRQ 0 to IRQ 2 pins, or IRQ 6 pin (including KEYIN 0 to KEYIN 15). Exit by Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, or IRQ6 interrupt request signal is input, the clock oscillator begins operating. After the waiting time set in bits STS2 to STS0 of SYSCR, a stable clock is supplied to the entire chip, software standby mode is released, and interrupt exception-handling begins. IRQ3, IRQ4, IRQ5, and IRQ7 interrupts should be disabled before the transition to software standby (clear IRQ3E, IRQ4E, IRQ5E, and IRQ7E to 0). Exit by RES Pin: When the RES input goes low, the clock oscillator begins operating. When RES is brought to the high level (after allowing time for the clock oscillator to settle), the CPU starts reset exception handling. Be sure to hold RES low long enough for clock oscillation to stabilize. Exit by STBY Pin: When the STBY input goes low, the chip exits from software standby mode to hardware standby mode. 547 22.3.3 Clock Settling Time for Exit from Software Standby Mode Set bits STS2 to STS0 in SYSCR as follows: * Crystal oscillator Set STS2 to STS0 for a settling time of at least 8 ms. Table 22.3 lists the settling times selected by these bits at several clock frequencies. * External clock The STS bits can be set to any value. When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted. If a period exceeding op/1,024 (e.g. op/2,048) is specified when selecting the 8-bit timer, PWM timer, or watchdog timer clock, the counter in the timer will not count up normally when 1,024 states is specified for the settling time. To avoid this problem, set the STS value just before the transition to software standby mode (before executing the SLEEP instruction), and re-set the value of STS2 to STS0 to a value from 000 to 100 directly after software standby mode is cleared by an interrupt. Table 22.3 Times Set by Standby Timer Select Bits (Unit: ms) STS2 STS1 STS0 Settling Time (States) 0 0 0 8,192 0.51 0.65 0.8 1.0 1.3 2.0 4.1 8.2 16.4 0 0 1 16,384 1.0 1.3 1.6 2.0 2.7 4.1 8.2 16.4 32.8 0 1 0 32,768 2.0 2.7 3.3 4.1 5.5 8.2 16.4 32.8 65.5 0 1 1 65,536 4.1 5.5 6.6 8.2 10.9 16.4 32.8 65.5 131.1 1 0 0/--* 131,072 8.2 10.9 13.1 16.4 21.8 32.8 65.5 131.1 262.1 System Clock Frequency (MHz) 16 12 10 8 6 4 2 1 0.5 Notes: 1. All times are in milliseconds. 2. Recommended values are printed in boldface. * F-ZTAT version/ZTAT and mask-ROM versions 548 22.3.4 Sample Application of Software Standby Mode In this example the chip enters the software standby mode when NMI goes low and exits when NMI goes high, as shown in figure 22.1. The NMI edge bit (NMIEG) in the system control register is originally cleared to 0, selecting the falling edge. When NMI goes low, the NMI interrupt handling routine sets NMIEG to 1, sets SSBY to 1 (selecting the rising edge), then executes the SLEEP instruction. The chip enters software standby mode. It recovers from software standby mode on the next rising edge of NMI. Clock oscillator o NMI NMIEG SSBY NMI interrupt handler NMIEG = 1 SSBY = 1 Software standby mode (powerdown state) Settling time NMI interrupt handler SLEEP Figure 22.1 NMI Timing in Software Standby Mode 549 22.3.5 Application Note 1. The I/O ports retain their current states in software standby mode. If a port is in the high output state, the current dissipation caused by the output current is not reduced. * * * BSET SLEEP #7, @SYSCR:8 * * * ; Sets the SSBY bit ; Executes the SLEEP instruction Replace the underlined part (SLEEP instruction) with the code shown below. * * * BSET MOV. W MOV. W MOV. W MOV. W JSR #7, @SYSCR:8 #H'0180, R0 R0, @H'FF00 #H'5470, R0 R0, @H'FF02 @H'FF00 * * * ; Sets the SSBY bit ; Writes the SLEEP code H'0180 ; to the RAM ; Writes the RTS code H'5470 ; to the RAM ; Subroutine branch * Registers and RAM addresses are arbitrary. Note: The current responsible for this phenomenon also flows when the mode is changed to SLEEP mode. In order to reduce current dissipation, therefore, please use the preliminary remedy for the SLEEP instruction when changing the mode to SLEEP mode. 550 22.4 Hardware Standby Mode 22.4.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting the CPU, stopping all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state. The registers of the on-chip supporting modules are reset to their initial values. Only the onchip RAM is held unchanged, provided the minimum necessary voltage supply is maintained. Notes: 1. The RAME bit in the system control register should be cleared to 0 before the STBY pin goes low. 2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby mode. Be particularly careful not to let both mode pins go low in hardware standby mode, since that places the chip in writer mode and increases current dissipation. 22.4.2 Recovery from Hardware Standby Mode Recovery from the hardware standby mode requires inputs at both the STBY and RES pins. When the STBY pin goes high, the clock oscillator begins running. The RES pin should be low at this time and should be held low long enough for the clock to stabilize. When the RES pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state. 551 22.4.3 Timing Relationships Figure 22.2 shows the timing relationships in hardware standby mode. In the sequence shown, first RES goes low, then STBY goes low, at which point the chip enters hardware standby mode. To recover, first STBY goes high, then after the clock settling time, RES goes high. Clock pulse generator RES STBY Clock settling time Restart Figure 22.2 Hardware Standby Mode Timing 552 Section 23 Electrical Specifications 23.1 Absolute Maximum Ratings Table 23.1 lists the absolute maximum ratings. Table 23.1 Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage VCC -0.3 to +7.0 V I/O buffer supply voltage VCCB -0.3 to +7.0 V Flash memory programming voltage (Dual-power-supply F-ZTATTM version) FV PP -0.3 to +13.0 V Programming voltage VPP -0.3 to +13.5 V Pins other than Vin ports 7, MD1, P86, P97, PA7 to PA 4 -0.3 to VCC + 0.3 V P86, P97, PA7 to PA 4 Vin -0.3 to VCCB + 0.3 V Port 7 Vin -0.3 to AVCC + 0.3 V MD1 Vin Dual-power-supply F-ZTAT version: -0.3 to +13.0 Other versions: -0.3 to V CC + 0.3 V Reference supply voltage AVref -0.3 to AVCC + 0.3 V Analog supply voltage AVCC -0.3 to +7.0 V Analog input voltage VAN -0.3 to AVCC + 0.3 V Operating temperature Topr Regular specifications: -20 to +75 C Wide-range specifications: -40 to +85 C -55 to +125 C Input voltage Storage temperature Tstg Caution: Exceeding the absolute maximum ratings shown in table 23.1 can permanently destroy the chip.* Note: * FV PP must not exceed 13 V and V PP must not exceed 13.5 V, including allowances for peak overshoot. For the dual-power-supply F-ZTAT version, MD1 must not exceed 13 V, including an allowance for peak overshoot. 553 23.2 Electrical Characteristics 23.2.1 DC Characteristics Table 23.2 lists the DC characteristics of the 5-V version. Table 23.3 lists the DC characteristics of 4-V version. Table 23.4 lists the DC characteristics of the 3 V version. Table 23.5 gives the allowable current output values of the 5-V and 4-V versions. Table 23.6 gives the allowable current output values of the 3-V version. Bus drive characteristics common to 5-V, 4-V and 3-V versions are listed in table 23.7. Table 23.2 DC Characteristics (5-V Version) Conditions: VCC = 5.0 V 10%, V CCB = 5.0 V 10%, AVCC = 5.0 V 10%*1, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol (1) *7 VT- Schmitt P67 to P6 0*4, trigger input KEYIN15 to VT+ voltage KEYIN8, IRQ2 to IRQ 0*5, VT+ - VT- IRQ7 to IRQ 3 Input high voltage Input low voltage RES, STBY, MD1, MD0, EXTAL, NMI (2) Typ Max Unit 1.0 -- -- V -- -- VCC x 0.7 VCCB x 0.7 0.4 -- -- VCC - 0.7 -- VCC + 0.3 PA7 to PA 0*7 SCL, SDA VCC x 0.7 -- VCCB x 0.7 VCC + 0.3 VCCB + 0.3 P77 to P7 0 2.0 -- AVCC + 0.3 All input pins other than (1) and (2) above *7 2.0 -- VCC + 0.3 VCCB + 0.3 -0.3 -- 0.5 PA7 to PA 0 SCL, SDA -0.3 -- 1.0 All input pins other than (1) and (3) above -0.3 -- 0.8 RES, STBY, MD1, MD0 (3) Output high All output pins voltage (except RESO) *6, *7 554 VIH Min VIL VOH VCC - 0.5 -- VCCB - 0.5 -- 3.5 -- -- Test Conditions V V V I OH = -200 A I OH = -1.0 mA Symbol Min Typ Max Unit Test Conditions VOL -- -- 0.4 V I OL = 1.6 mA P17 to P1 0, P27 to P2 0 -- -- 1.0 I OL = 10.0 mA RESO -- -- 0.4 I OL = 2.6 mA -- -- 10.0 NMI, MD1, MD0 -- -- 1.0 P77 to P7 0 -- -- 1.0 Item Output low voltage All output pins (except RESO) *6 A Input leakage current RES, STBY Leakage current in three-state (off state) Ports 1 to 6, 8, 9, A, B, RESO *7 | ITSI | -- -- 1.0 A Vin = 0.5 V to VCC - 0.5 V, Vin = 0.5 V to VCCB - 0.5 V Input pullup MOS current Ports 1 to 3 -I P 30 -- 250 A Vin = 0 V 60 -- 500 -- -- 120 pF Vin = 0 V, f = 1 MHz, Ta = 25C RES, STBY (except dualpower-supply F-ZTAT version) -- -- 60 NMI, MD1 -- -- 50 PA7 to PA 4, P97, P86 -- -- 20 All input pins other than (4) -- -- 15 -- 27 45 mA f = 12 MHz -- 36 60 f = 16 MHz -- 18 30 f = 12 MHz -- 24 40 f = 16 MHz | Iin | Ports 6, A, B Input STBY (dualcapacitance power-supply F-ZTAT version) (4) Current Normal operation dissipation *2 Sleep mode Cin I CC Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V 555 Item Symbol Min Typ Max Unit Test Conditions Current Standby modes *3 *2 dissipation I CC -- 0.01 5.0 A Ta 50C -- -- 20.0 Analog supply current AI CC -- 1.2 2.0 During A/D and D/A conversion -- 1.2 2.0 A/D and D/A conversion idle -- 0.01 5.0 A -- 0.3 0.6 mA During A/D and D/A conversion -- 1.3 3.0 A/D and D/A conversion idle -- 0.01 5.0 A AVref = 2.0 V to 5.5 V 4.5 -- 5.5 V During operation 2.0 -- 5.5 2.0 -- -- Reference supply current During A/D conversion During A/D conversion Analog supply voltage*1 RAM standby voltage AI ref AVCC VRAM 50C < Ta mA AVCC = 2.0 V to 5.5 V While idle or when not in use V Notes: *1 Even when the A/D and D/A converters are not used, connect AVCC to power supply VCC and keep the applied voltage between 2.0 V and 5.5 V. At this time, make sure AVref AVCC. *2 Current dissipation values assume that V IH min = VCC - 0.5 V, VCCB - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. *3 For these values it is assumed that V RAM VCC < 4.5 V and VIH min = VCC x 0.9, VCCB x 0.9, VIL max = 0.3 V. *4 P67 to P6 0 include supporting module inputs multiplexed with them. *5 IRQ2 includes ADTRG multiplexed with it. *6 Applies when IICS = IICE = 0. The output low level is determined separately when the bus drive function is selected. *7 The characteristics of PA7 to PA 4, KEYIN15 to KEYIN12 , P97/WAIT, SDA, and P86/IRQ5/SCK1, SCL depend on VCCB; the characteristics of all other pins depend on VCC. 556 Table 23.3 DC Characteristics (4-V Version) Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V*1, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Min Typ Max Unit 1.0 -- -- V -- -- VCC x 0.7 VCCB x 0.7 0.4 -- -- 0.8 -- -- -- -- VCC x 0.7 VCCB x 0.7 VT+ - VT- 0.3 -- -- VIH VCC - 0.7 -- VCC + 0.3 (1) *7 VT- Schmitt P67 to P6 0*4, trigger input KEYIN15 to, VT+ voltage KEYIN8, IRQ2 to IRQ0*5, VT+ - VT- IRQ7 to IRQ3 VT- VT Input high voltage Input low voltage RES, STBY, MD1, MD0, EXTAL, NMI (2) + Test Conditions VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V V PA7 to PA 0*7 SCL, SDA VCC x 0.7 -- VCCB x 0.7 VCC + 0.3 VCCB + 0.3 P77 to P7 0 2.0 -- AVCC + 0.3 All input pins other than (1) and (2) above *7 2.0 -- VCC + 0.3 VCCB + 0.3 -0.3 -- 0.5 -0.3 -- 1.0 VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V -0.3 -- 0.8 VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V -0.3 -- 0.8 VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V -0.3 -- 0.6 VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V RES, STBY, MD1, MD0 (3) PA7 to PA 0*7 SCL, SDA All input pins other than (1) and (3) above *7 VIL V 557 Max Unit Test Conditions VCC - 0.5 -- VCCB - 0.5 -- V I OH = -200 A 3.5 -- -- I OH = -1.0 mA, VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V 2.8 -- -- I OH = -1.0 mA, VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V -- -- 0.4 P17 to P1 0, P27 to P2 0 -- -- 1.0 I OL = 10.0 mA RESO -- -- 0.4 I OL = 2.6 mA Item Symbol Min Output high All output pins voltage (except RESO)*6, *7 VOH Output low voltage All output pins (except RESO)*6 Input leakage current RES, STBY Leakage current in three-state (off state) Ports 1 to 6, 8, 9, A, B, RESO *7 Ports 1 to 3 Input pullup MOS current | Iin | V A I OL = 1.6 mA -- -- 10.0 NMI, MD1, MD0 -- -- 1.0 P77 to P7 0 -- -- 1.0 | ITSI | -- -- 1.0 A Vin = 0.5 V to VCC - 0.5 V, Vin = 0.5 V to VCCB - 0.5 V -I P A Vin = 0 V, VCC = 4.5 V to 5.5 V, VCCB = 4.5 V to 5.5 V 30 -- 250 Ports 6, A, B *7 60 -- 500 Ports 1 to 3 20 -- 200 40 -- 400 Ports 6, A, B 558 VOL Typ *7 Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V Vin = 0 V, VCC = 4.0 V to 4.5 V, VCCB = 4.0 V to 4.5 V Item Min Typ Max Unit Cin -- -- 120 pF Vin = 0 V, f = 1 MHz, Ta = 25C RES, STBY (except dualpower-supply F-ZTAT version) -- -- 60 NMI, MD1 -- -- 50 PA7 to PA 4, P97, P8 6 -- -- 20 All input pins other than (4) above -- -- 15 -- 27 45 mA f = 12 MHz -- 36 60 f = 16 MHz, VCC = 4.5 V to 5.5 V -- 18 30 f = 12 MHz -- 24 40 f = 16 MHz VCC = 4.5 V to 5.5 V -- 0.01 5.0 -- -- 20.0 -- 1.2 2.0 During A/D and D/A conversion -- 1.2 2.0 A/D and D/A conversion idle -- 0.01 5.0 Input STBY (dualcapacitance power-supply F-ZTAT version) (4) Current Normal operation dissipation *2 I CC Sleep mode Standby modes *3 Analog supply current Test Conditions Symbol During A/D conversion AI CC A Ta 50C 50C < Ta mA A AVCC = 2.0 V to 5.5 V 559 Item Reference supply current Test Conditions Symbol Min Typ Max Unit AI ref -- 0.3 0.6 mA During A/D and D/A conversion -- 1.3 3.0 A/D and D/A conversion idle -- 0.01 5.0 A AVref = 2.0 V to 5.5 V 4.0 -- 5.5 V During operation 2.0 -- 5.5 2.0 -- -- During A/D conversion Analog supply voltage*1 RAM standby voltage AVCC VRAM While idle or when not in use V Notes: *1 Even when the A/D and D/A converters are not used, connect AVCC to power supply VCC and keep the applied voltage between 2.0 V and 5.5 V. At this time, make sure AVref AVCC. *2 Current dissipation values assume that V IH min = VCC - 0.5 V, VCCB - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. *3 For these values it is assumed that V RAM VCC < 4.0 V and VIH min = VCC x 0.9, VCCB x 0.9, VIL max = 0.3 V. *4 P67 to P6 0 include supporting module inputs multiplexed with them. *5 IRQ2 includes ADTRG multiplexed with it. *6 Applies when IICS = IICE = 0. The output low level is determined separately when the bus drive function is selected. *7 The characteristics of PA7 to PA 4, KEYIN15 to KEYIN12 , P97/WAIT, SDA, and P86/IRQ5/SCK1, SCL depend on VCCB; the characteristics of all other pins depend on VCC. 560 Table 23.4 DC Characteristics (3-V Version) Conditions: VCC = 2.7 V to 5.5 V*8, VCCB = 2.7 V to 5.5 V*8, AVCC = 2.7 V to 5.5 V*1, *8, AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C Item Symbol Schmitt P67 to P6 0*4, (1) *7 VT- trigger input KEYIN15 to, voltage KEYIN8, VT+ IRQ2 to IRQ0*5, IRQ7 to IRQ3 VT+ - VT- Input high voltage Input low voltage*4 RES, STBY, MD1, MD0, EXTAL, NMI (2) Typ Max Unit VCC x 0.15 -- VCCB x 0.15 -- V -- -- VCC x 0.7 VCCB x 0.7 0.2 -- -- VCC x 0.9 -- VCC + 0.3 PA7 to PA 0*7 SCL, SDA VCC x 0.7 -- VCC B x 0.7 VCC + 0.3 VCCB + 0.3 P77 to P7 0 AVCC x 0.7 -- AVCC + 0.3 All input pins other than (1) and (2) above *7 VCC x 0.7 -- VCCB x 0.7 VCC + 0.3 VCCB + 0.3 -0.3 -- VCC x 0.1 PA7 to PA 0*7 SCL, SDA -0.3 -- VCC x 0.15 VCCB x 0.15 All input pins other than (1) and (3) above *7 -0.3 -- VCC x 0.15 VCCB x 0.15 RES, STBY, MD1, MD0 (3) Output high All output pins voltage (except RESO)*6, *7 Output low voltage VIH Min VIL V V I OH = -200 A VCC - 0.5 -- VCCB - 0.5 -- VCC - 1.0 -- VCCB - 1.0 -- -- -- 0.4 P17 to P1 0, P27 to P2 0 -- -- 0.4 I OL = 1.6 mA RESO -- -- 0.4 I OL = 1.6 mA All output pins (except RESO)*6 VOH Test Conditions VOL V I OH = -1 mA V I OL = 0.8 mA 561 Item Symbol Min Typ Max Unit | Iin | -- -- 10.0 A NMI, MD1, MD0 -- -- 1.0 P77 to P7 0 -- -- 1.0 Test Conditions Input leakage current RES, STBY Leakage current in three-state (off state) Ports 1 to 6, 8, 9, A, B, RESO *7 | ITSI | -- -- 1.0 A Vin = 0.5 V to VCC - 0.5 V, Vin = 0.5 V to VCCB - 0.5 V Input pullup MOS current Ports 1 to 3 -I P 3 -- 120 A 30 -- 250 Vin = 0 V, VCC = 2.7 V to 3.6 V, VCCB = 2.7 V to 3.6 V -- -- 120 pF Vin = 0 V, f = 1 MHz, Ta = 25C RES, STBY (except dualpower-supply F-ZTAT version) -- -- 60 NMI, MD1 -- -- 50 PA7 to PA 4, P97, P8 6 -- -- 20 All input pins other than (4) above -- -- 15 Ports 6, A, B *7 Input STBY (dualcapacitance power-supply F-ZTAT version) 562 (4) Cin Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V Test Conditions Item Symbol Min Typ Max Unit Normal operation Current dissipation *2 I CC -- 7 -- mA -- 12 22 f = 10 MHz, VCC = 2.7 V to 3.6 V -- 25 -- f = 10 MHz, VCC = 4.0 V to 5.5 V -- 5 -- f = 6 MHz, VCC = 2.7 V to 3.6 V -- 9 16 f = 10 MHz, VCC = 2.7 V to 3.6 V -- 18 -- f = 10 MHz, VCC = 4.0 V to 5.5 V -- 0.01 5.0 -- -- 20.0 -- 1.2 2.0 During A/D and D/A conversion -- 1.2 2.0 A/D and D/A conversion idle -- 0.01 5.0 A -- 0.3 0.6 mA During A/D and D/A conversion -- 1.3 3.0 A/D and D/A conversion idle -- 0.01 5.0 Sleep mode Standby modes *3 Analog supply current Reference supply current During A/D conversion During A/D conversion AI CC AI ref A f = 6 MHz, VCC = 2.7 V to 3.6 V Ta 50C 50C < Ta mA A AVCC = 2.0 V to 5.5 V AVref = 2.0 V to 5.5 V 563 Item Symbol Min Typ Max Unit Analog supply voltage*1 AVCC 2.7 -- 5.5 V 2.0 -- 5.5 2.0 -- -- RAM standby voltage VRAM Test Conditions During operation While idle or when not in use V Notes: *1 Even when the A/D and D/A converters are not used, connect AVCC to power supply VCC and keep the applied voltage between 2.0 V and 5.5 V. At this time, make sure AVref AVCC. *2 Current dissipation values assume that V IH min = VCC - 0.5 V, VCCB - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. *3 For these values it is assumed that V RAM VCC < 2.7 V and VIH min = VCC x 0.9, VCCB x 0.9, VIL max = 0.3 V. *4 P67 to P6 0 include supporting module inputs multiplexed with them. *5 IRQ2 includes ADTRG multiplexed with it. *6 Applies when IICS = IICE = 0. The output low level is determined separately when the bus drive function is selected. *7 The characteristics of PA7 to PA 4, KEYIN15 to KEYIN12 , P97/WAIT, SDA, and P86/IRQ5/SCK1, SCL depend on VCCB; the characteristics of all other pins depend on VCC. *8 In the F-ZTAT LH version, V CC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V. 564 Table 23.5 Allowable Output Current Values (5-V and 4-V Versions) Conditions: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Allowable output low current (per pin) Allowable output low current (total) Symbol Min Typ Max Unit SCL, SDA, PA4 to PA 7 I OL (bus drive selection) -- -- 20 mA Ports 1 and 2 -- -- 10 RESO -- -- 3 Other output pins -- -- 2 -- -- 80 -- -- 120 Ports 1 and 2, total IOL Total of all output mA Allowable output high current (per pin) All output pins -I OH -- -- 2 mA Allowable output high current (total) Total of all output -IOH -- -- 40 mA 565 Table 23.6 Allowable Output Current Values (3-V Version) Conditions: VCC = 2.7 V to 5.5 V*, VCCB = 2.7 V to 5.5 V*, AVCC = 2.7 V to 5.5 V*, AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C Item Symbol Allowable output low current (per pin) Allowable output low current (total) Min Typ Max Unit SCL, SDA, PA4 to PA 7 I OL (bus drive selection) -- -- 10 mA Ports 1 and 2 -- -- 2 RESO -- -- 1 Other output pins -- -- 1 -- -- 40 -- -- 60 Ports 1 and 2, total IOL Total of all output mA Allowable output high current (per pin) All output pins -I OH -- -- 2 mA Allowable output high current (total) Total of all output -IOH -- -- 30 mA Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current values in tables 23.5 and 23.6. In particular, when driving a darlington transistor pair or LED directly, be sure to insert a current-limiting resistor in the output path. See figures 23.1 and 23.2. * In the F-ZTAT LH version, V CC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V. H8/3437 2 k Port Darlington transistor Figure 23.1 Example of Circuit for Driving a Darlington Transistor (5-V Version) 566 H8/3437 VCC 600 Ports 1 or 2 LED Figure 23.2 Example of Circuit for Driving an LED (5-V Version) Table 23.7 Bus Drive Characteristics Conditions: VCC = 2.7 V to 5.5 V*, VSS = 0 V, Ta = -20C to +75C Item Output low level voltage SCL, SDA PA4 to PA 7 (bus drive selection) Symbol Min Typ Max Unit Test Condition VOL -- -- 0.5 V VCCB = 5 V 10% I OL = 16 mA -- -- 0.5 VCCB = 2.7 V to 5.5 V* I OL = 8 mA -- -- 0.4 VCCB = 2.7 V to 5.5 V* I OL = 3 mA Note: * In the F-ZTAT LH version, VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V. 23.2.2 AC Characteristics The AC characteristics are listed in four tables. Bus timing parameters are given in table 23.8, control signal timing parameters in table 23.9, timing parameters of the on-chip supporting modules in table 23.10, I2C bus timing parameters in table 23.11, and external clock output stabilization delay time in table 23.12. 567 Table 23.8 Bus Timing Condition A: VCC = 5.0 V 10%, V CCB = 5.0 V 10%, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C: VCC = 2.7 V to 5.5 V*3, VCCB = 2.7 V to 5.5 V*3, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C Condition C Condition B Condition A 10 MHz 12 MHz 16 MHz Item Symbol Min Max Min Max Min Max Unit Test Conditions Clock cycle time tcyc 100 500 83.3 500 62.5 500 ns Fig. 23.7 Clock pulse width low tCL 30 -- 30 -- 20 -- ns Clock pulse width high tCH 30 -- 30 -- 20 -- ns Clock rise time tCr -- 20 -- 10 -- 10 ns Clock fall time tCf -- 20 -- 10 -- 10 ns Address delay time tAD -- 50 -- 35 -- 30 ns Address hold time tAH 20 -- 15 -- 10 -- ns Address strobe delay time tASD -- 50 -- 35 -- 30 ns Write strobe delay time tWSD -- 50 -- 35 -- 30 ns tSD -- 50 -- 35 -- 30 ns Strobe delay time *1 Write strobe pulse width tWSW 110 -- 90 -- 60 -- ns *1 Address setup time 1 tAS1 15 -- 10 -- 10 -- ns Address setup time 2*1 tAS2 65 -- 50 -- 40 -- ns Read data setup time tRDS 35 -- 20 -- 20 -- ns tRDH 0 -- 0 -- 0 -- ns Read data access time tACC -- 170 -- 160 -- 110 ns Write data delay time tWDD -- 80/75*2 -- 65/60*2 -- 60 ns Read data hold time *1 *1 *2 *2 *2 Write data setup time tWDS 0/5 -- 0/5 -- 0/5 -- ns Write data hold time tWDH 20 -- 20 -- 20 -- ns Wait setup time tWTS 40 -- 35 -- 30 -- ns Wait hold time tWTH 10 -- 10 -- 10 -- ns Notes: *1 Values at maximum operating frequency *2 H8/3437 F-ZTAT version/other products *3 In the F-ZTAT LH version, V CC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V 568 Fig. 23.8 Table 23.9 Control Signal Timing Condition A: VCC = 5.0 V 10%, V CCB = 5.0 V 10%, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C: VCC = 2.7 V to 5.5 V*, VCCB = 2.7 V to 5.5 V*, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20C to +75C Condition C Condition B Condition A 10 MHz 12 MHz 16 MHz Item Symbol Min Max Min Max Min Max Unit Test Conditions RES setup time tRESS 300 -- 200 -- 200 -- ns Fig. 23.9 RES pulse width tRESW 10 -- 10 -- 10 -- tcyc RESO output delay time tRESD -- 200 -- 120 -- 100 ns RESO output pulse width tRESOW 132 -- 132 -- 132 -- tcyc NMI setup time (NMI, IRQ0 to IRQ7) tNMIS 300 -- 150 -- 150 -- ns NMI hold time (NMI, IRQ0 to IRQ7) tNMIH 10 -- 10 -- 10 -- ns Interrupt pulse width for recovery from software standby mode (NMI, IRQ0 to IRQ2, IRQ6) tNMIW 300 -- 200 -- 200 -- ns Crystal oscillator settling time (reset) tOSC1 20 -- 20 -- 20 -- ms Fig. 23.11 Crystal oscillator settling time (software standby) tOSC2 8 -- 8 -- 8 -- ms Fig. 23.12 Fig. 23.25 Fig. 23.10 Note: * In the F-ZTAT LH version, V CC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V. 569 Measurement Conditions for AC Characteristics 5V RL LSI output pin RH C = 90 pF: Ports 1-4, 6, 9, A, B 30 pF: Ports 5, 8 RL = 2.4 k RH = 12 k C Input/output timing measurement levels Low: 0.8 V High: 2.0 V Figure 23.3 Measurement Conditions for A/C Characteristics 570 Table 23.10 Timing Conditions of On-Chip Supporting Modules Condition A: VCC = 5.0 V 10%, V CCB = 5.0 V 10%, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition C: VCC = 2.7 V to 5.5 V*, VCCB = 2.7 V to 5.5 V*, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20C to +75C Condition C Condition B 10 MHz Condition A 12 MHz 16 MHz Symbol Min Max Min Max Min Max Unit Test Conditions Timer output delay time tFTOD -- 150 -- 100 -- 100 ns Fig. 23.13 Timer input setup time tFTIS 80 -- 50 -- 50 -- ns Timer clock input setup time tFTCS 80 -- 50 -- 50 -- ns Timer clock pulse width tFTCWH tFTCWL 1.5 -- 1.5 -- 1.5 -- tcyc Timer output delay time tTMOD -- 150 -- 100 -- 100 ns Fig. 23.15 Timer reset input setup time tTMRS 80 -- 50 -- 50 -- ns Fig. 23.17 Timer clock input setup time tTMCS 80 -- 50 -- 50 -- ns Fig. 23.16 Timer clock pulse width (single edge) tTMCWH 1.5 -- 1.5 -- 1.5 -- tcyc Timer clock pulse width (both edges) tTMCWL 2.5 -- 2.5 -- 2.5 -- tcyc PWM Timer output delay time tPWOD -- 150 -- 100 -- 100 ns Fig. 23.18 SCI Input clock (Async) tScyc cycle (Sync) 4 -- 4 -- 4 -- tcyc Fig. 23.19 6 -- 6 -- 6 -- tcyc Transmit data delay tTXD time (Sync) -- 200 -- 100 -- 100 ns Receive data setup time (Sync) tRXS 150 -- 100 -- 100 -- ns Receive data hold time (Sync) tRXH 150 -- 100 -- 100 -- ns Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc Item FRT TMR Fig. 23.14 Fig. 23.20 571 HIF read cycle HIF write cycle Condition B Condition A 10 MHz 12 MHz 16 MHz Symbol Min Max Min Max Min Max Unit Test Conditions Output data delay time tPWD -- 150 -- 100 -- 100 ns Fig. 23.21 Input data setup time tPRS 80 -- 50 -- 50 -- ns Input data hold time tPRH 80 -- 50 -- 50 -- ns CS/HA0 setup time tHAR 10 -- 10 -- 10 -- ns CS/HA0 hold time tHRA 10 -- 10 -- 10 -- ns IOR pulse width tHRPW 220 -- 120 -- 120 -- ns HDB delay time tHRD -- 200 -- 100 -- 100 ns HDB hold time tHRF 0 40 0 25 0 25 ns HIRQ delay time tHIRQ -- 200 -- 120 -- 120 ns CS/HA0 setup time tHAW 10 -- 10 -- 10 -- ns CS/HA0 hold time tHWA 10 -- 10 -- 10 -- ns IOW pulse width tHWPW 100 -- 60 -- 60 -- ns HDB setup time tHDW 50 -- 30 -- 30 -- ns 85 -- 55 -- 45 -- Item Ports Condition C High-speed GATE A20 not used High-speed GATE A20 used HDB hold time tHWD 25 -- 15 -- 15 -- ns GA 20 delay time tHGA -- 180 -- 90 -- 90 ns Note: * In the F-ZTAT LH version, V CC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V. 572 Fig. 23.22 Fig. 23.23 Table 23.11 I2C Bus Timing Conditions: VCC = 2.7 V to 5.5 V*, VCCB = 2.7 V to 5.5 V*, VSS = 0 V, Ta = -20C to +75C, o 5 MHz Item Symbol Min Typ Max Unit SCL clock cycle time t SCL 12 tcyc -- -- ns SCL clock high pulse width t SCLH 3 tcyc -- -- ns SCL clock low pulse width t SCLL 5 tcyc -- -- ns -- -- 1000 ns 20 + 0.1Cb -- 300 -- -- 300 20 + 0.1Cb -- 300 SDA bus-free t BUF time 5 tcyc -- -- ns SCL start condition hold time t STAH 3 tcyc -- -- ns SCL resend t STAS start condition setup time 3 tcyc -- -- ns SDA stop condition setup time t STOS 3 tcyc -- -- ns SDA data setup time t SDAS 0.5 t cyc -- -- ns SDA data hold time t SDAH 0 -- -- ns SDA load capacitance Cb -- -- 400 pF SCL and SDA t Sr rise time SCL and SDA t Sf fall time Test Conditions Note Fig. 23.24 Normal mode 100 kbits/s (max) High-speed mode 400 kbits/s (max) ns Normal mode 100 kbits/s (max) High-speed mode 400 kbits/s (max) Note: * In the F-ZTAT LH version, V CC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V. 573 Table 23.12 External Clock Output Stabilization Delay Time Conditions: VCC = 2.7 V to 5.5 V*2, AVCC = 2.7 V to 5.5 V*2, VSS = AVSS = 0 V, Ta = -40C to +85C Item External clock output stabilization delay time Symbol t *1 DEXT Min Max Unit Notes 500 -- s Figure 23.26 Notes: *1 t DEXT includes a 10 tcyc RES pulse width (t RESW). *2 In the F-ZTAT LH version, V CC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V. 574 23.2.3 A/D Converter Characteristics Table 23.13 lists the characteristics of the on-chip A/D converter. Table 23.13 A/D Converter Characteristics Condition A: VCC = 5.0 V 10%, V CCB = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C: VCC = 2.7 V to 5.5 V*2, VCCB = 2.7 V to 5.5 V*2, AVCC = 2.7 V to 5.5 V*2, AVref = 2.7 V to AVCC*2, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C Item Condition C Condition B Condition A 10 MHz 12 MHz 16 MHz Min Typ Max Min Typ Max Min Typ Max Unit 10 10 10 10 10 10 10 10 10 Bits -- -- 13.4 -- -- 11.2 -- -- 8.4 s Analog input capacitance -- -- 20 -- -- 20 -- -- 20 pF Allowable signal source impedance -- -- 5 -- -- 10 -- -- 10 k Nonlinearity error -- -- 6.0 -- -- 3.0 -- -- 3.0 LSB Offset error -- -- 4.0 -- -- 3.5 -- -- 3.5 LSB Full-scale error -- -- 4.0 -- -- 3.5 -- -- 3.5 LSB Quantizing error -- -- 0.5 -- -- 0.5 -- -- 0.5 LSB Absolute accuracy -- -- 8.0 -- -- 4.0 -- -- 4.0 LSB Resolution Conversion (single mode) *1 Notes: *1 Values at maximum operating frequency *2 In the F-ZTAT LH version, VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC. 575 23.2.4 D/A Converter Characteristics Table 23.14 lists the characteristics of the on-chip D/A converter. Table 23.14 D/A Converter Characteristics Condition A: VCC = 5.0 V 10%, V CCB = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, AVref = 4.0 V to AVCC, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C: VCC = 2.7 V to 5.5 V*, VCCB = 2.7 V to 5.5 V*, AVCC = 2.7 V to 5.5 V*, AVref = 2.7 V to AVCC*, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C Condition C Condition B Condition A 10 MHz 12 MHz 16 MHz Item Min Typ Max Min Typ Max Min Test Typ Max Unit Conditions Resolution 8 8 8 8 8 8 8 8 8 Conversion time (settling time) -- -- 10.0 -- -- 10.0 -- -- 10.0 s Absolute accuracy -- 2.0 3.0 -- 1.0 1.5 -- 1.0 1.5 LSB 2 M load resistance -- -- 2.0 -- -- 1.0 -- -- Bits 30 pF load capacitance 1.0 LSB 4 M load resistance Note: * In the F-ZTAT LH version, V CC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC. 576 23.2.5 Flash Memory Characteristics (H8/3437SF Only) Table 23.15 shows the flash memory characteristics. Table 23.15 Flash Memory Characteristics Conditions: VCC = 5.0 V 10%, AV CC = 5.0 V 10%, V SS = AVSS = 0 V, Ta = 0 to +75C Item Symbol Min Typ Max Unit Programming time*1, *2, *4 tP -- 10 200 ms/ 32 bytes Erase time*1, *3, *5 tE -- 100 1200 ms/ block Reprogramming count NWEC -- -- 100 Times Programming Wait time after SWE-bit setting*1 x 10 -- -- s Wait time after PSU-bit setting*1 y 50 -- -- s Wait time after P-bit setting *1, *4 z 150 -- 500 s Wait time after P-bit clear*1 10 -- -- s Wait time after PSU-bit clear*1 10 -- -- s Wait time after PV-bit setting *1 4 -- -- s Wait time after dummy write*1 2 -- -- s Wait time after PV-bit clear *1 4 -- -- s Maximum programming count*1, *4, *5 N -- -- 403 Times Test Condition 577 Item Erase Symbol Min Typ Max Unit Wait time after SWE-bit setting*1 x 10 -- -- s Wait time after ESU-bit setting*1 y 200 -- -- s Wait time after E-bit setting *1, *6 z 5 -- 10 ms Wait time after E-bit clear*1 10 -- -- s Wait time after ESU-bit clear*1 10 -- -- s Wait time after EV-bit setting *1 20 -- -- s Wait time after dummy write*1 2 -- -- s Wait time after EV-bit clear *1 5 -- -- s Maximum erase count*1, *6, *7 N -- -- 120 Times Test Condition tE = 10 ms Notes: *1 Set the times according to the program/erase algorithms. *2 Programming time per 32 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) *3 Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) *4 Maximum programming time (tP (max) = wait time after P-bit setting (z) x maximum programming count (N)) Set the wait time after P-bit setting (z) to the minimum value of 150 s when the write counter in the 32-byte write algorithm is between 1 and 4. *5 Number of times when the wait time after P-bit setting (z) = 150 s or 500 s. The number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tP). *6 Maximum erase time (tE (max) = Wait time after E-bit setting (z) x maximum erase count (N)) *7 Number of times when the wait time after E-bit setting (z) = 10 ms. The number of erases should be set according to the actual set value of z to allow erasing within the maximum erase time (tE). 578 23.3 Absolute Maximum Ratings (H8/3437SF Low-Voltage Version) Table 23.16 lists the absolute maximum ratings. Table 23.16 Absolute Maximum Ratings Item Symbol Value Unit Supply voltage VCC - 0.3 to + 7.0 V Input output Buffer for Supply voltage VCCB - 0.3 to + 7.0 V Input voltage (except port 7, P86, P97, PA7 to PA4) Vin - 0.3 to V CC + 0.3 V Input voltage (P86, P97, PA7 to PA4) Vin - 0.3 to V CCB + 0.3 V Input voltage (Port 7) Vin - 0.3 to AV CC + 0.3 V Reference supply voltage AVref - 0.3 to AV CC + 0.3 V Analog supply voltage AVCC - 0.3 to + 7.0 V Analog input voltage VAN - 0.3 to AV CC + 0.3 V Operating temperature Topr - 20 to + 75 C Storage temperature Tstg - 55 to + 125 C Caution: Exceeding the absolute maximum ratings shown in table above can permanently destroy the chip. 579 23.4 Electrical Characteristics (H8/3437SF Low-Voltage Version) 23.4.1 DC Characteristics Table 23.17 lists the DC characteristics. Table 23.18 gives the allowable current output values. Bus drive characteristics common listed in table 23.19. Table 23.17 DC Characteristics Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V*1, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Schmitt P67 to P6 0*4, (1) *7 VT- KEYIN trigger input 15 to, voltage KEYIN8, VT+ IRQ2 to IRQ0*5, IRQ7 to IRQ3 VT+ - VT- Input high voltage Input low voltage*4 580 RES, STBY, MD1, MD0, EXTAL, NMI (2) VIH Min Typ Max Unit VCC x 0.15 -- VCCB x 0.15 -- V -- -- VCC x 0.7 VCCB x 0.7 0.2 -- -- VCC x 0.9 -- VCC + 0.3 PA7 to PA 0*7 SCL, SDA VCC x 0.7 -- VCC B x 0.7 VCC + 0.3 VCCB + 0.3 P77 to P7 0 VCC x 0.7 -- AVCC + 0.3 All input pins other than (1) and (2) above *7 VCC x 0.7 -- VCCB x 0.7 VCC + 0.3 VCCB + 0.3 -0.3 -- VCC x 0.1 PA7 to PA 0*7 SCL, SDA -0.3 -- VCC x 0.15 VCCB x 0.15 All input pins other than (1) and (3) above *7 -0.3 -- VCC x 0.15 VCCB x 0.15 RES, STBY, MD1, MD0 (3) VIL V V Test Conditions Max Unit Test Conditions VCC - 0.5 -- VCCB - 0.5 -- V I OH = -200 A VCC - 1.0 -- VCCB - 1.0 -- -- -- 0.4 P17 to P1 0, P27 to P2 0 -- -- 0.4 I OL = 1.6 mA RESO -- -- 0.4 I OL = 1.6 mA -- -- 10.0 NMI, MD1, MD0 -- -- 1.0 P77 to P7 0 -- -- 1.0 Item Symbol Min Output high All output pins voltage (except RESO)*6, *7 VOH Output low voltage All output pins (except RESO)*6 VOL Typ I OH = -1 mA V A I OL = 0.8 mA Input leakage current RES, STBY Leakage current in three-state (off state) Ports 1 to 6, 8, 9, A, B, RESO *7 | ITSI | -- -- 1.0 A Vin = 0.5 V to VCC - 0.5 V, Vin = 0.5 V to VCCB - 0.5 V Input pullup MOS current Ports 1 to 3 -I P 3 -- 120 A 30 -- 250 Vin = 0 V, VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 3.6 V -- -- 60 pF NMI, MD1 -- -- 50 Vin = 0 V, f = 1 MHz, Ta = 25C PA7 to PA 4, P97, P8 6 -- -- 20 All input pins other than (4) above -- -- 15 Ports 6, A, B Input STBY, RES capacitance | Iin | *7 (4) Cin Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V 581 Test Conditions Item Symbol Min Typ Max Unit Normal operation Current dissipation *2 I CC -- 7 -- mA -- 12 22 f = 10 MHz, VCC = 3.0 V to 3.6 V -- 25 -- f = 10 MHz, VCC = 4.5 V to 5.5 V -- 5 -- f = 6 MHz, VCC = 3.0 V to 3.6 V -- 9 16 f = 10 MHz, VCC = 3.0 V to 3.6 V -- 18 -- f = 10 MHz, VCC = 4.5 V to 5.5 V -- 0.01 5.0 -- -- 20.0 -- 1.2 2.0 During A/D and D/A conversion -- 1.2 2.0 A/D and D/A conversion idle -- 0.01 5.0 A -- 0.3 0.6 mA During A/D and D/A conversion -- 1.3 3.0 A/D and D/A conversion idle -- 0.01 5.0 Sleep mode Standby modes *3 Analog supply current Reference supply current 582 During A/D conversion During A/D conversion AI CC AI ref A f = 6 MHz, VCC = 3.0 V to 3.6 V Ta 50C 50C < Ta mA A AVCC = 2.0 V to 5.5 V AVref = 2.0 V to 5.5 V Item Symbol Min Typ Max Unit Analog supply voltage*1 AVCC 3.0 -- 5.5 V 2.0 -- 5.5 2.0 -- -- RAM standby voltage VRAM Test Conditions During operation While idle or when not in use V Notes: *1 Even when the A/D and D/A converters are not used, connect AVCC to power supply VCC and keep the applied voltage between 2.0 V and 5.5 V. At this time, make sure AVref AVCC. *2 Current dissipation values assume that V IH min = VCC - 0.5 V, VCCB - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. *3 For these values it is assumed that V RAM VCC < 3.0 V and VIH min = VCC x 0.9, VCCB x 0.9, VIL max = 0.3 V. *4 P67 to P6 0 include supporting module inputs multiplexed with them. *5 IRQ2 includes ADTRG multiplexed with it. *6 Applies when IICS = IICE = 0. The output low level is determined separately when the bus drive function is selected. *7 The characteristics of PA7 to PA 4, KEYIN15 to KEYIN12 , P97/WAIT, SDA, and P86/IRQ5/SCK1, SCL depend on VCCB; the characteristics of all other pins depend on VCC. 583 Table 23.18 Allowable Output Current Values Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Symbol Allowable output low current (per pin) Allowable output low current (total) Min Typ Max Unit SCL, SDA, PA4 to PA 7 I OL (bus drive selection) -- -- 10 mA Ports 1 and 2 -- -- 2 RESO -- -- 1 Other output pins -- -- 1 -- -- 40 -- -- 60 Ports 1 and 2, total IOL Total of all output mA Allowable output high current (per pin) All output pins -I OH -- -- 2 mA Allowable output high current (total) Total of all output -IOH -- -- 30 mA Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current values in table 23.19. In particular, when driving a darlington transistor pair or LED directly, be sure to insert a current-limiting resistor in the output path. See figures 23.4 and 23.5. H8/3437 2 k Port Darlington transistor Figure 23.4 Example of Circuit for Driving a Darlington Transistor (5-V Version) 584 H8/3437 VCC 600 Ports 1 or 2 LED Figure 23.5 Example of Circuit for Driving an LED (5-V Version) Table 23.19 Bus Drive Characteristics Conditions: VCC = 3.0 V to 5.5 V, VSS = 0 V, Ta = -20C to +75C Item Output low level voltage 23.4.2 SCL, SDA PA4 to PA 7 (bus drive selection) Symbol Min Typ Max Unit Test Condition VOL -- -- 0.5 V VCCB = 5 V 10% I OL = 16 mA -- -- 0.5 VCCB = 3.0 V to 5.5 V I OL = 8 mA -- -- 0.4 VCCB = 3.0 V to 5.5 V I OL = 3 mA AC Characteristics The AC characteristics are listed in four tables. Bus timing parameters are given in table 23.20, control signal timing parameters in table 23.21, timing parameters of the on-chip supporting modules in table 23.22, I2C bus timing parameters in table 23.23, and external clock output stabilization delay time in table 23.24. 585 Table 23.20 Bus Timing Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition 10MHz Item Symbol Min Max Unit Test Conditions Clock cycle time t cyc 100 500 ns Fig. 23.7 Clock pulse width low t CL 30 -- ns Clock pulse width high t CH 30 -- ns Clock rise time t Cr -- 20 ns Clock fall time t Cf -- 20 ns Address delay time t AD -- 50 ns Address hold time t AH 20 -- ns Address strobe delay time t ASD -- 50 ns Write strobe delay time t WSD -- 50 ns Strobe delay time t SD -- 50 ns Write strobe pulse width* t WSW 110 -- ns Address setup time 1* t AS1 15 -- ns Address setup time 2* t AS2 65 -- ns Read data setup time t RDS 35 -- ns Read data hold time* t RDH 0 -- ns Read data access time* t ACC -- 170 ns Write data delay time t WDD -- 75 ns Write data setup time t WDS 5 -- ns Write data hold time t WDH 20 -- ns Wait setup time t WTS 40 -- ns Wait hold time t WTH 10 -- ns Note: * Values at maximum operating frequency 586 Fig. 23.8 Table 23.21 Control Signal Timing Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition 10MHz Item Symbol Min Max Unit Test Conditions RES setup time t RESS 300 -- ns Fig. 23.9 RES pulse width t RESW 10 -- t cyc RESO output delay time t RESD -- 200 ns RESO output pulse width t RESOW 132 -- t cyc NMI setup time (NMI, IRQ0 to IRQ7) t NMIS 300 -- ns NMI hold time (NMI, IRQ0 to IRQ7) t NMIH 10 -- ns Interrupt pulse width for recovery from software standby mode (NMI, IRQ0 to IRQ2, IRQ6) t NMIW 300 -- ns Crystal oscillator settling time (reset) t OSC1 20 -- ms Fig. 23.11 Crystal oscillator settling time (software standby) t OSC2 8 -- ms Fig. 23.12 Fig. 23.25 Fig. 23.10 Measurement Conditions for AC Characteristics 5V RL LSI output pin RH C = 90 pF: Ports 1-4, 6, 9, A, B 30 pF: Ports 5, 8 RL = 2.4 k RH = 12 k C Input/output timing measurement levels Low: 0.8 V High: 2.0 V Figure 23.6 Measurement Conditions for A/C Characteristics 587 Table 23.22 Timing Conditions of On-Chip Supporting Modules Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20C to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition 10MHz Item FRT Symbol Min Max Unit Test Conditions Timer output delay time tFTOD -- 150 ns Fig. 23.13 Timer input setup time tFTIS 80 -- ns Timer clock input setup time tFTCS 80 -- ns Timer clock pulse width tFTCWH 1.5 -- tcyc Fig. 23.14 tFTCWL TMR Timer output delay time tTMOD -- 150 ns Fig. 23.15 Timer reset input setup time tTMRS 80 -- ns Fig. 23.17 Timer clock input setup time tTMCS 80 -- ns Fig. 23.16 Timer clock pulse width (single edge) tTMCWH 1.5 -- tcyc Timer clock pulse width (both edges) tTMCWL 2.5 -- tcyc PWM Timer output delay time tPWOD -- 150 ns Fig. 23.18 SCI Input clock cycle tScyc 4 -- tcyc Fig. 23.19 6 -- tcyc (Async) (Sync) Ports HIF read cycle 588 Transmit data delay time (Sync) tTXD -- 200 ns Receive data setup time (Sync) tRXS 150 -- ns Receive data hold time (Sync) tRXH 150 -- ns Input clock pulse width tSCKW 0.4 0.6 tScyc Fig. 23.20 Output data delay time tPWD -- 150 ns Fig. 23.21 Input data setup time tPRS 80 -- ns Input data hold time tPRH 80 -- ns CS/HA0 setup time tHAR 10 -- ns CS/HA0 hold time tHRA 10 -- ns IOR pulse width tHRPW 220 -- ns HDB delay time tHRD -- 200 ns HDB hold time tHRF 0 40 ns HIRQ delay time tHIRQ -- 200 ns Fig. 23.22 Item HIF write cycle Symbol Min Max Unit Test Conditions CS/HA0 setup time tHAW 10 -- ns Fig. 23.23 CS/HA0 hold time tHWA 10 -- ns IOW pulse width tHWPW 100 -- ns HDB setup time tHDW 50 -- ns 85 -- High-speed GATE A20 not used High-speed GATE A20 used HDB hold time tHWD 25 -- ns GA 20 delay time tHGA -- 180 ns 589 Table 23.23 I2C Bus Timing Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications), o = 5 MHz to maximum operating frequency Item Symbol Min Typ Max Unit SCL clock cycle time t SCL 12 tcyc -- -- ns SCL clock high pulse width t SCLH 3 tcyc -- -- ns SCL clock low pulse width t SCLL 5 tcyc -- -- ns -- -- 1000 ns 20 + 0.1Cb -- 300 -- -- 300 20 + 0.1Cb -- 300 SDA bus-free t BUF time 5 tcyc -- -- ns SCL start condition hold time t STAH 3 tcyc -- -- ns SCL resend t STAS start condition setup time 3 tcyc -- -- ns SDA stop condition setup time t STOS 3 tcyc -- -- ns SDA data setup time t SDAS 0.5 t cyc -- -- ns SDA data hold time t SDAH 0 -- -- ns SDA load capacitance Cb -- -- 400 pF SCL and SDA t Sr rise time SCL and SDA t Sf fall time 590 Test Conditions Fig. 23.24 Normal mode 100 kbits/s (max) High-speed mode 400 kbits/s (max) ns Note Normal mode 100 kbits/s (max) High-speed mode 400 kbits/s (max) Table 23.24 External Clock Output Stabilization Delay Time Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, Ta = -40C to +85C Item Symbol Min Max Unit Notes External clock output stabilization delay time t DEXT* 500 -- s Figure 23.26 Note: * tDEXT includes a 10 tcyc RES pulse width (t RESW). 23.4.3 A/D Converter Characteristics Table 23.25 lists the characteristics of the on-chip A/D converter. Table 23.25 A/D Converter Characteristics Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (widerange specifications) Condition 10 MHz Item Min Typ Max Unit Resolution 10 10 10 Bits Conversion (single mode)* -- -- 13.4 s Analog input capacitance -- -- 20 pF Allowable signal source impedance -- -- 5 k Nonlinearity error -- -- 6.0 LSB Offset error -- -- 4.0 LSB Full-scale error -- -- 4.0 LSB Quantizing error -- -- 0.5 LSB Absolute accuracy -- -- 8.0 LSB Note: * Values at maximum operating frequency 591 23.4.4 D/A Converter Characteristics Table 23.26 lists the characteristics of the on-chip D/A converter. Table 23.26 D/A Converter Characteristics Conditions: VCC = 3.0 V to 5.5 V, VCCB = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (widerange specifications) Condition 10 MHz Item Min Typ Max Unit Resolution 8 8 8 Bits Conversion time (settling time) -- -- 10.0 s 30 pF load capacitance Absolute accuracy -- 2.0 3.0 LSB 2 M load resistance -- -- 2.0 LSB 4 M load resistance 592 Test Conditions 23.4.5 Flash Memory Characteristics Table 23.27 shows the flash memory characteristics. Table 23.27 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, V CCB = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, AVref = 3.0 to AVCC, Ta = 0 to +75C (programming/erasing operation temperature), Ta = 0 to +85C Item Symbol Min Typ Max Unit Programming time*1, *2, *4 tP -- 10 200 ms/ 32 bytes Erase time*1, *3, *5 tE -- 100 1200 ms/ block Reprogramming count NWEC -- -- 100 Times Programming Wait time after SWE-bit setting*1 x 10 -- -- s Wait time after PSU-bit setting*1 y 50 -- -- s Wait time after P-bit setting *1, *4 z 150 -- 500 s Wait time after P-bit clear*1 10 -- -- s Wait time after PSU-bit clear*1 10 -- -- s Wait time after PV-bit setting *1 4 -- -- s Wait time after dummy write*1 2 -- -- s Wait time after PV-bit clear *1 4 -- -- s Maximum programming count*1, *4, *5 N -- -- 403 Times Test Condition 593 Item Erase Symbol Min Typ Max Unit Wait time after SWE-bit setting*1 x 10 -- -- s Wait time after ESU-bit setting*1 y 200 -- -- s Wait time after E-bit setting *1, *6 z 5 -- 10 ms Wait time after E-bit clear*1 10 -- -- s Wait time after ESU-bit clear*1 10 -- -- s Wait time after EV-bit setting *1 20 -- -- s Wait time after dummy write*1 2 -- -- s Wait time after EV-bit clear *1 5 -- -- s Maximum erase count*1, *6, *7 N -- -- 120 Times Test Condition tE = 10 ms Notes: *1 Set the times according to the program/erase algorithms. *2 Programming time per 32 bytes (Shows the total period for which the P-bit in FLMCR1 is set. It does not include the programming verification time.) *3 Block erase time (Shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) *4 Maximum programming time (tP (max) = wait time after P-bit setting (z) x maximum programming count (N)) Set the wait time after P-bit setting (z) to the minimum value of 150 s when the write counter in the 32-byte write algorithm is between 1 and 4. *5 Number of times when the wait time after P-bit setting (z) = 150 s or 500 s. The number of writes should be set according to the actual set value of (z) to allow programming within the maximum programming time (tP). *6 Maximum erase time (tE (max) = Wait time after E-bit setting (z) x maximum erase count (N)) *7 Number of times when the wait time after E-bit setting (z) = 10 ms. The number of erases should be set according to the actual set value of z to allow erasing within the maximum erase time (tE). 594 23.5 MCU Operational Timing This section provides the following timing charts: 23.5.1 Bus Timing 23.5.2 Control Signal Timing 23.5.3 16-Bit Free-Running Timer Timing 23.5.4 8-Bit Timer Timing 23.5.5 PWM Timer Timing 23.5.6 SCI Timing 23.5.7 I/O Port Timing 23.5.8 Host Interface Timing 23.5.9 I2C Bus Timing 23.5.10 Reset Output Timing 23.5.11 External Clock Output Timing 23.5.1 Figures 23.7 and 23.8 Figures 23.9 to 23.12 Figures 23.13 and 23.14 Figures 23.15 to 23.17 Figure 23.18 Figures 23.19 and 23.20 Figure 23.21 Figures 23.22 and 23.23 Figure 23.24 Figure 23.25 Figure 23.26 Bus Timing (1) Basic Bus Cycle (without Wait States) in Expanded Modes T1 T2 T3 t cyc t CH tCL o t Cf t AD t Cr A15 to A0 t ASD t SD t AH t ASI AS, RD D7 to D0 (read) t WSD t AS2 tRDH tRDS t ACC t SD tWSW t AH WR tWDD t WDS t WDH D7 to D0 (write) Figure 23.7 Basic Bus Cycle (without Wait States) in Expanded Modes 595 (2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes T2 T1 TW T3 o A15 to A0 AS, RD D7 to D0 (read) WR D7 to D0 (write) t WTS t WTH t WTS t WTH WAIT Figure 23.8 Basic Bus Cycle (with 1 Wait State) in Expanded Modes 23.5.2 Control Signal Timing (1) Reset Input Timing o tRESS tRESS RES tRESW Figure 23.9 Reset Input Timing 596 (2) Interrupt Input Timing o tNMIS NMI IRQE (edge) tNMIH tNMIS IRQL (level) tNMIW NMI IRQi Note: i = 0 to 7; IRQE: IRQi when edge-sensed; IRQL: IRQi when level-sensed Figure 23.10 Interrupt Input Timing (3) Clock Settling Timing o VCC STBY tOSC1 tOSC1 RES Figure 23.11 Clock Settling Timing 597 (4) Clock Settling Timing for Recovery from Software Standby Mode o NMI IRQi tOSC2 (i = 0, 1, 2, 6) Figure 23.12 Clock Settling Timing for Recovery from Software Standby Mode 23.5.3 16-Bit Free-Running Timer Timing (1) Free-Running Timer Input/Output Timing o Free-running Compare-match timer counter tFTOD FTOA , FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 23.13 Free-Running Timer Input/Output Timing 598 (2) External Clock Input Timing for Free-Running Timer o tFTCS FTCI tFTCWL tFTCWH Figure 23.14 External Clock Input Timing for Free-Running Timer 23.5.4 8-Bit Timer Timing (1) 8-Bit Timer Output Timing o Timer counter Compare-match tTMOD TMO0, TMO1 Figure 23.15 8-Bit Timer Output Timing (2) 8-Bit Timer Clock Input Timing o tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 23.16 8-Bit Timer Clock Input Timing 599 (3) 8-Bit Timer Reset Input Timing o tTMRS TMRI0, TMRI1 Timer counter H'00 N Figure 23.17 8-Bit Timer Reset Input Timing 23.5.5 Pulse Width Modulation Timer Timing o Timer counter Compare-match tPWOD PW0, PW1 Figure 23.18 PWM Timer Output Timing 600 23.5.6 Serial Communication Interface Timing (1) SCI Input/Output Timing tScyc Serial clock (SCK0, SCK1) tTXD Transmit data (TxD0, TxD1) tRXS tRXH Receive data (RxD0, RxD1) Figure 23.19 SCI Input/Output Timing (Synchronous Mode) (2) SCI Input Clock Timing tSCKW SCK0, SCK1 tScyc Figure 23.20 SCI Input Clock Timing 601 23.5.7 I/O Port Timing Port read/write cycle T1 T2 T3 o tPRS tPRH Port 1 to port 9 (input) Port A, B tPWD Port 1* to port 9 (output) Port A, B Note: * Except P96 and P77 to P70 Figure 23.21 I/O Port Input/Output Timing 23.5.8 Host Interface Timing (1) Host Interface Read Timing CS/HA0 HA0 tHAR tHRPW tHRA IOR tHRF tHRD HDB7 to HDB0 Valid data tHIRQ HIRQi* (i = 1, 11, 12) Note: * Rising edge timing is the same as in port 4 output timing. Refer to figure 23.21. Figure 23.22 Host Interface Read Timing 602 (2) Host Interface Write Timing CS/HA0 HA0 tHAW tHWPW tHWA IOW tHWD tHDW HDB7 to HDB0 tHGA GA20 Figure 23.23 Host Interface Write Timing 23.5.9 I2C Bus Timing (Option) VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL tSDAS tSr tSCL P* tSDAH Note: * Conditions S, P, and Sr are defined as follows: S: Start condition P: Stop condition Sr: Resend "start" condition Figure 23.24 I2C Bus Interface I/O Timing 603 23.5.10 Reset Output Timing o tRESD tRESD RESO tRESOW Figure 23.25 Reset Output Timing 23.5.11 External Clock Output Timing VCC STBY VIH EXTAL o (internal or external) RES tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW). Figure 23.26 External Clock Output Stabilization Delay Time 604 Appendix A CPU Instruction Set A.1 Instruction Set List Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) CCR Condition code register N N (negative) flag in CCR Z Z (zero) flag in CCR V V (overflow) flag in CCR C C (carry) flag in CCR PC Program counter SP Stack pointer #xx:3/8/16 Immediate data (3, 8, or 16 bits) d:8/16 Displacement (8 or 16 bits) @aa:8/16 Absolute address (8 or 16 bits) + Addition - Subtraction x Multiplication / Division Logical AND Logical OR Exclusive logical OR -- Move NOT (logical complement) Condition Code Notation Modified according to the instruction result * Undetermined (unpredictable) 0 Always cleared to 0 -- Not affected by the instruction result 605 Instruction Set Condition Code Implied @aa: 8/16 @(d:8, PC) @@aa @Rn @(d:16, Rn) @-Rn/@Rn+ Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length I H N Z V C MOV.B @Rs+, Rd B @Rs16 Rd8 Rs16+1 Rs16 MOV.B @aa:8, Rd B @aa:8 Rd8 2 -- -- MOV.B @aa:16, Rd B @aa:16 Rd8 4 -- -- MOV.B Rs, @Rd B Rs8 @Rd16 MOV.B Rs, @(d:16, Rd) B Rs8 @(d:16, Rd16) MOV.B Rs, @-Rd B Rd16-1 Rd16 Rs8 @Rd16 MOV.B Rs, @aa:8 B Rs8 @aa:8 2 -- -- MOV.B Rs, @aa:16 B Rs8 @aa:16 4 -- -- MOV.W #xx:16, Rd W #xx:16 Rd MOV.W Rs, Rd W Rs16 Rd16 MOV.W @Rs, Rd W @Rs16 Rd16 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 MOV.B @(d:16, Rs), Rd 0 -- 4 MOV.B @Rs, Rd 0 -- 2 0 -- 4 0 -- 6 MOV.W Rs, @-Rd W Rd16-2 Rd16 Rs16 @Rd16 B Rs8 Rd8 MOV.W Rs, @aa:16 W Rs16 @aa:16 0 -- 6 POP Rd W @SP Rd16 SP+2 SP 2 -- -- B #xx:8 Rd8 MOV.B Rs, Rd PUSH Rs W SP-2 SP Rs16 @SP 2 -- -- MOV.B #xx:8, Rd No. of States Table A.1 0 -- 6 2 -- -- 2 -- -- 2 W @Rs16 Rd16 Rs16+2 Rs16 MOV.W @aa:16, Rd W @aa:16 Rd16 MOV.W Rs, @Rd W Rs16 @Rd16 MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) 606 -- -- 2 -- -- 2 -- -- 4 -- -- 2 -- -- 4 -- -- 2 -- -- 2 MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd -- -- 4 -- -- 4 -- -- 2 -- -- 4 2 -- -- -- -- 4 -- -- 2 -- -- 4 -- -- 0 -- 2 0 -- 4 0 -- 6 0 -- 6 0 -- 6 0 -- 4 0 -- 6 0 -- 6 0 -- 6 0 -- 4 0 -- 2 0 -- 4 0 -- 6 0 -- 6 0 -- 4 0 -- 6 0 -- 6 0 -- 6 I No. of States Implied @aa: 8/16 @(d:8, PC) @@aa @Rn @(d:16, Rn) @-Rn/@Rn+ Condition Code H N Z V C B Not supported B Not supported EEPMOV -- if R4L0 then Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next ADD.B #xx:8, Rd B Rd8+#xx:8 Rd8 4 -- -- -- -- -- -- (4) 2 -- MOVTPE Rs, @aa:16 MOVFPE @aa:16, Rd Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length 2 B Rd8+Rs8 Rd8 2 -- ADD.W Rs, Rd W Rd16+Rs16 Rd16 2 -- (1) ADDX.B #xx:8, Rd B Rd8+#xx:8 +C Rd8 ADDX.B Rs, Rd B Rd8+Rs8 +C Rd8 2 -- ADDS.W #1, Rd W Rd16+1 Rd16 2 -- -- -- -- -- -- 2 ADDS.W #2, Rd W Rd16+2 Rd16 2 -- -- -- -- -- -- 2 INC.B Rd B Rd8+1 Rd8 2 -- -- DAA.B Rd B Rd8 decimal adjust Rd8 2 -- * SUB.B Rs, Rd B Rd8-Rs8 Rd8 2 -- SUB.W Rs, Rd W Rd16-Rs16 Rd16 2 -- (1) SUBX.B #xx:8, Rd B Rd8-#xx:8 -C Rd8 SUBX.B Rs, Rd B Rd8-Rs8 -C Rd8 2 -- SUBS.W #1, Rd W Rd16-1 Rd16 2 -- -- -- -- -- -- 2 SUBS.W #2, Rd W Rd16-2 Rd16 2 -- -- -- -- -- -- 2 DEC.B Rd B Rd8-1 Rd8 2 -- -- DAS.B Rd B Rd8 decimal adjust Rd8 2 -- * NEG.B Rd B 0-Rd8 Rd8 2 -- CMP.B #xx:8, Rd B Rd8-#xx:8 CMP.B Rs, Rd B Rd8-Rs8 2 -- CMP.W Rs, Rd W Rd16-Rs16 2 -- (1) MULXU.B Rs, Rd B Rd8 x Rs8 Rd16 2 -- -- -- -- -- -- 14 2 -- (2) 2 2 2 -- 2 (2) 2 * (3) 2 -- (2) 2 2 2 2 -- 2 * -- 2 2 (2) -- 2 ADD.B Rs, Rd 2 2 2 2 607 H N Z V C B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) AND.B #xx:8, Rd B Rd8#xx:8 Rd8 AND.B Rs, Rd B Rd8Rs8 Rd8 OR.B #xx:8, Rd B Rd8#xx:8 Rd8 OR.B Rs, Rd B Rd8Rs8 Rd8 XOR.B #xx:8, Rd B Rd8#xx:8 Rd8 XOR.B Rs, Rd B Rd8Rs8 Rd8 2 -- -- NOT.B Rd B Rd8 Rd8 2 -- -- SHAL.B Rd B 2 -- -- I DIVXU.B Rs, Rd SHAR.B Rd B 2 -- -- 2 -- -- 2 -- -- 0 2 -- -- 2 -- -- 2 -- -- 2 -- -- 2 0 2 0 2 0 2 0 2 0 2 0 2 b0 0 C b0 C b0 C b0 C b7 608 0 0 b0 B C b7 2 C b7 ROTR.B Rd 0 -- 2 B 0 -- 2 ROTL.B Rd 0 -- 2 B 0 -- 2 b0 b7 ROTXR.B Rd -- -- 0 -- 2 2 -- -- 0 -- 2 B -- -- 2 0 -- 2 b0 b7 ROTXL.B Rd -- -- B 2 C b7 SHLR.B Rd -- -- (6) (7) -- -- 14 -- -- 2 0 b7 B 2 C b7 SHLL.B Rd 2 No. of States Condition Code Implied @aa: 8/16 @(d:8, PC) @@aa @Rn @(d:16, Rn) @-Rn/@Rn+ Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length b0 B (#xx:3 of Rd8) 1 BSET #xx:3, @Rd B (#xx:3 of @Rd16) 1 BSET #xx:3, @aa:8 B (#xx:3 of @aa:8) 1 BSET Rn, Rd B (Rn8 of Rd8) 1 BSET Rn, @Rd B (Rn8 of @Rd16) 1 BSET Rn, @aa:8 B (Rn8 of @aa:8) 1 BCLR #xx:3, Rd B (#xx:3 of Rd8) 0 BCLR #xx:3, @Rd B (#xx:3 of @Rd16) 0 BCLR #xx:3, @aa:8 B (#xx:3 of @aa:8) 0 BCLR Rn, Rd B (Rn8 of Rd8) 0 BCLR Rn, @Rd B (Rn8 of @Rd16) 0 BCLR Rn, @aa:8 B (Rn8 of @aa:8) 0 BNOT #xx:3, Rd B (#xx:3 of Rd8) (#xx:3 of Rd8) BNOT #xx:3, @Rd B (#xx:3 of @Rd16) (#xx:3 of @Rd16) BNOT #xx:3, @aa:8 B (#xx:3 of @aa:8) (#xx:3 of @aa:8) BNOT Rn, Rd B (Rn8 of Rd8) (Rn8 of Rd8) BNOT Rn, @Rd B (Rn8 of @Rd16) (Rn8 of @Rd16) BNOT Rn, @aa:8 B (Rn8 of @aa:8) (Rn8 of @aa:8) BTST #xx:3, Rd B (#xx:3 of Rd8) Z BTST #xx:3, @Rd B (#xx:3 of @Rd16) Z BTST #xx:3, @aa:8 B (#xx:3 of @aa:8) Z BTST Rn, Rd B (Rn8 of Rd8) Z BTST Rn, @Rd B (Rn8 of @Rd16) Z BTST Rn, @aa:8 B (Rn8 of @aa:8) Z I H N Z V C No. of States Implied @aa: 8/16 @(d:8, PC) @@aa 2 Condition Code -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- 4 -- -- -- 4 2 -- -- -- -- -- -- 4 -- -- -- 4 -- -- -- BSET #xx:3, Rd @Rn @(d:16, Rn) @-Rn/@Rn+ Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length -- -- 2 -- -- 6 -- -- 6 -- -- 2 -- -- 6 -- -- 6 609 BLD #xx:3, @Rd B (#xx:3 of @Rd16) C BLD #xx:3, @aa:8 B (#xx:3 of @aa:8) C BILD #xx:3, Rd B (#xx:3 of Rd8) C BILD #xx:3, @Rd B (#xx:3 of @Rd16) C BILD #xx:3, @aa:8 B (#xx:3 of @aa:8) C BST #xx:3, Rd B C (#xx:3 of Rd8) BST #xx:3, @Rd B C (#xx:3 of @Rd16) BST #xx:3, @aa:8 B C (#xx:3 of @aa:8) BIST #xx:3, Rd B C (#xx:3 of Rd8) BIST #xx:3, @Rd B C (#xx:3 of @Rd16) BIST #xx:3, @aa:8 B C (#xx:3 of @aa:8) BAND #xx:3, Rd B C(#xx:3 of Rd8) C BAND #xx:3, @Rd B C(#xx:3 of @Rd16) C BAND #xx:3, @aa:8 B C(#xx:3 of @aa:8) C BIAND #xx:3, Rd B C(#xx:3 of Rd8) C BIAND #xx:3, @Rd B C(#xx:3 of @Rd16) C BIAND #xx:3, @aa:8 B C(#xx:3 of @aa:8) C BOR #xx:3, Rd B C(#xx:3 of Rd8) C BOR #xx:3, @Rd B C(#xx:3 of @Rd16) C BOR #xx:3, @aa:8 B C(#xx:3 of @aa:8) C BIOR #xx:3, Rd B C(#xx:3 of Rd8) C BIOR #xx:3, @Rd B C(#xx:3 of @Rd16) C BIOR #xx:3, @aa:8 B C(#xx:3 of @aa:8) C BXOR #xx:3, Rd B C(#xx:3 of Rd8) C BXOR #xx:3, @Rd B C(#xx:3 of @Rd16) C BXOR #xx:3, @aa:8 B C(#xx:3 of @aa:8) C BIXOR #xx:3, Rd B C(#xx:3 of Rd8) C 610 H N Z V C -- -- -- -- -- 4 2 -- -- -- -- -- -- -- -- -- -- 4 -- -- -- -- -- 4 2 -- -- -- -- -- No. of States I -- -- -- -- -- 4 2 6 6 2 6 6 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 2 4 -- -- -- -- -- -- 8 4 2 -- -- -- -- -- -- 8 -- -- -- -- -- 4 -- -- -- -- -- 4 2 -- -- -- -- -- -- -- -- -- -- 4 -- -- -- -- -- 4 2 -- -- -- -- -- -- -- -- -- -- 4 -- -- -- -- -- 4 2 -- -- -- -- -- -- -- -- -- -- 4 -- -- -- -- -- 4 2 -- -- -- -- -- -- -- -- -- -- 4 -- -- -- -- -- 4 2 Implied @aa: 8/16 @(d:8, PC) @@aa 2 B (#xx:3 of Rd8) C Condition Code -- -- -- -- -- -- -- -- -- -- BLD #xx:3, Rd @Rn @(d:16, Rn) @-Rn/@Rn+ Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 B C(#xx:3 of @Rd16) C 4 I No. of States Implied @aa: 8/16 @(d:8, PC) @@aa @Rn @(d:16, Rn) @-Rn/@Rn+ Branching Condition Condition Code H N Z V C -- -- -- -- -- BIXOR #xx:3, @Rd Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length 6 BIXOR #xx:3, @aa:8 B C(#xx:3 of @aa:8) C BRA d:8 (BT d:8) -- PC PC+d:8 2 -- -- -- -- -- -- 4 BRN d:8 (BF d:8) -- PC PC+2 2 -- -- -- -- -- -- 4 BHI d:8 CZ=0 2 -- -- -- -- -- -- 4 CZ=1 2 -- -- -- -- -- -- 4 C=0 2 -- -- -- -- -- -- 4 C=1 2 -- -- -- -- -- -- 4 Z=0 2 -- -- -- -- -- -- 4 BEQ d:8 -- If -- condition is true -- then -- PC PC+d:8 -- else next; -- Z=1 2 -- -- -- -- -- -- 4 BVC d:8 -- V=0 2 -- -- -- -- -- -- 4 BVS d:8 -- V=1 2 -- -- -- -- -- -- 4 BPL d:8 -- N=0 2 -- -- -- -- -- -- 4 BMI d:8 -- N=1 2 -- -- -- -- -- -- 4 BGE d:8 -- NV = 0 2 -- -- -- -- -- -- 4 BLT d:8 -- NV = 1 2 -- -- -- -- -- -- 4 BGT d:8 -- Z (NV) = 0 2 -- -- -- -- -- -- 4 BLE d:8 -- Z (NV) = 1 2 -- -- -- -- -- -- 4 JMP @Rn -- PC Rn16 JMP @aa:16 -- PC aa:16 JMP @@aa:8 -- PC @aa:8 BSR d:8 -- SP-2 SP PC @SP PC PC+d:8 JSR @Rn -- SP-2 SP PC @SP PC Rn16 JSR @aa:16 -- SP-2 SP PC @SP PC aa:16 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 4 -- -- -- -- -- 2 6 -- -- -- -- -- -- 4 4 -- -- -- -- -- -- 6 2 2 2 -- -- -- -- -- -- 8 -- -- -- -- -- -- 6 -- -- -- -- -- -- 6 4 -- -- -- -- -- -- 8 611 I H N Z V C No. of States Implied Condition Code JSR @@aa:8 -- SP-2 SP PC @SP PC @aa:8 RTS -- PC @SP SP+2 SP 2 -- -- -- -- -- -- 8 RTE -- CCR @SP SP+2 SP PC @SP SP+2 SP 2 SLEEP -- Transit to sleep mode. 2 -- -- -- -- -- -- 2 LDC #xx:8, CCR B #xx:8 CCR LDC Rs, CCR B Rs8 CCR 2 @aa: 8/16 @(d:8, PC) @@aa @Rn @(d:16, Rn) @-Rn/@Rn+ Operation #xx: 8/16 Rn Mnemonic Operand Size Addressing Mode/ Instruction Length STC CCR, Rd B CCR Rd8 2 -- -- -- -- -- -- 2 ANDC #xx:8, CCR B CCR#xx:8 CCR 2 ORC #xx:8, CCR B CCR#xx:8 CCR 2 XORC #xx:8, CCR B CCR#xx:8 CCR 2 NOP -- PC PC+2 2 -- -- -- -- -- -- 8 2 2 2 2 2 2 2 -- -- -- -- -- -- 2 Notes: The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. (4) The number of states required for execution is 4n+8 (n = value of R4L). (5) These instructions are not supported by the H8/3437 Series. (6) Set to 1 if the divisor is negative; otherwise cleared to 0. (7) Set to 1 if the divisor is 0; otherwise cleared to 0. 612 10 A.2 Operation Code Map Table A.2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 613 614 8 BVC SUB ADD BVS 9 DEC INC A SUBS ADDS B OR XOR AND MOV C D E F MOV JMP BPL EEPMOV CMP MOV BLT D JSR BGT SUBX ADDX E Bit manipulation instructions BGE MOV*1 BMI C Notes: *1 The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word). The PUSH and POP instructions are identical in machine language to MOV instructions. *2 The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively. SUBX BILD BIST BLD BST BEQ B BIAND BAND RTE BNE MOV NEG CMP BIXOR BXOR NOT LDC 7 A BIOR BOR BSR BCS*2 AND ANDC XORC XOR 6 5 ADDX BTS RTS BCC*2 OR ORC 4 9 BCLR BLS ROTR ROTXR LDC 3 ADD BNOT BHI ROTL ROTXL STC 2 8 7 BSET DIVXU MULXU 5 6 BRN*2 SHAR SHLR SLEEP 1 BRA*2 SHAL SHLL NOP 0 4 3 2 1 0 Low ; High BLE DAS DAA F Table A.2 Operation Code Map A.3 Number of States Required for Execution The tables below can be used to calculate the number of states required for instruction execution. Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL+ M x SM + N x SN Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state inserted in external memory access. 1. BSET #0, @FFC7 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: SI = 8, SL = 3 Number of states required for execution: 2 x 8 + 2 x 3 =22 2. JSR @@30 From table A.4: I = 2, J = K = 1, L = M = N = 0 From table A.3: SI = SJ = SK = 8 Number of states required for execution: 2 x 8 + 1 x 8 + 1 x 8 = 32 Table A.3 Number of States Taken by Each Cycle in Instruction Execution Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Reg. Field External Memory 2 6 6 + 2m Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 3 3+m Word data access SM 6 6 + 2m Internal operation SN 1 1 1 Notes: m: Number of wait states inserted in access to external device. 615 Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W Rs, Rd 1 ADDS ADDS.W #1/2, Rd 1 ADDX ADDX.B #xx:8, Rd 1 AND ADDX.B Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 ANDC ANDC #xx:8, CCR 1 BAND BAND #xx:3, Rd 1 BAND #xx:3, @Rd 2 1 BAND #xx:3, @aa:8 2 1 BRA d:8 (BT d:8) 2 Bcc BCLR 616 BRN d:8 (BF d:8) 2 BHI d:8 2 BLS d:8 2 BCC d:8 (BHS d:8) 2 BCS d:8 (BLO d:8) 2 BNE d:8 2 BEQ d:8 2 BVC d:8 2 BVS d:8 2 BPL d:8 2 BMI d:8 2 BGE d:8 2 BLT d:8 2 BGT d:8 2 BLE d:8 2 BCLR #xx:3, Rd 1 BCLR #xx:3, @Rd 2 2 BCLR #xx:3, @aa:8 2 2 BCLR Rn, Rd 1 BCLR Rn, @Rd 2 2 BCLR Rn, @aa:8 2 2 Word Data Internal Access Operation M N Instruction Mnemonic Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L BIAND BIAND #xx:3, Rd 1 BIAND #xx:3, @Rd 2 1 BIAND #xx:3, @aa:8 2 1 BILD BIOR BIST BIXOR BLD BNOT BOR BSET BILD #xx:3, Rd 1 BILD #xx:3, @Rd 2 1 BILD #xx:3, @aa:8 2 1 BIOR #xx:3, Rd 1 BIOR #xx:3, @Rd 2 1 BIOR #xx:3, @aa:8 2 1 BIST #xx:3, Rd 1 BIST #xx:3, @Rd 2 2 BIST #xx:3, @aa:8 2 2 BIXOR #xx:3, Rd 1 BIXOR #xx:3, @Rd 2 1 BIXOR #xx:3, @aa:8 2 1 BLD #xx:3, Rd 1 BLD #xx:3, @Rd 2 1 BLD #xx:3, @aa:8 2 1 BNOT #xx:3, Rd 1 BNOT #xx:3, @Rd 2 2 BNOT #xx:3, @aa:8 2 2 BNOT Rn, Rd 1 BNOT Rn, @Rd 2 2 BNOT Rn, @aa:8 2 2 BOR #xx:3, Rd 1 BOR #xx:3, @Rd 2 1 BOR #xx:3, @aa:8 2 1 BSET #xx:3, Rd 1 BSET #xx:3, @Rd 2 2 BSET #xx:3, @aa:8 2 2 BSET Rn, Rd 1 BSET Rn, @Rd 2 2 BSET Rn, @aa:8 2 2 Word Data Internal Access Operation M N 617 Instruction Mnemonic Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L BSR BSR d:8 2 BST BST #xx:3, Rd 1 BST #xx:3, @Rd 2 2 BST #xx:3, @aa:8 2 2 BTST #xx:3, Rd 1 BTST #xx:3, @Rd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @Rd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @Rd 2 1 BXOR #xx:3, @aa:8 2 1 BTST BXOR CMP CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W Rs, Rd 1 DAA DAA.B Rd 1 DAS DAS.B Rd 1 DEC DEC.B Rd 1 DIVXU DIVXU.B Rs, Rd 1 EEPMOV EEPMOV 2 INC INC.B Rd 1 JMP JMP @Rn 2 JMP @aa:16 2 JMP @@aa:8 2 JSR @Rn 2 JSR @aa:16 2 JSR @@aa:8 2 LDC #xx:8, CCR 1 LDC Rs, CCR 1 JSR LDC 618 Word Data Internal Access Operation M N 1 12 2n+2* 1 2 1 2 1 1 1 1 2 Instruction Mnemonic Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L MOV MOV.B #xx:8, Rd 1 MOV.B Rs, Rd 1 MOV.B @Rs, Rd 1 1 MOV.B @(d:16,Rs), Rd 2 1 MOV.B @Rs+, Rd 1 1 MOV.B @aa:8, Rd 1 1 MOV.B @aa:16, Rd 2 1 MOV.B Rs, @Rd 1 1 MOV.B Rs, @(d:16, Rd) 2 1 MOV.B Rs, @-Rd 1 1 MOV.B Rs, @aa:8 1 1 MOV.B Rs, @aa:16 2 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @Rs, Rd Word Data Internal Access Operation M N 2 2 1 1 MOV.W @(d:16, Rs), 2 Rd 1 MOV.W @Rs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W Rs, @Rd 1 1 MOV.W Rs, @(d:16, 2 Rd) 1 MOV.W Rs, @-Rd 1 1 1 MOV.W Rs, @aa:16 2 MOVFPE MOVFPE @aa:16, Rd Not supported MOVTPE MOVTPE.Rs, @aa:16 Not supported MULXU MULXU.Rs, Rd 1 NEG NEG.B Rd 1 NOP NOP 1 NOT NOT.B Rd 1 2 2 12 619 Instruction Mnemonic Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L OR OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 ORC ORC #xx:8, CCR 1 POP POP Rd 1 1 2 PUSH PUSH Rd 1 1 2 ROTL ROTL.B Rd 1 ROTR ROTR.B Rd 1 ROTXL ROTXL.B Rd 1 ROTXR ROTXR.B Rd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL.B Rd 1 SHAR SHAR.B Rd 1 SHLL SHLL.B Rd 1 SHLR SHLR.B Rd 1 SLEEP SLEEP 1 STC STC CCR, Rd 1 SUB SUB.B Rs, Rd 1 SUB.W Rs, Rd 1 SUBS SUBS.W #1/2, Rd 1 SUBX SUBX.B #xx:8, Rd 1 SUBX.B Rs, Rd 1 XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XORC #xx:8, CCR 1 XOR XORC Word Data Internal Access Operation M N Notes: All values left blank are zero. * n: Initial value in R4L. Source and destination are accessed n + 1 times each. 620 Appendix B Internal I/O Register B.1 Addresses Addr. (Last Register Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'80 -- -- -- EV PV E P Flash memory or external FLMCR1*3 FWE SWE -- -- EV PV E P FLMCR2*3 FLER -- -- -- -- -- ESU PSU addresses (in expanded modes) -- -- -- -- LB3 LB2 LB1 LB0 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 EBR2 *1, *2 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 EBR2 *3 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 C/A CHR PE O/E STOP MP CKS1 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER PER TEND MPB MPBT FLMCR VPP Bit Names *1, *2 H'81 *4 H'82 EBR1 *1 EBR1*2 H'83 H'84 H'85 H'86 H'87 H'88 SMR H'89 BRR H'8A SCR H'8B TDR H'8C SSR H'8D RDR SCI1 H'8E H'8F H'90 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE -- H'91 TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA H'92 FRCH H'93 FRCL H'94 FRT OCRAH OCRBH H'95 OCRAL OCRBL H'96 TCR IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 H'97 TOCR -- -- -- OCRS OEA OEB OLVLA OLVLB 621 Addr. (Last Register Byte) Name Bit 7 H'98 ICRAH H'99 ICRAL H'9A ICRBH H'9B ICRBL H'9C ICRCH H'9D ICRCL H'9E ICRDH H'9F ICRDL H'A0 TCR H'A1 DTR H'A2 TCNT H'A3 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module FRT OE OS -- -- -- CKS2 CKS1 CKS0 -- -- -- -- -- -- -- -- -- H'A4 TCR OE OS -- -- -- CKS2 CKS1 CKS0 H'A5 DTR H'A6 TCNT H'A7 -- -- -- -- -- -- -- -- -- H'A8 TCSR/ TCNT OVF WT/ IT TME -- RST/ NMI CKS2 CKS1 CKS0 WDT H'A9 TCNT H'AA PAODR PA 7 PA 6 PA 5 PA 4 PA 3 PA 2 PA 1 PA 0 Port A H'AB PAPIN/ PADDR PA 7/ PA 6/ PA 5/ PA 4/ PA 3/ PA 2/ PA 1/ PA 0/ PA 7DDR PA 6DDR PA 5DDR PA 4DDR PA 3DDR PA 2DDR PA 1DDR PA 0DDR H'AC P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Port 1 H'AD P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2 H'AE P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Port 3 H'AF -- -- H'B0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1 H'B1 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2 H'B2 P1DR P17 P16 P15 P14 P13 P12 P11 P10 Port 1 H'B3 P2DR P27 P26 P25 P24 P23 P22 P21 P20 Port 2 H'B4 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 H'B5 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4 H'B6 P3DR P37 P36 P35 P34 P33 P32 P31 P30 Port 3 H'B7 P4DR P47 P46 P45 P44 P43 P42 P41 P40 Port 4 622 -- -- -- -- -- -- -- PWM0 PWM1 -- Addr. (Last Register Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 H'B8 P5DDR -- -- -- -- -- P52DDR P51DDR P50DDR Port 5 H'B9 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6 H'BA P5DR -- -- -- -- -- P52 P51 P50 Port 5 H'BB P6DR P67 P66 P65 P64 P63 P62 P61 P60 Port 6 H'BC PBODR PB 7 PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 Port B H'BD P8DDR/ PBPIN --/ PB 7 P86DDR/ P85DDR/ P84DDR/ P83DDR/ P82DDR/ P81DDR/ P80DDR/ Port 8/ PB 6 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 Port B H'BE P7PIN/ PBDDR P77/ P76/ P75/ P74/ P73/ P72/ P71/ P70/ Port 7/ PB 7DDR PB 6DDR PB 5DDR PB 4DDR PB 3DDR PB 2DDR PB 1DDR PB 0DDR Port B H'BF P8DR -- H'C0 P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9 H'C1 P9DR P97 Bit Names P86 P85 P96 *2 P95 *2 P84 P83 P94 *3 P82 Bit 1 P81 Bit 0 P80 P93 P92 P91 P90 H'C2 WSCR RAMS RAM0 CKDBL FLSHE WMS1 WMS0 WC1 WC0 H'C3 STCR IICS IICD IICX IICE STAC MPE ICKS1 ICKS0 H'C4 SYSCR SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME -- -- -- -- -- MDS1 MDS0 *3 H'C5 MDCR EXPE H'C6 ISCR IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC H'C7 IER IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E H'C8 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'C9 TCSR CMFB CMFA OVF -- OS3 OS2 OS1 OS0 H'CA TCORA H'CB TCORB H'CC TCNT H'CD -- -- -- -- -- -- -- -- -- H'CE -- -- -- -- -- -- -- -- -- H'CF -- -- -- -- -- -- -- -- -- H'D0 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'D1 TCSR CMFB CMFA OVF -- OS3 OS2 OS1 OS0 H'D2 TCORA H'D3 TCORB H'D4 TCNT H'D5 -- -- -- -- -- -- -- -- -- H'D6 -- -- -- -- -- -- -- -- -- H'D7 -- -- -- -- -- -- -- -- -- Module Port 8 TMR0 TMR1 623 Addr. (Last Register Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'D8 SCI0 and I2C Bit Names SMR C/A CHR PE O/E STOP MP CKS1 CKS0 ICCR ICE IEIC MST TRS ACK CKS2 CKS1 CKS0 ICSR BBSY IRIC SCP -- AL AAS ADZ ACKB H'DA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 H'DB TDR H'DC SSR TDRE RDRF ORER FER PER TEND MPB MPBT H'DD RDR H'DE -- -- -- -- -- -- -- -- -- ICDR ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 -- -- -- -- -- -- -- -- -- ICMR/ SAR MLS/ SVA6 WAIT/ SVA5 --/ SVA4 --/ SVA3 --/ SVA2 BC2/ SVA1 BC1/ SVA0 BC0/ FS H'D9 H'DF BRR H'E0 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'E1 ADDRAL AD1 AD0 -- -- -- -- -- -- H'E2 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'E3 ADDRBL AD1 AD0 -- -- -- -- -- -- H'E4 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'E5 ADDRCL AD1 AD0 -- -- -- -- -- -- H'E6 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H'E7 ADDRDL AD1 AD0 -- -- -- -- -- -- H'E8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 H'E9 ADCR TRGE -- -- -- -- -- -- -- H'EA -- -- -- -- -- -- -- -- -- H'EB -- -- -- -- -- -- -- -- -- H'EC -- -- -- -- -- -- -- -- -- H'ED -- -- -- -- -- -- -- -- -- H'EE -- -- -- -- -- -- -- -- -- H'EF -- -- -- -- -- -- -- -- -- H'F0 HICR -- -- -- -- -- IBFIE2 IBFIE1 FGA20E HIF H'F1 KMIMR KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 H'F2 KMPCR KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR H'F3 KMIMRA KMIMR 15 624 KMIMR 14 KMIMR 13 KMIMR 12 KMIMR 11 KMIMR 10 KMIMR9 KMIMR8 A/D -- Addr. (Last Register Byte) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H'F4 IDR1 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 HIF1 H'F5 ODR1 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 H'F6 STR1 DBU DBU DBU DBU C/D DBU IBF OBF H'F7 -- -- -- -- -- -- -- -- -- H'F8 DADR0 H'F9 DADR1 H'FA DACR DAOE1 DAOE0 DAE -- -- -- -- -- H'FB -- -- -- -- -- -- -- -- -- H'FC IDR2 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 H'FD ODR2 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 H'FE STR2 DBU DBU DBU DBU C/D DBU IBF OBF H'FF -- -- -- -- -- -- -- -- -- Notes: *1 *2 *3 *4 Bit Names D/A HIF2 Applies to H8/3434F only (32k on-chip dual-power-supply flash memory version). Applies to H8/3437F only (60k on-chip dual-power-supply flash memory version). Applies to H8/3437SF only (60k on-chip single-power-supply flash memory version). Do not use this address with single-power-supply flash memory. FRT: SCI1: PWM0: PWM1: WDT: TMR0: Free-running timer Serial communication interface 1 Pulse-width modulation timer channel 0 Pulse-width modulation timer channel 1 Watchdog timer 8-bit timer channel 0 TMR1: 8-bit timer channel 1 A/D: Analog-to-digital converter SCI0: Serial communication interface 0 2 I C: I2C bus interface HIF: Host interface 625 B.2 Function Address onto which register is mapped Register name Abbreviation of register name TIER--Timer Interrupt Enable Register Bit No. Bit Initial value Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W H'FF90 4 ICIDE 0 R/W 3 2 OCIAE OCIBE 0 0 R/W R/W FRT 1 OVIE 0 R/W 0 -- 1 -- Name of on-chip supporting module Bit names (abbreviations). Bits marked "--" are reserved. Type of access permitted R Read only W Write only R/W Read or write Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt B Enable 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled. Output Compare Interrupt A Enable 0 Output compare interrupt request A is disabled. 1 Output compare interrupt request A is enabled. Input Capture Interrupt D Enable 0 Input capture interrupt request D is disabled. 1 Input capture interrupt request D is enabled. 626 Full name of bit Description of bit function (Dual-power-supply flash memory only) FLMCR--Flash Memory Control Register H'80 Flash memory * H8/3434F, H8/3437F Bit 7 6 5 4 3 2 1 0 VPP -- -- -- EV PV E P Initial value 0 0 0 0 0 0 0 0 Read/Write R -- -- -- R/W R/W R/W R/W Program Mode 0 Exit from program mode 1 Transition to program mode Erase Mode 0 Exit from erase mode 1 Transition to erase mode Program-Verify Mode 0 Exit from program-verify mode 1 Transition to program-verify mode Erase-Verify Mode 0 Exit from erase-verify mode 1 Transition to erase-verify mode Programming Power 0 12 V is not applied to FVPP 1 12 V is applied to FVPP 627 (Single-power-supply flash memory only) FLMCR1--Flash Memory Control Register 1 H'80 Flash memory * H8/3437SF Bit 7 6 5 4 3 2 1 0 P FWE SWE -- -- EV PV E Initial value 1 0 0 0 0 0 0 0 Read/Write R R/W -- -- R/W R/W R/W R/W Program Mode 0 Exit from program mode (initial value) 1 Transition to program mode [Setting condition] When SWE = 1 Erase Mode 0 Exit from erase mode (initial value) 1 Transition to erase mode [Setting condition] When SWE = 1 Program-Verify Mode 0 Exit from program-verify mode (initial value) 1 Transition to program-verify mode [Setting condition] When SWE = 1 Erase-Verify Mode 0 Exit from erase-verify mode (initial value) 1 Transition to erase-verify mode [Setting condition] When SWE = 1 Software Write Enable 0 Writes to flash memory disabled (initial value) 1 Writes to flash memory enabled Flash Write Enable (Controls programming and erasing of flash memory. In the H8/3437SF, this bit is always read as 1.) Note: The FLSHE bit in WSCR must be set to 1 in order for this register to be accessed. 628 (Single-power-supply flash memory only) FLMCR2--Flash Memory Control Register 2 H'81 Flash memory * H8/3437SF Bit 7 6 5 4 3 2 1 0 FLER -- -- -- -- -- ESU PSU Initial value 0 0 0 0 0 0 0 0 Read/Write R -- -- -- -- -- R/W R/W Program Setup 0 Program setup cleared (initial value) 1 Program setup [Setting condition] When SWE = 1 Erase Setup 0 Erase setup cleared (initial value) 1 Erase setup [Setting condition] When SWE = 1 Flash Memory Error 0 Flash memory is operating normally (initial value) 1 An error occurred during flash memory programming/erasing Note: The FLSHE bit in WSCR must be set to 1 in order for this register to be accessed. 629 (Dual-power-supply flash memory only) EBR1--Erase Block Register 1 H'82 Flash memory * H8/3434F Bit 7 6 5 4 3 2 1 0 -- -- -- -- LB3 LB2 LB1 LB0 Initial value 1 1 1 1 0 0 0 0 Read/Write -- -- -- -- R/W R/W R/W R/W Large Block 3 to 0 0 Corresponding block (LB3 to LB0) is not selected 1 Corresponding block (LB3 to LB0) is selected * H8/3437F Bit 7 6 5 4 3 2 1 0 LB7 LB6 LB5 LB4 LB3 LB2 LB1 LB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Large Block 7 to 0 0 Corresponding block (LB7 to LB0) is not selected (Initial value) 1 Corresponding block (LB7 to LB0) is selected 630 EBR2--Erase Block Register 2 H'83 Flash memory * H8/3434F, H8/3437F Bit 7 6 5 4 3 2 1 0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Small Block 7 to 0 0 Corresponding block (SB7 to SB0) is not selected 1 Corresponding block (SB7 to SB0) is selected * H8/3437SF Bit 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Erase Block 7 to 0 0 Corresponding block (EB7 to EB0) is not selected (initial value) 1 Corresponding block (EB7 to EB0) is selected 631 SMR--Serial Mode Register Bit H'88 SCI1 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 o clock 0 1 oP/4 clock 1 0 oP/16 clock 1 1 oP/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit added. Receive: Parity bit not checked. 1 Transmit: Parity bit added. Receive: Parity bit checked. Character Length 0 8-bit data length 1 7-bit data length Communication Mode 0 Asynchronous 1 Synchronous 632 BRR--Bit Rate Register H'89 SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Constant that determines the bit rate 633 SCR--Serial Control Register Bit H'8A SCI1 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 0 Asynchronous serial clock not output 1 Asynchronous serial clock output at SCK pin Clock Enable 1 0 Internal clock 1 External clock Transmit End Interrupt Enable 0 TSR-empty interrupt request is disabled. 1 TSR-empty interrupt request is enabled. Multiprocessor Interrupt Enable 0 Multiprocessor receive interrupt function is disabled. 1 Multiprocessor receive interrupt function is enabled. Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive interrupt and receive error interrupt requests are disabled. 1 Receive interrupt and receive error interrupt requests are enabled. Transmit Interrupt Enable 0 TDR-empty interrupt request is disabled. 1 TDR-empty interrupt request is enabled. 634 TDR--Transmit Data Register H'8B SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Transmit data 635 SSR--Serial Status Register Bit H'8C SCI1 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W) * R R R/W R/(W) * R/(W) * R/(W) * R/(W) * Multiprocessor Bit Transfer 0 Multiprocessor bit = 0 in transmit data. 1 Multiprocessor bit = 1 in transmit data. Multiprocessor Bit 0 Multiprocessor bit = 0 in receive data. 1 Multiprocessor bit = 1 in receive data. Transmit End 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set to 1 when TE = 0, or when TDRE = 1 at the end of character transmission. Parity Error 0 Cleared by reading PER = 1, then writing 0 in PER. 1 Set when a parity error occurs (parity of receive data does not match parity selected by O/E bit in SMR). Framing Error 0 Cleared by reading FER = 1, then writing 0 in FER. 1 Set when a framing error occurs (stop bit is 0). Overrun Error 0 Cleared by reading ORER = 1, then writing 0 in ORER. 1 Set when an overrun error occurs (next data is completely received while RDRF bit is set to 1). Receive Data Register Full 0 Cleared by reading RDRF = 1, then writing 0 in RDRF. 1 Set when one character is received normally and transferred from RSR to RDR. Transmit Data Register Empty 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set when: 1. Data is transferred from TDR to TSR. 2. TE is cleared while TDRE = 0. Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits. 636 RDR--Receive Data Register H'8D SCI1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Receive data 637 TIER--Timer Interrupt Enable Register Bit H'90 FRT 7 6 5 4 3 2 1 0 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE -- Initial value 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W -- Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt B Enable 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled. Output Compare Interrupt A Enable 0 Output compare interrupt request A is disabled. 1 Output compare interrupt request A is enabled. Input Capture Interrupt D Enable 0 Input capture interrupt request D is disabled. 1 Input capture interrupt request D is enabled. Input Capture Interrupt C Enable 0 Input capture interrupt request C is disabled. 1 Input capture interrupt request C is enabled. Input Capture Interrupt B Enable 0 Input capture interrupt request B is disabled. 1 Input capture interrupt request B is enabled. Input Capture Interrupt A Enable 0 Input capture interrupt request A is disabled. 1 Input capture interrupt request A is enabled. 638 TCSR--Timer Control/Status Register Bit H'91 FRT 7 6 5 4 3 2 1 0 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA Initial value 0 Read/Write R/(W) * 0 0 R/(W) * R/(W) * 0 R/(W) * 0 R/(W) * 0 R/(W) * 0 0 R/(W) * R/W Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by compare-match A. Timer Overflow Flag 0 Cleared by reading OVF = 1, then writing 0 in OVF. 1 Set when FRC changes from H'FFFF to H'0000. Output Compare Flag B 0 Cleared by reading OCFB = 1, then writing 0 in OCFB. 1 Set when FRC = OCRB. Output Compare Flag A 0 Cleared by reading OCFA = 1, then writing 0 in OCFA. 1 Set when FRC = OCRA. Input Capture Flag D 0 Cleared by reading ICFD = 1, then writing 0 in ICFD. 1 Set when FTID input signal is received. Input Capture Flag C 0 Cleared by reading ICFC = 1, then writing 0 in ICFC. 1 Set when FTIC input signal is received. Input Capture Flag B 0 Cleared by reading ICFB = 1, then writing 0 in ICFB. 1 Set when FTIB input causes FRC to be copied to ICRB. Input Capture Flag A 0 Cleared by reading ICFA = 1, then writing 0 in ICFA. 1 Set when FTIA input causes FRC to be copied to ICRA. Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits. 639 FRC (H and L)--Free-Running Counter H'92, H'93 FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Count value OCRA (H and L)--Output Compare Register A Bit Initial value Read/Write H'94, H'95 FRT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Continually compared with FRC OCFA is set when OCRA = FRC. OCRB (H and L)--Output Compare Register B H'94, H'95 FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Continually compared with FRC OCFB is set when OCRB = FRC. 640 TCR--Timer Control Register Bit H'96 FRT 7 6 5 4 3 2 1 0 IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 Internal clock source: oP/2 0 1 Internal clock source: oP/8 1 0 Internal clock source: oP/32 1 1 External clock source: counted on rising edge Buffer Enable B 0 ICRD is used for input capture D. 1 ICRD is buffer register for input capture B. Buffer Enable A 0 ICRC is used for input capture C. 1 ICRC is buffer register for input capture A. Input Edge Select D 0 Falling edge of FTID is valid. 1 Rising edge of FTID is valid. Input Edge Select C 0 Falling edge of FTIC is valid. 1 Rising edge of FTIC is valid. Input Edge Select B 0 Falling edge of FTIB is valid. 1 Rising edge of FTIB is valid. Input Edge Select A 0 Falling edge of FTIA is valid. 1 Rising edge of FTIA is valid. 641 TOCR--Timer Output Compare Control Register Bit H'97 FRT 7 6 5 4 3 2 1 0 -- -- -- OCRS OEA OEB OLVLA OLVLB Initial value 1 1 1 0 0 0 0 0 Read/Write -- -- -- R/W R/W R/W R/W R/W Output Level B 0 Compare-match B causes 0 output. 1 Compare-match B causes 1 output. Output Level A 0 Compare-match A causes 0 output. 1 Compare-match A causes 1 output. Output Enable B 0 Output compare B output is disabled. 1 Output compare B output is enabled. Output Enable A 0 Output compare A output is disabled. 1 Output compare A output is enabled. Output Compare Register Select 0 The CPU can access OCRA. 1 The CPU can access OCRB. ICRA (H and L)--Input Capture Register A Bit 15 14 13 12 11 10 H'98, H'99 9 8 7 6 5 4 FRT 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R Contains FRC count captured on FTIA input. 642 ICRB (H and L)--Input Capture Register B H'9A, H'9B FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R Contains FRC count captured on FTIB input. ICRC (H and L)--Input Capture Register C Bit 15 14 13 12 11 10 H'9C, H'9D 9 8 7 6 5 4 FRT 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R Contains FRC count captured on FTIC input, or old ICRA value in buffer mode. ICRD (H and L)--Input Capture Register D H'9E, H'9F FRT Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R Contains FRC count captured on FTID input, or old ICRB value in buffer mode. 643 TCR--Timer Control Register Bit H'A0 PWM0 7 6 5 4 3 2 1 0 OE OS -- -- -- CKS2 CKS1 CKS0 Initial value 0 0 1 1 1 0 0 0 Read/Write R/W R/W -- -- -- R/W R/W R/W Clock Select (Values when oP = 10 MHz) Internal clock freq. Resolution PWM period PWM frequency 0 0 0 oP/2 200 ns 50 s 20 kHz 1 oP/8 800 ns 200 s 5 kHz oP/32 3.2 s 800 s 1.25 kHz 1 oP/128 12.8 s 3.2 ms 312.5 Hz 1 0 0 1 0 oP/256 25.6 s 6.4 ms 156.3 Hz 1 oP/1024 102.4 s 25.6 ms 39.1 Hz 1 0 oP/2048 204.8 s 51.2 ms 19.5 Hz 1 oP/4096 409.6 s 102.4 ms 9.8 Hz Output Select 0 Positive logic 1 Negative logic Output Enable 0 PWM output disabled; TCNT cleared to H'00 and stops. 1 PWM output enabled; TCNT runs. DTR--Duty Register H'A1 PWM0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Pulse duty cycle 644 TCNT--Timer Counter H'A2 PWM0 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value (runs from H'00 to H'F9, then repeats from H'00) TCR--Timer Control Register Bit H'A4 PWM1 7 6 5 4 3 2 1 0 OE OS -- -- -- CKS2 CKS1 CKS0 Initial value 0 0 1 1 1 0 0 0 Read/Write R/W R/W -- -- -- R/W R/W R/W Note: Bit functions are the same as for PWM0. DTR--Duty Register H'A5 PWM1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for PWM0. TCNT--Timer Counter Bit 7 H'A6 6 5 4 3 PWM1 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for PWM0. 645 TCSR--Timer Control/Status Register Bit H'A8 WDT 7 6 5 4 3 2 1 0 OVF WT/IT TME -- RST/NMI CKS2 CKS1 CKS0 Initial value 0 0 0 1 0 0 0 0 Read/Write R/(W)* R/W R/W -- R/W R/W R/W R/W Clock Select 2 to 0 0 0 0 oP/2 1 oP/32 1 0 oP/64 1 oP/128 1 0 0 oP/256 1 oP/512 1 0 oP/2048 1 oP/4096 Reset or NMI 0 Functions as NMI (initial value) 1 Functions as reset Timer Enable 0 Timer disabled: TCNT is initialized to H'00 and stopped (initial value) 1 Timer enabled: TCNT runs; CPU interrupts can be requested Timer Mode Select 0 Interval timer mode (OVF interrupt request) (initial value) 1 Watchdog timer mode (generates reset or NMI signal) Overflow Flag 0 Cleared by reading OVF = 1, then writing 0 in OVF (initial value) 1 Set when TCNT changes from H'FF to H'00 Note: * Only 0 can be written, to clear the flag. 646 TCNT--Timer Counter Bit 7 H'A9 (read), H'A8 (write) 6 5 4 3 2 WDT 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value P1PCR--Port 1 Input Pull-Up Control Register Bit 7 6 5 H'AC 4 3 Port 1 2 1 0 P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 1 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on. P2PCR--Port 2 Input Pull-Up Control Register Bit 7 6 5 H'AD 4 3 Port 2 2 1 0 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 2 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on. 647 P3PCR--Port 3 Input Pull-Up Control Register Bit 7 6 5 H'AE 4 3 Port 3 2 1 0 P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 3 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on. P1DDR--Port 1 Data Direction Register Bit 6 7 H'B0 5 4 3 Port 1 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Mode 1 Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Modes 2 and 3 Port 1 Input/Output Control 0 Input port 1 Output port P1DR--Port 1 Data Register Bit H'B2 Port 1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 648 P2DDR--Port 2 Data Direction Register Bit 6 7 H'B1 5 4 3 Port 2 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Mode 1 Initial value 1 1 1 1 1 1 1 1 Read/Write -- -- -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Modes 2 and 3 Port 2 Input/Output Control 0 Input port 1 Output port P2DR--Port 2 Data Register Bit H'B3 Port 2 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P3DDR--Port 3 Data Direction Register Bit 7 6 5 H'B4 4 3 Port 3 2 1 0 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 3 Input/Output Control 0 Input port 1 Output port 649 P3DR--Port 3 Data Register Bit H'B6 Port 3 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P4DDR--Port 4 Data Direction Register Bit 7 6 H'B5 5 4 3 Port 4 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 4 Input/Output Control 0 Input port 1 Output port P4DR--Port 4 Data Register Bit H'B7 Port 4 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P5DDR--Port 5 Data Direction Register Bit H'B8 Port 5 7 6 5 4 3 -- -- -- -- -- Initial value 1 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- W W W 2 1 0 P52DDR P51DDR P50DDR Port 5 Input/Output Control 0 Input port 1 Output port 650 P5DR--Port 5 Data Register Bit H'BA Port 5 7 6 5 4 3 2 1 0 -- -- -- -- -- P52 P51 P50 Initial value 1 1 1 1 1 0 0 0 Read/Write -- -- -- -- -- R/W R/W R/W P6DDR--Port 6 Data Direction Register Bit 7 6 5 H'B9 4 Port 6 3 2 1 0 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 6 Input/Output Control 0 Input port 1 Output port P6DR--Port 6 Data Register Bit H'BB Port 6 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P7PIN--Port 7 Input Data Register Bit H'BE Port 7 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 Initial value * * * * * * * * Read/Write R R R R R R R R Note: * Depends on the levels of pins P77 to P70. 651 P8DDR--Port 8 Data Direction Register Bit 7 -- 6 5 H'BD 4 Port 8 3 2 1 0 P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Initial value 1 0 0 0 0 0 0 0 Read/Write -- W W W W W W W Port 8 Input/Output Control 0 Input port 1 Output port P8DR--Port 8 Data Register Bit H'BF Port 8 7 6 5 4 3 2 1 0 -- P86 P85 P84 P83 P82 P81 P80 Initial value 1 0 0 0 0 0 0 0 Read/Write -- R/W R/W R/W R/W R/W R/W R/W P9DDR--Port 9 Data Direction Register Bit 7 6 5 H'C0 4 Port 9 3 2 1 0 P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Modes 1 and 2 Initial value 0 1 0 0 0 0 0 0 Read/Write W -- W W W W W W Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Mode 3 Port 9 Input/Output Control 0 Input port 1 Output port 652 P9DR--Port 9 Data Register Bit H'C1 Port 9 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Initial value 0 * 0 0 0 0 0 0 Read/Write R/W R R/W R/W R/W R/W R/W R/W Note: * Depends on the level of pin P96. PADDR--Port A Data Direction Register Bit 7 6 H'AB 5 4 3 Port A 2 1 0 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port A Input/Output Control 0 Input port 1 Output port PAPIN--Port A Input Data Register Bit H'AB Port A 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Initial value --* --* --* --* --* --* --* --* Read/Write R R R R R R R R Note: * Depends on the levels of pins PA7 to PA0. PAODR--Port A Output Data Register Bit H'AA Port A 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port A Output Data/Input Pull-Up Control During output During input 0 0 output Input pull-up transistor off 1 1 output Input pull-up transistor on 653 PBDDR--Port B Data Direction Register Bit 7 6 H'BE 5 4 3 Port B 2 1 0 PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port B Input/Output Control 0 Input port 1 Output port PBPIN--Port B Input Data Register Bit H'BD Port B 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value --* --* --* --* --* --* --* --* Read/Write R R R R R R R R Note: * Depends on the levels of pins PB7 to PB0. PBODR--Port B Output Data Register Bit H'BC Port B 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port B Output Data/Input Pull-Up Control 654 During output During input 0 0 output Input pull-up transistor off 1 1 output Input pull-up transistor on WSCR--Wait-State Control Register Bit H'C2 System control 7 6 5 4 3 2 1 0 RAMS RAM0 CKDBL FLSHE WMS1 WMS0 WC1 WC0 Initial value 0 0 0 0 1 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Wait Count 0 0 No wait states inserted by wait-state controller (initial value) 0 1 1 state inserted 1 0 2 states inserted 1 1 3 states inserted Wait Mode Select 0 0 Programmable wait mode 0 1 No wait states inserted by wait-state controller 1 0 Pin wait mode (initial value) 1 1 Pin auto-wait mode Flash Memory Control Register Enable H8/3437SF (Single-power-supply flash memory only) 0 Flash memory control registers are in unselected state (Initial value) 1 Flash memory control registers are in selected state Clock Double 0 Supporting module clock frequency is not divided (oP = o) (initial value) 1 Supporting module clock frequency is divided by two (oP = o/2) RAM Select and RAM Area Select H8/3434F (Dual-power-supply flash memory only) RAMS, RAM0 RAM Area ROM Area 00 None -- 01 H'FC80 to H'FCFF H'0080 to H'00FF 10 H'FC80 to H'FD7F H'0080 to H'017F 11 H'FC00 to H'FC7F H'0000 to H'007F H8/3437F RAMS, RAM0 RAM Area ROM Area 00 None -- 01 H'F880 to H'F8FF H'0080 to H'00FF 10 H'F880 to H'F97F H'0080 to H'017F 11 H'F800 to H'F87F H'0000 to H'007F 655 STCR--Serial/Timer Control Register Bit H'C3 System Control 7 6 5 4 3 2 1 0 IICS IICD IICX IICE STAC MPE ICKS1 ICKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Internal Clock Source Select See TCR under TMR0 and TMR1. Multiprocessor Enable 0 Multiprocessor communication function is disabled. 1 Multiprocessor communication function is enabled. Slave Mode Control Input Switch 0 CS2 and IOW are enabled 1 ECS2 and EIOW are enabled I2C Master Enable 0 1 I2C bus interface data registers and control registers are disabled (initial value) I2C bus interface data registers and control registers are enabled I2C Transfer Rate Select IICX CKS2*2 CKS1*2 CKS0*2 Clock 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 oP/28 oP/40 oP/48 oP/64 oP/80 oP/100 oP/112 oP/128 oP/56 oP/80 oP/96 oP/128 oP/160 oP/200 oP/224 oP/256 oP = 4 MHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz 71.4 kHz 50.0 kHz 41.7 kHz 31.3 kHz 25.0 kHz 20.0 kHz 17.9 kHz 15.6 kHz Transfer Rate*1 oP = 5 MHz oP = 8 MHz oP = 10 MHz 179 kHz 286 kHz 357 kHz 125 kHz 200 kHz 250 kHz 104 kHz 167 kHz 208 kHz 78.1 kHz 125 kHz 156 kHz 62.5 kHz 100 kHz 125 kHz 50.0 kHz 80.0 kHz 100 kHz 44.6 kHz 71.4 kHz 89.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz 89.3 kHz 143 kHz 179 kHz 62.5 kHz 100 kHz 125 kHz 52.1 kHz 83.3 kHz 104 kHz 39.1 kHz 62.5 kHz 78.1 kHz 31.3 kHz 50.0 kHz 62.5 kHz 25.0 kHz 40.0 kHz 50.0 kHz 22.3 kHz 35.7 kHz 44.6 kHz 19.5 kHz 31.3 kHz 39.1 kHz oP = 16 MHz 571 kHz 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz Notes: *1 oP = o. *2 CKS2 to CKS0 are bits 2 to 0 of the I2C bus control register in the I2C bus interface. I2C Extra Buffer Reserve I2C Extra Buffer Select 0 PA7 to PA4 are normal input/output pins 1 PA7 to PA4 are selected for bus drive 656 SYSCR--System Control Register Bit H'C4 System Control 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 XRST NMIEG HIE RAME Initial value 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R R/W R/W R/W RAM Enable 0 On-chip RAM is disabled. 1 On-chip RAM is enabled. (initial value) Host Interface Enable 0 Host interface is prohibited (initial value) 1 Host interface is allowed (slave mode) NMI Edge 0 Falling edge of NMI is detected. 1 Rising edge of NMI is detected. External Reset 0 1 Reset was caused by watchdog timer overflow Reset was caused by external reset signal (initial value) Standby Timer Select 2 to 0 (ZTAT and Mask ROM Versions) 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 -- -- Clock settling time = 8,192 states (initial value) Clock settling time = 16,384 states Clock settling time = 32,768 states Clock settling time = 65,536 states Clock settling time = 131,072 states Unused Standby Timer Select 2 to 0 (F-ZTAT Version) 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 -- Settling time = 8,192 states (initial value) Settling time = 16,384 states Settling time = 32,768 states Settling time = 65,536 states Settling time = 131,072 states Settling time = 1,024 states Unused Software Standby 0 SLEEP instruction causes transition to sleep mode. (initial value) 1 SLEEP instruction causes transition to software standby mode. 657 MDCR--Mode Control Register H'C5 System Control * Except H8/3437SF Bit 7 6 5 4 3 2 1 0 -- -- -- -- -- -- MDS1 MDS0 Initial value 1 1 1 0 0 1 * * Read/Write -- -- -- -- -- -- R R Mode Select Bits Value at mode pins. Note: * Determined by inputs at pins MD1 and MD0. * H8/3437SF Bit 7 6 5 4 3 2 1 0 EXPE -- -- -- -- -- MDS1 MDS0 Initial value * 1 1 0 0 1 * * Read/Write R/W* -- -- -- -- -- R R Mode Select Bits Value at mode pins. Expanded Mode Enable 0 Single-chip mode is selected. 1 Expanded mode is selected (writable in boot mode only). Note: * Determined by inputs at pins MD1 and MD0. 658 ISCR--IRQ Sense Control Register Bit 7 6 H'C6 5 4 3 System Control 2 1 0 IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IRQ0 to IRQ7 Sense Control 0 IRQ0 to IRQ7 are level-sensed (active low). 1 IRQ0 to IRQ7 are edge-sensed (falling edge). IER--IRQ Enable Register Bit H'C7 System Control 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W IRQ0 to IRQ7 Enable 0 IRQ0 to IRQ7 are disabled. 1 IRQ0 to IRQ7 are enabled. 659 TCR--Timer Control Register Bit H'C8 TMR0 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select TCR STCR Description CKS2 CKS1 CKS0 ICKS1 ICKS0 0 0 0 -- -- Timer stopped 0 0 1 -- 0 oP/8 internal clock, falling edge 0 0 1 -- 1 oP/2 internal clock, falling edge 0 1 0 -- 0 oP/64 internal clock, falling edge 0 1 0 -- 1 oP/32 internal clock, falling edge 0 1 1 -- 0 oP/1024 internal clock, falling edge 0 1 1 -- 1 oP/256 internal clock, falling edge 1 0 0 -- -- Timer stopped 1 0 1 -- -- External clock, rising edge 1 1 0 -- -- External clock, falling edge 1 1 1 -- -- External clock, rising and falling edges Counter Clear 0 0 Counter is not cleared. 0 1 Cleared by compare-match A. 1 0 Cleared by compare-match B. 1 1 Cleared on rising edge of external reset input. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. 660 TCSR--Timer Control/Status Register Bit 7 Initial value Read/Write 6 H'C9 5 4 3 OS3 *2 TMR0 2 OS2 *2 1 OS1*2 0 OS0*2 CMFB CMFA OVF -- 0 0 0 1 0 0 0 0 -- R/W R/W R/W R/W R/(W) *1 R/(W)*1 R/(W)*1 Output Select 0 0 No change on compare-match A. 0 1 Output 0 on compare-match A. 1 0 Output 1 on compare-match A. 1 1 Invert (toggle) output on compare-match A. Output Select 0 0 No change on compare-match B. 0 1 Output 0 on compare-match B. 1 0 Output 1 on compare-match B. 1 1 Invert (toggle) output on compare-match B. Timer Overflow Flag 0 Cleared by reading OVF = 1, then writing 0 in OVF. 1 Set when TCNT changes from H'FF to H'00. Compare-Match Flag A 0 Cleared by reading CMFA = 1, then writing 0 in CMFA. 1 Set when TCNT = TCORA. Compare-Match Flag B 0 Cleared by reading CMFB = 1, then writing 0 in CMFB. 1 Set when TCNT = TCORB. Notes: *1 Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. *2 When all four bits (OS3 to OS0) are cleared to 0, output is disabled. 661 TCORA--Time Constant Register A H'CA TMR0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The CMFA bit is set to 1 when TCORA = TCNT. TCORB--Time Constant Register B Bit 7 6 H'CB 5 4 3 TMR0 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W The CMFB bit is set to 1 when TCORB = TCNT. TCNT--Timer Counter H'CC TMR0 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value 662 TCR--Timer Control Register Bit H'D0 TMR1 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select TCR STCR Description CKS2 CKS1 CKS0 ICKS1 ICKS0 0 0 0 -- -- Timer stopped 0 0 1 0 -- oP/8 internal clock, falling edge 0 0 1 1 -- oP/2 internal clock, falling edge 0 1 0 0 -- oP/64 internal clock, falling edge 0 1 0 1 -- oP/128 internal clock, falling edge 0 1 1 0 -- oP/1024 internal clock, falling edge 0 1 1 1 -- oP/2048 internal clock, falling edge 1 0 0 -- -- Timer stopped 1 0 1 -- -- External clock, rising edge 1 1 0 -- -- External clock, falling edge 1 1 1 -- -- External clock, rising and falling edges Counter Clear 0 0 Counter is not cleared. 0 1 Cleared by compare-match A. 1 0 Cleared by compare-match B. 1 1 Cleared on rising edge of external reset input. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. 663 TCSR--Timer Control/Status Register Bit Initial value Read/Write H'D1 TMR1 7 6 5 4 CMFB CMFA OVF -- 0 0 0 1 0 0 0 0 -- R/W R/W R/W R/W R/(W) *1 R/(W) *1 R/(W) *1 3 2 OS3*2 0 1 OS2 *2 OS1*2 OS0*2 Notes: Bit functions are the same as for TMR0. *1 Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. *2 When all four bits (OS3 to OS0) are cleared to 0, output is disabled. TCORA--Time Constant Register A H'D2 TMR1 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for TMR0. TCORB--Time Constant Register B Bit 7 6 H'D3 5 4 3 TMR1 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for TMR0. TCNT--Timer Counter H'D4 TMR1 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for TMR0. 664 ICCR--I2C Bus Control Register Bit I 2C H'D8 7 6 5 4 3 2 1 0 ICE IEIC MST TRS ACK CKS2 CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Transfer Clock Select IICX* CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock oP/28 oP/40 oP/48 oP/64 oP/80 oP/100 oP/112 oP/128 oP/56 oP/80 oP/96 oP/128 oP/160 oP/200 oP/224 oP/256 oP = 4 MHz 143 kHz 100 kHz 83.3 kHz 62.5 kHz 50.0 kHz 40.0 kHz 35.7 kHz 31.3 kHz 71.4 kHz 50.0 kHz 41.7 kHz 31.3 kHz 25.0 kHz 20.0 kHz 17.9 kHz 15.6 kHz Transfer Rate oP = 5 MHz oP = 8 MHz oP = 10 MHz 179 kHz 286 kHz 357 kHz 125 kHz 200 kHz 250 kHz 104 kHz 167 kHz 208 kHz 78.1 kHz 125 kHz 156 kHz 62.5 kHz 100 kHz 125 kHz 50.0 kHz 80.0 kHz 100 kHz 44.6 kHz 71.4 kHz 89.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz 89.3 kHz 143 kHz 179 kHz 62.5 kHz 100 kHz 125 kHz 52.1 kHz 83.3 kHz 104 kHz 39.1 kHz 62.5 kHz 78.1 kHz 31.3 kHz 50.0 kHz 62.5 kHz 25.0 kHz 40.0 kHz 50.0 kHz 22.3 kHz 35.7 kHz 44.6 kHz 19.5 kHz 31.3 kHz 39.1 kHz oP = 16 MHz 571 kHz 400 kHz 333 kHz 250 kHz 200 kHz 160 kHz 143 kHz 125 kHz 286 kHz 200 kHz 167 kHz 125 kHz 100 kHz 80.0 kHz 71.4 kHz 62.5 kHz Note: When oP = o. The shaded setting exceeds the maximum transfer rate in the standard I2C bus specifications. * IICX is bit 5 of the serial timer control register (STCR). Acknowledgement Mode Select 0 Acknowledgement mode 1 Serial mode Master/Slave Select and Transmit/Receive Select 0 0 Slave receive mode 1 Slave transmit mode 1 0 Master receive mode 1 Master transmit mode I2C Bus Interface Interrupt Enable 0 Interrupts disabled 1 Interrupts enabled I2C Bus Interface Enable 0 Interface module disabled, with pins SCL and SDA operating as ports 1 Interface module enabled for transfer operations, with pins SCL and SDA capable of bus drive 665 ICSR--I2C Bus Status Register Bit I 2C H'D9 7 6 5 4 3 2 1 0 BBSY IRIC SCP -- AL AAS ADZ ACKB Initial value 0 0 1 1 0 0 0 0 Read/Write R/W R/(W)* W -- R/(W)* R/(W)* R/(W)* R/W Acknowledge Bit 0 Receive mode: 0 is output at acknowledge output timing Transmit mode: indicates that the receiving device has acknowledged the data 1 Receive mode: 1 is output at acknowledge output timing Transmit mode: indicates that the receiving device has not acknowledged the data General Call Address Recognition Flag 0 General call address not recognized Cleared when ICDR data is written (transmit mode) or read (receive mode) Cleared by reading ADZ = 1, then writing 0 1 General call address recognized Set when the general call address is detected in slave receive mode Slave Address Recognition Flag 0 Slave address or general call address not recognized (Initial value) Cleared when ICDR data is written (transmit mode) or read (receive mode) Cleared by reading AAS = 1, then writing 0 1 Slave address or general call address recognized Set when the slave address or general call address is detected in slave receive mode Arbitration Lost Flag 0 Bus arbitration won Cleared when ICDR data is written (transmit mode) or read (receive mode) Cleared by reading AL = 1, then writing 0 1 Arbitration lost Set if the internal SDA and bus line disagree at the rise of SCL in master transmit mode Set if the internal SCL is high at the fall of SCL in master transmit mode Start Condition/Stop Condition Prohibit 0 Writing 0 issues a start or stop condition, in combination with BBSY 1 Reading always results in 1 Writing is ignored I2C Bus Interface Interrupt Request Flag Bus Busy 0 Bus is free Cleared by detection of a stop condition 1 Bus is busy Set by detection of a start condition 0 Waiting for transfer, or transfer in progress Cleared by reading IRIC = 1, then writing 0 1 Interrupt requested Set to 1 at the following times: Master mode * End of data transfer * Bus arbitration lost Slave mode (when FS = 0) * When the slave address is matched, and whenever a data transfer ends at timing of a retransmit start condition after address matching or a stop condition is detected * When a general call address is detected, and whenever a data transfer ends at timing of a retransmit start condition after address detection or a stop condition is detected Slave mode (when FS = 1) * End of data transfer Note: * Only 0 can be written, to clear the flag. 666 SMR--Serial Mode Register Bit H'D8 SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 o clock 0 1 oP/4 clock 1 0 oP/16 clock 1 1 oP/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit added. Receive: Parity bit not checked. 1 Transmit: Parity bit added. Receive: Parity bit checked. Character Length 0 8-bit data length 1 7-bit data length Communication Mode 0 Asynchronous 1 Synchronous Note: Bit functions are the same as for SCI1. 667 BRR--Bit Rate Register H'D9 SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Constant that determines the bit rate Note: Bit functions are the same as for SCI1. 668 SCR--Serial Control Register Bit H'DA SCI0 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 0 Asynchronous serial clock not output 1 Asynchronous serial clock output at SCK pin Clock Enable 1 0 Internal clock 1 External clock Transmit End Interrupt Enable 0 TSR-empty interrupt request is disabled. 1 TSR-empty interrupt request is enabled. Multiprocessor Interrupt Enable 0 Multiprocessor receive interrupt function is disabled. 1 Multiprocessor receive interrupt function is enabled. Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive-end interrupt and receive-error interrupt requests are disabled. 1 Receive-end interrupt and receive-error interrupt requests are enabled. Transmit Interrupt Enable 0 TDR-empty interrupt request is disabled. 1 TDR-empty interrupt request is enabled. Note: Bit functions are the same as for SCI1. 669 TDR--Transmit Data Register H'DB SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Transmit data Note: Bit functions are the same as for SCI1. 670 SSR--Serial Status Register Bit H'DC SCI0 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W) * R R R/W R/(W) * R/(W) * R/(W) * R/(W) * Multiprocessor Bit Transfer 0 Multiprocessor bit = 0 in transmit data. 1 Multiprocessor bit = 1 in transmit data. Multiprocessor Bit 0 Multiprocessor bit = 0 in receive data. 1 Multiprocessor bit = 1 in receive data. Transmit End 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set to 1 when TE = 0, or when TDRE = 1 at the end of character transmission. Parity Error 0 Cleared by reading PER = 1, then writing 0 in PER. 1 Set when a parity error occurs (parity of receive data does not match parity selected by O/E bit in SMR). Framing Error 0 Cleared by reading FER = 1, then writing 0 in FER. 1 Set when a framing error occurs (stop bit is 0). Overrun Error 0 Cleared by reading ORER = 1, then writing 0 in ORER. 1 Set when an overrun error occurs (next data is completely received while RDRF bit is set to 1). Receive Data Register Full 0 Cleared by reading RDRF = 1, then writing 0 in RDRF. 1 Set when one character is received normally and transferred from RSR to RDR. Transmit Data Register Empty 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set when: 1. Data is transferred from TDR to TSR. 2. TE is cleared while TDRE = 0. Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits. Bit functions are the same as for SCI1. 671 RDR--Receive Data Register H'DD SCI0 Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Receive data Note: Bit functions are the same as for SCI1. ICDR--I2C Bus Data Register Bit I 2C H'DE 7 6 5 4 3 2 1 0 ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0 Initial value -- -- -- -- -- -- -- -- Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Transmit/receive data SAR--Slave Address Register Bit I 2C H'DF 7 6 5 4 3 2 1 0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Slave address Format Select 0 Addressing format, slave address recognized 1 Non-addressing format 672 ICMR--I 2C Bus Mode Register Bit I 2C H'DF 7 6 5 4 3 2 1 0 MLS WAIT -- -- -- BC2 BC1 BC0 Initial value 0 0 1 1 1 0 0 0 Read/Write R/W R/W -- -- -- R/W R/W R/W Bit Counter BC2 BC1 BC0 0 0 1 1 0 1 Bits/Frame Serial Mode Acknowledgement Mode 0 8 9 1 1 2 0 2 3 1 3 4 0 4 5 1 5 6 0 6 7 1 7 8 Wait Insertion Bit 0 Data and acknowledge transferred consecutively 1 Wait inserted between data and acknowledge MSB-First/LSB-First 0 MSB-first 1 LSB-first 673 ADDRA (H and L)--A/D Data Register A Bit 15 14 13 12 11 10 H'E0, H'E1 9 8 7 6 A/D 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R ADDRAH ADDRAL A/D Conversion Data 10-bit data giving an A/D conversion result ADDRB (H and L)--A/D Data Register B Bit 15 14 13 12 11 10 Reserved Bits H'E2, H'E3 9 8 7 6 A/D 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R ADDRBH ADDRBL A/D Conversion Data 10-bit data giving an A/D conversion result ADDRC (H and L)--A/D Data Register C Bit 15 14 13 12 11 10 Reserved Bits H'E4, H'E5 9 8 7 6 A/D 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R ADDRCH A/D Conversion Data 10-bit data giving an A/D conversion result 674 ADDRCL Reserved Bits ADDRD (H and L)--A/D Data Register D Bit 15 14 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- -- -- -- -- -- 11 10 9 8 7 6 A/D 5 13 12 H'E6, H'E7 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R R R R R R R R R ADDRDH A/D Conversion Data 10-bit data giving an A/D conversion result ADDRDL Reserved Bits 675 ADCSR--A/D Control/Status Register Bit H'E8 A/D 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/W R/W R/W R/W R/W R/W R/W Channel Select CH2 CH1 0 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 Single Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Clock Select 0 Conversion time = 266 states (max) 1 Conversion time = 134 states (max) Note: When oP = o Scan Mode 0 Single mode 1 Scan mode A/D Start 0 A/D conversion is halted. 1 1. Single mode: One A/D conversion is performed, then this bit is automatically cleared to 0. 2. Scan mode: A/C conversion starts and continues cyclically on all selected channels until 0 is written in this bit. A/D Interrupt Enable 0 The A/D interrupt request (ADI) is disabled. 1 The A/D interrupt request (ADI) is enabled. A/D End Flag 0 Cleared from 1 to 0 when CPU reads ADF = 1, then writes 0 in ADF. 1 Set to 1 at the following times: 1. Single mode: at the completion of A/D conversion 2. Scan mode: when all selected channels have been converted. Note: * Only 0 can be written, to clear the flag. 676 ADCR--A/D Control Register Bit H'E9 A/D 7 6 5 4 3 2 1 0 TRGE -- -- -- -- -- -- -- Initial value 0 1 1 1 1 1 1 1 Read/Write R/W -- -- -- -- -- -- -- Trigger Enable 0 ADTRG is disabled. 1 ADTRG is enabled. A/D conversion can be started by external trigger, or by software. HICR--Host Interface Control Register Bit H'F0 HIF 7 6 5 4 3 2 -- -- -- -- -- IBFIE2 Initial value 1 1 1 1 1 0 0 0 Host Read/Write -- -- -- -- -- -- -- -- Slave Read/Write -- -- -- -- -- R/W R/W R/W 1 0 IBFIE1 FGA20E Fast Gate A20 Enable 0 Fast A20 gate function disabled 1 Fast A20 gate function enabled Input Buffer Full Interrupt Enable 1 0 IDR1 input buffer full interrupt disabled 1 IDR1 input buffer full interrupt enabled Input Buffer Full Interrupt Enable 2 0 IDR2 input buffer full interrupt disabled 1 IDR2 input buffer full interrupt enabled 677 KMIMR--Keyboard Matrix Interrupt Mask Register Bit 7 6 5 4 H'F1 HIF 3 2 0 1 KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value 1 0 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Keyboard Matrix Interrupt Mask 0 Key-sense input interrupt request enabled 1 Key-sense input interrupt request disabled (initial value)* Note: * Initial value of KMIMR6 is 0. KMPCR--Port 6 Input Pull-Up Control Register Bit 7 6 5 4 H'F2 HIF (port 6) 3 2 1 0 KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 6 Input Pull-Up Control 0 Input pull-up transistor is off. (initial value) 1 Input pull-up transistor is on. KMIMRA--Keyboard Matrix Interrupt Mask Register A H'F3 Bit 7 6 5 4 HIF 3 2 1 0 KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Keyboard Matrix Interrupt Mask 0 Key-sense input interrupt request enabled 1 Key-sense input interrupt request disabled (initial value) 678 IDR1--Input Data Register 1 Bit H'F4 HIF 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Initial value -- -- -- -- -- -- -- -- Host Read/Write W W W W W W W W Slave Read/Write R R R R R R R R Input data (command or data input from host processor) ODR1--Output Data Register 1 Bit H'F5 HIF 7 6 5 4 3 2 1 0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Initial value -- -- -- -- -- -- -- -- Host Read/Write R R R R R R R R Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Output data (data output to host processor) 679 STR1--Status Register 1 Bit H'F6 HIF 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF Initial value 0 0 0 0 0 0 0 0 Host Read/Write R R R R R R R R Slave Read/Write R/W R/W R/W R/W R R/W R R Output Buffer Full 0 Host has read ODR1 1 Slave has written to ODR1 Input Buffer Full 0 Slave has read IDR1 1 Host has written to IDR1 Defined By User Command/Data 0 IDR1 contains data 1 IDR1 contains a command Defined By User DADR0--D/A Data Register 0 H'F8 D/A Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data to be converted 680 DADR1--D/A Data Register 1 H'F9 D/A Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data to be converted DACR--D/A Control Register Bit H'FA 7 6 5 DAOE1 DAOE0 DAE 4 3 D/A 2 1 0 Initial value 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W -- -- -- -- -- D/A Enable Bit 7 Bit 6 DAOE1 DAOE0 0 1 Bit 5 Description DAE 0 -- Channels 0 and 1 disabled 1 0 Channel 0 enabled, channel 1 disabled 1 Channels 0 and 1 enabled 0 Channel 0 disabled, channel 1 enabled 1 Channels 0 and 1 enabled -- Channels 0 and 1 enabled 0 1 D/A Output Enable 0 0 Analog output at DA0 disabled 1 Analog conversion in channel 0 and output at DA0 enabled D/A Output Enable 1 0 Analog output at DA1 disabled 1 Analog conversion in channel 1 and output at DA1 enabled 681 IDR2--Input Data Register 2 Bit H'FC HIF 7 6 5 4 3 2 1 0 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0 Initial value -- -- -- -- -- -- -- -- Host Read/Write W W W W W W W W Slave Read/Write R R R R R R R R Input data (command or data input from host processor) ODR2--Output Data Register 2 Bit H'FD HIF 7 6 5 4 3 2 1 0 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Initial value -- -- -- -- -- -- -- -- Host Read/Write R R R R R R R R Slave Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Output data (data output to host processor) 682 STR2--Status Register 2 Bit H'FE HIF 7 6 5 4 3 2 1 0 DBU DBU DBU DBU C/D DBU IBF OBF Initial value 0 0 0 0 0 0 0 0 Host Read/Write R R R R R R R R Slave Read/Write R/W R/W R/W R/W R R/W R R Output Buffer Full 0 Host has read ODR2 1 Slave has written to ODR2 Input Buffer Full 0 Slave has read IDR2 1 Host has written to IDR2 Defined By User Command/Data 0 IDR2 contains data 1 IDR2 contains a command Defined By User 683 Appendix C I/O Port Block Diagrams Note: "Reset" here means "reset + hardware standby." C.1 Port 1 Block Diagram RP1P Hardware standby WP1P Mode 1 Reset S R Q D P1nDDR C * WP1D Mode 3 Reset R Q D P1nDR C P1n Modes 1 or 2 WP1 RP1 WP1P: Write to P1PCR WP1D: Write to P1DDR WP1: Write to port 1 RP1P: Read P1PCR RP1: Read port 1 n = 0 to 7 Note: * Set priority Figure C.1 Port 1 Block Diagram 684 Internal address bus (lower) R Q D P1nPCR C Internal data bus Reset C.2 Port 2 Block Diagram RP2P Hardware standby WP2P Mode 1 Reset S R Q D P2nDDR C * WP2D Mode 3 P2n Modes 1 or 2 Internal data bus R Q D P2nPCR C Internal address bus (upper) Reset Reset R Q D P2nDR C WP2 RP2 WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 n = 0 to 7 Note: * Set priority Figure C.2 Port 2 Block Diagram 685 C.3 Port 3 Block Diagram HIE Mode 3 Reset Reset R Q D P3nPCR C RP3P WP3P CS IOR R Q D P3nDDR External address write Reset P3n R Q D P3nDR C Modes 1 or 2 WP3 CS IOW RP3 External address read WP3P: Write to P3PCR WP3D: Write to P3DDR WP3: Write to port 3 RP3P: Read P3PCR RP3: Read port 3 n = 0 to 7 Figure C.3 Port 3 Block Diagram 686 Internal data bus WP3D Host interface data bus C C.4 Port 4 Block Diagrams R Q D P4nDDR C WP4D Reset Internal data bus Reset R Q D P4nDR C P4n WP4 RP4 8-bit timer Counter clock input Counter reset input WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 0, 2 Figure C.4 (a) Port 4 Block Diagram (Pins P4 0, P42) 687 R Q D P4nDDR C WP4D Reset R Q D P4nDR C P4n Internal data bus Reset 8-bit timer WP4 Output enable 8-bit timer output PWM timer output RP4 WP4D: Write to P4DDR WP4: Write to port 4 RP4: Read port 4 n = 1, 6, 7 Figure C.4 (b) Port 4 Block Diagram (Pins P41, P46, P47) 688 Reset R Q D P4nDDR C HIF WP4D R Q D P4nDR C P4n WP4 Internal data bus Reset Reset RESOBF2, RESOBF1 (reset HIRQ11 and HIRQ12, respectively) RP4 8-bit timer WP4D: Write to P4DDR WP4: Write to port 4* RP4: Read port 4 n = 3, 5 Counter clock input Counter reset input Note: * Refer to table 14.9. Figure C.4 (c) Port 4 Block Diagram (Pins P43, P45) 689 Reset R Q D P44DDR C Reset WP4D R Q D P44DR C P44 WP4 Internal data bus HIF RESOBF1 (reset HIRQ1) 8-bit timer PWM timer Output enable 8-bit timer output RP4 WP4D: Write to P4DDR WP4: Write to port 4* RP4: Read port 4 Note: * Refer to table 14.9. Figure C.4 (d) Port 4 Block Diagram (Pin P44) 690 C.5 Port 5 Block Diagrams R Q D P50DDR C WP5D Internal data bus Reset Reset R Q D P50DR C P50 SCI WP5 Output enable Serial transmit data RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C.5 (a) Port 5 Block Diagram (Pin P5 0) 691 R Q D P51DDR C WP5D Internal data bus Reset SCI Input enable Reset R Q D P51DR C P51 WP5 RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C.5 (b) Port 5 Block Diagram (Pin P51) 692 Serial receive data R Q D P52DDR C WP5D Reset Internal data bus Reset SCI Clock input enable R Q D P52DR C P52 WP5 Clock output enable Clock output RP5 Clock input WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C.5 (c) Port 5 Block Diagram (Pin P52) 693 C.6 Port 6 Block Diagrams Reset R Q D KMnPCR C WP6P Hardware standby Reset R Q D P6nDDR C WP6D Reset Internal data bus RP6P R Q D P6nDR C P6n WP6 RP6 Free-running timer Input capture input Counter clock input WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 RP6P: Read KMPCR WP6P: Write to KMPCR n = 0, 2, 3, 4, 5 Key-sense interrupt input KMIMRn Figure C.6 (a) Port 6 Block Diagram (Pins P6 0, P62, P63, P64, P65) 694 Reset R Q D KM1PCR C WP6P Reset Hardware standby R Q D P61DDR C WP6D Internal data bus RP6P Reset R Q D P61DR C P61 Free-running timer WP6 Output enable Output compare output RP6 WP6D: WP6: RP6: RP6P: WP6P: Write to P6DDR Write to port 6 Read port 6 Read KMPCR Write to KMPCR Key-sense interrupt input KMIMR1 Figure C.6 (b) Port 6 Block Diagram (Pin P61) 695 Reset R Q D KM6PCR C WP6P Reset Hardware standby R Q D P66DDR C WP6D Internal data bus RP6P Reset R Q D P66DR C P66 Free-running timer WP6 Output enable Output compare output RP6 KMIMR6 IRQ6 input Other key-sense interrupt inputs IRQ enable register IRQ6 enable WP6D: WP6: RP6: RP6P: WP6P: Write to P6DDR Write to port 6 Read port 6 Read KMPCR Write to KMPCR Figure C.6 (c) Port 6 Block Diagram (Pin P66) 696 Reset R Q D KM7PCR C WP6P Hardware standby Reset R Q D P67DDR C WP6D Internal data bus RP6P Reset R Q D P67DR C P67 WP6 RP6 KMIMR7 Key-sense interrupt input WP6D: WP6: RP6: RP6P: WP6P: IRQ7 input Write to P6DDR Write to port 6 Read port 6 Read KMPCR Write to KMPCR IRQ enable register IRQ7 enable Figure C.6 (d) Port 6 Block Diagram (Pin P67) 697 Port 7 Block Diagrams Internal data bus C.7 RP7 P7n A/D converter Analog input RP7: Read port 7 n = 0 to 5 RP7 P7n Internal data bus Figure C.7 (a) Port 7 Block Diagram (Pins P7 0 to P75) A/D converter Analog input D/A converter Output enable Analog output RP7: Read port 7 n = 6, 7 Figure C.7 (b) Port 7 Block Diagram (Pins P76 and P77) 698 Port 8 Block Diagrams Reset HIE R Q D P80DDR C WP8D Reset R Q D P80DR C P80 Internal data bus C.8 WP8 RP8 HIF HA0 WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.8 (a) Port 8 Block Diagram (Pin P8 0) 699 R Q D P81DDR C WP8D Internal data bus Reset Reset R Q D P81DR C P81 WP8 HIF FGA20E FGA20 RP8 WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.8 (b) Port 8 Block Diagram (Pin P81) 700 Reset HIE R Q D P8nDDR C Internal data bus WP8D Reset R Q D P8nDR C P8n WP8 RP8 HIF Input (CS1, IOR) WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 n = 2, 3 Figure C.8 (c) Port 8 Block Diagram (Pins P82, P83) 701 HIE STAC Reset WP8D Reset R Q D P84DR C P84 WP8 Internal data bus R Q D P84DDR C SCI Output enable Serial transmit data HIF IOW RP8 IRQ3 input IRQ enable register WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.8 (d) Port 8 Block Diagram (Pin P84) 702 IRQ3 enable Reset HIE STAC R Q D P85DDR C SCI WP8D R Q D P85DR C P85 Internal data bus Reset Input enable WP8 RP8 Serial receive data HIF CS2 input IRQ4 input IRQ enable register IRQ4 enable WP8D: Write to P9DDR WP8: Write to port 8 RP8: Read port 8 Figure C.8 (e) Port 8 Block Diagram (Pin P85) 703 Reset R Q D P86DDR C SCI WP8D Reset R Q D P86DR C P86 Internal data bus Clock input enable WP8 Clock output enable Clock output RP8 Clock input IRQ5 input IRQ enable register IRQ5 enable WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Note: For a block diagram when the SCL pin function is selected, see section 13, I2C Bus Interface. Figure C.8 (f) Port 8 Block Diagram (Pin P86) 704 C.9 Port 9 Block Diagrams HIE STAC R Q D P90DDR C WP9D Reset Internal data bus Reset R Q D P90DR C P90 WP9 RP9 HIF ECS2 input IRQ2 input IRQ enable register IRQ2 enable WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 A/D converter External trigger input Figure C.9 (a) Port 9 Block Diagram (Pin P9 0) 705 HIE STAC R Q D P91DDR C WP9D Reset R Q D P91DR C P91 Internal data bus Reset WP9 RP9 HIF EIOW input IRQ1 input IRQ enable register WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.9 (b) Port 9 Block Diagram (Pin P91) 706 IRQ1 enable R Q D P92DDR C WP9D Reset R Q D P92DR C P92 Internal data bus Reset WP9 RP9 IRQ0 input IRQ enable register WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 IRQ0 enable Figure C.9 (c) Port 9 Block Diagram (Pin P92) 707 Modes 1 or 2 Reset R Q D P9nDDR C WP9D Mode 3 P9n Modes 1 or 2 Internal data bus Hardware standby Reset R Q D P9nDR C WP9 RP9 WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 n = 3, 4, 5 Figure C.9 (d) Port 9 Block Diagram (Pins P93, P94, P95) 708 RD output WR output AS output Modes 1 or 2 Reset S R Q D P96DDR C WP9D P96 * Internal data bus Hardware standby o RP9 WP9D: Write to P9DDR Read port 9 RP9: Note: * Set priority Figure C.9 (e) Port 9 Block Diagram (Pin P96) 709 Wait input enable Modes 1 or 2 R Q D P97DDR C WP9D Reset Internal data bus Reset R Q D P97DR C P97 WP9 RP9 WAIT input WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: For a block diagram when the SDA pin function is selected, see section 13, I2C Bus Interface. Figure C.9 (f) Port 9 Block Diagram (Pin P97) 710 C.10 Port A Block Diagram IICS R Q D PAnDDR C WPAD Reset Internal data bus Reset R Q D PAnODR C PAn WPA RPA Key-sense interrupt input KMIMRn+8 WPAD: Write to PADDR WPA: Write to port A RPA: Read port A n = 0 to 7 Note: For a block diagram when pins PA7 to PA4 are used as bus buffer input/output pins, see section 13, I2C Bus Interface. Figure C.10 Port A Block Diagram (Pins PA0 to PA 7) 711 C.11 Port B Block Diagram HIE Modes 1 or 2 CS IOR Reset R Q D PBnDDR Reset PBn R Q D PBnODR C WPB CS IOW RPB WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B n = 0 to 7 Figure C.11 Port B Block Diagram 712 Internal data bus WPBD Host interface data bus C Appendix D Port States in Each Processing State Table D.1 Port States Port Name (Multiplexed Pin Names) Mode Reset Hardware Standby Mode Software Standby Mode Sleep Mode P17 to P1 0 1 L T L A7 to A 0 2 T keep P27 to P2 0 1 L A15 to A 8 2 T T 3 1 D7 to D0 2 T T 3 P47 to P4 0 1 A7 to A 0 Address/ input port (DDR = 1) L (DDR = 0) keep 3 P37 to P3 0 keep *1 Program Execution State (Normal Operation) I/O port L keep *1 A15 to A 8 (DDR = 1) L (DDR = 0) keep Address/ input port keep I/O port T keep T D7 to D0 keep I/O port *2 keep I/O port T T keep T T keep *2 keep I/O port T T keep *2 keep I/O port T T T T Input port 2 3 P52 to P5 0 1 2 3 P67 to P6 0 1 2 3 P77 to P7 0 1 2 3 713 Port Name (Multiplexed Pin Names) Mode P86 to P8 0 1 Reset Hardware Standby Mode Software Standby Mode Sleep Mode Program Execution State (Normal Operation) T T keep *2 keep I/O port T T T/keep *2 T/keep WAIT/ I/O port keep *2 keep I/O port H Clock output Clock output (DDR = 1) H (DDR = 0) T (DDR = 1) Clock output (DDR = 0) T (DDR = 1) Clock output (DDR = 0) Input port H H AS, WR, RD keep keep I/O port 2 3 P97/WAIT 1 2 3 P96/o P95 to P9 3, 1 2 Clock output 3 T 1 H T T AS, WR, RD 2 P92 to P9 0 3 T 1 T T keep keep I/O port T T keep *2 keep I/O port T T keep *2 keep I/O port 2 3 PA7 to PA 0 1 2 3 PB7 to PB 0 1 2 3 Legend: H: High level L: Low level T: High impedance keep: Input port becomes high-impedance (when DDR = 0 and PCR = 1, MOS input pull-ups remain on), output port retains state Notes: *1 With address outputs, the last address accessed is retained. *2 As on-chip supporting modules are initialized, becomes an I/O port determined by DDR and DR. 714 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents when the RAME bit in SYSCR is set to 1, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns). STBY t1 10 tcyc t2 0 ns RES (2) When the RAME bit in SYSCR is cleared to 0 or when it is not necessary to retain RAM contents, RES does not have to be driven low as in (1). Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high. STBY t 100 ns tOSC RES 715 Appendix F Option Lists HD6433437, HD6433436, HD6433434 Option List Please check off the appropriate applications and enter the necessary information. Date of order Customer Department Name ROM code name LSI number (Hitachi entry) 1 ROM Size HD6433434: 32-kbyte HD6433436: 48-kbyte HD6433437: 60-kbyte 2 System Oscillator Crystal oscillator f= MHz External clock f= MHz 3 Power Supply Voltage/Maximum Operating Frequency VCC = 4.5 V to 5.5 V (16 MHz max.) VCC = 4.0 V to 5.5 V (12 MHz max.) VCC = 2.7 V to 5.5 V (10 MHz max.) Notes: 1. Please select the power supply voltage/operating frequency version according to the power supply voltage used. Example: For use at VCC = 4.5 V to 5.5 V/f = 10 MHz, select VCC = 4.5 V to 5.5 V (16 MHz max.). 2. The power supply voltage and maximum operating frequency of the selected version should also be entered on the Single-Chip Microcomputer Ordering Specifications Sheet. Continued on the following page. 716 ROM code name Continued from the preceding page. LSI number (Hitachi entry) 4 I2C Bus Option I2C bus used I2C bus not used Notes: 1. The "I2C bus used" option includes all cases where data transfer is performed via the SCL and SDA pins using the on-chip I2C bus interface function (hardware module). If the I 2C bus interface function (hardware module) is used, various bus interfaces with different bus specifications and names are also included in "I2C bus used". The case in which only the bus drive function of pins PA7 to PA4 in port A is used is not included. 2. When "I 2C bus not used" is selected, values cannot be set in registers relating to the I 2C bus interface (ICCR, ICSR, ICDR, ICMR). These register always read H'FF. With emulators, and ZTAT and F-ZTAT versions, the "I2C bus used" option is selected. If the "I2C bus not used" option is selected, it is essential to ensure that I 2C bus interface related registers are not accessed. For the Microcomputer Family item in 1. Basic Specifications in the Single-Chip Microcomputer Ordering Specifications Sheet*, please specify the appropriate item from the table below according to the combination of items 1 and 4 above. If the "I 2C bus used" option is selected, please also specify this in Special Specifications (Product Specifications, Mark Specifications, etc.) in 1. Basic Specifications. * Please contact the relevant sales department for information on the Single-Chip Microcomputer Ordering Specifications Sheet. I 2C I 2C bus used I 2C bus not used 32-kbyte HD6433434W HD6433434 48-kbyte HD6433436W HD6433436 60-kbyte HD6433437W HD6433437 ROM Size 717 Appendix G Product Code Lineup Table G.1 H8/3437 Series Product Code Lineup Product Type H8/3437 Flash memory version Product Code Dual-powerHD64F3437F16 supply F-ZTAT HD64F3437FLH16 version HD64F3437TF16 Mark Code Package (Hitachi Package Code) HD64F3437F16 100-pin QFP (FP-100B) HD64F3437F16 HD64F3437TF16 100-pin TQFP (TFP-100B) HD64F3437TFLH16 HD64F3437TF16 Single-power- HD64F3437SF16 supply F-ZTAT HD64F3437STF16 version PROM version ZTAT version Mask ROM version With I2C interface 2 Without I C interface H8/3436 Mask ROM version 2 With I C interface 2 H8/3434 Flash memory version HD64F3437F16 100-pin QFP (FP-100B) HD64F3437TF16 100-pin TQFP (TFP-100B) HD6473437F16 HD6473437F16 100-pin QFP (FP-100B) HD6473437TF16 HD6473437TF16 100-pin TQFP (TFP-100B) HD6433437WF HD6433437W(***)F 100-pin QFP (FP-100B) HD6433437WTF HD6433437W(***)TF 100-pin TQFP (TFP-100B) HD6433437F HD6433437(***)F 100-pin QFP (FP-100B) HD6433437TF HD6433437(***)TF 100-pin TQFP (TFP-100B) HD6433436WF HD6433436W(***)F 100-pin QFP (FP-100B) HD6433436WTF HD6433436W(***)TF 100-pin TQFP (TFP-100B) Without I C interface HD6433436F HD6433436(***)F 100-pin QFP (FP-100B) HD6433436TF HD6433436(***)TF 100-pin TQFP (TFP-100B) F-ZTAT version HD64F3434F16 HD64F3434F16 100-pin QFP (FP-100B) HD64F3434FLH16 HD64F3434F16 HD64F3434TF16 HD64F3434TF16 100-pin TQFP (TFP-100B) HD64F3434TFLH16 HD64F3434TF16 PROM version Mask ROM version ZTAT version HD6473434F16 HD6473434F16 100-pin QFP (FP-100B) HD6473434TF16 HD6473434TF16 100-pin TQFP (TFP-100B) With I C interface HD6433434WF HD6433434W(***)F 100-pin QFP (FP-100B) HD6433434WTF HD6433434W(***)TF 100-pin TQFP (TFP-100B) Without I 2C interface HD6433434F HD6433434(***)F 100-pin QFP (FP-100B) HD6433434TF HD6433434(***)TF 100-pin TQFP (TFP-100B) 2 Note: (***) in mask ROM versions is the ROM code. 718 The I2C interface is an option. Please note the following points when using this optional function. 1. Notify your Hitachi sales representative that you will be using an optional function. 2. With mask ROM versions, optional functions can be used if the product code includes the letter W (e.g. HD6433437WF, HD6433434WTF). 3. The product code is the same for ZTAT versions, but please be sure to notify Hitachi if you are going to use this optional function. 719 Appendix H Package Dimensions Figure H.1 shows the dimensions of the FP-100B package. Figure H.2 shows the dimensions of the TFP-100B package. Unit: mm 16.0 0.3 14 75 51 50 100 26 0.10 *Dimension including the plating thickness Base material dimension *0.17 0.05 0.15 0.04 0.08 M 1.0 2.70 25 0.12 +0.13 -0.12 1 *0.22 0.05 0.20 0.04 3.05 Max 0.5 16.0 0.3 76 1.0 0 - 8 0.5 0.2 Hitachi Code JEDEC JEITA Mass (reference value) Figure H.1 Package Dimensions (FP-100B) 720 FP-100B -- Conforms 1.2 g Unit: mm 16.0 0.2 14 75 51 50 100 26 1.0 0.10 *Dimension including the plating thickness Base material dimension 1.00 0.08 M *0.17 0.05 0.15 0.04 25 0.10 0.10 1 *0.22 0.05 0.20 0.04 1.20 Max 0.5 16.0 0.2 76 1.0 0 - 8 0.5 0.1 Hitachi Code JEDEC JEITA Mass (reference value) TFP-100B -- Conforms 0.5 g Figure H.2 Package Dimensions (TFP-100B) 721 722 H8/3437 Series Hardware Manual Publication Date: 1st Edition, September 1994 7th Edition, March 2002 Published by: Business Planning Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Copyright (c) Hitachi, Ltd., 1994. All rights reserved. Printed in Japan.