MFRC631 High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Rev. 4.5 -- 12 September 2018 227445 1 Product data sheet COMPANY PUBLIC General description MFRC631, the cost efficient NFC frontend for payment. The MFRC631 multi-protocol NFC frontend IC supports the following operating modes: * Read/write mode supporting ISO/IEC 14443 type A and MIFARE Classic communication mode * Read/write mode supporting ISO/IEC 14443B The MFRC631's internal transmitter is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443A and MIFARE Classic IC-based cards and transponders without additional active circuitry. The digital module manages the complete ISO/IEC 14443A framing and error detection functionality (parity and CRC). The MFRC631 supports MIFARE Classic with 1 kB memory, MIFARE Classic with 4 kB memory, MIFARE Ultralight, MIFARE Ultralight C, MIFARE Plus and MIFARE DESFire products. The MFRC631 supports higher transfer speeds of the MIFARE product family up to 848 kbit/s in both directions. The MFRC631 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer communication scheme except anticollision. The anticollision needs to be implemented in the firmware of the host controller as well as in the upper layers. The following host interfaces are supported: * Serial Peripheral Interface (SPI) * Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply) 2 * I C-bus interface (two versions are implemented: I2C and I2CL) The MFRC631 supports the connection of a secure access module (SAM). A dedicated 2 separate I C interface is implemented for a connection of the SAM. The SAM can be used for high secure key storage and acts as a very performant crypto coprocessor. A dedicated SAM is available for connection to the MFRC631. In this document the term MIFARE Classic card" refers to a MIFARE Classic IC-based contactless card. MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 2 Features and benefits * Includes NXP ISO/IEC14443-A and Innovatron ISO/IEC14443-B intellectual property licensing rights * High-performance multi-protocol NFC frontend for transfer speed up to 848 kbit/s * Supports ISO/IEC 14443 type A, MIFARE Classic and ISO/IEC 14443 B modes * Supports MIFARE Classic product encryption by hardware in read/write mode Allows reading cards based on MIFARE Ultralight, MIFARE Classic with 1 kB memory, MIFARE Classic with 4 kB memory, MIFARE DESFire EV1, MIFARE DESFire EV2 and MIFARE Plus ICs. * Low-power card detection * Compliance to "EMV contactless protocol specification V2.3.1" on RF level can be achieved * Antenna connection with minimum number of external components * Supported host interfaces: - SPI up to 10 Mbit/s 2 - I C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus - RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin voltage supply 2 * Separate I C-bus interface for connection of a secure access module (SAM) * FIFO buffer with size of 512 byte for highest transaction performance * Flexible and efficient power saving modes including hard power down, standby and low-power card detection * Cost saving by integrated PLL to derive system clock from 27.12 MHz RF quartz crystal * 3 V to 5.5 V power supply (MFRC63102) 2.5 V to 5.5 V power supply (MFRC63103) * Up to 8 free programmable input/output pins * Typical operating distance in read/write mode for communication to a ISO/IEC 14443 type A and MIFARE Classic card up to 12 cm, depending on the antenna size and tuning The version CLRC63103 offers a more flexible configuration for Low-Power Card detection compared to the CLRC63102 with the new register LPCD_OPTIONS. In addition, the CLRC63103 offers new additional settings for the Load Protocol which fit very well to smaller antennas. The CLRC63103 is therefore the recommended version for new designs. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 2 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 3 Quick reference data Table 1. Quick reference data MFRC63102HN Symbol Parameter VDD supply voltage VDD(PVDD) PVDD supply voltage VDD(TVDD) TVDD supply voltage Conditions [1] Typ Max Unit 3.0 5.0 5.5 V 3.0 5.0 VDD V 3.0 5.0 5.5 V - 8 40 nA Ipd power-down current IDD supply current - 17 20 mA IDD(TVDD) TVDD supply current - 100 250 mA Tamb operating ambient temperature -25 +25 +85 C Tstg storage temperature -55 +25 +125 C Min Typ Max Unit 2.5 5.0 5.5 V 2.5 5.0 VDD V 2.5 5.0 5.5 V - 8 40 nA [1] [2] PDOWN pin pulled HIGH [2] Min no supply voltage applied VDD(PVDD) must always be the same or lower voltage than VDD. Ipd is the sum of all supply currents Table 2. Quick reference data MFRC63103HN Symbol Parameter VDD supply voltage VDD(PVDD) PVDD supply voltage VDD(TVDD) TVDD supply voltage Conditions [1] PDOWN pin pulled HIGH [2] Ipd power-down current IDD supply current - 17 20 mA IDD(TVDD) TVDD supply current - 180 350 mA - - 500 mA absolute limiting value Tamb operating ambient temperature device mounted on PCB which allows sufficient heat dissipation -40 +25 +105 C Tstg storage temperature -55 +25 +125 C [1] [2] no supply voltage applied VDD(PVDD) must always be the same or lower voltage than VDD. Ipd is the sum of all supply currents MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 3 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 4 Ordering information Table 3. Ordering information Type number Package [1] MFRC63102HN/TRAYBM [2] MFRC63102HN/T/R [3] MFRC63103HN/TRAYB [2] MFRC63103HN/T/R [1] [2] [3] Name Description Version HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; MSL1, 32 terminals + 1 central ground; body 5 x 5 x 0.85 mm SOT617-1 plastic thermal enhanced very thin quad flat package; no leads; MSL2, 32 terminals + 1 central ground; body 5 x 5 x 0.85 mm, wettable flanks SOT617-1 Delivered in five trays; MOQ: 5x 490 pcs Delivered on reel with 6000 pieces; MOQ: 6000 pcs Delivered in one tray, MOQ (Minimum order quantity) : 490 pcs MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 4 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 5 Block diagram The analog interface handles the modulation and demodulation of the antenna signals for the contactless interface. The contactless UART manages the protocol dependency of the contactless interface settings managed by the host. The FIFO buffer ensures fast and convenient data transfer between host and the contactless UART. The register bank contains the settings for the analog and digital functionality. REGISTER BANK ANTENNA ANALOG INTERFACE CONTACTLESS UART FIFO BUFFER SERIAL UART SPI I2C-BUS HOST 001aaj627 Figure 1. Simplified block diagram of the MFRC631 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 5 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 25 PVDD 26 IFSEL0/OUT4 27 IFSEL1/OUT5 28 IF0 29 IF1 30 IF2 terminal 1 index area 31 IF3 32 IRQ Pinning information TDO/OUT0 1 TDI/OUT1 2 24 SDA TMS/OUT2 3 TCK/OUT3 4 SIGIN/OUT7 5 SIGOUT 6 19 XTAL1 DVDD 7 18 TVDD VDD 8 17 TX1 (1) 23 SCL 22 CLKOUT/OUT6 21 PDOWN TVSS 16 20 XTAL2 TX2 15 VMID 14 RXN 13 RXP 12 AUX2 11 AVDD 9 heatsink AUX1 10 6 001aam004 Transparent top view 1. Pin 33 VSS - heatsink connection Figure 2. Pinning configuration HVQFN32 (SOT617-1) 6.1 Pin description Table 4. Pin description Pin Symbol Type Description 1 TDO / OUT0 O test data output for boundary scan interface / general purpose output 0 2 TDI / OUT1 I test data input boundary scan interface / general purpose output 1 3 TMS / OUT2 I test mode select boundary scan interface / general purpose output 2 4 TCK / OUT3 I test clock boundary scan interface / general purpose output 3 5 SIGIN /OUT7 I/O Contactless communication interface output. / general purpose output 7 6 SIGOUT O Contactless communication interface input. 7 DVDD PWR digital power supply buffer 8 VDD PWR power supply 9 AVDD PWR analog power supply buffer 10 AUX1 O auxiliary outputs: Pin is used for analog test signal 11 AUX2 O auxiliary outputs: Pin is used for analog test signal 12 RXP I receiver input pin for the received RF signal. 13 RXN I receiver input pin for the received RF signal. 14 VMID PWR internal receiver reference voltage 15 TX2 O transmitter 2: delivers the modulated 13.56 MHz carrier 16 TVSS PWR transmitter ground, supplies the output stage of TX1, TX2 17 TX1 O transmitter 1: delivers the modulated 13.56 MHz carrier MFRC631 Product data sheet COMPANY PUBLIC [1] [1] [1] All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 6 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Pin Symbol Type Description 18 TVDD PWR transmitter voltage supply 19 XTAL1 I crystal oscillator input: Input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (fosc = 27.12 MHz) 20 XTAL2 O crystal oscillator output: output of the inverting amplifier of the oscillator 21 PDOWN I Power Down (RESET) 22 CLKOUT / OUT6 O clock output / general purpose output 6 23 SCL O Serial Clock line 24 SDA I/O Serial Data Line 25 PVDD PWR pad power supply 26 IFSEL0 / OUT4 I host interface selection 0 / general purpose output 4 27 IFSEL1 / OUT5 I host interface selection 1 / general purpose output 5 28 IF0 I/O interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, 2 2 I C, I C-L 29 IF1 I/O interface pin, multifunction pin: Can be assigned to host interface SPI, I C, I C-L 30 IF2 I/O interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, 2 2 I C, I C-L 31 IF3 I/O interface pin, multifunction pin: Can be assigned to host interface RS232, SPI, 2 2 I C, I C-L 32 IRQ O interrupt request: output to signal an interrupt event 33 VSS PWR ground and heat sink connection [1] 2 2 This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 7 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7 Functional description SAM interface I2C, LOGICAL SDA SCL FIFO 512 Bytes EEPROM 8 kByte SPI host interfaces RESET LOGIC IFSEL1 IFSEL0 PDOWN I2 C IF0 REGISTERS IF1 UART IF2 STATEMACHINES IF3 SPI TCK TDI TMS TDO ANALOGUE FRONT-END BOUNDARY SCAN VOLTAGE REGULATOR 3/5 V => 1.8 V DVDD VOLTAGE REGULATOR 3/5 V => 1.8 V AVDD POR RNG VDD VSS PVDD TVDD TVSS AVDD DVDD TIMER0..3 INTERRUPT CONTROLLER IRQ TIMER4 (WAKE-UP TIMER) TX CODEC CRC SIGIN/ SIGOUT CONTROL SIGIN RX DECOD CLCOPRO SIGPRO SIGOUT ADC LFO PLL RX TX OSC RXP VMID RXN TX2 TX1 CLKOUT AUX1 XTAL2 XTAL1 AUX2 001aam005 Figure 3. Detailed block diagram of the MFRC631 7.1 Interrupt controller The interrupt controller handles the enabling/disabling of interrupt requests. All of the interrupts can be configured by firmware. Additionally, the firmware has possibilities to trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0 and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt controller registers is implemented. The MFRC631 indicates certain events by setting bit IRQ in the register Status1Reg and additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. Table 4. shows the available interrupt bits, the corresponding source and the condition for its activation. The interrupt bits Timer0IRQ, Timer1IRQ, Timer2IRQ, Timer3OIRQ, in register IRQ1 indicate an interrupt set by the timer unit. The setting is done if the timer underflows. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 8 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus The TxIRQ bit in register IRQ0 indicates that the transmission is finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit sets the interrupt bit automatically. The bit RxIRQ in register IRQ0 indicates an interrupt when the end of the received data is detected. The bit IdleIRQ in register IRQ0 is set if a command finishes and the content of the command register changes to idle. The register WaterLevel defines both - minimum and maximum warning levels - counting from top and from bottom of the FIFO by a single value. The bit HiAlertIRQ in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that means the FIFO data number has reached the top level as configured by the register WaterLevel and bit WaterLevelExtBit. The bit LoAlertIRQ in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that means the FIFO data number has reached the bottom level as configured by the register WaterLevel. The bit ErrIRQ in register IRQ0 indicates an error detected by the contactless UART during receive. This is indicated by any bit set to logic 1 in register Error. The bit LPCDIRQ in register IRQ0 indicates a card detected. The bit RxSOFIRQ in register IRQ0 indicates a detection of a SOF or a subcarrier by the contactless UART during receiving. The bit GlobalIRQ in register IRQ1 indicates an interrupt occurring at any other interrupt source when enabled. Table 5. Interrupt sources MFRC631 Product data sheet COMPANY PUBLIC Interrupt bit Interrupt source Is set automatically, when Timer0IRQ Timer Unit the timer register T0 CounterVal underflows Timer1IRQ Timer Unit the timer register T1 CounterVal underflows Timer2IRQ Timer Unit the timer register T2 CounterVal underflows Timer3IRQ Timer Unit the timer register T3 CounterVal underflows TxIRQ Transmitter a transmitted data stream ends RxIRQ Receiver a received data stream ends IdleIRQ Command Register a command execution finishes HiAlertIRQ FIFO-buffer pointer the FIFO data number has reached the top level as configured by the register WaterLevel LoAlertIRQ FIFO-buffer pointer the FIFO data number has reached the bottom level as configured by the register WaterLevel ErrIRQ contactless UART a communication error had been detected LPCDIRQ LPCD a card was detected when in low-power card detection mode RxSOFIRQ Receiver detection of a SOF or a subcarrier GlobalIRQ all interrupt sources will be set if another interrupt request source is set All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 9 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.2 Timer module Timer module overview The MFRC631 implements five timers. Four timers -Timer0 to Timer3 - have an input clock that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived from the 27.12 MHz quartz) or to be the underflow event of the fifth Timer (Timer4). Each timer implements a counter register which is 16 bit wide. A reload value for the counter is defined in a range of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo. The fifth timer Timer4 is intended to be used as a wakeup timer and is connected to the internal LFO (Low Frequency Oscillator) as input clock source. The TControl register allows the global start and stop of each of the four timers Timer0 to Timer3. Additionally, this register indicates if one of the timers is running or stopped. Each of the five timers implements an individual configuration register set defining timer reload value (e.g. T0ReloadHi,T0ReloadLo), the timer value (e.g. T0CounterValHi, T0CounterValLo) and the conditions which define start, stop and clockfrequency (e.g. T0Control). The external host may use these timers to manage timing relevant tasks. The timer unit may be used in one of the following configurations: * * * * * Time-out counter Watch-dog counter Stop watch Programmable one-shot timer Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific event has occurred after an elapsed time. The timer register content is modified by the timer unit, which can be used to generate an interrupt to allow an host to react on this event. The counter value of the timer is available in the registers T(x)CounterValHi, T(x)CounterValLo. The content of these registers is decremented at each timer clock. If the counter value has reached a value of 0000h and the interrupts are enabled for this specific timer, an interrupt will be generated as soon as the next clock is received. If enabled, the timer event can be indicated on the pin IRQ (interrupt request). The bit Timer(x)IRQ can be set and reset by the host controller. Depending on the configuration, the timer will stop counting at 0000h or restart with the value loaded from registers T(x)ReloadHi, T(x)ReloadLo. The counting of the timer is indicated by bit TControl.T(x)Running. The timer can be started by setting bits TControl.T(x)Running and TControl.T(x)StartStopNow or stopped by setting the bits TControl.T(x)StartStopNow and clearing TControl.T(x)Running. Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start, this can be useful if dedicated protocol requirements need to be fulfilled. 7.2.1 Timer modes MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 10 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.2.1.1 Time-Out- and Watch-Dog-Counter Having configured the timer by setting register T(x)ReloadValue and starting the counting of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit decrements the T(x)CounterValue Register beginning with the configured start event. If the configured stop event occurs before the Timer(x) underflows (e.g. a bit is received from the card), the timer unit stops (no interrupt is generated). If no stop event occurs, the timer unit continues to decrement the counter registers until the content is zero and generates a timer interrupt request at the next clock cycle. This allows to indicate to a host that the event did not occur during the configured time interval. 7.2.1.2 Wake-up timer The wake-up Timer4 allows to wakeup the system from standby after a predefined time. The system can be configured in such a way that it is entering the standby mode again in case no card had been detected. This functionality can be used to implement a low-power card detection (LPCD). For the low-power card detection it is recommended to set T4Control.T4AutoWakeUp and T4Control.T4AutoRestart, to activate the Timer4 and automatically set the system in standby. The internal low frequency oscillator (LFO) is then used as input clock for this Timer4. If a card is detected the host-communication can be started. If bit T4Control.T4AutoWakeUp is not set, the MFRC631 will not enter the standby mode again in case no card is detected but stays fully powered. 7.2.1.3 Stop watch The elapsed time between a configured start- and stop event may be measured by the MFRC631 timer unit. By setting the registers T(x)ReloadValueHi, T(x)reloadValueLo the timer starts to decrement as soon as activated. If the configured stop event occurs, the timers stops decrementing. The elapsed time between start and stop event can then be calculated by the host dependent on the timer interval TTimer: (1) If an underflow occurred which can be identified by evaluating the corresponding IRQ bit, the performed time measurement according to the formula above is not correct. 7.2.1.4 Programmable one-shot timer The host configures the interrupt and the timer, starts the timer and waits for the interrupt event on pin IRQ. After the configured time the interrupt request will be raised. 7.2.1.5 Periodical trigger If the bit T(x)Control.T(x)AutoRestart is set and the interrupt is activated, an interrupt request will be indicated periodically after every elapsed timer period. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 11 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.3 Contactless interface unit The contactless interface unit of the MFRC631 supports the following read/write operating modes: * ISO/IEC14443 type A and MIFARE Classic * ISO/IEC14443B BATTERY/POWER SUPPLY READER IC ISO/IEC 14443 A CARD MICROCONTROLLER reader/writer 001aal996 Figure 4. Read/write mode A typical system using the MFRC631 is using a microcontroller to implement the higher levels of the contactless communication protocol and a power supply (battery or external supply). 7.3.1 Communication mode for ISO/IEC14443 type A and for MIFARE Classic The physical level of the communication is shown in Figure 5. (1) ISO/IEC 14443 A READER (2) ISO/IEC 14443 A CARD 001aam268 1. Reader to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s 2. Card to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106 kbit/s to 848 kbit/s Figure 5. Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic The physical parameters are described in Table 5. Table 6. Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic Communication direction Signal type Reader to card (send data from the MFRC631 to a card) fc = 13.56 MHz Card to reader (MFRC631 receives data from a card) MFRC631 Product data sheet COMPANY PUBLIC Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s reader side modulation 100 % ASK 100% ASK 100% ASK 100% ASK bit encoding modified Miller encoding modified Miller encoding modified Miller encoding modified Miller encoding bit rate [kbit/s] fc / 128 fc / 64 fc / 32 fc / 16 card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency fc / 16 fc / 16 fc / 16 fc / 16 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 12 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Communication direction Signal type Transfer speed bit encoding 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s Manchester encoding BPSK BPSK BPSK The MFRC631 connection to a host is required to manage the complete ISO/IEC 14443 type A and MIFARE Classic communication protocol. Figure 6 shows the data coding and framing according to ISO/IEC 14443 type A and MIFARE Classic. ISO/IEC 14443 A framing at 106 kBd start 8-bit data 8-bit data odd parity start bit is 1 8-bit data odd parity odd parity ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd start 8-bit data start bit is 0 even parity 8-bit data odd parity 8-bit data odd parity burst of 32 subcarrier clocks even parity at the end of the frame 001aak585 Figure 6. Data coding and framing according to ISO/IEC 14443 A The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally according to the transfer speed. 7.3.2 ISO/IEC14443B functionality The physical level of the communication is shown in Figure 7. (1) ISO/IEC 14443 B READER (2) ISO/IEC 14443 B CARD 001aal997 1. Reader to Card NRZ, Miller coded, transfer speed 106 kbit/s to 848 kbit/s 2. Card to reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106 kbit/s to 848 kbit/s Figure 7. Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic The physical parameters are described in Table 6. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 13 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 7. Communication overview for ISO/IEC 14443 B reader/writer Communication direction Signal type Reader to card (send data from the MFRC631 to a card) fc = 13.56 MHz Card to reader (MFRC631 receives data from a card) Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s reader side modulation 10 % ASK 10 % ASK 10 % ASK 10 % ASK bit encoding NRZ NRZ NRZ NRZ bit rate [kbit/s] 128 / fc 64 / fc 32 / fc 16 / fc card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency fc / 16 fc / 16 fc / 16 fc / 16 bit encoding BPSK BPSK BPSK BPSK The MFRC631 connected to a host is required to manage the complete ISO/IEC 14443 B protocol. The following Figure 8 "SOF and EOF according to ISO/IEC 14443 B" shows the ISO/IEC 14443B SOF and EOF. Start of Frame (SOF) sequence 9.44 s UNMODULATED (SUB) CARRIER ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''1'' ''1'' DATA End of Frame (EOF) sequence 9.44 s LAST CHARACTER ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' UNMODULATED (SUB) CARRIER 001aam270 Figure 8. SOF and EOF according to ISO/IEC 14443 B 7.4 Host interfaces 7.4.1 Host interface configuration 2 2 The MFRC631 supports direct interfacing of various hosts as the SPI, I C, I CL and serial UART interface type. The MFRC631 resets its interface and checks the current host interface type automatically having performed a power-up or resuming from power down. The MFRC631 identifies the host interface by the means of the logic levels on the control pins after the Cold Reset Phase. This is done by a combination of fixed pin connections.The following table shows the possible configurations defined by IFSEL1,IFSEL0: MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 14 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 8. Connection scheme for detecting the different interface types 2 2 Pin Pin Symbol UART SPI I C I C-L 28 IF0 RX MOSI ADR1 ADR1 29 IF1 n.c. SCK SCL SCL 30 IF2 TX MISO ADR2 SDA 31 IF3 PAD_VDD NSS SDA ADR2 26 IFSEL0 VSS VSS PAD_VDD PAD_VDD 27 IFSEL1 VSS PAD_VDD VSS PAD_VDD 7.4.2 SPI interface 7.4.2.1 General READER IC SCK MOSI MISO NSS IF1 IF0 IF2 IF3 001aal998 Figure 9. Connection to host with SPI The MFRC631 acts as a slave during the SPI communication. The SPI clock SCK has to be generated by the master. Data communication from the master to the slave uses the Line MOSI. Line MISO is used to send data back from the MFRC631 to the master. A serial peripheral interface (SPI compatible) is supported to enable high speed communication to a host. The implemented SPI compatible interface is according to a standard SPI interface. The SPI compatible interface can handle data speed of up to 10 Mbit/s. In the communication with a host MFRC631 acts as a slave receiving data from the external host for register settings and to send and receive data relevant for the communication on the RF interface. NSS (Not Slave Select) enables or disables the SPI interface. When NSS is logical high, the interface is disabled and reset. Between every SPI command the NSS must go to logical high to be able to start the next command read or write. On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling edge. The same is valid for the MISO line. Data is provided by the MFRC631 on the falling edge and is stable on the rising edge.The polarity of the clock is low at SPI idle. 7.4.2.2 Read data To read out data from the MFRC631 by using the SPI compatible interface the following byte order has to be used. The first byte that is sent defines the mode (LSB bit) and the address. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 15 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 9. Byte Order for MOSI and MISO byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1 MOSI address 0 address 1 address 2 ........ address n 00h MISO X data 0 data 1 ........ data n - 1 data n Remark: The Most Significant Bit (MSB) has to be sent first. 7.4.2.3 Write data To write data to the MFRC631 using the SPI interface the following byte order has to be used. It is possible to write more than one byte by sending a single address byte (see.8.5.2.4). The first send byte defines both, the mode itself and the address byte. Table 10. Byte Order for MOSI and MISO byte 0 byte 1 byte 2 3 to n-1 byte n byte n + 1 MOSI address 0 data 0 data 1 ........ data n - 1 data n MISO X X X ........ X X Remark: The Most Significant Bit (MSB) has to be sent first. 7.4.2.4 Address byte The address byte has to fulfil the following format: The LSB bit of the first byte defines the used mode. To read data from the MFRC631 the LSB bit is set to logic 1. To write data to the MFRC631 the LSB bit has to be cleared. The bits 6 to 0 define the address byte. NOTE: When writing the sequence [address byte][data0][data1][data2]..., [data0] is written to address [address byte], [data1] is written to address [address byte + 1] and [data2] is written to [address byte + 2]. Exception: This auto increment of the address byte is not performed if data is written to the FIFO address Table 11. Address byte 0 register; address MOSI 7 6 5 4 3 2 1 0 address 6 address 5 address 4 address 3 address 2 address 1 address 0 1 (read) 0 (write) MSB LSB 7.4.2.5 Timing Specification SPI The timing condition for SPI interface is as follows: Table 12. Timing conditions SPI MFRC631 Product data sheet COMPANY PUBLIC Symbol Parameter Min Typ Max Unit tSCKL SCK LOW time 50 - - ns tSCKH SCK HIGH time 50 - - ns All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 16 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Symbol Parameter Min Typ Max Unit th(SCKH-D) SCK HIGH to data input hold time 25 - - ns tsu(D-SCKH) data input to SCK HIGH set-up time 25 - - ns th(SCKL-Q) SCK LOW to data output hold time - - 25 ns t(SCKL-NSSH) SCK LOW to NSS HIGH time 0 - - ns tNSSH NSS HIGH time 50 - - ns tNSSH tSCKL tSCKH tSCKL SCK tsu(D-SCKH) th(SCKL-Q) th(SCKH-D) MOSI MSB LSB MISO MSB LSB t(SCKL-NSSH) NSS aaa-016093 Figure 10. Connection to host with SPI Remark: To send more bytes in one data stream the NSS signal must be LOW during the send process. To send more than one data stream the NSS signal must be HIGH between each data stream. 7.4.3 RS232 interface 7.4.3.1 Selection of the transfer speeds The internal UART interface is compatible to a RS232 serial interface. The levels supplied to the pins are between VSS and PVDD. To achieve full compatibility of the voltage levels to the RS232 specification, a RS232 level shifter is required. Table 13 "Selectable transfer speeds" describes examples for different transfer speeds and relevant register settings. The resulting transfer speed error is less than 1.5 % for all described transfer speeds. The default transfer speed is 115.2 kbit/s. To change the transfer speed, the host controller has to write a value for the new transfer speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set the transfer speed in the SerialSpeedReg. Table 12 "Settings of BR_T0 and BR_T1" describes the settings of BR_T0 and BR_T1. Table 13. Settings of BR_T0 and BR_T1 BR_T0 MFRC631 Product data sheet COMPANY PUBLIC 0 1 2 3 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 4 5 6 7 (c) NXP B.V. 2018. All rights reserved. 17 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus factor BR_T0 1 1 2 4 8 16 32 64 range BR_T1 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 Table 14. Selectable transfer speeds Transfer speed (kbit/s) Serial SpeedReg Transfer speed accuracy (%) (Hex.) 7.2 FA -0.25 9.6 EB 0.32 14.4 DA -0.25 19.2 CB 0.32 38.4 AB 0.32 57.6 9A -0.25 115.2 7A -0.25 128 74 -0.06 230.4 5A -0.25 460.8 3A -0.25 921.6 1C 1.45 1228.8 15 0.32 The selectable transfer speeds as shown are calculated according to the following formulas: if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1) (BR_T0 - 1) if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2 Remark: Transfer speeds above 1228.8 kBits/s are not supported. 7.4.3.2 Framing Table 15. UART framing Bit Length Value Start bit (Sa) 1 bit 0 Data bits 8 bit Data Stop bit (So) 1 bit 1 Remark: For data and address bytes the LSB bit has to be sent first. No parity bit is used during transmission. Read data: To read out data using the UART interface the flow described below has to be used. The first send byte defines both the mode itself and the address.The Trigger on pin IF3 has to be set, otherwise no read of data is possible. Table 16. Byte Order to Read Data MFRC631 Product data sheet COMPANY PUBLIC Mode byte 0 byte 1 RX address - All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 18 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Mode byte 0 byte 1 TX - data 0 ADDRESS RX Sa A0 A1 A2 A3 A4 A5 A6 RD/ NWR So DATA TX Sa D0 D1 D2 D3 D4 D5 D6 D7 So 001aam298 Figure 11. Example for UART Read Write data: To write data to the MFRC631 using the UART interface the following sequence has to be used. The first send byte defines both, the mode itself and the address. Table 17. Byte Order to Write Data Mode byte 0 byte 1 RX address 0 data 0 TX address 0 ADDRESS RX Sa A0 A1 A2 A3 A4 DATA A5 A6 RD/ NWR So Sa D0 RD/ NWR So D1 D2 D3 D4 D5 D6 D7 So ADDRESS TX Sa A0 A1 A2 A3 A4 A5 A6 001aam299 Figure 12. Example diagram for a UART write Remark: Data can be sent before address is received. 2 7.4.4 I C-bus interface MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 19 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.4.4.1 General 2 An Inter IC (I C) bus interface is supported to enable a low cost, low pin count serial bus 2 interface to the host. The implemented I C interface is mainly implemented according the 2 NXP Semiconductors I C interface specification, rev. 3.0, June 2007. The MFRC631 can act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode plus. 2 The following features defined by the NXP Semiconductors I C interface specification, rev. 3.0, June 2007 are not supported: * The MFRC631 I2C interface does not stretch the clock * The MFRC631 I2C interface does not support the general call. This means that the MFRC631 does not support a software reset * The MFRC631 does not support the I2C device ID * The implemented interface can only act in slave mode. Therefore no clock generation and access arbitration is implemented in the MFRC631. * High speed mode is not supported by the MFRC631 PULL-UP NETWORK PULL-UP NETWORK MICROCONTROLLER READER IC SDA SCL 001aam000 2 Figure 13. I C-bus interface The voltage level on the I2C pins is not allowed to be higher than PVDD. SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor. 2 Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the I Cbus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in the fast mode+. 2 2 If the I C interface is selected, a spike suppression according to the I C interface specification on SCL and SDA is automatically activated. For timing requirements refer to Table 197 "I2C-bus timing in fast mode and fast mode plus" 2 7.4.4.2 I C Data validity Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state or LOW state of the data line shall only change when the clock signal on SCL is LOW. SDA SCL data line stable; data valid change of data allowed 001aam300 2 Figure 14. Bit transfer on the I C-bus. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 20 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 2 7.4.4.3 I C START and STOP conditions 2 To handle the data transfer on the I C-bus, unique START (S) and STOP (P) conditions are defined. A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is HIGH. A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is HIGH. The master always generates the START and STOP conditions. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In this respect, the START (S) and repeated START (Sr) conditions are functionally identical. Therefore, the S symbol will be used as a generic term to represent both the START and repeated START (Sr) conditions. SDA SDA SCL SCL S P START condition STOP condition 001aam301 Figure 15. START and STOP conditions 2 7.4.4.4 I C byte format Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB first, see Figure 15 "START and STOP conditions". The number of transmitted bytes during one data transfer is unrestricted but shall fulfil the read/write cycle format. 2 7.4.4.5 I C Acknowledge An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. The master can then generate either a STOP (P) condition to stop the transfer, or a repeated START (Sr) condition to start a new transfer. A master-receiver shall indicate the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slavetransmitter shall release the data line to allow the master to generate a STOP (P) or repeated START (Sr) condition. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 21 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVERER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition 001aam302 2 Figure 16. Acknowledge on the I C- bus P MSB acknowledgement signal from slave acknowledgement signal from receiver Sr byte complete, interrupt within slave clock line held low while interrupts are serviced S or Sr 1 2 7 8 9 1 2 3-8 ACK 9 ACK Sr or P 001aam303 2 Figure 17. Data transfer on the I C- bus 2 7.4.4.6 I C 7-bit addressing 2 During the I C-bus addressing procedure, the first byte after the START condition is used to determine which slave will be selected by the master. 2 Alternatively the I C address can be configured in the EEPROM. Several address numbers are reserved for this purpose. During device configuration, the designer has to ensure, that no collision with these reserved addresses in the system is possible. Check 2 the corresponding I C specification for a complete list of reserved addresses. For all MFRC631 devices the upper 5 bits of the device bus address are reserved by NXP and set to 01010(bin). The remaining 2 bits (ADR_2, ADR_1) of the slave address 2 can be freely configured by the customer in order to prevent collisions with other I C 2 devices by using the interface pins (refer to Table 7) or the value of the I C address EEPROM register (refer to Table 29). MSB Bit 6 LSB Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 slave address Bit 0 R/W 001aam304 Figure 18. First byte following the START procedure MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 22 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 2 7.4.4.7 I C-register write access 2 To write data from the host controller via I C to a specific register of the MFRC631 the following frame format shall be used. The read/write bit shall be set to logic 0. 2 The first byte of a frame indicates the device address according to the I C rules. The second byte indicates the register address followed by up to n-data bytes. In case the address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register address. This enables for example a fast FIFO access. 2 7.4.4.8 I C-register read access To read out data from a specific register address of the MFRC631 the host controller shall use the procedure: First a write access to the specific register address has to be performed as indicated in the following frame: 2 The first byte of a frame indicates the device address according to the I C rules. The second byte indicates the register address. No data bytes are added. The read/write bit shall be logic 0. Having performed this write access, the read access starts. The host sends the device address of the MFRC631. As an answer to this device address the MFRC631 responds with the content of the addressed register. In one frame n-data bytes could be read using the same register address. The address pointing to the register is incremented automatically (exception: FIFO register address is not incremented automatically). This enables a fast transfer of register content. The address pointer is incremented automatically and data is read from the locations [address], [address+1], [address+2]... [address+(n-1)] In order to support a fast FIFO data transfer, the address pointer is not incremented automatically in case the address is pointing to the FIFO. The read/write bit shall be set to logic 1. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 23 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Write Cycle I2C slave address A7-A0 SA 0 (W) Ack Frontend IC register address A6-A0 0 Ack DATA [7..0] [0..n] Ack SO Read Cycle 0 (W) I2C slave address A7-A0 SA Ack 0 Frontend IC register address A6-A0 Ack SO Optional, if the previous access was on the same register address 0..n 1 (R) I2C slave address A7-A0 SA Ack [0..n] sent by master DATA [7..0] Ack DATA [7..0] Nack SO sent by slave 001aam305 Figure 19. Register read and write access 2 7.4.4.9 I CL-bus interface The MFRC631 provides an additional interface option for connection of a SAM. This 2 logical interface fulfills the I C specification, but the rise/fall timings will not be compliant 2 2 to the I C standard. The I CL interface uses standard I/O pads, and the communication speed is limited to 5 MBaud. The protocol itself is equivalent to the fast mode protocol of 2 I C. The SCL levels are generated by the host in push/pull mode. The RC631 does not stretch the clock. During the high period of SCL the status of the line is maintained by a bus keeper. The address is 01010xxb, where the last two bits of the address can be defined by the application. The definition of this bits can be done by two options. With a pin, where the higher bit is fixed to 0 or the configuration can be defined via EEPROM. Refer to the EEPROM configuration in Section 7.7. 2 Table 18. Timing parameter I CL MFRC631 Product data sheet COMPANY PUBLIC Parameter Min Max Unit fSCL 0 5 MHz tHD;STA 80 - ns tLOW 100 - ns tHIGH 100 - ns tSU;SDA 80 - ns tHD;DAT 0 50 ns tSU;DAT 0 20 ns tSU;STO 80 - ns tBUF 200 - ns All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 24 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 2 The pull-up resistor is not required for the I CL interface. Instead, a on chip buskeeper 2 is implemented in the MFRC631 for SDA of the I CL interface. This protocol is intended to be used for a point to point connection of devices over a short distance and does not support a bus capability.The driver of the pin must force the line to the desired logic voltage. To avoid that two drivers are pushing the line at the same time following regulations must be fulfilled: SCL: As there is no clock stretching, the SCL is always under control of the Master. SDA: The SDA line is shared between master and slave. Therefore the master and the slave must have the control over the own driver enable line of the SDA pin. The following rules must be followed: * In the idle phase the SDA line is driven high by the master * In the time between start and stop condition the SDA line is driven by master or slave when SCL is low. If SCL is high the SDA line is not driven by any device * To keep the value on the SDA line a on chip buskeeper structure is implemented for the line 7.4.5 SAM interface 7.4.5.1 SAM functionality The MFRC631 implements a dedicated I2C or SPI interface to integrate a MIFARE SAM (Secure Access Module) in a very convenient way into applications (e.g. a proximity reader). The SAM can be connected to the microcontroller to operate like a cryptographic coprocessor. For any cryptographic task, the microcontroller requests a operation from the SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface to the connected reader IC. The MIFARE SAM supports a optimized method to integrate the SAM in a very efficient way to reduce the protocol overhead. In this system configuration, the SAM is integrated between the microprocessor and the reader IC, connected by one interface to the reader IC and by another interface to the microcontroller. In this application the microcontroller accesses the SAM using the T=1 protocol and the SAM accesses the reader IC using an I2C interface. The I2C SAM address is always defined by EEPROM register. Default value is 0101100. As the SAM is directly communicating with reader IC, the communication overhead is reduced. In this configuration, a performance boost of up to 40% can be achieved for a transaction time. The MIFARE SAM supports applications using MIFARE product-based cards. For multi application purposes an architecture connecting the microcontroller additionally directly to the reader IC is recommended. This is possible by connecting the MFRC631 on one interface (SAM Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/ T1AR1070) and by connecting the microcontroller to the S2C or SPI interface. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 25 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus T=1 C SAM AV2.6 I2C READER IC I2C Reader aaa-002963 Figure 20. I2C interface enables convenient MIFARE SAM integration 7.4.5.2 SAM connection The MFRC631 provides an interface to connect a SAM dedicated to the MFRC631. Both 2 2 interface options of the MFRC631, I C, I CL or SPI can be used for this purpose. The interface option of the SAM itself is configured by a host command sent from the host to the SAM. 2 The I CL interface is intended to be used as connection between two IC's over a short 2 distance. The protocol fulfills the I C specification, but does support a single device connected to the bus only. The SPI block for SAM connection is identical with the SPI host interface block. The pins used for the SAM SPI are described in Table 18. Table 19. SPI SAM connection SPI functionality PIN MISO SDA2 SCL SCL2 MOSI IFSEL1 NSS IFSEL0 7.4.6 Boundary scan interface The MFRC631 provides a boundary scan interface according to the IEEE 1149.1. This interface allows to test interconnections without using physical test probes. This is done by test cells, assigned to each pin, which override the functionality of this pin. To be able to program the test cells, the following commands are supported: Table 20. Boundary scan command MFRC631 Product data sheet COMPANY PUBLIC Value (decimal) Command Parameter in Parameter out 0 bypass - - 1 preload data (24) - 1 sample - data (24) 2 ID code (default) - data (32) 3 USER code - data (32) 4 Clamp - - All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 26 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value (decimal) Command Parameter in Parameter out 5 HIGH Z - - 7 extest data (24) data (24) 8 interface on/off interface (1) - 9 register access read address (7) data (8) 10 register access write address (7) - data (8) - The Standard IEEE 1149.1 describes the four basic blocks necessary to use this interface: Test Access Port (TAP), TAP controller, TAP instruction register, TAP data register; 7.4.6.1 Interface signals The boundary scan interface implements a four line interface between the chip and the environment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test Data Input (TDI) and one output Test Data Output (TDO). TCK and TMS are broadcast signals, TDI to TDO generate a serial line called Scan path. Advantage of this technique is that independent of the numbers of boundary scan devices the complete path can be handled with four signal lines. The signals TCK, TMS are directly connected with the boundary scan controller. Because these signals are responsible for the mode of the chip, all boundary scan devices in one scan path will be in the same boundary scan mode. 7.4.6.2 Test Clock (TCK) The TCK pin is the input clock for the module. If this clock is provided, the test logic is able to operate independent of any other system clocks. In addition, it ensures that multiple boundary scan controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the boundary scan controller does not change and data in the Instruction and Data Registers is not lost. The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking occurs if the pin is not driven from an external source. 7.4.6.3 Test Mode Select (TMS) The TMS pin selects the next state of the boundary scan controller. TMS is sampled on the rising edge of TCK. Depending on the current boundary scan state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the boundary scan controller state machine to the Test-Logic-Reset state. When the boundary scan controller enters the Test-Logic-Reset state, the Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism. The internal pull-up resistor on the TMS pin is enabled. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 27 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.4.6.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. The internal pull-up resistor on the TDI pin is enabled. 7.4.6.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. 7.4.6.6 Data register According to the IEEE1149.1 standard there are two types of data register defined: bypass and boundary scan The bypass register enable the possibility to bypass a device when part of the scan path.Serial data is allowed to be transferred through a device from the TDI pin to the TDO pin without affecting the operation of the device. The boundary scan register is the scan-chain of the boundary cells. The size of this register is dependent on the command. 7.4.6.7 Boundary scan cell The boundary scan cell opens the possibility to control a hardware pin independent of its normal use case. Basically the cell can only do one of the following: control, output and input. TDI TAP TCK IC2 LOGIC Boundary scan cell LOGIC IC1 TDO TDI TMS TDO TAP TCK TMS 001aam306 Figure 21. Boundary scan cell path structure 7.4.6.8 Boundary scan path This chapter shows the boundary scan path of the MFRC631. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 28 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 21. Boundary scan path of the MFRC631 Number (decimal) Cell Port Function 23 BC_1 - Control 22 BC_8 CLKOUT Bidir 21 BC_1 - Control 20 BC_8 SCL2 Bidir 19 BC_1 - Control 18 BC_8 SDA2 Bidir 17 BC_1 - Control 16 BC_8 IFSEL0 Bidir 15 BC_1 - Control 14 BC_8 IFSEL1 Bidir 13 BC_1 - Control 12 BC_8 IF0 Bidir 11 BC_1 - Control 10 BC_8 IF1 Bidir 9 BC_1 - Control 8 BC_8 IF2 Bidir 7 BC_1 IF2 Output2 6 BC_4 IF3 Bidir 5 BC_1 - Control 4 BC_8 IRQ Bidir 3 BC_1 - Control 2 BC_8 SIGIN Bidir 1 BC_1 - Control 0 BC_8 SIGOUT Bidir Refer to the MFRC631 BSDL file. 7.4.6.9 Boundary Scan Description Language (BSDL) All of the boundary scan devices have a unique boundary structure which is necessary to know for operating the device. Important components of this language are: * * * * * available test bus signal compliance pins command register data register boundary scan structure (number and types of the cells, their function and the connection to the pins.) 2 The MFRC631 is using the cell BC_8 for the IO-Lines. The I C Pin is using a BC_4 cell. For all pad enable lines the cell BC1 is used. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 29 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus The manufacturer's identification is 02Bh. * * * * attribute IDCODEISTER of MFRC631: entity is "0001" and -- version "0011110010000010b" and -- part number (3C82h) "00000010101b" and -- manufacturer (02Bh) "1b"; -- mandatory The user code data is coded as followed: * product ID (3 bytes) * version These four bytes are stored as the first four bytes in the EEPROM. 7.4.6.10 Non-IEEE1149.1 commands Interface on/off With this command the host/SAM interface can be deactivated and the Read and Write command of the boundary scan interface is activated. (Data = 1). With Update-DR the value is taken over. Register Access Read At Capture-DR the actual address is read and stored in the DR. Shifting the DR is shifting in a new address. With Update-DR this address is taken over into the actual address. Register Access Write At the Capture-DR the address and the data is taken over from the DR. The data is copied into the internal register at the given address. 7.5 Buffer 7.5.1 Overview An 512 x 8-bit FIFO buffer is implemented in the MFRC631. It buffers the input and output data stream between the host and the internal state machine of the MFRC631. Thus, it is possible to handle data streams with lengths of up to 512 bytes without taking timing constraints into account. The FIFO can also be limited to a size of 255 byte. In this case all the parameters (FIFO length, Watermark...) require a single byte only for definition. In case of a 512 byte FIFO length the definition of this values requires 2 bytes. 7.5.2 Accessing the FIFO buffer When the -Controller starts a command, the MFRC631 may, while the command is in progress, access the FIFO-buffer according to that command. Physically only one FIFObuffer is implemented, which can be used in input and output direction. Therefore the Controller has to take care, not to access the FIFO buffer in a way that corrupts the FIFO data. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 30 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.5.3 Controlling the FIFO buffer Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might be reset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits are set to logic 0, the actually stored bytes are not accessible any more and the FIFO buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1) again. 7.5.4 Status Information about the FIFO buffer The host may obtain the following data about the FIFO-buffers status: * Number of bytes already stored in the FIFO-buffer. Writing increments, reading decrements the FIFO level: FIFOLength in register FIFOLength (and FIFOControl Register in 512 byte mode) * Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according to the value of the water level in register WaterLevel (Register 02h bit [2], Register 03h bit[7:0]) * Warning, that the FIFO-buffer is almost empty: LoAlert in register FIFOControl according to the value of the water level in register WaterLevel (Register 02h bit [2], Register 03h bit[7:0]) * FIFOOvl bit indicates, that bytes were written to the FIFO buffer although it was already full: ErrIRQ in register IRQ0. WaterLevel is one single value defining both HiAlert (counting from the FIFO top) and LoAlert (counting from the FIFO bottom). The MFRC631 can generate an interrupt signal if: * LoAlertIRQEn in register IRQ0En is set to logic 1 it will activate pin IRQ when LoAlert in the register FIFOControl changes to 1. * HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert in the register FIFOControl changes to 1. The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register WaterLevel) or less can be stored in the FIFO-buffer. It is generated according to the following equation: (2) The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or less are actually stored in the FIFO-buffer. It is generated according to the following equation: (3) 7.6 Analog interface and contactless UART MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 31 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.6.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kbit/s. An external circuit can be connected to the communication interface pins SIGIN and SIGOUT to modulate and demodulate the data. The contactless UART handles the protocol requirements for the communication schemes in co-operation with the host. The protocol handling itself generates bit- and byte-oriented framing and handles error detection like Parity and CRC according to the different contactless communication schemes. The size, the tuning of the antenna, and the supply voltage of the output drivers have an impact on the achievable field strength. The operating distance between reader and card depends additionally on the type of card used. 7.6.2 TX transmitter The signal delivered on pin TX1 and pin TX2 is the 13.56 MHz carrier modulated by an envelope signal for energy and data transmission. It can be used to drive an antenna directly, using a few passive components for matching and filtering, see Section 13 "Application information". The signal on TX1 and TX2 can be configured by the register DrvMode, see Section 8.8.1 "TxMode". The modulation index can be set by the TxAmp. Following figure shows the general relations during modulation influenced by set_clk_mode envelope TX ASK100 TX ASK10 (1) (2) 1: Defined by set_cw_amplitude. 2: Defined by set_residual_carrier. time 001aan355 Figure 22. General dependences of modulation Note: When changing the continuous carrier amplitude, the residual carrier amplitude also changes, while the modulation index remains the same. The registers Section 8.8 and Section 8.10 control the data rate, the framing during transmission and the setting of the antenna driver to support the requirements at the different specified modes and transfer speeds. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 32 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 22. Settings for TX1 and TX2 TxClkMode (binary) Tx1 and TX2 output Remarks 000 High impedance - 001 0 output pulled to 0 in any case 010 1 output pulled to 1 in any case 110 RF high side push open drain, only high side (push) MOS supplied with clock, clock parity defined by invtx; low side MOS is off 101 RF low side pull open drain, only low side (pull) MOS supplied with clock, clock parity defined by invtx; high side MOS is off 111 13.56 MHz clock derived from 27.12 MHz quartz divided by 2 push/pull Operation, clock polarity defined by invtx; setting for 10% modulation Register TXamp and the bits for set_residual_carrier define the modulation index: Table 23. Setting residual carrier and modulation index by TXamp.set_residual_carrier MFRC631 Product data sheet COMPANY PUBLIC set_residual_carrier (decimal) residual carrier [%] modulation index [%] 0 99 0.5 1 98 1.0 2 96 2.0 3 94 3.1 4 91 4.7 5 89 5.8 6 87 7.0 7 86 7.5 8 85 8.1 9 84 8.7 10 83 9.3 11 82 9.9 12 81 10.5 13 80 11.1 14 79 11.7 15 78 12.4 16 77 13.0 17 76 13.6 18 75 14.3 19 74 14.9 20 72 16.3 21 70 17.6 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 33 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus set_residual_carrier (decimal) residual carrier [%] modulation index [%] 22 68 19.0 23 65 21.2 24 60 25.0 25 55 29.0 26 50 33.3 27 45 37.9 28 40 42.9 29 35 48.1 30 30 53.8 31 25 60.0 Note: At VDD(TVDD) <5 V and residual carrier settings <50%, the accuracy of the modulation index may be low in dependency of the antenna tuning impedance 7.6.2.1 Overshoot protection The MFRC631 provides an overshoot protection for 100% ASK to avoid overshoots during a PCD communication. Therefore two timers overshoot_t1 and overshoot_t2 can be used. During the timer overshoot_t1 runs an amplitude defined by set_cw_amplitude bits is provided to the output driver. Followed by an amplitude denoted by set_residual_carrier bits with the duration of overshoot_t2. 7.0 (V) 5.0 3.0 1.0 -1.0 2.50 3.03 3.56 4.10 time ( s) 001aan356 Figure 23. Example 1: overshoot_t1 = 2d; overhoot_t2 = 5d. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 34 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.0 (V) 5.0 3.0 1.0 -1.0 0 1 2 3 4 time ( s) 5 001aan357 Figure 24. Example 2: overshoot_t1 = 0d; overhoot_t2 = 5d 7.6.2.2 Bit generator The default coding of a data stream is done by using the Bit-Generator. It is activated when the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Generator encodes the data stream byte-wise and can apply the following encoding steps to each data byte. 1. Add a start-bit of specified type at beginning of every byte 2. Add a stop-bit and EGT bits of a specified type. The maximum number of EGT bit is 6, only full bits are supported 3. Add a parity-bit of a specified type 4. TxLastBits (skips a given number of bits at the end of the last byte in a frame) 5. Encrypt data-bit (MIFARE Classic encryption) It is not possible to skip more than 8 bit of a single byte! By default, data bytes are always treated LSB first. 7.6.3 Receiver circuitry 7.6.3.1 General The MFRC631 features a versatile quadrature receiver architecture with fully differential signal input at RXP and RXN. It can be configured to achieve optimum performance for reception of various 13.56 MHz based protocols. For all processing units various adjustments can be made to obtain optimum performance. 7.6.3.2 Block diagram Figure 25 shows the block diagram of the receiver circuitry. The receiving process includes several steps. First the quadrature demodulation of the carrier signal of 13.56 MHz is done. Several tuning steps in this circuit are possible. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 35 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus fully/quasi-differential rcv_hpcf<1:0> rcv_gain<1:0> rx_p mixer rx_n mix_out_i_p out_i_p mix_out_i_n out_i_n 2-stage BBA I-clks rx_p rx_n clk_27 MHz DATA 13.56 MHz I/O CLOCK GENERATION TIMING GENERATION ADC clk_27 MHz Q-clks rx_p mix_out_q_p rx_n mix_out_q_n 2-stage BBA out_q_p Adc_data_ready DATA out_q_n mixer rcv_gain<1:0> fully/quasi-differential rcv_hpcf<1:0> 001aan358 Figure 25. Block diagram of receiver circuitry The receiver can also be operated in a single ended mode. In this case the Rcv_RX_single bit has to be set. In the single ended mode, the two receiver pins RXP and RXN need to be connected together and will provide a single ended signal to the receiver circuitry. When using the receiver in a single ended mode the receiver sensitivity is decreased and the achievable reading distance might be reduced, compared to the fully differential mode. Table 24. Configuration for single or differential receiver Mode rcv_rx_single pins RXP and RXN Fully differential 0 provide differential signal from differential antenna by separate rxcoupling branches Quasi differential 1 connect RXP and RXN together and provide single ended signal from antenna by a single rxcoupling branch The quadrature-demodulator uses two different clocks, Q-clock and I-clock, with a phase shift of 90 between them. Both resulting baseband signals are amplified, filtered, digitized and forwarded to a correlation circuitry. The typical application is intended to implement the Fully differential mode and will deliver maximum reader/writer distance. The Quasi differential mode can be used together with dedicated antenna topologies that allow a reduction of matching components at the cost of overall reading performance. During low power card detection the DC levels at the I- and Q-channel mixer outputs are evaluated. This requires that mixers are directly connected to the ADC. This can be configured by setting the bit Rx_ADCmode in register Rcv (38h). MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 36 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.6.4 Active antenna concept Two main blocks are implemented in the MFRC631. A digital circuitry, comprising state machines, coder and decoder logic and an analog circuitry with the modulator and antenna drivers, receiver and amplification circuitry. For example, the interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins SIGIN and SIGOUT. The most important use of this topology is the active antenna concept where the digital and the analog blocks are separated. This opens the possibility to connect e.g. an additional digital block of another MFRC631 device with a single analog antenna front-end. READER IC (DIGITAL) SIGIN SIGOUT SIGOUT SIGIN READER IC (ANTENNA) 001aam307 Figure 26. Block diagram of the active Antenna concept The Table 24 and Table 25 describe the necessary register configuration for the use case active antenna concept. Table 25. Register configuration of MFRC631 active antenna concept (DIGITAL) Register Value (binary) Description SigOut.SigOutSel 0100 TxEnvelope Rcv.SigInSel 10 11 Receive over SigIn (ISO/IEC14443A) Receive over SigIn (Generic Code) DrvCon.TxSel 00 Low (idle) Table 26. Register configuration of MFRC631 active antenna concept (Antenna) Register Value (binary) Description SigOut.SigOutSel 0110 0111 Generic Code (Manchester) Manchester with Subcarrier (ISO/IEC14443A) Rcv.SigInSel 01 Internal DrvCon.TxSel 10 External (SigIn) RxCtrl.RxMultiple 1 RxMultiple on The interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins SIGIN and SIGOUT (see Figure 27 "Overview SIGIN/ SIGOUT Signal Routing"). This topology supports, that some parts of the analog part of the MFRC631 may be connected to the digital part of another device. The switch SigOutSel in registerSigOut can be used to measure signals. This is especially important during the design In phase or for test purposes to check the transmitted and received data. However, the most important use of SIGIN/SIGOUT pins is the active antenna concept. An external active antenna circuit can be connected to the digital circuit of the MFRC631. SigOutSel has to be configured in that way that the signal of the internal Miller Coder MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 37 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus is sent to SIGOUT pin (SigOutSel = 4). SigInSel has to be configured to receive Manchester signal with sub-carrier from SIGIN pin (SigInSel = 1). It is possible, to connect a passive antenna to pins TX1, TX2 and RX (via the appropriate filter and matching circuit) and at the same time an active antenna to the pins SIGOUT and SIGIN. In this configuration, two RF-parts may be driven (one after another) by a single host processor. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 38 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus SIGOUT TX bit stream tri-state LOW HIGH TX envelope TX active S3C signal RX envelope RX active RX bit signal CODER DIGITAL MODULE RX bit stream DECODER 0 1 2 Sigpro_in_sel 3 [1:0] 0, 1 2 SIGOUTSel[4:0] 3 4 5 6 7 8 9 tri-state internal analog block SIGIN over envelope SIGIN generic No_nodulation TX envelope SIGIN RFU 0 1 2 3 TxCon.TxSel [1:0] MODULATOR DRIVER TX2 TX1 ANALOG MODULE SUBCARRIER DEMODULATOR DEMODULATOR SIGIN RXN RXP 001aam001 Figure 27. Overview SIGIN/SIGOUT Signal Routing MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 39 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.6.5 Symbol generator The symbol generator is used to create various protocol symbols. These can be e.g. SOF or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol symbols. Symbols are defined by means of the symbol definition registers and the mode registers. Four different symbols can be used. Two of them, Symbol0 and Symbol1 have a maximum pattern length of 16 bit and feature a burst length of up to 256 bits of either logic "0" or logic "1". The Symbol2 and Symbol3 are limited to 8 bit pattern length and do not support a burst. The definition of symbol patterns is done by writing the bit sequence of the pattern to the appropriate register. The last bit of the pattern to be sent is located at the LSB of the register. By setting the symbol length in the symbol-length register (TxSym10Len and TxSym32Len) the definition of the symbol pattern is completed. All other bits at bitposition higher than the symbol length in the definition register are ignored. (Example: length of Symbol2 = 5, bit7 and bit6 are ignored, bit5 to bit0 define the symbol pattern, bit5 is sent first) Which symbol-pattern is sent can be configured in the TxFrameCon register. Symbol0, Symbol1 and Symbol2 can be sent before data packets, Symbol1, Symbol2 and Symbol3 can be sent after data packets. Each symbol is defined by a set of registers. Symbols are configured by a pair of registers. Symbol0 and Symbol1 share the same configuration and Symbol2 and Symbol3 share the same configuration. The configuration includes setting of bit-clock- and subcarrier-frequency, as well as selection of the pulse type/length and the envelope type. 7.7 Memory 7.7.1 Memory overview The MFRC631 implements three different memories: EEPROM, FIFO and Registers. At startup, the initialization of the registers which define the behavior of the IC is performed by an automatic copy of an EEPROM area (read/write EEPROM section1 and section2, register reset) into the registers. The behavior of the MFRC631 can be changed by executing the command LoadProtocol, which copies a selected default protocol from the EEPROM (read only EEPROM section4, register Set Protocol area) into the registers. The read/write EEPROM section2 can be used to store any user data or predefined register settings. These predefined settings can be copied with the command "LoadRegister" into the internal registers. The FIFO is used as Input/Out buffer and is able to improve the performance of a system with limited interface speed. 7.7.2 EEPROM memory organization The MFRC631 has implemented a EEPROM non-volatile memory with a size of 8 kB.The EEPROM is organized in pages of 64 bytes. One page of 64 bytes can be programmed at a time. Defined purposes had been assigned to specific memory areas MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 40 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus of the EEPROM, which are called Sections. Five sections 0..4 with different purpose do exist. Table 27. EEPROM memory organization Section Page Byte addresses Access rights Memory content 0 0 00 to 31 r product information and configuration 32 to 63 r/w product configuration 1 1 to 2 64 to 191 r/w register reset 2 3 to 95 192 to 6143 r/w free 3 96 to 111 6144 to 7167 w MIFARE Classic key 4 112 to 128 7168 to 8191 r Register Set Protocol (RSP) The following figure show the structure of the EEPROM: Section 0: Production and config Section 1: Register reset Section 2: Free Section 3: MIFARE Classic key area (MKA) Section 4_TX: RSP-Area for TX Section 4_RX: RSP-Area for RX 001aan359 Figure 28. Sector arrangement of the EEPROM 7.7.2.1 Product information and configuration - Page 0 The first EEPROM page includes production data as well as configuration information. Table 28. Production area (Page 0) Address (Hex.) 0 00 ProductID 08 Unique Identifier 10 ManufacturerData 18 ManufacturerData MFRC631 Product data sheet COMPANY PUBLIC 1 2 3 4 5 Version Unique Identifier 6 7 Manufacturer Data All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 41 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus ProductID: Identifier for this MFRC631 product, only address 01h shall be evaluated for identifying the Product of the CLRC663 family, address 00h and 02h shall be ignored by software. Table 29. Product ID overview of CLRC663 family Address 01h Product ID CLRC663 01h MFRC631 C0h MFRC630 80h SLRC610 20h Version: This register indicates the version of the EEPROM initialization data during production. (Identification of the Hardware version is available in the register 7Fh, not in the EEPROM Version address. The hardware information in register 7Fh is hardwired and therefore independent from any EEPROM configuration.) Unique Identifier: Unique number code for this device Manufacturer Data: This data is programmed during production. The content is not intended to be used by any application and might be not the same for different devices. Therefore this content needs to be considered to be undefined. Table 30. Configuration area (Page 0) Address 0 (Hex.) 2 20 I C_Address 28 RxCRCPreset 30 - 38 - 1 2 Interface 3 4 5 6 I C SAM_Address DefaultProtRx DefaultProtTx - TxCRCPreset - - - - 2 - 7 - 2 I C-Address 2 Two possibilities exist to define the address of the I C interface. This can be done either by configuring the pins IF0, IF2 (address is then 10101xx, xx is defined by the interface 2 pins IF0, IF2) or by writing value into the I C address area. The selection, which of this 2 2-information pin configuration or EEPROM content - is used as I C-address is done at EEPROM address 21h (Interface, bit4) Interface This section describes the interface byte configuration. Table 31. Interface byte Bit access rights MFRC631 Product data sheet COMPANY PUBLIC 7 6 5 4 3 2 2 I C_HSP - - I2C_Address Boundary Scan Host r/w RFU RFU r/w r/w - All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 1 0 - - (c) NXP B.V. 2018. All rights reserved. 42 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 32. Interface bits Bit Symbol 7 I C_HSP Description 2 when cleared, the high speed mode is used when set, the high speed+ mode is used (default) 6, 5 RFU - 2 4 I C_Address when cleared, the pins are used (default) when set, the EEPROM is used 3 2 to 0 Boundary Scan when cleared, the boundary scan interface is ON (default) Host 000b - RS232 when set, the boundary scan is OFF 2 001b - I C 010b - SPI 2 011b - I CL 1xxb - pin selection 2 I C_SAM_Address 2 The I C SAM Address is always defined by the EEPROM content. The Register Set Protocol (RSP) Area contains settings for the TX registers (16 bytes) and for the RX registers (8 bytes). Table 33. Tx and Rx arrangements in the register set protocol area Section Section 4 TX Tx0 Tx1 TX2 Tx3 Section 4 TX Tx4 Tx5 TX6 TX7 Section 4 Rx RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 Section 4 Rx RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 TxCrcPreset The data bits are send by the analog module and are automatically extended by a CRC. 7.7.3 EEPROM initialization content LoadProtocol The MFRC631 EEPROM is initialized at production with values which are used to reset certain registers of the MFRC631 to default settings by copying the EEprom content to the registers. Only registers or bits with "read/write" or "dynamic" access rights are initialized with this default values copied from the EEProm. Note that the addresses used for copying reset values from EEprom to registers are dependent on the configured protocol and can be changed by the user. Table 34. Register reset values (Hex.) (Page0) Address 0 (8) Function Product ID MFRC631 Product data sheet COMPANY PUBLIC 1 (9) 2 (A) 3 (B) 4 (C) Version Unique Identifier All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 5 (D) 6 (E) 7 (F) (c) NXP B.V. 2018. All rights reserved. 43 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Address 0 (8) 1 (9) 00 XX see table 30 XX Function Unique Identifier 08 XX XX Function TrimLFO Factory trim values 10 XX XX Function Factory trim values 18.... XX XX 2 (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 (F) XX XX XX XX XX Factory trim value XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX XX Factory trim values ....38 XX XX The register reset values are configuration parameters used after startup of the IC. They can be changed to modify the default behavior of the device. In addition to this register reset values, is the possibility to load settings for various user implemented protocols.The load protocol command is used for this purpose. Table 35. Register reset values (Hex.)(Page1 and page 2) Address 40 48 50 58 60 68 70 78 0 (8) 1 (9) 2 (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 (F) Command HostCtrl FiFoControl WaterLevel FiFoLength FiFoData IRQ0 IRQ1 40 00 80 05 00 00 00 00 IRQ0En IRQ1En Error Status RxBitCtrl RxColl TControl T0Control 10 00 00 00 00 00 00 00 T0ReloadHi T0ReloadLo T0Counter ValHi T0Counter ValLo T1Control T1ReloadHi T1ReloadLo T1Counter ValHi 00 80 00 00 00 00 80 00 T1Counter ValLo T2Control T2ReloadHi T2ReloadLo T2Counter ValHi T2Counter ValLo T3Control T3ReloadHi 00 00 00 80 00 00 00 00 T3ReloadLo T3Counter ValHi T3Counter ValHi T4Control T4ReloadHi T4ReloadLo T4Counter ValHi T4Counter ValLo 80 00 00 00 00 80 00 00 DrvMode TxAmp DrvCon Txl TxCRC Preset RxCRC Preset TxDataNum TxModWith 86 15 11 06 18 18 08 27 TxSym10 BurstLen TxWaitCtrl TxWaitLo FrameCon RxSofD RxCtrl RxWait RxThres hold 00 C0 12 CF 00 04 90 3F Rcv RxAna RFU SerialSpeed LFO_trimm PLL_Ctrl PLL_Div LPCD_QMin 12 0A 00 7A 04 20 48 MFRC631 Product data sheet COMPANY PUBLIC 80 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 44 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Address 80 88 90 98 0 (8) 1 (9) 2 (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 (F) LPCD_ QMax LPCD_IMin LPCD _result_I LPCD _result_Q PadEn PadOut PadIn SigOut 12 88 00 00 00 00 00 00 TxBitMod RFU TxDataCon TxDataMod TxSymFreq TxSym0H TySym0L TxSym1H 20 xx 04 50 40 00 00 00 TxSym1L TxSym2 TxSym3 TxSym10Le TxSym32Le TxSym32Bu TxSym10M ngth ngth rstCtrl od TxSym32M od 0x00 0x00 0x00 0x00 0x00 0x50 RxBitMod RxEOFSym RxSyncValH RxSyncValL RxSyncMod RxMod RXCorr FabCal 0x02 0x00 0x08 0xB2 0x00 0x01 0x00 0x00 0x00 0x08 7.8 Clock generation 7.8.1 Crystal oscillator The clock applied to the MFRC631 acts as time basis for generation of the carrier sent out at TX and for the quadrature mixer I and Q clock generation as well as for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter has to be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. READER IC XTAL1 XTAL2 27.12 MHz 001aam308 Figure 29. Quartz connection Table 36. Crystal requirements recommendations MFRC631 Product data sheet COMPANY PUBLIC Symbol Parameter fxtal Conditions Min Typ max Unit crystal frequency - 27.12 - MHz fxtal/fxtal relative crystal frequency variation -250 - +250 ppm ESR equivalent series resistance - 50 100 CL load capacitance - 10 - pF Pxtal crystal power dissipation - 50 100 W All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 45 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.8.2 IntegerN PLL clock line The MFRC631 is able to provide a clock with configurable frequency at CLKOUT from 1 MHz to 24 MHz (PLL_Ctrl and PLL_DIV). There it can serve as a clock source to a microcontroller which avoids the need of a second crystal oscillator in the reader system. Clock source for the IntegerN-PLL is the 27.12 MHz crystal oscillator. Two dividers are determining the output frequency. First a feedback integer-N divider configures the VCO frequency to be N x fin/2 (control signal pll_set_divfb). As supported Feedback Divider Ratios are 23, 27 and 28, VCO frequencies can be 23 x fin / 2 (312 MHz), 27 x fin / 2 (366 MHz) and 28 x fin / 2 (380 MHz). The VCO frequency is divided by a factor which is defined by the output divider (pll_set_divout). Table 36 "Divider values for selected frequencies using the integerN PLL" shows the accuracy achieved for various frequencies (integer multiples of 1 MHz and some typical RS232 frequencies) and the divider ratios to be used. The register bit ClkOutEn enables the clock at CLKOUT pin. The following formula can be used to calculate the output frequency: fout = 13.56 MHz x PLLDiv_FB /PLLDiv_Out Table 37. Divider values for selected frequencies using the integerN PLL Frequency [MHz] 4 6 8 10 12 20 24 1.8432 3.6864 PLLDiv_FB 23 27 23 28 23 28 23 28 28 PLLDiv_Out 78 61 39 38 26 19 16 206 103 accuracy [%] 0.04 0.03 0.04 0.08 0.04 0.08 0.04 0.01 0.01 7.8.3 Low Frequency Oscillator (LFO) The MFRC631 implements an Low-Frequency Oscillator (LFO). Timer T4 can be configured to use a clock generated by this LFO as input clock, and can be configured as wakeup counter. As wakeup counter, the timer T4 allows to wake up the system in regular time intervals which allows to design a reader that is regularly polling for card presence or implements a low-power card detection (LPCD). The LFO is trimmed during chip production to run at 16 kHz. Unless a high accuracy of the LFO is required by the application, and the device is operated in an environment with changing ambient temperatures, trimming of the LFO is not required. For a typical application making use of the LFO for wake-up from power saving mode, the trim value set during production can be used. Optional trimming to achieve a higher accuracy of the 16 kHz LFO clock is supported by a digital state machine which compares LFO-clock to a reference clock generated by the connected 27.12Mhz crystal. As reference clock frequency for trimming of the LFO, a 13.56 MHz clock (27.12Mhz divided by 2 ) input clock to one of the timers T0,T1,T2 or T3 is used. One of the timers T0,T1,T2,T3 with an input clock of 13,56 MHz crystal clock is used to count one clock period of the LFO. For an LFO Clock running at 16KHz this would result in 848 wakeup timer clocks of timer Tx (T0, T1, T2, T3). Therefrore, the timer count value Tx at the end of a trimming cycle is expected to be 176 (wakeup timer is counting down: 1023-848=175, +/- 1 tolerance is accepted). The trim cycle is executed once in the T4 timer cycle. Therefore the T4 autoload value shall be bigger than 0x05 to ensure that one trimming cycle takes place before T4 expires. The Tx timer value is reloaded to 1023 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 46 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus during the start of an Auto trim cycle. This happens every time, once after the T4 timer underflows. At the end of each trim cycle, the timer value is checked: * Timer Tx value < 174: LFO Frequency is too low and the trim value is incremented by 1 on T4 Timer event * Timer Tx value > 176: LFO Frequency is too high and the trim value is decremented by 1 on T4 Timer event * Timer Tx value is within 174 and 176: LFO Frequency = 16 KHz and trimming procedure is stopped The cycle proceeds until the autotrimm function is stopped (Timer Tx value is within 174 and 176). In addition, the trimming cycle can be aborted by sending an IDLE Command from the host to cancel the current command execution. T3 is not allowed to be used in case T4AutoLPCD is set in parallel. It is not required to configure a TXStart condition with underflow. The T0/1/2/3 timer will typically not underflow. It may happen if the LPO clock is very slow, but it is not required to take an action to generate this event. 7.9 Power management 7.9.1 Supply concept The MFRC631 is supplied by VDD (Supply Voltage), PVDD (Pad Supply) and TVDD (Transmitter Power Supply). These three voltages are independent from each other. To connect the MFRC631 to a Microcontroller supplied by 3.3 V, PVDD and VDD shall be at a level of 3.3 V, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage at TVDD will result in a higher field strength. Independent of the voltage it is recommended to buffer these supplies with blocking capacitances close to the terminals of the package. VDD and PVDD are recommended to be blocked with a capacitor of 100 nF min, TVDD is recommended to be blocked with 2 capacitors, 100 nF parallel to 1.0 F AVDD and DVDD are not supply input pins. They are output pins and shall be connected to blocking capacitors 470 nF each. 7.9.2 Power reduction mode 7.9.2.1 Power-down A hard power-down is enabled with HIGH level on pin PDOWN. This turns off the internal 1.8 V voltage regulators for the analog and digital core supply as well as the oscillator. All digital input buffers are separated from the input pads and clamped internally (except pin PDOWN itself). The output pins are switched to high impedance. HardPowerDown is performing a reset of the IC. All registers will be reset, the Fifo will be cleared. To leave the power-down mode the level at the pin PDOWN as to be set to LOW. This will start the internal start-up sequence. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 47 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.9.2.2 Standby mode The standby mode is entered immediately after setting the bit PowerDown in the register Command. All internal current sinks are switched off. Voltage references and voltage regulators will be set into stand-by mode. In opposition to the power-down mode, the digital input buffers are not separated by the input pads and keep their functionality. The digital output pins do not change their state. During standby mode, all registers values, the FIFO's content and the configuration itself will keep its current content. To leave the standby mode the bit PowerDown in the register Command is cleared. This will trigger the internal start-up sequence. The reader IC is in full operation mode again when the internal start-up sequence is finalized (the typical duration is 15 us). A value of 55h must be sent to the MFRC631 using the RS232 interface to leave the 2 standby mode. This is must at RS232, but cannot be used for the I C/SPI interface. Then read accesses shall be performed at address 00h until the device returns the content of this address. The return of the content of address 00h indicates that the device is ready to receive further commands and the internal start-up sequence is finalized. 7.9.2.3 Modem off mode When the ModemOff bit in the register Control is set the antenna transmitter and the receiver are switched off. To leave the modem off mode clears the ModemOff bit in the register Control. 7.9.3 Low-Power Card Detection (LPCD) The low-power card detection is an energy saving mode in which the MFRC631 is not fully powered permanently. The LPCD works in two phases. First the standby phase is controlled by the wake-up counter (WUC), which defines the duration of the standby of the MFRC631. Second phase is the detection-phase. In this phase the values of the I and Q channel are detected and stored in the register map. (LPCD_I_Result, LPCD_Q_Result).This time period can be handled with Timer3. The value is compared with the min/max values in the registers (LPCD_IMin, LPCD_IMax; LPCD_QMin, LPCD_QMax). If it exceeds the limits, a LPCDIRQ is raised. After the command LPCD the standby of the MFRC631 is activated, if selected. The wake-up Timer4 can activate the system after a given time. For the LPCD it is recommended to set T4AutoWakeUp and T4AutoRestart, to start the timer and then go to standby. If a card is detected the communication can be started. If T4AutoWakeUp is not set, the IC will not enter Standby mode in case no card is detected. 7.9.4 Reset and start-up time A 10 s constant high level at the PDOWN pin starts the internal reset procedure. The following figure shows the internal voltage regulator: MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 48 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus VDD PVDD 1.8 V GLITCH FILTER PDown INTERNAL VOLTAGE REGULATOR 1.8 V VSS AVDD DVDD VSS 001aan360 Figure 30. Internal PDown to voltage regulator logic When the MFRC631 has finished the reset phase and the oscillator has entered a stable working condition the IC is ready to be used. A typical duration before the IC is ready to receive commands after the reset had been released is 2.5ms. 7.10 Command set 7.10.1 General The behavior is determined by a state machine capable to perform a certain set of commands. By writing a command-code to the command register the command is executed. Arguments and/or data necessary to process a command, are exchanged via the FIFO buffer. * Each command that needs a certain number of arguments will start processing only when it has received the correct number of arguments via the FIFO buffer. * The FIFO buffer is not cleared automatically at command start. It is recommended to write the command arguments and/or the data bytes into the FIFO buffer and start the command afterwards. * Each command may be stopped by the host by writing a new command code into the command register e.g.: the Idle-Command. 7.10.2 Command set overview Table 38. Command set Command No. Parameter (bytes) Short description Idle 00h - no action, cancels current command execution LPCD 01h - low-power card detection LoadKey 02h (keybyte1),(keybyte2), (keybyte3), (keybyte4), (keybyte5),(keybyte6); reads a MIFARE Classic key (size of 6 bytes) from FIFO buffer ant puts it into Key buffer MFAuthent 03h 60h or 61h, (block address), (card serial number byte0),(card serial number byte1), (card serial number byte2),(card serial number byte3); performs the MIFARE Classic authentication AckReq 04h - performs a query, an Ack and a Req-Rn for ISO/IEC 18000-3 mode 3/ EPC Class-1 HF Receive 05h - activates the receive circuit Transmit 06h bytes to send: byte1, byte2,.... transmits data from the FIFO buffer MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 49 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Command No. Parameter (bytes) Short description Transceive 07h bytes to send: byte1, byte2,.... transmits data from the FIFO buffer and automatically activates the receiver after transmission finished WriteE2 08h addressH, addressL, data; gets one byte from FIFO buffer and writes it to the internal EEPROM WriteE2Page 09h (page Address), data0, [data1 ..data63]; gets up to 64 bytes (one EEPROM page) from the FIFO buffer and writes it to the EEPROM ReadE2 0Ah addressH, address L, length; reads data from the EEPROM and copies it into the FIFO buffer LoadReg 0Ch (EEPROM addressH), (EEPROM addressL), RegAdr, (number of Register to be copied); reads data from the internal EEPROM and initializes the MFRC631 registers. EEPROM address needs to be within EEPROM sector 2 LoadProtocol 0Dh (Protocol number RX), (Protocol number TX); reads data from the internal EEPROM and initializes the MFRC631 registers needed for a Protocol change LoadKeyE2 0Eh KeyNr; copies a key from the EEPROM into the key buffer StoreKeyE2 0Fh KeyNr, byte1,byte2, byte3, byte4, byte5,byte6; stores a MIFARE Classic key (size of 6 bytes) into the EEPROM ReadRNR 1Ch - Copies bytes from the Random Number generator into the FIFO until the FiFo is full Soft Reset 1Fh - resets the MFRC631 7.10.3 Command functionality 7.10.3.1 Idle command Command (00h); This command indicates that the MFRC631 is in idle mode. This command is also used to terminate the actual command. 7.10.3.2 LPCD command Command (01h); This command performs a low-power card detection and/or an automatic trimming of the LFO. After wakeup from standby, the values of the sampled I and Q channels are compared with the min/max threshold values in the registers. If it exceeds the limits, an LPCD_IRQ will be raised. After the LPCD command the standby is activated, if selected. 7.10.3.3 Load key command Command (02h), Parameter1 (key byte1),..., Parameter6 (key byte6); Loads a MIFARE Classic key (6 bytes) for Authentication from the FIFO into the crypto unit. Abort condition: Less than 6 bytes written to the FIFO. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 50 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.10.3.4 MFAuthent command Command (03h), Parameter1 (Authentication command code 60h or 61h), Parameter2 (block address), Parameter3 (card serial number byte0), Parameter4 (card serial number byte1), Parameter5 (card serial number byte2), Parameter6 (card serial number byte3); This command handles the MIFARE Classic authentication in Reader/Writer mode to ensure a secure communication to any MIFARE Classic card. When the MFAuthent command is active, any FIFO access is blocked. Anyhow if there is an access to the FIFO, the bit WrErr in the Error register is set. This command terminates automatically when the MIFARE Classic card is authenticated and the bit MFCrypto1On is set to logic 1. This command does not terminate automatically, when the card does not answer, therefore the timer should be initialized to automatic mode. In this case, beside the bit IdleIRQ the bit TimerIRQ can be used as termination criteria. During authentication processing the bits RxIRQ and TxIRQ are blocked. The Crypto1On shows if the authentication was successful. The Crypto1On is always valid. In case there is an error during authentication, the bit ProtocolErr in the Error register is set to logic 1 and the bit Crypto1On in register Status2Reg is set to logic 0. 7.10.3.5 Receive command Command (05h); The MFRC631 activates the receiver path and waits for any data stream to be received, according to its register settings. The registers must be set before starting this command according to the used protocol and antenna configuration. The correct settings have to be chosen before starting the command. This command terminates automatically when the received data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected framing and speed. 7.10.3.6 Transmit command Command (06h); data to transmit The content of the FIFO is transmitted immediately after starting the command. Before transmitting the FIFO all relevant registers have to be set to transmit data. This command terminates automatically when the FIFO gets empty. It can be terminated by any other command written to the command register. 7.10.3.7 Transceive command Command (07h); data to transmit This command transmits data from FIFO buffer and automatically activates the receiver after a transmission is finished. Each transmission process starts by writing the command into CommandReg. Remark: If the bit RxMultiple in register RxModeReg is set to logic 1, this command will never leave the receiving state, because the receiving will not be cancelled automatically. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 51 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.10.3.8 WriteE2 command Command (08h), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (data); This command writes one byte into the EEPROM. If the FIFO contains no data, the command will wait until the data is available. Abort condition: Address-parameter outside of allowed range 0x00 - 0x7F. 7.10.3.9 WriteE2PAGE command Command (09h), Parameter1 (page address), Parameter2..63 (data0, data1...data63); This command writes up to 64 bytes into the EEPROM. The addresses are not allowed to wrap over a page border. If this is the case, this additional data be ignored and stays in the fifo. The programming starts after 64 bytes are read from the FIFO or the FIFO is empty. Abort condition: Insufficient parameters in FIFO; Page address parameter outside of range 0x00 - 0x7F. 7.10.3.10 ReadE2 command Command (0Ah), Parameter1 (addressH), Parameter2 (addressL), Parameter3 (length); Reads up to 256 bytes from the EEPROM to the FIFO. If a read operation exceeds the address 1FFFh, the read operation continues from address 0000h. Abort condition: Insufficient parameter in FIFO; Address parameter outside of range. 7.10.3.11 LoadReg command Command (0Ch), Parameter1 (EEPROM addressH),Parameter2 (EEPROM addressL), Parameter3 (RegAdr), Parameter4 (number); Read a defined number of bytes from the EEPROM and copies the value into the Register set, beginning at the given address RegAdr. Abort condition: Insufficient parameter in FIFO; Address parameter outside of range. 7.10.3.12 LoadProtocol command Command (0Dh), Parameter1 (Protocol number RX), Parameter2 (Protocol number TX); Reads out the EEPROM Register Set Protocol Area and overwrites the content of the Rx- and Tx- related registers. These registers are important for a Protocol selection. Abort condition: Insufficient parameter in FIFO Table 39. Predefined protocol overview RX MFRC631 Product data sheet COMPANY PUBLIC [1] Protocol Number (decimal) Protocol Receiver speed [kbits/s] Receiver Coding 00 ISO/IEC14443 A 106 Manchester SubC 01 ISO/IEC14443 A 212 BPSK 02 ISO/IEC14443 A 424 BPSK All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 52 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Protocol Number (decimal) Protocol Receiver speed [kbits/s] Receiver Coding 03 ISO/IEC14443 A 848 BPSK 04 ISO/IEC14443 B 106 BPSK 05 ISO/IEC14443 B 212 BPSK 06 ISO/IEC14443 B 424 BPSK 07 ISO/IEC14443 B 848 BPSK [1] For more protocol details please refer to Section 7 "Functional description". [1] Table 40. Predefined protocol overview TX Protocol Number (decimal) Protocol Transmitter speed [kbits/s] Transmitter Coding 00 ISO/IEC14443 A 106 Miller 01 ISO/IEC14443 A 212 Miller 02 ISO/IEC14443 A 424 Miller 03 ISO/IEC14443 A 848 Miller 04 ISO/IEC14443 B 106 NRZ 05 ISO/IEC14443 B 212 NRZ 06 ISO/IEC14443 B 424 NRZ 07 ISO/IEC14443 B 848 NRZ [1] For more protocol details please refer to Section 7 "Functional description". 7.10.3.13 LoadKeyE2 command Command (0Eh), Parameter1 (key number); Loads a MIFARE Classic key for authentication from the EEPROM into the crypto 1 unit. Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MIFARE Classic key area. 7.10.3.14 StoreKeyE2 command Command (0Fh), Parameter1 (KeyNr), Parameter2(keybyte1), Parameter3(keybyte2), Parameter4(keybyte3), Parameter5(keybyte4), Parameter6(keybyte5), Parameter7 (keybyte6); Stores MIFARE Classic keys into the EEPROM. The key number parameter indicates the first key (n) in the MKA that will be written. If more than one MIFARE Classic key is available in the FIFO then the next key (n+1) will be written until the FIFO is empty. If an incomplete key (less than 6 bytes) is written into the FIFO, this key will be ignored and will remain in the FIFO. Abort condition: Insufficient parameter in FIFO; KeyNr is outside the MKA; MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 53 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 7.10.3.15 GetRNR command Command (1Ch); This command is reading Random Numbers from the random number generator of the MFRC631. The Random Numbers are copied to the FIFO until the FIFO is full. 7.10.3.16 SoftReset command Command (1Fh); This command is performing a soft reset. Triggered by this command all the default values for the register setting will be read from the EEPROM and copied into the register set. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 54 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8 MFRC631 registers 8.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described in Table 40. Table 41. Behavior of register bits and their designation Abbreviation Behavior Description r/w read and write These bits can be written and read via the host interface. Since they are used only for control purposes, the content is not influenced by the state machines but can be read by internal state machines. dy dynamic These bits can be written and read via the host interface. They can also be written automatically by internal state machines, for example Command register changes its value automatically after the execution of the command. r read only These register bits indicates hold values which are determined by internal states only. w write only Reading these register bits always returns zero. RFU - These bits are reserved for future use and must not be changed. In case of a required write access, it is recommended to write a logic 0. 8.2 MFRC631 registers overview The following table gives an overview on the registers which can be modified by the host. Please note that not all registers available for the CLRC663 are available on the MFRC631. Table 42. MFRC631 registers overview Address Register name Function 00h Command Starts and stops command execution 01h HostCtrl Host control register 02h FIFOControl Control register of the FIFO 03h WaterLevel Level of the FIFO underflow and overflow warning 04h FIFOLength Length of the FIFO 05h FIFOData Data In/Out exchange register of FIFO buffer 06h IRQ0 Interrupt register 0 07h IRQ1 Interrupt register 1 08h IRQ0En Interrupt enable register 0 09h IRQ1En Interrupt enable register 1 0Ah Error Error bits showing the error status of the last command execution 0Bh Status Contains status of the communication MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 55 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Address Register name Function 0Ch RxBitCtrl Control register for anticollision adjustments for bit oriented protocols 0Dh RxColl Collision position register 0Eh TControl Control of Timer 0..3 0Fh T0Control Control of Timer0 10h T0ReloadHi High register of the reload value of Timer0 11h T0ReloadLo Low register of the reload value of Timer0 12h T0CounterValHi Counter value high register of Timer0 13h T0CounterValLo Counter value low register of Timer0 14h T1Control Control of Timer1 15h T1ReloadHi High register of the reload value of Timer1 16h T1ReloadLo Low register of the reload value of Timer1 17h T1CounterValHi Counter value high register of Timer1 18h T1CounterValLo Counter value low register of Timer1 19h T2Control Control of Timer2 1Ah T2ReloadHi High byte of the reload value of Timer2 1Bh T2ReloadLo Low byte of the reload value of Timer2 1Ch T2CounterValHi Counter value high byte of Timer2 1Dh T2CounterValLo Counter value low byte of Timer2 1Eh T3Control Control of Timer3 1Fh T3ReloadHi High byte of the reload value of Timer3 20h T3ReloadLo Low byte of the reload value of Timer3 21h T3CounterValHi Counter value high byte of Timer3 22h T3CounterValLo Counter value low byte of Timer3 23h T4Control Control of Timer4 24h T4ReloadHi High byte of the reload value of Timer4 25h T4ReloadLo Low byte of the reload value of Timer4 26h T4CounterValHi Counter value high byte of Timer4 27h T4CounterValLo Counter value low byte of Timer4 28h DrvMod Driver mode register 29h TxAmp Transmitter amplifier register 2Ah DrvCon Driver configuration register 2Bh Txl Transmitter register 2Ch TxCrcPreset Transmitter CRC control register, preset value 2Dh RxCrcPreset Receiver CRC control register, preset value 2Eh TxDataNum Transmitter data number register 2Fh TxModWidth Transmitter modulation width register 30h TxSym10BurstLen Transmitter symbol 1 + symbol 0 burst length register MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 56 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Address Register name Function 31h TXWaitCtrl Transmitter wait control 32h TxWaitLo Transmitter wait low 33h FrameCon Transmitter frame control 34h RxSofD Receiver start of frame detection 35h RxCtrl Receiver control register 36h RxWait Receiver wait register 37h RxThreshold Receiver threshold register 38h Rcv Receiver register 39h RxAna Receiver analog register 3Ah MFRC63102: RFU - MFRC63103: LPCD options LPCD settings only available for MFRC63103 3Bh SerialSpeed Serial speed register 3Ch LFO_Trimm Low-power oscillator trimming register 3Dh PLL_Ctrl IntegerN PLL control register, for microcontroller clock output adjustment 3Eh PLL_DivOut IntegerN PLL control register, for microcontroller clock output adjustment 3Fh LPCD_QMin Low-power card detection Q channel minimum threshold 40h LPCD_QMax Low-power card detection Q channel maximum threshold 41h LPCD_IMin Low-power card detection I channel minimum threshold 42h LPCD_I_Result Low-power card detection I channel result register 43h LPCD_Q_Result Low-power card detection Q channel result register 44h PadEn PIN enable register 45h PadOut PIN out register 46h PadIn PIN in register 47h SigOut Enables and controls the SIGOUT Pin 48h-5Fh RFU - 7Fh Version Version and subversion register 8.3 Command configuration 8.3.1 Command Starts and stops command execution. Table 43. Command register (address 00h) Bit Symbol MFRC631 Product data sheet COMPANY PUBLIC 7 6 5 Standby Modem Off RFU 4 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 3 2 1 0 Command (c) NXP B.V. 2018. All rights reserved. 57 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit 7 6 5 Access rights dy r/w - 4 3 2 1 0 dy Table 44. Command bits Bit Symbol Description 7 Standby Set to 1, the IC is entering power-down mode. 6 ModemOff Set to logic 1, the receiver and the transmitter circuit is powering down. 5 RFU - 4 to 0 Command Defines the actual command for the MFRC631. 8.4 SAM configuration register 8.4.1 HostCtrl Via the HostCtrl Register the interface access right can be controlled Table 45. HostCtrl register (address 01h); Bit 7 6 5 4 3 2 1 0 Symbol RegEn BusHost BusSAM RFU SAMInterface SAMInterface RFU RFU Access rights dy r/w r/w - r/w r/w - - Table 46. HostCtrl bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 RegEn If this bit is set to logic 1, the register HostCtrl_reg can be changed at the next register access. The next write access clears this bit automatically. 6 BusHost Set to logic 1, the bus is controlled by the host. This bit cannot be set together with the bit BusSAM. This bit can only be set if the bit RegEn is previously set. 5 BusSAM Set to logic 1, the bus is controlled by the SAM. This bit cannot be set together with BusHost. This bit can only be set if the bit RegEn is previously set. 4 RFU - 3 to 2 SAMInterface 0h:SAM Interface switched off 1h:SAM Interface SPI active 2 2h:SAM Interface I CL active 2 3h:SAM Interface I C active 1 to 0 RFU - All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 58 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.5 FIFO configuration register 8.5.1 FIFOControl FIFOControl defines the characteristics of the FIFO Table 47. FIFOControl register (address 02h); Bit 7 6 5 4 3 2 1 0 Symbol FIFOSize HiAlert LoAlert FIFOFlush RFU WaterLe velExtBit FIFOLengthExtBits Access rights r/w r r w - r/w r Table 48. FIFOControl bits Bit Symbol Description 7 FIFOSize Set to logic 1, FIFO size is 255 bytes; Set to logic 0, FIFO size is 512 bytes. It is recommended to change the FIFO size only, when the FIFO content had been cleared. 6 HiAlert Set to logic 1, when the number of bytes stored in the FIFO buffer fulfils the following equation: HiAlert = (FIFOSize - FIFOLength) <= WaterLevel 5 LoAlert Set to logic 1, when the number of bytes stored in the FIFO buffer fulfils the following conditions: LoAlert =1 if FIFOLength <= WaterLevel 4 FIFOFlush Set to logic 1 clears the FIFO buffer. Reading this bit will always return 0 3 RFU - 2 WaterLevelExtBit Defines the bit 8 (MSB) for the waterlevel (extension of register WaterLevel). This bit is only evaluated in the 512-byte FIFO mode. Bits 7..0 are defined in register WaterLevel. 1 to 0 FIFOLengthExtBits Defines the bit9 (MSB) and bit8 for the FIFO length (extension of FIFOLength). These two bits are only evaluated in the 512-byte FIFO mode, The bits 7..0 are defined in register FIFOLength. 8.5.2 WaterLevel Defines the level for FIFO under- and overflow warning levels.This register is extended by 1 bit in FIFOControl in case the 512-byte FIFO mode is activated by setting bit FIFOControl.FIFOSize. Table 49. WaterLevel register (address 03h); Bit 7 6 5 Symbol Access rights 4 3 2 1 0 r/w r/w r/w WaterLevelBits r/w MFRC631 Product data sheet COMPANY PUBLIC r/w r/w r/w r/w All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 59 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 50. WaterLevel bits Bit Symbol Description 7 to 0 WaterLevelBits Sets a level to indicate a FIFO-buffer state which can be read from bits HighAlert and LowAlert in the FifoControl. In 512-byte FIFO mode, the register is extended by bit WaterLevelExtBit in the FIFOControl. This functionality can be used to avoid a FIFO buffer overflow or underflow: The bit HiAlert bit in FIFO Control is read logic 1, if the number of bytes in the FIFO-buffer is equal or less than the number defined by the waterlevel configuration. The bit LoAlert bit in FIFO control is read logic 1, if the number of bytes in the FIFO buffer is equal or less than the number defined by the waterlevel configuration. Note: For the calculation of HiAlert and LoAlert see register description of these bits (Section 8.4.1 "FIFOControl"). 8.5.3 FIFOLength Number of bytes in the FIFO buffer. In 512-byte mode this register is extended by FIFOControl.FifoLength. Table 51. FIFOLength register (address 04h); reset value: 00h Bit 7 6 5 4 3 Symbol FIFOLength Access rights dy 2 1 0 Table 52. FIFOLength bits Bit 7 to 0 Symbol Description FIFOLength Indicates the number of bytes in the FIFO buffer. In 512-byte mode this register is extended by the bits FIFOLength in the FIFOControl register. Writing to the FIFOData register increments, reading decrements the number of available bytes in the FIFO. 8.5.4 FIFOData In- and output of FIFO buffer. Contrary to any read/write access to other addresses, reading or writing to the FIFO address does not increment the address pointer. Writing to the FIFOData register increments, reading decrements the number of bytes present in the FIFO. Table 53. FIFOData register (address 05h); Bit 7 6 5 Symbol Access rights MFRC631 Product data sheet COMPANY PUBLIC 4 3 2 1 0 dy dy dy dy FIFOData dy dy dy dy All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 60 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 54. FIFOData bits Bit Symbol Description 7 to 0 FIFOData Data input and output port for the internal FIFO buffer. Refer to Section 7.5 "Buffer". 8.6 Interrupt configuration registers The Registers IRQ0 register and IRQ1 register implement a special functionality to avoid the unintended modification of bits. The mechanism of changing register contents requires the following consideration: IRQ(x).Set indicates, if a set bit on position 0 to 6 shall be cleared or set. Depending on the content of IRQ(x).Set, a write of a 1 to positions 0 to 6 either clears or sets the corresponding bit. With this register the application can modify the interrupt status which is maintained by the MFRC631. Bit 7 indicates, if the intended modification is a setting or clearance of a bit. Any 1 written to a bit position 6...0 will trigger the setting or clearance of this bit as defined by bit 7. Example: writing FFh sets all bits 6..0, writing 7Fh clears all bits 6..0 of the interrupt request register 8.6.1 IRQ0 register Interrupt request register 0. Table 55. IRQ0 register (address 06h); reset value: 00h Bit 7 6 5 4 3 2 1 0 Symbol Set Hi AlertIRQ Lo AlertIRQ IdleIRQ TxIRQ RxIRQ ErrIRQ RxSOF IRQ Access rights w dy dy dy dy dy dy dy Table 56. IRQ0 bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 Set 1: writing a 1 to a bit position 6..0 sets the interrupt request 0: Writing a 1 to a bit position 6..0 clears the interrupt request 6 HiAlerIRQ Set, when bit HiAlert in register Status1Reg is set. In opposition to HiAlert, HiAlertIRQ stores this event. 5 LoAlertIRQ Set, when bit LoAlert in register Status1 is set. In opposition to LoAlert, LoAlertIRQ stores this event. 4 IdleIRQ Set, when a command terminates by itself e.g. when the Command changes its value from any command to the Idle command. If an unknown command is started, the Command changes its content to the idle state and the bit IdleIRQ is set. Starting the Idle command by the Controller does not set bit IdleIRQ. . 3 TxIRQ Set, when data transmission is completed, which is immediately after the last bit is sent. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 61 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 2 RxIRQ Set, when the receiver detects the end of a data stream. Note: This flag is no indication that the received data stream is correct. The error flags have to be evaluated to get the status of the reception. 1 ErrIRQ Set, when the one of the following errors is set: FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr. 0 RxSOFlrq Set, when a SOF or a subcarrier is detected. 8.6.2 IRQ1 register Interrupt request register 1. Table 57. IRQ1 register (address 07h) Bit 7 Symbol Set Access rights w 6 5 4 GlobalIRQ LPCD_IRQ Timer4IRQ dy dy dy 3 2 1 0 Timer3IRQ Timer2IRQ Timer1IRQ Timer0IRQ dy dy dy dy Table 58. IRQ1 bits Bit Symbol Description 7 Set 1: writing a 1 to a bit position 5..0 sets the interrupt request 0: Writing a 1 to a bit position 5..0 clears the interrupt request 6 GlobalIRQ Set, if an enabled IRQ occurs. 5 LPCD_IRQ Set if a card is detected in Low-power card detection sequence. 4 Timer4IRQ Set to logic 1 when Timer4 has an underflow. 3 Timer3IRQ Set to logic 1 when Timer3 has an underflow. 2 Timer2IRQ Set to logic 1 when Timer2 has an underflow. 1 Timer1IRQ Set to logic 1 when Timer1 has an underflow. 0 Timer0IRQ Set to logic 1 when Timer0 has an underflow. 8.6.3 IRQ0En register Interrupt request enable register for IRQ0. This register allows to define if an interrupt request is processed by the MFRC631. Table 59. IRQ0En register (address 08h) Bit 7 6 Symbol IRQ_Inv Hi AlertIRQEn Access rights r/w r/w MFRC631 Product data sheet COMPANY PUBLIC 5 4 LoAlertIRQEn IdleIRQEn r/w r/w 3 2 1 0 TxIRQEn RxIRQEn ErrIRQEn RxSOF IRQEn r/w r/w r/w r/w All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 62 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 60. IRQ0En bits Bit Symbol Description 7 IRQ_Inv Set to one the signal of the IRQ pin is inverted 6 Hi AlerIRQEn Set to logic 1, it allows the High Alert interrupt Request (indicated by the bit HiAlertIRQ) to be propagated to the GlobalIRQ 5 Lo AlertIRQEn Set to logic 1, it allows the Low Alert Interrupt Request (indicated by the bit LoAlertIRQ) to be propagated to the GlobalIRQ 4 IdleIRQEn Set to logic 1, it allows the Idle interrupt request (indicated by the bit IdleIRQ) to be propagated to the GlobalIRQ 3 TxIRQEn Set to logic 1, it allows the transmitter interrupt request (indicated by the bit TxtIRQ) to be propagated to the GlobalIRQ 2 RxIRQEn Set to logic 1, it allows the receiver interrupt request (indicated by the bit RxIRQ) to be propagated to the GlobalIRQ 1 ErrIRQEn Set to logic 1, it allows the Error interrupt request (indicated by the bit ErrorIRQ) to be propagated to the GlobalIRQ 0 RxSOFIRQEn Set to logic 1, it allows the RxSOF interrupt request (indicated by the bit RxSOFIRQ) to be propagated to the GlobalIRQ 8.6.4 IRQ1En Interrupt request enable register for IRQ1. Table 61. IRQ1EN register (address 09h); Bit 7 6 5 Symbol IRQPushPull IRQPinEn LPCD_IRQEn Access rights r/w r/w r/w 4 3 2 1 0 Timer4 IRQEn Timer3 IRQEn Timer2 IRQEn Timer1 IRQEn Timer0 IRQEn r/w r/w r/w r/w r/w Table 62. IRQ1EN bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 IRQPushPull Set to 1 the IRQ-pin acts as PushPull pin, otherwise it acts as OpenDrain pin 6 IRQPinEN Set to logic 1, it allows the global interrupt request (indicated by the bit GlobalIRQ) to be propagated to the interrupt pin 5 LPCD_IRQEN Set to logic 1, it allows the LPCDinterrupt request (indicated by the bit LPCDIRQ) to be propagated to the GlobalIRQ 4 Timer4IRQEn Set to logic 1, it allows the Timer4 interrupt request (indicated by the bit Timer4IRQ) to be propagated to the GlobalIRQ 3 Timer3IRQEn Set to logic 1, it allows the Timer3 interrupt request (indicated by the bit Timer3IRQ) to be propagated to the GlobalIRQ 2 Timer2IRQEn Set to logic 1, it allows the Timer2 interrupt request (indicated by the bit Timer2IRQ) to be propagated to the GlobalIRQ 1 Timer1IRQEn Set to logic 1, it allows the Timer1 interrupt request (indicated by the bit Timer1IRQ) to be propagated to the GlobalIRQ All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 63 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 0 Timer0IRQEn Set to logic 1, it allows the Timer0 interrupt request (indicated by the bit Timer0IRQ) to be propagated to the GlobalIRQ 8.7 Contactless interface configuration registers 8.7.1 Error Error register. Table 63. Error register (address 0Ah) Bit 7 6 5 4 3 2 1 0 Symbol EE_Err FiFoWrErr FIFOOvl MinFrameErr NoDataErr CollDet ProtErr IntegErr Access rights dy dy dy dy dy dy dy dy Table 64. Error bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 EE_Err An error appeared during the last EEPROM command. For details see the descriptions of the EEPROM commands 6 FIFOWrErr Data was written into the FIFO, during a transmission of a possible CRC, during "RxWait", "Wait for data" or "Receiving" state, or during an authentication command. The Flag is cleared when a new CL command is started. If RxMultiple is active, the flag is cleared after the error flags have been written to the FIFO. 5 FIFOOvl Data is written into the FIFO when it is already full. The data that is already in the FIFO will remain untouched. All data that is written to the FIFO after this Flag is set to 1 will be ignored. 4 Min FrameErr A valid SOF was received, but afterwards less then 4 bits of data were received. Note: Frames with less than 4 bits of data are automatically discarded and the RxDecoder stays enabled. Furthermore no RxIRQ is set. The same is valid for less than 3 Bytes if the EMD suppression is activated Note: MinFrameErr is automatically cleared at the start of a receive or transceive command. In case of a transceive command, it is cleared at the start of the receiving phase ("Wait for data" state) 3 NoDataErr Data should be sent, but no data is in FIFO 2 CollDet A collision has occurred. The position of the first collision is shown in the register RxColl. Note: CollDet is automatically cleared at the start of a receive or transceive command. In case of a transceive command, it is cleared at the start of the receiving phase ("Wait for data" state). Note: If a collision is part of the defined EOF symbol, CollDet is not set to 1. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 64 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 1 ProtErr A protocol error has occurred. A protocol error can be a wrong stop bit, a missing or wrong ISO/IEC14443B EOF or SOF or a wrong number of received data bytes. When a protocol error is detected, data reception is stopped. Note: ProtErr is automatically cleared at start of a receive or transceive command. In case of a transceive command, it is cleared at the start of the receiving phase ("Wait for data" state). Note: When a protocol error occurs the last received data byte is not written into the FIFO. 0 IntegErr A data integrity error has been detected. Possible cause can be a wrong parity or a wrong CRC. In case of a data integrity error the reception is continued. Note: IntegErr is automatically cleared at start of a Receive or Transceive command. In case of a Transceive command, it is cleared at the start of the receiving phase ("Wait for data" state). Note: If the NoColl bit is set, also a collision is setting the IntegErr. 8.7.2 Status Status register. Table 65. Status register (address 0Bh) Bit 7 6 5 4 3 2 1 Symbol - - Crypto1On - - ComState Access rights RFU RFU dy RFU RFU r 0 Table 66. Status bits Bit Symbol Description 7 to 6 - RFU 5 Crypto1On Indicates if the MIFARE Classic Crypto is on. Clearing this bit is switching the MIFARE Classic Crypto off. The bit can only be set by the MFAuthent command. 4 to 3 - RFU 2 to 0 ComState ComState shows the status of the transmitter and receiver state machine: 000b ... Idle 001b ... TxWait 011b ... Transmitting 101b ... RxWait 110b ... Wait for data 111b ... Receiving 100b ... not used MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 65 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.7.3 RxBitCtrl Receiver control register. Table 67. RxBitCtrl register (address 0Ch); Bit 7 6 Symbol ValuesAfterColl Access rights r/w 5 4 3 r/w 1 NoColl RxAlign r/w 2 r/w 0 RxLastBits r/w w w w Table 68. RxBitCtrl bits Bit Symbol Description 7 ValuesAfter Coll If cleared, every received bit after a collision is replaced by a zero. This function is needed for ISO/IEC14443 anticollision 6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position length for the first bit received to be stored. Further received bits are stored at the following bit positions. Example: RxAlign = 0h - the LSB of the received bit is stored at bit 0, the second received bit is stored at bit position 1. RxAlign = 1h - the LSB of the received bit is stored at bit 1, the second received bit is stored at bit position 2. RxAlign = 7h - the LSB of the received bit is stored at bit 7, the second received bit is stored in the following byte at position 0. Note: If RxAlign = 0, data is received byte-oriented, otherwise bitoriented. 3 NoColl If this bit is set, a collision will result in an IntegErr 2 to 0 RxLastBits Defines the number of valid bits of the last data byte received in bitoriented communications. If zero the whole byte is valid. Note: These bits are set by the RxDecoder in a bit-oriented communication at the end of the communication. They are reset at start of reception. 8.7.4 RxColl Receiver collision register. Table 69. RxColl register (address 0Dh); Bit 7 6 5 4 3 2 Symbol CollPosValid CollPos Access rights r r MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 1 0 (c) NXP B.V. 2018. All rights reserved. 66 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 70. RxColl bits Bit Symbol Description 7 CollPos Valid If set to 1, the value of CollPos is valid. Otherwise no collision is detected or the position of the collision is out of the range of bits CollPos. 6 to 0 CollPos These bits show the bit position of the first detected collision in a received frame (only data bits are interpreted). CollPos can only be displayed for the first 8 bytes of a data stream. Example: 00h indicates a bit collision in the 1st bit 01h indicates a bit collision in the 2nd bit 08h indicates a bit collision in the 9th bit (1st bit of 2nd byte) 3Fh indicates a bit collision in the 64th bit (8th bit of the 8th byte) These bits shall only be interpreted in Passive communication mode at 106 kbit/s or ISO/IEC 14443 type A and read/write mode for MIFARE Classic if bit CollPosValid is set. Note: If RxBitCtrl.RxAlign is set to a value different to 0, this value is included in the CollPos. Example: RxAlign = 4h, a collision occurs in the 4th received bit (which is the last bit of that UID byte). The CollPos = 7h in this case. 8.8 Timer configuration registers 8.8.1 TControl Control register of the timer section. The TControl implements a special functionality to avoid the not intended modification of bits. Bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified. Example: writing FFh sets all bits 7..4, writing F0h does not change any of the bits 7..4 Table 71. TControl register (address 0Eh) Bit Symbol Access rights 7 6 T3Running T2Running dy dy 5 4 3 2 1 0 T1Running T0Running T3Start StopNow T2Start StopNow T1Start StopNow T0Start StopNow dy dy w w w w Table 72. TControl bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 T3Running Indicates Timer3 is running.If the bit T3startStopNow is set/reset, this bit and the timer can be started/stopped 6 T2Running Indicates Timer2 is running. If the bit T2startStopNow is set/reset, this bit and the timer can be started/stopped 5 T1Running Indicates tTmer1 is running. If the bit T1startStopNow is set/reset, this bit and the timer can be started/stopped All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 67 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 4 T0Running Indicates Timer0 is running. If the bit T0startStopNow is set/reset, this bit and the timer can be started/stopped 3 T3StartStop Now The bit 7 of TControl T3Running can be modified if set 2 T2StartStop Now The bit 6of TControl T2Running can be modified if set 1 T1StartStop Now The bit 5of TControl T1Running can be modified if set 0 T0StartStop Now The bit 4 of TControl T0Running can be modified if set 8.8.2 T0Control Control register of the Timer0. Table 73. T0Control register (address 0Fh); Bit 7 6 Symbol T0StopRx - Access rights r/w RFU 5 4 3 2 1 0 T0Start T0AutoRestart - T0Clk r/w r/w RFU r/w Table 74. T0Control bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 T0StopRx If set, the timer stops immediately after receiving the first 4 bits. If cleared the timer does not stop automatically. Note: If LFO Trimming is selected by T0Start, this bit has no effect. 6 - RFU 5 to 4 T0Start 00b: The timer is not started automatically 01 b: The timer starts automatically at the end of the transmission 10 b: Timer is used for LFO trimming without underflow (Start/Stop on PosEdge) 11 b: Timer is used for LFO trimming with underflow (Start/Stop on PosEdge) 3 T0AutoRestart 1: the timer automatically restarts its count-down from T0ReloadValue, after the counter value has reached the value zero. 0: the timer decrements to zero and stops. The bit Timer1IRQ is set to logic 1 when the timer underflows. 2 - RFU 1 to 0 T0Clk 00 b: The timer input clock is 13.56 MHz. 01 b: The timer input clock is 211,875 kHz. 10 b: The timer input clock is an underflow of Timer2. 11 b: The timer input clock is an underflow of Timer1. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 68 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.8.2.1 T0ReloadHi High byte reload value of the Timer0. Table 75. T0ReloadHi register (address 10h); Bit 7 6 5 4 3 Symbol T0Reload Hi Access rights r/w 2 1 0 Table 76. T0ReloadHi bits Bit Symbol Description 7 to 0 T0ReloadHi Defines the high byte of the reload value of the timer. With the start event the timer loads the value of the registers T0ReloadValHi, T0ReloadValLo. Changing this register affects the timer only at the next start event. 8.8.2.2 T0ReloadLo Low byte reload value of the Timer0. Table 77. T0ReloadLo register (address 11h); Bit 7 6 5 4 3 Symbol T0ReloadLo Access rights r/w 2 1 0 Table 78. T0ReloadLo bits Bit Symbol Description 7 to0 T0ReloadLo Defines the low byte of the reload value of the timer. With the start event the timer loads the value of the T0ReloadValHi, T0ReloadValLo. Changing this register affects the timer only at the next start event. 8.8.2.3 T0CounterValHi High byte of the counter value of Timer0. Table 79. T0CounterValHi register (address 12h) Bit 7 6 5 4 3 Symbol T0CounterValHi Access rights dy MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 2 1 0 (c) NXP B.V. 2018. All rights reserved. 69 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 80. T0CounterValHi bits Bit Symbol Description 7to0 T0Counter ValHi High byte value of the Timer0. This value shall not be read out during reception. 8.8.2.4 T0CounterValLo Low byte of the counter value of Timer0. Table 81. T0CounterValLo register (address 13h) Bit 7 6 5 4 3 Symbol T0CounterValLo Access rights dy 2 1 0 Table 82. T0CounterValLo bits Bit Symbol Description 7 to 0 T0CounterValLo Low byte value of the Timer0. This value shall not be read out during reception. 8.8.2.5 T1Control Control register of the Timer1. Table 83. T1Control register (address 14h); Bit 7 6 Symbol T1StopRx - Access rights r/w RFU 5 4 3 2 1 0 T1Start T1AutoRestart - T1Clk r/w r/w RFU r/w Table 84. T1Control bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 T1StopRx If set, the timer stops after receiving the first 4 bits. If cleared, the timer is not stopped automatically. Note: If LFO trimming is selected by T1start, this bit has no effect. 6 - RFU 5 to 4 T1Start 00b: The timer is not started automatically 01 b: The timer starts automatically at the end of the transmission 10 b: Timer is used for LFO trimming without underflow (Start/Stop on PosEdge) 11 b: Timer is used for LFO trimming with underflow (Start/Stop on PosEdge) All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 70 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 3 T1AutoRestart Set to logic 1, the timer automatically restarts its countdown from T1ReloadValue, after the counter value has reached the value zero. Set to logic 0 the timer decrements to zero and stops. The bit Timer1IRQ is set to logic 1 when the timer underflows. 2 - RFU 1 to 0 T1Clk 00 b: The timer input clock is 13.56 MHz 01 b: The timer input clock is 211,875 kHz. 10 b: The timer input clock is an underflow of Timer0 11 b: The timer input clock is an underflow of Timer2 8.8.2.6 T1ReloadHi High byte (MSB) reload value of the Timer1. Table 85. T0ReloadHi register (address 15h) Bit 7 6 5 4 3 Symbol T1ReloadHi Access rights r/w 2 1 0 Table 86. T1ReloadHi bits Bit Symbol Description 7 to 0 T1ReloadHi Defines the high byte reload value of the Timer 1. With the start event the timer loads the value of the T1ReloadValHi and T1ReloadValLo. Changing this register affects the Timer only at the next start event. 8.8.2.7 T1ReloadLo Low byte (LSB) reload value of the Timer1. Table 87. T1ReloadLo register (address 16h) Bit 7 6 5 4 3 Symbol T1ReloadLo Access rights r/w 2 1 0 Table 88. T1ReloadValLo bits Bit Symbol Description 7 to 0 T1ReloadLo Defines the low byte of the reload value of the Timer1. Changing this register affects the timer only at the next start event. 8.8.2.8 T1CounterValHi High byte (MSB) of the counter value of byte Timer1. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 71 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 89. T1CounterValHi register (address 17h) Bit 7 6 5 4 3 Symbol T1CounterValHi Access rights dy 2 1 0 1 0 1 0 Table 90. T1CounterValHi bits Bit Symbol Description 7 to 0 T1Counter ValHi High byte of the current value of the Timer1. This value shall not be read out during reception. 8.8.2.9 T1CounterValLo Low byte (LSB) of the counter value of byte Timer1. Table 91. T1CounterValLo register (address 18h) Bit 7 6 5 4 3 Symbol T1CounterValLo Access rights dy 2 Table 92. T1CounterValLo bits Bit Symbol Description 7 to 0 T1Counter ValLo Low byte of the current value of the counter 1. This value shall not be read out during reception. 8.8.2.10 T2Control Control register of the Timer2. Table 93. T2Control register (address 19h) Bit 7 6 Symbol T2StopRx - Access rights r/w RFU 5 4 3 2 T2Start T2AutoRestart - T2Clk r/w r/w RFU r/w Table 94. T2Control bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 T2StopRx If set the timer stops immediately after receiving the first 4 bits. If cleared indicates, that the timer is not stopped automatically. Note: If LFO Trimming is selected by T2Start, this bit has no effect. 6 - RFU All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 72 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 5 to 4 T2Start 00 b: The timer is not started automatically. 01 b: The timer starts automatically at the end of the transmission. 10 b: Timer is used for LFO trimming without underflow (Start/Stop on PosEdge). 11 b: Timer is used for LFO trimming with underflow (Start/Stop on PosEdge). 3 T2AutoRestart Set to logic 1, the timer automatically restarts its countdown from T2ReloadValue, after the counter value has reached the value zero. Set to logic 0 the timer decrements to zero and stops. The bit Timer2IRQ is set to logic 1 when the timer underflows 2 - RFU 1 to 0 T2Clk 00 b: The timer input clock is 13.56 MHz. 01 b: The timer input clock is 212 kHz. 10 b: The timer input clock is an underflow of Timer0 11b: The timer input clock is an underflow of Timer1 8.8.2.11 T2ReloadHi High byte of the reload value of Timer2. Table 95. T2ReloadHi register (address 1Ah) Bit 7 6 5 4 3 Symbol T2ReloadHi Access rights r/w 2 1 0 Table 96. T2Reload bits Bit Symbol Description 7 to 0 T2ReloadHi Defines the high byte of the reload value of the Timer2. With the start event the timer load the value of the T2ReloadValHi and T2ReloadValLo. Changing this register affects the timer only at the next start event. 8.8.2.12 T2ReloadLo Low byte of the reload value of Timer2. Table 97. T2ReloadLo register (address 1Bh) Bit 7 6 5 4 3 Symbol T2ReloadLo Access rights r/w MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 2 1 0 (c) NXP B.V. 2018. All rights reserved. 73 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 98. T2ReloadLo bits Bit Symbol Description 7 to 0 T2ReloadLo Defines the low byte of the reload value of the Timer2. With the start event the timer load the value of the T2ReloadValHi and T2RelaodVaLo. Changing this register affects the timer only at the next start event. 8.8.2.13 T2CounterValHi High byte of the counter register of Timer2. Table 99. T2CounterValHi register (address 1Ch) Bit 7 6 5 4 3 Symbol T2CounterValHi Access rights dy 2 1 0 1 0 Table 100. T2CounterValHi bits Bit Symbol Description 7 to 0 T2Counter ValHi High byte current counter value of Timer2. This value shall not be read out during reception. 8.8.2.14 T2CounterValLoReg Low byte of the current value of Timer 2. Table 101. T2CounterValLo register (address 1Dh) Bit 7 6 5 4 3 Symbol T2CounterValLo Access rights dy 2 Table 102. T2CounterValLo bits Bit Symbol Description 7 to 0 T2Counter ValLo Low byte of the current counter value of Timer1Timer2. This value shall not be read out during reception. 8.8.2.15 T3Control Control register of the Timer 3. Table 103. T3Control register (address 1Eh) Bit 7 6 Symbol T3StopRx - Access rights r/w RFU MFRC631 Product data sheet COMPANY PUBLIC 5 4 3 2 T3Start T3AutoRestart - T3Clk r/w r/w RFU r/w All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 1 0 (c) NXP B.V. 2018. All rights reserved. 74 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 104. T3Control bits Bit Symbol Description 7 T3StopRx If set, the timer stops immediately after receiving the first 4 bits. If cleared, indicates that the timer is not stopped automatically. Note: If LFO Trimming is selected by T3Start, this bit has no effect. 6 - RFU 5 to 4 T3Start 00b - timer is not started automatically 01 b - timer starts automatically at the end of the transmission 10 b - timer is used for LFO trimming without underflow (Start/Stop on PosEdge) 11 b - timer is used for LFO trimming with underflow (Start/Stop on PosEdge). 3 T3AutoRestart Set to logic 1, the timer automatically restarts its countdown from T3ReloadValue, after the counter value has reached the value zero. Set to logic 0 the timer decrements to zero and stops. The bit Timer1IRQ is set to logic 1 when the timer underflows. 2 - RFU 1 to 0 T3Clk 00 b - the timer input clock is 13.56 MHz. 01 b - the timer input clock is 211,875 kHz. 10 b - the timer input clock is an underflow of Timer0 11 b - the timer input clock is an underflow of Timer1 8.8.2.16 T3ReloadHi High byte of the reload value of Timer3. Table 105. T3ReloadHi register (address 1Fh); Bit 7 6 5 4 3 Symbol T3ReloadHi Access rights r/w 2 1 0 Table 106. T3ReloadHi bits Bit Symbol Description 7 to 0 T3ReloadHi Defines the high byte of the reload value of the Timer3. With the start event the timer load the value of the T3ReloadValHi and T3ReloadValLo. Changing this register affects the timer only at the next start event. 8.8.2.17 T3ReloadLo Low byte of the reload value of Timer3. Table 107. T3ReloadLo register (address 20h) Bit Symbol MFRC631 Product data sheet COMPANY PUBLIC 7 6 5 4 3 2 1 0 T3ReloadLo All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 75 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit 7 6 5 4 Access rights 3 2 1 0 r/w Table 108. T3ReloadLo bits Bit Symbol Description 7 to 0 T3ReloadLo Defines the low byte of the reload value of Timer3. With the start event the timer load the value of the T3ReloadValHi and T3RelaodValLo. Changing this register affects the timer only at the next start event. 8.8.2.18 T3CounterValHi High byte of the current counter value the 16-bit Timer3. Table 109. T3CounterValHi register (address 21h) Bit 7 6 5 4 3 Symbol T3CounterValHi Access rights dy 2 1 0 1 0 Table 110. T3CounterValHi bits Bit Symbol Description 7 to 0 T3Counter ValHi High byte of the current counter value of Timer3. This value shall not be read out during reception. 8.8.2.19 T3CounterValLo Low byte of the current counter value the 16-bit Timer3. Table 111. T3CounterValLo register (address 22h) Bit 7 6 5 4 3 Symbol T3CounterValLo Access rights dy 2 Table 112. T3CounterValLo bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 to 0 T3Counter ValLo Low byte current counter value of Timer3. This value shall not be read out during reception. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 76 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.8.2.20 T4Control The wake-up timer T4 activates the system after a given time. If enabled, it can start the low power card detection function. Table 113. T4Control register (address 23h) Bit 7 6 5 4 3 2 1 0 Symbol T4Running T4Start StopNow T4Auto Trimm T4Auto LPCD T4Auto Restart T4AutoWakeUp T4Clk Access rights dy w r/w r/w r/w r/w r/w Table 114. T4Control bits Bit Symbol Description 7 T4Running Shows if the timer T4 is running. If the bit T4StartStopNow is set, this bit and the timer T4 can be started/stopped. 6 T4Start StopNow if set, the bit T4Running can be changed. 5 T4AutoTrimm If set to one, the timer activates an LFO trimming procedure when it underflows. For the T4AutoTrimm function, at least one timer (T0 to T3) has to be configured properly for trimming (T3 is not allowed if T4AutoLPCD is set in parallel). 4 T4AutoLPCD If set to one, the timer activates a low-power card detection sequence. If a card is detected an interrupt request is raised and the system remains active if enabled. If no card is detected the MFRC631 enters the Power down mode if enabled. The timer is automatically restarted (no gap). Timer 3 is used to specify the time where the RF field is enabled to check if a card is present. Therefor you may not use Timer 3 for T4AutoTrimm in parallel. 3 T4AutoRestart Set to logic 1, the timer automatically restarts its countdown from T4ReloadValue, after the counter value has reached the value zero. Set to logic 0 the timer decrements to zero and stops. The bit Timer4IRQ is set to logic 1 at timer underflow. 2 T4AutoWakeUp If set, the MFRC631 wakes up automatically, when the timer T4 has an underflow. This bit has to be set if the IC should enter the Power down mode after T4AutoTrimm and/or T4AutoLPCD is finished and no card has been detected. If the IC should stay active after one of these procedures this bit has to be set to 0. 1 to 0 T4Clk 00b - the timer input clock is the LFO clock 01b - the timer input clock is the LFO clock/8 10b - the timer input clock is the LFO clock/16 11b - the timer input clock is the LFO clock/32 8.8.2.21 T4ReloadHi High byte of the reload value of the 16-bit timer 4. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 77 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 115. T4ReloadHi register (address 24h) Bit 7 6 5 4 3 Symbol T4ReloadHi Access rights r/w 2 1 0 Table 116. T4ReloadHi bits Bit Symbol Description 7 to 0 T4ReloadHi Defines high byte of the for the reload value of timer 4. With the start event the timer 4 loads the T4ReloadVal. Changing this register affects the timer only at the next start event. 8.8.2.22 T4ReloadLo Low byte of the reload value of the 16-bit timer 4. Table 117. T4ReloadLo register (address 25h) Bit 7 6 5 4 3 Symbol T4ReloadLo Access rights r/w 2 1 0 Table 118. T4ReloadLo bits Bit Symbol Description 7 to 0 T4ReloadLo Defines the low byte of the reload value of the timer 4. With the start event the timer loads the value of the T4ReloadVal. Changing this register affects the timer only at the next start event. 8.8.2.23 T4CounterValHi High byte of the counter value of the 16-bit timer 4. Table 119. T4CounterValHi register (address 26h) Bit 7 6 5 4 3 Symbol T4CounterValHi Access rights dy 2 1 0 Table 120. T4CounterValHi bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 to 0 T4CounterValHi High byte of the current counter value of timer 4. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 78 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.8.2.24 T4CounterValLo Low byte of the counter value of the 16-bit timer 4. Table 121. T4CounterValLo register (address 27h) Bit 7 6 5 4 3 Symbol T4CounterValLo Access rights dy 2 1 0 Table 122. T4CounterValLo bits Bit Symbol Description 7 to 0 T4CounterValLo Low byte of the current counter value of the timer 4. 8.9 Transmitter configuration registers 8.9.1 TxMode Table 123. DrvMode register (address 28h) Bit 7 6 5 4 3 2 1 Symbol Tx2Inv Tx1Inv - - TxEn TxClk Mode Access rights r/w r/w RFU RFU r/w r/w 0 Table 124. DrvMode bits Bit Symbol Description 7 Tx2Inv Inverts transmitter 2 at TX2 pin 6 Tx1Inv Inverts transmitter 1 at TX1 pin 5 RFU 4 - RFU 3 TxEn If set to 1 both transmitter pins are enabled 2 to 0 TxClkMode Transmitter clock settings (see 8.6.2. Table 27). Codes 011b and 0b110 are not supported. This register defines, if the output is operated in open drain, push-pull, at high impedance or pulled to a fix high or low level. 8.9.2 TxAmp With the set_cw_amplitude register output power can be traded off against power supply rejection. Spending more headroom leads to better power supply rejection ration and better accuracy of the modulation degree. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 79 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus With CwMax set, the voltage of TX1 will be pulled to the maximum possible. This register overrides the settings made by set_cw_amplitude. Table 125. TxAmp register (address 29h) Bit 7 6 5 4 3 2 Symbol set_cw_amplitude - set_residual_carrier Access rights r/w RFU r/w 1 0 Table 126. TxAmp bits Bit Symbol Description 7 to 6 set_cw_amplitude Allows to reduce the output amplitude of the transmitter by a fix value. Four different preset values that are subtracted from TVDD can be selected: 0: TVDD -100 mV 1: TVDD -250 mV 2: TVDD -500 mV 3: TVDD -1000 mV 5 RFU - 4 to 0 set_residual_ carrier Set the residual carrier percentage. refer to Section 7.6.2 8.9.3 TxCon Table 127. TxCon register (address 2Ah) Bit 7 6 5 4 3 2 1 0 Symbol OvershootT2 CwMax TxInv TxSel Access rights r/w r/w r/w r/w Table 128. TxCon bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 to 4 OvershootT2 Specifies the length (number of carrier clocks) of the additional modulation for overshoot prevention. Refer to Section 7.6.2.1 "Overshoot protection" 3 Cwmax Set amplitude of continuous wave carrier to the maximum. If set, set_cw_amplitude in Register TxAmp has no influence on the continuous amplitude. 2 TxInv If set, the resulting modulation signal defined by TxSel is inverted 1 to 0 TxSel Defines which signal is used as source for modulation 00b ... no modulation 01b ... TxEnvelope 10b ... SigIn 11b ... RFU All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 80 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.9.4 Txl Table 129. Txl register (address 2Bh) Bit 7 6 5 4 3 2 1 Symbol OvershootT1 tx_set_iLoad Access rights r/w r/w 0 Table 130. Txl bits Bit Symbol Description 7 to 4 OvershootT1 Overshoot value for Timer1. Refer to Section 7.6.2.1 "Overshoot protection" 3 to 0 tx_set_iLoad Factory trim value, sets the expected Tx load current. This value is used to control the modulation index in an optimized way dependent on the expected TX load current. 8.10 CRC configuration registers 8.10.1 TxCrcPreset Table 131. TXCrcPreset register (address 2Ch) Bit 7 6 5 4 3 2 1 0 Symbol RFU TXPresetVal TxCRCtype TxCRCInvert TxCRCEn Access rights - r/w r/w r/w r/w Table 132. TxCrcPreset bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 RFU - 6 to 4 TXPresetVal Specifies the CRC preset value for transmission (see Table 132). 3 to 2 TxCRCtype Defines which type of CRC (CRC8/CRC16/CRC5) is calculated: * 00h -- CRC5 * 01h -- CRC8 * 02h -- CRC16 * 03h -- RFU 1 TxCRCInvert if set, the resulting CRC is inverted and attached to the data frame (ISO/IEC 3309) 0 TxCRCEn if set, a CRC is appended to the data stream All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 81 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 133. Transmitter CRC preset value configuration TXPresetVal[6...4] CRC16 CRC8 CRC5 0h 0000h 00h 00h 1h 6363h 12h 12h 2h A671h BFh - 3h FFFEh FDh - 4h - - - 5h - - - 6h User defined User defined User defined 7h FFFFh FFh 1Fh Remark: User defined CRC preset values can be configured by EEprom (see Section 7.7.2.1, Table 29 "Configuration area (Page 0)"). 8.10.2 RxCrcCon Table 134. RxCrcCon register (address 2Dh) Bit 7 6 5 4 3 2 1 0 Symbol RxForceCRCWrite RXPresetVal RXCRCtype RxCRCInvert RxCRCEn Access rights r/w r/w r/w r/w r/w Table 135. RxCrcCon bits Bit Symbol Description 7 RxForceCrc Write If set, the received CRC byte(s) are copied to the FIFO. If cleared CRC Bytes are only checked, but not copied to the FIFO. This bit has to be always set in case of a not byte aligned CRC (e.g. ISO/IEC 18000-3 mode 3/ EPC Class-1HF) 6 to 4 RXPresetVal Defines the CRC preset value (Hex.) for transmission. (see Table 135). 3 to 2 RxCRCtype Defines which type of CRC (CRC8/CRC16/CRC5) is calculated: * 00h -- CRC5 * 01h -- CRC8 * 02h -- CRC16 * 03h -- RFU 1 RxCrcInvert If set, the CRC check is done for the inverted CRC. 0 RxCrcEn If set, the CRC is checked and in case of a wrong CRC an error flag is set. Otherwise the CRC is calculated but the error flag is not modified. Table 136. Receiver CRC preset value configuration MFRC631 Product data sheet COMPANY PUBLIC RXPresetVal[6...4] CRC16 CRC8 CRC5 0h 0000h 00h 00h All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 82 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus RXPresetVal[6...4] CRC16 CRC8 CRC5 1h 6363h 12h 12h 2h A671h BFh - 3h FFFEh FDh - 4h - - - 5h - - - 6h User defined User defined User defined 7h FFFFh FFh 1Fh 8.11 Transmitter configuration registers 8.11.1 TxDataNum Table 137. TxDataNum register (address 2Eh) Bit Symbol 7 6 5 4 3 RFU RFU- RFU- KeepBitGrid DataEn TxLastBits r/w r/w r/w Access rights 2 1 0 Table 138. TxDataNum bits Bit Symbol Description 7 to 5 RFU - 4 KeepBitGrid If set, the time between consecutive transmissions starts is a multiple of one ETU. If cleared, consecutive transmissions can even start within one ETU 3 DataEn If cleared - it is possible to send a single symbol pattern. If set - data is sent. 2 to 0 TxLastBits Defines how many bits of the last data byte to be sent. If set to 000b all bits of the last data byte are sent. Note - bits are skipped at the end of the byte. Example - Data byte B2h (sent LSB first). TxLastBits = 011b (3h) => 010b (LSB first) is sent TxLastBits = 110b (6h) => 010011b (LSB first) is sent 8.11.2 TxDATAModWidth Transmitter data modulation width register Table 139. TxDataModWidth register (address 2Fh) Bit 7 6 5 4 3 Symbol DModWidth Access rights r/w MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 2 1 0 (c) NXP B.V. 2018. All rights reserved. 83 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 140. TxDataModWidth bits Bit Symbol Description 7 to 0 DModWidth Specifies the length of a pulse for sending data with enabled pulse modulation. The length is given by the number of carrier clocks + 1. A pulse can never be longer than from the start of the pulse to the end of the bit. The starting position of a pulse is given by the setting of TxDataMod.DPulseType. Note: This register is only used if Miller modulation (ISO/IEC 14443A PCD) is used. The settings are also used for the modulation width of start and/or stop symbols. 8.11.3 TxSym10BurstLen If a protocol requires a burst (an unmodulated subcarrier) the length can be defined with this TxSymBurstLen, the value high or low can be defined by TxSym10BurstCtrl. Table 141. TxSym10BurstLen register (address 30h) Bit 7 6 5 4 3 2 1 Symbol RFU Sym1Burst Len RFU Sym0Burst Len Access rights - r/w - r/w 0 Table 142. TxSym10BurstLen bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 RFU - 6 to 4 Sym1BurstLen Specifies the number of bits issued for symbol 1 burst. The 3 bits encodes a range from 8 to 256 bit: 00h - 8bit 01h - 16bit 02h - 32bit 04h - 48bit 05h - 64bit 06h - 96bit 07h - 128bit 08h - 256bit 3 RFU 2 to 0 Sym0BurstLen Specifies the number of bits issued for symbol 1 burst. The 3 bits encodes a range from 8 to 256 bit: 00h - 8bit 01h - 16bit 02h - 32bit 03h - 48bit 04h - 64bit 05h - 96bit 06h - 128bit 07h - 256bit - All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 84 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.11.4 TxWaitCtrl Table 143. TxWaitCtrl register (address 31h); reset value: C0h Bit 7 6 5 4 3 2 1 Symbol TxWaitStart TxWaitEtu TxWait High TxStopBitLength Access rights r/w r/w r/w r/w 0 Table 144. TXWaitCtrl bits Bit Symbol Description 7 TxWaitStart If cleared, the TxWait time is starting at the End of the send data (TX). If set, the TxWait time is starting at the End of the received data (RX). 6 TxWaitEtu If cleared, the TxWait time is TxWait x 16/13.56 MHz. If set, the TxWait time is TxWait x 0.5 / DBFreq (DBFreq is the frequency of the bit stream as defined by TxDataCon). 5 to 3 TxWait High Bit extension of TxWaitLo. TxWaitCtrl bit 5 is MSB. 2 to 0 TxStopBitLength Defines stop-bits and EGT (= stop-bit + extra guard time EGT) to be send: 0h: no stop-bit, no EGT 1h: 1 stop-bit, no EGT 2h: 1 stop-bit + 1 EGT 3h: 1 stop-bit + 2 EGT 4h: 1 stop-bit + 3 EGT 5h: 1 stop-bit + 4 EGT 6h: 1 stop-bit + 5 EGT 7h: 1 stop-bit + 6 EGT Note: This is only valid for ISO/IEC14443 Type B 8.11.5 TxWaitLo Table 145. TxWaitLo register (address 32h) Bit 7 6 5 4 3 Symbol TxWaitLo Access rights r/w MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 2 1 0 (c) NXP B.V. 2018. All rights reserved. 85 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 146. TxWaitLo bits Bit Symbol Description 7 to 0 TxWaitLo Defines the minimum time between receive and send or between two send data streams Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl register)! See also TxWaitEtu and TxWaitStart. 8.12 FrameCon Table 147. FrameCon register (address 33h) Bit 7 6 5 4 3 2 1 0 Symbol TxParityEn RxParityEn - - StopSym StartSym Access rights r/w r/w RFU RFU r/w r/w Table 148. FrameCon bits Bit Symbol Description 7 TxParityEn If set, a parity bit is calculated and appended to each byte transmitted. 6 RxParityEn If set, the parity calculation is enabled. The parity is not transferred to the FIFO. 5 to 4 - RFU 3 to 2 StopSym Defines which symbol is sent as stop-symbol: * 0h: No symbol is sent * 1h: Symbol0 is sent * 2 h symbol1 is sent * 3h Symbol2 is sent 1 to 0 StartSym Defines which symbol is sent as start-symbol: * 0h: No Symbol is sent * 1h: Symbol0 is sent * 2 h: Symbol1 is sent * 3h: Symbol2 is sent 8.13 Receiver configuration registers 8.13.1 RxSofD Table 149. RxSofD register (address 34h) Bit 7 6 5 4 3 2 1 0 Symbol RFU SOF_En SOFDetected RFU SubC_En SubC_Detected SubC_Present Access rights - r/w dy - r/w dy r MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 86 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 150. RxSofD bits Bit Symbol Description 7 to 6 RFU - 5 SOF_En If set and a SOF is detected an RxSOFIRQ is raised. 4 SOF_Detected Shows that a SOF is or was detected. Can be cleared by SW. 3 RFU - 2 SubC_En If set and a subcarrier is detected an RxSOFIRQ is raised. 1 SubC_Detected Shows that a subcarrier is or was detected. Can be cleared by SW. 0 SubC_Present Shows that a subcarrier is currently detected. 8.13.2 RxCtrl Table 151. RxCtrl register (address 35h) Bit 7 6 5 4 3 2 1 Symbol RxAllowBits RxMultiple RxEOFType EGT_Check EMD_Sup Baudrate Access rights r/w r/w r/w r/w r/w r/w 0 Table 152. RxCtrl bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 RxAllowBits If set, data is written into FIFO even if CRC is enabled, and no complete byte has been received. 6 RxMultiple If set, RxMultiple is activated and the receiver will not terminate automatically (refer Section 7.10.3.5 "Receive command"). If set to logic 1, at the end of a received data stream an error byte is added to the FIFO. The error byte is a copy of the Error register. 5 RxEOFType 0: EOF as defined in the RxEOFSymbolReg is expected. 1: ISO/IEC14443B EOF is expected. Note: Clearing this bit to 0 and clearing bit 0 and bit 1 in the RxEOFSymbolReg disables the EOF check. 4 EGT_Check If set to 1, the EGT is checked and if it is too long a protocol error is set. (This is only valid for ISO/IEC14443 Type B). 3 EMD_Sup Enables the EMD suppression according ISO/IEC14443. If an error occurs within the first three bytes, these three bytes are assumed to be EMD, ignored and the FIFO is reset. A collision is treated as an error as well If a valid SOF was received, the EMD_Sup is set and a frame of less than 3 bytes had been received. RX_IRQ is not set in this EMD error cases. If RxForceCRCWrite is set, the FIFO should not be read out before three bytes are written into. 2 to 0 Baudrate Defines the baud rate of the receiving signal. 4h: 106 kBd 5h: 212 kBd 6h: 424 kBd 7h: 847 kBd all remaining values are RFU All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 87 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.13.3 RxWait Selects internal receiver settings. Table 153. RxWait register (address 36h) Bit 7 6 5 4 3 2 Symbol RxWaitEtu RxWait Access rights r/w r/w 1 0 Table 154. RxWait bits Bit Symbol Description 7 RXWaitEtu If set to 0, the RxWait time is RxWait x 16/13.56 MHz. If set to 1, the RxWait time is RxWait x (0.5/DBFreq). 6 to 0 RxWait Defines the time after sending, where every input is ignored. 8.13.4 RxThreshold Selects minimum threshold level for the bit decoder. Table 155. RxThreshold register (address 37h) Bit 7 6 5 4 3 2 1 Symbol MinLevel MinLevelP Access rights r/w r/w 0 Table 156. RxThreshold bits Bit Symbol Description 7 to 4 MinLevel Defines the MinLevel of the reception. Note: The MinLevel should be higher than the noise level in the system. 3 to 0 MinLevelP Defines the MinLevel of the phase shift detector unit. 8.13.5 Rcv Table 157. Rcv register (address 38h) Bit 7 6 Symbol Rcv_Rx_single Rx_ADCmode SigInSel RFU CollLevel Access rights r/w r/w r/w - r/w MFRC631 Product data sheet COMPANY PUBLIC 5 4 3 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 2 1 0 (c) NXP B.V. 2018. All rights reserved. 88 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 158. Rcv bits Bit Symbol Description 7 Rcv_Rx_single Single RXP Input Pin Mode; 0: Fully Differential 1: Quasi-Differential 6 Rx_ADCmode Defines the operation mode of the Analog Digital Converter (ADC) 0: normal reception mode for ADC 1: LPCD mode for ADC 5 to 4 SigInSel Defines input for the signal processing unit: 0h - idle 1h - internal analog block (RX) 2h - signal in over envelope (ISO/IEC14443A) 3h - signal in over s3c-generic 3 to 2 RFU - 1 to 0 CollLevel Defines the strength of a signal to be interpreted as a collision: 0h - Collision has at least 1/8 of signal strength 1h - Collision has at least 1/4 of signal strength 2h - Collision has at least 1/2 of signal strength 3h - Collision detection is switched off 8.13.6 RxAna This register allows to set the gain (rcv_gain) and high pass corner frequencies (rcv_hpcf). Table 159. RxAna register (address 39h) Bit 7 6 5 4 3 2 1 0 Symbol VMid_r_sel RFU rcv_hpcf rcv_gain Access rights r/w - r/w r/w Table 160. RxAna bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7, 6 VMid_r_sel Factory trim value, needs to be 0. 5, 4 RFU 3, 2 rcv_hpcf The rcv_hpcf [1:0] signals allow 4 different settings of the base band amplifier high pass cut-off frequency from ~40 kHz to ~300 kHz. 1 to 0 rcv_gain With rcv_gain[1:0] four different gain settings from 30 dB and 60 dB can be configured (differential output voltage/differential input voltage). All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 89 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 161. Effect of gain and highpass corner register settings rcv_gain (Hex.) rcv_hpcf (Hex.) fl (kHz) fU (MHz) gain (dB20) bandwith (MHz) 03 00 38 2,3 60 2,3 03 01 79 2,4 59 2,3 03 02 150 2,6 58 2,5 03 03 264 2,9 55 2,6 02 00 41 2,3 51 2,3 02 01 83 2,4 50 2,3 02 02 157 2,6 49 2,4 02 03 272 3,0 41 2,7 01 00 42 2,6 43 2,6 01 01 84 2,7 42 2,6 01 02 157 2,9 41 2,7 01 03 273 3,3 39 3,0 00 00 43 2,6 35 2,6 00 01 85 2,7 34 2,6 00 02 159 2,9 33 2,7 00 03 276 3,4 30 3,1 8.14 Clock configuration 8.14.1 SerialSpeed This register allows to set speed of the RS232 interface. The default speed is set to 115.2 kbit/s. The transmission speed of the interface can be changed by modifying the entries for BR_T0 and BR_T1. The transfer speed can be calculated by using the following formulas: BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1) BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1) The framing is implemented with 1 startbit, 8 databits and 1 stop bit. A parity bit is not used. Transfer speeds above 1228,8 kbit/s are not supported. Table 162. SerialSpeed register (address3Bh); reset value: 7Ah Bit 7 6 5 4 3 2 Symbol BR_T0 BR_T1 Access rights r/w r/w MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 1 0 (c) NXP B.V. 2018. All rights reserved. 90 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 163. SerialSpeed bits Bit Symbol Description 7 to 5 BR_T0 BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1) BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1) 4 to 0 BR_T1 BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1) BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33) / 2^(BR_T0 - 1) Table 164. RS232 speed settings Transfer speed (kbit/s) SerialSpeed register content (Hex.) 7,2 FA 9,6 EB 14,4 DA 19,2 CB 38,4 AB 57,6 9A 115,2 7A 128,0 74 230,4 5A 460,8 3A 921,6 1C 1228,8 15 8.14.2 LFO_Trimm Table 165. LFO_Trim register (address 3Ch) Bit 7 6 5 4 3 Symbol LFO_trimm Access rights r/w 2 1 0 Table 166. LFO_Trim bits Bit Symbol Description 7 to 0 LFO_trimm Trimm value. Refer to Section 7.8.3 Note: If the trimm value is increased, the frequency of the oscillator decreases. 8.14.3 PLL_Ctrl Register The PLL_Ctrl register implements the control register for the IntegerN PLL. Two stages exist to create the ClkOut signal from the 27,12MHz input. In the first stage the 27,12Mhz MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 91 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus input signal is multiplied by the value defined in PLLDiv_FB and divided by two, and the second stage divides this frequency by the value defined by PLLDIV_Out. Table 167. PLL_Ctrl register (address3Dh) Bit 7 6 5 4 3 2 1 0 Symbol ClkOutSel ClkOut_En PLL_PD PLLDiv_FB Access rights r/w r/w r/w r/w Table 168. PLL_Ctrl register bits Bit Symbol Description 7 to 4 CLkOutSel * * * * * * * * * * * * * 3 ClkOut_En Enables the clock at Pin CLKOUT 2 PLL_PD PLL power down 1-0 PLLDiv_FB PLL feedback divider (see table 174) 0h - pin CLKOUT is used as I/O 1h - pin CLKOUT shows the output of the analog PLL 2h - pin CLKOUT is hold on 0 3h - pin CLKOUT is hold on 1 4h - pin CLKOUT shows 27.12 MHz from the crystal 5h - pin CLKOUT shows 13.56 MHz derived from the crystal 6h - pin CLKOUT shows 6.78 MHz derived from the crystal 7h - pin CLKOUT shows 3.39 MHz derived from the crystal 8h - pin CLKOUT is toggled by the Timer0 overflow 9h - pin CLKOUT is toggled by the Timer1 overflow Ah - pin CLKOUT is toggled by the Timer2 overflow Bh - pin CLKOUT is toggled by the Timer3 overflow Ch...Fh - RFU Table 169. Setting of feedback divider PLLDiv_FB [1:0] Bit 1 Bit 0 Division 0 0 23 (VCO frequency 312Mhz) 0 1 27 (VCO frequency 366MHz) 1 0 28 (VCO frequency 380Mhz) 1 1 23 (VCO frequency 312Mhz) 8.14.4 PLLDiv_Out Table 170. PLLDiv_Out register (address 3Eh) Bit 7 6 5 4 3 Symbol PLLDiv_Out Access rights r/w MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 2 1 0 (c) NXP B.V. 2018. All rights reserved. 92 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 171. PLLDiv_Out bits Bit Symbol Description 7 to 0 PLLDiv_Out PLL output divider factor; Refer to Section 7.8.2 Table 172. Setting for the output divider ratio PLLDiv_Out [7:0] Value Division 0 RFU 1 RFU 2 RFU 3 RFU 4 RFU 5 RFU 6 RFU 7 RFU 8 8 9 9 10 10 ... ... 253 253 254 254 8.15 Low-power card detection configuration registers The LPCD registers contain the settings for the low-power card detection. The setting for LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers LPCD_QMin, LPCD_QMax and LPCD_IMin each. 8.15.1 LPCD_QMin Table 173. LPCD_QMin register (address 3Fh) Bit 7 6 5 4 3 2 Symbol LPCD_IMax.5 LPCD_IMax.4 LPCD_QMin Access rights r/w r/w r/w 1 0 Table 174. LPCD_QMin bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7, 6 LPCD_IMax Defines the highest two bits of the higher border for the LPCD. If the measurement value of the I channel is higher than LPCD_IMax, a LPCD interrupt request is indicated by bit IRQ0.LPCDIRQ. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 93 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 5 to 0 LPCD_QMin Defines the lower border for the LPCD. If the measurement value of the Q channel is higher than LPCD_QMin, a LPCDinterrupt request is indicated by bit IRQ0.LPCDIRQ. 8.15.2 LPCD_QMax Table 175. LPCD_QMax register (address 40h) Bit 7 6 5 4 3 2 Symbol LPCD_IMax.3 LPCD_IMax.2 LPCD_QMax Access rights r/w r/w r/w 1 0 Table 176. LPCD_QMax bits Bit Symbol Description 7 LPCD_IMax.3 Defines the bit 3 of the high border for the LPCD. If the measurement value of the I channel is higher than LPCD IMax, a LPCD IRQ is raised. 6 LPCD_IMax.2 Defines the bit 2 of the high border for the LPCD. If the measurement value of the I channel is higher than LPCD IMax, a LPCD IRQ is raised. 5 to 0 LPCD_QMax Defines the high border for the LPCD. If the measurement value of the Q channel is higher than LPCD QMax, a LPCD IRQ is raised. 8.15.3 LPCD_IMin Table 177. LPCD_IMin register (address 41h) Bit 7 6 5 Symbol LPCD_IMax.1 LPCD_IMax.0 Access rights r/w r/w 4 3 2 1 0 LPCD_IMin r/w Table 178. LPCD_IMin bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 to 6 LPCD_IMax Defines lowest two bits of the higher border for the low-power card detection (LPCD). If the measurement value of the I channel is higher than LPCD IMax, a LPCD IRQ is raised. 5 to 0 LPCD_IMin Defines the lower border for the ow power card detection. If the measurement value of the I channel is lower than LPCD IMin, a LPCD IRQ is raised. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 94 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.15.4 LPCD_Result_I Table 179. LPCD_Result_I register (address 42h) Bit 7 6 5 4 3 2 Symbol RFU- RFU- LPCD_Result_I Access rights - - r 1 0 Table 180. LPCD_I_Result bits Bit Symbol Description 7 to 6 RFU - 5 to 0 LPCD_Result_I Shows the result of the last low-power card detection (I-Channel). 8.15.5 LPCD_Result_Q Table 181. LPCD_Result_Q register (address 43h) Bit Symbol 7 6 RFU LPCD_I RQ_Clr LPCD_Reslult_Q r/w r Access rights 5 4 3 2 1 0 Table 182. LPCD_Q_Result bits Bit Symbol Description 7 RFU - 6 LPCD_IRQ_Clr If set no LPCD IRQ is raised any more until the next low-power card detection procedure. Can be used by software to clear the interrupt source. 5 to 0 LPCD_Result_Q Shows the result of the last ow power card detection (Q-Channel). 8.15.6 LPCD_Options This register is available on the CLRC63103 only. For silicon version CLRC63102 this register on address 3AH is RFU. Table 183. LPCD_Options register (address 3Ah) Bit 7 Symbol Access rights MFRC631 Product data sheet COMPANY PUBLIC 6 5 RFU - 4 3 2 1 0 LPCD_TX_HIGH LPCD_FILTER LPCD_Q_ UNSTABLE LPCD_I_UNSTABLE r/w r/w r r All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 95 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 184. LPCD_Options Bit Symbol Description 7 to 4 RFU - 3 LPCD_TX_HIGH If set, the TX-driver will be the same as VTVDD during LPCD. This will allow for a better LPCD detection range (higher transmitter output voltage) at the cost of a higher current consumption. If this bit is cleared, the output voltage at the TX drivers will be = TVDD- 0.4V. If this bit is set, the output voltage at the TX drivers will be = VTVDD. 2 LPCD_FILTER If set, The LPCD decision is based on the result of a filter which allows to remove noise from the evaluated signal in I and Q channel. Enabling LPCD_FILTER allows compensating for noisy conditions at the cost of a longer RF-ON time required for sampling. The total maximum LPCD sampling time is 4.72us. 1 LPCD_Q_UNSTABLE If bit 2 of this register is set, bit 1 indicates that the Q-channel ADC value was changing during the LPCD measuring time. Note: Only valid if LPCD_FILTER (bit 2) = 1. This information can be used by the host application for configuration of e.g. the threshold LPCD_QMax or inverting the TX drivers. 0 LPCD_I_UNSTABLE If bit 2 of this register is set, bit 0 Indicates that the I-channel ADC value was changing during the LPCD measuring time. Note: Only valid if LPCD_FILTER (bit2) = 1. This information can be used by the host application for configuration of e.g. the threshold LPCD_IMax or inverting the TX drivers. 8.16 Pin configuration 8.16.1 PinEn Table 185. PinEn register (address 44h) Bit 7 6 5 4 3 2 1 0 Symbol SIGIN_EN CLKOUT_EN IFSEL1_EN IFSEL0_EN TCK_EN TMS_EN TDI_EN TMDO_EN Access rights r/w r/w r/w r/w r/w r/w r/w r/w Table 186. PinEn bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 SIGIN_EN Enables the output functionality on SIGIN (pin 5). The pin is then used as I/O. 6 CLKOUT_EN Enables the output functionality of the CLKOUT (pin 22). The pin is then used as I/O. The CLKOUT function is switched off. 5 IFSEL1_EN Enables the output functionality of the IFSEL1 (pin 27). The pin is then used as I/O. 4 IFSEL0_EN Enables the output functionality of the IFSEL0 (pin 26). The pin is then used as I/O. 3 TCK_EN Enables the output functionality of the TCK (pin 4) of the boundary scan interface. The pin is then used as I/O. If the boundary scan is activated in EEPROM, this bit has no function. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 96 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 2 TMS_EN Enables the output functionality of the TMS (pin 2) of the boundary scan interface. The pin is then used as I/O. If the boundary scan is activated in EEPROM, this bit has no function. 1 TDI_EN Enables the output functionality of the TDI (pin 1) of the boundary scan interface. The pin is then used as I/O. If the boundary scan is activated in EEPROM, this bit has no function. 0 TDO_EN Enables the output functionality of the TDO(pin 3) of the boundary scan interface. The pin is then used as I/O. If the boundary scan is activated in EEPROM, this bit has no function. 8.16.2 PinOut Table 187. PinOut register (address 45h) Bit 7 6 5 Symbol SIGIN_OUT CLKOUT_OUT Access rights r/w r/w 4 3 2 1 0 TDI_OUT TDO_OUT r/w r/w r/w IFSEL1_OUT IFSEL0_OUT TCK_OUT TMS_OUT r/w r/w r/w Table 188. PinOut bits Bit Symbol Description 7 SIGIN_OUT Output buffer of the SIGIN pin 6 CLKOUT_OUT Output buffer of the CLKOUT pin 5 IFSEL1_OUT Output buffer of the IFSEL1 pin 4 IFSEL0_OUT Output buffer of the IFSEL0 pin 3 TCK_OUT Output buffer of the TCK pin 2 TMS_OUT Output buffer of the TMS pin 1 TDI_OUT Output buffer of the TDI pin 0 TDO_OUT Output buffer of the TDO pin 8.16.3 PinIn Table 189. PinIn register (address 46h) Bit 7 6 5 4 3 2 1 0 Symbol SIGIN_IN CLKOUT_IN IFSEL1_IN IFSEL0_IN TCK_IN TMS_IN TDI_IN TDO_IN Access rights r r r r r r r r Table 190. PinIn bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 SIGIN_IN Input buffer of the SIGIN pin All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 97 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit Symbol Description 6 CLKOUT_IN Input buffer of the CLKOUT pin 5 IFSEL1_IN Input buffer of the IFSEL1 pin 4 IFSEL0_IN Input buffer of the IFSEL0 pin 3 TCK_IN Input buffer of the TCK pin 2 TMS_IN Input buffer of the TMS pin 1 TDI_IN Input buffer of the TDI pin 0 TDO_IN Input buffer of the TDO pin 8.16.4 SigOut Table 191. SigOut register (address 47h) Bit 7 6 5 4 3 2 1 Symbol Pad Speed RFU SigOutSel Access rights r/w - r/w 0 Table 192. SigOut bits Bit Symbol Description 7 PadSpeed If set, the I/O pins are supporting a fast switching mode.The fast mode for the I/O's will increase the peak current consumption of the device, especially if multiple I/Os are switching at the same time. The power supply needs to be designed to deliver this peak currents. 6 to 4 RFU - 3 to 0 SIGOutSel 0h, 1h - The pin SIGOUT is 3-state 2h - The pin SIGOUT is 0 3h - The pin SIGOUT is 1 4h - The pin SIGOUT shows the TX-envelope 5h - The pin SIGOUT shows the TX-active signal 6h - The pin SIGOUT shows the S3C (generic) signal 7h - The pin SIGOUT shows the RX-envelope (only valid for ISO/IEC 14443A, 106 kBd) 8h - The pin SIGOUT shows the RX-active signal 9h - The pin SIGOUT shows the RX-bit signal 8.17 Version register 8.17.1 Version Table 193. Version register (address 7Fh) Bit Symbol MFRC631 Product data sheet COMPANY PUBLIC 7 6 5 4 3 Version 2 1 0 SubVersion All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 98 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Bit 7 6 Access rights 5 4 3 r 2 1 0 r Table 194. Version bits MFRC631 Product data sheet COMPANY PUBLIC Bit Symbol Description 7 to 4 Version Includes the version of the MFRC631 silicon. MFRC63102: 0x1 MFRC63103: 0x1 3 to 0 SubVersion Includes the subversion of the MFRC631 silicon. MFRC63102: 0x8 MFRC63103: 0xA All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 99 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 9 Limiting values Table 195. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Conditions Min Max Unit supply voltage -0.5 + 6.0 V VDD(PVDD) PVDD supply voltage -0.5 + 6.0 V VDD(TVDD) TVDD supply voltage -0.5 + 6.0 V IDD(TVDD) TVDD supply current MFRC63102 - 250 mA MFRC63103 - 500 Vi(RXP) input voltage on pin RXP -0.5 + 2.0 V Vi(RXN) input voltage on pin RXN -0.5 + 2.0 V Ptot total power dissipation - 1125 mW VESD(HBM) electrostatic discharge voltage Human Body Model (HBM); 1500 , 100 pF; JESD22-A114B -2000 2000 V VESD(CDM) electrostatic discharge voltage Charge Device Model (CDM); -500 500 V Tj(max) maximum junction temperature - 125 C Tstg storage temperature -55 +150 C MFRC631 Product data sheet COMPANY PUBLIC per package no supply voltage applied All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 100 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 10 Recommended operating conditions Exposure of the device to other conditions than specified in the Recommended Operating Conditions section for extended periods may affect device reliability. Electrical parameters (minimum, typical and maximum) of the device are guaranteed only when it is used within the recommended operating conditions. Table 196. Operating conditions MFRC63102HN Symbol Parameter VDD supply voltage Conditions [1] Min Typ Max Unit 3.0 5.0 5.5 V 3.0 5.0 5.5 V 3.0 5.0 5.5 V VDD(TVDD) TVDD supply voltage VDD(PVDD) PVDD supply voltage Tamb operating ambient temperature in still air with exposed pin soldered on a 4 layer JEDEC PCB -25 +25 +85 C Tstg storage temperature no supply voltage applied, relative humidity 45...75% -40 +25 +125 C Min Typ Max Unit 2.5 5.0 5.5 V 2.5 5.0 5.5 V all host interfaces except I2C interface 2.5 5.0 5.5 V all host interfaces incl. I2C interface 3.0 5.0 5.5 V [1] VDD(PVDD) must always be the same or lower than VDD. Table 197. Operating conditions MFRC63103HN Symbol Parameter VDD supply voltage VDD(TVDD) TVDD supply voltage VDD(PVDD) PVDD supply voltage Conditions [1] Tamb operating ambient temperature in still air with exposed pin soldered on a 4 layer JEDEC PCB -40 +25 +105 C Tstg storage temperature no supply voltage applied, relative humidity 45...75% -45 +25 +125 C [1] VDD(PVDD) must always be the same or lower than VDD. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 101 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 11 Thermal characteristics Table 198. Thermal characteristics Symbol Parameter Conditions Package Rth(j-a) thermal resistance from junction to ambient in still air with exposed pin soldered on a 4 layer JEDEC PCB HVQFN32 40 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 Typ Unit K/W (c) NXP B.V. 2018. All rights reserved. 102 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 12 Characteristics Table 199. Characteristics Symbol Parameter Conditions Min Typ Max Unit IDD = AVDD+DVDD; modem on (transmitter and receiver are switched on) - 17 20 mA IDD = AVDD+DVDD; modem off (transmitter and receiver are switched off) - 0.45 0.5 mA Current consumption IDD supply current IDD(PVDD) PVDD supply current no load on digital pins, leakage current only - 0.5 5 A IDD(TVDD) TVDD supply current MFRC63102HN - 100 250 mA MFRC63103HN - 250 350 mA ambient temp = +25 C - 40 400 nA ambient temp = -40C... +85C - 1.5 2.1 A MFRC63103: ambient temp = +105 C - 3.5 5.2 A ambient temp = 25 C, IVDD+ITVDD+ IPVDD - 3 6 A ambient temp = -40C... +105C, Istby = IVDD+ITVDD+ IPVDD - 5.25 26 - 3.3 6.3 A LPCD_TX_HIGH = 0, - 12 - A LPCD_TX_HIGH = 1 - 23 - LPCD_TX_HIGH = 0; TVDD=5.0 V T=25C; - 10 - s LPCD_TX_HIGH = 1; TVDD=5.0 V; T=25C - 50 - s AVDD 220 470 - nF Ipd Istby power-down current standby current ILPCD(sleep) LPCD sleep current All OUTx pins floating All OUTx pins floating All OUTx pins floating LFO active, no RF field on, ambient temp = 25 C ILPCD(average)LPCD average current tRFON RF-on time during LPCD [1] All OUTx pins floating, TxLoad = 50 ohms. LPCD_FILTER = 0; Rfon duration = 10 us, RF-off duration 300ms; VTVDD = 3.0V; Tamb = 25C; ILPCD = IVDD+ITVDD+ IPVDD Buffer capacitors on AVDD,DVDD CL external buffer capacitor MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 103 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Symbol Parameter Conditions Min Typ Max Unit CL external buffer capacitor DVDD 220 470 - nF 0.0 50 500 nA 0.3 x VDD(PVDD) V I/O pin characteristics SIGIN/OUT7, SIGOUT, CLKOUT/OUT6, IFSEL0/OUT4, IFSEL1/OUT5, TCK/OUT3, TMS/OUT2, TDI/ OUT1, TDO/OUT0, IRQ, IF0, IF1, IF2, SCL2, SDA2 ILI input leakage current output disabled VIL low-level input voltage -0.5 - VIH high-level input voltage 0.7 x VDD(PVDD) VDD(PVDD)VDD(PVDD) + 0.5 V VOL low-level output voltage 0.0 0.0 VOH high-level output voltage Ci input capacitance If pins are used as output OUTx, IOH = 4 mA driving current for each pin 0.4 V VDD(PVDD)-0.4 VDD(PVDD)VDD(PVDD) V 0.0 2.5 4.5 pF 0.4 V Pin characteristics PDOWN VIL low-level input voltage 0.0 0.0 VIH high-level input voltage 0.6 x VPVDD VDD(PVDD)VDD(PVDD) V 50 72 120 K Pull-up resistance for TCK, TMS, TDI, IF2 Rpu pull-up resistance Pin characteristics AUX 1, AUX 2 Vo output voltage 0.0 - 1.8 V CL load capacitance 0.0 - 400 pF Pin characteristics RXP, RXN Vpp input voltage 0 1.65 1.8 V Ci input capacitance 2 3.5 5 pF Vmod(pp) modulation voltage - 2.5 - mV Vss(TVSS) - VDD(TVDD) V MFRC63102: T=25C, VDD(TVDD) = 5.0V - 1.5 - MFRC63103: T=25C, VDD(TVDD) = 5.0V - 1.2 - configured to 27.12 MHz - 27.12 - MHz - 50 - % Vmod(pp) = Vi(pp)(max) - Vi(pp) (min) Pins TX1 and TX2 Vo output voltage Ro output resistance Clock frequency Pin CLKOUT fclk clock frequency clk clock duty cycle Crystal connection XTAL1, XTAL2 Vo(p-p) peak-to-peak output voltage pin XTAL1 - 1.0 - V Vi input voltage pin XTAL1 0.0 - 1.8 V Ci input capacitance pin XTAL1 - 3 - pF MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 104 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Symbol Parameter Conditions Min Typ Max Unit ISO/IEC14443 compliancy 27.12-14kHz 27.12 27.12+14kHz MHz Crystal requirements fxtal crystal frequency ESR equivalent series resistance - 50 100 CL load capacitance - 10 - pF Pxtal crystal power dissipation - 50 100 W - 2 100 nA - +0.3 VDD(PVDD) V 2 Input characteristics I/O Pin Characteristics IF3-SDA in I C configuration ILI input leakage current VIL LOW-level input voltage -0.5 VIH HIGH-level input voltage 0.7 VDD(PVDD) - VDD(PVDD) + 0.5 V VOL LOW-level output voltage IOL = 3 mA - - 0.3 V IOL LOW-level output current VOL = 0.4 V; Standard mode, Fast mode 4 - - mA VOL = 0.6 V; Standard mode, Fast mode 6 - - mA Standard mode, Fast mode, CL < 400 pF - - 250 ns Fast mode +; CL < 550 pF - - 120 ns tf(o) output fall time output disabled tSP pulse width of spikes that must be suppressed by the input filter 0 - 50 ns Ci input capacitance - 3.5 5 pF CL load capacitance Standard mode - - 400 pF Fast mode - - 550 pF - - year - - cycle tEER EEPROM data retention time Tamb = +55 C 10 NEEC EEPROM endurance (number of programming cycles) under all operating conditions 5 x 10 [1] 5 Ipd is the total current for all supplies. Vmod Vi(p-p)(max) VMID Vi(p-p)(min) 13.56 MHz carrier 0V 001aak012 Figure 31. Pin RX input voltage MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 105 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 12.1 Timing characteristics Table 200. SPI timing characteristics Symbol Parameter tSCKL Conditions Min Typ Max Unit SCK LOW time 50 - - ns tSCKH SCK HIGH time 50 - - ns th(SCKH-D) SCK HIGH to data input hold time SCK to changing MOSI 25 - - ns tsu(D-SCKH) data input to SCK HIGH set- changing MOSI to SCK up time 25 - - ns th(SCKL-Q) SCK LOW to data output hold time - - 25 ns t(SCKL-NSSH) SCK LOW to NSS HIGH time 0 - - ns tNSSH NSS HIGH time 50 - - ns SCK to changing MISO before communication Remark: To send more bytes in one data stream the NSS signal must be LOW during the send process. To send more than one data stream the NSS signal must be HIGH between each data stream. 2 Table 201. I C-bus timing in fast mode and fast mode plus Symbol MFRC631 Product data sheet COMPANY PUBLIC Parameter Conditions Fast mode Fast mode Unit Plus Min Max Min Max 0 400 0 1000 kHz after this period, 600 the first clock pulse is generated - 260 - ns fSCL SCL clock frequency tHD;STA hold time (repeated) START condition tSU;STA set-up time for a repeated START condition 600 - 260 - ns tSU;STO set-up time for STOP condition 600 - 260 - ns tLOW LOW period of the SCL clock 1300 - 500 - ns tHIGH HIGH period of the SCL clock 600 - 260 - ns tHD;DAT data hold time 0 900 - 450 ns tSU;DAT data set-up time 100 - - - ns tr rise time SCL signal 20 300 - 120 ns tf fall time SCL signal 20 300 - 120 ns tr rise time SDA and SCL signals 20 300 - 120 ns tf fall time SDA and SCL signals 20 300 - 120 ns tBUF bus free time between a STOP and START condition 1.3 - 0.5 - s All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 106 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus SDA tf tSU;DAT tLOW tSP tf tr tHD;STA tBUF SCL tr tHD;STA S tHIGH tHD;DAT tSU;STO tSU;STA Sr P S 001aaj635 2 Figure 32. Timing for fast and standard mode devices on the I C-bus MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 107 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 13 Application information A typical application diagram using a complementary antenna connection to the MFRC631 is shown in Figure 33. The antenna tuning and RF part matching is described in the application note [1] and [2]. VDD PVDD TVDD 25 18 8 AVDD 9 13 14 PDOWN MICROPROCESSOR host interface IRQ DVDD 21 28-31 17 READER IC 16 32 15 CRXN RXN VMID R1 C vmid TX1 R2 C1 L0 TVSS TX2 Ra C0 C2 C0 C2 Ra antenna Lant L0 C1 14 7 12 33 VSS 19 RXP 20 XTAL1 XTAL2 R3 R4 CRXP 27.12 MHz 001aam269 Figure 33. Typical application antenna circuit diagram 13.1 Antenna design description The matching circuit for the antenna consists of an EMC low pass filter (L0 and C0), a matching circuitry (C1 and C2), and a receiving circuits (R1 = R3, R2 = R4, C3 = C5 and C4 = C6;), and the antenna itself. The receiving circuit component values needs to be designed for operation with the MFRC631. A reuse of dedicated antenna designs done for other products without adaptation of component values will result in degraded performance. 13.1.1 EMC low pass filter The MIFARE product-based system operates at a frequency of 13.56 MHz. This frequency is derived from a quartz oscillator to clock the MFRC631 and is also the basis for driving the antenna with the 13.56 MHz energy carrier. This will not only cause emitted power at 13.56 MHz but will also emit power at higher harmonics. The international EMC regulations define the amplitude of the emitted power in a broad frequency range. Thus, an appropriate filtering of the output signal is necessary to fulfil these regulations. Remark: The PCB layout has a major influence on the overall performance of the filter. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 108 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 13.1.2 Antenna matching Due to the impedance transformation of the given low pass filter, the antenna coil has to be matched to a certain impedance. The matching elements C1 and C2 can be estimated and have to be fine tuned depending on the design of the antenna coil. The correct impedance matching is important to provide the optimum performance. The overall quality factor has to be considered to guarantee a proper ISO/IEC 14443 communication scheme. Environmental influences have to be considered as well as common EMC design rules. For details refer to the NXP application notes. 13.1.3 Receiving circuit The internal receiving concept of the MFRC631 makes use both side-bands of the subcarrier load modulation of the card response via a differential receiving concept (RXP, RXN). No external filtering is required. It is recommended to use the internally generated VMID potential as the input potential of pin RX. This DC voltage level of VMID has to be coupled to the Rx-pins via R2 and R4. To provide a stable DC reference voltage capacitances C4, C6 has to be connected between VMID and ground. Refer to Figure 33 Considering the (AC) voltage limits at the Rx-pins the AC voltage divider of R1 + C3 and R2 as well as R3 + C5 and R4 has to be designed. Depending on the antenna coil design and the impedance matching the voltage at the antenna coil varies from antenna design to antenna design. Therefore the recommended way to design the receiving circuit is to use the given values for R1(= R3), R2 (= R4), and C3 (= C5) from the above mentioned application note, and adjust the voltage at the RX-pins by varying R1(= R3) within the given limits. Remark: R2 and R4 are AC-wise connected to ground (via C4 and C6). 13.1.4 Antenna coil The precise calculation of the antenna coils' inductance is not practicable but the inductance can be estimated using the following formula. We recommend designing an antenna either with a circular or rectangular shape. (4) * I1 - Length in cm of one turn of the conductor loop * D1 - Diameter of the wire or width of the PCB conductor respectively * K - Antenna shape factor (K = 1,07 for circular antennas and K = 1,47 for square antennas) * L1 - Inductance in nH * N1 - Number of turns * Ln: Natural logarithm function The actual values of the antenna inductance, resistance, and capacitance at 13.56 MHz depend on various parameters such as: MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 109 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus * * * * * antenna construction (Type of PCB) thickness of conductor distance between the windings shielding layer metal or ferrite in the near environment Therefore a measurement of those parameters under real life conditions, or at least a rough measurement and a tuning procedure is highly recommended to guarantee a reasonable performance. For details refer to the above mentioned application notes. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 110 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 14 Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm B D SOT617-1 A terminal 1 index area A E A1 c detail X C e1 e 1/2 e b 9 L y y1 C v M C A B w M C 16 17 8 e e2 Eh 1/2 1 terminal 1 index area e 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.1 4.9 3.25 2.95 5.1 4.9 3.25 2.95 0.5 3.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT617-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18 Figure 34. Package outline SOT617-1 (HVQFN32) MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 111 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Detailed package information can be found at http://www.nxp.com/package/ SOT617-1.html. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 112 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 15 Handling information Moisture Sensitivity Level (MSL) evaluation has been performed according to SNWFQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 2 which means 260 C convection reflow temperature. For MSL2: * Dry pack is required. * 1 year out-of-pack floor life at maximum ambient temperature 30 C/ 85 % RH. For MSL1: * No dry pack is required. * No out-of-pack floor live spec. required. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 113 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 16 Packing information The straps around the package of stacked trays inside the plano-box have sufficient pre-tension to avoid loosening of the trays. strap 46 mm from corner tray ESD warning preprinted chamfer barcode label (permanent) PIN 1 barcode label (peel-off) chamfer QA seal PIN 1 Hyatt patent preprinted In the traystack (2 trays) only ONE tray type* allowed *one supplier and one revision number. printed plano box 001aaj740 Figure 35. Packing information 1 tray MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 114 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus strap 46 mm from the corner PQ-label (permanent) bag dry-agent relative humidity indicator preprinted: recycling symbol moisture caution label ESD warning tray manufacturer bag info chamfer ESD warning preprinted PQ-label (permanent) PIN 1 PLCC52 dry-pack ID preprinted chamfer strap PIN 1 QA seal chamfer printed plano box PIN 1 aaa-004952 Figure 36. Packing information 5 tray MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 115 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus BC BB BA BA BD BD BC 0.50 section BC-BC scale 4:1 BB A B C 0.50 section BA-BA scale 4:1 3.00 1.55 2.50 end lock AJ AJ AR AR side lock AN AK AL AL AK detail AC scale 20:1 section BD-BD scale 4:1 3.32 1.10 (0.30) A B C vacuum cell AM AM 0.35 14.200.08+10/S SQ. 1.20 12.80-5/S SQ. 0.56 (0.64) (14.40+5/S SQ.) (1.45) 16.600.08+7/S SQ. 13.850.08+12/S SQ. section AJ-AJ scale 2:1 section AL-AL scale 5:1 section AK-AK scale 5:1 AN section AN-AN scale 4:1 section AM-AM scale 4:1 section AR-AR scale 2:1 aaa-004949 Figure 37. Tray details MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 116 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus ASSY REEL + LABELS tape (see: HOW TO SECURE) see: ASSY REEL + LABELS guard band O 330x12/16/24/32 (hub 7'') label side embossed ESD logo tape (see: HOW TO SECURE) circular sprocket holes opposite the label side of reel printed plano-box cover tape embossed ESD logo carrier tape O 330x16/24/32/44 (hub 4'') O 330x44 (hub 6'') O 180x12/16/24 enlongated PIN1 has to be in quadrant 1 circular PIN1 PIN1 SO PLCC enlongated PIN1 1 PIN1 2 3 4 BGA bare die QFP product orientation in carrier tape unreeling direction (HV)QFN (HV)SON (H)BCC product orientation ONLY for turned products with 12nc ending 128 PIN1 SO PIN1 QFP HOW TO SECURE LEADER END TO THE GUARD BAND, HOW TO SECURE GUARD BAND PIN1 1 2 PIN1 3 4 PIN1 for SOT765 BGA for SOT505-2 ending 125 bare die ending 125 (HV)QFN (HV)SON (H)BCC tapeslot label side trailer trailer : lenght of trailer shall be 160 mm min. and covered with cover tape leader : lenght of trailer shall be 400 mm min. and covered with cover tape circular sprocket hole side guard band leader QA seal preprinted ESD warning PQ-label (permanent) dry-pack ID preprinted tape (with pull tabs on both ends) lape double-backed onto itself on both ends guard band aaa-004950 Figure 38. Packing information Reel MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 117 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 118 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 17 Appendix 17.1 LoadProtocol command register initialization The RF configuration is loaded with the command Load Protocol. The tables below show the register configuration as performed by this command for each of the protocols. Antenna specific configurations are not covered by this register settings. The MFRC63102 is not initialized for any antenna configuration. For this products the antenna configuration needs to be done by firmware. The MFRC63103 antenna configuration in the user EEPROM is described in the Section 17.2. Table 202. Protocol Number 00: ISO/IEC14443-A 106 / MIFARE Classic MFRC631 Product data sheet COMPANY PUBLIC Value for register Value (hex) TxBitMod 20 RFU 00 TxDataCon 04 TxDataMod 50 TxSymFreq 40 TxSym0H 00 TxSym0L 00 TxSym1H 00 TxSym1L 00 TxSym2 00 TxSym3 00 TxSym10Len 00 TxSym32Len 00 TxSym10BurstCtrl 00 TxSym10Mod 00 TxSym32Mod 50 RxBitMod 02 RxEofSym 00 RxSyncValH 00 RxSyncValL 01 RxSyncMod 00 RxMod 08 RxCorr 80 FabCal B2 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 119 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 203. Protocol Number 01: ISO/IEC14443-A 212/ MIFARE Classic Value for register Value (hex) TxBitMod 20 RFU 00 TxDataCon 05 TxDataMod 50 TxSymFreq 50 TxSym0H 00 TxSym0L 00 TxSym1H 00 TxSym1L 00 TxSym2 00 TxSym3 00 TxSym10Len 00 TxSym32Len 00 TxSym10BurstCtrl 00 TxSym10Mod 00 TxSym32Mod 50 RxBitMod 22 RxEofSym 00 RxSyncValH 00 RxSyncValL 00 RxSyncMod 00 RxMod 0D RxCorr 80 FabCal B2 Table 204. Protocol Number 02: ISO/IEC14443-A 424/ MIFARE Classic MFRC631 Product data sheet COMPANY PUBLIC Value for register Value (hex) TxBitMod 20 RFU 00 TxDataCon 06 TxDataMod 50 TxSymFreq 60 TxSym0H 00 TxSym0L 00 TxSym1H 00 TxSym1L 00 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 120 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register Value (hex) TxSym2 00 TxSym3 00 TxSym10Len 00 TxSym32Len 00 TxSym10BurstCtrl 00 TxSym10Mod 00 TxSym32Mod 50 RxBitMod 22 RxEofSym 00 RxSyncValH 00 RxSyncValL 00 RxSyncMod 00 RxMod 0D RxCorr 80 FabCal B2 Table 205. Protocol Number 03: ISO/IEC14443-A 848/ MIFARE Classic MFRC631 Product data sheet COMPANY PUBLIC Value for register Value (hex) TxBitMod 20 RFU 00 TxDataCon 07 TxDataMod 50 TxSymFreq 70 TxSym0H 00 TxSym0L 00 TxSym1H 00 TxSym1L 00 TxSym2 00 TxSym3 00 TxSym10Len 00 TxSym32Len 00 TxSym10BurstCtrl 00 TxSym10Mod 00 TxSym32Mod 50 RxBitMod 22 RxEofSym 00 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 121 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register Value (hex) RxSyncValH 00 RxSyncValL 00 RxSyncMod 00 RxMod 0D RxCorr 80 FabCal B2 Table 206. Protocol Number 04: ISO/IEC14443-B 106 Value for register Value (hex) TxBitMod 09 RFU 00 TxDataCon 04 TxDataMod 08 TxSymFreq 04 TxSym0H 00 TxSym0L 03 TxSym1H 00 TxSym1L 01 TxSym2 00 TxSym3 00 TxSym10Len AB TxSym32Len 00 TxSym10BurstCtrl 00 TxSym10Mod 08 TxSym32Mod 00 RxBitMod 04 RxEofSym 00 RxSyncValH 00 RxSyncValL 00 RxSyncMod 02 RxMod MFRC63102: 1D MFRC63103: 0D MFRC631 Product data sheet COMPANY PUBLIC RxCorr 80 FabCal B2 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 122 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 207. Protocol Number 05: ISO/IEC14443-B 212 Value for register Value (hex) TxBitMod 09 RFU 00 TxDataCon 05 TxDataMod 08 TxSymFreq 05 TxSym0H 00 TxSym0L 03 TxSym1H 00 TxSym1L 01 TxSym2 00 TxSym3 00 TxSym10Len AB TxSym32Len 00 TxSym10BurstCtrl 00 TxSym10Mod 08 TxSym32Mod 00 RxBitMod 04 RxEofSym 00 RxSyncValH 00 RxSyncValL 00 RxSyncMod 02 RxMod MFRC63102: 1D MFRC63103: 0D RxCorr 80 FabCal B2 Table 208. Protocol Number 06: ISO/IEC14443-B 424 MFRC631 Product data sheet COMPANY PUBLIC Value for register Value (hex) TxBitMod 09 RFU 00 TxDataCon 06 TxDataMod 08 TxSymFreq 06 TxSym0H 00 TxSym0L 03 TxSym1H 00 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 123 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register Value (hex) TxSym1L 01 TxSym2 00 TxSym3 00 TxSym10Len AB TxSym32Len 00 TxSym10BurstCtrl 00 TxSym10Mod 08 TxSym32Mod 00 RxBitMod 04 RxEofSym 00 RxSyncValH 00 RxSyncValL 00 RxSyncMod 02 RxMod MFRC63102: 1D MFRC63103: 0D RxCorr 80 FabCal B2 Table 209. Protocol Number 07: ISO/IEC14443-B 848 MFRC631 Product data sheet COMPANY PUBLIC Value for register Value (hex) TxBitMod 09 RFU 00 TxDataCon 07 TxDataMod 08 TxSymFreq 07 TxSym0H 00 TxSym0L 03 TxSym1H 00 TxSym1L 01 TxSym2 00 TxSym3 00 TxSym10Len AB TxSym32Len 00 TxSym10BurstCtrl 00 TxSym10Mod 08 TxSym32Mod 00 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 124 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register Value (hex) RxBitMod 04 RxEofSym 00 RxSyncValH 00 RxSyncValL 00 RxSyncMod 02 RxMod MFRC63102: 1D MFRC63103: 0D RxCorr 80 FabCal B2 17.2 MFRC63103 EEPROM configuration The MFRC63103 user EEPROM had been initalized with useful values for configuration of the chip using a typical 65x65mm antenna. This values stored in EEPROM can be used to configure the MFRC63103 with the command LoadReg.Typically, some of this entries will be required to be modified compared to the preset values to achieve the best RF performance for a specific antenna. The registers 0x28...0x39 are relevant for configuration of the Antenna. For each supported protocol, a dedicated preset configuration is available. To ensure compatibility between products of the CLRC63103 family, all products use the same default settings which are initialized in EEPROM, even if some of this protocols are not supported by the MFRC63103 product (e.g.ISO/IEC14443-B) and cannot be used. Alternatively, the registers can be initialized by individual register write commands. Table 210. ISO/IEC14443-A 106 / MIFARE Classic MFRC631 Product data sheet COMPANY PUBLIC Value for register EEPROM address (hex) Value (hex) DrvMode C0 8E TxAmp C1 12 DrvCon C2 39 TxI C3 0A TXCrcPreset C4 18 RXCrcPreset C5 18 TxDataNum C6 0F TxModWidth C7 21 TxSym10BurstLen C8 00 TxWaitCtrl C9 C0 TxWaitLo CA 12 TxFrameCon CB CF RxSofD CC 00 RxCtrl CD 04 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 125 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) RxWait CE 90 RxTreshold CF 5C Rcv D0 12 RxAna D1 0A Table 211. ISO/IEC14443-A 212/ MIFARE Classic Value for register EEPROM address (hex) Value (hex) DrvMode D4 8E TxAmp D5 D2 DrvCon D6 11 TxI D7 0A TXCrcPreset D8 18 RXCrcPreset D9 18 TxDataNum DA 0F TxModWidth DB 10 TxSym10BurstLen DC 00 TxWaitCtrl DD C0 TxWaitLo DE 12 TxFrameCon DF CF RxSofD E0 00 RxCtrl E1 05 RxWait E2 90 RxTreshold E3 3C Rcv E4 12 RxAna E5 0B Table 212. ISO/IEC14443-A 424/ MIFARE Classic MFRC631 Product data sheet COMPANY PUBLIC Value for register EEPROM address (hex) Value (hex) DrvMode E8 8F TxAmp E9 DE DrvCon EA 11 TxI EB 0F TXCrcPreset EC 18 RXCrcPreset ED 18 TxDataNum EE 0F TxModWidth EF 07 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 126 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) TxSym10BurstLen F0 00 TxWaitCtrl F1 C0 TxWaitLo F2 12 TxFrameCon F3 CF RxSofD F4 00 RxCtrl F5 06 RxWait F6 90 RxTreshold F7 2B Rcv F8 12 RxAna F9 0B Table 213. ISO/IEC14443-A 848/ MIFARE Classic Value for register EEPROM address (hex) Value (hex) DrvMode 0100 8F TxAmp 0101 DB DrvCon 0102 21 TxI 0103 0F TXCrcPreset 0104 18 RXCrcPreset 0105 18 TxDataNum 0106 0F TxModWidth 0107 02 TxSym10BurstLen 0108 00 TxWaitCtrl 0109 C0 TxWaitLo 010A 12 TxFrameCon 010B CF RxSofD 010C 00 RxCtrl 010D 07 RxWait 010E 90 RxTreshold 010F 3A Rcv 0110 12 RxAna 0111 0B Value for register EEPROM address (hex) Value (hex) DrvMode 0114 8F TxAmp 0115 0E Table 214. ISO/IEC14443-B 106 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 127 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) DrvCon 0116 09 TxI 0117 0A TXCrcPreset 0118 7B RXCrcPreset 0119 7B TxDataNum 011A 08 TxModWidth 011B 00 TxSym10BurstLen 011C 00 TxWaitCtrl 011D 01 TxWaitLo 011E 00 TxFrameCon 011F 05 RxSofD 0120 00 RxCtrl 0121 34 RxWait 0112 90 RxTreshold 0113 6F Rcv 0114 12 RxAna 0115 03 Value for register EEPROM address (hex) Value (hex) DrvMode 0128 8F TxAmp 0129 0E DrvCon 012A 09 TxI 012B 0A TXCrcPreset 012C 7B RXCrcPreset 012D 7B TxDataNum 012E 08 TxModWidth 012F 00 TxSym10BurstLen 0130 00 TxWaitCtrl 0131 01 TxWaitLo 0132 00 TxFrameCon 0133 05 RxSofD 0134 00 RxCtrl 0135 35 RxWait 0136 90 RxTreshold 0137 3F Rcv 0138 12 Table 215. ISO/IEC14443-B 212 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 128 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) RxAna 0139 03 Value for register EEPROM address (hex) Value (hex) DrvMode 0140 8F TxAmp 0141 0F DrvCon 0142 09 TxI 0143 0A TXCrcPreset 0144 7B RXCrcPreset 0145 7B TxDataNum 0146 08 TxModWidth 0147 00 TxSym10BurstLen 0148 00 TxWaitCtrl 0149 01 TxWaitLo 014A 00 TxFrameCon 014B 05 RxSofD 014C 00 RxCtrl 014D 36 RxWait 014E 90 RxTreshold 014F 3F Rcv 0150 12 RxAna 0151 03 Value for register EEPROM address (hex) Value (hex) DrvMode 0154 8F TxAmp 0155 10 DrvCon 0156 09 TxI 0157 0A TXCrcPreset 0158 7B RXCrcPreset 0159 7B TxDataNum 015A 08 TxModWidth 015B 00 TxSym10BurstLen 015C 00 TxWaitCtrl 015D 01 TxWaitLo 015E 00 Table 216. ISO/IEC14443-B 424 Table 217. ISO/IEC14443-B 848 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 129 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) TxFrameCon 015F 05 RxSofD 0160 00 RxCtrl 0161 37 RxWait 0162 90 RxTreshold 0163 3F Rcv 0164 12 RxAna 0165 03 The following EEprom values for initializing the Receiver cannot be used on the MFRC63103. They are provided for compatibility reasons between the products of the CLRC66303 product family Table 218. JIS X 6319-4 (FeliCa) 212 Value for register EEPROM address (hex) Value (hex) DrvMode 0168 8F TxAmp 0169 17 DrvCon 016A 01 TxI 016B 06 TXCrcPreset 016C 09 RXCrcPreset 016D 09 TxDataNum 016E 08 TxModWidth 016F 00 TxSym10BurstLen 0170 03 TxWaitCtrl 0171 80 TxWaitLo 0172 12 TxFrameCon 0173 01 RxSofD 0174 00 RxCtrl 0175 05 RxWait 0176 86 RxTreshold 0177 3F Rcv 0178 12 RxAna 0179 02 Table 219. JIS X 6319-4 (FeliCa) 424 MFRC631 Product data sheet COMPANY PUBLIC Value for register EEPROM address (hex) Value (hex) DrvMode 0180 8F TxAmp 0181 17 DrvCon 0182 01 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 130 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) TxI 0183 06 TXCrcPreset 0184 09 RXCrcPreset 0185 09 TxDataNum 0186 08 TxModWidth 0187 00 TxSym10BurstLen 0188 03 TxWaitCtrl 0189 80 TxWaitLo 018A 12 TxFrameCon 018B 01 RxSofD 018C 00 RxCtrl 018D 06 RxWait 018E 86 RxTreshold 018F 3F Rcv 0190 12 RxAna 0191 02 Table 220. ISO/IEC15693 SLI 1/4 - SSC- 26 MFRC631 Product data sheet COMPANY PUBLIC Value for register EEPROM address (hex) Value (hex) DrvMode 0194 89 TxAmp 0195 10 DrvCon 0196 09 TxI 0197 0A TXCrcPreset 0198 7B RXCrcPreset 0199 7B TxDataNum 019A 08 TxModWidth 019B 00 TxSym10BurstLen 019C 00 TxWaitCtrl 019D 88 TxWaitLo 019E A9 TxFrameCon 019F 0F RxSofD 01A0 00 RxCtrl 01A1 02 RxWait 01A2 9C RxTreshold 01A3 74 Rcv 01A4 12 RxAna 01A5 07 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 131 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 221. ISO/IEC15693 SLI 1/4 - SSC-53 Value for register EEPROM address (hex) Value (hex) DrvMode 01A8 89 TxAmp 01A9 10 DrvCon 01AA 09 TxI 01AB 0A TXCrcPreset 01AC 7B RXCrcPreset 01AD 7B TxDataNum 01AE 08 TxModWidth 016F 00 TxSym10BurstLen 01B0 00 TxWaitCtrl 01B1 88 TxWaitLo 01B2 A9 TxFrameCon 01B3 0F RxSofD 01B4 00 RxCtrl 01B5 03 RxWait 01B6 9C RxTreshold 01B7 74 Rcv 01B8 12 RxAna 01B9 03 Table 222. ISO/IEC15693 SLI 1/256 - DSC MFRC631 Product data sheet COMPANY PUBLIC Value for register EEPROM address (hex) Value (hex) DrvMode 01C0 8E TxAmp 01C1 10 DrvCon 01C2 01 TxI 01C3 06 TXCrcPreset 01C4 7B RXCrcPreset 01C5 7B TxDataNum 01C6 08 TxModWidth 01C7 00 TxSym10BurstLen 01C8 00 TxWaitCtrl 01C9 88 TxWaitLo 01CA A9 TxFrameCon 01CB 0F RxSofD 01CC 00 RxCtrl 01CD 02 RxWait 01CE 10 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 132 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) RxTreshold 01CF 44 Rcv 01D0 12 RxAna 01D1 06 Value for register EEPROM address (hex) Value (hex) DrvMode 01D4 8F TxAmp 01D5 10 DrvCon 01D6 01 TxI 01D7 06 TXCrcPreset 01D8 74 RXCrcPreset 01D9 7B TxDataNum 01DA 18 TxModWidth 01DB 00 TxSym10BurstLen 01DC 00 TxWaitCtrl 01DD 50 TxWaitLo 01DE 5C TxFrameCon 01DF 0F RxSofD 01E0 00 RxCtrl 01E1 03 RxWait 01E2 10 RxTreshold 01E3 4E Rcv 01E4 12 RxAna 01E5 06 Value for register EEPROM address (hex) Value (hex) DrvMode 01E8 8F TxAmp 01E9 10 DrvCon 01EA 09 TxI 01EB 0A TXCrcPreset 01EC 11 RXCrcPreset 01ED 91 TxDataNum 01EE 09 TxModWidth 01EF 00 TxSym10BurstLen 01F0 00 Table 223. EPC/UID - SSC -26 Table 224. EPC-V2 - 2/424 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 133 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) TxWaitCtrl 01F1 80 TxWaitLo 01F2 12 TxFrameCon 01F3 01 RxSofD 01F4 00 RxCtrl 01F5 03 RxWait 01F6 A0 RxTreshold 01F7 56 Rcv 01F8 12 RxAna 01F9 0F Value for register EEPROM address (hex) Value (hex) DrvMode 0200 8F TxAmp 0201 10 DrvCon 0202 09 TxI 0203 0A TXCrcPreset 0204 11 RXCrcPreset 0205 91 TxDataNum 0206 09 TxModWidth 0207 00 TxSym10BurstLen 0208 00 TxWaitCtrl 0209 80 TxWaitLo 020A 12 TxFrameCon 020B 01 RxSofD 020C 00 RxCtrl 020D 03 RxWait 020E A0 RxTreshold 020F 56 Rcv 0210 12 RxAna 0211 0F Value for register EEPROM address (hex) Value (hex) DrvMode 0214 8F TxAmp 0215 D0 DrvCon 0216 01 Table 225. EPC-V2 - 4/424 Table 226. EPC-V2 - 2/848 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 134 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Value for register EEPROM address (hex) Value (hex) TxI 0217 0A TXCrcPreset 0218 11 RXCrcPreset 0219 91 TxDataNum 021A 09 TxModWidth 021B 00 TxSym10BurstLen 021C 00 TxWaitCtrl 021D 80 TxWaitLo 021E 12 TxFrameCon 021F 01 RxSofD 0220 00 RxCtrl 0221 05 RxWait 0222 A0 RxTreshold 0223 26 Rcv 0224 12 RxAna 0225 0E Value for register EEPROM address (hex) Value (hex) DrvMode 0228 8F TxAmp 0229 D0 DrvCon 022A 01 TxI 022B 0A TXCrcPreset 022C 11 RXCrcPreset 022D 91 TxDataNum 022E 09 TxModWidth 022F 00 TxSym10BurstLen 0230 00 TxWaitCtrl 0231 80 TxWaitLo 0232 12 TxFrameCon 0233 01 RxSofD 0234 00 RxCtrl 0235 05 RxWait 0236 A0 RxTreshold 0237 26 Rcv 0238 12 RxAna 0239 0E Table 227. EPC-V2 - 4/848 MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 135 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Table 228. Jewel Value for register EEPROM address (hex) Value (hex) DrvMode 0240 8E TxAmp 0241 15 DrvCon 0242 11 TxI 0243 06 TXCrcPreset 0244 18 RXCrcPreset 0245 18 TxDataNum 0246 0F TxModWidth 0247 20 TxSym10BurstLen 0248 00 TxWaitCtrl 0249 40 TxWaitLo 024A 09 TxFrameCon 024B 4F RxSofD 024C 00 RxCtrl 024D 04 RxWait 024E 8F RxTreshold 024F 32 Rcv 0250 12 RxAna 0251 0A Table 229. ISO/IEC14443 - B 106 EMVCo Optimized MFRC631 Product data sheet COMPANY PUBLIC Value for register EEPROM address (hex) Value (hex) DrvMode 0254 8F TxAmp 0255 0E DrvCon 0256 09 TxI 0257 0A TXCrcPreset 0258 7B RXCrcPreset 0259 7B TxDataNum 025A 08 TxModWidth 025B 00 TxSym10BurstLen 025C 00 TxWaitCtrl 025D 01 TxWaitLo 025E 00 TxFrameCon 025F 05 RxSofD 0260 00 RxCtrl 0261 34 RxWait 0262 90 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 136 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus MFRC631 Product data sheet COMPANY PUBLIC Value for register EEPROM address (hex) Value (hex) RxTreshold 0263 9F Rcv 0264 12 RxAna 0265 03 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 137 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 18 Abbreviations Table 230. Abbreviations Acronym Description ADC Analog-to-Digital Converter BPSK Binary Phase Shift Keying CRC Cyclic Redundancy Check CW Continuous Wave EGT Extra Guard Time EMC Electro Magnetic Compatibility EMD Electro Magnetic Disturbance EOF End Of Frame EPC Electronic Product Code ETU Elementary Time Unit GPIO General Purpose Input/Output HBM Human Body Model 2 MFRC631 Product data sheet COMPANY PUBLIC I C Inter-Integrated Circuit IRQ Interrupt Request LFO Low Frequency Oscillator LPCD Low-Power Card Detection LSB Least Significant Bit MISO Master In Slave Out MOSI Master Out Slave In MSB Most Significant Bit NRZ Not Return to Zero NSS Not Slave Select PCD Proximity Coupling Device PLL Phase-Locked Loop RZ Return To Zero RX Receiver SAM Secure Access Module SOF Start Of Frame SPI Serial Peripheral Interface SW Software TTimer Timing of the clk period TX Transmitter UART Universal Asynchronous Receiver Transmitter UID Unique IDentification All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 138 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus MFRC631 Product data sheet COMPANY PUBLIC Acronym Description VCO Voltage Controlled Oscillator All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 139 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 19 References [1] Application note AN11019 CLRC663, MFRC630, MFRC631, SLRC610 Antenna Design Guide [2] Application note AN11783 CLRC663 plus Low Power Card Detection MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 140 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 20 Revision history Table 231. Revision history Document ID Release date Data sheet status Change notice Supersedes MFRC631 v.4.5 20180912 Product data sheet - MFRC631 v.4.4 Modifications: * Description of Low frequency timer in Section 7.8.3 more detailed now MFRC631 v.4.4 20180627 Modifications: * Editorial updates MFRC631 v.4.3 20171219 Modifications: * Deleted references to MICORE Application notes * Description for new product type MFRC63103 added * Section 19 updated MFRC631 v.4.2 20160427 Modifications: * Descriptive title updated MFRC631 v.4.1 20160211 Modifications: * Table: Quick reference data: Table notes [3] and [4] removed * Table: Characteristics: TVDD supply current value updated MFRC631 v.4.0 20151029 Modifications: * Table: Characteristics: - AVDD and DVDD min and max values added - IDD(TVDD) max value updated to 250 mA * Figure 10 "Connection to host with SPI": updated * Figure 19 "Register read and write access": updated MFRC631 v.3.3 20140204 Modifications: * * * * * * * * MFRC631 v.3.2 20130312 Modifications: * Update of EEPROM content * Descriptive title changed * Table 184 "PinOut register (address 45h)": corrected MFRC631 v.3.1 <tbd> MFRC631 Product data sheet COMPANY PUBLIC Product data sheet Product data sheet Product data sheet Product data sheet Product data sheet Product data sheet - MFRC631 v.4.3 - MFRC631 v.4.2 - MFRC631 v.4.1 - MFRC631 v.4.0 - - MFRC631 v.3.3 MFRC631 v.3.2 PVDD, TVDD data updated Information on FIFO size corrected Typing error corrected in description for LPCD WaterLevel and FIFOLength updated in register overview description WaterLevel and FIFOLength updated in register FIFOControl Waterlevel Register updated FIFOLength Register updated Section 8.15.2 "PinOut": Pin Out register description corrected Product data sheet Product data sheet - - All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 MFRC631 v.3.1 - (c) NXP B.V. 2018. All rights reserved. 141 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 21 Legal information 21.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 21.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. MFRC631 Product data sheet COMPANY PUBLIC Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 142 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 21.4 Licenses Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron's Contactless Card patents license for ISO/IEC 14443 B. RATP/Innovatron Technology The license includes the right to use the IC in systems and/or end-user equipment. Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/ IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP Semiconductors IC does not include a license to any NXP patent (or other IP right) covering combinations of those products with other products, whether hardware or software. 21.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2 I C-bus -- logo is a trademark of NXP B.V. MIFARE -- is a trademark of NXP B.V. DESFire -- is a trademark of NXP B.V. ICODE and I-CODE -- are trademarks of NXP B.V. MIFARE Plus -- is a trademark of NXP B.V. MIFARE Ultralight -- is a trademark of NXP B.V. MIFARE Classic -- is a trademark of NXP B.V. MFRC631 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 143 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. Tab. 19. Tab. 20. Tab. 21. Tab. 22. Tab. 23. Tab. 24. Tab. 25. Tab. 26. Tab. 27. Tab. 28. Tab. 29. Tab. 30. Tab. 31. Tab. 32. Tab. 33. Tab. 34. Tab. 35. Tab. 36. Tab. 37. Tab. 38. Tab. 39. Tab. 40. Tab. 41. Quick reference data MFRC63102HN ...............3 Quick reference data MFRC63103HN ...............3 Ordering information ..........................................4 Pin description ...................................................6 Interrupt sources ............................................... 9 Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic ....... 12 Communication overview for ISO/IEC 14443 B reader/writer .................................................14 Connection scheme for detecting the different interface types ...................................15 Byte Order for MOSI and MISO ...................... 16 Byte Order for MOSI and MISO ...................... 16 Address byte 0 register; address MOSI ...........16 Timing conditions SPI ..................................... 16 Settings of BR_T0 and BR_T1 ........................17 Selectable transfer speeds ..............................18 UART framing ................................................. 18 Byte Order to Read Data ................................ 18 Byte Order to Write Data ................................ 19 Timing parameter I2CL ................................... 24 SPI SAM connection ....................................... 26 Boundary scan command ............................... 26 Boundary scan path of the MFRC631 ............. 29 Settings for TX1 and TX2 ............................... 33 Setting residual carrier and modulation index by TXamp.set_residual_carrier .............. 33 Configuration for single or differential receiver ............................................................36 Register configuration of MFRC631 active antenna concept (DIGITAL) ............................ 37 Register configuration of MFRC631 active antenna concept (Antenna) ............................. 37 EEPROM memory organization ...................... 41 Production area (Page 0) ................................41 Product ID overview of CLRC663 family ......... 42 Configuration area (Page 0) ............................42 Interface byte .................................................. 42 Interface bits ....................................................43 Tx and Rx arrangements in the register set protocol area ................................................... 43 Register reset values (Hex.) (Page0) .............. 43 Register reset values (Hex.)(Page1 and page 2) ............................................................ 44 Crystal requirements recommendations .......... 45 Divider values for selected frequencies using the integerN PLL ................................... 46 Command set ..................................................49 Predefined protocol overview RXFor more protocol details please refer to Section 7 "Functional description". .................................. 52 Predefined protocol overview TXFor more protocol details please refer to Section 7 "Functional description". .................................. 53 Behavior of register bits and their designation ...................................................... 55 MFRC631 Product data sheet COMPANY PUBLIC Tab. 42. Tab. 43. Tab. 44. Tab. 45. Tab. 46. Tab. 47. Tab. 48. Tab. 49. Tab. 50. Tab. 51. Tab. 52. Tab. 53. Tab. 54. Tab. 55. Tab. 56. Tab. 57. Tab. 58. Tab. 59. Tab. 60. Tab. 61. Tab. 62. Tab. 63. Tab. 64. Tab. 65. Tab. 66. Tab. 67. Tab. 68. Tab. 69. Tab. 70. Tab. 71. Tab. 72. Tab. 73. Tab. 74. Tab. 75. Tab. 76. Tab. 77. Tab. 78. Tab. 79. Tab. 80. Tab. 81. Tab. 82. Tab. 83. Tab. 84. Tab. 85. Tab. 86. Tab. 87. Tab. 88. Tab. 89. Tab. 90. Tab. 91. Tab. 92. Tab. 93. Tab. 94. Tab. 95. MFRC631 registers overview .......................... 55 Command register (address 00h) ....................57 Command bits ................................................. 58 HostCtrl register (address 01h); ...................... 58 HostCtrl bits .....................................................58 FIFOControl register (address 02h); ............... 59 FIFOControl bits .............................................. 59 WaterLevel register (address 03h); ................. 59 WaterLevel bits ............................................... 60 FIFOLength register (address 04h); reset value: 00h ........................................................60 FIFOLength bits .............................................. 60 FIFOData register (address 05h); ................... 60 FIFOData bits ..................................................61 IRQ0 register (address 06h); reset value: 00h .................................................................. 61 IRQ0 bits ......................................................... 61 IRQ1 register (address 07h) ............................62 IRQ1 bits ......................................................... 62 IRQ0En register (address 08h) ....................... 62 IRQ0En bits .....................................................63 IRQ1EN register (address 09h); ......................63 IRQ1EN bits .................................................... 63 Error register (address 0Ah) ............................64 Error bits ..........................................................64 Status register (address 0Bh) ......................... 65 Status bits ....................................................... 65 RxBitCtrl register (address 0Ch); .................... 66 RxBitCtrl bits ................................................... 66 RxColl register (address 0Dh); ........................66 RxColl bits ....................................................... 67 TControl register (address 0Eh) ...................... 67 TControl bits ....................................................67 T0Control register (address 0Fh); ................... 68 T0Control bits ..................................................68 T0ReloadHi register (address 10h); ................ 69 T0ReloadHi bits ...............................................69 T0ReloadLo register (address 11h); ................69 T0ReloadLo bits .............................................. 69 T0CounterValHi register (address 12h) ...........69 T0CounterValHi bits ........................................ 70 T0CounterValLo register (address 13h) .......... 70 T0CounterValLo bits ........................................70 T1Control register (address 14h); ................... 70 T1Control bits ..................................................70 T0ReloadHi register (address 15h) ................. 71 T1ReloadHi bits ...............................................71 T1ReloadLo register (address 16h) .................71 T1ReloadValLo bits ......................................... 71 T1CounterValHi register (address 17h) ...........72 T1CounterValHi bits ........................................ 72 T1CounterValLo register (address 18h) .......... 72 T1CounterValLo bits ........................................72 T2Control register (address 19h) .................... 72 T2Control bits ..................................................72 T2ReloadHi register (address 1Ah) .................73 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 144 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Tab. 96. Tab. 97. Tab. 98. Tab. 99. Tab. 100. Tab. 101. Tab. 102. Tab. 103. Tab. 104. Tab. 105. Tab. 106. Tab. 107. Tab. 108. Tab. 109. Tab. 110. Tab. 111. Tab. 112. Tab. 113. Tab. 114. Tab. 115. Tab. 116. Tab. 117. Tab. 118. Tab. 119. Tab. 120. Tab. 121. Tab. 122. Tab. 123. Tab. 124. Tab. 125. Tab. 126. Tab. 127. Tab. 128. Tab. 129. Tab. 130. Tab. 131. Tab. 132. Tab. 133. Tab. 134. Tab. 135. Tab. 136. Tab. 137. Tab. 138. Tab. 139. Tab. 140. Tab. 141. Tab. 142. Tab. 143. Tab. 144. Tab. 145. Tab. 146. Tab. 147. Tab. 148. Tab. 149. Tab. 150. Tab. 151. Tab. 152. Tab. 153. T2Reload bits .................................................. 73 T2ReloadLo register (address 1Bh) ................ 73 T2ReloadLo bits .............................................. 74 T2CounterValHi register (address 1Ch) .......... 74 T2CounterValHi bits ........................................ 74 T2CounterValLo register (address 1Dh) ..........74 T2CounterValLo bits ........................................74 T3Control register (address 1Eh) .................... 74 T3Control bits ..................................................75 T3ReloadHi register (address 1Fh); ................ 75 T3ReloadHi bits ...............................................75 T3ReloadLo register (address 20h) .................75 T3ReloadLo bits .............................................. 76 T3CounterValHi register (address 21h) ...........76 T3CounterValHi bits ........................................ 76 T3CounterValLo register (address 22h) .......... 76 T3CounterValLo bits ........................................76 T4Control register (address 23h) .................... 77 T4Control bits ..................................................77 T4ReloadHi register (address 24h) ................. 78 T4ReloadHi bits ...............................................78 T4ReloadLo register (address 25h) .................78 T4ReloadLo bits .............................................. 78 T4CounterValHi register (address 26h) ...........78 T4CounterValHi bits ........................................ 78 T4CounterValLo register (address 27h) .......... 79 T4CounterValLo bits ........................................79 DrvMode register (address 28h) ......................79 DrvMode bits ................................................... 79 TxAmp register (address 29h) .........................80 TxAmp bits ...................................................... 80 TxCon register (address 2Ah) ......................... 80 TxCon bits ....................................................... 80 Txl register (address 2Bh) ...............................81 Txl bits .............................................................81 TXCrcPreset register (address 2Ch) ............... 81 TxCrcPreset bits ..............................................81 Transmitter CRC preset value configuration ....82 RxCrcCon register (address 2Dh) ................... 82 RxCrcCon bits ................................................. 82 Receiver CRC preset value configuration ....... 82 TxDataNum register (address 2Eh) .................83 TxDataNum bits .............................................. 83 TxDataModWidth register (address 2Fh) ........ 83 TxDataModWidth bits ...................................... 84 TxSym10BurstLen register (address 30h) ....... 84 TxSym10BurstLen bits .................................... 84 TxWaitCtrl register (address 31h); reset value: C0h ....................................................... 85 TXWaitCtrl bits ................................................ 85 TxWaitLo register (address 32h) ..................... 85 TxWaitLo bits .................................................. 86 FrameCon register (address 33h) ................... 86 FrameCon bits .................................................86 RxSofD register (address 34h) ........................86 RxSofD bits ..................................................... 87 RxCtrl register (address 35h) .......................... 87 RxCtrl bits ........................................................87 RxWait register (address 36h) ........................ 88 MFRC631 Product data sheet COMPANY PUBLIC Tab. 154. Tab. 155. Tab. 156. Tab. 157. Tab. 158. Tab. 159. Tab. 160. Tab. 161. Tab. 162. Tab. 163. Tab. 164. Tab. 165. Tab. 166. Tab. 167. Tab. 168. Tab. 169. Tab. 170. Tab. 171. Tab. 172. Tab. 173. Tab. 174. Tab. 175. Tab. 176. Tab. 177. Tab. 178. Tab. 179. Tab. 180. Tab. 181. Tab. 182. Tab. 183. Tab. 184. Tab. 185. Tab. 186. Tab. 187. Tab. 188. Tab. 189. Tab. 190. Tab. 191. Tab. 192. Tab. 193. Tab. 194. Tab. 195. Tab. 196. Tab. 197. Tab. 198. Tab. 199. Tab. 200. Tab. 201. Tab. 202. Tab. 203. Tab. 204. RxWait bits ...................................................... 88 RxThreshold register (address 37h) ................ 88 RxThreshold bits ............................................. 88 Rcv register (address 38h) ..............................88 Rcv bits ........................................................... 89 RxAna register (address 39h) ......................... 89 RxAna bits .......................................................89 Effect of gain and highpass corner register settings ............................................................ 90 SerialSpeed register (address3Bh); reset value: 7Ah ....................................................... 90 SerialSpeed bits .............................................. 91 RS232 speed settings ..................................... 91 LFO_Trim register (address 3Ch) ................... 91 LFO_Trim bits ................................................. 91 PLL_Ctrl register (address3Dh) .......................92 PLL_Ctrl register bits .......................................92 Setting of feedback divider PLLDiv_FB [1:0] ....92 PLLDiv_Out register (address 3Eh) ................ 92 PLLDiv_Out bits .............................................. 93 Setting for the output divider ratio PLLDiv_Out [7:0] ............................................. 93 LPCD_QMin register (address 3Fh) ................ 93 LPCD_QMin bits ............................................. 93 LPCD_QMax register (address 40h) ............... 94 LPCD_QMax bits ............................................ 94 LPCD_IMin register (address 41h) ..................94 LPCD_IMin bits ............................................... 94 LPCD_Result_I register (address 42h) ............95 LPCD_I_Result bits ......................................... 95 LPCD_Result_Q register (address 43h) ..........95 LPCD_Q_Result bits ....................................... 95 LPCD_Options register (address 3Ah) ............ 95 LPCD_Options .................................................96 PinEn register (address 44h) .......................... 96 PinEn bits ........................................................ 96 PinOut register (address 45h) ......................... 97 PinOut bits .......................................................97 PinIn register (address 46h) ............................97 PinIn bits ......................................................... 97 SigOut register (address 47h) ......................... 98 SigOut bits .......................................................98 Version register (address 7Fh) ........................98 Version bits ..................................................... 99 Limiting values .............................................. 100 Operating conditions MFRC63102HN ........... 101 Operating conditions MFRC63103HN ........... 101 Thermal characteristics ................................. 102 Characteristics ...............................................103 SPI timing characteristics .............................. 106 I2C-bus timing in fast mode and fast mode plus ................................................................ 106 Protocol Number 00: ISO/IEC14443-A 106 / MIFARE Classic ............................................ 119 Protocol Number 01: ISO/IEC14443-A 212/ MIFARE Classic ............................................ 120 Protocol Number 02: ISO/IEC14443-A 424/ MIFARE Classic ............................................ 120 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 145 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Tab. 205. Protocol Number 03: ISO/IEC14443-A 848/ MIFARE Classic ............................................ 121 Tab. 206. Protocol Number 04: ISO/IEC14443-B 106 ... 122 Tab. 207. Protocol Number 05: ISO/IEC14443-B 212 ... 123 Tab. 208. Protocol Number 06: ISO/IEC14443-B 424 ... 123 Tab. 209. Protocol Number 07: ISO/IEC14443-B 848 ... 124 Tab. 210. ISO/IEC14443-A 106 / MIFARE Classic ........125 Tab. 211. ISO/IEC14443-A 212/ MIFARE Classic .........126 Tab. 212. ISO/IEC14443-A 424/ MIFARE Classic .........126 Tab. 213. ISO/IEC14443-A 848/ MIFARE Classic .........127 Tab. 214. ISO/IEC14443-B 106 .....................................127 Tab. 215. ISO/IEC14443-B 212 .....................................128 Tab. 216. ISO/IEC14443-B 424 .....................................129 Tab. 217. ISO/IEC14443-B 848 .....................................129 MFRC631 Product data sheet COMPANY PUBLIC Tab. 218. Tab. 219. Tab. 220. Tab. 221. Tab. 222. Tab. 223. Tab. 224. Tab. 225. Tab. 226. Tab. 227. Tab. 228. Tab. 229. Tab. 230. Tab. 231. JIS X 6319-4 (FeliCa) 212 ............................ 130 JIS X 6319-4 (FeliCa) 424 ............................ 130 ISO/IEC15693 SLI 1/4 - SSC- 26 ..................131 ISO/IEC15693 SLI 1/4 - SSC-53 ................... 132 ISO/IEC15693 SLI 1/256 - DSC ....................132 EPC/UID - SSC -26 ...................................... 133 EPC-V2 - 2/424 .............................................133 EPC-V2 - 4/424 .............................................134 EPC-V2 - 2/848 .............................................134 EPC-V2 - 4/848 .............................................135 Jewel ............................................................. 136 ISO/IEC14443 - B 106 EMVCo Optimized .... 136 Abbreviations .................................................138 Revision history ............................................. 141 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 146 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Fig. 15. Fig. 16. Fig. 17. Fig. 18. Fig. 19. Simplified block diagram of the MFRC631 ........ 5 Pinning configuration HVQFN32 (SOT617-1) ........................................................6 Detailed block diagram of the MFRC631 ...........8 Read/write mode ............................................. 12 Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic ....... 12 Data coding and framing according to ISO/ IEC 14443 A ................................................... 13 Read/write mode for ISO/IEC 14443 type A and read/write mode for MIFARE Classic ....... 13 SOF and EOF according to ISO/IEC 14443 B ...................................................................... 14 Connection to host with SPI ............................15 Connection to host with SPI ............................17 Example for UART Read ................................ 19 Example diagram for a UART write .................19 I2C-bus interface ............................................. 20 Bit transfer on the I2C-bus. ............................. 20 START and STOP conditions ......................... 21 Acknowledge on the I2C- bus ......................... 22 Data transfer on the I2C- bus ......................... 22 First byte following the START procedure ....... 22 Register read and write access .......................24 MFRC631 Product data sheet COMPANY PUBLIC Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Fig. 26. Fig. 27. Fig. 28. Fig. 29. Fig. 30. Fig. 31. Fig. 32. Fig. 33. Fig. 34. Fig. 35. Fig. 36. Fig. 37. Fig. 38. I2C interface enables convenient MIFARE SAM integration ...............................................26 Boundary scan cell path structure ................... 28 General dependences of modulation .............. 32 Example 1: overshoot_t1 = 2d; overhoot_t2 = 5d. ................................................................ 34 Example 2: overshoot_t1 = 0d; overhoot_t2 = 5d ................................................................. 35 Block diagram of receiver circuitry .................. 36 Block diagram of the active Antenna concept .. 37 Overview SIGIN/SIGOUT Signal Routing ........39 Sector arrangement of the EEPROM .............. 41 Quartz connection ........................................... 45 Internal PDown to voltage regulator logic ........49 Pin RX input voltage ..................................... 105 Timing for fast and standard mode devices on the I2C-bus .............................................. 107 Typical application antenna circuit diagram ... 108 Package outline SOT617-1 (HVQFN32) ........111 Packing information 1 tray .............................114 Packing information 5 tray .............................115 Tray details ....................................................116 Packing information Reel .............................. 117 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 147 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus Contents 1 2 3 4 5 6 6.1 7 7.1 7.2 7.2.1 7.2.1.1 7.2.1.2 7.2.1.3 7.2.1.4 7.2.1.5 7.3 7.3.1 General description ............................................ 1 Features and benefits .........................................2 Quick reference data .......................................... 3 Ordering information .......................................... 4 Block diagram ..................................................... 5 Pinning information ............................................ 6 Pin description ................................................... 6 Functional description ........................................8 Interrupt controller ............................................. 8 Timer module ...................................................10 Timer modes ....................................................10 Time-Out- and Watch-Dog-Counter .................11 Wake-up timer ................................................. 11 Stop watch .......................................................11 Programmable one-shot timer ......................... 11 Periodical trigger ..............................................11 Contactless interface unit ................................ 12 Communication mode for ISO/IEC14443 type A and for MIFARE Classic .......................12 7.3.2 ISO/IEC14443B functionality ........................... 13 7.4 Host interfaces .................................................14 7.4.1 Host interface configuration ............................. 14 7.4.2 SPI interface .................................................... 15 7.4.2.1 General ............................................................ 15 7.4.2.2 Read data ........................................................ 15 7.4.2.3 Write data ........................................................ 16 7.4.2.4 Address byte ....................................................16 7.4.2.5 Timing Specification SPI ..................................16 7.4.3 RS232 interface ............................................... 17 7.4.3.1 Selection of the transfer speeds ...................... 17 7.4.3.2 Framing ............................................................18 7.4.4 I2C-bus interface ............................................. 19 7.4.4.1 General ............................................................ 20 7.4.4.2 I2C Data validity .............................................. 20 7.4.4.3 I2C START and STOP conditions ................... 21 7.4.4.4 I2C byte format ................................................21 7.4.4.5 I2C Acknowledge .............................................21 7.4.4.6 I2C 7-bit addressing ........................................ 22 7.4.4.7 I2C-register write access ................................. 23 7.4.4.8 I2C-register read access ................................. 23 7.4.4.9 I2CL-bus interface ........................................... 24 7.4.5 SAM interface .................................................. 25 7.4.5.1 SAM functionality ............................................. 25 7.4.5.2 SAM connection .............................................. 26 7.4.6 Boundary scan interface ..................................26 7.4.6.1 Interface signals .............................................. 27 7.4.6.2 Test Clock (TCK) .............................................27 7.4.6.3 Test Mode Select (TMS) ................................. 27 7.4.6.4 Test Data Input (TDI) ...................................... 28 7.4.6.5 Test Data Output (TDO) .................................. 28 7.4.6.6 Data register .................................................... 28 7.4.6.7 Boundary scan cell .......................................... 28 7.4.6.8 Boundary scan path ........................................ 28 7.4.6.9 Boundary Scan Description Language (BSDL) ............................................................. 29 7.4.6.10 Non-IEEE1149.1 commands ........................... 30 MFRC631 Product data sheet COMPANY PUBLIC 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.6 7.6.1 7.6.2 7.6.2.1 7.6.2.2 7.6.3 7.6.3.1 7.6.3.2 7.6.4 7.6.5 7.7 7.7.1 7.7.2 7.7.2.1 Buffer ............................................................... 30 Overview .......................................................... 30 Accessing the FIFO buffer ...............................30 Controlling the FIFO buffer .............................. 31 Status Information about the FIFO buffer ........ 31 Analog interface and contactless UART .......... 31 General ............................................................ 32 TX transmitter .................................................. 32 Overshoot protection ....................................... 34 Bit generator .................................................... 35 Receiver circuitry ............................................. 35 General ............................................................ 35 Block diagram ..................................................35 Active antenna concept ................................... 37 Symbol generator ............................................ 40 Memory ............................................................ 40 Memory overview .............................................40 EEPROM memory organization .......................40 Product information and configuration - Page 0 ....................................................................... 41 7.7.3 EEPROM initialization content LoadProtocol ... 43 7.8 Clock generation ..............................................45 7.8.1 Crystal oscillator .............................................. 45 7.8.2 IntegerN PLL clock line ................................... 46 7.8.3 Low Frequency Oscillator (LFO) ......................46 7.9 Power management .........................................47 7.9.1 Supply concept ................................................ 47 7.9.2 Power reduction mode .....................................47 7.9.2.1 Power-down ..................................................... 47 7.9.2.2 Standby mode ................................................. 48 7.9.2.3 Modem off mode ............................................. 48 7.9.3 Low-Power Card Detection (LPCD) ................. 48 7.9.4 Reset and start-up time ................................... 48 7.10 Command set .................................................. 49 7.10.1 General ............................................................ 49 7.10.2 Command set overview ................................... 49 7.10.3 Command functionality .................................... 50 7.10.3.1 Idle command .................................................. 50 7.10.3.2 LPCD command .............................................. 50 7.10.3.3 Load key command ......................................... 50 7.10.3.4 MFAuthent command ...................................... 51 7.10.3.5 Receive command ........................................... 51 7.10.3.6 Transmit command .......................................... 51 7.10.3.7 Transceive command ...................................... 51 7.10.3.8 WriteE2 command ........................................... 52 7.10.3.9 WriteE2PAGE command ................................. 52 7.10.3.10 ReadE2 command ........................................... 52 7.10.3.11 LoadReg command ......................................... 52 7.10.3.12 LoadProtocol command ...................................52 7.10.3.13 LoadKeyE2 command ..................................... 53 7.10.3.14 StoreKeyE2 command .....................................53 7.10.3.15 GetRNR command .......................................... 54 7.10.3.16 SoftReset command ........................................ 54 8 MFRC631 registers ............................................55 8.1 Register bit behavior ....................................... 55 8.2 MFRC631 registers overview .......................... 55 All information provided in this document is subject to legal disclaimers. Rev. 4.5 -- 12 September 2018 227445 (c) NXP B.V. 2018. All rights reserved. 148 / 149 MFRC631 NXP Semiconductors High-performance ISO/IEC 14443 A/B frontend MFRC631 and MFRC631 plus 8.3 8.3.1 8.4 8.4.1 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.7 8.7.1 8.7.2 8.7.3 8.7.4 8.8 8.8.1 8.8.2 8.8.2.1 8.8.2.2 8.8.2.3 8.8.2.4 8.8.2.5 8.8.2.6 8.8.2.7 8.8.2.8 8.8.2.9 8.8.2.10 8.8.2.11 8.8.2.12 8.8.2.13 8.8.2.14 8.8.2.15 8.8.2.16 8.8.2.17 8.8.2.18 8.8.2.19 8.8.2.20 8.8.2.21 8.8.2.22 8.8.2.23 8.8.2.24 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.10 8.10.1 8.10.2 8.11 8.11.1 Command configuration ...................................57 Command ........................................................ 57 SAM configuration register .............................. 58 HostCtrl ............................................................ 58 FIFO configuration register .............................. 59 FIFOControl ..................................................... 59 WaterLevel .......................................................59 FIFOLength ......................................................60 FIFOData ......................................................... 60 Interrupt configuration registers ....................... 61 IRQ0 register ................................................... 61 IRQ1 register ................................................... 62 IRQ0En register ............................................... 62 IRQ1En ............................................................ 63 Contactless interface configuration registers ... 64 Error ................................................................. 64 Status ...............................................................65 RxBitCtrl ...........................................................66 RxColl .............................................................. 66 Timer configuration registers ........................... 67 TControl ........................................................... 67 T0Control ......................................................... 68 T0ReloadHi ...................................................... 69 T0ReloadLo ..................................................... 69 T0CounterValHi ............................................... 69 T0CounterValLo ...............................................70 T1Control ......................................................... 70 T1ReloadHi ...................................................... 71 T1ReloadLo ..................................................... 71 T1CounterValHi ............................................... 71 T1CounterValLo ...............................................72 T2Control ......................................................... 72 T2ReloadHi ...................................................... 73 T2ReloadLo ..................................................... 73 T2CounterValHi ............................................... 74 T2CounterValLoReg ........................................ 74 T3Control ......................................................... 74 T3ReloadHi ...................................................... 75 T3ReloadLo ..................................................... 75 T3CounterValHi ............................................... 76 T3CounterValLo ...............................................76 T4Control ......................................................... 77 T4ReloadHi ...................................................... 77 T4ReloadLo ..................................................... 78 T4CounterValHi ............................................... 78 T4CounterValLo ...............................................79 Transmitter configuration registers .................. 79 TxMode ............................................................ 79 TxAmp ..............................................................79 TxCon .............................................................. 80 Txl .................................................................... 81 CRC configuration registers .............................81 TxCrcPreset ..................................................... 81 RxCrcCon ........................................................ 82 Transmitter configuration registers .................. 83 TxDataNum ......................................................83 8.11.2 8.11.3 8.11.4 8.11.5 8.12 8.13 8.13.1 8.13.2 8.13.3 8.13.4 8.13.5 8.13.6 8.14 8.14.1 8.14.2 8.14.3 8.14.4 8.15 8.15.1 8.15.2 8.15.3 8.15.4 8.15.5 8.15.6 8.16 8.16.1 8.16.2 8.16.3 8.16.4 8.17 8.17.1 9 10 11 12 12.1 13 13.1 13.1.1 13.1.2 13.1.3 13.1.4 14 15 16 17 17.1 17.2 18 19 20 21 TxDATAModWidth ........................................... 83 TxSym10BurstLen ........................................... 84 TxWaitCtrl ........................................................ 85 TxWaitLo ..........................................................85 FrameCon ........................................................ 86 Receiver configuration registers ...................... 86 RxSofD .............................................................86 RxCtrl ............................................................... 87 RxWait ............................................................. 88 RxThreshold .....................................................88 Rcv ...................................................................88 RxAna .............................................................. 89 Clock configuration .......................................... 90 SerialSpeed ..................................................... 90 LFO_Trimm ......................................................91 PLL_Ctrl Register ............................................ 91 PLLDiv_Out ......................................................92 Low-power card detection configuration registers ........................................................... 93 LPCD_QMin .....................................................93 LPCD_QMax ....................................................94 LPCD_IMin .......................................................94 LPCD_Result_I ................................................ 95 LPCD_Result_Q .............................................. 95 LPCD_Options ................................................. 95 Pin configuration .............................................. 96 PinEn ............................................................... 96 PinOut .............................................................. 97 PinIn .................................................................97 SigOut .............................................................. 98 Version register ............................................... 98 Version .............................................................98 Limiting values ................................................ 100 Recommended operating conditions ............ 101 Thermal characteristics .................................. 102 Characteristics ................................................ 103 Timing characteristics .................................... 106 Application information .................................. 108 Antenna design description ........................... 108 EMC low pass filter ....................................... 108 Antenna matching ..........................................109 Receiving circuit .............................................109 Antenna coil ...................................................109 Package outline ...............................................111 Handling information ...................................... 113 Packing information ........................................114 Appendix .......................................................... 119 LoadProtocol command register initialization . 119 MFRC63103 EEPROM configuration ............ 125 Abbreviations .................................................. 138 References ....................................................... 140 Revision history .............................................. 141 Legal information ............................................ 142 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. (c) NXP B.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 September 2018 Document identifier: MFRC631 Document number: 227445