To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
Document No. U17473EJ2V0UD00 (2nd edition)
Date Published September 2006 NS CP(K)
Printed in Japan
2005
μ
PD78F0393
μ
PD78F0394
μ
PD78F0395
μ
PD78F0396
μ
PD78F0397
μ
PD78F0397D
78K0/LG2
8-Bit Single-Chip Microcontrollers
With LCD Controller/Driver
User’s Manual
User’s Manual U17473EJ2V0UD
2
[MEMO]
User’s Manual U17473EJ2V0UD 3
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
User’s Manual U17473EJ2V0UD
4
EEPROM is a trademark of NEC Electronics Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
User’s Manual U17473EJ2V0UD 5
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
The information in this document is current as of September, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
User’s Manual U17473EJ2V0UD
6
INTRODUCTION
Readers This manual is intended for user engineers who wish to understand the functions of the
78K0/LG2 and design and develop application systems and programs for these devices.
The target products are as follows.
78K0/LG2:
μ
PD78F0393, 78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The 78K0/LG2 manual is separated into two parts: this manual and the instructions
edition (common to the 78K/0 Series).
78K0/LG2
User’s Manual
(This Manual)
78K/0 Series
User’s Manual
Instructions
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications
• CPU functions
• Instruction set
• Explanation of each instruction
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major
revised points. The revised points can be easily searched by copying an “<R>” in
the PDF file and specifying it in the “Find what:” field.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a
reserved word in the RA78K0, and is defined as an sfr variable using the
#pragma sfr directive in the CC78K0.
• To check the details of a register when you know the register name:
→ Refer to APPENDIX B REGISTER INDEX.
• To know details of the 78K/0 Series instructions:
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
User’s Manual U17473EJ2V0UD 7
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
... ×××× or ××××B
Decimal
... ××××
Hexadecimal
... ××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
78K0/LG2 User’s Manual This manual
78K/0 Series Instructions User’s Manual U12326E
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name Document No.
Operation U17199E
Language U17198E
RA78K0 Ver. 3.80 Assembler Package
Structured Assembly Language U17197E
Operation U17201E CC78K0 Ver. 3.70 C Compiler
Language U17200E
ID78K0-QB Ver. 2.90 Integrated Debugger Operation U17437E
PM plus Ver. 5.20 U16934E
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name Document No.
QB-78K0LX2 In-Circuit Emulator U17468E
QB-78K0MINI On-Chip Debug Emulator U17029E
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP4 Flash Memory Programmer User’s Manual U15260E
PG-FPL3 Flash Memory Programmer User’s Manual U17454E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U17473EJ2V0UD
8
Other Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
User’s Manual U17473EJ2V0UD 9
CONTENTS
CHAPTER 1 OUTLINE......................................................................................................................................................................17
1.1 Features ........................................................................................................................................ 17
1.2 Applications.................................................................................................................................. 18
1.3 Ordering Information ................................................................................................................... 18
1.4 Pin Configuration (Top View)...................................................................................................... 19
1.5 Configuration................................................................................................................................ 22
1.6 78K0/Lx2 Series Lineup............................................................................................................... 23
1.7 Block Diagram .............................................................................................................................. 25
1.8 Outline of Functions .................................................................................................................... 26
CHAPTER 2 PIN FUNCTIONS.......................................................................................................................................................29
2.1 Pin Function List .......................................................................................................................... 29
2.2 Description of Pin Functions ...................................................................................................... 33
2.2.1 P00 to P06 (port 0)...........................................................................................................................33
2.2.2 P10 to P17 (port 1)...........................................................................................................................34
2.2.3 P20 to P27 (port 2)...........................................................................................................................35
2.2.4 P30 to P33 (port 3)...........................................................................................................................35
2.2.5 P60, P61 (port 6) .............................................................................................................................36
2.2.6 P70 to P77 (port 7)...........................................................................................................................36
2.2.7 P120 to P124 (port 12).....................................................................................................................36
2.2.8 AVREF ...............................................................................................................................................37
2.2.9 AVSS.................................................................................................................................................37
2.2.10 S0 to S39 .......................................................................................................................................37
2.2.11 COM0 to COM3 .............................................................................................................................37
2.2.12 LVDD ...............................................................................................................................................37
2.2.13 LVSS ...............................................................................................................................................37
2.2.14 VLC0 to VLC2 ....................................................................................................................................38
2.2.15 CAPH, CAPL .................................................................................................................................38
2.2.16 RESET...........................................................................................................................................38
2.2.17 REGC ............................................................................................................................................38
2.2.18 VDD .................................................................................................................................................38
2.2.19 VSS .................................................................................................................................................38
2.2.20 FLMD0 ...........................................................................................................................................38
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 39
CHAPTER 3 CPU ARCHITECTURE ............................................................................................................................................43
3.1 Memory Space.............................................................................................................................. 43
3.1.1 Internal program memory space ......................................................................................................50
3.1.2 Memory bank (
μ
PD78F0396, 78F0397, and 78F0397D only) .........................................................51
3.1.3 Internal data memory space ............................................................................................................51
3.1.4 Special function register (SFR) area................................................................................................52
3.1.5 Data memory addressing.................................................................................................................52
3.2 Processor Registers .................................................................................................................... 58
3.2.1 Control registers...............................................................................................................................58
User’s Manual U17473EJ2V0UD
10
3.2.2 General-purpose registers .............................................................................................................. 62
3.2.3 Special function registers (SFRs).................................................................................................... 63
3.3 Instruction Address Addressing................................................................................................. 68
3.3.1 Relative addressing......................................................................................................................... 68
3.3.2 Immediate addressing..................................................................................................................... 69
3.3.3 Table indirect addressing ................................................................................................................ 70
3.3.4 Register addressing ........................................................................................................................ 70
3.4 Operand Address Addressing .................................................................................................... 71
3.4.1 Implied addressing .......................................................................................................................... 71
3.4.2 Register addressing ........................................................................................................................ 72
3.4.3 Direct addressing ............................................................................................................................ 73
3.4.4 Short direct addressing ................................................................................................................... 74
3.4.5 Special function register (SFR) addressing..................................................................................... 75
3.4.6 Register indirect addressing............................................................................................................ 76
3.4.7 Based addressing ........................................................................................................................... 77
3.4.8 Based indexed addressing.............................................................................................................. 78
3.4.9 Stack addressing............................................................................................................................. 79
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)............80
4.1 Memory Bank ................................................................................................................................ 80
4.2 Memory Bank Select Register (BANK) ....................................................................................... 81
4.3 Selecting Memory Bank............................................................................................................... 82
4.3.1 Referencing values between memory banks................................................................................... 82
4.3.2 Branching instruction between memory banks................................................................................ 84
4.3.3 Subroutine call between memory banks ......................................................................................... 86
4.3.4 Instruction branch to bank area by interrupt.................................................................................... 88
CHAPTER 5 PORT FUNCTIONS ..................................................................................................................................................90
5.1 Port Functions .............................................................................................................................. 90
5.2 Port Configuration........................................................................................................................ 92
5.2.1 Port 0 .............................................................................................................................................. 93
5.2.2 Port 1 .............................................................................................................................................. 99
5.2.3 Port 2 .............................................................................................................................................104
5.2.4 Port 3 .............................................................................................................................................105
5.2.5 Port 6 .............................................................................................................................................107
5.2.6 Port 7 .............................................................................................................................................108
5.2.7 Port 12 ...........................................................................................................................................109
5.3 Registers Controlling Port Function ........................................................................................ 111
5.4 Port Function Operations .......................................................................................................... 115
5.4.1 Writing to I/O port...........................................................................................................................115
5.4.2 Reading from I/O port.....................................................................................................................115
5.4.3 Operations on I/O port....................................................................................................................115
5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 116
5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 118
CHAPTER 6 CLOCK GENERATOR ......................................................................................................................................... 119
6.1 Functions of Clock Generator................................................................................................... 119
User’s Manual U17473EJ2V0UD 11
6.2 Configuration of Clock Generator ............................................................................................ 120
6.3 Registers Controlling Clock Generator ................................................................................... 122
6.4 System Clock Oscillator ............................................................................................................ 131
6.4.1 X1 oscillator ...................................................................................................................................131
6.4.2 XT1 oscillator .................................................................................................................................131
6.4.3 When subsystem clock is not used................................................................................................134
6.4.4 Internal high-speed oscillator .........................................................................................................134
6.4.5 Internal low-speed oscillator ..........................................................................................................134
6.4.6 Prescaler........................................................................................................................................134
6.5 Clock Generator Operation ....................................................................................................... 135
6.6 Controlling Clock ....................................................................................................................... 139
6.6.1 Example of controlling high-speed system clock ...........................................................................139
6.6.2 Example of controlling internal high-speed oscillation clock ..........................................................142
6.6.3 Example of controlling subsystem clock ........................................................................................144
6.6.4 Example of controlling internal low-speed oscillation clock............................................................146
6.6.5 Clocks supplied to CPU and peripheral hardware .........................................................................146
6.6.6 CPU clock status transition diagram ..............................................................................................147
6.6.7 Condition before changing CPU clock and processing after changing CPU clock.........................152
6.6.8 Time required for switchover of CPU clock and main system clock...............................................153
6.6.9 Conditions before clock oscillation is stopped................................................................................154
6.6.10 Peripheral hardware and source clocks.......................................................................................155
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01......................................................................................... 156
7.1 Functions of 16-Bit Timer/Event Counters 00 and 01............................................................. 156
7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 ...................................................... 157
7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 ............................................. 163
7.4 Operation of 16-Bit Timer/Event Counters 00 and 01............................................................. 175
7.4.1 Interval timer operation ..................................................................................................................175
7.4.2 Square wave output operation .......................................................................................................178
7.4.3 External event counter operation ...................................................................................................181
7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input..........................................185
7.4.5 Free-running timer operation .........................................................................................................201
7.4.6 PPG output operation ....................................................................................................................210
7.4.7 One-shot pulse output operation....................................................................................................213
7.4.8 Pulse width measurement operation..............................................................................................218
7.5 Special Use of TM0n .................................................................................................................. 227
7.5.1 Rewriting CR01n during TM0n operation.......................................................................................227
7.5.2 Setting LVS0n and LVR0n .............................................................................................................227
7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01............................................................. 229
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51........................................................................................... 233
8.1 Functions of 8-Bit Timer/Event Counters 50 and 51............................................................... 233
8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 ........................................................ 233
8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ............................................... 236
8.4 Operations of 8-Bit Timer/Event Counters 50 and 51............................................................. 241
8.4.1 Operation as interval timer.............................................................................................................241
8.4.2 Operation as external event counter ..............................................................................................243
8.4.3 Square-wave output operation.......................................................................................................244
User’s Manual U17473EJ2V0UD
12
8.4.4 PWM output operation ...................................................................................................................245
8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................... 249
CHAPTER 9 8-BIT TIMERS H0 AND H1 ............................................................................................................................... 250
9.1 Functions of 8-Bit Timers H0 and H1 ....................................................................................... 250
9.2 Configuration of 8-Bit Timers H0 and H1................................................................................. 250
9.3 Registers Controlling 8-Bit Timers H0 and H1 ........................................................................ 254
9.4 Operation of 8-Bit Timers H0 and H1........................................................................................ 259
9.4.1 Operation as interval timer/square-wave output.............................................................................259
9.4.2 Operation as PWM output..............................................................................................................262
9.4.3 Carrier generator operation (8-bit timer H1 only)............................................................................268
CHAPTER 10 WATCH TIMER .................................................................................................................................................... 275
10.1 Functions of Watch Timer ....................................................................................................... 275
10.2 Configuration of Watch Timer................................................................................................. 276
10.3 Register Controlling Watch Timer .......................................................................................... 277
10.4 Watch Timer Operations.......................................................................................................... 279
10.4.1 Watch timer operation ..................................................................................................................279
10.4.2 Interval timer operation ................................................................................................................279
10.5 Cautions for Watch Timer........................................................................................................ 280
CHAPTER 11 WATCHDOG TIMER........................................................................................................................................... 281
11.1 Functions of Watchdog Timer................................................................................................. 281
11.2 Configuration of Watchdog Timer .......................................................................................... 282
11.3 Register Controlling Watchdog Timer.................................................................................... 283
11.4 Operation of Watchdog Timer................................................................................................. 284
11.4.1 Controlling operation of watchdog timer.......................................................................................284
11.4.2 Setting overflow time of watchdog timer.......................................................................................285
11.4.3 Setting window open period of watchdog timer............................................................................286
CHAPTER 12 CLOCK OUTPUT CONTROLLER ................................................................................................................. 288
12.1 Functions of Clock Output Controller.................................................................................... 288
12.2 Configuration of Clock Output Controller ............................................................................. 289
12.3 Registers Controlling Clock Output Controller..................................................................... 289
12.4 Operations of Clock Output Controller .................................................................................. 291
CHAPTER 13 A/D CONVERTER ............................................................................................................................................... 292
13.1 Function of A/D Converter....................................................................................................... 292
13.2 Configuration of A/D Converter .............................................................................................. 293
13.3 Registers Used in A/D Converter............................................................................................ 295
13.4 A/D Converter Operations ....................................................................................................... 303
13.4.1 Basic operations of A/D converter................................................................................................303
13.4.2 Input voltage and conversion results............................................................................................305
13.4.3 A/D converter operation mode .....................................................................................................306
13.5 How to Read A/D Converter Characteristics Table............................................................... 308
13.6 Cautions for A/D Converter ..................................................................................................... 310
User’s Manual U17473EJ2V0UD 13
CHAPTER 14 SERIAL INTERFACE UART0.......................................................................................................................... 314
14.1 Functions of Serial Interface UART0...................................................................................... 314
14.2 Configuration of Serial Interface UART0 ............................................................................... 315
14.3 Registers Controlling Serial Interface UART0....................................................................... 318
14.4 Operation of Serial Interface UART0...................................................................................... 323
14.4.1 Operation stop mode ...................................................................................................................323
14.4.2 Asynchronous serial interface (UART) mode...............................................................................324
14.4.3 Dedicated baud rate generator ....................................................................................................330
14.4.4 Calculation of baud rate ...............................................................................................................331
CHAPTER 15 SERIAL INTERFACE UART6.......................................................................................................................... 335
15.1 Functions of Serial Interface UART6...................................................................................... 335
15.2 Configuration of Serial Interface UART6 ............................................................................... 339
15.3 Registers Controlling Serial Interface UART6....................................................................... 342
15.4 Operation of Serial Interface UART6...................................................................................... 351
15.4.1 Operation stop mode ...................................................................................................................351
15.4.2 Asynchronous serial interface (UART) mode...............................................................................352
15.4.3 Dedicated baud rate generator ....................................................................................................365
15.4.4 Calculation of baud rate ...............................................................................................................367
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11................................................................................................. 372
16.1 Functions of Serial Interfaces CSI10 and CSI11 ................................................................... 372
16.2 Configuration of Serial Interfaces CSI10 and CSI11............................................................. 373
16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 .................................................... 376
16.4 Operation of Serial Interfaces CSI10 and CSI11 ................................................................... 381
16.4.1 Operation stop mode ...................................................................................................................381
16.4.2 3-wire serial I/O mode..................................................................................................................382
CHAPTER 17 SERIAL INTERFACE IIC0 ................................................................................................................................ 394
17.1 Functions of Serial Interface IIC0 ........................................................................................... 394
17.2 Configuration of Serial Interface IIC0..................................................................................... 397
17.3 Registers to Control Serial Interface IIC0 .............................................................................. 400
17.4 I2C Bus Mode Functions .......................................................................................................... 414
17.4.1 Pin configuration ..........................................................................................................................414
17.5 I2C Bus Definitions and Control Methods .............................................................................. 415
17.5.1 Start conditions ............................................................................................................................415
17.5.2 Addresses....................................................................................................................................416
17.5.3 Transfer direction specification ....................................................................................................416
17.5.4 Acknowledge (ACK).....................................................................................................................417
17.5.5 Stop condition ..............................................................................................................................418
17.5.6 Wait..............................................................................................................................................419
17.5.7 Canceling wait..............................................................................................................................421
17.5.8 Interrupt request (INTIIC0) generation timing and wait control ....................................................421
17.5.9 Address match detection method ................................................................................................422
17.5.10 Error detection ...........................................................................................................................422
17.5.11 Extension code ..........................................................................................................................423
17.5.12 Arbitration ..................................................................................................................................424
User’s Manual U17473EJ2V0UD
14
17.5.13 Wakeup function ........................................................................................................................425
17.5.14 Communication reservation........................................................................................................426
17.5.15 Other cautions............................................................................................................................429
17.5.16 Communication operations.........................................................................................................430
17.5.17 Timing of I2C interrupt request (INTIIC0) occurrence .................................................................438
17.6 Timing Charts ........................................................................................................................... 459
17.7 Communication with LCD Controller/Driver.......................................................................... 466
17.7.1 System configuration....................................................................................................................466
17.7.2 Write operation.............................................................................................................................467
17.7.3 Read operation.............................................................................................................................470
17.7.3 Read operation.............................................................................................................................470
CHAPTER 18 LCD CONTROLLER/DRIVER .......................................................................................................................... 474
18.1 Functions of LCD Controller/Driver........................................................................................ 474
18.2 Configuration of LCD Controller/Driver ................................................................................. 475
18.3 Controlling LCD Controller/Driver .......................................................................................... 477
18.4 Registers Controlling LCD Controller/Driver......................................................................... 479
18.5 Setting LCD Controller/Driver ................................................................................................. 485
18.6 LCD Display Data Memory....................................................................................................... 487
18.7 Common and Segment Signals .............................................................................................. 488
18.8 Display Modes .......................................................................................................................... 492
18.8.1 Static display example .................................................................................................................492
18.8.2 Two-time-slice display example ...................................................................................................495
18.8.3 Three-time-slice display example.................................................................................................498
18.8.4 Four-time-slice display example...................................................................................................502
18.9 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2 ............................................................. 505
18.9.1 Internal resistance division method ..............................................................................................505
18.9.2 External resistance division method.............................................................................................507
18.9.3 Internal voltage boosting method .................................................................................................508
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY).. 509
19.1 Functions of Multiplier/Divider................................................................................................ 509
19.2 Configuration of Multiplier/Divider ......................................................................................... 509
19.3 Register Controlling Multiplier/Divider................................................................................... 513
19.4 Operations of Multiplier/Divider.............................................................................................. 514
19.4.1 Multiplication operation ................................................................................................................514
19.4.2 Division operation.........................................................................................................................516
CHAPTER 20 INTERRUPT FUNCTIONS................................................................................................................................. 518
20.1 Interrupt Function Types ......................................................................................................... 518
20.2 Interrupt Sources and Configuration ..................................................................................... 518
20.3 Registers Controlling Interrupt Functions............................................................................. 522
20.4 Interrupt Servicing Operations ............................................................................................... 530
20.4.1 Maskable interrupt acknowledgement..........................................................................................530
20.4.2 Software interrupt request acknowledgement ..............................................................................532
20.4.3 Multiple interrupt servicing ...........................................................................................................533
20.4.4 Interrupt request hold ...................................................................................................................536
User’s Manual U17473EJ2V0UD 15
CHAPTER 21 KEY INTERRUPT FUNCTION......................................................................................................................... 537
21.1 Functions of Key Interrupt ...................................................................................................... 537
21.2 Configuration of Key Interrupt................................................................................................ 537
21.3 Register Controlling Key Interrupt ......................................................................................... 538
CHAPTER 22 STANDBY FUNCTION....................................................................................................................................... 539
22.1 Standby Function and Configuration..................................................................................... 539
22.1.1 Standby function ..........................................................................................................................539
22.1.2 Registers controlling standby function .........................................................................................539
22.2 Standby Function Operation................................................................................................... 542
22.2.1 HALT mode..................................................................................................................................542
22.2.2 STOP mode .................................................................................................................................547
CHAPTER 23 RESET FUNCTION ............................................................................................................................................. 552
23.1 Register for Confirming Reset Source................................................................................... 560
CHAPTER 24 POWER-ON-CLEAR CIRCUIT......................................................................................................................... 561
24.1 Functions of Power-on-Clear Circuit ..................................................................................... 561
24.2 Configuration of Power-on-Clear Circuit ............................................................................... 562
24.3 Operation of Power-on-Clear Circuit...................................................................................... 562
24.4 Cautions for Power-on-Clear Circuit ...................................................................................... 565
CHAPTER 25 LOW-VOLTAGE DETECTOR .......................................................................................................................... 567
25.1 Functions of Low-Voltage Detector ....................................................................................... 567
25.2 Configuration of Low-Voltage Detector ................................................................................. 568
25.3 Registers Controlling Low-Voltage Detector ........................................................................ 568
25.4 Operation of Low-Voltage Detector........................................................................................ 571
25.4.1 When used as reset .....................................................................................................................572
25.4.2 When used as interrupt................................................................................................................577
25.5 Cautions for Low-Voltage Detector........................................................................................ 582
CHAPTER 26 OPTION BYTE...................................................................................................................................................... 585
26.1 Functions of Option Bytes.................................................................................................... 585
26.2 Format of Option Byte ........................................................................................................... 587
CHAPTER 27 FLASH MEMORY................................................................................................................................................ 590
27.1 Internal Memory Size Switching Register.............................................................................. 590
27.2 Internal Expansion RAM Size Switching Register................................................................ 591
27.3 Writing with Flash Programmer.............................................................................................. 592
27.4 Programming Environment..................................................................................................... 598
27.5 Communication Mode.............................................................................................................. 598
27.6 Handling of Pins on Board ...................................................................................................... 600
27.6.1 FLMD0 pin ...................................................................................................................................600
27.6.2 Serial interface pins .....................................................................................................................600
27.6.3 RESET pin ...................................................................................................................................602
27.6.4 Port pins.......................................................................................................................................602
27.6.5 REGC pin.....................................................................................................................................602
27.6.6 Other signal pins..........................................................................................................................602
27.6.7 Power supply ...............................................................................................................................603
User’s Manual U17473EJ2V0UD
16
27.7 Programming Method .............................................................................................................. 603
27.7.1 Controlling flash memory .............................................................................................................603
27.7.2 Flash memory programming mode ..............................................................................................603
27.7.3 Selecting communication mode ...................................................................................................604
27.7.4 Communication commands..........................................................................................................605
27.8 Security Settings ...................................................................................................................... 606
27.9 Processing Time for Each Command When PG-FP4 Is Used (Reference)......................... 608
27.10 Flash Memory Programming by Self-Writing ...................................................................... 609
27.10.1 Boot swap function.....................................................................................................................616
CHAPTER 28 ON-CHIP DEBUG FUNCTION (
μ
PD78F0397D ONLY)............................................................................ 618
28.1 Connecting QB-78K0MINI to
μ
PD78F0397D .......................................................................... 618
28.2 On-Chip Debug Security ID ..................................................................................................... 620
CHAPTER 29 INSTRUCTION SET ............................................................................................................................................ 621
29.1 Conventions Used in Operation List ...................................................................................... 621
29.1.1 Operand identifiers and specification methods.............................................................................621
29.1.2 Description of operation column...................................................................................................622
29.1.3 Description of flag operation column ............................................................................................622
29.2 Operation List ........................................................................................................................... 623
29.3 Instructions Listed by Addressing Type................................................................................ 631
CHAPTER 30 ELECTRICAL SPECIFICATIONS.................................................................................................................... 634
CHAPTER 31 PACKAGE DRAWINGS .................................................................................................................................... 655
CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS.......................................................................................... 657
CHAPTER 33 CAUTIONS FOR WAIT...................................................................................................................................... 658
33.1 Cautions for Wait...................................................................................................................... 658
33.2 Peripheral Hardware That Generates Wait ............................................................................ 659
APPENDIX A DEVELOPMENT TOOLS................................................................................................................................... 660
A.1 Software Package ...................................................................................................................... 663
A.2 Language Processing Software ............................................................................................... 663
A.3 Control Software ........................................................................................................................ 664
A.4 Flash Memory Writing Tools..................................................................................................... 664
A.5 Debugging Tools (Hardware).................................................................................................... 665
A.5.1 When using in-circuit emulator QB-78K0LX2.................................................................................665
A.5.2 When using on-chip debug emulator QB-78K0MINI ......................................................................666
A.6 Debugging Tools (Software)..................................................................................................... 666
APPENDIX B REGISTER INDEX ............................................................................................................................................... 667
B.1 Register Index (In Alphabetical Order with Respect to Register Names)............................ 667
B.2 Register Index (In Alphabetical Order with Respect to Register Symbol)........................... 671
APPENDIX C REVISION HISTORY ........................................................................................................................................... 675
C.1 Major Revisions in This Edition ............................................................................................... 675
User’s Manual U17473EJ2V0UD 17
CHAPTER 1 OUTLINE
1.1 Features
{ Minimum instruction execution time can be changed from high speed (0.1
μ
s: @ 20 MHz operation with high-
speed system clock) to ultra low-speed (122
μ
s: @ 32.768 kHz operation with subsystem clock)
{ General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
{ ROM, RAM capacities
Data Memory Item
Part Number
Program Memory
(ROM) Internal High-
Speed RAMNote
Internal Expansion
RAMNote
LCD Display
RAM
μ
PD78F0393 32 KB −
μ
PD78F0394 48 KB 1 KB
μ
PD78F0395 60 KB 2 KB
μ
PD78F0396 96 KB 4 KB
μ
PD78F0397, 78F0397D
Flash memoryNote
128 KB
1 KB
6 KB
40 × 4 bits
Note The internal flash memory, internal high-speed RAM capacities, and internal expansion RAM capacities
can be changed using the internal memory size switching register (IMS) and the internal expansion RAM
size switching register (IXS).
{ On-chip single-power-supply flash memory
{ Self-programming (with boot swap function)
{ On-chip debug function (
μ
PD78F0397D only)
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ On-chip watchdog timer (operable with internal low-speed oscillation clock)
{ LCD controller/driver (internal voltage boosting, external resistance division, and internal resistance division are
switchable)
Segment signals: 40, Common signals: 4
{ On-chip multiplier/divider (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D only)
{ On-chip key interrupt function: 8 channels
{ On-chip clock output controller
{ I/O ports: 40
{ Timer
μ
PD78F0393: 7 channels
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D: 8 channels
{ Serial interface
μ
PD78F0393: 3 channels
(UART (LIN (Local Interconnect Network)-bus supported): 1 channel, CSI/UARTNote: 1 channel, I2C: 1 channel)
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D: 4 channels
(UART (LIN (Local Interconnect Network)-bus supported: 1 channel, CSI/UARTNote: 1 channel, CSI: 1 channel,
I2C: 1 channel)
Note Select either of the functions of these alternate-function pins.
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD
18
{ 10-bit resolution A/D converter: 8 channels
{ Power supply voltage: VDD = 1.8 to 5.5 V
{ Operating ambient temperature: TA = −40 to +85°C
1.2 Applications
APS cameras, digital cameras, AV equipments, and household electrical appliances, etc.
1.3 Ordering Information
• Flash memory version (Lead-free products)
Part Number Package
μ
PD78F0393GC-8EA-A 100-pin plastic LQFP (14 × 14)
μ
PD78F0394GC-8EA-A 100-pin plastic LQFP (14 × 14)
μ
PD78F0395GC-8EA-A 100-pin plastic LQFP (14 × 14)
μ
PD78F0396GC-8EA-A 100-pin plastic LQFP (14 × 14)
μ
PD78F0397GC-8EA-A 100-pin plastic LQFP (14 × 14)
μ
PD78F0397DGC-8EA-ANote1 100-pin plastic LQFP (14 × 14)
μ
PD78F0393GF-GAS-ANote2 100-pin plastic LQFP (14 × 20)
μ
PD78F0394GF-GAS-ANote2 100-pin plastic LQFP (14 × 20)
μ
PD78F0395GF-GAS-ANote2 100-pin plastic LQFP (14 × 20)
μ
PD78F0396GF-GAS-ANote2 100-pin plastic LQFP (14 × 20)
μ
PD78F0397GF-GAS-ANote2 100-pin plastic LQFP (14 × 20)
μ
PD78F0397DGF-GAS-ANotes1, 2 100-pin plastic LQFP (14 × 20)
Notes1. The
μ
PD78F0397D has an on-chip debug function. Do not use this product for mass production, because its
reliability cannot be guaranteed after the on-chip debug function has been used, with respect to the number
of times the flash memory can be rewritten. NEC Electronics does not accept complaints about this product.
2. Under development
<R>
<R>
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD 19
1.4 Pin Configuration (Top View)
• 100-pin plastic LQFP (14 × 14)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P30/INTP1
P31/INTP2/OCD1A
Note1
P32/INTP3/OCD1B
Note1
LV
DD
LV
SS
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
P76/KR6
P75/KR5
P74/KR4
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P06/TI011 /TO01
P05/TI001 /SSI11
P00/TI000
P01/TI010/TO00
P02/SO11
P03/SI11
P04/SCK11
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
AV
SS
AV
REF
P10/SCK10/TxD0
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
P77/KR7
P120/INTP0/EXLVI
P33/INTP4/TI51/TO51
P61/SDA0
P60/SCL0
RESET
P124/XT2/EXCLKS
P123/XT1
FLMD0
P122/X2/EXCLK/OCD0B
Note1
P121/X1/OCD0A
Note1
REGC
V
SS
V
DD
CAPH
CAPL
V
LC0
V
LC1
V
LC2
COM0
COM1
COM2
COM3
S0
S1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Note2 Note2
Note2
Note2
Note2
Note2
Note2
Notes 1.
μ
PD78F0397D (product with on-chip debug function) only.
2.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Cautions 1. Connect the AVSS pin to VSS.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F: recommended).
3. P20/ANI0 to P27/ANI7 are set in the analog input mode after release of reset.
<R>
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD
20
• 100-pin plastic LQFP (14 × 20)
AVREF
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P30/INTP1
P31/INTP2/OCD1ANote1
P32/INTP3/OCD1BNote1
LVDD
LVSS
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
P73/KR3
P72/KR2
P71/KR1
P70/KR0
P06/TI011 /TO01
P05/TI001 /SSI11
P00/TI000
P01/TI010/TO00
P02/SO11
P03/SI11
P04/SCK11
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
AVSS
P74/KR4
P75/KR5
P76/KR6
P77/KR7
P120/INTP0/EXLVI
P33/INTP4/TI51/TO51
P61/SDA0
P60/SCL0
RESET
P124/XT2/EXCLKS
P123/XT1
FLMD0
P122/X2/EXCLK/OCD0BNote1
P121/X1/OCD0ANote1
REGC
VSS
VDD
CAPH
CAPL
VLC0
VLC1
VLC2
COM0
COM1
COM2
COM3
S0
S1
S2
S3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Note2 Note2
Note2 Note2
Note2
Note2
Note2
Notes 1.
μ
PD78F0397D (product with on-chip debug function) only.
2.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Cautions 1. Connect the AVSS pin to VSS.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F: recommended).
3. P20/ANI0 to P27/ANI7 are set in the analog input mode after release of reset.
<R>
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD 21
Pin Identification
ANI0 to ANI7: Analog input
AVREF: Analog reference voltage
AVSS: Analog ground
CAPH, CAPL: LCD power supply
capacitance control
COM0 to COM3: Common output
EXCLK: External clock input
(main system clock)
EXCLKS: External clock input
(subsystem clock)
EXLVI: External potential input
for low-voltage detector
FLMD0: Flash programming mode
INTP0 to INTP5: External interrupt input
KR0 to KR7: Key return
LVDD: Power supply for
LCD controller/driver
LVSS: Ground for LCD controller/driver
OCD0ANote1, OCD0BNote1: On Chip Debug Input/Output
OCD1ANote1, OCD1BNote1: On Chip Debug Input/Output
P00 to P06: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30 to P33: Port 3
P60, P61: Port 6
P70 to P77: Port 7
P120 to P124: Port 12
REGC Regulator capacitance
RESET: Reset
RxD0, RxD6: Receive data
S0 to S39: Segment output
SCK10, SCK11Note2: Serial clock input/output
SCL0: Serial clock input/output
SDA0: Serial data input/output
SI10, SI11Note2: Serial data input
SO10, SO11Note2: Serial data output
SSI11Note2: Serial interface chip select input
TI000, TI010: Timer input
TI001Note2, TI011Note2: Timer input
TI50, TI51: Timer input
TO00, TO01Note2: Timer output
TO50, TO51: Timer output
TOH0, TOH1: Timer output
TxD0, TxD6: Transmit data
VDD: Power supply
VSS: Ground
VLC0 to VLC2: LCD power supply
X1, X2: Crystal oscillator
(main system clock)
XT1, XT2: Crystal oscillator
(subsystem clock)
Notes 1.
μ
PD78F0397D (product with on-chip debug function) only.
2.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD
22
1.5 Configuration
78K0/LG2 is the SiP (System in a Package) product configured by the CPU part and LCD part.
LCD part CPU part
VLC0
VLC1
VLC2
CAPH
CAPL
COM0
COM1
COM2
COM3
S0
S1
:
:
S39
P60/SCL0
P61/SDA0
P121/X1/OCD0A
P122/X2/EXCLK/OCD0B
P123/XT1
P124/XT2/EXCLKS
P120/INTP0/EXLVI
VSS AVREF AVSS
LVDD LV SS RESET REGC VDD
P00/TI000
P01/TI010/TO00
P02/SO11
P03/SI11
P04/SCK11
P05/TI001/SSI11
P06/TI011/TO01
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
P13/TxD6
P14/RxD6
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P30/INTP1
P31/INTP2/OCD1A
P32/INTP3/OCD1B
P33/INTP4/TI51/TO51
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P74/KR4
P75/KR5
P76/KR6
P77/KR7
P130Note
P140/PCLNote
LRESETBNote
LCLKNote
LSCLNote LSDANote
Note It is an internal pin.
<R>
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD 23
1.6 78K0/Lx2 Series Lineup
78K0/LE2 78K0/LF2 78K0/LG2 ROM RAM
64 Pins 80 Pins 100 Pins
128 KB 7 KB − −
μ
PD78F0397DNote
μ
PD78F0397
96 KB 5 KB −
μ
PD78F0386DNote
μ
PD78F0376DNote
μ
PD78F0386
μ
PD78F0376
μ
PD78F0396
60 KB 3 KB −
μ
PD78F0385
μ
PD78F0375
μ
PD78F0395
48 KB 2 KB −
μ
PD78F0384
μ
PD78F0374
μ
PD78F0394
32 KB 1 KB
μ
PD78F0363DNote
μ
PD78F0363
μ
PD78F0383
μ
PD78F0373
μ
PD78F0393
24 KB 1 KB
μ
PD78F0362
μ
PD78F0382
μ
PD78F0372
−
16 KB 768 B
μ
PD78F0361 − −
Note Product with on-chip debug function
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD
24
The list of functions in the 78K0/Lx2 Series is shown below.
78K0/LE2 78K0/LF2 78K0/LG2
μ
PD78F036x
μ
PD78F037x
μ
PD78F038x
μ
PD78F039x
Part Number
Item 64 Pins 80 Pins 100 Pins
Flash memory (KB) 16 24 32 24 32 48 60 96 24 32 48 60 96 32 48 60 96 128
RAM (KB) 0.75 1 1 1 1 2 3 5 1 1 2 3 5 1 2 3 5 7
Bank (flash memory) − 4 − 4 − 4 6
Power supply voltage VDD = 1.8 to 5.5 V
Regulator Provided
Minimum instruction
execution time
0.1
μ
s (20 MHz: VDD = 4.0 to 5.5 V)/0.2
μ
s (10 MHz: VDD = 2.7 to 5.5 V)/
0.4
μ
s (5 MHz: VDD = 1.8 to 5.5 V)
High-speed system
clock
20 MHz: VDD = 4.0 to 5.5 V/10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.5 V
Main
Internal high-speed
oscillation clock
8 MHz (TYP.): VDD = 1.8 to 5.5 V
Subclock 32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Clock
Internal low-speed
oscillation clock
240 kHz (TYP.): VDD = 1.8 to 5.5 V
Port
Total 24 34 26 40
16 bits (TM0) 1 ch 2 ch 1 ch 2 ch 1 ch 2 ch
8 bits (TM5) 2 ch
8 bits (TMH) 2 ch
Watch 1 ch
Timer
WDT 1 ch
3-wire CSI − 1 ch
3-wire CSI/UARTNote 1 ch
UART supporting LIN-
bus
1 ch
Serial interface
I2C bus 1 ch
Type Internal voltage boosting, external resistance division, and internal resistance division are switchable.
Segment signal 20 26 36 40
LCD
Common signal 4
10-bit A/D 5 ch 8 ch − 8 ch
External 6 7
Interrupt
Internal 16 18 15 17 16 19
Key interrupt − 7 ch 8 ch
RESET pin Provided
POC 1.59 V ±0.15 V (Time for rising up to 1.8 V : 3.6 ms (MAX.))
LVI The detection level of the supply voltage is selectable in 16 steps.
Reset
WDT Provided
Clock output Provided
Multiplier/divider −
Provided
−
Provided
−
Provided
On-chip debug function
μ
PD78F0363D only
μ
PD78F0376D only
μ
PD78F0386D only
μ
PD78F0397D only
Operating ambient
temperature
TA = −40 to +85°C
Note Select either of the functions of these alternate-function pins.
<R>
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD 25
1.7 Block Diagram
PORT 0 P00 to P06
7
PORT 1 P10 to P17
PORT 2 P20 to P27
8
PORT 3 P30 to P33
4
VSS FLMD0 VDD
8
PORT 7 P70 to P77
PORT 12 P120 to P124
8
ANI0/P20 to
ANI7/P27
INTERRUPT
CONTROL
A/D CONVERTER AVREF
AVSS
INTP1/P30 to
INTP4/P33
INTP0/P120(LINSEL)
INTP5/P16
INTERNAL
HIGH-SPEED
RAM
INTERNAL
EXPANSION
RAM
Note2
78K/0
CPU
CORE
FLASH
MEMORY
BANK
Note
1
16-bit TIMER/
EVENT
COUNTER 01
Note
2
TO01
Note2
/TI011
Note2
/P06
TI001
Note2
/P05
8-bit TIMER
H0
TOH0/P15
8-bit TIMER
H1
TOH1/P16
TI50/TO50/P17 8-bit TIMER/
EVENT COUNTER 50
RxD0/P11
TxD0/P10
SERIAL
INTERFACE UART0
WATCHDOG TIMER
RxD6/P14
TxD6/P13
SERIAL
INTERFACE UART6
TI51/TO51/P33 8-bit TIMER/
EVENT COUNTER 51
WATCH TIMER
SERIAL
INTERFACE CSI10
SI10/P11
SO10/P12
SCK10/P10
16-bit TIMER/
EVENT COUNTER 00
TO00/TI010/P01
TI000/P00 (LINSEL)
SERIAL INTERFACE
CSI11
Note
2
SI11
Note2
/P03
SO11
Note2
/P02
SCK11
Note2
/P04
SSI11
Note2
/P05
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
KEY RETURN
8KR0/P70 to
KR7/P77
EXLVI/P120
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
MULTIPLIER&
DIVIDER
Note2
ON-CHIP
DEBUG
Note3
RxD6/P14 (LINSEL)
RxD6/P14 (LINSEL)
LINSEL
5
4
8
VOLTAGE
REGULATOR REGC
INTERNAL
HIGH-SPEED
OSCILLATOR
INTERNAL
LOW-SPEED
OSCILLATOR
OCD0A
Note3
/X1, OCD1A
Note3
/P31
OCD0B
Note3
/X2, OCD1B
Note3
/P32
SERIAL
INTERFACE IIC0
P61/SDA0
P60/SCL0
RESET CONTROL
LCD
CONTROLLER
DRIVER
S0 to S39
COM0 to COM3
VLC0 to VLC2
CAPH
CAPL
40
4
LVDD
LVSS
RAM SPACE
FOR
LCD DATA
CLOCK OUTPUT
CONTROL
LCD part
CPU part
PORT 6 P60, P61
2
Notes 1.
μ
PD78F0396, 78F0397 and 78F0397D only.
2.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
3.
μ
PD78F0397D only.
<R>
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD
26
1.8 Outline of Functions
(1/2)
Item
μ
PD78F0393
μ
PD78F0394
μ
PD78F0395
μ
PD78F0396
μ
PD78F0397
μ
PD78F0397D
Flash memory
(self-programming
supported)Note 1
32 K 48 K 60 K 96 K 128 K
BankNote 2 − − − 4 6
High-speed RAMNote 1 1 K
Expansion RAMNote 1 − 1 K 2 K 4 K 6 K
Internal
memory
(bytes)
LCD display RAM 40 × 4 bits
Memory space 64 KB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 4.0 to 5.5 V, 1 to 10 MHz: VDD = 2.7 to 5.5 V,
1 to 5 MHz: VDD = 1.8 to 5.5 V
Main system
clock
(oscillation
frequency) Internal high-speed
oscillation clock
Internal oscillation
8 MHz (TYP.): VDD = 1.8 to 5.5 V
Subsystem clock
(oscillation frequency)
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Internal low-speed oscillation clock
(for TMH1, WDT)
Internal oscillation
240 kHz (TYP.): VDD = 1.8 to 5.5 V
General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
0.1
μ
s (high-speed system clock: @ fXH = 20 MHz operation)
0.25
μ
s (internal high-speed oscillation clock: @ fRH = 8 MHz (TYP.) operation)
Minimum instruction execution time
122
μ
s (subsystem clock: @ fSUB = 32.768 kHz operation)
Instruction set • 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O ports CMOS I/O: 40
• 16-bit
timer/event
counter:
1 channel
• 16-bit timer/event counter: 2 channels
Timers
• 8-bit timer/event counter: 2 channels
• 8-bit timer: 2 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel
Timer outputs 5 (PWM
output: 4)
6 (PWM output: 4)
Clock output • 156.25 kHz, 312.5 kHz (peripheral hardware clock: @ fPRS = 20 MHz operation)
• 32.768 kHz (subsystem clock: @ fSUB = 32.768 kHz operation)
Notes 1. The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM
capacity can be changed using the internal memory size switching register (IMS) and the internal
expansion RAM size switching register (IXS).
2. Banks to be used can be changed using the bank select register (BANK).
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD 27
(2/2)
Item
μ
PD78F0393
μ
PD78F0394
μ
PD78F0395
μ
PD78F0396
μ
PD78F0397
μ
PD78F0397D
A/D converter 10-bit resolution × 8 channels (AVREF = 2.3 to 5.5 V)
Serial interface • UART
supporting
LIN-bus
: 1 channel
• 3-wire serial
I/O/UARTNote
: 1 channel
• I2C bus
: 1 channel
• UART supporting LIN-bus: 1 channel
• 3-wire serial I/O/UARTNote: 1 channel
• 3-wire serial I/O mode: 1 channel
• I2C bus: 1 channel
LCD controller/driver • Internal voltage boosting, external resistance division, and internal resistance division are
switchable.
• Segment signal outputs: 40
• Common signal outputs: 4
Multiplier/divider − • 16 bits × 16 bits = 32 bits (multiplication)
• 32 bits ÷ 16 bits = 32 bits remainder of 16 bits (division)
Internal 16 19 Vectored
interrupt sources External 7
Key interrupt Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR7).
Reset • Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
On-chip debug function − Provided
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = −40 to +85°C
Package • 100-pin plastic LQFP (14 × 14)
• 100-pin plastic LQFP (14 × 20)
Note Select either of the functions of these alternate-function pins.
<R>
CHAPTER 1 OUTLINE
User’s Manual U17473EJ2V0UD
28
An outline of the timer is shown below.
16-Bit Timer/
Event Counters
00 and 01Note 1
8-Bit Timer/
Event Counters
50 and 51
8-Bit Timers H0 and
H1
TM00 TM01Note 1 TM50 TM51 TMH0 TMH1
Watch
Timer
Watchdog
Timer
Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channelNote 2 −
External event
counter
1 channel 1 channel 1 channel 1 channel − − − −
PPG output 1 output 1 output − − − − − −
PWM output − − 1 output 1 output 1 output 1 output − −
Pulse width
measurement
2 inputs 2 inputs − − − − − −
Square-wave
output
1 output 1 output 1 output 1 output 1 output 1 output − −
Carrier generator − − − − − 1 output
Note 3
− −
Watch timer − − − − − − 1 channel
Note 2
−
Function
Watchdog timer − − − − − − − 1 channel
Interrupt source 2 2 1 1 1 1 1 −
Notes 1.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
2. In the watch timer, the watch timer function and interval timer function can be used simultaneously.
3. TM51 and TMH1 can be used in combination as a carrier generator mode.
User’s Manual U17473EJ2V0UD 29
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
There are three types of pin I/O buffer power supplies: AVREF, LVDD, and VDD. The relationship between these
power supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P20 to P27
LVDD CAPH, CAPL, COM0 to COM3, S0 to S39, VLC0 to VLC2
VDD Pins other than above
(1) Port pins (1/2)
Function Name I/O Function After Reset Alternate Function
P00 TI000
P01 TI010/TO00
P02 SO11Note1
P03 SI11Note1
P04 SCK11Note1
P05 SSI11Note1/TI001Note1
P06
I/O Port 0.
7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI011Note1/TO01Note1
P10 SCK10/TxD0
P11 SI10/RxD0
P12 SO10
P13 TxD6
P14 RxD6
P15 TOH0
P16 TOH1/INTP5
P17
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI50/TO50
P20 to P27 I/O Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Analog input ANI0 to ANI7
P30 INTP1 to INTP3
P31 INTP2/OCD1ANote2
P32 INTP3/OCD1BNote2
P33
I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP4/TI51/TO51
Notes 1.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
2.
μ
PD78F0397D only.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD
30
(1) Port pins (2/2)
Function Name I/O Function After Reset Alternate Function
P60 SCL0
P61
I/O Port 6.
2-bit I/O port.
N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.
Input port
SDA0
P70 to P77 I/O Port 7.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port KR0 to KR7
P120 INTP0/EXLVI
P121 X1/OCD0ANote
P122 X2/EXCLK/OCD0BNote
P123 XT1
P124
I/O Port 12.
5-bit I/O port.
Input/output can be specified in 1-bit units.
Only for P120, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
XT2/EXCLKS
Note
μ
PD78F0397D only.
<R>
<R>
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD 31
(2) Non-port pins (1/2)
Function Name I/O Function After Reset Alternate Function
INTP0 P120/EXLVI
INTP1 P30
INTP2 P31/OCD1ANote1
INTP3 P32/OCD1BNote1
INTP4 P33/TI51/TO51
INTP5
Input External interrupt request input for which the valid edge (rising
edge, falling edge, or both rising and falling edges) can be
specified
Input port
P16/TOH1
SI10 P11/RxD0
SI11Note2
Input Serial data input to serial interface Input port
P03
SO10 P12
SO11Note2
Output Serial data output from serial interface Input port
P02
SDA0 I/O Serial data I/O for serial interface Input port P61
SCK10 P10/TxD0
SCK11Note2
I/O Clock input/output for serial interface Input port
P04
SCL0 I/O Clock input/output for serial interface Input port P60
SSI11Note2 Input Chip select input for serial interface Input port P05/TI001
RxD0 P11/SI10
RxD6
Input Serial data input to asynchronous serial interface Input port
P14
TxD0 P10/SCK10
TxD6
Output Serial data output from asynchronous serial interface Input port
P13
TI000 External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
P00
TI001Note2 External count clock input to 16-bit timer/event counter 01
Capture trigger input to capture registers (CR001, CR011) of
16-bit timer/event counter 01
P05/SSI11Note2
TI010 Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
P01/TO00
TI011Note2
Input
Capture trigger input to capture register (CR001) of 16-bit
timer/event counter 01
Input port
P06/TO01Note2
TO00 16-bit timer/event counter 00 output P01/TI010
TO01Note2
Output
16-bit timer/event counter 01 output
Input port
P06/TI011Note2
TI50 External count clock input to 8-bit timer/event counter 50 P17/TO50
TI51
Input
External count clock input to 8-bit timer/event counter 51
Input port
P33/TO51/INTP4
TO50 8-bit timer/event counter 50 output P17/TI50
TO51 8-bit timer/event counter 51 output P33/TI51/INTP4
TOH0 8-bit timer H0 output P15
TOH1
Output
8-bit timer H1 output
Input port
P16/INTP5
Notes 1.
μ
PD78F0397D only.
2.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD
32
(2) Non-port pins (2/2)
Function Name I/O Function After Reset Alternate Function
ANI0 to ANI7 Input A/D converter analog input Analog input P20 to P27
AVREF Input
A/D converter reference voltage input and positive power
supply for port 2
− −
AVSS − A/D converter ground potential. Make the same potential
as VSS.
− −
S0 to S39 Output LCD controller/driver segment signal outputs − −
COM0 to COM3 Output LCD controller/driver common signal outputs − −
LVDD − Positive power supply for LCD controller/driver − −
LVSS − Ground potential for LCD controller/driver − −
VLC0 to VLC2 − LCD drive voltage − −
CAPH −
CAPL −
LCD drive voltage booster capacitor connection − −
KR0 to KR7 Input Key interrupt input Input port P70 to P77
REGC − Connecting regulator output (2.5 V) stabilization
capacitance for internal operation.
Connect to VSS via a capacitor (0.47 to 1
μ
F:
recommended).
− −
RESET Input System reset input − −
EXLVI Input Potential input for external low-voltage detection Input port P120/INTP0
X1 Input P121/OCD0ANote
X2 −
Connecting resonator for main system clock Input port
P122/EXCLK/OCD0B
Note
EXCLK Input External clock input for main system clock Input port P122/X2/OCD0BNote
XT1 Input P123
XT2 −
Connecting resonator for subsystem clock Input port
P124/EXCLKS
EXCLKS Input External clock input for subsystem clock Input port P124/XT2
VDD − Positive power supply − −
VSS − Ground potential − −
FLMD0 − Flash memory programming mode setting − −
OCD0ANote P121/X1
OCD1ANote
Input
P31/INTP2
OCD0BNote P122/X2/EXCLK
OCD1BNote
−
On-chip debug mode setting connection Input port
P32/INTP3
Note
μ
PD78F0397D only.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD 33
2.2 Description of Pin Functions
2.2.1 P00 to P06 (port 0)
P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O,
and chip select input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 to P06 function as a 7-bit I/O port. P00 to P06 can be set to input or output port in 1-bit units using port
mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0
(PU0).
(2) Control mode
P00 to P06 function as timer I/O, serial interface data I/O, clock I/O, and chip select input.
(a) TI000, TI001Note
These are the pins for inputting an external count clock to 16-bit timer/event counters 00 and 01 and are also
for inputting a capture trigger signal to the capture registers (CR000, CR010 or CR001, CR011) of 16-bit
timer/event counters 00 and 01.
(b) TI010, TI011Note
These are the pins for inputting a capture trigger signal to the capture register (CR000 or CR001) of 16-bit
timer/event counters 00 and 01.
(c) TO00, TO01Note
These are timer output pins.
(d) SI11Note
This is a serial interface serial data input pin.
(e) SO11Note
This is a serial interface serial data output pin.
(f) SCK11Note
This is the serial interface serial clock I/O pin.
(g) SSI11Note
This is the serial interface chip select input pin.
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD
34
2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output port in 1-bit units using port
mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1
(PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
(a) SI10
This is a serial interface serial data input pin.
(b) SO10
This is a serial interface serial data output pin.
(c) SCK10
This is a serial interface serial clock I/O pin.
(d) RxD0, RxD6
These are the serial data input pins of the asynchronous serial interface.
(e) TxD0, TxD6
These are the serial data output pins of the asynchronous serial interface.
(f) TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(g) TO50, TOH0, and TOH1
These are timer output pins.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD 35
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an 8-bit I/O port. P20 to P27 can be set to input or output port in 1-bit units using port
mode register 2 (PM2).
(2) Control mode
P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7). When using these pins as analog input
pins, see (5) ANI0/P20 to ANI7/P27 in 13.6 Cautions for A/D Converter.
Caution P20/ANI0 to P27/ANI7 are set in the analog input mode after release of reset.
2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and
timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output port in 1-bit units using port
mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3
(PU3).
(2) Control mode
P30 to P33 function as external interrupt request input and timer I/O.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin.
Caution In the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D, be sure to pull the P31 pin
down before a reset release, to prevent malfunction.
Remark Only for the
μ
PD78F0397D, P31 and P32 can be used as on-chip debug mode setting pins
(OCD1A, OCD1B) when the on-chip debug function is used. For how to connect an in-circuit
emulator supporting on-chip debugging (QB-78K0MINI), see CHAPTER 28 ON-CHIP DEBUG
FUNCTION (
μ
PD78F0397D ONLY).
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD
36
2.2.5 P60, P61 (port 6)
P60 and P61 function as a 2-bit I/O port. These pins also function as pins for serial interface clock I/O and data I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P60 and P61 function as a 2-bit I/O port. P60 and P61 can be set to input port or output port in 1-bit units using
port mode register 6 (PM6).
Output of P60 and P61 is N-ch open-drain output (6 V tolerance).
(2) Control mode
P60 and P61 function as serial interface clock I/O and data I/O.
(a) SCL0
This is a serial clock I/O pin for serial interface IIC0.
Be sure to pull the SCL0 pin up externally.
(b) SDA0
This is a serial data I/O pin for serial interface IIC0.
Be sure to pull the SDA0 pin up externally.
Caution In the 78K0/LG2, be sure to use the P60/SCL0 and P61/SDA0 as the serial clock I/O pin and serial data
I/O pin, respectively, in accordance with the specifications.
2.2.6 P70 to P77 (port 7)
P70 to P77 function as an 8-bit I/O port. These pins also function as key interrupt input pins.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P77 function as an 8-bit I/O port. P70 to P77 can be set to input or output port in 1-bit units using port
mode register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7
(PU7).
(2) Control mode
P70 to P77 function as key interrupt input pins.
2.2.7 P120 to P124 (port 12)
P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input,
potential input for external low-voltage detection, resonator for main system clock connection, resonator for subsystem
clock connection, and external clock input. The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 to P124 function as a 5-bit I/O port. P120 to P124 can be set to input or output port using port mode
register 12 (PM12). Only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option
register 12 (PU12).
<R>
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD 37
(2) Control mode
P120 to P124 function as an external interrupt request input, potential input for external low-voltage detection,
resonator for main system clock connection, resonator for subsystem clock connection, and external clock input.
(a) INTP0
This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
(b) EXLVI
This is a potential input pin for external low-voltage detection.
(c) X1, X2
These are the pins for connecting a resonator for main system clock.
(d) EXCLK
This is an external clock input pin for main system clock.
(e) XT1, XT2
These are the pins for connecting a resonator for subsystem clock.
(f) EXCLKS
This is an external clock input pin for subsystem clock.
Remark Only for the
μ
PD78F0397D, X1 and X2 can be used as on-chip debug mode setting pins (OCD0A,
OCD0B) when the on-chip debug function is used. For how to connect an in-circuit emulator
supporting on-chip debugging (QB-78K0MINI), see CHAPTER 28 ON-CHIP DEBUG FUNCTION
(
μ
PD78F0397D ONLY).
2.2.8 AVREF
This is the A/D converter reference voltage input pin.
When the A/D converter is not used, connect this pin directly to VDD.
2.2.9 AVSS
This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with
the same potential as the VSS pin.
2.2.10 S0 to S39
These pins are the segment signal output pins for the LCD controller/driver.
2.2.11 COM0 to COM3
These pins are the common signal output pins for the LCD controller/driver.
2.2.12 LVDD
This is the positive power supply pin for the LCD controller/driver.
2.2.13 LVSS
This is the ground potential pin for the LCD controller/driver.
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD
38
2.2.14 VLC0 to VLC2
These pins are the power supply voltage pins for driving the LCD.
2.2.15 CAPH, CAPL
These pins are the capacitor connection pins for driving the LCD.
2.2.16 RESET
This is the active-low system reset input pin.
2.2.17 REGC
This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this
pin to VSS via a capacitor (0.47 to 1
μ
F: recommended).
REGC
VSS
Caution Keep the wiring length as short as possible in the area enclosed by the broken lines in the above figures.
2.2.18 VDD
This is the positive power supply pin.
2.2.19 VSS
This is the ground potential pin.
2.2.20 FLMD0
This is a pin for setting flash memory programming mode.
Connect FLMD0 to VSS in the normal operation mode.
In flash memory programming mode, be sure to connect this pin to the flash programmer.
<R>
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD 39
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
See Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types (1/2)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/TI000
P01/TI010/TO00
5-AH
P02/SO11Note 1 5-AG
P03/SI11Note 1
P04/SCK11Note 1
P05/SSI11Note 1/TI001Note 1
P06/TI011Note 1/TO01Note 1
5-AG (
μ
PD78F0393),
5-AH (
μ
PD78F0394,
78F0395, 78F0396,
78F0397, 78F0397D)
P10/SCK10/TxD0
P11/SI10/RxD0
5-AH
P12/SO10
P13/TxD6
5-AG
P14/RxD6 5-AH
P15/TOH0 5-AG
P16/TOH1/INTP5
P17/TI50/TO50
5-AH
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P20/ANI0 to
P27/ANI7Note 2
11-G <Analog setting>
Connect to AVREF or AVSS.
<Digital setting>
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P30/INTP1
P31/INTP2/OCD1ANotes 3, 4
P32/INTP3/OCD1BNote 4
P33/TI51/TO51/INTP4
5-AH Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P60/SCL0
P61/SDA0
13-AD
I/O
Be sure to pull up externally.
Notes 1.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
2. P20/ANI0 to P27/ANI7 are set in the analog input mode after release of reset.
3. For products without an on-chip debug function and with the flash memory of 48 KB or more
(
μ
PD78F0394, 78F0395, 78F0396, and 78F0397) and having a product rank of “I” or “E”, and for the
product with an on-chip debug function (
μ
PD78F0397D), connect P31/INTP2/OCD1ANote 4 as follows
when writing the flash memory with a flash memory programmer.
• P31/INTP2/OCD1ANote 4: Connect to VSS via a resistor (10 kΩ: recommended).
The above connection is not necessary when writing the flash memory by means of self programming.
4. OCD1A and OCD1B are provided to the
μ
PD78F0397D only.
Remark For the product ranks, consult an NEC Electronics sales representative.
<R>
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD
40
Table 2-2. Pin I/O Circuit Types (2/2)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P70/KR0 to P77/KR7
P120/INTP0/EXLVI
5-AH
P121/X1/OCD0ANotes 1, 2, 5
P122/X2/EXCLK
/OCD0BNotes 1, 5
P123/XT1Note 1
P124/XT2/EXCLKSNote 1
37
I/O Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
S0 to S39 17
COM0 to COM3 18
Output
VLC0 to VLC2
CAPH, CAPL
− −
Leave open.
AVREF Connect directly to VDD. Note 3
AVSS
− −
Connect directly to VSS.
FLMD0 38 Input Connect to VSS. Note 4
RESET 2 Input Connect directly to VDD or via a resistor.
Notes 1. Use recommended connection above in I/O port mode (see Figure 6-2 Format of Clock Operation
Mode Select Register (OSCCTL)) when these pins are not used.
2. For products without an on-chip debug function and with the flash memory of 48 KB or more
(
μ
PD78F0394, 78F0395, 78F0396, and 78F0397) and having a product rank of “I” or “E”, and for the
product with an on-chip debug function (
μ
PD78F0397D), connect P121/X1/OCD0ANote 5 as follows when
writing the flash memory with a flash memory programmer.
• P121/X1/OCD0ANote 5: When using this pin as a port, connect it to VSS via a resistor (10 kΩ:
recommended) (in the input mode) or leave it open (in the output mode).
The above connection is not necessary when writing the flash memory by means of self programming.
3. Make the same potential as the VDD pin when port 2 is used as a digital port.
4. FLMD0 is a pin that is used to write data to the flash memory. To rewrite the data of the flash memory
on-board, connect this pin to VSS via a resistor (10 kΩ: recommended). The same applies when
executing on-chip debugging with a product with an on-chip debug function (
μ
PD78F0397D).
5. OCD0A and OCD0B are provided to the
μ
PD78F0397D only.
Remark For the product ranks, consult an NEC Electronics sales representative.
<R>
<R>
<R>
<R>
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD 41
Figure 2-1. Pin I/O Circuit List (1/2)
Type 2 Type 11-G
Schmitt-triggered input with hysteresis characteristics
IN
Data
Output
disable
AVREF
P-ch
IN/OUT
N-ch
P-ch
N-ch
AVREF
(threshold voltage)
Comparator
Input enable
+
_
AVSS
AVSS
Type 5-AG Type 13-AD
Pull-up
enable
Data
Output
disable
Input
enable
VDD
P-ch
VDD
P-ch
IN/OUT
N
-ch
VSS
Data
Output
disable
Input
enable
IN/OUT
N-ch
V
SS
Type 5-AH Type 17
Pull-up
enable
Data
Output
disable
Input
enable
VDD
P-ch
VDD
P-ch
IN/O
U
N
-ch
VSS
P-ch
N-ch
P-ch
N-ch
N-ch
N-ch
data OUT
V
LC0
V
LC1
SEG
V
LC2
P-ch
P-ch
CHAPTER 2 PIN FUNCTIONS
User’s Manual U17473EJ2V0UD
42
Figure 2-1. Pin I/O Circuit List (2/2)
Type 18 Type 38
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch P-ch
N-ch
data
P-ch N-ch
V
LC1
V
LC0
V
LC2
OUT
COM
Input
enable
IN
Type 37
Data
Output
disable
Input
enable
VDD
P-ch
X1,
XT1
N
-ch
VSS
Reset
Data
Output
disable
Input
enable
VDD
P-ch
N
-ch
VSS
Reset
P-ch
N-ch
X2,
XT2
User’s Manual U17473EJ2V0UD 43
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
Products in the 78K0/LG2 can each access a 64 KB memory space. Figures 3-1 to 3-6 show the memory maps.
Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size
switching register (IMS) and internal expansion RAM size switching register (IXS) of all
products in the 78K0/LG2 are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value
corresponding to each product as indicated below.
2. To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM
and internal expansion RAM areas do not overlap.
Table 3-1. Set Values of Internal Memory Size Switching Register (IMS)
and Internal Expansion RAM Size Switching Register (IXS)
Flash Memory Version
(78K0/LG2)
IMS IXS ROM
Capacity
Internal High-Speed
RAM Capacity
Internal Expansion
RAM Capacity
μ
PD78F0393 C8H 0CH 32 KB −
μ
PD78F0394 CCH 0AH 48 KB 1 KB
μ
PD78F0395 CFH 0BH 60 KB 2 KB
μ
PD78F0396 CCHNote 2 04H 96 KBNote 2 4 KB
μ
PD78F0397, 78F0397DNote 1 CCHNote 2 00H 128 KBNote 2
1 KB
6 KB
Notes 1. The ROM and RAM capacities of the products with the on-chip debug function can be debugged
according to the debug target products. Set IMS and IXS according to the debug target products.
2. The
μ
PD78F0396, 78F0397, and 78F0397D have internal ROMs of 96 KB and 128 KB, respectively.
However, the set value of IMS of these devices is the same as those of the 48 KB product because
memory banks are used. For how to set the memory banks, see 4.2 Memory Bank Select Register
(BANK).
<R>
<R>
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
44
Figure 3-1. Memory Map (
μ
PD78F0393)
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits
Program
memory space
Data memory
space
Vector table area
64 x 8 bits
CALLT table area
64 x 8 bits
Program area
1915 x 8 bits
Option byte area
Note1
5 x 8 bits
CALLF entry area
2048 x 8 bits
Program area
Program area
Option byte area
Note1
5 x 8 bits
Boot cluster 0
Note2
Boot cluster 1
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
8000H
7FFFH
0000H
0040H
003FH
0000H
0080H
007FH
0800H
07FFH
1000H
0FFFH
1085H
1084H
1080H
107FH
0085H
0084H
7FFFH
1FFFH
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 45
Figure 3-2. Memory Map (
μ
PD78F0394)
Internal expansion RAM
1024 x 8 bits
RAM spcae in
which instruction
can be fetched
Program RAM area
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
49152 x 8 bits
Program
memory space
Data memory
space
Vector table area
64 x 8 bits
CALLT table area
64 x 8 bits
Program area
1915 x 8 bits
Option byte area
Note1
5 x 8 bits
CALLF entry area
2048 x 8 bits
Program area
Program area
Option byte area
Note1
5 x 8 bits
Boot cluster 0
Note2
Boost cluster 1
Reserved
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
C000H
BFFFH
0000H
0040H
003FH
0000H
0080H
007FH
0800H
07FFH
1000H
0FFFH
1085H
1084H
1080H
107FH
0085H
0084H
BFFFH
1FFFH
F800H
F7FFH
F400H
F3FFH
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
46
Figure 3-3. Memory Map (
μ
PD78F0395)
Internal expansion RAM
2048 x 8 bits
RAM spcae in
which instruction
can be fetched
Program RAM area
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
61440 x 8 bits
Program
memory space
Data memory
space
Vector table area
64 x 8 bits
CALLT table area
64 x 8 bits
Program area
1915 x 8 bits
Option byte area
Note1
5 x 8 bits
CALLF entry area
2048 x 8 bits
Program area
Program area
Option byte area
Note1
5 x 8 bits
Boot cluster 0
Note2
Boot cluster 1
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
F000H
EFFFH
0000H
0040H
003FH
0000H
0080H
007FH
0800H
07FFH
1000H
0FFFH
1085H
1084H
1080H
107FH
0085H
0084H
EFFFH
1FFFH
F800H
F7FFH
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 47
Figure 3-4. Memory Map (
μ
PD78F0396)
0000H
Program
memory
space
Bank
area
Common
area
Internal expansion RAM
4096 x 8 bits
RAM spcae in
which instruction
can be fetched
Program RAM area
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits
Data memory
space
Vector table area
64 x 8 bits
CALLT table area
64 x 8 bits
Program area
1915 x 8 bits
Option byte area
Note1
5 x 8 bits
CALLF entry area
2048 x 8 bits
Program area
Program area
Option byte area
Note1
5 x 8 bits
Boot cluster 0
Note2
Boot cluster 1
Reserved
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
C000H
BFFFH
0040H
003FH
0000H
0080H
007FH
0800H
07FFH
1000H
0FFFH
1085H
1084H
1080H
107FH
0085H
0084H
7FFFH
1FFFH
F800H
F7FFH
E800H
E7FFH
8000H
7FFFH
Flash memory
16384 x 8 bits
(memory bank 0)
(Memory bank 1)
(Memory bank 2)
(Memory bank 3)
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
48
Figure 3-5. Memory Map (
μ
PD78F0397)
Internal expansion RAM
6144 x 8 bits
RAM spcae in
which instruction
can be fetched
Program RAM area
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits Vector table area
64 x 8 bits
CALLT table area
64 x 8 bits
Program area
1915 x 8 bits
Option byte area
Note1
5 x 8 bits
CALLF entry area
2048 x 8 bits
Program area
Program area
Option byte area
Note1
5 x 8 bits
Boot cluster 0
Note2
Boot cluster 1
Reserved
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
C000H
BFFFH
0040H
003FH
0000H
0080H
007FH
0800H
07FFH
1000H
0FFFH
1085H
1084H
1080H
107FH
0085H
0084H
7FFFH
1FFFH
F800H
F7FFH
E000H
DFFFH
8000H
7FFFH
Flash memory
16384 x 8 bits
(memory bank 0)
(Memory bank 1)
(Memory bank 2)
(Memory bank 3)
Data memory
space
Program
memory
space
0000H
(Memory bank 5)
(Memory bank 4)
Bank
area
Common
area
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 49
Figure 3-6. Memory Map (
μ
PD78F0397D)
Internal expansion RAM
6144 x 8 bits
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits Vector table area
64 x 8 bits
CALLT table area
64 x 8 bits
Program area
1905 x 8 bits
Option byte areaNote1
5 x 8 bits
CALLF entry area
2048 x 8 bits
Program area
Program area
Option byte areaNote1
5 x 8 bits
Boot cluster 0Note2
Boot cluster 1
Reserved
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
C000H
BFFFH
0040H
003FH
0000H
0080H
007FH
0800H
07FFH
1000H
0FFFH
1085H
1084H
1080H
107FH
0085H
0084H
7FFFH
1FFFH
F800H
F7FFH
E000H
DFFFH
8000H
7FFFH
Flash memory
16384 x 8 bits
(memory bank 0)
(Memory bank 1)
(Memory bank 2)
(Memory bank 3)
0000H
(Memory bank 5)
(Memory bank 4)
Data memory
space
RAM spcae in
which instruction
can be fetched
Program RAM area
Program
memory
space
Bank
area
Common
area
108FH
108EH
008FH
008EH
On-chip debug security
ID setting areaNote1
10 x 8 bits
On-chip debug security
ID setting areaNote1
10 x 8 bits
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 27.8 Security
Setting).
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
50
3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0/LG2 products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
μ
PD78F0393 32768 × 8 bits (0000H to 7FFFH)
μ
PD78F0394 49152 × 8 bits (0000H to BFFFH)
μ
PD78F0395 61440 × 8 bits (0000H to EFFFH)
μ
PD78F0396 98304 × 8 bits
(0000H to 7FFFH (common area) + 8000H to BFFFH (bank area) × 4)
μ
PD78F0397,
78F0397D
Flash memory
131072 × 8 bits
(0000H to 7FFFH (common area) + 8000H to BFFFH (bank area) × 6)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon reset signal input or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-3. Vector Table
Vector Table Address Interrupt Source Vector Table Address Interrupt Source
0000H RESET input, POC, LVI, WDT 001EH INTTM50
0004H INTLVI 0020H INTTM000
0006H INTP0 0022H INTTM010
0008H INTP1 0024H INTAD
000AH INTP2 0026H INTSR0
000CH INTP3 0028H INTWTI
000EH INTP4 002AH INTTM51
0010H INTP5 002CH INTKR
0012H INTSRE6 002EH INTWT
0014H INTSR6 0034H INTIIC0/INTDMUNote
0016H INTST6 0036HNote INTCSI11Note
0018H INTCSI10/INTST0 0038HNote INTTM001Note
001AH INTTMH1 003AHNote INTTM011Note
001CH INTTMH0 003EH BRK
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 51
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) Option byte area
A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte
at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot
swap is used. For details, see CHAPTER 26 OPTION BYTE.
(4) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
(5) On-chip debug security ID setting area (
μ
PD78F0397D only)
A 10-byte area of 0085H to 008EH and 1085H to 108EH can be used as an on-chip debug security ID setting
area. Set the on-chip debug security ID of 10 bytes at 0085H to 008EH when the boot swap is not used and at
0085H to 008EH and 1085H to 108EH when the boot swap is used. For details, see CHAPTER 28 ON-CHIP
DEBUG FUNCTION (
μ
PD78F0397D ONLY).
3.1.2 Memory bank (
μ
PD78F0396, 78F0397, and 78F0397D only)
The 16 KB area 8000H to BFFFH is assigned to memory banks 0 to 3 in the
μ
PD78F0396, and assigned to
memory banks 0 to 5 in the
μ
PD78F0397 and 78F0397D.
The banks are selected by using a memory bank select register (BANK). For details, see CHAPTER 4 MEMORY
BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)).
Cautions 1. Instructions cannot be fetched between different memory banks.
2. Branch and access cannot be directly executed between different memory banks. Execute
branch or access between different memory banks via the common area.
3. Allocate interrupt servicing in the common area.
4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0.
3.1.3 Internal data memory space
78K0/LG2 products incorporate the following RAMs.
(1) Internal high-speed RAM
Table 3-4. Internal High-Speed RAM Capacity
Part Number Internal High-Speed RAM
μ
PD78F0393
μ
PD78F0394
μ
PD78F0395
μ
PD78F0396
μ
PD78F0397, 78F0397D
1024 × 8 bits (FB00H to FEFFH)
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
<R>
<R>
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
52
(2) Internal expansion RAM
Table 3-5. Internal Expansion RAM Capacity
Part Number Internal Expansion RAM
μ
PD78F0393 −
μ
PD78F0394 1024 × 8 bits (F400H to F7FFH)
μ
PD78F0395 2048 × 8 bits (F000H to F7FFH)
μ
PD78F0396 4096 × 8 bits (E800H to F7FFH)
μ
PD78F0397, 78F0397D 6144 × 8 bits (E000H to F7FFH)
The internal expansion RAM can also be used as a normal data area similar to the internal high-speed RAM, as
well as a program area in which instructions can be written and executed.
The internal expansion RAM cannot be used as a stack memory.
(3) LCD display RAM
LCD display RAM is incorporated in the LCD controller/driver (see Figure 18-4 LCD Display RAM).
Table 3-6. LCD Display RAM Capacity
Part Number LCD Display RAM
μ
PD78F0393
μ
PD78F0394
μ
PD78F0395
μ
PD78F0396
μ
PD78F0397, 78F0397D
40 × 4 bits (00H to 27H of LCDSEG)
3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (see
Table 3-7 Special Function Register List in 3.2.3 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0/LG2, based on operability and other considerations. For areas containing data memory in particular, special
addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are
available for use. Figures 3-7 to 3-11 show correspondence between data memory and addressing. For details of
each addressing mode, see 3.4 Operand Address Addressing.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 53
Figure 3-7. Correspondence Between Data Memory and Addressing (
μ
PD78F0393)
SFR addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
8000H
7FFFH
0000H
FF20H
FF1FH
FE20H
FE1FH
Register addressing
Short direct
addressing
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
54
Figure 3-8. Correspondence Between Data Memory and Addressing (
μ
PD78F0394)
SFR addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
49152 x 8 bits
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
C000H
BFFFH
0000H
FF20H
FF1FH
FE20H
FE1FH
Register addressing
Short direct
addressing
Reserved
F800H
F7FFH
F400H
F3FFH
Internal expansion RAM
1024 x 8 bits
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 55
Figure 3-9. Correspondence Between Data Memory and Addressing (
μ
PD78F0395)
SFR addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
61440 x 8 bits
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
0000H
FF20H
FF1FH
FE20H
FE1FH
Register addressing
Short direct
addressing
F800H
F7FFH
F000H
EFFFH
Internal expansion RAM
2048 x 8 bits
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
56
Figure 3-10. Correspondence Between Data Memory and Addressing (
μ
PD78F0396)
16384 x 8 bits
(memory bank 2)
Note
SFR addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
C000H
BFFFH
0000H
FF20H
FF1FH
FE20H
FE1FH
Register addressing
Short direct
addressing
Reserved
F800H
F7FFH
E800H
E7FFH
Internal expansion RAM
4096 x 8 bits
FA00H
F9FFH
8000H
7FFFH
Flash memory
16384 x 8 bits
(memory bank 0)
Note
16384 x 8 bits
(memory bank 3)
Note
16384 x 8 bits
(memory bank 1)
Note
FA20H
FA1FH
Note To branch to or address a memory bank that is not set by the memory bank select register (BANK), change
the setting of the memory bank by using BANK.
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 57
Figure 3-11. Correspondence Between Data Memory and Addressing (
μ
PD78F0397, 78F0397D)
SFR addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
C000H
BFFFH
0000H
FF20H
FF1FH
FE20H
FE1FH
Register addressing
Short direct
addressing
Reserved
F800H
F7FFH
E000H
DFFFH
Internal expansion RAM
6144 x 8 bits
FA00H
F9FFH
8000H
7FFFH
Flash memory
16384 x 8 bits
(memory bank 0)
Note
16384 x 8 bits
(memory bank 2)
Note
16384 x 8 bits
(memory bank 3)
Note
16384 x 8 bits
(memory bank 1)
Note
16384 x 8 bits
(memory bank 4)
Note
16384 x 8 bits
(memory bank 5)
Note
FA20H
FA1FH
Note To branch to or address a memory bank that is not set by the memory bank select register (BANK), change
the setting of the memory bank by using BANK.
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
58
3.2 Processor Registers
The 78K0/LG2 products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-12. Format of Program Counter
15 0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets PSW to 02H.
Figure 3-13. Format of Program Status Word
7 0
PSW IE Z RBS1 AC RBS0 0 ISP CY
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgement and is set (1) upon EI
instruction execution.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 59
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L, PR1H)
(see 20.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)) can not be acknowledged.
Actual request acknowledgement is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-14. Format of Stack Pointer
15 0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-15 and 3-16.
Caution Since reset signal generation makes the SP contents undefined, be sure to initialize the SP
before using the stack.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
60
Figure 3-15. Data to Be Saved to Stack Memory
(a) PUSH rp instruction (when SP = FEE0H)
Register pair lower
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH
Register pair higher
FEDEH
(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)
PC15 to PC8
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH PC7 to PC0
FEDEH
(c) Interrupt, BRK instructions (when SP = FEE0H)
PC15 to PC8
PSW
FEDFH
FEE0H
SP
SP
FEE0H
FEDEH
FEDDH PC7 to PC0
FEDDH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 61
Figure 3-16. Data to Be Restored from Stack Memory
(a) POP rp instruction (when SP = FEDEH)
Register pair lower
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH
Register pair higher
FEDEH
(b) RET instruction (when SP = FEDEH)
PC15 to PC8
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH PC7 to PC0
FEDEH
(c) RETI, RETB instructions (when SP = FEDDH)
PC15 to PC8
PSW
FEDFH
FEE0H
SP
SP
FEE0H
FEDEH
FEDDH PC7 to PC0
FEDDH
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
62
3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-17. Configuration of General-Purpose Registers
(a) Function name
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEE0H
HL
DE
BC
AX
H
15 0 7 0
L
D
E
B
C
A
X
16-bit processing 8-bit processing
FEF0H
FEE8H
(b) Absolute name
BANK0
BANK1
BANK2
BANK3
FEFFH
FEF8H
FEE0H
RP3
RP2
RP1
RP0
R7
15 0 7 0
R6
R5
R4
R3
R2
R1
R0
16-bit processing 8-bit processing
FEF0H
FEE8H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 63
3.2.3 Special function registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH areas in the CPU, and are allocated to the 00H to 03H areas of
LCDCTL in the LCD controller/driver.
Special function registers of the CPU can be manipulated like general-purpose registers, using operation, transfer,
and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register
type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Remark For the operation method of special function registers in the LCD controller/driver, see 17.7
Communication with LCD Controller/Driver.
Table 3-7 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
as an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-QB, and
SM+, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
• After reset
Indicates each register status upon reset signal generation.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
64
Table 3-7. Special Function Register List (1/4)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FF00H Port register 0 P0 R/W √ √ − 00H
FF01H Port register 1 P1 R/W √ √ − 00H
FF02H Port register 2 P2 R/W √ √ − 00H
FF03H Port register 3 P3 R/W √ √ − 00H
FF06H Port register 6 P6 R/W √ √ − 00H
FF07H Port register 7 P7 R/W √ √ − 00H
FF08H 10-bit A/D conversion result register ADCR R − − √ 0000H
FF09H 8-bit A/D conversion result register ADCRH R − √ − 00H
FF0AH Receive buffer register 6 RXB6 R − √ − FFH
FF0BH Transmit buffer register 6 TXB6 R/W − √ − FFH
FF0CH Port register 12 P12 R/W √ √ − 00H
FF0DH Port register 13 P13 R/W √ √ − 00H
FF0FH Serial I/O shift register 10 SIO10 R − √ − 00H
FF10H
FF11H
16-bit timer counter 00 TM00 R − − √ 0000H
FF12H
FF13H
16-bit timer capture/compare register 000 CR000 R/W − − √ 0000H
FF14H
FF15H
16-bit timer capture/compare register 010 CR010 R/W − − √ 0000H
FF16H 8-bit timer counter 50 TM50 R − √ − 00H
FF17H 8-bit timer compare register 50 CR50 R/W − √ − 00H
FF18H 8-bit timer H compare register 00 CMP00 R/W − √ − 00H
FF19H 8-bit timer H compare register 10 CMP10 R/W − √ − 00H
FF1AH 8-bit timer H compare register 01 CMP01 R/W − √ − 00H
FF1BH 8-bit timer H compare register 11 CMP11 R/W − √ − 00H
FF1FH 8-bit timer counter 51 TM51 R − √ − 00H
FF20H Port mode register 0 PM0 R/W √ √ − FFH
FF21H Port mode register 1 PM1 R/W √ √ − FFH
FF22H Port mode register 2 PM2 R/W √ √ − FFH
FF23H Port mode register 3 PM3 R/W √ √ − FFH
FF26H Port mode register 6 PM6 R/W √ √ − FFH
FF27H Port mode register 7 PM7 R/W √ √ − FFH
FF28H A/D converter mode register ADM R/W √ √ − 00H
FF29H Analog input channel specification register ADS R/W √ √ − 00H
FF2CH Port mode register 12 PM12 R/W √ √ − FFH
FF2EH Port mode register 14 PM14 R/W √ √ − FFH
FF2FH A/D port configuration register ADPC R/W √ √ − 00H
FF30H Pull-up resistor option register 0 PU0 R/W √ √ − 00H
FF31H Pull-up resistor option register 1 PU1 R/W √ √ − 00H
FF33H Pull-up resistor option register 3 PU3 R/W √ √ − 00H
FF37H Pull-up resistor option register 7 PU7 R/W √ √ − 00H
FF3CH Pull-up resistor option register 12 PU12 R/W √ √ − 00H
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 65
Table 3-7. Special Function Register List (2/4)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FF40H Clock output selection register CKS R/W √ √ − 00H
FF41H 8-bit timer compare register 51 CR51 R/W − √ − 00H
FF43H 8-bit timer mode control register 51 TMC51 R/W √ √ − 00H
FF48H External interrupt rising edge enable register EGP R/W √ √ − 00H
FF49H External interrupt falling edge enable register EGN R/W √ √ − 00H
FF4AH Serial I/O shift register 11Note SIO11 R
− √ − 00H
FF4CH Transmit buffer register 11Note SOTB11 R/W − √ − 00H
FF4FH Input switch control register ISC R/W √ √ − 00H
FF50H Asynchronous serial interface operation mode
register 6
ASIM6 R/W √ √ − 01H
FF53H Asynchronous serial interface reception error
status register 6
ASIS6 R
− √ − 00H
FF55H Asynchronous serial interface transmission
status register 6
ASIF6 R
− √ − 00H
FF56H Clock selection register 6 CKSR6 R/W − √ − 00H
FF57H Baud rate generator control register 6 BRGC6 R/W − √ − FFH
FF58H Asynchronous serial interface control register 6 ASICL6 R/W √ √ − 16H
FF60H
SDR0L
− √ 00H
FF61H
Remainder data register 0Note SDR0
SDR0H
R
− √
√
00H
FF62H
MDA0LL
− √ 00H
FF63H
MDA0L
MDA0LH
R/W
− √
√
00H
FF64H
MDA0HL
− √ 00H
FF65H
Multiplication/division data register A0Note
MDA0H
MDA0HH
R/W
− √
√
00H
FF66H
MDB0L
− √ 00H
FF67H
Multiplication/division data register B0Note MDB0
MDB0H
R/W
− √
√
00H
FF68H Multiplier/divider control register 0Note DMUC0 R/W √ √ − 00H
FF69H 8-bit timer H mode register 0 TMHMD0 R/W √ √ − 00H
FF6AH Timer clock selection register 50 TCL50 R/W √ √ − 00H
FF6BH 8-bit timer mode control register 50 TMC50 R/W √ √ − 00H
FF6CH 8-bit timer H mode register 1 TMHMD1 R/W √ √ − 00H
FF6DH 8-bit timer H carrier control register 1 TMCYC1 R/W √ √ − 00H
FF6EH Key return mode register KRM R/W √ √ − 00H
FF6FH Watch timer operation mode register WTM R/W √ √ − 00H
FF70H Asynchronous serial interface operation mode
register 0
ASIM0 R/W √ √ − 01H
FF71H Baud rate generator control register 0 BRGC0 R/W − √ − 1FH
FF72H Receive buffer register 0 RXB0 R − √ − FFH
FF73H Asynchronous serial interface reception error
status register 0
ASIS0 R
− √ − 00H
FF74H Transmit shift register 0 TXS0 W − √ − FFH
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
66
Table 3-7. Special Function Register List (3/4)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FF80H Serial operation mode register 10 CSIM10 R/W √ √ − 00H
FF81H Serial clock selection register 10 CSIC10 R/W √ √ − 00H
FF84H Transmit buffer register 10 SOTB10 R/W − √ − 00H
FF88H Serial operation mode register 11Note 1 CSIM11 R/W √ √ − 00H
FF89H Serial clock selection register 11Note 1 CSIC11 R/W √ √ − 00H
FF8CH Timer clock selection register 51 TCL51 R/W √ √ − 00H
FF99H Watchdog timer enable register WDTE R/W − √ − Note 2
1AH/9AH
FF9FH Clock operation mode select register OSCCTL R/W √ √ − 00H
FFA0H Internal oscillation mode register RCM R/W √ √ − 80HNote 3
FFA1H Main clock mode register MCM R/W √ √ − 00H
FFA2H Main OSC control register MOC R/W √ √ − 80H
FFA3H Oscillation stabilization time counter status register OSTC R √ √ − 00H
FFA4H Oscillation stabilization time select register OSTS R/W − √ − 05H
FFA5H IIC shift register 0 IIC0 R/W − √ − 00H
FFA6H IIC control register 0 IICC0 R/W √ √ − 00H
FFA7H Slave address register 0 SVA0 R/W − √ − 00H
FFA8H IIC clock selection register 0 IICCL0 R/W √ √ − 00H
FFA9H IIC function expansion register 0 IICX0 R/W √ √ − 00H
FFAAH IIC status register 0 IICS0 R √ √ − 00H
FFABH IIC flag register 0 IICF0 R/W √ √ − 00H
FFACH Reset control flag register RESF R − √ − 00HNote 4
FFB0H
FFB1H
16-bit timer counter 01Note 1 TM01 R
− − √ 0000H
FFB2H
FFB3H
16-bit timer capture/compare register 001Note 1 CR001 R/W − − √ 0000H
FFB4H
FFB5H
16-bit timer capture/compare register 011Note 1 CR011 R/W − − √ 0000H
FFB6H 16-bit timer mode control register 01Note 1 TMC01 R/W √ √ − 00H
FFB7H Prescaler mode register 01Note 1 PRM01 R/W √ √ − 00H
FFB8H Capture/compare control register 01Note 1 CRC01 R/W √ √ − 00H
FFB9H 16-bit timer output control register 01Note 1 TOC01 R/W √ √ − 00H
FFBAH 16-bit timer mode control register 00 TMC00 R/W √ √ − 00H
FFBBH Prescaler mode register 00 PRM00 R/W √ √ − 00H
FFBCH Capture/compare control register 00 CRC00 R/W √ √ − 00H
FFBDH 16-bit timer output control register 00 TOC00 R/W √ √ − 00H
Notes 1.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
2. The reset value of WDTE is determined by setting of option byte.
3. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
internal high-speed oscillator has been stabilized.
4. The reset value of RESF varies depending on the reset source.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 67
Table 3-7. Special Function Register List (4/4)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FFBEH Low-voltage detection register LVIM R/W √ √ − 00HNote 1
FFBFH Low-voltage detection level selection register LVIS R/W √ √ − 00HNote 1
FFE0H Interrupt request flag register 0L IF0 IF0L R/W √ √ 00H
FFE1H Interrupt request flag register 0H IF0H R/W √ √
√
00H
FFE2H Interrupt request flag register 1L IF1 IF1L R/W √ √ 00H
FFE3H Interrupt request flag register 1H IF1H R/W √ √
√
00H
FFE4H Interrupt mask flag register 0L MK0 MK0L R/W √ √ FFH
FFE5H Interrupt mask flag register 0H MK0H R/W √ √
√
FFH
FFE6H Interrupt mask flag register 1L MK1 MK1L R/W √ √ FFH
FFE7H Interrupt mask flag register 1H MK1H R/W √ √
√
FFH
FFE8H Priority specification flag register 0L PR0 PR0L R/W √ √ FFH
FFE9H Priority specification flag register 0H PR0H R/W √ √
√
FFH
FFEAH Priority specification flag register 1L PR1 PR1L R/W √ √ FFH
FFEBH Priority specification flag register 1H PR1H R/W √ √
√
FFH
FFF0H Internal memory size switching registerNote 2 IMS R/W − √ − CFH
FFF3H Bank select register BANK R/W − √ − 00H
FFF4H Internal expansion RAM size switching
registerNote 2
IXS R/W − √ − 0CH
FFFBH Processor clock control register PCC R/W √ √ − 01H
LCDCTL's
00H
LCD mode setting register LCDMD R/W − √ − 00H
LCDCTL's
01H
LCD display mode register LCDM R/W − √ − 00H
LCDCTL's
02H
LCD clock control register LCDC R/W − √ − 00H
LCDCTL's
03H
LCD voltage boost control register 0 VLCG0 R/W − √ − 00H
Notes 1. The reset values of LVIM and LVIS vary depending on the reset source.
2. Regardless of the internal memory capacity, the initial values of the internal memory size switching
register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/LG2
are fixed (IMS = CFH, IXS = 0CH). Therefore, set the value corresponding to each product as indicated
below.
Flash Memory Version
(78K0/LG2)
IMS IXS ROM
Capacity
Internal High-Speed
RAM Capacity
Internal Expansion
RAM Capacity
μ
PD78F0393 C8H 0CH 32 KB −
μ
PD78F0394 CCH 0AH 48 KB 1 KB
μ
PD78F0395 CFH 0BH 60 KB 2 KB
μ
PD78F0396 CCH 04H 96 KB 4 KB
μ
PD78F0397, 78F0397D Note 3 CCH 00H 128 KB
1 KB
6 KB
3. The ROM and RAM capacities of the products with the on-chip debug function can be debugged
according to the debug target products. Set IMS and IXS according to the debug target products.
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
68
3.3 Instruction Address Addressing
An instruction address is determined by contents of the program counter (PC) and memory bank select register
(BANK), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an
instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch
destination information is set to PC and branched by the following addressing (for details of instructions, refer to the
78K/0 Series Instructions User’s Manual (U12326E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
+
15 0
876
S
15 0
PC
α
jdisp8
When S = 0, all bits of are 0.
When S = 1, all bits of are 1.
PC indicates the start address
of the instruction after the BR instruction.
...
α
α
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 69
3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. However, before
branching to a memory bank that is not set by the memory bank select register (BANK), change the setting of
the memory bank by using BANK.
The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
15 0
PC
87
70
CALL or BR
Low Addr.
High Addr.
In the case of CALLF !addr11 instruction
15 0
PC
87
70
fa10–8
11 10
00001
643
CALLF
fa7–0
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
70
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space. However, before branching to a memory bank that is not set by the memory bank
select register (BANK), change the setting of the memory bank by using BANK.
[Illustration]
15 1
15 0
PC
70
Low Addr.
High Addr.
Memory (Table)
Effective address+1
Effective address 01
00000000
87
87
65 0
0
111
765 10
ta4–0
Operation code
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
rp
07
AX
15 0
PC
87
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 71
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/LG2 instruction words, the following instructions employ implied addressing.
Instruction Register to Be Specified by Implied Addressing
MULU A register for multiplicand and AX register for product storage
DIVUW AX register for dividend and quotient storage
ADJBA/ADJBS A register for storage of numeric values that become decimal correction targets
ROR4/ROL4 A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
72
3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code 0 1100010
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code 1 0000100
Register specify code
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 73
3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank
that is not set by the memory bank select register (BANK), change the setting of the memory bank by using
BANK.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code 10001110 OP code
00000000 00H
11111110 FEH
[Illustration]
Memory
07
addr16 (lower)
addr16 (upper)
OP code
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
74
3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special
function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to the [Illustration] shown below.
[Operand format]
Identifier Description
saddr Immediate data that indicate label or FE20H to FF1FH
saddrp Immediate data that indicate label or FE20H to FF1FH (even address only)
[Description example]
LB1 EQU 0FE30H ; Defines FE30H by LB1.
:
MOV LB1, A ; When LB1 indicates FE30H of the saddr area and the value of register A is transferred to
that address
Operation code 1 1110010 OP code
0 0110000 30H (saddr-offset)
[Illustration]
15 0
Short direct memory
Effective address 1111111
87
07
OP code
saddr-offset
α
When 8-bit immediate data is 20H to FFH,
α
= 0
When 8-bit immediate data is 00H to 1FH,
α
= 1
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 75
3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special function register name
sfrp 16-bit manipulatable special function register name (even address
only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code 11110110 OP code
00100000 20H (sfr-offset)
[Illustration]
15 0
SFR
Effective address 1111111
87
07
OP code
sfr-offset
1
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
76
3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory.
This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank
that is not set by the memory bank select register (BANK), change the setting of the memory bank by using
BANK.
[Operand format]
Identifier Description
− [DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code 10000101
[Illustration]
16 08
D
7
E
07
7 0
A
DE
The contents of the memory
addressed are transferred.
Memory
The memory address
specified with the
register pair DE
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 77
3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored.
This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank
that is not set by the memory bank select register (BANK), change the setting of the memory bank by using
BANK.
[Operand format]
Identifier Description
− [HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code 10101110
00010000
[Illustration]
16 08
H
7
L
07
7 0
A
HL
The contents of the memory
addressed are transferred.
Memory +10
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD
78
3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory. Addition is performed by expanding the B or C register contents as a
positive number to 16 bits. A carry from the 16th bit is ignored.
This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank
that is not set by the memory bank select register (BANK), change the setting of the memory bank by using
BANK.
[Operand format]
Identifier Description
− [HL + B], [HL + C]
[Description example]
MOV A, [HL +B]; when selecting B register
Operation code 10101011
[Illustration]
16 0
H
78
L
07
B
+
07
7 0
A
HL
The contents of the memory
addressed are transferred.
Memory
<R>
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17473EJ2V0UD 79
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return
instructions are executed or the register is saved/reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
PUSH DE; when saving DE register
Operation code 10110101
[Illustration]
E
FEE0H
SP
SP
FEE0H
FEDFH
FEDEH
D
Memory 07
FEDEH
User’s Manual U17473EJ2V0UD
80
CHAPTER 4 MEMORY BANK SELECT FUNCTION
(
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
4.1 Memory Bank
The
μ
PD78F0396, 78F0397, and 78F0397D implement a ROM capacity of 96 KB or 128 KB by selecting a
memory bank from a memory space of 8000H to BFFFH.
The
μ
PD78F0396 has memory banks 0 to 3, and the
μ
PD78F0397 and 78F0397D have memory banks 0 to 5, as
shown below.
The memory banks are selected by using a memory bank select register (BANK).
Figure 4-1. Internal ROM (Flash Memory) Configuration
(a)
μ
PD78F0396
8000H
7FFFH
0000H
Flash memory
32768 × 8 bits
BFFFH
Flash memory
16384 × 8 bits
(memory bank 0)
(Memory bank 1)
(Memory bank 2)
Common
area
Bank
area
(Memory bank 3)
(b)
μ
PD78F0397, 78F0397D
8000H
7FFFH
0000H
Flash memory
32768 × 8 bits
BFFFH
Flash memory
16384 × 8 bits
(memory bank 0)
(Memory bank 1)
Common
area
Bank
area
(Memory bank 3)
(Memory bank 4)
(Memory bank 5)
(Memory bank 2)
<R>
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 81
4.2 Memory Bank Select Register (BANK)
The memory bank select register (BANK) is used to select a memory bank to be used.
BANK can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears BANK to 00H.
Figure 4-2. Format of Memory Bank Select Register (BANK)
Address: FFF3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
BANK 0 0 0 0 0 BANK2 BANK1 BANK0
Bank setting BANK2 BANK1 BANK0
μ
PD78F0396
μ
PD78F0397, 78F0397D
0 0 0 Common area (32 K) + memory bank 0 (16 K)
0 0 1 Common area (32 K) + memory bank 1 (16 K)
0 1 0 Common area (32 K) + memory bank 2 (16 K)
0 1 1 Common area (32 K) + memory bank 3 (16 K)
1 0 0 Common area (32 K) +
memory bank 4 (16 K)
1 0 1
Setting prohibited
Common area (32 K) +
memory bank 5 (16 K)
Other than above Setting prohibited
Caution Be sure to change the value of the BANK register in the common area (0000H to 7FFFH).
If the value of the BANK register is changed in the bank area (8000H to BFFFH), an inadvertent
program loop occurs in the CPU. Therefore, never change the value of the BANK register in the
bank area.
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD
82
4.3 Selecting Memory Bank
The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be
addressed. Therefore, to access a memory bank different from the one currently selected, that memory bank must be
selected by using the BANK register.
The value of the BANK register must not be changed in the bank area (8000H to BFFFH). Therefore, to change
the memory bank, branch an instruction to the common area (0000H to 7FFFH) and change the value of the BANK
register in that area.
Cautions 1. Instructions cannot be fetched between different memory banks.
2. Branching and accessing cannot be directly executed between different memory banks.
Execute branching or accessing between different memory banks via the common area.
3. Allocate interrupt servicing in the common area.
4. An instruction that extends from 7FFFH to 8000H can only be executed in memory bank 0.
4.3.1 Referencing values between memory banks
Values cannot be directly referenced from one memory bank to another.
To access another memory bank from one memory bank, branch once to the common area (0000H to 7FFFH),
change the setting of the BANK register there, and then reference a value.
Memory bank m
Common
area
Bank
area
Memory bank n
Referencing value
Common
area
Bank
area Referencing value
Memory bank m
Memory bank n
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 83
• Software example (to store a value to be referenced in register A)
RAMD DSEG SADDR
R_BNKA: DS 2 ; Secures RAM for specifying an address at the reference destination.
R_BNKN: DS 1 ; Secures RAM for specifying a memory bank number at the reference destination.
R_BNKRN: DS 1 ; Secures RAM for saving a memory bank number at the reference source.
ETRC CSEG UNIT
ENTRY:
MOV R_BNKN,#BANKNUM DATA1 ; Stores the memory bank number at the reference destination.
MOVW R_BNKA,#DATA1 ; Stores the address at the reference destination.
CALL !BNKRD ; Calls a subroutine for referencing between memory banks.
:
:
BNKC CSEG AT 7000H
BNKRD: ; Subroutine for referencing between memory banks.
PUSH HL ; Saves the contents of the HL register.
MOV A,R_BNKN ; Acquires the memory bank number at the reference destination.
XCH A,BANK ; Swaps the memory bank number at the reference source for that at the reference
; destination
MOV R_BNKRN,A ; Saves the memory bank number at the reference source.
XCHW AX,HL ; Saves the contents of the X register.
MOVW AX,R_BNKA ; Acquires the address at the reference destination.
XCHW AX,HL ; Specifies the address at the reference destination.
MOV A,[HL] ; Reads the target value.
XCH A,R_BNKRN ; Acquires the memory bank number at the reference source.
MOV BANK,A ; Specifies the memory bank number at the reference source.
MOV A,R_BNKRN ; Write the target value to the A register.
POP HL ; Restores the contents of the HL register.
RET ; Return
DATA CSEG BANK3
DATA1: DB 0AAH
END
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD
84
4.3.2 Branching instruction between memory banks
Instructions cannot branch directly from one memory bank to another.
To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH),
change the setting of the BANK register there, and then execute the branch instruction again.
Memory bank m
Common
area
Bank
area
Memory bank n
Instruction branch
Common
area
Bank
area Instruction branch
Memory bank m
Memory bank n
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 85
• Software example 1 (to branch from all areas)
• Software example 2 (to branch from common area to any bank area)
RAMD DSEG SADDR
R_BNKA: DS 2 ; Secures RAM for specifying a memory bank at the branch destination.
R_BNKN: DS 1 ; Secures RAM for specifying a memory bank number at the branch destination.
RSAVEAX: DS 2 ; Secures RAM for saving the AX register.
ETRC CSEG UNIT
ENTRY:
MOV R_BNKN,#BANKNUM TEST ; Stores the memory bank number at the branch destination in RAM.
MOVW R_BNKA,#TEST ; Stores the address at the branch destination in RAM.
BR !BNKBR ; Branches to inter-memory bank branch processing.
:
:
BNKC CSEG AT 7000H ;
BNKBR:
MOVW RSAVEAX,AX ; Saves the AX register.
MOV A,R_BNKN ; Acquires the memory bank number at the branch destination.
MOV BANK,A ; Specifies the memory bank number at the branch destination.
MOVW AX,R_BNKA ; Specifies the address at the branch destination.
PUSH AX ; Sets the address at the branch destination to stack.
MOVW AX,RSAVEAX ; Restores the AX register.
RET ; Branch
BN3 CSEG BANK3
TEST:
MOV ⋅⋅⋅
:
:
END
ETRC CSEG AT 2000H
ENTRY:
MOV R_BNKN,#BANKNUM TEST ; Stores the memory bank number at the branch destination in RAM.
BR !TEST ; Stores the address at the branch destination in RAM.
BN3 CSEG BANK3
TEST:
MOV ⋅⋅⋅
:
:
END
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD
86
4.3.3 Subroutine call between memory banks
Subroutines cannot be directly called between memory banks.
To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the
memory bank at the calling destination by using the BANK register there, execute the CALL instruction, and branch to
the call destination by that instruction.
At this time, save the current value of the BANK register to RAM. Restore the value of the BANK register before
executing the RET instruction.
Memory bank m
Common
area
Bank
area
Memory bank n
BR instruction
Common
area
Bank
area CALL instruction
Memory bank m
Memory bank n
CALL
inst-
ruction CALL
instruction
Change BANK and save
memory bank number at
calling source.
RET instruction
RET instruction
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 87
• Software example
Remark In the software example above, multiplexed processing is not supported.
RAMD DSEG SADDR
R_BNKA: DS 2 ; Secures RAM for specifying an address at the calling destination.
R_BNKN: DS 1 ; Secures RAM for specifying a memory bank number at the calling destination.
R_BNKRN: DS 1 ; Secures RAM for saving a memory bank number at the calling source.
RSAVEAX: DS 2 ; Secures RAM for saving the AX register.
ETRC CSEG UNIT
ENTRY:
MOV R_BNKN,#BANKNUM TEST ; Store the memory bank number at the calling destination in RAM.
MOVW R_BNKA,#TEST ; Stores the address at the calling destination in RAM.
CALL !BNKCAL ; Branches to an inter-memory bank calling processing routine.
:
:
BNKC CSEG AT 7000H
BNKCAL: ; Inter-memory bank calling processing routine
MOVW RSAVEAX,AX ; Saves the AX register.
MOV A,R_BNKN ; Acquires the memory bank number at the calling destination.
XCH A,BANK ; Changes the bank and acquires the memory bank number at the calling source.
MOV R_BNKRN,A ; Saves the memory bank number at the calling source to RAM.
CALL !BNKCALS ; Calls a subroutine to branch to the calling destination.
MOVW RSAVEAX,AX ; Saves the AX register.
XCH A,R_BNKRN ; Acquires the memory bank number at the calling source.
MOV BANK,A ; Specifies the memory bank number at the calling source.
MOVW AX,RSAVEAX ; Restores the AX register.
RET ; Returns to the calling source.
BNKCALS:
MOVW AX,R_BNKA ; Specifies the address at the calling destination.
PUSH AX ; Sets the address at the calling destination to stack.
MOVW AX,RSAVEAX ; Restores source AX register.
RET AX ; Branches to the calling destination.
BN3 CSEG BANK3
TEST: ;
MOV ⋅⋅⋅
:
:
RET
END
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD
88
4.3.4 Instruction branch to bank area by interrupt
When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the
vector table, but it is difficult to identify the BANK register when the interrupt occurs.
Therefore, specify the branch destination address specified by the vector table in the common area (0000H to
7FFFH), specify the memory bank at the branch destination by using the BANK register in the common area, and
execute the CALL instruction. At this time, save the BANK register value before the change to RAM, and restore the
value of the BANK register before executing the RETI instruction.
Remark Allocate interrupt servicing that requires a quick response in the common area.
Memory bank m
Common
area
Bank
area
Memory bank n
Instruction branch
Save the original memory bank number.
Specify the address and memory bank
at the destination, and execute the call
instruction.
Vector table
• Software example (when using interrupt request of 16-bit timer/event counter 00)
VCTBL CSEG AT 0020H
DW BNKITM000 ; Specifies an address at the timer interrupt destination.
RAMD DSEG SADDR
R_BNKRN: DS 1 ; Secures RAM for saving the memory bank number before the interrupt occurs.
BNKC CSEG AT 7000H
BNKITM000: ; Inter-memory bank interrupt servicing routine
PUSH AX ; Saves the contents of the AX register.
MOV A,BANK
MOV R_BNKRN,A ; Saves the memory bank number before the interrupt to RAM.
MOV BANK,#BANKNUM TEST ; Specifies the memory bank number of the interrupt routine.
CALL !TEST ; Calls the interrupt routine.
MOV A,R_BNKRN ; Restores the memory bank number before the interrupt.
MOV BANK,A
POP AX ; Restores the contents of the AX register.
RETI
BN3 CSEG BANK3
TEST: ; Interrupt servicing routine
MOV ⋅⋅⋅
:
:
RET
END
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 89
Remark Note the following points to use the memory bank select function efficiently.
• Allocate a routine that is used often in the common area.
• If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas.
• If the reference destination and the branch destination of the routine placed in a memory bank are
placed in the same memory bank, then the code size and processing are more efficient.
• Allocate interrupt servicing that requires a quick response in the common area.
User’s Manual U17473EJ2V0UD
90
CHAPTER 5 PORT FUNCTIONS
5.1 Port Functions
There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power
supplies and the pins is shown below.
Table 5-1. Pin I/O Buffer Power Supplies
Power Supply Corresponding Pins
AVREF P20 to P27
VDD Port pins other than P20 to P27
78K0/LG2 products are provided with the ports shown in Figure 5-1, which enable variety of control operations.
The functions of each port are shown in Table 5-2.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, see CHAPTER 2 PIN FUNCTIONS.
Figure 5-1. Port Types
P20
P27
Port 3
P30
P33
P00
P06
P10
P17
P70
P77
P120
P124
Port 7
Port 12
Port 0
Port 1
Port 2
Port 6
Note
P60
P61
Note In the 78K0/LG2, be sure to use the P60/SCL0 and P61/SDA0 as the serial clock I/O pin and serial data I/O
pin, respectively, in accordance with the specifications.
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 91
Table 5-2. Port Functions
Function Name I/O Function After Reset Alternate Function
P00 TI000
P01 TI010/TO00
P02 SO11Note1
P03 SI11Note1
P04 SCK11Note1
P05 SSI11Note1/TI001Note1
P06
I/O Port 0.
7-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI011Note1/TO01Note1
P10 SCK10/TxD0
P11 SI10/RxD0
P12 SO10
P13 TxD6
P14 RxD6
P15 TOH0
P16 TOH1/INTP5
P17
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
TI50/TO50
P20 to P27 I/O Port 2.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Analog
input
ANI0 to ANI7
P30 INTP1
P31 INTP2/OCD1A Note2
P32 INTP3/OCD1B Note2
P33
I/O Port 3.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port
INTP4/TI51/TO51
P60 SCL0
P61
I/O Port 6.
2-bit I/O port.
N-ch open-drain output (6 V tolerance).
Input/output can be specified in 1-bit units.
Input port
SDA0
P70 to P77 I/O Port 7.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Input port KR0 to KR7
P120 INTP0/EXLVI
P121 X1/OCD0ANote2
P122 X2/EXCLK/OCD0BNote2
P123 XT1
P124
I/O Port 12.
5-bit I/O port.
Input/output can be specified in 1-bit units.
Only for P120, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
XT2/EXCLKS
Notes 1.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
2.
μ
PD78F0397D only.
Remark The port function of P60 and P61 is used only when initializing the pin level of I2C bus.
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
92
5.2 Port Configuration
Ports include the following hardware.
Table 5-3. Port Configuration
Item Configuration
Control registers Port mode register (PM0 to PM3, PM6, PM7, PM12, PM14)
Port register (P0 to P3, P6, P7, P12)
Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12)
A/D port configuration register (ADPC)
Port Total: 40
Pull-up resistor Total: 28
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 93
5.2.1 Port 0
Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O, serial interface data I/ONote, and clock I/O.
Reset signal generation sets port 0 to input mode.
Figures 5-2 to 5-7 show block diagrams of port 0.
Caution When P02/SO11Note and P04/SCK11Note are used as general-purpose ports, set serial operation
mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the initial setting
(00H).
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Figure 5-2. Block Diagram of P00
P00/TI000
WRPU
RD
WRPORT
WRPM
PU00
Alternate function
Output latch
(P00)
PM00
VDD
P-ch
Selector
Internal bus
PU0
PM0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
94
Figure 5-3. Block Diagram of P01
P01/TI010/TO00
WRPU
RD
WRPORT
WRPM
PU01
Alternate
function
Output latch
(P01)
PM01
Alternate
function
VDD
P-ch
Selector
Internal bus
PU0
PM0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 95
Figure 5-4. Block Diagram of P02
Internal bus
P02/SO11
Note
WRPU
RD
WRPORT
WRPM
PU02
Output latch
(P02)
PM02
Alternate
function
Note
VDD
P-ch
PU0
PM0
Selector
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
96
Figure 5-5. Block Diagram of P03 and P05
(a)
μ
PD78F0393
P03, P05
WR
PU
RD
WR
PORT
WR
PM
PU03, PU05
Output latch
(P03, P05)
PM03, PM05
V
DD
P-ch
Selector
Internal bus
PU0
PM0
(b)
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D
P03/SI11,
P05/SSI11/TI001
WR
PU
RD
WR
PORT
WR
PM
PU03, PU05
Alternate function
Output latch
(P03, P05)
PM03, PM05
V
DD
P-ch
Selector
Internal bus
PU0
PM0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 97
Figure 5-6. Block Diagram of P04
(a)
μ
PD78F0393
P04
WR
PU
RD
WR
PORT
WR
PM
PU04
Output latch
(P04)
PM04
V
DD
P-ch
Selector
Internal bus
PU0
PM0
(b)
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D
P04/SCK11
WR
PU
RD
WR
PORT
WR
PM
PU04
Alternate
function
Output latch
(P04)
PM04
Alternate
function
V
DD
P-ch
Selector
Internal bus
PU0
PM0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
98
Figure 5-7. Block Diagram of P06
(a)
μ
PD78F0393
P06
WR
PU
RD
WR
PORT
WR
PM
PU06
Output latch
(P06)
PM06
V
DD
P-ch
Selector
Internal bus
PU0
PM0
(b)
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D
P06/TI011/TO01
WR
PU
RD
WR
PORT
WR
PM
PU06
Alternate
function
Output latch
(P06)
PM06
Alternate
function
V
DD
P-ch
Selector
Internal bus
PU0
PM0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 99
5.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
Reset signal generation sets port 1 to input mode.
Figures 5-8 to 5-12 show block diagrams of port 1.
Caution When P10/SCK10/TxD0 and P12/SO10 are used as general-purpose ports, set serial operation
mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the initial setting
(00H).
Figure 5-8. Block Diagram of P10
P10/SCK10/TxD0
WRPU
RD
WRPORT
WRPM
PU10
Alternate
function
Output latch
(P10)
PM10
Alternate
function
VDD
P-ch
Selector
Internal bus
PU1
PM1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
100
Figure 5-9. Block Diagram of P11 and P14
P11/SI10/RxD0,
P14/RxD6
WR
PU
RD
WR
PORT
WR
PM
PU11, PU14
Alternate
function
Output latch
(P11, P14)
PM11, PM14
V
DD
P-ch
Selector
Internal bus
PU1
PM1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 101
Figure 5-10. Block Diagram of P12 and P15
P12/SO10
P15/TOH0
WR
PU
RD
WR
PORT
WR
PM
PU12, PU15
Output latch
(P12, P15)
PM12, PM15
Alternate
function
V
DD
P-ch
Selector
Internal bus
PU1
PM1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
102
Figure 5-11. Block Diagram of P13
P13/TxD6
WRPU
RD
WRPORT
WRPM
PU13
Output latch
(P13)
PM13
Alternate
function
VDD
P-ch
Internal bus
Selector
PU1
PM1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 103
Figure 5-12. Block Diagram of P16 and P17
P16/TOH1/INTP5,
P17/TI50/TO50
WRPU
RD
WRPORT
WRPM
PU16, PU17
Alternate
function
Output latch
(P16, P17)
PM16, PM17
Alternate
function
VDD
P-ch
Selector
Internal bus
PU1
PM1
PU1: Pull-up resistor option register 1
PM1: Port mode register 1
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
104
5.2.3 Port 2
Port 2 is an 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units
using port mode register 2 (PM2).
This port can also be used for A/D converter analog input.
When P20/ANI0 to P27/ANI7 are used as digital input ports, select digital I/O using the A/D port configuration
register (ADPC), set the input mode using PM2, and then use these ports from the lower bits.
When P20/ANI0 to P27/ANI7 are used as digital output ports, select digital I/O using ADPC, and then set output
mode using PM2.
Table 5-4. Settings of P20/ANI0 to P27/ANI7 pin function
ADPC Setting PM2 Setting ADS Setting P20/ANI0 to P27/ANI7 Pins
Input mode − Digital input Digital I/O selection
Output mode − Digital output
ANI selection Analog input (target for
conversion)
Input mode
ANI non-selection Analog input (target for non-
conversion)
ANI selection
Analog input selection
Output mode
ANI non-selection
Setting prohibited
When a reset signal is generated, P20/ANI0 to P27/ANI7 are all set to analog input mode.
Figure 5-13 shows a block diagram of port 2.
Caution Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port.
Figure 5-13. Block Diagram of P20 to P27
Internal bus
P20/ANI0 to
P27/ANI7
RD
WR
PORT
WR
PM
Output latch
(P20 to P27)
PM20 to PM27
Selector
PM2
A/D converter
PM2: Port mode register 2
RD: Read signal
WR××: Write signal
<R>
<R>
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 105
5.2.4 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified in
1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input and timer I/O.
Reset signal generation sets port 3 to input mode.
Figures 5-14 and 5-15 show block diagrams of port 3.
Caution In the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D, be sure to pull the P31 pin down
before a reset release, to prevent malfunction.
Remark The P31 and P32 pins of the
μ
PD78F0397D can be used as on-chip debug mode setting pins (OCD1A,
OCD1B) when the on-chip debug function is used. For details, see CHAPTER 28 ON-CHIP DEBUG
FUNCTION (
μ
PD78F0397D ONLY).
Figure 5-14. Block Diagram of P30 to P32
P30/INTP1 to
P32/INTP3
WRPU
RD
WRPORT
WRPM
PU30 to PU32
Alternate
function
Output latch
(P30 to P32)
PM30 to PM32
VDD
P-ch
Selector
Internal bus
PU3
PM3
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
106
Figure 5-15. Block Diagram of P33
P33/INTP4/TI51/TO51
WRPU
RD
WRPORT
WRPM
PU33
Alternate
function
Output latch
(P33)
PM33
Alternate
function
VDD
P-ch
Selector
Internal bus
PU3
PM3
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 107
5.2.5 Port 6
Port 6 is an 2-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units
using port mode register 6 (PM6). When the P60 and P61 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6).
The output of the P60 and P61 pins is N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface clock I/O and data I/O.
Reset signal generation sets port 6 to input mode.
Figure 5-16 shows block diagrams of port 6.
Caution In the 78K0/LG2, be sure to use the P60/SCL0 and P61/SDA0 as the serial clock I/O pin and serial data
I/O pin, respectively, in accordance with the specifications.
Figure 5-16. Block Diagram of P60 and P61
P60/SCL0,
P61/SDA0
RD
WR
PORT
WR
PM
Alternate
function
Output latch
(P60, P61)
PM60, PM61
Alternate
function
Internal bus
Selector
PM6
P6
P6: Port register 6
PM6: Port mode register 6
RD: Read signal
WR××: Write signal
<R>
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
108
5.2.6 Port 7
Port 7 is an 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units
using port mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up
resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7).
This port can also be used for key return input.
Reset signal generation sets port 7 to input mode.
Figure 5-17 shows a block diagram of port 7.
Figure 5-17. Block Diagram of P70 to P77
P70/KR0 to
P77/KR7
WRPU
RD
WRPORT
WRPM
PU70 to PU77
Alternate
function
Output latch
(P70 to P77)
PM70 to PM77
VDD
P-ch
Selector
Internal bus
PU7
PM7
PU7: Pull-up resistor option register 7
PM7: Port mode register 7
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 109
5.2.7 Port 12
Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can
be specified by pull-up resistor option register 12 (PU12).
This port can also be used as pins for external interrupt request input, potential input for external low-voltage
detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input
for main system clock, and external clock input for subsystem clock.
Reset signal generation sets port 12 to input mode.
Figures 5-18 and 5-19 show block diagrams of port 12.
Caution When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or
subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or
subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock
input mode must be set by using the clock operation mode select register (OSCCTL) (for details,
see 6.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode for
subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are I/O port
pins). At this time, setting of the PM121 to PM124 and P121 to P124 pins is not necessary.
Remark The X1 and X2 pins of the
μ
PD78F0397D can be used as on-chip debug mode setting pins (OCD0A,
OCD0B) when the on-chip debug function is used. For details, see CHAPTER 28 ON-CHIP DEBUG
FUNCTION (
μ
PD78F0397D ONLY).
Figure 5-18. Block Diagram of P120
P120/INTP0/EXLVI
WRPU
RD
WRPORT
WRPM
PU120
Alternate
function
Output latch
(P120)
PM120
VDD
P-ch
Selector
Internal bus
PU12
PM12
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
110
Figure 5-19. Block Diagram of P121 to P124
P122/X2/EXCLK,
P124/XT2/EXCLKS
RD
WR
PORT
WR
PM
Output latch
(P122/P124)
PM122/PM124
PM12
PM12
RD
WR
PORT
WR
PM
Output latch
(P121/P123)
PM121/PM123
PM12
PM12
EXCLK, OSCSEL/
EXCLKS, OSCSELS
OSCCTL
OSCSEL/
OSCSELS
OSCCTL
P121/X1,P123/XT1
OSCSEL/
OSCSELS
OSCCTL
OSCSEL/
OSCSELS
OSCCTL
Selector
Selector
Internal bus
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 111
5.3 Registers Controlling Port Function
Port functions are controlled by the following four types of registers.
• Port mode registers (PM0 to PM3, PM6, PM7, PM12, PM14)
• Port registers (P0 to P3, P7, P12)
• Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12)
• A/D port configuration register (ADPC)
(1) Port mode registers (PM0 to PM3, PM6, PM7, PM12 and PM14)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register by referencing 5.5 Settings of
Port Mode Register and Output Latch When Using Alternate Function.
Figure 5-20. Format of Port Mode Register
7
1
Symbol
PM0
6
PM06
5
PM05
4
PM04
3
PM03
2
PM02
1
PM01
0
PM00
Address
FF20H
After reset
FFH
R/W
R/W
PM17
PM1 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R/W
PM27
PM2 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W
1
PM3 1 1 1 PM33 PM32 PM31 PM30 FF23H FFH R/W
PM77
PM7 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R/W
1
PM12 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R/W
1
PM6 1 1 1 1 PM62 PM61 PM60 FF26H FFH R/W
1
PM14 1 1 1 1 1 PM141 PM140 FF2EH FFH R/W
PMmn Pmn pin I/O mode selection
(m = 0 to 3, 6, 7, 12, 14; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Caution After a reset release, be sure to set PM62 and PM141 to 0.
<R>
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
112
(2) Port registers (P0 to P3, P6, P7, P12)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output
latch is read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 5-21. Format of Port Register
7
0
Symbol
P0
6
P06
5
P05
4
P04
3
P03
2
P02
1
P01
0
P00
Address
FF00H
After reset
00H (output latch)
R/W
R/W
P17
P1 P16 P15 P14 P13 P12 P11 P10 FF01H 00H (output latch) R/W
R/W
P27
P2 P26 P25 P24 P23 P22 P21 P20 FF02H 00H (output latch)
0
P3 0 0 0 P33 P32 P31 P30 FF03H 00H (output latch) R/W
P77
P7 P76 P75 P74 P73 P72 P71 P70 FF07H 00H (output latch) R/W
0
P12 0 0 P124
Note
P123
Note
P122
Note
P121
Note
P120 FF0CH 00H (output latch) R/W
0
P6 0 0 0 0 0 P61 P60 FF06H 00H (output latch) R/W
m = 0 to 3, 6, 7, 12; n = 0 to 7
Pmn
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Note “0” is always read from the output latch of P121 to P124 if the pin is in the external clock input mode.
Remark For P13, see 18.4 Registers Controlling LCD Controller/Driver.
<R>
<R>
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 113
(3) Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12)
These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P70 to P77,
and P120 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input
mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU7, and
PU12. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-
function output pins, regardless of the settings of PU0, PU1, PU3, PU7, and PU12.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 5-22. Format of Pull-up Resistor Option Register
7
0
Symbol
PU0
6
PU06
5
PU05
4
PU04
3
PU03
2
PU02
1
PU01
0
PU00
Address
FF30H
After reset
00H
R/W
R/W
PU17
PU1 PU16 PU15 PU14 PU13 PU12 PU11 PU10 FF31H 00H R/W
0
PU3 0 0 0 PU33 PU32 PU31 PU30 FF33H 00H R/W
PU77
PU7 PU76 PU75 PU74 PU73 PU72 PU71 PU70 FF37H 00H R/W
0
PU12 0 0 0 0 0 0 PU120 FF3CH 00H R/W
PUmn Pmn pin on-chip pull-up resistor selection
(m = 0, 1, 3, 7, 12; n = 0 to 7)
0 On-chip pull-up resistor not connected
1 On-chip pull-up resistor connected
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
114
(4) A/D port configuration register (ADPC)
This register switches the P20/ANI0 to P27/ANI7 pins to analog input of A/D converter or digital I/O of port.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-23. Format of A/D Port Configuration Register (ADPC)
ADPC0ADPC1ADPC2ADPC30000
Analog input (A)/digital I/O (D) switching
Setting prohibited
ADPC3
01234567
ADPC
Address: FF2FH After reset: 00H R/W
Symbol
P27/
ANI7
A
A
A
A
A
A
A
A
D
P26/
ANI6
A
A
A
A
A
A
A
D
D
P25/
ANI5
A
A
A
A
A
A
D
D
D
P24/
ANI4
A
A
A
A
A
D
D
D
D
P23/
ANI3
A
A
A
A
D
D
D
D
D
P22/
ANI2
A
A
A
D
D
D
D
D
D
P21/
ANI1
A
A
D
D
D
D
D
D
D
P20/
ANI0
A
D
D
D
D
D
D
D
D
0
0
0
0
0
0
0
0
1
ADPC2
0
0
0
0
1
1
1
1
0
ADPC1
0
0
1
1
0
0
1
1
0
ADPC0
0
1
0
1
0
1
0
1
0
Other than above
Cautions 1. Set the channel used for A/D conversion in the input mode by using port mode register 2
(PM2).
2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU
is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 33 CAUTIONS FOR WAIT.
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 115
5.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the
port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the
output latch contents for pins specified as input are undefined, even for bits other than the
manipulated bit.
5.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
5.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
5.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
The pin level is read and an operation is performed on its contents. The result of the operation is written to the
output latch, but since the output buffer is off, the pin status does not change.
The data of the output latch is cleared when a reset signal is generated.
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
116
5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function
When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table
5-5.
Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function
Alternate Function Pin Name
Function Name I/O
PM×× P××
P00 TI000 Input 1 ×
TI010 Input 1
×
P01
TO00 Output 0 0
P02 SO11Note1 Output 0 0
P03 SI11Note1 Input 1
×
Input 1 ×
P04 SCK11Note1
Output 0 1
SSI11Note1 Input 1
×
P05
TI001Note1 Input 1
×
TI011Note1 Input 1
×
P06
TO01Note1 Output 0 0
Input 1 ×
SCK10
Output 0 1
P10
TxD0 Output 0 1
SI10 Input 1
×
P11
RxD0 Input 1
×
P12 SO10 Output 0 0
P13 TxD6 Output 0 1
P14 RxD6 Input 1 ×
P15 TOH0 Output 0 0
TOH1 Output 0 0 P16
INTP5 Input 1
×
TI50 Input 1
×
P17
TO50 Output 0 0
P20 to P27Note2 ANI0 to ANI7Note2 Input 1
×
P30 to P32 INTP1 to INTP3 Input 1 ×
INTP4 Input 1
×
TI51 Input 1
×
P33
TO51 Output 0 0
P60 SCL0 I/O 0 0
P61 SDA0 I/O 0 0
P70 to P77 KR0 to KR7 Input 1 ×
INTP0 Input 1
×
P120
EXLVI Input 1
×
P121 X1Note3 − × ×
X2Note3 − × ×
P122
EXCLKNote3 Input
× ×
P123 XT1Note3 − × ×
XT2Note3 − × ×
P124
EXCLKSNote3 Input
× ×
(Refer to Notes and Remarks on the next page.)
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD 117
Notes1.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
2. The functions of the ANI0/P20 to ANI7/P27 pins are determined according to the settings of A/D port
configuration register (ADPC), Analog input channel specification register (ADS), and PM2.
Table 5-6. Settings of ANI0/P20 to ANI7/P27 pin function
ADPC Setting PM2 Setting ADS Setting P20/ANI0 to P27/ANI7 Pins
ANI selection Analog input (target for
conversion)
Input mode
ANI non-selection Analog input (target for non-
conversion)
ANI selection
Analog input selection
Output mode
ANI non-selection
Setting prohibited
Input mode − Digital input Digital I/O selection
Output mode − Digital output
3. When using P121/X1, P122/X2/EXCLK, P123/XT1, or P124/XT2/EXCLKS to connect a resonator for the
main system clock or subsystem clock, or to input an external clock, the X1 oscillation mode, XT1
oscillation mode, or external clock input mode must be set by using the clock operation mode select
register (OSCCTL) (for details, see 5.3 (1) Clock operation mode select register (OSCCTL) and (3)
Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all P121 to
P124 are I/O port pins). At this time, settings of PM121 to PM124 and P121 to P124 are not necessary.
Remarks1. ×: Don’t care
PM××: Port mode register
P××: Port output latch
2. The X1, X2, P31, and P32 pins of the
μ
PD78F0397D can be used as on-chip debug mode setting pins
(OCD0A, OCD0B, OCD1A, OCD1B) when the on-chip debug function is used. For details, see
CHAPTER 28 ON-CHIP DEBUG FUNCTION (
μ
PD78F0397D ONLY).
<R>
CHAPTER 5 PORT FUNCTIONS
User’s Manual U17473EJ2V0UD
118
5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the
output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example> When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port
latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level
via a 1-bit manipulation instruction, the output latch value of port 1 is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the
output latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the 78K0/LG2.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses
of P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at
this time, the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
Figure 5-24. Bit Manipulation Instruction (P10)
Low-level output
1-bit manipulation
instruction
(set1 P1.0)
is executed for P10
bit.
Pin status: High level
P10
P11 to P17
Port 1 output latch
00000000
Low-level output
Pin status: High level
P10
P11 to P17
Port 1 output latch
11111111
1-bit manipulation instruction for P10 bit
<1> Port register 1 (P1) is read in 8-bit units.
• In the case of P10, an output port, the value of the port output latch (0) is read.
• In the case of P11 to P17, input ports, the pin status (1) is read.
<2> Set the P10 bit to 1.
<3> Write the results of <2> to the output latch of port register 1 (P1)
in 8-bit units.
<R>
User’s Manual U17473EJ2V0UD 119
CHAPTER 6 CLOCK GENERATOR
6.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
<1> X1 oscillator
This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or using the main OSC control register
(MOC).
<2> Internal high-speed oscillator
This circuit oscillates a clock of fRH = 8 MHz (TYP.). After a reset release, the CPU always starts
operating with this internal high-speed oscillation clock. Oscillation can be stopped by executing the
STOP instruction or using the internal oscillation mode register (RCM).
An external main system clock (fEXCLK = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An
external main system clock input can be disabled by executing the STOP instruction or using RCM.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal high-
speed oscillation clock can be selected by using the main clock mode register (MCM).
(2) Subsystem clock
• Subsystem clock oscillator
This circuit oscillates at a frequency of fXT = 32.768 kHz by connecting a 32.768 kHz resonator across XT1
and XT2. Oscillation can be stopped by using the processor clock control register (PCC) and clock
operation mode select register (OSCCTL).
An external subsystem clock (fEXCLKS = 32.768 kHz) can also be supplied from the EXCLKS/XT2/P124 pin. An
external subsystem clock input can be disabled by setting PCC and OSCCTL.
Remarks 1. fX: X1 clock oscillation frequency
2. fRH: Internal high-speed oscillation clock frequency
3. fEXCLK: External main system clock frequency
4. fXT: XT1 clock oscillation frequency
5. fEXCLKS: External subsystem clock frequency
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
120
(3) Internal low-speed oscillation clock (clock for watchdog timer)
• Internal low-speed oscillator
This circuit oscillates a clock of fRL = 240 kHz (TYP.). After a reset release, the internal low-speed oscillation
clock always starts operating.
Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed
oscillator can be stopped by software” is set by option byte.
The internal low-speed oscillation clock cannot be used as the CPU clock. The following hardware operates
with the internal low-speed oscillation clock.
• Watchdog timer
• TMH1 (when fRL, fRL/27, or fRL/29 is selected)
Remark fRL: Internal low-speed oscillation clock frequency
6.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 6-1. Configuration of Clock Generator
Item Configuration
Control registers Clock operation mode select register (OSCCTL)
Processor clock control register (PCC)
Internal oscillation mode register (RCM)
Main OSC control register (MOC)
Main clock mode register (MCM)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillators X1 oscillator
XT1 oscillator
Internal high-speed oscillator
Internal low-speed oscillator
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 121
<R> Figure 6-1. Block Diagram of Clock Generator
Option byte
1: Cannot be stopped
0: Can be stopped
Internal oscillation
mode register
(RCM)
LSRSTOP
RSTS RSTOP
Internal high-
speed oscillator
(8 MHz (TYP.))
Internal low-
speed oscillator
(240 kHz (TYP.))
f
RL
Clock operation mode
select register
(OSCCTL)
OSCSELS
EXCLKS
XT1/P123
XT2/EXCLKS/
P124
f
SUB
Peripheral
hardware
clock (f
PRS
)
Watchdog timer,
8-bit timer H1
1/2
CPU clock
(f
CPU
)
Processor clock
control register
(PCC)
CSS PCC2CLS PCC1 PCC0
Prescaler
Main system
clock switch
f
XP
Peripheral
hardware
clock switch
X1 oscillation
stabilization time counter
OSTS1 OSTS0OSTS2
Oscillation stabilization
time select register (OSTS)
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
Oscillation
stabilization
time counter
status register
(OSTC)
Controller
MCM0
XSEL
MCS
MSTOP
EXCLK
OSCSEL
AMPH
Clock operation mode
select register
(OSCCTL)
4
f
XP
2
f
XP
2
2
f
XP
2
3
f
XP
2
4
Main clock
mode register
(MCM)
Main clock
mode register
(MCM)
Main OSC
control register
(MOC)
f
RH
Internal bus
Internal bus
High-speed system
clock oscillator
Crystal/ceramic
oscillation
External input
clock
X1/P121
X2/EXCLK/
P122
f
XH
f
SUB
2
Crystal
oscillation
External input
clock
Subsystem
clock oscillator
f
X
f
EXCLK
f
XT
f
EXCLKS
XTSTART
To subsystem
clock oscillator
XTSTART
Processor clock
control register
(PCC)
Selector
STOP
Watch timer,
LCD controller/driver
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
122
Remarks 1. fX: X1 clock oscillation frequency
2. fRH: Internal high-speed oscillation clock frequency
3. fEXCLK: External main system clock frequency
4. fXH: High-speed system clock oscillation frequency
5. fXP: Main system clock oscillation frequency
6. fPRS: Peripheral hardware clock oscillation frequency
7. fCPU: CPU clock oscillation frequency
8. fXT: XT1 clock oscillation frequency
9. fEXCLKS: External subsystem clock frequency
10. fSUB: Subsystem clock oscillation frequency
11. fRL: Internal low-speed oscillation clock frequency
6.3 Registers Controlling Clock Generator
The following seven registers are used to control the clock generator.
• Clock operation mode select register (OSCCTL)
• Processor clock control register (PCC)
• Internal oscillation mode register (RCM)
• Main OSC control register (MOC)
• Main clock mode register (MCM)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
(1) Clock operation mode select register (OSCCTL)
This register selects the operation modes of the high-speed system and subsystem clocks, and the gain of the
on-chip oscillator.
OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 123
Figure 6-2. Format of Clock Operation Mode Select Register (OSCCTL)
Address: FF9FH After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 <0>
OSCCTL EXCLK OSCSEL EXCLKSNote
OSCSELS
Note 0 0 0 AMPH
EXCLK OSCSEL High-speed system clock
pin operation mode
P121/X1 pin P122/X2/EXCLK pin
0 0 I/O port mode I/O port
0 1 X1 oscillation mode Crystal/ceramic resonator connection
1 0 I/O port mode I/O port
1 1 External clock input
mode
I/O port External clock input
AMPH Operating frequency control
0 1 MHz ≤ fXH ≤ 10 MHz
1 10 MHz < fXH ≤ 20 MHz
Note EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor
clock control register (PCC)). See (3) Setting of operation mode for subsystem clock
pin.
Cautions 1. Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
exceeds 10 MHz.
2. Set AMPH before setting the peripheral functions after a reset release. The value
of AMPH can be changed only once after a reset release. When the high-speed
system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU
clock is stopped for 4.06 to 16.12
μ
s after AMPH is set to 1. When the high-
speed system clock (external clock input) is selected as the CPU clock, supply of
the CPU clock is stopped for the duration of 160 external clocks after AMPH is
set to 1.
3. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
stopped for 4.06 to 16.12
μ
s after the STOP mode is released when the internal
high-speed oscillation clock is selected as the CPU clock, or for the duration of
160 external clocks when the high-speed system clock (external clock input) is
selected as the CPU clock. When the high-speed system clock (X1 oscillation) is
selected as the CPU clock, the oscillation stabilization time is counted after the
STOP mode is released.
4. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or
the external clock from the EXCLK pin is disabled).
Remark f
XH: High-speed system clock oscillation frequency
<R>
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
124
(2) Processor clock control register (PCC)
This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.
Figure 6-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 01H R/WNote 1
Symbol 7 6 <5> <4> 3 2 1 0
PCC 0
XTSTART
Note2 CLS CSS 0 PCC2 PCC1 PCC0
CLS CPU clock status
0 Main system clock
1 Subsystem clock
Notes 1. Bit 5 is read-only.
2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the Clock
operation mode select register (OSCCTL)). See (3) Setting of operation mode for
subsystem clock pin.
Caution Be sure to clear bits 3 and 7 to 0.
Remarks 1. fXP: Main system clock oscillation frequency
2. fSUB: Subsystem clock oscillation frequency
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/LG2. Therefore, the relationship
between the CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 6-2.
CSS PCC2 PCC1 PCC0 CPU clock (fCPU) selection
0 0 0 fXP
0 0 1 fXP/2 (default)
0 1 0 fXP/22
0 1 1 fXP/23
0
1 0 0 fXP/24
0 0 0
0 0 1
0 1 0
0 1 1
1
1 0 0
fSUB/2
Other than above Setting prohibited
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 125
Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
Minimum Instruction Execution Time: 2/fCPU
Main System Clock
High-Speed System ClockNote Internal High-Speed
Oscillation ClockNote
Subsystem Clock
CPU Clock (fCPU)
At 10 MHz
Operation
At 20 MHz
Operation
At 8 MHz (TYP.) Operation At 32.768 kHz Operation
fXP 0.2
μ
s 0.1
μ
s 0.25
μ
s (TYP.) −
fXP/2 0.4
μ
s 0.2
μ
s 0.5
μ
s (TYP.) −
fXP/22 0.8
μ
s 0.4
μ
s 1.0
μ
s (TYP.) −
fXP/23 1.6
μ
s 0.8
μ
s 2.0
μ
s (TYP.) −
fXP/24 3.2
μ
s 1.6
μ
s 4.0
μ
s (TYP.) −
fSUB/2 − − 122.1
μ
s
Note The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (high-
speed system clock/internal high-speed oscillation clock) (see Figure 6-6).
(3) Setting of operation mode for subsystem clock pin
The operation mode for the subsystem clock pin can be set by using bit 6 (XTSTART) of the processor clock
control register (PCC) and bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode select register
(OSCCTL) in combination.
Table 6-3. Setting of Operation Mode for Subsystem Clock Pin
PCC OSCCTL
Bit 6 Bit 5 Bit 4
XTSTART EXCLKS OSCSELS
Subsystem Clock Pin
Operation Mode
P123/XT1 Pin P124/XT2/EXCLKS
Pin
0 0 0 I/O port mode I/O port
0 0 1 XT1 oscillation mode Crystal resonator connection
0 1 0 I/O port mode I/O port
0 1 1 External clock input mode I/O port External clock input
1 × × XT1 oscillation mode Crystal resonator connection
Caution Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating
with main system clock) when changing the current values of XTSTART, EXCLKS, and
OSCSELS.
Remark ×: don’t care
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
126
(4) Internal oscillation mode register (RCM)
This register sets the operation mode of internal oscillator.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80HNote 1.
Figure 6-4. Format of Internal Oscillation Mode Register (RCM)
Address: FFA0H After reset: 80HNote 1 R/WNote 2
Symbol <7> 6 5 4 3 2 <1> <0>
RCM RSTS 0 0 0 0 0 LSRSTOP RSTOP
RSTS Status of internal high-speed oscillator
0 Waiting for accuracy stabilization of internal high-speed oscillator
1 Stability operating of internal high-speed oscillator
LSRSTOP Internal low-speed oscillator oscillating/stopped
0 Internal low-speed oscillator oscillating
1 Internal low-speed oscillator stopped
RSTOP Internal high-speed oscillator oscillating/stopped
0 Internal high-speed oscillator oscillating
1 Internal high-speed oscillator stopped
Notes 1. The value of this register is 00H immediately after a reset release but automatically
changes to 80H after internal high-speed oscillator has been stabilized.
2. Bit 7 is read-only.
Caution When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the internal high-speed oscillation clock. Specifically, set under either of
the following conditions.
• When MCS = 1 (when CPU operates with the high-speed system clock)
• When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the internal high-speed
oscillation clock before setting RSTOP to 1.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 127
(5) Main OSC control register (MOC)
This register selects the operation mode of the high-speed system clock.
This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the
CPU operates with a clock other than the high-speed system clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H.
Figure 6-5. Format of Main OSC Control Register (MOC)
Address: FFA2H After reset: 80H R/W
Symbol <7> 6 5 4 3 2 1 0
MOC MSTOP 0 0 0 0 0 0 0
Control of high-speed system clock operation
MSTOP
X1 oscillation mode External clock input mode
0 X1 oscillator operating External clock from EXCLK pin is enabled
1 X1 oscillator stopped External clock from EXCLK pin is disabled
Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the high-speed system clock. Specifically, set under either of the
following conditions.
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
clock)
• When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
register (OSCCTL) is 0 (I/O port mode).
3. The peripheral hardware cannot operate when the peripheral hardware clock is
stopped. To resume the operation of the peripheral hardware after the
peripheral hardware clock has been stopped, initialize the peripheral hardware.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
128
(6) Main clock mode register (MCM)
This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware
clock.
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 6-6. Format of Main Clock Mode Register (MCM)
Address: FFA1H After reset: 00H R/WNote
Symbol 7 6 5 4 3 <2> <1> <0>
MCM 0 0 0 0 0 XSEL MCS MCM0
Selection of clock supplied to main system clock and peripheral hardware
XSEL MCM0
Main system clock (fXP) Peripheral hardware clock (fPRS)
0 0
0 1
Internal high-speed oscillation clock
(fRH)
1 0
Internal high-speed oscillation clock
(fRH)
1 1 High-speed system clock (fXH)
High-speed system clock (fXH)
MCS Main system clock status
0 Operates with internal high-speed oscillation clock
1 Operates with high-speed system clock
Note Bit 1 is read-only.
Cautions 1. XSEL can be changed only once after a reset release.
2. A clock other than fPRS is supplied to the following peripheral functions
regardless of the setting of XSEL and MCM0.
• Watchdog timer (operates with internal low-speed oscillation clock)
• When “fRL”, “fRL/27”, or “fRL/29” is selected as the count clock for 8-bit timer H1
(operates with internal low-speed oscillation clock)
• Peripheral hardware selects the external clock as the clock source
(Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin
valid edge))
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 129
(7) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1
clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock,
the X1 clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of
MOC register) = 1 clear OSTC to 00H.
Figure 6-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16
MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status
fX = 10 MHz fX = 20 MHz
1 0 0 0 0 211/fX min. 204.8
μ
s min. 102.4
μ
s min.
1 1 0 0 0 213/fX min. 819.2
μ
s min. 409.6
μ
s min.
1 1 1 0 0 214/fX min. 1.64 ms min. 819.2
μ
s min.
1 1 1 1 0 215/fX min. 3.27 ms min. 1.64 ms min.
1 1 1 1 1 216/fX min. 6.55 ms min. 3.27 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
130
(8) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 05H.
Figure 6-8. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection
fX = 10 MHz fX = 20 MHz
0 0 1 211/fX 204.8
μ
s 102.4
μ
s
0 1 0 213/fX 819.2
μ
s 409.6
μ
s
0 1 1 214/fX 1.64 ms 819.2
μ
s
1 0 0 215/fX 3.27 ms 1.64 ms
1 0 1 216/fX 6.55 ms 3.27 ms
Other than above Setting prohibited
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
2. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
3. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
4. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 131
6.4 System Clock Oscillator
6.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2
pins.
An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
Figure 6-9 shows an example of the external circuit of the X1 oscillator.
Figure 6-9. Example of External Circuit of X1 Oscillator
(a) Crystal or ceramic oscillation <R> (b) External clock
VSS
X1
X2
Crystal resonator
or
ceramic resonator
EXCLK
External clock
Cautions are listed on the next page.
6.4.2 XT1 oscillator
The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins.
An external clock can also be input. In this case, input the clock signal to the EXCLKS pin.
Figure 6-10 shows an example of the external circuit of the XT1 oscillator.
Figure 6-10. Example of External Circuit of XT1 Oscillator
(a) Crystal oscillation <R> (b) External clock
XT2
V
SS
XT1
32.768
kHz
EXCLKS
External clock
Cautions are listed on the next page.
<R>
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
132
Cautions 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the
broken lines in the Figures 6-9 and 6-10 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do
not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power
consumption.
Figure 6-11 shows examples of incorrect resonator connection.
Figure 6-11. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring (b) Crossed signal line
X2V
SS
X1 X1V
SS
X2
PORT
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 133
Figure 6-11. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high alternating current (d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
SS
X1 X2
V
SS
X1 X2
AB C
Pmn
V
DD
High current
High current
(e) Signals are fetched
VSS X1 X2
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1,
resulting in malfunctioning.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
134
6.4.3 When subsystem clock is not used
If it is not necessary to use the subsystem clock for low power consumption operations, or if not using the
subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows.
Input (PM123/PM124 = 1): Independently connect to VDD or VSS via a resistor.
Output (PM123/PM124 = 0): Leave open.
Remark OSCSELS: Bit 4 of clock operation mode select register (OSCCTL)
PM123, PM124: Bits 3 and 4 of port mode register 12 (PM12)
6.4.4 Internal high-speed oscillator
The internal high-speed oscillator is incorporated in the 78K0/LG2. Oscillation can be controlled by the internal
oscillation mode register (RCM).
After a reset release, the internal high-speed oscillator automatically starts oscillation (8 MHz (TYP.)).
6.4.5 Internal low-speed oscillator
The internal low-speed oscillator is incorporated in the 78K0/LG2.
The internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The
internal low-speed oscillation clock cannot be used as the CPU clock.
“Can be stopped by software” or “Cannot be stopped” can be selected by the option byte. When “Can be stopped
by software” is set, oscillation can be controlled by the internal oscillation mode register (RCM).
After a reset release, the internal low-speed oscillator automatically starts oscillation, and the watchdog timer is
driven (240 kHz (TYP.)) if the watchdog timer operation is enabled using the option byte.
6.4.6 Prescaler
The prescaler generates various clocks by dividing the main system clock when the main system clock is selected
as the clock to be supplied to the CPU.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 135
6.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 6-1).
• Main system clock fXP
• High-speed system clock fXH
X1 clock fX
External main system clock fEXCLK
• Internal high-speed oscillation clock fRH
• Subsystem clock fSUB
• XT1 clock fXT
• External subsystem clock fEXCLKS
• Internal low-speed oscillation clock fRL
• CPU clock fCPU
• Peripheral hardware clock fPRS
The CPU starts operation when the internal high-speed oscillator starts outputting after a reset release in the
78K0/LG2, thus enabling the following.
(1) Enhancement of security function
When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is
damaged or badly connected and therefore does not operate after reset is released. However, the start clock of
the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed
oscillation clock after a reset release. Consequently, the system can be safely shut down by performing a
minimum operation, such as acknowledging a reset source by software or performing safety processing when
there is a malfunction.
(2) Improvement of performance
Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total
performance can be improved.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 6-12.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
136
Figure 6-12. Clock Generator Operation When Power Supply Voltage Is Turned On
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Internal high-speed
oscillation clock (f
RH
)
CPU clock
High-speed
system clock (f
XH
)
(when X1 oscillation
selected)
Internal high-speed oscillation clock
High-speed system clock
Switched by
software
Subsystem clock (f
SUB
)
(when XT1 oscillation
selected)
Subsystem clock
X1 clock
oscillation stabilization time:
2
11
/f
X
to 2
16
/f
XNote 2
Starting X1 oscillation
is set by software.
Starting XT1 oscillation
is set by software.
Reset processing
(11 to 45 s)
<3> Waiting for
voltage stabilization
Internal reset signal
0 V
1.59 V
(TYP.)
1.8 V
0.5 V/ms
(MIN.)
Power supply
voltage (VDD)
<1>
<2>
<4>
<5> <5>
<4>
Note 1
(1.93 to 5.39 ms)
μ
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 1.59 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
<3> When the power supply voltage rises with a slope of 0.5 V/ms (MIN.), the CPU starts operation on the
internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage
of the power supply and regulator have elapsed, and then reset processing is performed.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling high-
speed system clock and (1) in 6.6.3 Example of controlling subsystem clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3
Example of controlling subsystem clock).
Notes 1. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
2. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the
internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the
oscillation stabilization time counter status register (OSTC). If the CPU operates on the high-speed
system clock (X1 oscillation), set the oscillation stabilization time when releasing STOP mode using the
oscillation stabilization time select register (OSTS).
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 137
Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the
voltage reaches 1.8 V, input a low level to the RESET pin from power application until the
voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using the option byte (POCMODE
= 1) (see Figure 6-13). By doing so, the CPU operates with the same timing as <2> and
thereafter in Figure 6-12 after reset release by the RESET pin.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input
from the EXCLK and EXCLKS pins is used.
Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings. The internal high-speed oscillation clock and high-speed system clock can be
stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed
system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in
6.6.3 Example of controlling subsystem clock).
Figure 6-13. Clock Generator Operation When Power Supply Voltage Is Turned On
(When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1))
Internal high-speed
oscillation clock (fRH)
CPU clock
High-speed
system clock (fXH)
(when X1 oscillation
selected)
Internal high-speed
oscillation clock High-speed system clock
Switched by
software
Subsystem clock (fSUB)
(when XT1 oscillation
selected)
Subsystem clock
X1 clock
oscillation stabilization time:
2
11
/f
X
to 2
16
/f
XNote
Starting X1 oscillation
is set by software.
Starting XT1 oscillation
is set by software.
Waiting for oscillation accuracy
stabilization (86 to 361 s)
Internal reset signal
0 V
2.7 V (TYP.)
Power supply
voltage (V
DD
)
<1>
<3>
<2>
<4>
<5>
Reset processing
(11 to 45 s)
<4>
<5>
μ
μ
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 2.7 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
<3> After the reset is released and reset processing is performed, the CPU starts operation on the internal high-
speed oscillation clock.
<4> Set the start of oscillation of the X1 or XT1 clock via software (see (1) in 6.6.1 Example of controlling high-
speed system clock and (1) in 6.6.3 Example of controlling subsystem clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (see (3) in 6.6.1 Example of controlling high-speed system clock and (3) in 6.6.3
Example of controlling subsystem clock).
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
138
Note When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal
high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1
oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation
stabilization time select register (OSTS).
Cautions 1. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
2. It is not necessary to wait for the oscillation stabilization time when an external clock input
from the EXCLK and EXCLKS pins is used.
Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via
software settings. The internal high-speed oscillation clock and high-speed system clock can be
stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed
system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in
6.6.3 Example of controlling subsystem clock).
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 139
6.6 Controlling Clock
6.6.1 Example of controlling high-speed system clock
The following two types of high-speed system clocks are available.
• X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins.
• External main system clock: External clock is input to the EXCLK pin.
When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port
pins.
Caution The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating X1 clock
(2) When using external main system clock
(3) When using high-speed system clock as CPU clock and peripheral hardware clock
(4) When stopping high-speed system clock
(1) Example of setting procedure when oscillating the X1 clock
<1> Setting frequency (OSCCTL register)
Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used.
AMPHNote Operating Frequency Control
0 1 MHz ≤ fXH ≤ 10 MHz
1 10 MHz < fXH ≤ 20 MHz
Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can
be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU
is stopped for 4.06 to 16.12
μ
s.
Remark f
XH: High-speed system clock oscillation frequency
<2> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register)
When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1
oscillation mode.
EXCLK OSCSEL Operation Mode of High-
Speed System Clock Pin
P121/X1 Pin P122/X2/EXCLK Pin
0 1 X1 oscillation mode Crystal/ceramic resonator connection
<3> Controlling oscillation of X1 clock (MOC register)
If MSTOP is cleared to 0, the X1 oscillator starts oscillating.
<4> Waiting for the stabilization of the oscillation of X1 clock
Check the OSTC register and wait for the necessary time.
During the wait time, other software processing can be executed with the internal high-speed oscillation
clock.
Cautions 1. Do not change the value of EXCLK and OSCSEL while the X1 clock is operating.
2. Set the X1 clock after the supply voltage has reached the operable voltage of the clock to
be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS).
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
140
(2) Example of setting procedure when using the external main system clock
<1> Setting frequency (OSCCTL register)
Using AMPH, set the frequency to be used.
AMPHNote Operating Frequency Control
0 1 MHz ≤ fXH ≤ 10 MHz
1 10 MHz < fXH ≤ 20 MHz
Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can
be changed only once after a reset release. The clock supply to the CPU is stopped for the
duration of 160 external clocks after AMPH is set to 1.
Remark f
XH: High-speed system clock oscillation frequency
<2> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register)
When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input
mode.
EXCLK OSCSEL Operation Mode of High-
Speed System Clock Pin
P121/X1 Pin P122/X2/EXCLK Pin
1 1 External clock input mode I/O port External clock input
<3> Controlling external main system clock input (MOC register)
When MSTOP is cleared to 0, the input of the external main system clock is enabled.
Cautions 1. Do not change the value of EXCLK and OSCSEL while the external main system clock is
operating.
2. Set the external main system clock after the supply voltage has reached the operable
voltage of the clock to be used (see CHAPTER 30 ELECTRICAL SPECIFICATIONS).
(3) Example of setting procedure when using high-speed system clock as CPU clock and peripheral
hardware clock
<1> Setting high-speed system clock oscillationNote
(See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of <1> is not necessary when high-speed system clock is already operating.
<2> Setting the high-speed system clock as the main system clock (MCM register)
When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock
and peripheral hardware clock.
Selection of Main System Clock and Clock Supplied to Peripheral Hardware XSEL MCM0
Main System Clock (fXP) Peripheral Hardware Clock (fPRS)
1 1 High-speed system clock (fXH) High-speed system clock (fXH)
Caution If the high-speed system clock is selected as the main system clock, a clock other than
the high-speed system clock cannot be set as the peripheral hardware clock.
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 141
<3> Setting the main system clock as the CPU clock and selecting the division ratio (PCC register)
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock
division ratio, use PCC0, PCC1, and PCC2.
CSS PCC2 PCC1 PCC0 CPU Clock (fCPU) Selection
0 0 0 fXP
0 0 1 fXP/2 (default)
0 1 0 fXP/22
0 1 1 fXP/23
1 0 0 fXP/24
0
Other than above Setting prohibited
(4) Example of setting procedure when stopping the high-speed system clock
The high-speed system clock can be stopped in the following two ways.
• Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is
used)
• Setting MSTOP to 1 and stopping the X1 oscillation (disabling clock input if the external clock is used)
(a) To execute a STOP instruction
<1> Setting to stop peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 22 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after standby release
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and X1 oscillation
is stopped (the input of the external clock is disabled).
(b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1
<1> Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the
CPU clock to the subsystem clock or internal high-speed oscillation clock.
CLS MCS CPU Clock Status
0 0 Internal high-speed oscillation clock
0 1 High-speed system clock
1 × Subsystem clock
<2> Stopping the high-speed system clock (MOC register)
When MSTOP is set to 1, X1 oscillation is stopped (the input of the external clock is disabled).
Caution Be sure to confirm that MCS = 0 or CLS = 1 when setting MSTOP to 1. In addition, stop
peripheral hardware that is operating on the high-speed system clock.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
142
6.6.2 Example of controlling internal high-speed oscillation clock
The following describes examples of clock setting procedures for the following cases.
(1) When restarting oscillation of the internal high-speed oscillation clock
(2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-
speed system clock as peripheral hardware clock
(3) When stopping the internal high-speed oscillation clock
(1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote 1
<1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register)
When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating.
<2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM
register)
Wait until RSTS is set to 1Note 2.
Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the
internal high-speed oscillation clock is selected as the CPU clock.
2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral
hardware clock.
(2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and
internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock
<1> • Restarting oscillation of the internal high-speed oscillation clockNote
(See 6.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation
clock).
• Oscillating the high-speed system clockNote
(This setting is required when using the high-speed system clock as the peripheral hardware clock.
See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of
setting procedure when using the external main system clock.)
Note The setting of <1> is not necessary when the internal high-speed oscillation clock or high-
speed system clock is already operating.
<2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register)
Set the main system clock and peripheral hardware clock using XSEL and MCM0.
Selection of Main System Clock and Clock Supplied to Peripheral Hardware XSEL MCM0
Main System Clock (fXP) Peripheral Hardware Clock (fPRS)
0 0
0 1
Internal high-speed oscillation clock
(fRH)
1 0
Internal high-speed oscillation clock
(fRH)
High-speed system clock (fXH)
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 143
<3> Selecting the CPU clock division ratio (PCC register)
When CSS is cleared to 0, the main system clock is supplied to the CPU. To select the CPU clock
division ratio, use PCC0, PCC1, and PCC2.
CSS PCC2 PCC1 PCC0 CPU Clock (fCPU) Selection
0 0 0 fXP
0 0 1 fXP/2 (default)
0 1 0 fXP/22
0 1 1 fXP/23
1 0 0 fXP/24
0
Other than above Setting prohibited
(3) Example of setting procedure when stopping the internal high-speed oscillation clock
The internal high-speed oscillation clock can be stopped in the following two ways.
• Executing the STOP instruction to set the STOP mode
• Setting RSTOP to 1 and stopping the internal high-speed oscillation clock
(a) To execute a STOP instruction
<1> Setting of peripheral hardware
Stop peripheral hardware that cannot be used in the STOP mode (for peripheral hardware that
cannot be used in STOP mode, see CHAPTER 22 STANDBY FUNCTION).
<2> Setting the X1 clock oscillation stabilization time after standby release
When the CPU is operating on the X1 clock, set the value of the OSTS register before the STOP
instruction is executed.
<3> Executing the STOP instruction
When the STOP instruction is executed, the system is placed in the STOP mode and internal high-
speed oscillation clock is stopped.
(b) To stop internal high-speed oscillation clock by setting RSTOP to 1
<1> Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed
oscillation clock.
When CLS = 0 and MCS = 0, the internal high-speed oscillation clock is supplied to the CPU, so
change the CPU clock to the high-speed system clock or subsystem clock.
CLS MCS CPU Clock Status
0 0 Internal high-speed oscillation clock
0 1 High-speed system clock
1 × Subsystem clock
<2> Stopping the internal high-speed oscillation clock (RCM register)
When RSTOP is set to 1, internal high-speed oscillation clock is stopped.
Caution Be sure to confirm that MCS = 1 or CLS = 1 when setting RSTOP to 1. In addition, stop
peripheral hardware that is operating on the internal high-speed oscillation clock.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
144
6.6.3 Example of controlling subsystem clock
The following two types of subsystem clocks are available.
• XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins.
• External subsystem clock: External clock is input to the EXCLKS pin.
When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins.
Caution The XT1/P123 and XT2/EXCLKS/P124 pins are in the I/O port mode after a reset release.
The following describes examples of setting procedures for the following cases.
(1) When oscillating XT1 clock
(2) When using external subsystem clock
(3) When using subsystem clock as CPU clock
(4) When stopping subsystem clock
(1) Example of setting procedure when oscillating the XT1 clock
<1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers)
When XTSTART, EXCLKS, and OSCSELS are set as any of the following, the mode is switched from
port mode to XT1 oscillation mode.
XTSTART EXCLKS OSCSELS Operation Mode of
Subsystem Clock Pin
P123/XT1 Pin P124/XT2/
EXCLKS Pin
0 0 1
1 × ×
XT1 oscillation mode Crystal/ceramic resonator connection
Remark ×: don’t care
<2> Waiting for the stabilization of the subsystem clock oscillation
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
operating.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 145
(2) Example of setting procedure when using the external subsystem clock
<1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and
OSCCTL registers)
When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from
port mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124
pins.
XTSTART EXCLKS OSCSELS Operation Mode of
Subsystem Clock Pin
P123/XT1 Pin P124/XT2/
EXCLKS Pin
0 1 1 External clock input
mode
I/O port External clock input
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
operating.
(3) Example of setting procedure when using the subsystem clock as the CPU clock
<1> Setting subsystem clock oscillationNote
(See 6.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of
setting procedure when using the external subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
<2> Switching the CPU clock (PCC register)
When CSS is set to 1, the subsystem clock is supplied to the CPU.
CSS PCC2 PCC1 PCC0 CPU Clock (fCPU) Selection
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
fSUB/2 1
Other than above Setting prohibited
(4) Example of setting procedure when stopping the subsystem clock
<1> Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to the internal
high-speed oscillation clock or high-speed system clock.
CLS MCS CPU Clock Status
0 0 Internal high-speed oscillation clock
0 1 High-speed system clock
1 × Subsystem clock
<2> Stopping the subsystem clock (OSCCTL register)
When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled).
Caution1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch
timer if it is operating on the subsystem clock.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
146
6.6.4 Example of controlling internal low-speed oscillation clock
The internal low-speed oscillation clock cannot be used as the CPU clock.
Only the following peripheral hardware can operate with this clock.
• Watchdog timer
• 8-bit timer H1 (if fRL is selected as the count clock)
In addition, the following operation modes can be selected by the option byte.
• Internal low-speed oscillator cannot be stopped
• Internal low-speed oscillator can be stopped by software
The internal low-speed oscillator automatically starts oscillation after a reset release, and the watchdog timer is
driven (240 kHz (TYP.)) if the watchdog timer operation has been enabled by the option byte.
(1) Example of setting procedure when stopping the internal low-speed oscillation clock
<1> Setting LSRSTOP to 1 (RCM register)
When LSRSTOP is set to 1, the internal low-speed oscillation clock is stopped.
(2) Example of setting procedure when restarting oscillation of the internal low-speed oscillation clock
<1> Clearing LSRSTOP to 0 (RCM register)
When LSRSTOP is cleared to 0, the internal low-speed oscillation clock is restarted.
Caution If “Internal low-speed oscillator cannot be stopped” is selected by the option byte, oscillation of
the internal low-speed oscillation clock cannot be controlled.
6.6.5 Clocks supplied to CPU and peripheral hardware
The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting
of registers.
Table 6-4. Clocks Supplied to CPU and Peripheral Hardware, and Register Setting
Supplied Clock
Clock Supplied to CPU Clock Supplied to Peripheral Hardware
XSEL CSS MCM0 EXCLK
Internal high-speed oscillation clock 0 0 × ×
X1 clock 1 0 0 0 Internal high-speed oscillation clock
External main system clock 1 0 0 1
X1 clock 1 0 1 0
External main system clock 1 0 1 1
Internal high-speed oscillation clock 0 1 × ×
1 1 0 0 X1 clock
1 1 1 0
1 1 0 1
Subsystem clock
External main system clock
1 1 1 1
Remarks 1. XSEL: Bit 2 of the main clock mode register (MCM)
2. CSS: Bit 4 of the processor clock control register (PCC)
3. MCM0: Bit 0 of MCM
4. EXCLK: Bit 7 of the clock operation mode select register (OSCCTL)
5. ×: don’t care
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 147
6.6.6 CPU clock status transition diagram
Figure 6-14 shows the CPU clock status transition diagram of this product.
Figure 6-14. CPU Clock Status Transition Diagram
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Power ON
Reset release V
DD
1.59 V (TYP.)
V
DD
1.8 V (MIN.)
V
DD
< 1.59 V (TYP.)
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation/EXCLKS input: Stops (I/O port mode)
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation/EXCLKS input: Stops (I/O port mode)
CPU: Operating
with internal high-
speed oscillation
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input:
Selectable by CPU
CPU: Internal high-
speed oscillation
→ STOP
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Stops
CPU: Internal high-
speed oscillation
→ HALT
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operable
CPU: Operating
with X1 oscillation or
EXCLK input
CPU: X1
oscillation/EXCLK
input → STOP
CPU: X1
oscillation/EXCLK
input → HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation: Stops
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input: Operable
CPU: Operating
with XT1 oscillation or
EXCLKS input
CPU: XT1
oscillation/EXCLKS
input → HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input: Operating
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operating
(B)
(A)
(C)
(D)
(E)
(F)
(G)
(H)
(I)
Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 45
μ
s).
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
148
Table 6-5 shows transition of the CPU clock and examples of setting the SFR registers.
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (1/4)
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
Status Transition SFR Register Setting
(A) → (B) SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
AMPH EXCLK OSCSEL MSTOP OSTC
Register
XSEL MCM0
(A) → (B) → (C) (X1 clock: 1 MHz ≤ fXH ≤
10 MHz)
0 0 1 0
Must be
checked
1 1
(A) → (B) → (C) (external main clock: 1 MHz ≤
fXH ≤ 10 MHz)
0 1 1 0
Must not be
checked
1 1
(A) → (B) → (C) (X1 clock: 10 MHz < fXH ≤
20 MHz)
1 0 1 0
Must be
checked
1 1
(A) → (B) → (C) (external main clock: 10 MHz <
fXH ≤ 20 MHz)
1 1 1 0
Must not be
checked
1 1
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
XTSTART EXCLKS OSCSELS
Waiting for
Oscillation
Stabilization
CSS
0 0 1 (A) → (B) → (D) (XT1 clock)
1 × ×
Necessary 1
(A) → (B) → (D) (external subsystem clock) 0 1 1 Unnecessary 1
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
MSTOP: Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×: Don’t care
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 149
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (2/4)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
AMPHNote EXCLK OSCSEL MSTOP OSTC
Register
XSELNote MCM0
(B) → (C) (X1 clock: 1 MHz ≤ fXH ≤ 10 MHz) 0 0 1 0 Must be
checked
1 1
(B) → (C) (external main clock: 1 MHz ≤ fXH ≤
10 MHz)
0 1 1 0
Must not be
checked
1 1
(B) → (C) (X1 clock: 10 MHz < fXH ≤ 20 MHz) 1 0 1 0 Must be
checked
1 1
(B) → (C) (external main clock: 10 MHz < fXH ≤
20 MHz)
1 1 1 0
Must not be
checked
1 1
Unnecessary if these registers
are already set
Unnecessary if the
CPU is operating
with the high-speed
system clock
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS).
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
XTSTART EXCLKS OSCSELS
Waiting for
Oscillation
Stabilization
CSS
0 0 1 (B) → (D) (XT1 clock)
1 × ×
Necessary 1
(B) → (D) (external subsystem clock) 0 1 1 Unnecessary 1
Unnecessary if the CPU is operating
with the subsystem clock
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
MSTOP: Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×: Don’t care
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
150
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (3/4)
(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
RSTOP RSTS MCM0
(C) → (B) 0 Confirm this flag is 1. 0
Unnecessary if the CPU is operating
with the internal high-speed oscillation clock
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
XTSTART EXCLKS OSCSELS
Waiting for
Oscillation
Stabilization
CSS
0 0 1 (C) → (D) (XT1 clock)
1 × ×
Necessary 1
(C) → (D) (external subsystem clock) 0 1 1 Unnecessary 1
Unnecessary if the CPU is operating
with the subsystem clock
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
RSTOP RSTS MCM0 CSS
(D) → (B) 0 Confirm this flag
is 1.
0 0
Unnecessary if the CPU is operating
with the internal high-speed
oscillation clock
↑
Unnecessary if
XSEL is 0
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. MCM0: Bit 0 of the main clock mode register (MCM)
EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL)
RSTS, RSTOP: Bits 7 and 0 of the internal oscillation mode register (RCM)
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×: Don’t care
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 151
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (4/4)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
AMPHNote EXCLK OSCSEL MSTOP OSTC
Register
XSELNote MCM0 CSS
(D) → (C) (X1 clock: 1 MHz ≤ fXH ≤
10 MHz)
0 0 1 0
Must be
checked
1 1 0
(D) → (C) (external main clock: 1 MHz ≤
fXH ≤ 10 MHz
0 1 1 0
Must not be
checked
1 1 0
(D) → (C) (X1 clock: 10 MHz < fXH ≤
20 MHz)
1 0 1 0
Must be
checked
1 1 0
(D) → (C) (external main clock: 10 MHz <
fXH ≤ 20 MHz)
1 1 1 0
Must not be
checked
1 1 0
Unnecessary if these registers
are already set
Unnecessary if the
CPU is operating
with the high-speed
system clock
Unnecessary if this register
is already set
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS).
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
Status Transition Setting
(B) → (E)
(C) → (F)
(D) → (G)
Executing HALT instruction
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition Setting
(B) → (H)
(C) → (I)
Stopping peripheral functions that
cannot operate in STOP mode
Executing STOP instruction
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
MSTOP: Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
CSS: Bit 4 of the processor clock control register (PCC)
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
152
6.6.7 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 6-6. Changing CPU Clock
CPU Clock
Before Change After Change
Condition Before Change Processing After Change
X1 clock Stabilization of X1 oscillation
• MSTOP = 0, OSCSEL = 1, EXCLK = 0
• After elapse of oscillation stabilization time
• Internal high-speed oscillator can be
stopped (RSTOP = 1).
• Clock supply to CPU is stopped for 4.06
to 16.12
μ
s after AMPH has been set to 1.
Internal high-
speed oscillation
clock
External main
system clock
Enabling input of external clock from EXCLK
pin
• MSTOP = 0, OSCSEL = 1, EXCLK = 1
• Internal high-speed oscillator can be
stopped (RSTOP = 1).
• Clock supply to CPU is stopped for the
duration of 160 external clocks from the
EXCLK pin after AMPH has been set to 1.
X1 clock X1 oscillation can be stopped (MSTOP = 1).
External main
system clock
Internal high-
speed oscillation
clock
Oscillation of internal high-speed oscillator
• RSTOP = 0 External main system clock input can be
disabled (MSTOP = 1).
Internal high-
speed oscillation
clock
Operating current can be reduced by
stopping internal high-speed oscillator
(RSTOP = 1).
X1 clock X1 oscillation can be stopped (MSTOP = 1).
External main
system clock
XT1 clock Stabilization of XT1 oscillation
• XTSTART = 0, EXCLKS = 0,
OSCSELS = 1, or XTSTART = 1
• After elapse of oscillation stabilization time
External main system clock input can be
disabled (MSTOP = 1).
Internal high-
speed oscillation
clock
Operating current can be reduced by
stopping internal high-speed oscillator
(RSTOP = 1).
X1 clock X1 oscillation can be stopped (MSTOP = 1).
External main
system clock
External
subsystem clock
Enabling input of external clock from
EXCLKS pin
• XTSTART = 0, EXCLKS = 1,
OSCSELS = 1
External main system clock input can be
disabled (MSTOP = 1).
Internal high-
speed oscillation
clock
Oscillation of internal high-speed oscillator
and selection of internal high-speed
oscillation clock as main system clock
• RSTOP = 0, MCS = 0
XT1 oscillation can be stopped or external
subsystem clock input can be disabled
(OSCSELS = 0).
X1 clock Stabilization of X1 oscillation and selection
of high-speed system clock as main system
clock
• MSTOP = 0, OSCSEL = 1, EXCLK = 0
• After elapse of oscillation stabilization time
• MCS = 1
• XT1 oscillation can be stopped or external
subsystem clock input can be disabled
(OSCSELS = 0).
• Clock supply to CPU is stopped for 4.06
to 16.12
μ
s after AMPH has been set to 1.
XT1 clock,
external
subsystem clock
External main
system clock
Enabling input of external clock from EXCLK
pin and selection of high-speed system
clock as main system clock
• MSTOP = 0, OSCSEL = 1, EXCLK = 1
• MCS = 1
• XT1 oscillation can be stopped or external
subsystem clock input can be disabled
(OSCSELS = 0).
• Clock supply to CPU is stopped for the
duration of 160 external clocks from the
EXCLK pin after AMPH has been set to 1.
<R>
<R>
<R>
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 153
6.6.8 Time required for switchover of CPU clock and main system clock
By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock
can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system
clock can be changed.
The actual switchover operation is not performed immediately after rewriting to PCC; operation continues on the
pre-switchover clock for several clocks (see Table 6-7).
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 5
(CLS) of the PCC register.
Table 6-7. Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor
Set Value Before
Switchover
Set Value After Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0CSS PCC2 PCC1 PCC0
0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 × × ×
0 0 0 16 clocks 16 clocks 16 clocks 16 clocks 2fXP/fSUB clocks
0 0 1 8 clocks 8 clocks 8 clocks 8 clocks fXP/fSUB clocks
0 1 0 4 clocks 4 clocks 4 clocks 4 clocks fXP/2fSUB clocks
0 1 1 2 clocks 2 clocks 2 clocks 2 clocks fXP/4fSUB clocks
0
1 0 0 1 clock 1 clock 1 clock 1 clock fXP/8fSUB clocks
1 × × × 2 clocks 2 clocks 2 clocks 2 clocks 2 clocks
Caution Selection of the main system clock cycle division factor (PCC0 to PCC2) and switchover from the
main system clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the main system clock cycle division
factor (PCC0 to PCC2) and switchover from the subsystem clock to the main system clock
(changing CSS from 1 to 0).
Remarks 1. The number of clocks listed in Table 6-7 is the number of CPU clocks before switchover.
2. When switching the CPU clock from the main system clock to the subsystem clock, calculate the
number of clocks by rounding up to the next clock and discarding the decimal portion, as shown
below.
Example When switching CPU clock from fXP/2 to fSUB/2 (@ oscillation with fSUB = 32.768 kHz, fXP =
10 MHz)
fXP/fSUB = 10000/32.768 ≅ 305.1 → 306 clocks
By setting bit 0 (MCM0) of the main clock mode register (MCM), the main system clock can be switched (between
the internal high-speed oscillation clock and the high-speed system clock).
The actual switchover operation is not performed immediately after rewriting to MCM0; operation continues on the
pre-switchover clock for several clocks (see Table 6-8).
Whether the CPU is operating on the internal high-speed oscillation clock or the high-speed system clock can be
ascertained using bit 1 (MCS) of MCM.
<R>
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD
154
Table 6-8. Maximum Time Required for Main System Clock Switchover
Set Value Before Switchover Set Value After Switchover
MCM0 MCM0
0 1
0 1 + 2fRH/fXH clock
1 1 + 2fXH/fRH clock
Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2
(XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a
reset release.
Remarks 1. The number of clocks listed in Table 6-8 is the number of main system clocks before switchover.
2. Calculate the number of clocks in Table 6-8 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fRH = 8 MHz, fXH = 10 MHz)
1 + 2fRH/fXH = 1 + 2 × 8/10 = 1 + 2 × 0.8 = 1 + 1.6 = 2.6 → 2 clocks
6.6.9 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 6-9. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR
Register
Internal high-speed
oscillation clock
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock)
RSTOP = 1
X1 clock
External main system clock
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
MSTOP = 1
XT1 clock
External subsystem clock
CLS = 0
(The CPU is operating on a clock other than the subsystem clock)
OSCSELS = 0
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17473EJ2V0UD 155
6.6.10 Peripheral hardware and source clocks
The following lists peripheral hardware and source clocks incorporated in the 78K0/LG2.
Table 6-10. Peripheral Hardware and Source Clocks
Source Clock
Peripheral Hardware
Peripheral
Hardware Clock
(fPRS)
Subsystem Clock
(fSUB)
Internal Low-
Speed Oscillation
Clock (fRL)
TM50 Output External Clock
from Peripheral
Hardware Pins
00 Y N N N Y (TI000 pin)Note 16-bit timer/
event counter 01 Y N N N Y (TI001 pin)Note
50 Y N N N Y (TI50 pin)Note 8-bit timer/
event counter 51 Y N N N Y (TI51 pin)Note
H0 Y N N Y N 8-Bit timer
H1 Y N Y N N
Watch timer Y Y N N N
Watchdog timer N N Y N N
Clock output Y Y N N N
A/D converter Y N N N N
UART0 Y N N Y N
UART6 Y N N Y N
CSI10 Y N N N Y (SCK10 pin)Note
CSI11 Y N N N Y (SCK11 pin)Note
Serial interface
IIC0 Y N N N Y (SCL0 pin)Note
LCD controller/driver Y Y N N N
Note When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
Remark Y: Can be selected, N: Cannot be selected
User’s Manual U17473EJ2V0UD
156
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
The
μ
PD78F0393 incorporates 16-bit timer/event counter 00, and the
μ
PD78F0394, 78F0395, 78F0396, 78F0397,
and 78F0397D incorporate 16-bit timer/event counters 00 and 01.
7.1 Functions of 16-Bit Timer/Event Counters 00 and 01
16-bit timer/event counters 00 and 01Note have the following functions.
(1) Interval timer
16-bit timer/event counters 00 and 01 generate an interrupt request at the preset time interval.
(2) Square-wave output
16-bit timer/event counters 00 and 01 can output a square wave with any selected frequency.
(3) External event counter
16-bit timer/event counters 00 and 01 can measure the number of pulses of an externally input signal.
(4) One-shot pulse output
16-bit timer event counters 00 and 01 can output a one-shot pulse whose output pulse width can be set freely.
(5) PPG output
16-bit timer/event counters 00 and 01 can output a rectangular wave whose frequency and output pulse width can
be set freely.
(6) Pulse width measurement
16-bit timer/event counters 00 and 01 can measure the pulse width of an externally input signal.
Note Available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D.
<R>
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 157
7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01
16-bit timer/event counters 00 and 01 include the following hardware.
Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01
Item Configuration
Time/counter 16-bit timer counter 0n (TM0n)
Register 16-bit timer capture/compare registers 00n, 01n (CR00n, CR01n)
Timer input TI00n, TI01n pins
Timer output TO0n pin, output controller
Control registers 16-bit timer mode control register 0n (TMC0n)
16-bit timer capture/compare control register 0n (CRC0n)
16-bit timer output control register 0n (TOC0n)
Prescaler mode register 0n (PRM0n)
Port mode register 0 (PM0)
Port register 0 (P0)
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Figures 7-1 and 7-2 show the block diagrams.
Figure 7-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
TI010/TO00/P01
f
PRS
f
PRS
/2
2
f
PRS
/2
8
f
PRS
TI000/P00
Prescaler mode
register 00 (PRM00)
2
PRM001 PRM000
CRC002
16-bit timer capture/compare
register 010 (CR010)
Match
Match
16-bit timer counter 00
(TM00) Clear
Noise
elimi-
nator
CRC002 CRC001 CRC000
INTTM000
TO00/TI010/
P01
INTTM010
16-bit timer output
control register 00
(TOC00)
16-bit timer mode
control register 00
(TMC00)
Internal bus
TMC003 TMC002
TMC001
OVF00
TOC004
LVS00 LVR00
TOC001
TOE00
Selector
16-bit timer capture/compare
register 000 (CR000)
Selector
Selector
Selector
Noise
elimi-
nator
Noise
elimi-
nator
Output
controller
OSPE00
OSPT00
Output latch
(P01)
PM01
To CR010
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
158
Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01
(Available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D)
Internal bus
Capture/compare control
register 01 (CRC01)
TI011/TO01/P06
f
PRS
f
PRS
/2
4
f
PRS
/2
6
f
PRS
TI001/P05/
SSI11
Prescaler mode
register 01 (PRM01)
2
PRM011 PRM010
CRC012
16-bit timer capture/compare
register 011 (CR011)
Match
Match
16-bit timer counter 01
(TM01) Clear
Noise
elimi-
nator
CRC012 CRC011 CRC010
INTTM001
TO01/TI011/
P06
INTTM011
16-bit timer output
control register 01
(TOC01)
16-bit timer mode
control register 01
(TMC01)
Internal bus
TMC013 TMC012
TMC011
OVF01
TOC014
LVS01 LVR01
TOC011
TOE01
Selector
16-bit timer capture/compare
register 001 (CR001)
Selector
Selector
Selector
Noise
elimi-
nator
Noise
elimi-
nator
Output
controller
OSPE01
OSPT01
Output latch
(P06)
PM06
To CR011
Cautions 1. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same
time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at
the same time. Select either of the functions.
2. If clearing of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n
(TMC0n) to 00 and input of the capture trigger conflict, then the captured data is undefined.
3. To change the mode from the capture mode to the comparison mode, first clear the TMC0n3
and TMC0n2 bits to 00, and then change the setting.
A value that has been once captured remains stored in CR00n unless the device is reset. If
the mode has been changed to the comparison mode, be sure to set a comparison value.
(1) 16-bit timer counter 0n (TM0n)
TM0n is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the count clock.
If the count value is read during operation, then input of the count clock is temporarily stopped, and the count
value at that point is read.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 159
Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n)
TM0n
(n = 0, 1)
FF11H (TM00), FFB1H (TM01) FF10H (TM00), FFB0H (TM01)
Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) After reset: 0000H R
1514131211109876543210
The count value of TM0n can be read by reading TM0n when the value of bits 3 and 2 (TMC0n3 and TMC0n2) of
16-bit timer mode control register 0n (TMC0n) is other than 00. The value of TM0n is 0000H if it is read when
TMC0n3 and TMC0n2 = 00.
The count value is reset to 0000H in the following cases.
• At reset signal generation
• If TMC0n3 and TMC0n2 are cleared to 00
• If the valid edge of the TI00n pin is input in the mode in which the clear & start occurs when inputting the valid
edge to the TI00n pin
• If TM0n and CR00n match in the mode in which the clear & start occurs when TM0n and CR00n match
• OSPT0n is set to 1 in one-shot pulse output mode or the valid edge is input to the TI00n pin
Caution Even if TM0n is read, the value is not captured by CR01n.
(2) 16-bit timer capture/compare register 00n (CR00n)), 16-bit timer capture/compare register 01n (CR01n)
CR00n and CR01n are 16-bit registers that are used with a capture function or comparison function selected by
using CRC0n.
Change the value of CR00n while the timer is stopped (TMC0n3 and TMC0n2 = 00).
The value of CR01n can be changed during operation if the value has been set in a specific way. For details, see
7.5.1 Rewriting CR01n during TM0n operation.
These registers can be read or written in 16-bit units.
Reset signal generation sets these registers to 0000H.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
160
Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n)
CR00n
(n = 0, 1)
FF13H (CR000), FFB3H (CR001) FF12H (CR000), FFB2H (CR001)
Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001) After reset: 0000H R/W
1514131211109876543210
(i) When CR00n is used as a compare register
The value set in CR00n is constantly compared with the TM0n count value, and an interrupt request signal
(INTTM00n) is generated if they match. The value is held until CR00n is rewritten.
Caution CR00n does not perform the capture operation when it is set in the comparison mode, even
if a capture trigger is input to it.
(ii) When CR00n is used as a capture register
The count value of TM0n is captured to CR00n when a capture trigger is input.
As the capture trigger, an edge of a phase reverse to that of the TI00n pin or the valid edge of the TI01n pin
can be selected by using CRC0n or PRM0n.
Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)
CR01n
(n = 0, 1)
FF15H (CR010), FFB5H (CR011) FF14H (CR010), FFB4H (CR011)
Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011) After reset: 0000H R/W
1514131211109876543210
(i) When CR01n is used as a compare register
The value set in CR01n is constantly compared with the TM0n count value, and an interrupt request signal
(INTTM01n) is generated if they match.
Caution CR01n does not perform the capture operation when it is set in the comparison mode, even
if a capture trigger is input to it.
(ii) When CR01n is used as a capture register
The count value of TM0n is captured to CR01n when a capture trigger is input.
It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set
by PRM0n.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 161
(iii) Setting range when CR00n or CR01n is used as a compare register
When CR00n or CR01n is used as a compare register, set it as shown below.
Operation CR00n Register Setting Range CR01n Register Setting Range
Operation as interval timer
Operation as square-wave output
Operation as external event counter
0000H < N ≤ FFFFH 0000HNote ≤ M ≤ FFFFH
Normally, this setting is not used. Mask the
match interrupt signal (INTTM01n).
Operation in the clear & start mode
entered by TI00n pin valid edge input
Operation as free-running timer
0000HNote ≤ N ≤ FFFFH 0000HNote ≤ M ≤ FFFFH
Operation as PPG output M < N ≤ FFFFH 0000HNote ≤ M < N
Operation as one-shot pulse output 0000HNote ≤ N ≤ FFFFH (N ≠ M) 0000HNote ≤ M ≤ FFFFH (M ≠ N)
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output
is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the
timer counter (TM0n register) is changed from 0000H to 0001H.
• When the timer counter is cleared due to overflow
• When the timer counter is cleared due to TI00n pin valid edge (when clear & start mode is entered by
TI00n pin valid edge input)
• When the timer counter is cleared due to compare match (when clear & start mode is entered by match
between TM0n and CR00n (CR00n = other than 0000H, CR01n = 0000H))
Operation enabled
(other than 00)
TM0n register
Timer counter clear
Interrupt signal
is not generated Interrupt signal
is generated
Timer operation enable bit
(TMC0n3, TMC0n2)
Interrupt request signal
Compare register set value
(0000H)
Operation
disabled (00)
Remarks 1. N: CR00n register set value, M: CR01n register set value
2. For details of TMC0n3 and TMC0n2, see 7.3 (1) 16-bit timer mode control register 0n (TMC0n).
3. n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
162
Table 7-2. Capture Operation of CR00n and CR01n
External Input
Signal
Capture
Operation
TI00n Pin Input
TI01n Pin Input
Set values of ES0n1 and
ES0n0
Position of edge to be
captured
Set values of ES1n1 and
ES1n0
Position of edge to be
captured
01: Rising
01: Rising
00: Falling
00: Falling
CRC0n1 = 1
TI00n pin input
(reverse phase)
11: Both edges
(cannot be captured)
CRC0n1 bit = 0
TI01n pin input
11: Both edges
Capture operation of
CR00n
Interrupt signal INTTM00n signal is not
generated even if value
is captured.
Interrupt signal INTTM00n signal is
generated each time
value is captured.
Set values of ES0n1 and
ES0n0
Position of edge to be
captured
01: Rising
00: Falling
TI00n pin inputNote
11: Both edges
Capture operation of
CR01n
Interrupt signal INTTM01n signal is
generated each time
value is captured.
Note The capture operation of CR01n is not affected by the setting of the CRC0n1 bit.
Caution To capture the count value of the TM0n register to the CR00n register by using the phase
reverse to that input to the TI00n pin, the interrupt request signal (INTTM00n) is not generated
after the value has been captured. If the valid edge is detected on the TI01n pin during this
operation, the capture operation is not performed but the INTTM00n signal is generated as an
external interrupt signal. To not use the external interrupt, mask the INTTM00n signal.
Remarks 1. CRC0n1: See 7.3 (2) Capture/compare control register 0n (CRC0n).
ES1n1, ES1n0, ES0n1, ES0n0: See 7.3 (4) Prescaler mode register 0n (PRM0n).
2. n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 163
7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01
Registers used to control 16-bit timer/event counters 00 and 01 are shown below.
• 16-bit timer mode control register 0n (TMC0n)
• Capture/compare control register 0n (CRC0n)
• 16-bit timer output control register 0n (TOC0n)
• Prescaler mode register 0n (PRM0n)
• Port mode register 0 (PM0)
• Port register 0 (P0)
(1) 16-bit timer mode control register 0n (TMC0n)
TMC0n is an 8-bit register that sets the 16-bit timer/event counter 0n operation mode, TM0n clear mode, and
output timing, and detects an overflow.
Rewriting TMC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). However, it can
be changed when TMC0n3 and TMC0n2 are cleared to 00 (stopping operation) and when OVF0n is cleared to 0.
TMC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets TMC0n to 00H.
Caution 16-bit timer/event counter 0n starts operation at the moment TMC0n2 and TMC0n3 are set to
values other than 00 (operation stop mode), respectively. Set TMC0n2 and TMC0n3 to 00 to
stop the operation.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
164
Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address: FFBAH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
TMC00 0 0 0 0 TMC003 TMC002 TMC001 OVF00
TMC003 TMC002 Operation enable of 16-bit timer/event counter 00
0 0
Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock.
Clears 16-bit timer counter 00 (TM00).
0 1 Free-running timer mode
1 0 Clear & start mode entered by TI000 pin valid edge inputNote
1 1 Clear & start mode entered upon a match between TM00 and CR000
TMC001 Condition to reverse timer output (TO00)
0 • Match between TM00 and CR000 or match between TM00 and CR010
1 • Match between TM00 and CR000 or match between TM00 and CR010
• Trigger input of TI000 pin valid edge
OVF00 TM00 overflow flag
Clear (0) Clears OVF00 to 0 or TMC003 and TMC002 = 00
Set (1) Overflow occurs.
OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match
between TM00 and CR000).
It can also be set to 1 by writing 1 to OVF00.
Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00).
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 165
Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01)
Address: FFB6H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
TMC01 0 0 0 0 TMC013 TMC012 TMC011 OVF01
TMC013 TMC012 Operation enable of 16-bit timer/event counter 01
0 0
Disables 16-bit timer/event counter 01 operation. Stops supplying operating clock.
Clears 16-bit timer counter 01 (TM01).
0 1 Free-running timer mode
1 0 Clear & start mode entered by TI001 pin valid edge inputNote
1 1 Clear & start mode entered upon a match between TM01 and CR001
TMC011 Condition to reverse timer output (TO01)
0 • Match between TM01 and CR001 or match between TM01 and CR011
1 • Match between TM01 and CR001 or match between TM01 and CR011
• Trigger input of TI001 pin valid edge
OVF01 TM01 overflow flag
Clear (0) Clears OVF01 to 0 or TMC013 and TMC012 = 00
Set (1) Overflow occurs.
OVF01 is set to 1 when the value of TM01 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI001 pin valid edge input, and clear & start mode entered upon a match
between TM01 and CR001).
It can also be set to 1 by writing 1 to OVF01.
Note The TI001 pin valid edge is set by bits 5 and 4 (ES011, ES010) of prescaler mode register 01 (PRM01).
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
166
(2) Capture/compare control register 0n (CRC0n)
CRC0n is the register that controls the operation of CR00n and CR01n.
Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00).
CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears CRC0n to 00H.
Figure 7-8. Format of Capture/Compare Control Register 00 (CRC00)
Address: FFBCH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CRC00 0 0 0 0 0 CRC002 CRC001 CRC000
CRC002 CR010 operating mode selection
0 Operates as compare register
1 Operates as capture register
CRC001 CR000 capture trigger selection
0 Captures on valid edge of TI010 pin
1 Captures on valid edge of TI000 pin by reverse phaseNote
The valid edge of the TI010 and TI000 pin is set by PRM00.
If ES001 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot
be detected.
CRC000 CR000 operating mode selection
0 Operates as compare register
1 Operates as capture register
If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and
CR000), be sure to set CRC000 to 0.
Note When the valid edge is detected from the TI010 pin, the capture operation is not performed but the
INTTM000 signal is generated as an external interrupt signal.
Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse
two cycles longer than the count clock selected by prescaler mode register 00 (PRM00).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 167
Figure 7-9. Example of CR01n Capture Operation (When Rising Edge Is Specified)
Count clock
TM0n
TI00n
Rising edge detection
CR01n
INTTM01n
N − 3N − 2N − 1 N N + 1
N
Valid edge
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Figure 7-10. Format of Capture/Compare Control Register 01 (CRC01)
Address: FFB8H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CRC01 0 0 0 0 0 CRC012 CRC011 CRC010
CRC012 CR011 operating mode selection
0 Operates as compare register
1 Operates as capture register
CRC011 CR001 capture trigger selection
0 Captures on valid edge of TI011 pin
1 Captures on valid edge of TI001 pin by reverse phaseNote
The valid edge of the TI011 and TI001 pin is set by PRM01.
If ES011 and ES010 are set to 11 (both edges) when CRC011 is 1, the valid edge of the TI001 pin cannot
be detected.
CRC010 CR001 operating mode selection
0 Operates as compare register
1 Operates as capture register
If TMC013 and TMC012 are set to 11 (clear & start mode entered upon a match between TM01 and
CR001), be sure to set CRC010 to 0.
Note When the valid edge is detected from the TI011 pin, the capture operation is not performed but the
INTTM001 signal is generated as an external interrupt signal.
Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse
two cycles longer than the count clock selected by prescaler mode register 01 (PRM01) (see
Figure 7-9 Example of CR01n Capture Operation (When Rising Edge Is Specified).
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
168
(3) 16-bit timer output control register 0n (TOC0n)
TOC0n is an 8-bit register that controls the TO0n pin output.
TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 = other than 00).
Rewriting the other bits is prohibited during operation.
However, TOC0n4 can be rewritten during timer operation as a means to rewrite CR01n (see 7.5.1 Rewriting
CR01n during TM0n operation).
TOC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TOC0n to 00H.
Caution Be sure to set TOC0n using the following procedure.
<1> Set TOC0n4 and TOC0n1 to 1.
<2> Set only TOE0n to 1.
<3> Set either of LVS0n or LVR0n to 1.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 169
Figure 7-11. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FFBDH After reset: 00H R/W
Symbol 7 <6> <5> 4 <3> <2> 1 <0>
TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
OSPT00 One-shot pulse output trigger via software
0 −
1 One-shot pulse output
The value of this bit is always “0” when it is read. Do not set this bit to 1 in a mode other than the one-
shot pulse output mode.
If it is set to 1, TM00 is cleared and started.
OSPE00 One-shot pulse output operation control
0 Successive pulse output
1 One-shot pulse output
One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by
TI000 pin valid edge input.
The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM00 and
CR000.
TOC004 TO00 pin output control on match between CR010 and TM00
0 Disables inversion operation
1 Enables inversion operation
The interrupt signal (INTTM010) is generated even when TOC004 = 0.
LVS00 LVR00 Setting of TO00 pin output status
0 0 No change
0 1 Initial value of TO00 pin output is low level (TO00 pin output is cleared to 0).
1 0 Initial value of TO00 pin output is high level (TO00 pin output is set to 1).
1 1 Setting prohibited
• LVS00 and LVR00 can be used to set the initial value of the output level of the TO00 pin. If the initial
value does not have to be set, leave LVS00 and LVR00 as 00.
• Be sure to set LVS00 and LVR00 when TOE00 = 1.
LVS00, LVR00, and TOE00 being simultaneously set to 1 is prohibited.
• LVS00 and LVR00 are trigger bits. By setting these bits to 1, the initial value of the output level of the
TO00 pin can be set. Even if these bits are cleared to 0, output of the TO00 pin is not affected.
• The values of LVS00 and LVR00 are always 0 when they are read.
• For how to set LVS00 and LVR00, see 7.5.2 Setting LVS0n and LVR0n.
TOC001 TO00 pin output control on match between CR000 and TM00
0 Disables inversion operation
1 Enables inversion operation
The interrupt signal (INTTM000) is generated even when TOC001 = 0.
TOE00 TO00 pin output control
0 Disables output (TO00 pin output fixed to low level)
1 Enables output
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
170
Figure 7-12. Format of 16-Bit Timer Output Control Register 01 (TOC01)
Address: FFB9H After reset: 00H R/W
Symbol 7 <6> <5> 4 <3> <2> 1 <0>
TOC01 0 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01
OSPT01 One-shot pulse output trigger via software
0 −
1 One-shot pulse output
The value of this bit is always 0 when it is read. Do not set this bit to 1 in a mode other than the one-shot
pulse output mode.
If it is set to 1, TM01 is cleared and started.
OSPE01 One-shot pulse output operation control
0 Successive pulse output
1 One-shot pulse output
One-shot pulse output operates correctly in the free-running timer mode or clear & start mode entered by
TI001 pin valid edge input.
The one-shot pulse cannot be output in the clear & start mode entered upon a match between TM01 and
CR001.
TOC014 TO01 pin output control on match between CR011 and TM01
0 Disables inversion operation
1 Enables inversion operation
The interrupt signal (INTTM011) is generated even when TOC014 = 0.
LVS01 LVR01 Setting of TO01 pin output status
0 0 No change
0 1 Initial value of TO01 pin output is low level (TO01 pin output is cleared to 0).
1 0 Initial value of TO01 pin output is high level (TO01 pin output is set to 1).
1 1 Setting prohibited
• LVS01 and LVR01 can be used to set the initial value of the output level of the TO01 pin. If the initial
value does not have to be set, leave LVS01 and LVR01 as 00.
• Be sure to set LVS01 and LVR01 when TOE01 = 1.
LVS01, LVR01, and TOE01 being simultaneously set to 1 is prohibited.
• LVS01 and LVR01 are trigger bits. By setting these bits to 1, the initial value of the output level of the
TO01 pin can be set. Even if these bits are cleared to 0, output of the TO01 pin is not affected.
• The values of LVS01 and LVR01 are always 0 when they are read.
• For how to set LVS01 and LVR01, see 7.5.2 Setting LVS0n and LVR0n.
TOC011 TO01 pin output control on match between CR001 and TM01
0 Disables inversion operation
1 Enables inversion operation
The interrupt signal (INTTM001) is generated even when TOC011 = 0.
TOE01 TO01 pin output control
0 Disables output (TO01 pin output is fixed to low level)
1 Enables output
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 171
(4) Prescaler mode register 0n (PRM0n)
PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges.
Rewriting PRM0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00).
PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PRM0n to 00H.
Cautions 1. Do not apply the following setting when setting the PRM0n1 and PRM0n0 bits to 11 (to
specify the valid edge of the TI00n pin as a count clock).
• Clear & start mode entered by the TI00n pin valid edge
• Setting the TI00n pin as a capture trigger
2. If the operation of the 16-bit timer/event counter 0n is enabled when the TI00n or TI01n pin
is at high level and when the valid edge of the TI00n or TI01n pin is specified to be the rising
edge or both edges, the high level of the TI00n or TI01n pin is detected as a rising edge.
Note this when the TI00n or TI01n pin is pulled up. However, the rising edge is not detected
when the timer operation has been once stopped and then is enabled again.
3. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same
time, and the valid edge of TI011 and timer output (TO01) cannot be used for the P06 pin at
the same time. Select either of the functions.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
172
Figure 7-13. Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PRM00 ES101 ES100 ES001 ES000 0 0 PRM001 PRM000
ES101 ES100 TI010 pin valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
ES001 ES000 TI000 pin valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
Count clock selection PRM001 PRM000
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz
0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz
0 1 fPRS/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz
1 0 fPRS/28 7.81 kHz 19.53 kHz 39.06 kHz 78.12 kHz
1 1 TI000 valid edgeNote
Note The external clock requires a pulse two cycles longer than internal clock (fPRS).
Remark f
PRS: Peripheral hardware clock frequency
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 173
Figure 7-14. Format of Prescaler Mode Register 01 (PRM01)
Address: FFB7H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PRM01 ES111 ES110 ES011 ES010 0 0 PRM011 PRM010
ES111 ES110 TI011 pin valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
ES011 ES010 TI001 pin valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
Count clock selection PRM011 PRM010
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz
0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz
0 1 fPRS/24 125 kHz 312.5 kHz 625 kHz 1.25 MHz
1 0 fPRS/26 31.25 kHz 78.125 kHz 156.25 kHz 312.5 kHz
1 1 TI001 valid edgeNote
Note The external clock requires a pulse two cycles longer than internal clock (fPRS).
Remark f
PRS: Peripheral hardware clock frequency
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
174
(5) Port mode register 0 (PM0)
This register sets port 0 input/output in 1-bit units.
When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output
latches of P01 and P06 to 0.
When using the P00/TI000, P01/TO00/TI010, P05/TI001/SSI11, and P06/TO01/TI011 pins for timer input, set
PM00, PM01, PM05, and PM06 to 1. At this time, the output latches of P00, P01, P05, and P06 may be 0 or 1.
PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM0 to FFH.
Figure 7-15. Format of Port Mode Register 0 (PM0)
7
1
6
PM06
5
PM05
4
PM04
3
PM03
2
PM02
1
PM01
0
PM00
Symbol
PM0
Address: FF20H After reset: FFH R/W
PM0n
0
1
P0n pin I/O mode selection (n = 0 to 6)
Output mode (output buffer on)
Input mode (output buffer off)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 175
7.4 Operation of 16-Bit Timer/Event Counters 00 and 01
7.4.1 Interval timer operation
If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to 11 (clear & start
mode entered upon a match between TM0n and CR00n), the count operation is started in synchronization with the
count clock.
When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H and a match interrupt signal
(INTTM00n) is generated. This INTTM00n signal enables TM0n to operate as an interval timer.
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Figure 7-16. Block Diagram of Interval Timer Operation
16-bit counter (TM0n)
CR00n register
Operable bits
TMC0n3, TMC0n2
Count clock
Clear
Match signal INTTM00n signal
Figure 7-17. Basic Timing Example of Interval Timer Operation
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
N
1100
N N N N
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
176
Figure 7-18. Example of Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 0n (TMC0n)
00001100
TMC0n3 TMC0n2 TMC0n1 OVF0n
Clears and starts on match
between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
00000000
CRC0n2 CRC0n1 CRC0n0
CR00n used as
compare register
(c) 16-bit timer output control register 0n (TOC0n)
00000
LVR0nLVS0nTOC0n4OSPE0nOSPT0n TOC0n1 TOE0n
000
(d) Prescaler mode register 0n (PRM0n)
00000
3 2 PRM0n1 PRM0n0ES1n1 ES1n0 ES0n1 ES0n0
Selects count clock
0 0/1 0/1
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
If M is set to CR00n, the interval time is as follows.
• Interval time = (M + 1) × Count clock cycle
Setting CR00n to 0000H is prohibited.
(g) 16-bit capture/compare register 01n (CR01n)
Usually, CR01n is not used for the interval timer function. However, a compare match interrupt (INTTM01n)
is generated when the set value of CR01n matches the value of TM0n.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 177
Figure 7-19. Example of Software Processing for Interval Timer Function
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
CR00n register
INTTM00n signal
N
1100
N N N
<1> <2>
TMC0n3, TMC0n2 bits = 11
TMC0n3, TMC0n2 bits = 00
Register initial setting
PRM0n register,
CRC0n register,
CR00n register,
port setting
Initial setting of these registers is performed before
setting the TMC0n3 and TMC0n2 bits to 11.
Starts count operation
The counter is initialized and counting is stopped
by clearing the TMC0n3 and TMC0n2 bits to 00.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
178
7.4.2 Square wave output operation
When 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1), a square wave can be output from the
TO0n pin by setting the 16-bit timer output control register 0n (TOC0n) to 03H.
When TMC0n3 and TMC0n2 are set to 11 (count clear & start mode entered upon a match between TM0n and
CR00n), the counting operation is started in synchronization with the count clock.
When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H, an interrupt signal
(INTTM00n) is generated, and output of the TO0n pin is inverted. This TO0n pin output that is inverted at fixed
intervals enables TO0n to output a square wave.
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Figure 7-20. Block Diagram of Square Wave Output Operation
16-bit counter (TM0n)
CR00n register
Operable bits
TMC0n3, TMC0n2
Count clock
Clear
Match signal INTTM00n signal
Output
controller TO0n pin
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Figure 7-21. Basic Timing Example of Square Wave Output Operation
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Compare register
(CR00n)
TO0n pin output
Compare match interrupt
(INTTM00n)
N
1100
N N N N
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
Interval
(N + 1)
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 179
Figure 7-22. Example of Register Settings for Square Wave Output Operation
(a) 16-bit timer mode control register 0n (TMC0n)
00001100
TMC0n3 TMC0n2 TMC0n1 OVF0n
Clears and starts on match
between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
00000000
CRC0n2 CRC0n1 CRC0n0
CR00n used as
compare register
(c) 16-bit timer output control register 0n (TOC0n)
0 0 0 0 0/1
LVR0nLVS0nTOC0n4OSPE0nOSPT0n TOC0n1 TOE0n
Enables TO0n pin output.
Inverts TO0n pin output on match
between TM0n and CR00n.
0/1 1 1
Specifies initial value of TO0n output F/F
(d) Prescaler mode register 0n (PRM0n)
00000
3 2 PRM0n1 PRM0n0ES1n1 ES1n0 ES0n1 ES0n0
Selects count clock
0 0/1 0/1
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
If M is set to CR00n, the interval time is as follows.
• Square wave frequency = 1 / [2 × (M + 1) × Count clock cycle]
Setting CR00n to 0000H is prohibited.
(g) 16-bit capture/compare register 01n (CR01n)
Usually, CR01n is not used for the square wave output function. However, a compare match interrupt
(INTTM01n) is generated when the set value of CR01n matches the value of TM0n.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
180
Figure 7-23. Example of Software Processing for Square Wave Output Function
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
CR00n register
TO0n pin output
INTTM00n signal
TO0n output control bit
(TOC0n1, TOE0n)
TMC0n3, TMC0n2 bits = 11
TMC0n3, TMC0n2 bits = 00
Register initial setting
PRM0n register,
CRC0n register,
TOC0n register
Note
,
CR00n register,
port setting
Initial setting of these registers is performed before
setting the TMC0n3 and TMC0n2 bits to 11.
Starts count operation
The counter is initialized and counting is stopped
by clearing the TMC0n3 and TMC0n2 bits to 00.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
N
1100
NNN
<1> <2>
00
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 181
7.4.3 External event counter operation
When bits 1 and 0 (PRM0n1 and PRM0n0) of the prescaler mode register 0n (PRM0n) are set to 11 (for counting
up with the valid edge of the TI00n pin) and bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register
0n (TMC0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating
matching between TM0n and CR00n (INTTM00n) is generated.
To input the external event, the TI00n pin is used. Therefore, the timer/event counter cannot be used as an
external event counter in the clear & start mode entered by the TI00n pin valid edge input (when TMC0n3 and
TMC0n2 = 10).
The INTTM00n signal is generated with the following timing.
• Timing of generation of INTTM00n signal (second time or later)
= Number of times of detection of valid edge of external event × (Set value of CR00n + 1)
However, the first match interrupt immediately after the timer/event counter has started operating is generated with
the following timing.
• Timing of generation of INTTM00n signal (first time only)
= Number of times of detection of valid edge of external event input × (Set value of CR00n + 2)
To detect the valid edge, the signal input to the TI00n pin is sampled during the clock cycle of fPRS. The valid edge
is not detected until it is detected two times in a row. Therefore, a noise with a short pulse width can be eliminated.
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Figure 7-24. Block Diagram of External Event Counter Operation
16-bit counter (TM0n)
CR00n register
Operable bits
TMC0n3, TMC0n2
Clear
Match signal INTTM00n signal
f
PRS
Edge
detection
TI00n pin
Output
controller TO0n pin
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
182
Figure 7-25. Example of Register Settings in External Event Counter Mode (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
00001100
TMC0n3 TMC0n2 TMC0n1 OVF0n
Clears and starts on match
between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
00000000
CRC0n2 CRC0n1 CRC0n0
CR00n used as
compare register
(c) 16-bit timer output control register 0n (TOC0n)
0 0 0 0/1 0/1
LVR0nLVS0nTOC0n4OSPE0nOSPT0n TOC0n1 TOE0n
0/1 0/1 0/1
0: Disables TO0n output
1: Enables TO0n output
00: Does not invert TO0n output on match
between TM0n and CR00n/CR01n.
01: Inverts TO0n output on match between
TM0n and CR00n.
10: Inverts TO0n output on match between
TM0n and CR01n.
11: Inverts TO0n output on match between
TM0n and CR00n/CR01n.
Specifies initial value of
TO0n output F/F
(d) Prescaler mode register 0n (PRM0n)
0 0 0/1 0/1 0
3 2 PRM0n1 PRM0n0ES1n1 ES1n0 ES0n1 ES0n0
Selects count clock
(specifies valid edge of TI00n).
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
011
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 183
Figure 7-25. Example of Register Settings in External Event Counter Mode (2/2)
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
If M is set to CR00n, the interrupt signal (INTTM00n) is generated when the number of external events
reaches (M + 1).
Setting CR00n to 0000H is prohibited.
(g) 16-bit capture/compare register 01n (CR01n)
Usually, CR01n is not used in the external event counter mode. However, a compare match interrupt
(INTTM01n) is generated when the set value of CR01n matches the value of TM0n.
Therefore, mask the interrupt request by using the interrupt mask flag (TMMK01n).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
184
Figure 7-26. Example of Software Processing in External Event Counter Mode
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2) 1100
N N N
TMC0n3, TMC0n2 bits = 11
TMC0n3, TMC0n2 bits = 00
Register initial setting
PRM0n register,
CRC0n register,
TOC0n register
Note
,
CR00n register,
port setting
START
STOP
<1> <2>
Compare match interrupt
(INTTM00n)
Compare register
(CR00n)
TO0n output control bits
(TOC0n4, TOC0n1, TOE0n)
TO0n pin output
N
00
Initial setting of these registers is performed before
setting the TMC0n3 and TMC0n2 bits to 11.
Starts count operation
The counter is initialized and counting is stopped
by clearing the TMC0n3 and TMC0n2 bits to 00.
<1> Count operation start flow
<2> Count operation stop flow
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 185
7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input
When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 10 (clear &
start mode entered by the TI00n pin valid edge input) and the count clock (set by PRM0n) is supplied to the
timer/event counter, TM0n starts counting up. When the valid edge of the TI00n pin is detected during the counting
operation, TM0n is cleared to 0000H and starts counting up again. If the valid edge of the TI00n pin is not detected,
TM0n overflows and continues counting.
The valid edge of the TI00n pin is a cause to clear TM0n. Starting the counter is not controlled immediately after
the start of the operation.
CR00n and CR01n are used as compare registers and capture registers.
(a) When CR00n and CR01n are used as compare registers
Signals INTTM00n and INTTM01n are generated when the value of TM0n matches the value of CR00n and
CR01n.
(b) When CR00n and CR01n are used as capture registers
The count value of TM0n is captured to CR00n and the INTTM00n signal is generated when the valid edge is
input to the TI01n pin (or when the phase reverse to that of the valid edge is input to the TI00n pin).
When the valid edge is input to the TI00n pin, the count value of TM0n is captured to CR01n and the
INTTM01n signal is generated. As soon as the count value has been captured, the counter is cleared to
0000H.
Caution Do not set the count clock as the valid edge of the TI00n pin (PRM0n1 and PRM0n0 = 11). When
PRM0n1 and PRM0n0 = 11, TM0n is cleared.
Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
3. n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
186
(1) Operation in clear & start mode entered by TI00n pin valid edge input
(CR00n: compare register, CR01n: compare register)
Figure 7-27. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Compare Register)
Timer counter
(TM0n)
Clear
Output
controller
Edge
detection
Compare register
(CR01n)
Match signal
TO0n pin
Match signal Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
TI00n pin
Compare register
(CR00n)
Operable bits
TMC0n3, TMC0n2
Count clock
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 187
Figure 7-28. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Compare Register)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 08H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
M
10
M
NN NN
MMM
00
N
(b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 0AH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
M
10
M
NN NN
MMM
00
N
(a) and (b) differ as follows depending on the setting of bit 1 (TMC0n1) of the 16-bit timer mode control register 0n
(TMC0n).
(a) The output level of the TO0n pin is inverted when TM0n matches a compare register.
(b) The output level of the TO0n pin is inverted when TM0n matches a compare register or when the valid
edge of the TI00n pin is detected.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
188
(2) Operation in clear & start mode entered by TI00n pin valid edge input
(CR00n: compare register, CR01n: capture register)
Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Capture Register)
Timer counter
(TM0n)
Clear
Output
controller
Edge
detector
Capture register
(CR01n)
Capture signal
TO0n pin
Match signal Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
TI00n pin
Compare register
(CR00n)
Operable bits
TMC0n3, TMC0n2
Count clock
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 189
Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Capture Register) (1/2)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR00n = 0001H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
TO0n pin output
0001H
10
QPNM
S
00
0000H M N S P Q
This is an application example where the output level of the TO0n pin is inverted when the count value has been
captured & cleared.
The count value is captured to CR01n and TM0n is cleared (to 0000H) when the valid edge of the TI00n pin is
detected. When the count value of TM0n is 0001H, a compare match interrupt signal (INTTM00n) is generated,
and the output level of the TO0n pin is inverted.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
190
Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Compare Register, CR01n: Capture Register) (2/2)
(b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 0AH, CR00n = 0003H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
TO0n pin output
0003H
0003H
10
QPNM
S
00
0000H M
4444
NS PQ
This is an application example where the width set to CR00n (4 clocks in this example) is to be output from the
TO0n pin when the count value has been captured & cleared.
The count value is captured to CR01n, a capture interrupt signal (INTTM01n) is generated, TM0n is cleared (to
0000H), and the output level of the TO0n pin is inverted when the valid edge of the TI00n pin is detected. When
the count value of TM0n is 0003H (four clocks have been counted), a compare match interrupt signal (INTTM00n)
is generated and the output level of the TO0n pin is inverted.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 191
(3) Operation in clear & start mode by entered TI00n pin valid edge input
(CR00n: capture register, CR01n: compare register)
Figure 7-31. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Compare Register)
Timer counter
(TM0n)
Clear
Output
controller
Edge
detection
Capture register
(CR00n)
Capture signal
TO0n pin
Match signal Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
TI00n pin
Compare register
(CR01n)
Operable bits
TMC0n3, TMC0n2
Count clock
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
192
Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Compare Register) (1/2)
(a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 08H, CR01n = 0001H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
10
P
N
MS
00
L
0001H
0000H MNS P
This is an application example where the output level of the TO0n pin is to be inverted when the count value has
been captured & cleared.
TM0n is cleared at the rising edge detection of the TI00n pin and it is captured to CR00n at the falling edge
detection of the TI00n pin.
When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is set to 1, the count value of TM0n is
captured to CR00n in the phase reverse to that of the signal input to the TI00n pin, but the capture interrupt signal
(INTTM00n) is not generated. However, the INTTM00n signal is generated when the valid edge of the TI01n pin
is detected. Mask the INTTM00n signal when it is not used.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 193
Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Compare Register) (2/2)
(b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 0AH, CR01n = 0003H
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
TO0n pin output
0003H
0003H
10
P
N
MS
00
4444
L
0000H M N S P
This is an application example where the width set to CR01n (4 clocks in this example) is to be output from the
TO0n pin when the count value has been captured & cleared.
TM0n is cleared (to 0000H) at the rising edge detection of the TI00n pin and captured to CR00n at the falling
edge detection of the TI00n pin. The output level of the TO0n pin is inverted when TM0n is cleared (to 0000H)
because the rising edge of the TI00n pin has been detected or when the value of TM0n matches that of a
compare register (CR01n).
When bit 1 (CRC0n1) of capture/compare control register 0n (CRC0n) is 1, the count value of TM0n is captured
to CR00n in the phase reverse to that of the input signal of the TI00n pin, but the capture interrupt signal
(INTTM00n) is not generated. However, the INTTM00n interrupt is generated when the valid edge of the TI01n
pin is detected. Mask the INTTM00n signal when it is not used.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
194
(4) Operation in clear & start mode entered by TI00n pin valid edge input
(CR00n: capture register, CR01n: capture register)
Figure 7-33. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register)
Timer counter
(TM0n)
Clear
Output
controller
Capture register
(CR00n)
Capture
signal
Capture signal
TO0n pin
Note
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
Capture register
(CR01n)
Operable bits
TMC0n3, TMC0n2
Count clock
Edge
detection
TI00n pin
Edge
detection
TI01n pin
Note
Selector
Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 195
Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register) (1/3)
(a) TOC0n = 13H, PRM0n = 30H, CRC0n = 05H, TMC0n = 0AH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
TO0n pin output
10
RST
O
L
M
N
P
Q
00
L
0000H
0000H LM NOP QRST
This is an application example where the count value is captured to CR01n, TM0n is cleared, and the TO0n pin
output is inverted when the rising or falling edge of the TI00n pin is detected.
When the edge of the TI01n pin is detected, an interrupt signal (INTTM00n) is generated. Mask the INTTM00n
signal when it is not used.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
196
Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register) (2/3)
(b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 0AH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI01n pin input)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Capture & count clear input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
10
R
S
T
O
L
M
N
P
Q
00
FFFFH
L
L
0000H
0000H
LMN
OPQ R S T
This is a timing example where an edge is not input to the TI00n pin, in an application where the count value is
captured to CR00n when the rising or falling edge of the TI01n pin is detected.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 197
Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input
(CR00n: Capture Register, CR01n: Capture Register) (3/3)
(c) TOC0n = 13H, PRM0n = 00H, CRC0n = 07H, TMC0n = 0AH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n pin input)
Capture register
(CR00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
Capture input
(TI01n)
Compare match interrupt
(INTTM00n)
0000H
10
P
O
M
QRT
S W
N
L
00
L
L
LN RPT
0000H MOQ SW
This is an application example where the pulse width of the signal input to the TI00n pin is measured.
By setting CRC0n, the count value can be captured to CR00n in the phase reverse to the falling edge of the
TI00n pin (i.e., rising edge) and to CR01n at the falling edge of the TI00n pin.
The high- and low-level widths of the input pulse can be calculated by the following expressions.
• High-level width = [CR01n value] – [CR00n value] × [Count clock cycle]
• Low-level width = [CR00n value] × [Count clock cycle]
If the reverse phase of the TI00n pin is selected as a trigger to capture the count value to CR00n, the INTTM00n
signal is not generated. Read the values of CR00n and CR01n to measure the pulse width immediately after the
INTTM01n signal is generated.
However, if the valid edge specified by bits 6 and 5 (ES1n1 and ES1n0) of prescaler mode register 0n (PRM0n) is
input to the TI01n pin, the count value is not captured but the INTTM00n signal is generated. To measure the
pulse width of the TI00n pin, mask the INTTM00n signal when it is not used.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
198
Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
0000100/10
TMC0n3 TMC0n2 TMC0n1 OVF0n
Clears and starts at valid
edge input of TI00n pin.
0: Inverts TO0n output on match
between CR00n and CR01n.
1: Inverts TO0n output on match
between CR00n and CR01n
and valid edge of TI00n pin.
(b) Capture/compare control register 0n (CRC0n)
000000/10/10/1
CRC0n2 CRC0n1 CRC0n0
0: CR00n used as compare register
1: CR00n used as capture register
0: CR01n used as compare register
1: CR01n used as capture register
0: TI01n pin is used as capture
trigger of CR00n.
1: Reverse phase of TI00n pin is
used as capture trigger of CR00n.
(c) 16-bit timer output control register 0n (TOC0n)
0 0 0 0/1 0/1
LVR0nLVS0nTOC0n4OSPE0nOSPT0n TOC0n1 TOE0n
0: Disables TO0n output
Note
1: Enables TO0n output
00: Does not invert TO0n output on match
between TM0n and CR00n/CR01n.
01: Inverts TO0n output on match between
TM0n and CR00n.
10: Inverts TO0n output on match between
TM0n and CR01n.
11: Inverts TO0n output on match between
TM0n and CR00n/CR01n.
Specifies initial value of
TO0n output F/F
0/1 0/1 0/1
Note The timer output (TO0n) cannot be used when detecting the valid edge of the TI01n pin is used.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 199
Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (2/2)
(d) Prescaler mode register 0n (PRM0n)
0/1 0/1 0/1 0/1 0
3 2 PRM0n1 PRM0n0ES1n1 ES1n0 ES0n1 ES0n0
Count clock selection
(setting TI00n valid edge is prohibited)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
(setting prohibited when CRC0n1 = 1)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
0 0/1 0/1
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
When this register is used as a compare register and when its value matches the count value of TM0n, an
interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared.
To use this register as a capture register, select either the TI00n or TI01n pinNote input as a capture trigger.
When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n.
Note The timer output (TO0n) cannot be used when detection of the valid edge of the TI01n pin is used.
(g) 16-bit capture/compare register 01n (CR01n)
When this register is used as a compare register and when its value matches the count value of TM0n, an
interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared.
When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the
valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
200
Figure 7-36. Example of Software Processing in Clear & Start Mode Entered by TI00n Pin Valid Edge Input
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Count clear input
(TI00n pin input)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
M
10
M
NN N N
MMM
00
<1> <2> <2> <2> <3><2>
00
N
TMC0n3, TMC0n2 bits = 10
Edge input to TI00n pin
Register initial setting
PRM0n register,
CRC0n register,
TOC0n registerNote,
CR00n, CR01n registers,
TMC0n.TMC0n1 bit,
port setting
Initial setting of these
registers is performed
before setting the
TMC0n3 and TMC0n2
bits to 10.
Starts count operation
When the valid edge is input to the TI00n pin,
the value of the TM0n register is cleared.
START
<1> Count operation start flow
<2> TM0n register clear & start flow
TMC0n3, TMC0n2 bits = 00 The counter is initialized
and counting is stopped
by clearing the TMC0n3
and TMC0n2 bits to 00.
STOP
<3> Count operation stop flow
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 201
7.4.5 Free-running timer operation
When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 01 (free-
running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock.
When it has counted up to FFFFH, the overflow flag (OVF0n) is set to 1 at the next clock, and TM0n is cleared (to
0000H) and continues counting. Clear OVF0n to 0 by executing the CLR instruction via software.
The following three types of free-running timer operations are available.
• Both CR00n and CR01n are used as compare registers.
• One of CR00n or CR01n is used as a compare register and the other is used as a capture register.
• Both CR00n and CR01n are used as capture registers.
Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
(1) Free-running timer mode operation
(CR00n: compare register, CR01n: compare register)
Figure 7-37. Block Diagram of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Compare Register)
Timer counter
(TM0n)
Output
controller
Compare register
(CR01n)
Match signal
TO0n pin
Match signal Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
Compare register
(CR00n)
Operable bits
TMC0n3, TMC0n2
Count clock
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
202
Figure 7-38. Timing Example of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Compare Register)
• TOC0n = 13H, PRM0n = 00H, CRC0n = 00H, TMC0n = 04H
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
OVF0n bit
01
M
NM
NM
NM
N
00 00
N
0 write clear 0 write clear 0 write clear 0 write clear
M
This is an application example where two compare registers are used in the free-running timer mode.
The output level of the TO0n pin is reversed each time the count value of TM0n matches the set value of CR00n
or CR01n. When the count value matches the register value, the INTTM00n or INTTM01n signal is generated.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
(2) Free-running timer mode operation
(CR00n: compare register, CR01n: capture register)
Figure 7-39. Block Diagram of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Capture Register)
Timer counter
(TM0n)
Output
controller
Edge
detection
Capture register
(CR01n)
Capture signal
TO0n pin
Match signal Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
TI00n pin
Compare register
(CR00n)
Operable bits
TMC0n3, TMC0n2
Count clock
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 203
Figure 7-40. Timing Example of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Capture Register)
• TOC0n = 13H, PRM0n = 10H, CRC0n = 04H, TMC0n = 04H
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI00n)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
TO0n pin output
Overflow flag
(OVF0n)
0 write clear 0 write clear 0 write clear 0 write clear
01
MNSP
Q
00
0000H
0000H
MN S
PQ
This is an application example where a compare register and a capture register are used at the same time in the
free-running timer mode.
In this example, the INTTM00n signal is generated and the output level of the TO0n pin is reversed each time the
count value of TM0n matches the set value of CR00n (compare register). In addition, the INTTM01n signal is
generated and the count value of TM0n is captured to CR01n each time the valid edge of the TI00n pin is
detected.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
204
(3) Free-running timer mode operation
(CR00n: capture register, CR01n: capture register)
Figure 7-41. Block Diagram of Free-Running Timer Mode
(CR00n: Capture Register, CR01n: Capture Register)
Timer counter
(TM0n)
Capture register
(CR00n)
Capture
signal
Capture signal
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
Capture register
(CR01n)
Operable bits
TMC0n3, TMC0n2
Count clock
Edge
detection
TI00n pin
Edge
detection
TI01n pin
Selector
Remarks 1. If both CR00n and CR01n are used as capture registers in the free-running timer mode, the output
level of the TO0n pin is not inverted.
However, it can be inverted each time the valid edge of the TI00n pin is detected if bit 1 (TMC0n1)
of 16-bit timer mode control register 0n (TMC0n) is set to 1.
2. n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 205
Figure 7-42. Timing Example of Free-Running Timer Mode
(CR00n: Capture Register, CR01n: Capture Register) (1/2)
(a) TOC0n = 13H, PRM0n = 50H, CRC0n = 05H, TMC0n = 04H
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
Capture trigger input
(TI01n)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Overflow flag
(OVF0n)
01
M
ABCDE
NSPQ
00
0 write clear 0 write clear 0 write clear 0 write clear
0000H ABC
DE
0000H MN S
PQ
This is an application example where the count values that have been captured at the valid edges of separate
capture trigger signals are stored in separate capture registers in the free-running timer mode.
The count value is captured to CR01n when the valid edge of the TI00n pin input is detected and to CR00n when
the valid edge of the TI01n pin input is detected.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
206
Figure 7-42. Timing Example of Free-Running Timer Mode
(CR00n: Capture Register, CR01n: Capture Register) (2/2)
(b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 04H
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI01n)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Capture trigger input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
01
L
MPS
N
O R
QT
00
0000H
0000H
LMN
OPQ R S T
L
L
This is an application example where both the edges of the TI01n pin are detected and the count value is
captured to CR00n in the free-running timer mode.
When both CR00n and CR01n are used as capture registers and when the valid edge of only the TI01n pin is to
be detected, the count value cannot be captured to CR01n.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 207
Figure 7-43. Example of Register Settings in Free-Running Timer Mode (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
0000010/10
TMC0n3 TMC0n2 TMC0n1 OVF0n
Free-running timer mode
0: Inverts TO0n pin output on match
between CR00n and CR01n.
1: Inverts TO0n pin output on match
between CR00n and CR01n and
valid edge of TI00n pin.
(b) Capture/compare control register 0n (CRC0n)
000000/10/10/1
CRC0n2 CRC0n1 CRC0n0
0: CR00n used as compare register
1: CR00n used as capture register
0: CR01n used as compare register
1: CR01n used as capture register
0: TI01n pin is used as capture
trigger of CR00n.
1: Reverse phase of TI00n pin is
used as capture trigger of CR00n.
(c) 16-bit timer output control register 0n (TOC0n)
0 0 0 0/1 0/1
LVR0nLVS0nTOC0n4OSPE0nOSPT0n TOC0n1 TOE0n
0: Disables TO0n output
1: Enables TO0n output
00: Does not invert TO0n output on match
between TM0n and CR00n/CR01n.
01: Inverts TO0n output on match between
TM0n and CR00n.
10: Inverts TO0n output on match between
TM0n and CR01n.
11: Inverts TO0n output on match between
TM0n and CR00n/CR01n.
Specifies initial value of
TO0n output F/F
0/1 0/1 0/1
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
208
Figure 7-43. Example of Register Settings in Free-Running Timer Mode (2/2)
(d) Prescaler mode register 0n (PRM0n)
0/1 0/1 0/1 0/1 0
3 2 PRM0n1 PRM0n0ES1n1 ES1n0 ES0n1 ES0n0
Count clock selection
(setting TI00n valid edge is prohibited)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
(setting prohibited when CRC0n1 = 1)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
0 0/1 0/1
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
When this register is used as a compare register and when its value matches the count value of TM0n, an
interrupt signal (INTTM00n) is generated. The count value of TM0n is not cleared.
To use this register as a capture register, select either the TI00n or TI01n pin input as a capture trigger.
When the valid edge of the capture trigger is detected, the count value of TM0n is stored in CR00n.
(g) 16-bit capture/compare register 01n (CR01n)
When this register is used as a compare register and when its value matches the count value of TM0n, an
interrupt signal (INTTM01n) is generated. The count value of TM0n is not cleared.
When this register is used as a capture register, the TI00n pin input is used as a capture trigger. When the
valid edge of the capture trigger is detected, the count value of TM0n is stored in CR01n.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 209
Figure 7-44. Example of Software Processing in Free-Running Timer Mode
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
Timer output control bits
(TOE0n, TOC0n4, TOC0n1)
TO0n pin output
M
01
N N N N
M
M
M
00
<1> <2>
00
N
TMC0n3, TMC0n2 bits = 0, 1
Register initial setting
PRM0n register,
CRC0n register,
TOC0n register
Note
,
CR00n/CR01n register,
TMC0n.TMC0n1 bit,
port setting
Initial setting of these registers is performed
before setting the TMC0n3 and TMC0n2
bits to 01.
Starts count operation
START
<1> Count operation start flow
TMC0n3, TMC0n2 bits = 0, 0 The counter is initialized and counting is stopped
by clearing the TMC0n3 and TMC0n2 bits to 00.
STOP
<2> Count operation stop flow
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
210
7.4.6 PPG output operation
A square wave having a pulse width set in advance by CR01n is output from the TO0n pin as a PPG
(Programmable Pulse Generator) signal during a cycle set by CR00n when bits 3 and 2 (TMC0n3 and TMC0n2) of 16-
bit timer mode control register 0n (TMC0n) are set to 11 (clear & start upon a match between TM0n and CR00n).
The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
• Pulse cycle = (Set value of CR00n + 1) × Count clock cycle
• Duty = (Set value of CR01n + 1) / (Set value of CR00n + 1)
Caution To change the duty factor (value of CR01n) during operation, see 7.5.1 Rewriting CR01n during
TM0n operation.
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Figure 7-45. Block Diagram of PPG Output Operation
Timer counter
(TM0n)
Clear
Output
controller
Compare register
(CR01n)
Match signal
TO0n pin
Match signal Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
Compare register
(CR00n)
Operable bits
TMC0n3, TMC0n2
Count clock
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 211
Figure 7-46. Example of Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 0n (TMC0n)
00001100
TMC0n3 TMC0n2 TMC0n1 OVF0n
Clears and starts on match
between TM0n and CR00n.
(b) Capture/compare control register 0n (CRC0n)
00000000
CRC0n2 CRC0n1 CRC0n0
CR00n used as
compare register
CR01n used as
compare register
(c) 16-bit timer output control register 0n (TOC0n)
0 0 0 1 0/1
LVR0nLVS0nTOC0n4OSPE0nOSPT0n TOC0n1 TOE0n
Enables TO0n output
11: Inverts TO0n output on
match between TM0n
and CR00n/CR01n.
00: Disables one-shot pulse
output
Specifies initial value of
TO0n output F/F
0/1 1 1
(d) Prescaler mode register 0n (PRM0n)
00000
3 2 PRM0n1 PRM0n0ES1n1 ES1n0 ES0n1 ES0n0
Selects count clock
0 0/1 0/1
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
An interrupt signal (INTTM00n) is generated when the value of this register matches the count value of TM0n.
The count value of TM0n is not cleared.
(g) 16-bit capture/compare register 01n (CR01n)
An interrupt signal (INTTM01n) is generated when the value of this register matches the count value of TM0n.
The count value of TM0n is not cleared.
Caution Set values to CR00n and CR01n such that the condition 0000H ≤ CR01n < CR00n ≤ FFFFH is
satisfied.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
212
Figure 7-47. Example of Software Processing for PPG Output Operation
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
Timer output control bits
(TOE0n, TOC0n4, TOC0n1)
TO0n pin output
N
11
M M M
N
N
N
00
<1>
N + 1
<2>
00
M
TMC0n3, TMC0n2 bits = 11
Register initial setting
PRM0n register,
CRC0n register,
TOC0n register
Note
,
CR00n, CR01n registers,
port setting
Initial setting of these
registers is performed
before setting the
TMC0n3 and TMC0n2
bits.
Starts count operation
START
<1> Count operation start flow
TMC0n3, TMC0n2 bits = 00 The counter is initialized
and counting is stopped
by clearing the TMC0n3
and TMC0n2 bits to 00.
STOP
<2> Count operation stop flow
N + 1 N + 1
M + 1M + 1M + 1
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remarks 1. PPG pulse cycle = (M + 1) × Count clock cycle
PPG duty = (N + 1)/(M + 1)
2. n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 213
7.4.7 One-shot pulse output operation
A one-shot pulse can be output by setting bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control
register 0n (TMC0n) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI00n pin valid edge)
and setting bit 5 (OSPE0n) of 16-bit timer output control register 0n (TOC0n) to 1.
When bit 6 (OSPT0n) of TOC0n is set to 1 or when the valid edge is input to the TI00n pin during timer operation,
clearing & starting of TM0n is triggered, and a pulse of the difference between the values of CR00n and CR01n is
output only once from the TO0n pin.
Cautions 1. Do not input the trigger again (setting OSPT0n to 1 or detecting the valid edge of the TI00n
pin) while the one-shot pulse is output. To output the one-shot pulse again, generate the
trigger after the current one-shot pulse output has completed.
2. To use only the setting of OSPT0n to 1 as the trigger of one-shot pulse output, do not change
the level of the TI00n pin or its alternate function port pin. Otherwise, the pulse will be
unexpectedly output.
Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Figure 7-48. Block Diagram of One-Shot Pulse Output Operation
Timer counter
(TM0n)
Output
controller
Compare register
(CR01n)
Match signal
TO0n pin
Match signal Interrupt signal
(INTTM00n)
Interrupt signal
(INTTM01n)
Compare register
(CR00n)
Operable bits
TMC0n3, TMC0n2
Count clock
TI00n edge detection
OSPT0n bit
OSPE0n bit
Clear
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
214
Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
00000/10/100
TMC0n3 TMC0n2 TMC0n1 OVF0n
01: Free running timer mode
10: Clear and start mode by
valid edge of TI00n pin.
(b) Capture/compare control register 0n (CRC0n)
00000000
CRC0n2 CRC0n1 CRC0n0
CR00n used as
compare register
CR01n used as
compare register
(c) 16-bit timer output control register 0n (TOC0n)
0 0/1 1 1 0/1
LVR0nLVS0nTOC0n4OSPE0nOSPT0n TOC0n1 TOE0n
Enables TO0n pin output
Inverts TO0n output on
match between TM0n
and CR00n/CR01n.
Specifies initial value of
TO0n pin output
Enables one-shot pulse
output
Software trigger is generated
by writing 1 to this bit
(operation is not affected
even if 0 is written to it).
0/1 1 1
(d) Prescaler mode register 0n (PRM0n)
00000
3 2 PRM0n1 PRM0n0ES1n1 ES1n0 ES0n1 ES0n0
Selects count clock
0 0/1 0/1
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 215
Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (2/2)
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
This register is used as a compare register when a one-shot pulse is output. When the value of TM0n
matches that of CR00n, an interrupt signal (INTTM00n) is generated and the output level of the TO0n pin is
inverted.
(g) 16-bit capture/compare register 01n (CR01n)
This register is used as a compare register when a one-shot pulse is output. When the value of TM0n
matches that of CR01n, an interrupt signal (INTTM01n) is generated and the output level of the TO0n pin is
inverted.
Caution Do not set the same value to CR0n0 and CR0n1.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
216
Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (1/2)
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
One-shot pulse enable bit
(OSPEn)
One-shot pulse trigger bit
(OSPTn)
One-shot pulse trigger input
(TI00n pin)
Overflow plug
(OVF0n)
Compare register
(CR00n)
Compare match interrupt
(INTTM00n)
Compare register
(CR01n)
Compare match interrupt
(INTTM01n)
TO0n pin output
TO0n output control bits
(TOE0n, TOC0n4, TOC0n1)
N
M
N − M N − M
01 or 1000 00
NN N
M
MM
M + 1 M + 1
<1> <2> <2> <3>
TO0n output level is not
inverted because no one-
shot trigger is input.
• Time from when the one-shot pulse trigger is input until the one-shot pulse is output
= (M + 1) × Count clock cycle
• One-shot pulse output active level width
= (N − M) × Count clock cycle
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 217
Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (2/2)
TMC0n3, TMC0n2 bits =
01 or 10
Register initial setting
PRM0n register,
CRC0n register,
TOC0n register
Note
,
CR00n, CR01n registers,
port setting
Initial setting of these registers is performed
before setting the TMC0n3 and TMC0n2 bits.
Starts count operation
START
<1> Count operation start flow
<2> One-shot trigger input flow
TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped
by clearing the TMC0n3 and TMC0n2 bits to 00.
STOP
<3> Count operation stop flow
TOC0n.OSPT0n bit = 1
or edge input to TI00n pin
Write the same value to the bits other than the
OSTP0n bit.
Note Care must be exercised when setting TOC0n. For details, see 7.3 (3) 16-bit timer output control
register 0n (TOC0n).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
218
7.4.8 Pulse width measurement operation
TM0n can be used to measure the pulse width of the signal input to the TI00n and TI01n pins.
Measurement can be accomplished by operating the 16-bit timer/event counter 0n in the free-running timer mode
or by restarting the timer in synchronization with the signal input to the TI00n pin.
When an interrupt is generated, read the value of the valid capture register and measure the pulse width. Check
bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n). If it is set (to 1), clear it to 0 by software.
Figure 7-51. Block Diagram of Pulse Width Measurement (Free-Running Timer Mode)
Timer counter
(TM0n)
Capture register
(CR00n)
Capture
signal
Capture signal
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
Capture register
(CR01n)
Operable bits
TMC0n3, TMC0n2
Count clock
Edge
detection
TI00n pin
Edge
detection
TI01n pin
Selector
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Figure 7-52. Block Diagram of Pulse Width Measurement
(Clear & Start Mode Entered by TI00n Pin Valid Edge Input)
Timer counter
(TM0n)
Capture register
(CR00n)
Capture
signal
Capture signal
Interrupt signal
(INTTM01n)
Interrupt signal
(INTTM00n)
Capture register
(CR01n)
Operable bits
TMC0n3, TMC0n2
Count clock
Edge
detection
TI00n pin
Edge
detection
TI01n pin
Clear
Selector
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 219
A pulse width can be measured in the following three ways.
• Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer mode)
• Measuring the pulse width by using one input signal of the TI00n pin (free-running timer mode)
• Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the TI00n pin
valid edge input)
Remarks 1. For the setting of the I/O pins, see 7.3 (5) Port mode register 0 (PM0).
2. For how to enable the INTTM00n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
3. n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
(1) Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer
mode)
Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). When the valid edge of the TI00n pin is detected,
the count value of TM0n is captured to CR01n. When the valid edge of the TI01n pin is detected, the count value
of TM0n is captured to CR00n. Specify detection of both the edges of the TI00n and TI01n pins.
By this measurement method, the previous count value is subtracted from the count value captured by the edge
of each input signal. Therefore, save the previously captured value to a separate register in advance.
If an overflow occurs, the value becomes negative if the previously captured value is simply subtracted from the
current captured value and, therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1).
If this happens, ignore CY and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of
16-bit timer mode control register 0n (TMC0n) to 0.
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
220
Figure 7-53. Timing Example of Pulse Width Measurement (1)
• TMC0n = 04H, PRM0n = F0H, CRC0n = 05H
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
Capture trigger input
(TI01n)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Overflow flag
(OVF0n)
01
M
ABCDE
NSPQ
00
0 write clear 0 write clear 0 write clear 0 write clear
0000H ABC
DE
0000H MN S
PQ
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 221
(2) Measuring the pulse width by using one input signal of the TI00n pin (free-running mode)
Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). The count value of TM0n is captured to CR00n in
the phase reverse to the valid edge detected on the TI00n pin. When the valid edge of the TI00n pin is detected,
the count value of TM0n is captured to CR01n.
By this measurement method, values are stored in separate capture registers when a width from one edge to
another is measured. Therefore, the capture values do not have to be saved. By subtracting the value of one
capture register from that of another, a high-level width, low-level width, and cycle are calculated.
If an overflow occurs, the value becomes negative if one captured value is simply subtracted from another and,
therefore, a borrow occurs (bit 0 (CY) of the program status word (PSW) is set to 1). If this happens, ignore CY
and take the calculated value as the pulse width. In addition, clear bit 0 (OVF0n) of 16-bit timer mode control
register 0n (TMC0n) to 0.
Figure 7-54. Timing Example of Pulse Width Measurement (2)
• TMC0n = 04H, PRM0n = 10H, CRC0n = 07H
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI00n)
Capture register
(CR00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
Overflow flag
(OVF0n)
Capture trigger input
(TI01n)
Compare match interrupt
(INTTM00n)
01
M
ABCDE
NSPQ
00
0 write clear 0 write clear 0 write clear 0 write clear
0000H
L
L
ABC
DE
0000H MN S
PQ
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
222
(3) Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the
TI00n pin valid edge input)
Set the clear & start mode entered by the TI00n pin valid edge (TMC0n3 and TMC0n2 = 10). The count value of
TM0n is captured to CR00n in the phase reverse to the valid edge of the TI00n pin, and the count value of TM0n
is captured to CR01n and TM0n is cleared (0000H) when the valid edge of the TI00n pin is detected. Therefore,
a cycle is stored in CR01n if TM0n does not overflow.
If an overflow occurs, take the value that results from adding 10000H to the value stored in CR01n as a cycle.
Clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0.
Figure 7-55. Timing Example of Pulse Width Measurement (3)
• TMC0n = 08H, PRM0n = 10H, CRC0n = 07H
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n)
Capture register
(CR00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
Overflow flag
(OVF0n)
Capture trigger input
(TI01n)
Capture interrupt
(INTTM00n)
10
<1>
<2> <3> <3> <3> <3><2> <2> <2>
<1> <1> <1>
M
A
BCD
N
S
PQ
00 00
0 write clear
0000H
L
L
ABC
D
0000H MN S
PQ
<1> Pulse cycle = (10000H × Number of times OVF0n bit is set to 1 + Captured value of CR01n) ×
Count clock cycle
<2> High-level pulse width = (10000H × Number of times OVF0n bit is set to 1 + Captured value of CR00n) ×
Count clock cycle
<3> Low-level pulse width = (Pulse cycle − High-level pulse width)
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 223
Figure 7-56. Example of Register Settings for Pulse Width Measurement (1/2)
(a) 16-bit timer mode control register 0n (TMC0n)
00000/10/100
TMC0n3 TMC0n2 TMC0n1 OVF0n
01: Free running timer mode
10: Clear and start mode entered
by valid edge of TI00n pin.
(b) Capture/compare control register 0n (CRC0n)
0000010/11
CRC0n2 CRC0n1 CRC0n0
1: CR00n used as capture register
1: CR01n used as capture register
0: TI01n pin is used as capture
trigger of CR00n.
1: Reverse phase of TI00n pin is
used as capture trigger of CR00n.
(c) 16-bit timer output control register 0n (TOC0n)
00000
LVR0nLVS0nTOC0n4OSPE0nOSPT0n TOC0n1 TOE0n
000
(d) Prescaler mode register 0n (PRM0n)
0/1 0/1 0/1 0/1 0
3 2 PRM0n1 PRM0n0ES1n1 ES1n0 ES0n1 ES0n0
Selects count clock
(setting valid edge of TI00n is prohibited)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
(setting when CRC0n1 = 1 is prohibited)
00: Falling edge detection
01: Rising edge detection
10: Setting prohibited
11: Both edges detection
0 0/1 0/1
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
224
Figure 7-56. Example of Register Settings for Pulse Width Measurement (2/2)
(e) 16-bit timer counter 0n (TM0n)
By reading TM0n, the count value can be read.
(f) 16-bit capture/compare register 00n (CR00n)
This register is used as a capture register. Either the TI00n or TI01n pin is selected as a capture trigger.
When a specified edge of the capture trigger is detected, the count value of TM0n is stored in CR00n.
(g) 16-bit capture/compare register 01n (CR01n)
This register is used as a capture register. The signal input to the TI00n pin is used as a capture trigger.
When the capture trigger is detected, the count value of TM0n is stored in CR01n.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 225
Figure 7-57. Example of Software Processing for Pulse Width Measurement (1/2)
(a) Example of free-running timer mode
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture trigger input
(TI00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
Capture trigger input
(TI01n)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
01
D00
D00
D01
D01
D02
D02
D03
D03
D04
D04
D10
D10
D11
D11
D12
D12
D13
D13
00 00
0000H
0000H
<1> <2> <2> <2> <2> <2> <2> <2> <2> <2><3>
(b) Example of clear & start mode entered by TI00n pin valid edge
FFFFH
TM0n register
0000H
Operable bits
(TMC0n3, TMC0n2)
Capture & count clear input
(TI00n)
Capture register
(CR00n)
Capture interrupt
(INTTM00n)
Capture register
(CR01n)
Capture interrupt
(INTTM01n)
10
D0
L
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
00 00
0000H
0000H
<1> <2> <2> <2> <2> <2> <2> <2> <2> <3><2>
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
226
Figure 7-57. Example of Software Processing for Pulse Width Measurement (2/2)
<2> Capture trigger input flow
Edge detection of TI00n, TI01n pins
Calculated pulse width
from capture value
Stores count value to
CR00n, CR01n registers
Generates capture interrupt
Note
TMC0n3, TMC0n2 bits =
01 or 10
Register initial setting
PRM0n register,
CRC0n register,
port setting
Initial setting of these registers is performed
before setting the TMC0n3 and TMC0n2 bits.
Starts count operation
START
<1> Count operation start flow
TMC0n3, TMC0n2 bits = 00 The counter is initialized and counting is stopped
by clearing the TMC0n3 and TMC0n2 bits to 00.
STOP
<3> Count operation stop flow
Note The capture interrupt signal (INTTM00n) is not generated when the reverse-phase edge of the TI00n pin
input is selected to the valid edge of CR00n.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 227
7.5 Special Use of TM0n
7.5.1 Rewriting CR01n during TM0n operation
In principle, rewriting CR00n and CR01n of the 78K0/LG2 when they are used as compare registers is prohibited
while TM0n is operating (TMC0n3 and TMC0n2 = other than 00).
However, the value of CR01n can be changed, even while TM0n is operating, using the following procedure if
CR01n is used for PPG output and the duty factor is changed (change the value of CR01n immediately after its value
matches the value of TM0n. If the value of CR01n is changed immediately before its value matches TM0n, an
unexpected operation may be performed).
Procedure for changing value of CR01n
<1> Disable interrupt INTTM01n (TMMK01n = 1).
<2> Disable reversal of the timer output when the value of TM0n matches that of CR01n (TOC0n4 = 0).
<3> Change the value of CR01n.
<4> Wait for one cycle of the count clock of TM0n.
<5> Enable reversal of the timer output when the value of TM0n matches that of CR01n (TOC0n4 = 1).
<6> Clear the interrupt flag of INTTM01n (TMIF01n = 0) to 0.
<7> Enable interrupt INTTM01n (TMMK01n = 0).
Remark For TMIF01n and TMMK01n, see CHAPTER 20 INTERRUPT FUNCTIONS.
7.5.2 Setting LVS0n and LVR0n
(1) Usage of LVS0n and LVR0n
LVS0n and LVR0n are used to set the default value of the TO0n pin output and to invert the timer output without
enabling the timer operation (TMC0n3 and TMC0n2 = 00). Clear LVS0n and LVR0n to 00 (default value: low-
level output) when software control is unnecessary.
LVS0n LVR0n Timer Output Status
0 0 Not changed (low-level output)
0 1 Cleared (low-level output)
1 0 Set (high-level output)
1 1 Setting prohibited
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
228
(2) Setting LVS0n and LVR0n
Set LVS0n and LVR0n using the following procedure.
Figure 7-58. Example of Flow for Setting LVS0n and LVR0n Bits
Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits
Setting TOC0n.TOE0n bit
Setting TOC0n.LVS0n, LVR0n bits
Setting TMC0n.TMC0n3, TMC0n2 bits <3> Enabling timer operation
<2> Setting of timer output F/F
<1> Setting of timer output operation
Caution Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above.
Step <2> can be performed after <1> and before <3>.
Figure 7-59. Timing Example of LVR0n and LVS0n
TOC0n.LVS0n bit
TOC0n.LVR0n bit
Operable bits
(TMC0n3, TMC0n2)
TO0n pin output
INTTM00n signal
<1>
00
<2> <1> <3> <4> <4> <4>
01, 10, or 11
<1> The TO0n pin output goes high when LVS0n and LVR0n = 10.
<2> The TO0n pin output goes low when LVS0n and LVR0n = 01 (the pin output remains unchanged from the
high level even if LVS0n and LVR0n are cleared to 00).
<3> The timer starts operating when TMC0n3 and TMC0n2 are set to 01, 10, or 11. Because LVS0n and
LVR0n were set to 10 before the operation was started, the TO0n pin output starts from the high level.
After the timer starts operating, setting LVS0n and LVR0n is prohibited until TMC0n3 and TMC0n2 = 00
(disabling the timer operation).
<4> The output level of the TO0n pin is inverted each time an interrupt signal (INTTM00n) is generated.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 229
7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01
(1) Restrictions for each channel of 16-bit timer/event counter 0n
Table 7-5 shows the restrictions for each channel.
Table 7-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n
Operation Restriction
As interval timer
As square wave output
As external event counter
−
As clear & start mode entered by
TI00n pin valid edge input
Using timer output (TO0n) is prohibited when detection of the valid edge of the TI01n pin is
used.
TOC0n = 00H
As free-running timer −
As PPG output 0000H ≤ CP01n < CR00n ≤ FFFFH
As one-shot pulse output Setting the same value to CR00n and CP01n is prohibited.
As pulse width measurement Using timer output (TO0n) is prohibited (TOC0n = 00H)
(2) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because counting TM0n is started asynchronously to the count pulse.
Figure 7-60. Start Timing of TM0n Count
0000H
Timer start
0001H 0002H 0003H 0004H
Count pulse
TM0n count value
(3) Setting of CR00n and CR01n (clear & start mode entered upon a match between TM0n and CR00n)
Set a value other than 0000H to CR00n and CR01n (TM0n cannot count one pulse when it is used as an external
event counter).
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
230
(4) Timing of holding data by capture register
(a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while
CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not
guaranteed. At this time, an interrupt signal (INTTM00n/INTTM01n) is generated when the valid edge of the
TI00n/TI01n pin is detected (the interrupt signal is not generated when the reverse-phase edge of the TI00n
pin is detected).
When the count value is captured because the valid edge of the TI00n/TI01n pin was detected, read the
value of CR00n/CR01n after INTTM00n/INTTM01n is generated.
Figure 7-61. Timing of Holding Data by Capture Register
N N + 1 N + 2
X N + 1
M M + 1 M + 2
Count pulse
TM0n count value
Edge input
INTTM01n
Value captured to CR01n
Capture read signal
Capture operation is performed
but read value is not guaranteed.
Capture operation
(b) The values of CR00n and CR01n are not guaranteed after 16-bit timer/event counter 0n stops.
(5) Setting valid edge
Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3 and TMC0n2 = 00). Set the
valid edge by using ES0n0 and ES0n1.
(6) Re-triggering one-shot pulse
Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode.
Be sure to input the next trigger after the current active level is output.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD 231
(7) Operation of OVF0n flag
(a) Setting OVF0n flag (1)
The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows.
Select the clear & start mode entered upon a match between TM0n and CR00n.
↓
Set CR00n to FFFFH.
↓
When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H
Figure 7-62. Operation Timing of OVF0n Flag
FFFEH
FFFFH
FFFFH 0000H 0001H
Count pulse
TM0n
INTTM00n
OVF0n
CR00n
(b) Clearing OVF0n flag
Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next count clock is counted
(before the value of TM0n becomes 0001H), it is set to 1 again and clearing is invalid.
(8) One-shot pulse output
One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the
TI00n pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match
between TM0n and CR00n.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17473EJ2V0UD
232
(9) Capture operation
(a) When valid edge of TI00n is specified as count clock
When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified
as a trigger does not operate correctly.
(b) Pulse width to accurately capture value by signals input to TI01n and TI00n pins
To accurately capture the count value, the pulse input to the TI00n and TI01n pins as a capture trigger must
be wider than two count clocks selected by PRM0n (see Figure 7-9).
(c) Generation of interrupt signal
The capture operation is performed at the falling edge of the count clock but the interrupt signals (INTTM00n
and INTTM01n) are generated at the rising edge of the next count clock (see Figure 7-9).
(d) Note when CRC0n1 (bit 1 of capture/compare control register 0n (CRC0n)) is set to 1
When the count value of the TM0n register is captured to the CR00n register in the phase reverse to the
signal input to the TI00n pin, the interrupt signal (INTTM00n) is not generated after the count value is
captured. If the valid edge is detected on the TI01n pin during this operation, the capture operation is not
performed but the INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n signal
when the external interrupt is not used.
(10) Edge detection
(a) Specifying valid edge after reset
If the operation of the 16-bit timer/event counter 0n is enabled after reset and while the TI00n or TI01n pin is
at high level and when the rising edge or both the edges are specified as the valid edge of the TI00n or TI01n
pin, then the high level of the TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n or
TI01n pin is pulled up. However, the rising edge is not detected when the operation is once stopped and
then enabled again.
(b) Sampling clock for eliminating noise
The sampling clock for eliminating noise differs depending on whether the valid edge of TI00n is used as the
count clock or capture trigger. In the former case, the sampling clock is fixed to fPRS. In the latter, the count
clock selected by PRM0n is used for sampling.
When the signal input to the TI00n pin is sampled and the valid level is detected two times in a row, the valid
edge is detected. Therefore, noise having a short pulse width can be eliminated (see Figure 7-9).
(11) Timer operation
The signal input to the TI00n/TI01n pin is not acknowledged while the timer is stopped, regardless of the
operation mode of the CPU.
Remarks 1. fPRS: Peripheral hardware clock frequency
2. n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
User’s Manual U17473EJ2V0UD 233
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
8.1 Functions of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 have the following functions.
• Interval timer
• External event counter
• Square-wave output
• PWM output
8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 include the following hardware.
Table 8-1. Configuration of 8-Bit Timer/Event Counters 50 and 51
Item Configuration
Timer register 8-bit timer counter 5n (TM5n)
Register 8-bit timer compare register 5n (CR5n)
Timer input TI5n
Timer output TO5n
Control registers Timer clock selection register 5n (TCL5n)
8-bit timer mode control register 5n (TMC5n)
Port mode register 1 (PM1) or port mode register 3 (PM3)
Port register 1 (P1) or port register 3 (P3)
Figures 8-1 and 8-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD
234
Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
8-bit timer compare
register 50 (CR50)
TI50/TO50/P17
fPRS/213
fPRS
fPRS/2
Match
Mask circuit
OVF
3
Clear
TCL502 TCL501 TCL500
Timer clock selection
register 50 (TCL50)
Internal bus
TCE50
TMC506
LVS50 LVR50
TMC501
TOE50
Invert
level
8-bit timer mode control
register 50 (TMC50)
S
R
SQ
R
INV
Selector
To TMH0
To UART0
To UART6
INTTM50
TO50/TI50/
P17
Note 1
Note 2
Selector
8-bit timer
counter 50 (TM50)
Selector
Output latch
(P17)
PM17
fPRS/22
fPRS/28
fPRS/26
Figure 8-2. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
8-bit timer compare
register 51 (CR51)
TI51/TO51/
P33/INTP4
f
PRS
/2
12
f
PRS
f
PRS
/2
Match
Mask circuit
OVF
3
Clear
TCL512 TCL511 TCL510
Timer clock selection
register 51 (TCL51)
Internal bus
TCE51
TMC516
LVS51 LVR51
TMC511
TOE51
Invert
level
8-bit timer mode control
register 51 (TMC51)
S
R
SQ
R
INV
Selector INTTM51
TO51/TI51/
P33/INTP4
Note 1
Note 2
Selector
8-bit timer
counter 51 (TM51)
Selector
Output latch
(P33)
PM33
f
PRS
/2
6
f
PRS
/2
4
f
PRS
/2
8
Notes 1. Timer output F/F
2. PWM output F/F
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD 235
(1) 8-bit timer counter 5n (TM5n)
TM5n is an 8-bit register that counts the count pulses and is read-only.
The counter is incremented in synchronization with the rising edge of the count clock.
Figure 8-3. Format of 8-Bit Timer Counter 5n (TM5n)
Symbol
TM5n
(n = 0, 1)
Address: FF16H (TM50), FF1FH (TM51) After reset: 00H R
In the following situations, the count value is cleared to 00H.
<1> Reset signal generation
<2> When TCE5n is cleared
<3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and
CR5n.
(2) 8-bit timer compare register 5n (CR5n)
CR5n can be read and written by an 8-bit memory manipulation instruction.
Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count
value, and an interrupt request (INTTM5n) is generated if they match.
In the PWM mode, the TO5n pin becomes inactive when the values of TM5n and CR5n match, but no interrupt is
generated.
The value of CR5n can be set within 00H to FFH.
Reset signal generation sets CR5n to 00H.
Figure 8-4. Format of 8-Bit Timer Compare Register 5n (CR5n)
Symbol
CR5n
(n = 0, 1)
Address: FF17H (CR50), FF41H (CR51) After reset: 00H R/W
Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do
not write other values to CR5n during operation.
2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock
selected by TCL5n) or more.
Remark n = 0, 1
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD
236
8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
The following four registers are used to control 8-bit timer/event counters 50 and 51.
• Timer clock selection register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Port mode register 1 (PM1) or port mode register 3 (PM3)
• Port register 1 (P1) or port register 3 (P3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets TCL5n to 00H.
Remark n = 0, 1
Figure 8-5. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TCL50 0 0 0 0 0 TCL502 TCL501 TCL500
Count clock selection TCL502 TCL501 TCL500
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
0 0 0 TI50 pin falling edge
0 0 1 TI50 pin rising edge
0 1 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz
0 1 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz
1 0 0 fPRS/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz
1 0 1 fPRS/26 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
1 1 0 fPRS/28 7.81 kHz 19.53 kHz 39.06 kHz 78.13 kHz
1 1 1 fPRS/213 0.24 kHz 0.61 kHz 1.22 kHz 2.44 kHz
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark f
PRS: Peripheral hardware clock frequency
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD 237
Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51)
Address: FF8CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TCL51 0 0 0 0 0 TCL512 TCL511 TCL510
Count clock selection TCL512 TCL511 TCL510
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
0 0 0 TI51 pin falling edge
0 0 1 TI51 pin rising edge
0 1 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz
0 1 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz
1 0 0 fPRS/24 125 kHz 312.5 kHz 625 kHz 1.25 MHz
1 0 1 fPRS/26 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
1 1 0 fPRS/28 7.81 kHz 19.53 kHz 39.06 kHz 78.13 kHz
1 1 1 fPRS/212 0.49 kHz 1.22 kHz 2.44 kHz 4.88 kHz
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark f
PRS: Peripheral hardware clock frequency
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD
238
(2) 8-bit timer mode control register 5n (TMC5n)
TMC5n is a register that performs the following five types of settings.
<1> 8-bit timer counter 5n (TM5n) count operation control
<2> 8-bit timer counter 5n (TM5n) operating mode selection
<3> Timer output F/F (flip flop) status setting
<4> Active level selection in timer F/F control or PWM (free-running) mode.
<5> Timer output control
TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark n = 0, 1
Figure 8-7. Format of 8-Bit Timer Mode Control Register 50 (TMC50)
Address: FF6BH After reset: 00H R/WNote
Symbol <7> 6 5 4 <3> <2> 1 <0>
TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50
TCE50 TM50 count operation control
0 After clearing to 0, count operation disabled (counter stopped)
1 Count operation start
TMC506 TM50 operating mode selection
0 Mode in which clear & start occurs on a match between TM50 and CR50
1 PWM (free-running) mode
LVS50 LVR50 Timer output F/F status setting
0 0 No change
0 1 Timer output F/F clear (0) (default output value of TO50 pin: low level)
1 0 Timer output F/F set (1) (default output value of TO50 pin: high level)
1 1 Setting prohibited
In other modes (TMC506 = 0) In PWM mode (TMC506 = 1) TMC501
Timer F/F control Active level selection
0 Inversion operation disabled Active-high
1 Inversion operation enabled Active-low
TOE50 Timer output control
0 Output disabled (TM50 output is low level)
1 Output enabled
Note Bits 2 and 3 are write-only.
(Cautions and Remarks are listed on the next page.)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD 239
Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51)
Address: FF43H After reset: 00H R/WNote
Symbol <7> 6 5 4 <3> <2> 1 <0>
TMC51 TCE51 TMC516 0 0 LVS51 LVR51 TMC511 TOE51
TCE51 TM51 count operation control
0 After clearing to 0, count operation disabled (counter stopped)
1 Count operation start
TMC516 TM51 operating mode selection
0 Mode in which clear & start occurs on a match between TM51 and CR51
1 PWM (free-running) mode
LVS51 LVR51 Timer output F/F status setting
0 0 No change
0 1 Timer output F/F clear (0) (default output value of TO51 pin: low)
1 0 Timer output F/F set (1) (default output value of TO51 pin: high)
1 1 Setting prohibited
In other modes (TMC516 = 0) In PWM mode (TMC516 = 1) TMC511
Timer F/F control Active level selection
0 Inversion operation disabled Active-high
1 Inversion operation enabled Active-low
TOE51 Timer output control
0 Output disabled (TM51 output is low level)
1 Output enabled
Note Bits 2 and 3 are write-only.
Cautions 1. The settings of LVS5n and LVR5n are valid in other than PWM mode.
2. Perform <1> to <4> below in the following order, not at the same time.
<1> Set TMC5n1, TMC5n6: Operation mode setting
<2> Set TOE5n to enable output: Timer output enable
<3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting
<4> Set TCE5n
3. When TCE5n = 1, setting the other bits of TMC5n is prohibited.
Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE5n to 0.
2. If LVS5n and LVR5n are read, the value is 0.
3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin
regardless of the value of TCE5n.
4. n = 0, 1
<R>
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD
240
(3) Port mode registers 1 and 3 (PM1, PM3)
These registers set port 1 and 3 input/output in 1-bit units.
When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the
output latches of P17 and P33 to 0.
When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer input, set PM17 and PM33 to 1. The
output latches of P17 and P33 at this time may be 0 or 1.
PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 8-9. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Figure 8-10. Format of Port Mode Register 3 (PM3)
Address: FF23H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM3 1 1 1 1 PM33 PM32 PM31 PM30
PM3n P3n pin I/O mode selection (n = 0 to 3)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD 241
8.4 Operations of 8-Bit Timer/Event Counters 50 and 51
8.4.1 Operation as interval timer
8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals
of the count value preset to 8-bit timer compare register 5n (CR5n).
When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the
TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n
(TCL5n).
Setting
<1> Set the registers.
• TCL5n: Select the count clock.
• CR5n: Compare value
• TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n
and CR5n.
(TMC5n = 0000×××0B × = Don’t care)
<2> After TCE5n = 1 is set, the count operation starts.
<3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> INTTM5n is generated repeatedly at the same interval.
Set TCE5n to 0 to stop the count operation.
Caution Do not write other values to CR5n during operation.
Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
2. n = 0, 1
Figure 8-11. Interval Timer Operation Timing (1/2)
(a) Basic operation
t
Count clock
TM5n count value
CR5n
TCE5n
INTTM5n
Count start Clear Clear
00H 01H N 00H 01H N 00H 01H N
NNNN
Interrupt acknowledged Interrupt acknowledged
Interval timeInterval time
Remark Interval time = (N + 1) × t
N = 01H to FFH
n = 0, 1
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD
242
Figure 8-11. Interval Timer Operation Timing (2/2)
(b) When CR5n = 00H
t
Interval time
Count clock
TM5n
CR5n
TCE5n
INTTM5n
00H 00H 00H
00H 00H
(c) When CR5n = FFH
t
Count clock
TM5n
CR5n
TCE5n
INTTM5n
01H FEH FFH 00H FEH FFH 00H
FFHFFHFFH
Interval time
Interrupt
acknowledged
Interrupt acknowledged
Remark n = 0, 1
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD 243
8.4.2 Operation as external event counter
The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer
counter 5n (TM5n).
TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input.
Either the rising or falling edge can be selected.
When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0
and an interrupt request signal (INTTM5n) is generated.
Whenever the TM5n value matches the value of CR5n, INTTM5n is generated.
Setting
<1> Set each register.
• Set the port mode register (PM17 or PM33)Note to 1.
• TCL5n: Select TI5n pin input edge.
TI5n pin falling edge → TCL5n = 00H
TI5n pin rising edge → TCL5n = 01H
• CR5n: Compare value
• TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and
CR5n, disable the timer F/F inversion operation, disable timer output.
(TMC5n = 00000000B)
<2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted.
<3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match.
Note 8-bit timer/event counter 50: PM17
8-bit timer/event counter 51: PM33
Remark For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
Figure 8-12. External Event Counter Operation Timing (with Rising Edge Specified)
TI5n
TM5n count value
CR5n
INTTM5n
00H 01H 02H 03H 04H 05H N − 1 N 00H 01H 02H 03H
N
Count start
Remark N = 00H to FFH
n = 0, 1
<R>
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD
244
8.4.3 Square-wave output operation
A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer
compare register 5n (CR5n).
The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0
(TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected
frequency to be output (duty = 50%).
Setting
<1> Set each register.
• Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0.
• TCL5n: Select the count clock.
• CR5n: Compare value
• TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and
CR5n.
LVS5n LVR5n Timer Output F/F Status Setting
1 0 Timer output F/F clear (0) (default output value of TO50 pin: low level)
0 1 Timer output F/F set (1) (default output value of TO5n pin: high level)
Timer output enabled
(TMC5n = 00001011B or 00000111B)
<2> After TCE5n = 1 is set, the count operation starts.
<3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is
cleared to 00H.
<4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from
TO5n.
The frequency is as follows.
• Frequency = 1/2t (N + 1)
(N: 00H to FFH)
Note 8-bit timer/event counter 50: P17, PM17
8-bit timer/event counter 51: P33, PM33
Caution Do not write other values to CR5n during operation.
Remarks 1. For how to enable the INTTM5n signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
2. n = 0, 1
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD 245
Figure 8-13. Square-Wave Output Operation Timing
Count clock
TM5n count value 00H 01H 02H N − 1N
N
00H N − 1 N 00H01H 02H
CR5n
TO5n
Note
t
Count start
Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control
register 5n (TMC5n).
8.4.4 PWM output operation
8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n
(TMC5n) is set to 1.
The duty pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n.
Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of
TMC5n.
The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n).
PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n.
Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by
TCL5n) or more.
Remark n = 0, 1
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD
246
(1) PWM output basic operation
Setting
<1> Set each register.
• Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0.
• TCL5n: Select the count clock.
• CR5n: Compare value
• TMC5n: Stop the count operation, select PWM mode.
The timer output F/F is not changed.
TMC5n1 Active Level Selection
0 Active-high
1 Active-low
Timer output enabled
(TMC5n = 01000001B or 01000011B)
<2> The count operation starts when TCE5n = 1.
Clear TCE5n to 0 to stop the count operation.
Note 8-bit timer/event counter 50: P17, PM17
8-bit timer/event counter 51: P33, PM33
PWM output operation
<1> PWM output (output from TO5n) outputs an inactive level until an overflow occurs.
<2> When an overflow occurs, the active level is output. The active level is output until CR5n matches the count
value of 8-bit timer counter 5n (TM5n).
<3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again.
<4> Operations <2> and <3> are repeated until the count operation stops.
<5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive.
For details of timing, see Figures 8-14 and 8-15.
The cycle, active-level width, and duty are as follows.
• Cycle = 28t
• Active-level width = Nt
• Duty = N/28
(N = 00H to FFH)
Remark n = 0, 1
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD 247
Figure 8-14. PWM Output Operation Timing
(a) Basic operation (active level = H)
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
00H 01H FFH 00H 01H 02H
N
N + 1
FFH 00H 01H 02H
M
00H
N
<2> Active level
<1> Inactive level <3> Inactive level <5> Inactive level
t
<2> Active level
(b) CR5n = 00H
Count clock
TM5n
CR5n
TCE5n
INTTM5n
01H00H FFH 00H 01H 02H
00H
FFH 00H 01H 02H
M
00H
TO5n L (Inactive level)
t
(c) CR5n = FFH
TM5n
CR5n
TCE5n
INTTM5n
TO5n
01H00H FFH 00H 01H 02H
FFH
<1> Inactive level <2> Active level
FFH 00H 01H 02H
M
00H
<3> Inactive level
<2> Active level<5> Inactive level
t
Remarks 1. <1> to <3> and <5> in Figure 8-14 (a) correspond to <1> to <3> and <5> in PWM output operation in
8.4.4 (1) PWM output basic operation.
2. n = 0, 1
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD
248
(2) Operation with CR5n changed
Figure 8-15. Timing of Operation with CR5n Changed
(a) CR5n value is changed from N to M before clock rising edge of FFH
→ Value is transferred to CR5n at overflow immediately after change.
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
<1> CR5n change (N → M)
N
N + 1 N + 2
FFH 00H 01H
M
M + 1 M + 2
FFH 00H 01H 02H
M
M + 1 M + 2
N
02H
M
H
<2>
t
(b) CR5n value is changed from N to M after clock rising edge of FFH
→ Value is transferred to CR5n at second overflow.
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
N
N + 1 N + 2
FFH 00H 01H
N
N + 1 N + 2
FFH 00H 01H 02H
N
02H
N
H
M
M
M + 1 M + 2
<1> CR5n change (N → M) <2>
t
Caution When reading from CR5n between <1> and <2> in Figure 8-15, the value read differs from the
actual value (read value: M, actual value of CR5n: N).
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
User’s Manual U17473EJ2V0UD 249
8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51
(1) Timer start error
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Figure 8-16. 8-Bit Timer Counter 5n Start Timing
Count clock
TM5n count value 00H 01H 02H 03H 04H
Timer start
Remark n = 0, 1
User’s Manual U17473EJ2V0UD
250
CHAPTER 9 8-BIT TIMERS H0 AND H1
9.1 Functions of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 have the following functions.
• Interval timer
• Square-wave output
• PWM output
• Carrier generator (8-bit timer H1 only)
9.2 Configuration of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 include the following hardware.
Table 9-1. Configuration of 8-Bit Timers H0 and H1
Item Configuration
Timer register 8-bit timer counter Hn
Registers 8-bit timer H compare register 0n (CMP0n)
8-bit timer H compare register 1n (CMP1n)
Timer output TOHn, output controller
Control registers 8-bit timer H mode register n (TMHMDn)
8-bit timer H carrier control register 1 (TMCYC1)Note
Port mode register 1 (PM1)
Port register 1 (P1)
Note 8-bit timer H1 only
Remark n = 0, 1
Figures 9-1 and 9-2 show the block diagrams.
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 251
Figure 9-1. Block Diagram of 8-Bit Timer H0
TMHE0
CKS02
CKS01
CKS00
TMMD01 TMMD00
TOLEV0
TOEN0
TOH0/P15
INTTMH0
f
PRS
f
PRS
/2
f
PRS
/2
2
f
PRS
/2
6
f
PRS
/2
10
1
0
F/F
R
32
PM15
Match
Internal bus
8-bit timer H mode register 0
(TMHMD0)
8-bit timer H
compare register
10 (CMP10)
Decoder
Selector
Interrupt
generator
Output
controller
Level
inversion
PWM mode signal
Timer H enable signal
Clear
8-bit timer H
compare register
00 (CMP00)
Output latch
(P15)
8-bit timer/
event counter 50
output
Selector
8-bit timer
counter H0
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
252
Figure 9-2. Block Diagram of 8-Bit Timer H1
Match
Internal bus
TMHE1
CKS12
CKS11
CKS10
TMMD11 TMMD10
TOLEV1
TOEN1
8-bit timer H
compare
register 11
(CMP11)
Decoder
TOH1/
INTP5/
P16
8-bit timer H carrier
control register 1
(TMCYC1)
INTTMH1
INTTM51
Selector
f
PRS
f
PRS
/2
2
f
PRS
/2
4
f
PRS
/2
6
f
PRS
/2
12
f
RL
f
RL
/2
7
f
RL
/2
9
Interrupt
generator
Output
controller
Level
inversion
PM16
Output latch
(P16)
1
0
F/F
R
PWM mode signal
Carrier generator mode signal
Timer H enable signal
3 2
8-bit timer H
compare
register 01
(CMP01)
8-bit timer
counter H1
Clear
RMC1
NRZB1
NRZ1
Reload/
interrupt control
8-bit timer H mode
register 1 (TMHMD1)
Selector
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 253
(1) 8-bit timer H compare register 0n (CMP0n)
This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the
timer operation modes.
This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and,
when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of
TOHn.
Rewrite the value of CMP0n while the timer is stopped (TMHEn = 0).
A reset signal generation sets this register to 00H.
Figure 9-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n)
Symbol
CMP0n
(n = 0, 1)
Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H R/W
765432 1 0
Caution CMP0n cannot be rewritten during timer count operation. CMP0n can be refreshed (the same
value is written) during timer count operation.
(2) 8-bit timer H compare register 1n (CMP1n)
This register can be read or written by an 8-bit memory manipulation instruction. This register is used in the
PWM output mode and carrier generator mode.
In the PWM output mode, this register constantly compares the value set to CMP1n with the count value of the 8-
bit timer counter Hn and, when the two values match, inverts the output level of TOHn. No interrupt request
signal is generated.
In the carrier generator mode, the CMP1n register always compares the value set to CMP1n with the count value
of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn).
At the same time, the count value is cleared.
CMP1n can be refreshed (the same value is written) and rewritten during timer count operation.
If the value of CMP1n is rewritten while the timer is operating, the new value is latched and transferred to CMP1n
when the count value of the timer matches the old value of CMP1n, and then the value of CMP1n is changed to
the new value. If matching of the count value and the CMP1n value and writing a value to CMP1n conflict, the
value of CMP1n is not changed.
A reset signal generation sets this register to 00H.
Figure 9-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n)
Symbol
CMP1n
(n = 0, 1)
Address: FF19H (CMP10), FF1BH (CMP11) After reset: 00H R/W
765432 1 0
Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the
timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be
sure to set again even if setting the same value to CMP1n).
Remark n = 0, 1
<R>
<R>
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
254
9.3 Registers Controlling 8-Bit Timers H0 and H1
The following four registers are used to control 8-bit timers H0 and H1.
• 8-bit timer H mode register n (TMHMDn)
• 8-bit timer H carrier control register 1 (TMCYC1)Note
• Port mode register 1 (PM1)
• Port register 1 (P1)
Note 8-bit timer H1 only
(1) 8-bit timer H mode register n (TMHMDn)
This register controls the mode of timer H.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark n = 0, 1
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 255
Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
TMHE0
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMHE0
0
1
Timer operation enable
TMHMD0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0
Address: FF69H After reset: 00H R/W
f
PRS
f
PRS
/2
f
PRS
/2
2
f
PRS
/2
6
f
PRS
/2
10
TM50 output
Note
Setting prohibited
CKS02
0
0
0
0
1
1
CKS01
0
0
1
1
0
0
CKS00
0
1
0
1
0
1
f
PRS
=
2 MHz
2 MHz
1 MHz
500 kHz
31.25 kHz
1.95 kHz
Count clock selection
Other than above
Interval timer mode
PWM output mode
Setting prohibited
TMMD01
0
1
TMMD00
0
0
Timer operation mode
Low level
High level
TOLEV0
0
1
Timer output level control (in default mode)
Disables output
Enables output
TOEN0
0
1
Timer output control
Other than above
<7> 6543 2 <1> <0>
f
PRS
=
5 MHz
5 MHz
2.5 MHz
1.25 MHz
78.13 kHz
4.88 kHz
f
PRS
=
10 MHz
10 MHz
5 MHz
2.5 MHz
156.25 kHz
9.77 kHz
f
PRS
=
20 MHz
20 MHz
10 MHz
5 MHz
312.5 kHz
19.54 kHz
Note Note the following points when selecting the TM50 output as the count clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of the 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of the 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
256
Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be
refreshed (the same value is written).
2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when
starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped
(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
Remarks 1. f
PRS: Peripheral hardware clock frequency
2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50
<R>
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 257
Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
TMHE1
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMHE1
0
1
Timer operation enable
TMHMD1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
Address: FF6CH After reset: 00H R/W
Interval timer mode
Carrier generator mode
PWM output mode
Setting prohibited
TMMD11
0
0
1
1
TMMD10
0
1
0
1
Timer operation mode
Low level
High level
TOLEV1
0
1
Timer output level control (in default mode)
Disables output
Enables output
TOEN1
0
1
Timer output control
<7> 6543 2 <1> <0>
f
PRS
f
PRS
/2
2
f
PRS
/2
4
f
PRS
/2
6
f
PRS
/2
12
f
RL
/2
7
f
RL
/2
9
f
RL
CKS12
0
0
0
0
1
1
1
1
CKS11
0
0
1
1
0
0
1
1
CKS10
0
1
0
1
0
1
0
1
f
PRS
=
2 MHz
2 MHz
500 kHz
125 kHz
31.25 kHz
0.49 kHz
1.88 kHz (TYP.)
0.47 kHz (TYP.)
240 kHz (TYP.)
Count clock selection
f
PRS
=
5 MHz
5 MHz
1.25 MHz
312.5 kHz
78.13 kHz
1.22 kHz
f
PRS
=
10 MHz
10 MHz
2.5 MHz
625 kHz
156.25 kHz
2.44 kHz
f
PRS
=
20 MHz
20 MHz
5 MHz
1.25 MHz
312.5 kHz
4.88 kHz
Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be
refreshed (the same value is written).
2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare
register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count
operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to
CMP11).
3. When the carrier generator mode is used, set so that the count clock frequency of TMH1
becomes more than 6 times the count clock frequency of TM51.
Remarks 1. f
PRS: Peripheral hardware clock frequency
2. fRL: Internal low-speed oscillation clock frequency
<R>
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
258
(2) 8-bit timer H carrier control register 1 (TMCYC1)
This register controls the remote control output and carrier pulse output status of 8-bit timer H1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 9-7. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)
0TMCYC1 0 0 0 0 RMC1 NRZB1 NRZ1
Address: FF6DH After reset: 00H R/W
Note
Low-level output
High-level output at rising edge of INTTM5 signal input
Low-level output
Carrier pulse output at rising edge of INTTM5 signal input
RMC1
0
0
1
1
NRZB1
0
1
0
1
Remote control output
Carrier output disabled status (low-level status)
Carrier output enabled status
(RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status)
NRZ1
0
1
Carrier pulse output status flag
<0>
Note Bit 0 is read-only.
Caution Do not rewrite RMC1 when TMHE = 1. However, TMCYC1 can be refreshed (the same value is
written).
(3) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P15/TOH0 and P16/TOH1/INTP5 pins for timer output, clear PM15 and PM16 and the output
latches of P15 and P16 to 0.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 9-8. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
<R>
<R>
<R>
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 259
9.4 Operation of 8-Bit Timers H0 and H1
9.4.1 Operation as interval timer/square-wave output
When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn)
is generated and the 8-bit timer counter Hn is cleared to 00H.
Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of the 8-bit timer counter Hn and
the CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.
By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%)
is output from TOHn.
Setting
<1> Set each register.
Figure 9-9. Register Setting During Interval Timer/Square-Wave Output Operation
(i) Setting timer H mode register n (TMHMDn)
0 0/1 0/1 0/1 0 0 0/1 0/1
TMMDn0 TOLEVn TOENnCKSn1CKSn2TMHEn
TMHMDn
CKSn0 TMMDn1
Timer output setting
Default setting of timer output level
Interval timer mode setting
Count clock (f
CNT
) selection
Count operation stopped
(ii) CMP0n register setting
The interval time is as follows if N is set as a comparison value.
• Interval time = (N +1)/fCNT
<2> Count operation starts when TMHEn = 1.
<3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is
generated and the 8-bit timer counter Hn is cleared to 00H.
<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, clear
TMHEn to 0.
Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1).
2. For how to enable the INTTMHn signal interrupt, see CHAPTER 20 INTERRUPT FUNCTIONS.
3. n = 0, 1
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
260
Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2)
(a) Basic operation (Operation When 01H ≤ CMP0n ≤ FEH)
00H
Count clock
Count start
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
01H N
Clear
Interval time
Clear
N
00H 01H N 00H 01H 00H
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
<3><1>
<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
<2> When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer
counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at
the rising edge of the count clock.
<3> If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to
the default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level
is maintained.
Remark n = 0, 1
01H ≤ N ≤ FEH
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 261
Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2)
(b) Operation when CMP0n = FFH
00H
Count clock
Count start
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
01H FEH
Clear
Clear
FFH 00H FEH FFH 00H
FFH
Interval time
(c) Operation when CMP0n = 00H
00H
00H
Count clock
Count start
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
Interval time
Remark n = 0, 1
<R>
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
262
9.4.2 Operation as PWM output
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n
register during timer operation is prohibited.
The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n
register during timer operation is possible.
The operation in PWM output mode is as follows.
The TOHn output level is inverted and the 8-bit timer counter Hn is cleared to 0 when the 8-bit timer counter Hn
and the CMP0n register match after the timer count is started. The TOHn output level is inverted when the 8-bit timer
counter Hn and the CMP1n register match.
Setting
<1> Set each register.
Figure 9-11. Register Setting in PWM Output Mode
(i) Setting timer H mode register n (TMHMDn)
0 0/1 0/1 0/1 1 0 0/1 1
TMMDn0 TOLEVn TOENnCKSn1CKSn2TMHEn
TMHMDn
CKSn0 TMMDn1
Timer output enabled
Default setting of timer output level
PWM output mode selection
Count clock (f
CNT
) selection
Count operation stopped
(ii) Setting CMP0n register
• Compare value (N): Cycle setting
(iii) Setting CMP1n register
• Compare value (M): Duty setting
Remarks 1. n = 0, 1
2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is
cleared, an interrupt request signal (INTTMHn) is generated, and TOHn output is inverted. At the same time,
the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to
the CMP1n register.
<4> When the 8-bit timer counter Hn and the CMP1n register match, TOHn output is inverted and the compare
register to be compared with the 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n
register. At this time, the 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 263
<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.
<6> To stop the count operation, set TMHEn = 0.
If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count
clock frequency is fCNT, the PWM pulse output cycle and duty are as follows.
• PWM pulse output cycle = (N + 1)/fCNT
• Duty = (M + 1)/(N + 1)
Cautions 1. The set value of the CMP1n register can be changed while the timer counter is operating.
However, this takes a duration of three operating clocks (signal selected by the CKSn2 to
CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed
until the value is transferred to the register.
2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after
the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the
same value to the CMP1n register).
3. Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are
within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1).
2. For details on how to enable the INTTMHn signal interrupt, see CHAPTER 20 INTERRUPT
FUNCTIONS.
3. n = 0, 1
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
264
Figure 9-12. Operation Timing in PWM Output Mode (1/4)
(a) Basic operation
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
TOHn
(TOLEVn = 1)
00H 01H A5H 00H 01H 02H A5H 00H A5H 00H01H 02H
CMP1n
A5H
01H
<1> <2> <3> <4>
<1> The count operation is enabled by setting the TMHEn bit to 1. Start the 8-bit timer counter Hn by masking
one count clock to count up. At this time, TOHn output remains the default.
<2> When the values of the 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is
inverted, the value of the 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.
<3> When the values of the 8-bit timer counter Hn and the CMP1n register match, the TOHn output level is
inverted. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output.
<4> Clearing the TMHEn bit to 0 during timer Hn operation sets the INTTMHn signal and TOHn output to the
default.
Remark n = 0, 1
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 265
Figure 9-12. Operation Timing in PWM Output Mode (2/4)
(b) Operation when CMP0n = FFH, CMP1n = 00H
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
00H 01H FFH 00H 01H 02H FFH 00H FFH 00H01H 02H
CMP1n
FFH
00H
(c) Operation when CMP0n = FFH, CMP1n = FEH
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H
CMP1n
FFH
FEH
Remark n = 0, 1
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
266
Figure 9-12. Operation Timing in PWM Output Mode (3/4)
(d) Operation when CMP0n = 01H, CMP1n = 00H
Count clock
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
01H
00H 01H 00H 01H 00H 00H 01H 00H 01H
CMP1n 00H
Remark n = 0, 1
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 267
Figure 9-12. Operation Timing in PWM Output Mode (4/4)
(e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H)
Count clock
8-bit timer
counter Hn
CMP01
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H
<1> <4>
<3>
<2>
CMP11
<6>
<5>
02H
A5H
03H02H (03H)
<2>’
80H
<1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count
clock to count up. At this time, the TOHn output remains default.
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of the 8-bit timer counter Hn and the CMP0n register match, the value of the 8-bit timer
counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output.
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
values of the 8-bit timer counter Hn and the CMP1n register before the change match, the value is
transferred to the CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
<5> When the values of the 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn
output level is inverted. The 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
<6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output default.
Remark n = 0, 1
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
268
9.4.3 Carrier generator operation (8-bit timer H1 only)
In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote
controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count).
The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51.
In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by the 8-bit timer/event counter
51, and the carrier pulse is output from the TOH1 output.
(1) Carrier generation
In carrier generator mode, the 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier
pulse waveform and the 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse
waveform.
Rewriting the CMP11 register during the 8-bit timer H1 operation is possible but rewriting the CMP01 register is
prohibited.
(2) Carrier output control
Carrier output is controlled by the interrupt request signal (INTTM51) of the 8-bit timer/event counter 51 and the
NRZB1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the
outputs is shown below.
RMC1 Bit NRZB1 Bit Output
0 0 Low-level output
0 1
High-level output at rising edge of
INTTM51 signal input
1 0 Low-level output
1 1
Carrier pulse output at rising edge of
INTTM51 signal input
<R>
<R>
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 269
To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register
have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written.
The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal.
The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to
the NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below.
Figure 9-13. Transfer Timing
8-bit timer H1
count clock
TMHE1
INTTM51
INTTM5H1
NRZ1
NRZB1
RMC1
1
1
10
00
<1>
<2>
<3>
<1> The INTTM51 signal is synchronized with the count clock of the 8-bit timer H1 and is output as the
INTTM5H1 signal.
<2> The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the
INTTM5H1 signal.
<3> Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the
INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to
count the next time to the CR51 register.
Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten,
or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.
2. When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is
generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a mode other
than the carrier generator mode, the timing of the interrupt generation differs.
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
270
Setting
<1> Set each register.
Figure 9-14. Register Setting in Carrier Generator Mode
(i) Setting 8-bit timer H mode register 1 (TMHMD1)
0 0/1 0/1 0/1 0
Timer output enabled
Default setting of timer output level
Carrier generator mode selection
Count clock (f
CNT
) selection
Count operation stopped
1 0/1 1
TMMD10 TOLEV1 TOEN1CKS11CKS12TMHE1
TMHMD1
CKS10 TMMD11
(ii) CMP01 register setting
• Compare value
(iii) CMP11 register setting
• Compare value
(iv) TMCYC1 register setting
• RMC1 = 1 ... Remote control output enable bit
• NRZB1 = 0/1 ... carrier output enable bit
(v) TCL51 and TMC51 register setting
• See 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51.
<2> When TMHE1 = 1, the 8-bit timer H1 starts counting.
<3> When TCE51 of the 8-bit timer mode control register 51 (TMC51) is set to 1, the 8-bit timer/event counter
51 starts counting.
<4> After the count operation is enabled, the first compare register to be compared is the CMP01 register.
When the count value of the 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1
signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be
compared with the 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register.
<5> When the count value of the 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1
signal is generated, the 8-bit timer counter H1 is cleared. At the same time, the compare register to be
compared with the 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register.
<6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated.
<7> The INTTM51 signal is synchronized with count clock of the 8-bit timer H1 and output as the INTTM5H1
signal. The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value
is transferred to the NRZ1 bit.
<8> Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the
INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag. Write data to
count the next time to the CR51 register.
<9> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin.
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 271
<10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation,
clear TMHE1 to 0.
If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count
clock frequency is fCNT, the carrier clock output cycle and duty are as follows.
• Carrier clock output cycle = (N + M + 2)/fCNT
• Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2)
Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1)
after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if
setting the same value to the CMP11 register).
2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count
clock frequency of TM51.
3. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
4. The set value of the CMP11 register can be changed while the timer counter is
operating. However, it takes the duration of three operating clocks (signal selected by
the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11
register has been changed until the value is transferred to the register.
5. Be sure to set the RMC1 bit before the count operation is started.
Remarks 1. For the setting of the output pin, see 9.3 (3) Port mode register 1 (PM1).
2. For how to enable the INTTMH1 signal interrupt, see CHAPTER 20 INTERRUPT
FUNCTIONS.
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
272
Figure 9-15. Carrier Generator Mode Operation Timing (1/3)
(a) Operation when CMP01 = N, CMP11 = N
CMP01
CMP11
TMHE11
INTTMH1
Carrier clock
00H N 00H N 00H N 00H N 00H N 00H N
N
N
8-bit timer 51
count clock
TM51 count value
CR5
1
TCE5
1
TOH
11
0
0
1
1
0
0
1
1
0
0
INTTM5n
1
NRZB
1
NRZ
1
Carrier clock
00H 01H K 00H 01H L 00H 01H M 00H 01H 00H 01HN
INTTM5H
1
<1><2>
<3> <4>
<5>
<6>
<7>
8-bit timer H1
count clock
8-bit timer counter
H1 count value
KLMN
<1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped.
<2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock
remains default.
<3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1
signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-
bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1
is cleared to 00H.
<4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared
to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is
generated.
<5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as
the INTTM5H1 signal.
<6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is
transferred to the NRZ1 bit.
<7> When NRZ1 = 0 is set, the TOH1 output becomes low level.
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD 273
Figure 9-15. Carrier Generator Mode Operation Timing (2/3)
(b) Operation when CMP01 = N, CMP11 = M
N
CMP01
CMP11
TMHE1
INTTMH1
Carrier clock
TM51 count value
00H N 00H 01H M 00H N 00H 01H M 00H 00HN
M
TCE51
TOH1
0
0
1
1
0
0
1
1
0
0
INTTM51
NRZB1
NRZ1
Carrier clock
00H 01H K 00H 01H L 00H 01H M 00H 01H 00H 01HN
INTTM5H1
<1><2>
<3> <4>
<5>
<6> <7>
8-bit timer 51
count clock
8-bit timer H1
count clock
8-bit timer counter
H1 count value
K
CR51
LMN
<1> When TMHE1 = 0 and TCE51 = 0, the 8-bit timer counter H1 operation is stopped.
<2> When TMHE1 = 1 is set, the 8-bit timer counter H1 starts a count operation. At that time, the carrier clock
remains default.
<3> When the count value of the 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1
signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-
bit timer counter H1 is switched from the CMP01 register to the CMP11 register. The 8-bit timer counter H1
is cleared to 00H.
<4> When the count value of the 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. The 8-bit timer counter H1 is cleared
to 00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50%
is generated.
<5> When the INTTM51 signal is generated, it is synchronized with the 8-bit timer H1 count clock and is output as
the INTTM5H1 signal.
<6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1.
<7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier
clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).
CHAPTER 9 8-BIT TIMERS H0 AND H1
User’s Manual U17473EJ2V0UD
274
Figure 9-15. Carrier Generator Mode Operation Timing (3/3)
(c) Operation when CMP11 is changed
8-bit timer H1
count clock
CMP01
TMHE1
INTTMH1
Carrier clock
00H 01H N 00H 01H 01H
M00H N 00H L 00H
<1>
<3>’
<4>
<3>
<2>
CMP11
<5>
M
N
L
M (L)
8-bit timer counter
H1 count value
<1> When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains
default.
<2> When the count value of the 8-bit timer counter H1 matches the value of the CMP01 register, the INTTMH1
signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H. At the same time, the
compare register whose value is to be compared with that of the 8-bit timer counter H1 is changed from the
CMP01 register to the CMP11 register.
<3> The CMP11 register is asynchronous to the count clock, and its value can be changed while the 8-bit timer
H1 is operating. The new value (L) to which the value of the register is to be changed is latched. When the
count value of the 8-bit timer counter H1 matches the value (M) of the CMP11 register before the change, the
CMP11 register is changed (<3>’).
However, it takes three count clocks or more since the value of the CMP11 register has been changed until
the value is transferred to the register. Even if a match signal is generated before the duration of three count
clocks elapses, the new value is not transferred to the register.
<4> When the count value of 8-bit timer counter H1 matches the value (M) of the CMP1 register before the
change, the INTTMH1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00H.
At the same time, the compare register whose value is to be compared with that of the 8-bit timer counter H1
is changed from the CMP11 register to the CMP01 register.
<5> The timing at which the count value of the 8-bit timer counter H1 and the CMP11 register value match again
is indicated by the value after the change (L).
User’s Manual U17473EJ2V0UD 275
CHAPTER 10 WATCH TIMER
10.1 Functions of Watch Timer
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch timer and the interval timer can be used simultaneously.
Figure 10-1 shows the watch timer block diagram.
Figure 10-1. Block Diagram of Watch Timer
f
PRS
/2
7
f
W
/2
4
f
W
/2
5
f
W
/2
6
f
W
/2
7
f
W
/2
8
f
W
/2
10
f
W
/2
11
f
W
/2
9
f
SUB
INTWT
INTWTI
WTM0WTM1WTM2WTM3WTM4WTM5WTM6WTM7
f
W
Clear
11-bit prescaler
Clear
5-bit counter
Watch timer operation
mode register (WTM)
Internal bus
Selector
Selector
Selector
Selector
f
WX
/2
4
f
WX
/2
5
f
WX
Remark f
PRS: Peripheral hardware clock frequency
f
SUB: Subsystem clock frequency
f
W: Watch timer clock frequency (fPRS/27 or fSUB)
fWX: fW or fW/29
CHAPTER 10 WATCH TIMER
User’s Manual U17473EJ2V0UD
276
(1) Watch timer
When the peripheral hardware clock or subsystem clock is used, interrupt request signals (INTWT) are
generated at preset intervals.
Table 10-1. Watch Timer Interrupt Time
Interrupt Time When Operated at
fSUB = 32.768 kHz
When Operated at
fPRS = 2 MHz
When Operated at
fPRS = 5 MHz
When Operated at
fPRS = 10 MHz
When Operated at
fPRS = 20 MHz
24/fW 488
μ
s 1.02 ms 410
μ
s 205
μ
s 102
μ
s
25/fW 977
μ
s 2.05 ms 819
μ
s 410
μ
s 205
μ
s
213/fW 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms
214/fW 0.5 s 1.05 s 0.419 s 0.210 s 0.105 s
Remark fPRS: Peripheral hardware clock frequency
f
SUB: Subsystem clock frequency
f
W: Watch timer clock frequency (fPRS/27 or fSUB)
(2) Interval timer
Interrupt request signals (INTWTI) are generated at preset time intervals.
Table 10-2. Interval Timer Interval Time
Interval Time When Operated at
fSUB = 32.768 kHz
When Operated at
fPRS = 2 MHz
When Operated at
fPRS = 5 MHz
When Operated at
fPRS = 10 MHz
When Operated at
fPRS = 20 MHz
24/fW 488
μ
s 1.02 ms 410
μ
s 205
μ
s 102
μ
s
25/fW 977
μ
s 2.05 ms 820
μ
s 410
μ
s 205
μ
s
26/fW 1.95 ms 4.10 ms 1.64 ms 820
μ
s 410
μ
s
27/fW 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820
μ
s
28/fW 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms
29/fW 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms
210/fW 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms
211/fW 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms
Remark fPRS: Peripheral hardware clock frequency
f
SUB: Subsystem clock frequency
f
W: Watch timer clock frequency (fPRS/27 or fSUB)
10.2 Configuration of Watch Timer
The watch timer includes the following hardware.
Table 10-3. Watch Timer Configuration
Item Configuration
Counter 5 bits × 1
Prescaler 11 bits × 1
Control register Watch timer operation mode register (WTM)
CHAPTER 10 WATCH TIMER
User’s Manual U17473EJ2V0UD 277
10.3 Register Controlling Watch Timer
The watch timer is controlled by the watch timer operation mode register (WTM).
• Watch timer operation mode register (WTM)
This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit
counter operation control.
WTM is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets WTM to 00H.
Figure 10-2. Format of Watch Timer Operation Mode Register (WTM)
Address: FF6FH After reset: 00H R/W
Symbol 7 6 5 4 3 2 <1> <0>
WTM WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0
Watch timer count clock selection (fW) WTM7
f
SUB = 32.768 kHz fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz
0 fPRS/27 − 15.625 kHz 39.062 kHz 78.125 kHz 156.25 kHz
1 fSUB 32.768 kHz −
WTM6 WTM5 WTM4 Prescaler interval time selection
0 0 0 24/fW
0 0 1 25/fW
0 1 0 26/fW
0 1 1 27/fW
1 0 0 28/fW
1 0 1 29/fW
1 1 0 210/fW
1 1 1 211/fW
WTM3 WTM2 Selection of watch timer interrupt time
0 0 214/fW
0 1 213/fW
1 0 25/fW
1 1 24/fW
WTM1 5-bit counter operation control
0 Clear after operation stop
1 Start
WTM0 Watch timer operation enable
0 Operation stop (clear both prescaler and 5-bit counter)
1 Operation enable
CHAPTER 10 WATCH TIMER
User’s Manual U17473EJ2V0UD
278
Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM)
during watch timer operation.
Remarks 1. f
W: Watch timer clock frequency (fPRS/27 or fSUB)
2. f
PRS: Peripheral hardware clock frequency
3. fSUB: Subsystem clock frequency
CHAPTER 10 WATCH TIMER
User’s Manual U17473EJ2V0UD 279
10.4 Watch Timer Operations
10.4.1 Watch timer operation
The watch timer generates an interrupt request signal (INTWT) at a specific time interval by using the peripheral
hardware clock or subsystem clock.
When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count
operation starts. When these bits are cleared to 0, the 5-bit counter is cleared and the count operation stops.
When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by
clearing WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 29 × 1/fW
seconds occurs in the first overflow (INTWT) after zero-second start.
The interrupt request is generated at the following time intervals.
Table 10-4. Watch Timer Interrupt Time
WTM3
WTM2
Interrupt Time
Selection
When Operated at
fSUB = 32.768 kHz
(WTM7 = 1)
When Operated at
fPRS = 2 MHz
(WTM7 = 0)
When Operated at
fPRS = 5 MHz
(WTM7 = 0)
When Operated at
fPRS = 10 MHz
(WTM7 = 0)
When Operated at
fPRS = 20 MHz
(WTM7 = 0)
0 0 214/fW 0.5 s 1.05 s 0.419 s 0.210 s 0.105 s
0 1 213/fW 0.25 s 0.52 s 0.210 s 0.105 s 52.5 ms
1 0 25/fW 977
μ
s 2.05 ms 819
μ
s 410
μ
s 205
μ
s
1 1 24/fW 488
μ
s 1.02 ms 410
μ
s 205
μ
s 102
μ
s
Remarks 1. fW: Watch timer clock frequency (fPRS/27 or fSUB)
2. f
PRS: Peripheral hardware clock frequency
3. fSUB: Subsystem clock frequency
10.4.2 Interval timer operation
The watch timer operates as interval timer which generates interrupt request signals (INTWTI) repeatedly at an
interval of the preset count value.
The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register
(WTM).
When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is set to 0, the count operation
stops.
Table 10-5. Interval Timer Interval Time
WTM6
WTM5
WTM4 Interval Time When Operated
at fSUB = 32.768
kHz (WTM7 = 1)
When Operated
at fPRS = 2 MHz
(WTM7 = 0)
When Operated
at fPRS = 5 MHz
(WTM7 = 0)
When Operated
at fPRS = 10 MHz
(WTM7 = 0)
When Operated
at fPRS = 20 MHz
(WTM7 = 0)
0 0 0 24/fW 488
μ
s 1.02 ms 410
μ
s 205
μ
s 102
μ
s
0 0 1 25/fW 977
μ
s 2.05 ms 820
μ
s 410
μ
s 205
μ
s
0 1 0 26/fW 1.95 ms 4.10 ms 1.64 ms 820
μ
s 410
μ
s
0 1 1 27/fW 3.91 ms 8.20 ms 3.28 ms 1.64 ms 820
μ
s
1 0 0 28/fW 7.81 ms 16.4 ms 6.55 ms 3.28 ms 1.64 ms
1 0 1 29/fW 15.6 ms 32.8 ms 13.1 ms 6.55 ms 3.28 ms
1 1 0 210/fW 31.3 ms 65.5 ms 26.2 ms 13.1 ms 6.55 ms
1 1 1 211/fW 62.5 ms 131.1 ms 52.4 ms 26.2 ms 13.1 ms
Remarks 1. fW: Watch timer clock frequency (fPRS/27 or fSUB)
2. f
PRS: Peripheral hardware clock frequency
3. f
SUB: Subsystem clock frequency
CHAPTER 10 WATCH TIMER
User’s Manual U17473EJ2V0UD
280
Figure 10-3. Operation Timing of Watch Timer/Interval Timer
0H
Start Overflow Overflow
5-bit counter
Count clock
Watch timer
interrupt INTWT
Interval timer
interrupt INTWTI
Interrupt time of watch timer (0.5 s)
Interval time
(T)
T
Interrupt time of watch timer (0.5 s)
Remark fW: Watch timer clock frequency
Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0)
10.5 Cautions for Watch Timer
When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by
setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request signal (INTWT) is
generated after the register is set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of
WTM. Subsequently, however, the INTWT signal is generated at the specified intervals.
Figure 10-4. Example of Generation of Watch Timer Interrupt Request Signal (INTWT)
(When Interrupt Period = 0.5 s)
It takes 0.515625 seconds for the first INTWT to be generated (29 × 1/32768 = 0.015625 s longer).
INTWT is then generated every 0.5 seconds.
0.5 s0.5 s0.515625 s
WTM0, WTM1
INTWT
User’s Manual U17473EJ2V0UD 281
CHAPTER 11 WATCHDOG TIMER
11.1 Functions of Watchdog Timer
The watchdog timer operates on the internal low-speed oscillation clock.
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cases.
• If the watchdog timer counter overflows
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
• If data is written to WDTE during a window close period
• If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check while
the CPU hangs up)
• If the CPU accesses an area that is not set by the IMS and IXS registers (excluding FB00H to FFFFH) by
executing a read/write instruction (detection of an abnormal access during a CPU program loop)
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, see CHAPTER 23 RESET FUNCTION.
CHAPTER 11 WATCHDOG TIMER
User’s Manual U17473EJ2V0UD
282
11.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 11-1. Configuration of Watchdog Timer
Item Configuration
Control register Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
Table 11-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer Option Byte (0080H)
Window open period Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer Bit 4 (WDTON)
Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0)
Remark For the option byte, see CHAPTER 26 OPTION BYTE.
Figure 11-1. Block Diagram of Watchdog Timer
f
RL
/2
Clock
input
controller
Reset
output
controller
Internal reset signal
Internal bus
Selector
17-bit
counter
2
10
/f
RL
to
2
17
/f
RL
Watchdog timer enable
register (WDTE)
Clear, reset control
WDTON of option
byte (0080H)
WINDOW1 and WINDOW0
of option byte (0080H)
Count clear
signal
WDCS2 to WDCS0 of
option byte (0080H)
Overflow
signal
CPU access signal CPU access
error detector
Window size
determination
signal
CHAPTER 11 WATCHDOG TIMER
User’s Manual U17473EJ2V0UD 283
11.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
(1) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH or 1AHNote.
Figure 11-2. Format of Watchdog Timer Enable Register (WDTE)
01234567
Symbol
WDTE
Address: FF99H After reset: 9AH/1AH
Note
R/W
Note The WDTE reset value differs depending on the WDTON setting value of the option byte (0080H). To
operate watchdog timer, set WDTON to 1.
WDTON Setting Value WDTE Reset Value
0 (watchdog timer count operation disabled) 1AH
1 (watchdog timer count operation enabled) 9AH
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If the
source clock to the watchdog timer is stopped, however, an internal reset signal is
generated when the source clock to the watchdog timer resumes operation.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal
is generated. If the source clock to the watchdog timer is stopped, however, an internal
reset signal is generated when the source clock to the watchdog timer resumes operation.
3. The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
CHAPTER 11 WATCHDOG TIMER
User’s Manual U17473EJ2V0UD
284
11.4 Operation of Watchdog Timer
11.4.1 Controlling operation of watchdog timer
1. When the watchdog timer is used, its operation is specified by the option byte (0080H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1
(the counter starts operating after a reset release) (for details, see CHAPTER 26).
WDTON Operation Control of Watchdog Timer Counter/Illegal Access Detection
0 Counter operation disabled (counting stopped after reset), illegal access detection operation disabled
1 Counter operation enabled (counting started after reset), illegal access detection operation enabled
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, see
11.4.2 and CHAPTER 26).
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for
details, see 11.4.3 and CHAPTER 26).
2. After a reset release, the watchdog timer starts counting.
3. By writing “ACH” to WDTE after the watchdog timer starts counting and before the overflow time set by the
option byte, the watchdog timer is cleared and starts counting again.
4. After that, write WDTE the second time or later after a reset release during the window open period. If WDTE
is written during a window close period, an internal reset signal is generated.
5. If the overflow time expires without “ACH” written to WDTE, an internal reset signal is generated.
A internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
• If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check
during a CPU program loop)
• If the CPU accesses an area not set by the IMS and IXS registers (excluding FB00H to FFFFH) by executing
a read/write instruction (detection of an abnormal access during a CPU program loop)
Cautions 1. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before
the overflow time regardless of the timing of the writing, and the watchdog timer starts
counting again.
2. If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may be
different from the overflow time set by the option byte by up to 2/fRL seconds.
3. The watchdog timer can be cleared immediately before the count value overflows (FFFFH).
CHAPTER 11 WATCHDOG TIMER
User’s Manual U17473EJ2V0UD 285
Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows
depending on the set value of bit 0 (LSROSC) of the option byte.
LSROSC = 0 (Internal Low-Speed
Oscillator Can Be Stopped by Software)
LSROSC = 1 (Internal Low-Speed
Oscillator Cannot Be Stopped)
In HALT mode
In STOP mode
Watchdog timer operation stops. Watchdog timer operation continues.
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is not cleared to 0 but starts counting from the value at
which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP (bit 1 of the
internal oscillation mode register (RCM) = 1) when LSROSC = 0, the watchdog timer stops
operating. At this time, the counter is not cleared to 0.
5. The watchdog timer continues its operation during self-programming and EEPROMTM
emulation of the flash memory. During processing, the interrupt acknowledge time is
delayed. Set the overflow time and window size taking this delay into consideration.
11.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer
starts counting again by writing “ACH” to WDTE during the window open period before the overflow time.
The following overflow time is set.
Table 11-3. Setting of Overflow Time of Watchdog Timer
WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer
0 0 0 210/fRL (3.88 ms)
0 0 1 211/fRL (7.76 ms)
0 1 0 212/fRL (15.52 ms)
0 1 1 213/fRL (31.03 ms)
1 0 0 214/fRL (62.06 ms)
1 0 1 215/fRL (124.12 ms)
1 1 0 216/fRL (248.24 ms)
1 1 1 217/fRL (496.48 ms)
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
is prohibited.
2. The watchdog timer continues its operation during self-programming and EEPROM
emulation of the flash memory. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
Remarks 1. fRL: Internal low-speed oscillation clock frequency
2. ( ): fRL = 264 kHz (MAX.)
<R>
<R>
CHAPTER 11 WATCHDOG TIMER
User’s Manual U17473EJ2V0UD
286
11.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option
byte (0080H). The outline of the window is as follows.
• If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting
again.
• Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal
reset signal is generated.
Example: If the window open period is 25%
Window close period (75%) Window open
period (25%)
Counting
starts
Overflow
time
Counting starts again when
ACH is written to WDTE.
Internal reset signal is generated
if ACH is written to WDTE.
Caution The first writing to WDTE after a reset release clears the watchdog timer, if it is made before the
overflow time regardless of the timing of the writing, and the watchdog timer starts counting
again.
The window open period to be set is as follows.
Table 11-4. Setting Window Open Period of Watchdog Timer
WINDOW1 WINDOW0 Window Open Period of Watchdog Timer
0 0 25%
0 1 50%
1 0 75%
1 1 100%
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0
is prohibited.
2. The watchdog timer continues its operation during self-programming and EEPROM
emulation of the flash memory. During processing, the interrupt acknowledge time
is delayed. Set the overflow time and window size taking this delay into
consideration.
<R>
CHAPTER 11 WATCHDOG TIMER
User’s Manual U17473EJ2V0UD 287
Remark If the overflow time is set to 210/fRL, the window close time and open time are as follows.
Setting of Window Open Period
25% 50% 75% 100%
Window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms None
Window open time 3.56 to 3.88 ms 2.37 to 3.88 ms 0.119 to 3.88 ms 0 to 3.88 ms
<When window open period is 25%>
• Overflow time:
210/fRL (MAX.) = 210/264 kHz (MAX.) = 3.88 ms
• Window close time:
0 to 210/fRL (MIN.) × (1 − 0.25) = 0 to 210/216 kHz (MIN.) × 0.75 = 0 to 3.56 ms
• Window open time:
210/fRL (MIN.) × (1 − 0.25) to 210/fRL (MAX.) = 210/216 kHz (MIN.) × 0.75 to 210/264 kHz (MAX.)
= 3.56 to 3.88 ms
User’s Manual U17473EJ2V0UD
288
CHAPTER 12 CLOCK OUTPUT CONTROLLER
12.1 Functions of Clock Output Controller
The clock output controller of 78K0/LG2 is intended for clock output for supply to LCD controller/driver. The clock
selected with the clock output selection register (CKS) is supplied to the LCD controller/driver.
Figure 12-1 shows the block diagram of clock output controller.
Figure 12-1. Block Diagram of Clock Output Controller
f
PRS
f
PRS
/2
6
, f
PRS
/2
7
f
SUB
CLOE
2
LCD controller/driver
Clock
controller
Prescaler
Internal bus
CCS3
Clock output selection register (CKS)
CCS2 CCS1 CCS0
PM140
Selector
Port mode register 14
(PM14)
f
PCL
CHAPTER 12 CLOCK OUTPUT CONTROLLER
User’s Manual U17473EJ2V0UD 289
12.2 Configuration of Clock Output Controller
The clock output controller includes the following hardware.
Table 12-1. Configuration of Clock Output Controller
Item Configuration
Control registers Clock output selection register (CKS)
Port mode register 14 (PM14)
12.3 Registers Controlling Clock Output Controller
The following two registers are used to control the clock output controller.
• Clock output selection register (CKS)
• Port mode register 14 (PM14)
CHAPTER 12 CLOCK OUTPUT CONTROLLER
User’s Manual U17473EJ2V0UD
290
(1) Clock output selection register (CKS)
CKS enables/disables the clock output to the LCD controller/driver, and sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets CKS to 00H.
Figure 12-2. Format of Clock Output Selection Register (CKS)
Address: FF40H After reset: 00H R/W
Symbol 7 6 5 3 2 1 0
CKS 0 0 0 CLOE CCS3 CCS2 CCS1 CCS0
CLOE
PM140 Specification of enable/disable for clock output
to LCD controller/driverNote
1
0 Clock output to LCD controller/driver enabled
Other than above Clock output to LCD controller/driver disabled
LCD output clock selection
CCS3 CCS2 CCS1 CCS0
f
SUB =
32.768 kHz
fPRS =
10 MHz
fPRS =
20 MHz
0 1 1 0 fPRS/26156.25 kHz 312.5 kHz
0 1 1 1 fPRS/27
-
78.125 kHz 156.25 kHz
1 0 0 0 fSUB 32.768 kHz -
Other than above Setting prohibited
Note Enabling/disabling the PCL clock output is specified by combining the PM140 settings (see 18.4 (7)
Port mode register 14 (PM14)).
Cautions 1. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
2. Bits 5 to 7 must be set to 0.
Remarks 1. fPRS: Peripheral hardware clock oscillation frequency
2. fSUB: Subsystem clock oscillation frequency
4
<R>
CHAPTER 12 CLOCK OUTPUT CONTROLLER
User’s Manual U17473EJ2V0UD 291
(2) Port mode register 14 (PM14)
PM14 controls the clock output to the LCD controller/driver.
Set the PM140 bit to 0 to use this register as the clock output function.
PM14 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM14 to FFH.
Figure 12-3. Format of Port Mode Register 14 (PM14)
Address: FF2EH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM14 1 1 1 1 1 1 PM141 PM140
PM140 Clock output control to LCD controller/driver
0 Clock output to LCD controller/driver enabled
1 Clock output to LCD controller/driver disabled
Caution After a reset release, be sure to set PM141 to 0.
12.4 Operations of Clock Output Controller
The clock pulse is output as the following procedure.
<1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register
(CKS) (clock pulse output in disabled status).
<2> Set bit 4 (CLOE) of CKS to 1 to enable clock output.
Remark The clock output controller is designed not to output pulses with a small width during output
enable/disable switching of the clock output. As shown in Figure 12-4, be sure to start output from the
low period of the clock (marked with * in the figure). When stopping output, do so after securing a high
level of the clock.
Figure 12-4. Clock Output Application Example
CLOE
Clock output
**
User’s Manual U17473EJ2V0UD
292
CHAPTER 13 A/D CONVERTER
13.1 Function of A/D Converter
The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to
ANI7) with a resolution of 10 bits.
The A/D converter has the following function.
• 10-bit resolution A/D conversion
10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to
ANI7. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
Figure 13-1. Block Diagram of A/D Converter
AV
REF
AV
SS
INTAD
ADCS bit
ADCS FR2 FR1 ADCEFR0
Sample & hold circuit
AV
SS
Voltage comparator
A/D converter mode
register (ADM)
Internal bus
3
ADS2 ADS1 ADS0
Analog input channel
specification register (ADS)
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
Controller
A/D conversion result
register (ADCR)
Successive
approximation
register (SAR)
LV1 LV0
5
A/D port configuration
register (ADPC)
ADPC3 ADPC2 ADPC1 ADPC0
4
Selector
Tap selector
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 293
13.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI7 pins
These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into
digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
(2) Sample & hold circuit
The sample & hold circuit samples the input voltage of the analog input pin selected by the selector when A/D
conversion is started, and holds the sampled voltage value during A/D conversion.
(3) Series resistor string
The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with
the sampled voltage value.
Figure 13-2. Circuit Configuration of Series Resistor String
ADCS
Series resistor string
AV
REF
P-ch
AV
SS
(4) Voltage comparator
The voltage comparator compares the sampled voltage value and the output voltage of the series resistor string.
(5) Successive approximation register (SAR)
This register converts the result of comparison by the voltage comparator, starting from the most significant bit
(MSB).
When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D
conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).
(6) 10-bit A/D conversion result register (ADCR)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6
bits are fixed to 0).
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
294
(7) 8-bit A/D conversion result register (ADCRH)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
Caution When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read data from
ADCR and ADCRH when the CPU is operating on the subsystem clock and the peripheral
hardware clock is stopped. For details, see CHAPTER 33 CAUTIONS FOR WAIT.
(8) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as
well as starting and stopping of the conversion operation. When A/D conversion has been completed, this
controller generates INTAD.
(9) AVREF pin
This pin inputs an analog power/reference voltage to the A/D converter. Make this pin the same potential as the
VDD pin when port 2 is used as a digital port.
The signal input to ANI0 to ANI7 is converted into a digital signal, based on the voltage applied across AVREF and
AVSS.
(10) AVSS pin
This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the VSS
pin even when the A/D converter is not used.
(11) A/D converter mode register (ADM)
This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the
conversion operation.
(12) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port.
(13) Analog input channel specification register (ADS)
This register is used to specify the port that inputs the analog voltage to be converted into a digital signal.
(14) Port mode register 2 (PM2)
This register switches the ANI0/P20 to ANI7/P27 pins to input or output.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 295
13.3 Registers Used in A/D Converter
The A/D converter uses the following six registers.
• A/D converter mode register (ADM)
• A/D port configuration register (ADPC)
• Analog input channel specification register (ADS)
• Port mode register 2 (PM2)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
(1) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 13-3. Format of A/D Converter Mode Register (ADM)
ADCELV0Note 1
LV1Note 1
FR0Note 1
FR1Note 1
FR2Note 1
0ADCS
A/D conversion operation control
Stops conversion operation
Enables conversion operation
ADCS
0
1
<0>123456<7>
ADM
Address: FF28H After reset: 00H R/W
Symbol
Comparator operation controlNote 2
Stops comparator operation
Enables comparator operation (comparator: 1/2AVREF operation)
ADCE
0
1
Notes 1. For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 13-2 A/D Conversion Time
Selection.
2. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1
μ
s from operation
start to operation stabilization. Therefore, when ADCS is set to 1 after 1
μ
s or more has elapsed from
the time ADCE is set to 1, the conversion result at that time has priority over the first conversion
result. Otherwise, ignore data of the first conversion.
Table 13-1. Settings of ADCS and ADCE
ADCS ADCE A/D Conversion Operation
0 0 Stop status (DC power consumption path does not exist)
0 1
Conversion waiting mode (comparator: 1/2AVREF operation, only comparator
consumes power)
1 0 Conversion mode (comparator operation stoppedNote)
1 1 Conversion mode (comparator: 1/2AVREF operation)
Note Ignore data of the first conversion because it is not guaranteed range.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
296
Figure 13-4. Timing Chart When Comparator Is Used
ADCE
Comparator
ADCS
Conversion
operation
Conversion
operation
Conversion
stopped
Conversion
waiting
Comparator: 1/2AV
REF
operation
Note
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be
1
μ
s or longer.
Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values
other than the identical data.
2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is
operating on the subsystem clock and the peripheral hardware clock is stopped. For details,
see CHAPTER 33 CAUTIONS FOR WAIT.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 297
Table 13-2. A/D Conversion Time Selection
(1) 2.7 V ≤ AVREF ≤ 5.5 V
A/D Converter Mode Register (ADM) Conversion Time Selection
FR2 FR1 FR0 LV1 LV0 fPRS = 2 MHz fPRS = 10 MHz fPRS = 20 MHzNote
Conversion Clock
(fAD)
0 0 0 0 0 264/fPRS 26.4
μ
s 13.2
μ
sNote fPRS/12
0 0 1 0 0 176/fPRS 17.6
μ
s 8.8
μ
sNote fPRS/8
0 1 0 0 0 132/fPRS 13.2
μ
s 6.6
μ
sNote fPRS/6
0 1 1 0 0 88/fPRS
Setting prohibited
8.8
μ
sNote fPRS/4
1 0 0 0 0 66/fPRS 33.0
μ
s 6.6
μ
sNote fPRS/3
1 0 1 0 0 44/fPRS 22.0
μ
s Setting prohibited
Setting prohibited
fPRS/2
Other than above Setting prohibited
Note This can be set only when 4.0 V ≤ AVREF ≤ 5.5 V.
(2) 2.3 V ≤ AVREF < 2.7 V
A/D Converter Mode Register (ADM) Conversion Time Selection
FR2 FR1 FR0 LV1 LV0 fPRS = 2 MHz fPRS = 5 MHz
Conversion Clock
(fAD)
0 0 0 0 1 480/fPRS Setting prohibited fPRS/12
0 0 1 0 1 320/fPRS 64.0
μ
s fPRS/8
0 1 0 0 1 240/fPRS 48.0
μ
s fPRS/6
0 1 1 0 1 160/fPRS
Setting prohibited
32.0
μ
s fPRS/4
1 0 0 0 1 120/fPRS 60.0
μ
s Setting prohibited fPRS/3
1 0 1 0 1 80/fPRS 40.0
μ
s Setting prohibited fPRS/2
Other than above Setting prohibited
Cautions 1. Set the conversion times with the following conditions.
• 4.0 V ≤ AVREF ≤ 5.5 V: fAD = 0.6 to 3.6 MHz
• 2.7 V ≤ AVREF < 4.0 V: fAD = 0.6 to 1.8 MHz
• 2.3 V ≤ AVREF < 2.7 V: fAD = 0.6 to 1.48 MHz
2. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
3. Change LV1 and LV0 from the default value, when 2.3 V ≤ AVREF < 2.7 V.
4. The above conversion time does not include clock frequency errors. Select conversion time,
taking clock frequency errors into consideration.
Remark f
PRS: Peripheral hardware clock frequency
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
298
Figure 13-5. A/D Converter Sampling and A/D Conversion Timing
ADCS
Wait
period
Note
Conversion time Conversion time
Sampling
Sampling
timing
INTAD
ADCS ← 1 or ADS rewrite
Sampling
SAR
clear
SAR
clear
Transfer
to ADCR,
INTAD
generation
Successive conversion
Note For details of wait period, see CHAPTER 33 CAUTIONS FOR WAIT.
(2) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8
bits of the conversion result are stored in FF09H and the lower 2 bits are stored in the higher 2 bits of FF08H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation sets this register to 0000H.
Figure 13-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Symbol
Address: FF08H, FF09H After reset: 0000H R
FF09H FF08H
000000
ADCR
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCR may
become undefined. Read the conversion result following conversion completion before
writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect
conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 33 CAUTIONS FOR WAIT.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 299
(3) 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are
stored.
ADCRH can be read by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 13-7. Format of 8-Bit A/D Conversion Result Register (ADCRH)
Symbol
ADCRH
Address: FF09H After reset: 00H R
76543210
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of ADCRH may
become undefined. Read the conversion result following conversion completion before
writing to ADM, ADS, and ADPC. Using timing other than the above may cause an incorrect
conversion result to be read.
2. If data is read from ADCRH, a wait cycle is generated. Do not read data from ADCRH when
the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped.
For details, see CHAPTER 33 CAUTIONS FOR WAIT.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
300
(4) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 13-8. Format of Analog Input Channel Specification Register (ADS)
ADS0ADS1ADS200000
Analog input channel specification
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ADS0
0
1
0
1
0
1
0
1
ADS1
0
0
1
1
0
0
1
1
ADS2
0
0
0
0
1
1
1
1
01234567
ADS
Address: FF29H After reset: 00H R/W
Symbol
Cautions 1. Be sure to clear bits 3 to 7 to 0.
2 Set a channel to be used for A/D conversion in the input mode by using port mode register 2
(PM2).
3. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the CPU is
operating on the subsystem clock and the peripheral hardware clock is stopped. For details,
see CHAPTER 33 CAUTIONS FOR WAIT.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 301
(5) A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port.
ADPC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 13-9. Format of A/D Port Configuration Register (ADPC)
ADPC0ADPC1ADPC2ADPC30000
Analog input (A)/digital I/O (D) switching
Setting prohibited
ADPC3
01234567
ADPC
Address: FF2FH After reset: 00H R/W
Symbol
ANI7/
P27
A
A
A
A
A
A
A
A
D
ANI6/
P26
A
A
A
A
A
A
A
D
D
ANI5/
P25
A
A
A
A
A
A
D
D
D
ANI4/
P24
A
A
A
A
A
D
D
D
D
ANI3/
P23
A
A
A
A
D
D
D
D
D
ANI2/
P22
A
A
A
D
D
D
D
D
D
ANI1/
P21
A
A
D
D
D
D
D
D
D
ANI0/
P20
A
D
D
D
D
D
D
D
D
0
0
0
0
0
0
0
0
1
ADPC2
0
0
0
0
1
1
1
1
0
ADPC1
0
0
1
1
0
0
1
1
0
ADPC0
0
1
0
1
0
1
0
1
0
Other than above
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode register 2
(PM2).
2. If data is written to ADPC, a wait cycle is generated. Do not write data to ADPC when the CPU
is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 33 CAUTIONS FOR WAIT.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
302
(6) Port mode register 2 (PM2)
When using the ANI0/P20 to ANI7/P27 pins for analog input port, set PM20 to PM27 to 1. The output latches of
P20 to P27 at this time may be 0 or 1.
If PM20 to PM27 are set to 0, they cannot be used as analog input port pins.
PM2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 13-10. Format of Port Mode Register 2 (PM2)
PM20PM21PM22PM23PM24PM25PM26PM27
P2n pin I/O mode selection (n = 0 to 7)
Output mode (output buffer on)
Input mode (output buffer off)
PM2n
0
1
01234567
PM2
Address: FF22H After reset: FFH R/W
Symbol
ANI0/P20 to ANI7/P27 pins are as shown below depending on the settings of ADPC, ADS, and PM2.
Table 13-3. Setting Functions of ANI0/P20 to ANI7/P27 Pins
ADPC PM2 ADS ANI0/P20 to ANI7/P27 Pin
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
Input mode − Digital input Digital I/O selection
Output mode − Digital output
<R>
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 303
13.4 A/D Converter Operations
13.4.1 Basic operations of A/D converter
<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator.
<2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set
to input mode by using port mode register 2 (PM2).
<3> Set A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM.
<4> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<5> Start the conversion operation by setting bit 7 (ADCS) of ADM to 1.
(<6> to <12> are operations performed by hardware.)
<6> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<7> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
<8> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to
(1/2) AVREF by the tap selector.
<9> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the
analog input is smaller than (1/2) AVREF, the MSB is reset to 0.
<10> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AVREF
• Bit 9 = 0: (1/4) AVREF
The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows.
• Analog input voltage ≥ Voltage tap: Bit 8 = 1
• Analog input voltage < Voltage tap: Bit 8 = 0
<11> Comparison is continued in this way up to bit 0 of SAR.
<12> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
<13> Repeat steps <6> to <12>, until ADCS is cleared to 0.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <5>. To start A/D conversion again when
ADCE = 0, set ADCE to 1, wait for 1
μ
s or longer, and start <5>. To change a channel of A/D conversion,
start from <4>.
Caution Make sure the period of <1> to <5> is 1
μ
s or more.
Remark Two types of A/D conversion result registers are available.
• ADCR (16 bits): Store 10-bit A/D conversion value
• ADCRH (8 bits): Store 8-bit A/D conversion value
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
304
Figure 13-11. Basic Operation of A/D Converter
Conversion time
Sampling time
Sampling A/D conversion
Undefined Conversion
result
A/D converter
operation
SAR
ADCR
INTAD
Conversion
result
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)
is reset (0) by software.
If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion
operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the
beginning.
Reset signal generation sets the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 305
13.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical
A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following
expression.
SAR = INT ( × 1024 + 0.5)
ADCR = SAR × 64
or
( − 0.5) × ≤ VAIN < ( + 0.5) ×
where, INT( ): Function which returns integer part of value in parentheses
V
AIN: Analog input voltage
AVREF: AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
SAR: Successive approximation register
Figure 13-12 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 13-12. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021
3
2
1
0
FFC0H
FF80H
FF40H
00C0H
0080H
0040H
0000H
A/D conversion result
SAR ADCR
1
2048
1
1024
3
2048
2
1024
5
2048
Input voltage/AVREF
3
1024
2043
2048
1022
1024
2045
2048
1023
1024
2047
2048
1
VAIN
AVREF
AVREF
1024
AVREF
1024
ADCR
64
ADCR
64
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
306
13.4.3 A/D converter operation mode
The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to
ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed.
(1) A/D conversion operation
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the
voltage, which is applied to the analog input pin specified by the analog input channel specification register
(ADS), is started.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR), and an interrupt request signal (INTAD) is generated. When one A/D conversion has been
completed, the next A/D conversion operation is immediately started.
If ADS is rewritten during A/D conversion, the A/D conversion operation under execution is stopped and restarted
from the beginning.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the
conversion result immediately before is retained.
Figure 13-13. A/D Conversion Operation
ANIn
Rewriting ADM
ADCS = 1 Rewriting ADS ADCS = 0
ANIn
ANIn ANIn ANIm
ANIn ANIm ANIm
Stopped
Conversion result
immediately before
is retained
A/D conversion
ADCR,
ADCRH
INTAD
Conversion is stopped
Conversion result immediately
before is retained
Remarks 1. n = 0 to 7
2. m = 0 to 7
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 307
The setting methods are described below.
<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<2> Set the channel to be used in the analog input mode by using bits 3 to 0 (ADPC3 to ADPC0) of the A/D
port configuration register (ADPC) and bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2).
<3> Select conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM.
<4> Select a channel to be used by using bits 2 to 0 (ADS2 to ADS0) of the analog input channel
specification register (ADS).
<5> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.
<6> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<7> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Change the channel>
<8> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS to start A/D conversion.
<9> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<10> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Complete A/D conversion>
<11> Clear ADCS to 0.
<12> Clear ADCE to 0.
Cautions 1. Make sure the period of <1> to <5> is 1
μ
s or more.
2. <1> may be done between <2> and <4>.
3. <1> can be omitted. However, ignore data of the first conversion after <5> in this case.
4. The period from <6> to <9> differs from the conversion time set using bits 5 to 1 (FR2 to
FR0, LV1, LV0) of ADM. The period from <8> to <9> is the conversion time set using FR2
to FR0, LV1, and LV0.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
308
13.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input
voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the
full scale is expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of
these express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an
analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot
be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral
linearity error, and differential linearity error in the characteristics table.
Figure 13-14. Overall Error Figure 13-15. Quantization Error
Ideal line
0……0
1……1
Digital output
Overall
error
Analog input
AV
REF
0
0……0
1……1
Digital output
Quantization error
1/2LSB
1/2LSB
Analog input
0AVREF
(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output
changes from 0……001 to 0……010.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 309
(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It
expresses the maximum value of the difference between the actual measurement value and the ideal straight line
when the zero-scale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value
and the ideal value.
Figure 13-16. Zero-Scale Error Figure 13-17. Full-Scale Error
111
011
010
001 Zero-scale error
Ideal line
000
012 3 AV
REF
Digital output (Lower 3 bits)
Analog input (LSB)
111
110
101
000
0
AVREF−3
Full-scale error
Ideal line
Analog input (LSB)
Digital output (Lower 3 bits)
AVREF−2AVREF−1
AV
REF
Figure 13-18. Integral Linearity Error Figure 13-19. Differential Linearity Error
0
AV
REF
Digital output
Analog input
Integral linearity
error
Ideal line
1……1
0……0
0
AV
REF
Digital output
Analog input
Differential
linearity error
1……1
0……0
Ideal 1LSB width
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time Conversion time
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
310
13.6 Cautions for A/D Converter
(1) Operating current in STOP mode
The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by
clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start
operation.
(2) Input range of ANI0 to ANI7
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
(3) Conflicting operations
<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR or ADCRH read by
instruction upon the end of conversion
ADCR or ADCRH read has priority. After the read operation, the new conversion result is written to ADCR
or ADCRH.
<2> Conflict between ADCR or ADCRH write and A/D converter mode register (ADM) write, analog input
channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of
conversion
ADM, ADS, or ADPC write has priority. ADCR or ADCRH write is not performed, nor is the conversion end
interrupt signal (INTAD) generated.
(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI7.
<1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply.
<2> The higher the output impedance of the analog input source, the greater the influence. To reduce the
noise, connecting external C as shown in Figure 13-20 is recommended.
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of conversion.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 311
Figure 13-20. Analog Input Pin Connection
Reference
voltage
input
C = 100 to 1,000 pF
If there is a possibility that noise equal to or higher than AV
REF
or
equal to or lower than AV
SS
may enter, clamp with a diode with a
small V
F
value (0.3 V or lower).
AV
REF
AV
SS
V
SS
ANI0 to ANI7
(5) ANI0/P20 to ANI7/P27
<1> The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27).
When A/D conversion is performed with any of ANI0 to ANI7 selected, do not access P20 to P27 while
conversion is in progress; otherwise the conversion resolution may be degraded. It is recommended to
select pins used as P20 to P27 starting with the ANI0/P20 that is the furthest from AVREF.
<2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected
value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to
the pins adjacent to the pin undergoing A/D conversion.
(6) Input impedance of ANI0 to ANI7 pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the
capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling
is in progress, and on the other states.
To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog
input source to within 10 kΩ, and to connect a capacitor of about 100 pF to the ANI0 to ANI7 pins (see Figure 13-
20).
(7) AVREF pin input impedance
A series resistor string of several tens of kΩ is connected between the AVREF and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to
the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD
312
(8) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-
change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 13-21. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ADCR
ADIF
ANIn ANIn ANIm ANIm
ANIn ANIn ANIm ANIm
ADS rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
Remarks 1. n = 0 to 7
2. m = 0 to 7
(9) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the
ADCS bit is set to 1 within 1
μ
s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =
0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
(10) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to the A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents of ADCR and ADCRH may
become undefined. Read the conversion result following conversion completion before writing to ADM, ADS, and
ADPC. Using a timing other than the above may cause an incorrect conversion result to be read.
CHAPTER 13 A/D CONVERTER
User’s Manual U17473EJ2V0UD 313
(11) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 13-22. Internal Equivalent Circuit of ANIn Pin
ANIn
C1 C2
R1
Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)
AVREF R1 C1 C2
4.0 V ≤ AVREF ≤ 5.5 V 8.1 kΩ 8 pF 5 pF
2.7 V ≤ AVREF < 4.0 V 31 kΩ 8 pF 5 pF
2.3 V ≤ AVREF < 2.7 V 381 kΩ 8 pF 5 pF
Remarks 1. The resistance and capacitance values shown in Table 13-4 are not guaranteed values.
2. n = 0 to 7
User’s Manual U17473EJ2V0UD
314
CHAPTER 14 SERIAL INTERFACE UART0
14.1 Functions of Serial Interface UART0
Serial interface UART0 has the following two modes.
(1) Operation stop mode
This mode is used when serial communication is not executed and can enable a reduction in the power
consumption.
For details, see 14.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
The functions of this mode are outlined below.
For details, see 14.4.2 Asynchronous serial interface (UART) mode and 14.4.3 Dedicated baud rate
generator.
• Maximum transfer rate: 625 kbps
• Two-pin configuration TXD0: Transmit data output pin
R
XD0: Receive data input pin
• Length of communication data can be selected from 7 or 8 bits.
• Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set
• Transmission and reception can be performed independently (full-duplex operation).
• Fixed to LSB-first communication
Cautions 1. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD0 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
2. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start
communication.
3. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock
after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base
clock, the transmission circuit or reception circuit may not be initialized.
4. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
<R>
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 315
14.2 Configuration of Serial Interface UART0
Serial interface UART0 includes the following hardware.
Table 14-1. Configuration of Serial Interface UART0
Item Configuration
Registers Receive buffer register 0 (RXB0)
Receive shift register 0 (RXS0)
Transmit shift register 0 (TXS0)
Control registers Asynchronous serial interface operation mode register 0 (ASIM0)
Asynchronous serial interface reception error status register 0 (ASIS0)
Baud rate generator control register 0 (BRGC0)
Port mode register 1 (PM1)
Port register 1 (P1)
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
316
Figure 14-1. Block Diagram of Serial Interface UART0
T
X
D0/
SCK10/P10
INTST0
R
X
D0/
SI10/P11
INTSR0
f
PRS
/2
5
f
PRS
/2
3
f
PRS
/2
Transmit shift register 0
(TXS0)
Receive shift register 0
(RXS0)
Receive buffer register 0
(RXB0)
Asynchronous serial
interface reception error
status register 0 (ASIS0)
Asynchronous serial
interface operation mode
register 0 (ASIM0)
Baud rate generator
control register 0
(BRGC0)
8-bit timer/
event counter
50 output
Registers
Selector
Baud rate
generator
Baud rate
generator
Reception unit
Reception control
Filter
Internal bus
Transmission control
Transmission unit
Output latch
(P10)
PM10
77
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 317
(1) Receive buffer register 0 (RXB0)
This 8-bit register stores parallel data converted by receive shift register 0 (RXS0).
Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift
register 0 (RXS0).
If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is
always 0.
If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0.
RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.
Reset signal generation and POWER0 = 0 set this register to FFH.
(2) Receive shift register 0 (RXS0)
This register converts the serial data input to the RXD0 pin into parallel data.
RXS0 cannot be directly manipulated by a program.
(3) Transmit shift register 0 (TXS0)
This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is
transmitted from the TXD0 pins.
TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read.
Reset signal generation, POWER0 = 0, and TXE0 = 0 set this register to FFH.
Cautions 1. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
2. Do not write the next transmit data to TXS0 before the transmission completion interrupt
signal (INTST0) is generated.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
318
14.3 Registers Controlling Serial Interface UART0
Serial interface UART0 is controlled by the following five registers.
• Asynchronous serial interface operation mode register 0 (ASIM0)
• Asynchronous serial interface reception error status register 0 (ASIS0)
• Baud rate generator control register 0 (BRGC0)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Asynchronous serial interface operation mode register 0 (ASIM0)
This 8-bit register controls the serial communication operations of serial interface UART0.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2)
Address: FF70H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1
POWER0 Enables/disables operation of internal operation clock
0
Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
1 Enables operation of the internal operation clock.
TXE0 Enables/disables transmission
0 Disables transmission (synchronously resets the transmission circuit).
1 Enables transmission.
RXE0 Enables/disables reception
0 Disables reception (synchronously resets the reception circuit).
1 Enables reception.
Notes 1. The input from the RXD0 pin is fixed to high level when POWER0 = 0.
2. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 319
Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
PS01 PS00 Transmission operation Reception operation
0 0 Does not output parity bit. Reception without parity
0 1 Outputs 0 parity. Reception as 0 parityNote
1 0 Outputs odd parity. Judges as odd parity.
1 1 Outputs even parity. Judges as even parity.
CL0 Specifies character length of transmit/receive data
0 Character length of data = 7 bits
1 Character length of data = 8 bits
SL0 Specifies number of stop bits of transmit data
0 Number of stop bits = 1
1 Number of stop bits = 2
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission,
clear TXE0 to 0, and then clear POWER0 to 0.
2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear
RXE0 to 0, and then clear POWER0 to 0.
3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If
POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.
4. TXE0 and RXE0 are synchronized by the base clock (fXCLK0) set by BRGC0. To enable
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after
TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock,
the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXS0 at least one base clock (fXCLK0) after setting TXE0 = 1.
6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
7. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.
8. Be sure to set bit 0 to 1.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
320
(2) Asynchronous serial interface reception error status register 0 (ASIS0)
This register indicates an error status on completion of reception by serial interface UART0. It includes three
error flag bits (PE0, FE0, OVE0).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read
when this register is read. If a reception error occurs, read ASIS0 and then read receive buffer register 0 (RXB0)
to clear the error flag.
Figure 14-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
Address: FF73H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIS0 0 0 0 0 0 PE0 FE0 OVE0
PE0 Status flag indicating parity error
0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
1 If the parity of transmit data does not match the parity bit on completion of reception.
FE0 Status flag indicating framing error
0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
1 If the stop bit is not detected on completion of reception.
OVE0 Status flag indicating overrun error
0 If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
1
If receive data is set to the RXB0 register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
asynchronous serial interface operation mode register 0 (ASIM0).
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0
(RXB0) but discarded.
4. If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 33 CAUTIONS FOR WAIT.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 321
(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 1FH.
Figure 14-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol 7 6 5 4 3 2 1 0
BRGC0 TPS01 TPS00 0 MDL04 MDL03 MDL02 MDL01 MDL00
Base clock (fXCLK0) selection TPS01 TPS00
fPRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz
0 0 TM50 outputNote
0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz
1 0 fPRS/23 250 kHz 625 kHz 1.25 MHz 2.5 MHz
1 1 fPRS/25 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz
MDL04 MDL03 MDL02 MDL01 MDL00 k Selection of 5-bit counter
output clock
0 0
× × × × Setting prohibited
0 1 0 0 0 8 fXCLK0/8
0 1 0 0 1 9 fXCLK0/9
0 1 0 1 0 10 fXCLK0/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 0 1 0 26 fXCLK0/26
1 1 0 1 1 27 fXCLK0/27
1 1 1 0 0 28 fXCLK0/28
1 1 1 0 1 29 fXCLK0/29
1 1 1 1 0 30 fXCLK0/30
1 1 1 1 1 31 fXCLK0/31
Note Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation
(TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
322
Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
2. The baud rate value is the output clock of the 5-bit counter divided by 2.
Remarks 1. f
XCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits
2. fPRS: Peripheral hardware clock frequency
3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31)
4. ×: Don’t care
5. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50
(4) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P10/TxD0/SCK10 pin for serial interface data output, clear PM10 to 0 and set the output latch of
P10 to 1.
When using the P11/RxD0/SI10 pin for serial interface data input, set PM11 to 1. The output latch of P11 at this
time may be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 14-5. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 323
14.4 Operation of Serial Interface UART0
Serial interface UART0 has the following two modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
14.4.1 Operation stop mode
In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the
pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0,
TXE0, and RXE0) of ASIM0 to 0.
(1) Register used
The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0).
ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Address: FF70H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM0 POWER0 TXE0 RXE0 PS01 PS00 CL0 SL0 1
POWER0 Enables/disables operation of internal operation clock
0
Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
TXE0 Enables/disables transmission
0 Disables transmission (synchronously resets the transmission circuit).
RXE0 Enables/disables reception
0 Disables reception (synchronously resets the reception circuit).
Notes 1. The input from the RXD0 pin is fixed to high level when POWER0 = 0.
2. Asynchronous serial interface reception error status register 0 (ASIS0), transmit shift register 0 (TXS0),
and receive buffer register 0 (RXB0) are reset.
Caution Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation stop mode.
To start the communication, set POWER0 to 1, and then set TXE0 or RXE0 to 1.
Remark To use the RxD0/SI10/P11 and TxD0/SCK10/P10 pins as general-purpose port pins, see CHAPTER 5
PORT FUNCTIONS.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
324
14.4.2 Asynchronous serial interface (UART) mode
In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed.
A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of
baud rates.
(1) Registers used
• Asynchronous serial interface operation mode register 0 (ASIM0)
• Asynchronous serial interface reception error status register 0 (ASIS0)
• Baud rate generator control register 0 (BRGC0)
• Port mode register 1 (PM1)
• Port register 1 (P1)
The basic procedure of setting an operation in the UART mode is as follows.
<1> Set the BRGC0 register (see Figure 14-4).
<2> Set bits 1 to 4 (SL0, CL0, PS00, and PS01) of the ASIM0 register (see Figure 14-2).
<3> Set bit 7 (POWER0) of the ASIM0 register to 1.
<4> Set bit 6 (TXE0) of the ASIM0 register to 1. → Transmission is enabled.
Set bit 5 (RXE0) of the ASIM0 register to 1. → Reception is enabled.
<5> Write data to the TXS0 register. → Data transmission is started.
Caution Take relationship with the other party of communication when setting the port mode register
and port register.
The relationship between the register settings and pins is shown below.
Table 14-2. Relationship Between Register Settings and Pins
Pin Function POWER0 TXE0 RXE0 PM10 P10 PM11 P11 UART0
Operation TxD0/SCK10/P10 RxD0/SI10/P11
0 0 0 ×Note ×Note ×Note ×Note Stop SCK10/P10 SI10/P11
0 1 ×Note ×Note 1 × Reception SCK10/P10 RxD0
1 0 0 1 ×Note ×Note Transmission TxD0 SI10/P11
1
1 1 0 1 1 × Transmission/
reception
TxD0 RxD0
Note Can be set as port function or serial interface CSI10.
Remark ×: don’t care
POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)
TXE0: Bit 6 of ASIM0
RXE0: Bit 5 of ASIM0
PM1×: Port mode register
P1×: Port output latch
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 325
(2) Communication operation
(a) Format and waveform example of normal transmit/receive data
Figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data.
Figure 14-6. Format of Normal UART Transmit/Receive Data
Start
bit
Parity
bit
D0 D1 D2 D3 D4
1 data frame
Character bits
D5 D6 D7 Stop bit
One data frame consists of the following bits.
• Start bit ... 1 bit
• Character bits ... 7 or 8 bits (LSB first)
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface operation mode register 0 (ASIM0).
Figure 14-7. Example of Normal UART Transmit/Receive Data Waveform
1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 Parity StopStop
3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
326
(b) Parity types and operation
The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
(i) Even parity
• Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Reception is performed assuming that there is no parity bit when data is received. Because there is no
parity bit, a parity error does not occur.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 327
(c) Transmission
If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6
(TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit
data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to
the data.
When transmission is started, the start bit is output from the TXD0 pin, and the transmit data is output
followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity
and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is
generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
transmission completion interrupt signal (INTST0) is generated.
Figure 14-8. Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
INTST0
D0Start D1 D2 D6 D7 Stop
TXD0 (output) Parity
2. Stop bit length: 2
TXD0 (output)
INTST0
D0Start D1 D2 D6 D7 Parity Stop
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
328
(d) Reception
Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial
interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is
detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the
RXD0 pin input is sampled again ( in Figure 14-9). If the RXD0 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift
register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an
overrun error (OVE0) occurs, however, the receive data is not written to RXB0.
Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an reception error interrupt (INTSR0) is generated after completion of reception.
INTSR0 occurs upon completion of reception and in case of a reception error.
Figure 14-9. Reception Completion Interrupt Request Timing
RXD0 (input)
INTSR0
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
RXB0
Cautions 1. If a reception error occurs, read asynchronous serial interface reception error status
register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 329
(e) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data
reception, a reception error interrupt (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception
error interrupt (INTSR0) servicing (see Figure 14-3).
The contents of ASIS0 are cleared to 0 when ASIS0 is read.
Table 14-3. Cause of Reception Error
Reception Error Cause
Parity error The parity specified for transmission does not match the parity of the receive data.
Framing error Stop bit is not detected.
Overrun error Reception of the next data is completed before data is read from receive buffer
register 0 (RXB0).
(f) Noise filter of receive data
The RXD0 signal is sampled using the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 14-10, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Figure 14-10. Noise Filter Circuit
Internal signal B
Internal signal A
Match detector
In
Base clock
R
X
D0/SI10/P11 QIn
LD_EN
Q
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
330
14.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and
generates a serial clock for transmission/reception of UART0.
Separate 5-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
• Base clock
The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is
supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0
(ASIM0) is 1. This clock is called the base clock and its frequency is called fXCLK0. The base clock is fixed
to low level when POWER0 = 0.
• Transmission counter
This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial
interface operation mode register 0 (ASIM0) is 0.
It starts counting when POWER0 = 1 and TXE0 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0).
• Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial
interface operation mode register 0 (ASIM0) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
Figure 14-11. Configuration of Baud Rate Generator
f
XCLK0
Selector
POWER0
5-bit counter
Match detector Baud rate
BRGC0: MDL04 to MDL00
1/2
POWER0, TXE0 (or RXE0)
BRGC0: TPS01, TPS00
8-bit timer/
event counter
50 output
f
PRS
/2
5
f
PRS
/2
f
PRS
/2
3
Baud rate generator
Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)
TXE0: Bit 6 of ASIM0
RXE0: Bit 5 of ASIM0
BRGC0: Baud rate generator control register 0
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 331
(2) Generation of serial clock
A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0).
Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0.
Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (fXCLK0/8 to fXCLK0/31) of the 5-bit
counter.
14.4.4 Calculation of baud rate
(1) Baud rate calculation expression
The baud rate can be calculated by the following expression.
• Baud rate = [bps]
fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register
k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
Table 14-4. Set Value of TPS01 and TPS00
Base clock (fXCLK0) selection TPS01 TPS00
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz fPRS = 20 MHz
0 0 TM50 output
0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz
1 0 fPRS/23 250 kHz 625 kHz 1.25 MHz 2.5 MHz
1 1 fPRS/25 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz
(2) Error of baud rate
The baud rate error can be calculated by the following expression.
• Error (%) = − 1 × 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the
reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz
Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16)
Target baud rate = 76,800 bps
Baud rate = 2.5 M/(2 × 16)
= 2,500,000/(2 × 16) = 78,125 [bps]
Error = (78,125/76,800 − 1) × 100
= 1.725 [%]
fXCLK0
2 × k
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
332
(3) Example of setting baud rate
Table 14-5. Set Data of Baud Rate Generator
fPRS = 2.0 MHz fPRS = 5.0 MHz fPRS = 10.0 MHz fPRS = 20.0 MHz
Baud
Rate
[bps]
TPS01,
TPS00
k Calculated
Value
ERR
[%]
TPS01,
TPS00
k Calculated
Value
ERR
[%]
TPS01,
TPS00
k Calculated
Value
ERR
[%]
TPS01,
TPS00
k Calculated
Value
ERR
[%]
4800 2H 26 4808 0.16 3H 16 4883 1.73 − − − − − − − −
9600 2H 13 9615 0.16 3H 8 9766 1.73 3H 16 9766 1.73 − − − −
10400 2H 12 10417 0.16 2H 30 10417 0.16 3H 15 10417 0.16 3H 30 10417 0.16
19200 1H 26 19231 0.16 2H 16 19531 1.73 3H 8 19531 1.73 3H 16 19531 1.73
24000 1H 21 23810 −0.79 2H 13 24038 0.16 2H 26 24038 0.16 3H 13 24038 0.16
31250 1H 16 31250 0 2H 10 31250 0 2H 20 31250 0 3H 10 31250 0
33660 1H 15 33333 −0.79 2H 9 34722 3.34 2H 18 34722 3.34 3H 9 34722 3.34
38400 1H 13 38462 0.16 2H 8 39063 1.73 2H 16 39063 1.73 3H 8 39063 1.73
56000 1H 9 55556 −0.79 1H 22 56818 1.46 2H 11 56818 1.46 2H 22 56818 1.46
62500 1H 8 62500 0 1H 20 62500 0 2H 10 62500 0 2H 20 62500 0
76800 − − − − 1H 16 78125 1.73 2H 8 78125 1.73 2H 16 78125 1.73
115200 − − − − 1H 11 113636 −1.36 1H 22 113636 −1.36 2H 11 113636 −1.36
153600 − − − − 1H 8 156250 1.73 1H 16 156250 1.73 2H 8 156250 1.73
312500 − − − − − − − − 1H 8 312500 0 1H 16 312500 0
625000 − − − − − − − − − − − − 1H 8 625000 0
Remark TPS01, TPS00: Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock
(fXCLK0))
k: Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31)
f
PRS: Peripheral hardware clock frequency
ERR: Baud rate error
<R>
<R>
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD 333
(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 14-12. Permissible Baud Rate Range During Reception
FL
1 data frame (11 × FL)
FLmin
FLmax
Data frame length
of UART0 Start bit Bit 0 Bit 1 Bit 7 Parity bit
Minimum permissible
data frame length
Maximum permissible
data frame length
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit
Latch timing
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit
As shown in Figure 14-12, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)−1
Brate: Baud rate of UART0
k: Set value of BRGC0
FL: 1-bit data length
Margin of latch timing: 2 clocks
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17473EJ2V0UD
334
Minimum permissible data frame length: FLmin = 11 × FL − × FL = FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
BRmax = (FLmin/11)−1 = Brate
Similarly, the maximum permissible data frame length can be calculated as follows.
10 k + 2 21k − 2
11 2 × k 2 × k
FLmax = FL × 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)−1 = Brate
The permissible baud rate error between UART0 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 14-6. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error
8 +3.53% −3.61%
16 +4.14% −4.19%
24 +4.34% −4.38%
31 +4.44% −4.47%
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
2. k: Set value of BRGC0
k − 2
2k
21k + 2
2k
22k
21k + 2
× FLmax = 11 × FL − × FL = FL
21k – 2
20k
20k
21k − 2
User’s Manual U17473EJ2V0UD 335
CHAPTER 15 SERIAL INTERFACE UART6
15.1 Functions of Serial Interface UART6
Serial interface UART6 has the following two modes.
(1) Operation stop mode
This mode is used when serial communication is not executed and can enable a reduction in the power
consumption.
For details, see 15.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below.
For details, see 15.4.2 Asynchronous serial interface (UART) mode and 15.4.3 Dedicated baud rate
generator.
• Maximum transfer rate: 625 kbps
• Two-pin configuration TXD6: Transmit data output pin
R
XD6: Receive data input pin
• Data length of communication data can be selected from 7 or 8 bits.
• Dedicated internal 8-bit baud rate generator allowing any baud rate to be set
• Transmission and reception can be performed independently (full duplex operation).
• MSB- or LSB-first communication selectable
• Inverted transmission operation
• Sync break field transmission from 13 to 20 bits
• More than 11 bits can be identified for sync break field reception (SBF reception flag provided).
Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception
side. To use this function, the reception side must be ready for reception of inverted data.
2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD6 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.
3. Set POWER6 = 1 and then set TXE6 = 1 (transmission) or RXE6 = 1 (reception) to start
communication.
4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable
transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock
after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the
base clock, the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
6. If data is continuously transmitted, the communication timing from the stop bit to the next
start bit is extended two operating clocks of the macro. However, this does not affect the
result of communication because the reception side initializes the timing when it has
detected a start bit. Do not use the continuous transmission function if the interface is
incorporated in LIN communication operation.
<R>
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
336
Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication
protocol intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one
master.
The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the
LIN master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave
is ±15% or less.
Figures 15-1 and 15-2 outline the transmission and reception operations of LIN.
Figure 15-1. LIN Transmission Operation
LIN Bus
Wakeup
signal frame
8 bits
Note 1
55H
transmission
Data
transmission
Data
transmission
Data
transmission
Data
transmission
13-bit
Note 2
SBF
transmission
Sync
break field
Sync field Identifier
field
Data field Data field Checksum
field
TX6
(output)
INTST6
Note 3
Notes 1. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode.
2. The sync break field is output by hardware. The output width is the bit length set by bits 4 to 2 (SBL62
to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 15.4.2 (2) (h) SBF
transmission).
3. INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.
Remark The interval between each field is controlled by software.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 337
Figure 15-2. LIN Reception Operation
LIN Bus
13-bit
SBF reception
SF
reception
ID
reception
Data
reception
Data
reception
Data
reception
Wakeup
signal frame
Sync
break field
Sync field Identifier
field
Data field Data field Checksum
field
RXD6
(input)
Reception interrupt
(INTSR6)
Edge detection
(INTP0)
Capture timer Disable Enable
Disable Enable
<1>
<2>
<3>
<4>
<5>
Reception processing is as follows.
<1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception
mode.
<2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has
been detected, it is assumed that SBF reception has been completed correctly, and an interrupt signal is
output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF
reception error has occurred. The interrupt signal is not output and the SBF reception mode is restored.
<3> If SBF reception has been completed correctly, an interrupt signal is output. Start 16-bit timer/event counter
00 by the SBF reception end interrupt servicing and measure the bit interval (pulse width) of the sync field
(see 7.4.8 Pulse width measurement operation). Detection of errors OVE6, PE6, and FE6 is
suppressed, and error detection processing of UART communication and data transfer of the shift register
and RXB6 is not performed. The shift register holds the reset value FFH.
<4> Calculate the baud rate error from the bit interval of the sync field, disable UART6 after SF reception, and
then re-set baud rate generator control register 6 (BRGC6).
<5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after
reception of the checksum field and to set the SBF reception mode again.
Figure 15-3 shows the port configuration for LIN reception operation.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt
(INTP0). The length of the sync field transmitted from the LIN master can be measured using the external event
capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.
The input source of the reception port input (RXD6) can be input to the external interrupt (INTP0) and 16-bit
timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RXD6 and INTP0/TI000 externally.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
338
Figure 15-3. Port Configuration for LIN Reception Operation
RXD6 input
INTP0 input
TI000 input
P14/RxD6
P120/INTP0/EXLVI
P00/TI000
Port input
switch control
(ISC0)
<ISC0>
0: Select INTP0 (P120)
1: Select RxD6 (P14)
Port mode
(PM14)
Output latch
(P14)
Port mode
(PM120)
Output latch
(P120)
Port input
switch control
(ISC1)
<ISC1>
0: Select TI000 (P00)
1: Select RxD6 (P14)
Selector Selector
Selector
Selector
Selector
Port mode
(PM00)
Output latch
(P00)
Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 15-11)
The peripheral functions used in the LIN communication operation are shown below.
<Peripheral functions used>
• External interrupt (INTP0); wakeup signal detection
Use: Detects the wakeup signal edges and detects start of communication.
• 16-bit timer/event counter 00 (TI000); baud rate error detection
Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the
sync field (SF) length and divides it by the number of bits.
• Serial interface UART6
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 339
15.2 Configuration of Serial Interface UART6
Serial interface UART6 includes the following hardware.
Table 15-1. Configuration of Serial Interface UART6
Item Configuration
Registers Receive buffer register 6 (RXB6)
Receive shift register 6 (RXS6)
Transmit buffer register 6 (TXB6)
Transmit shift register 6 (TXS6)
Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
Input switch control register (ISC)
Port mode register 1 (PM1)
Port register 1 (P1)
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
340
Figure 15-4. Block Diagram of Serial Interface UART6
Internal bus
Asynchronous serial interface
control register 6 (ASICL6)
Transmit buffer register 6
(TXB6)
Transmit shift register 6
(TXS6)
T
X
D6/
P13
INTST6
Baud rate
generator
Asynchronous serial interface
control register 6 (ASICL6)
Reception control
Receive shift register 6
(RXS6)
Receive buffer register 6
(RXB6)
R
X
D6/
P14
TI000, INTP0Note
INTSR6
Baud rate
generator
Filter
INTSRE6
Asynchronous serial
interface reception error
status register 6 (ASIS6)
Asynchronous serial
interface operation mode
register 6 (ASIM6)
Asynchronous serial
interface transmission
status register 6 (ASIF6)
Transmission control
Registers
fPRS
fPRS/2
fPRS/22
fPRS/23
fPRS/24
fPRS/25
fPRS/26
fPRS/27
fPRS/28
fPRS/29
fPRS/210
8-bit timer/
event counter
50 output
8
Reception unit
Transmission unit
Clock selection
register 6 (CKSR6)
Baud rate generator
control register 6
(BRGC6)
Output latch
(P13)
PM13
8
Selector
Note Selectable with input switch control register (ISC).
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 341
(1) Receive buffer register 6 (RXB6)
This 8-bit register stores parallel data converted by receive shift register 6 (RXS6).
Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the
data length is set to 7 bits, data is transferred as follows.
• In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
• In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0.
If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.
RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.
Reset signal generation sets this register to FFH.
(2) Receive shift register 6 (RXS6)
This register converts the serial data input to the RXD6 pin into parallel data.
RXS6 cannot be directly manipulated by a program.
(3) Transmit buffer register 6 (TXB6)
This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.
This register can be read or written by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission
status register 6 (ASIF6) is 1.
2. Do not refresh (write the same value to) TXB6 by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation
mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).
3. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
(4) Transmit shift register 6 (TXS6)
This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from
TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one
frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6
pin at the falling edge of the base clock.
TXS6 cannot be directly manipulated by a program.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
342
15.3 Registers Controlling Serial Interface UART6
Serial interface UART6 is controlled by the following nine registers.
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 1 (PM1)
• Port register 1 (P1)
(1) Asynchronous serial interface operation mode register 6 (ASIM6)
This 8-bit register controls the serial communication operations of serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
Address: FF50H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6
POWER6 Enables/disables operation of internal operation clock
0
Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
1 Enables operation of the internal operation clock
TXE6 Enables/disables transmission
0 Disables transmission (synchronously resets the transmission circuit).
1 Enables transmission
RXE6 Enables/disables reception
0 Disables reception (synchronously resets the reception circuit).
1 Enables reception
Notes 1. The output of the TXD6 pin goes high level and the input from the RXD6 pin is fixed to the high level
when POWER6 = 0 during transmission.
2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 343
Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
PS61 PS60 Transmission operation Reception operation
0 0 Does not output parity bit. Reception without parity
0 1 Outputs 0 parity. Reception as 0 parityNote
1 0 Outputs odd parity. Judges as odd parity.
1 1 Outputs even parity. Judges as even parity.
CL6 Specifies character length of transmit/receive data
0 Character length of data = 7 bits
1 Character length of data = 8 bits
SL6 Specifies number of stop bits of transmit data
0 Number of stop bits = 1
1 Number of stop bits = 2
ISRM6 Enables/disables occurrence of reception completion interrupt in case of error
0 “INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
1 “INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. To start the transmission, set POWER6 to 1 and then set TXE6 to 1. To stop the transmission,
clear TXE6 to 0, and then clear POWER6 to 0.
2. To start the reception, set POWER6 to 1 and then set RXE6 to 1. To stop the reception, clear
RXE6 to 0, and then clear POWER6 to 0.
3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin. If
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
4. TXE6 and RXE6 are synchronized by the base clock (fXCLK6) set by CKSR6. To enable
transmission or reception again, set TXE6 or RXE6 to 1 at least two clocks of the base clock
after TXE6 or RXE6 has been cleared to 0. If TXE6 or RXE6 is set within two clocks of the
base clock, the transmission circuit or reception circuit may not be initialized.
5. Set transmit data to TXB6 at least one base clock (fXCLK6) after setting TXE6 = 1.
6. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
7. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.
8. Clear TXE6 to 0 before rewriting the SL6 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
9. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
344
(2) Asynchronous serial interface reception error status register 6 (ASIS6)
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read
when this register is read. If a reception error occurs, read ASIS6 and then read receive buffer register 6 (RXB6)
to clear the error flag.
Figure 15-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
Address: FF53H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIS6 0 0 0 0 0 PE6 FE6 OVE6
PE6 Status flag indicating parity error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1 If the parity of transmit data does not match the parity bit on completion of reception
FE6 Status flag indicating framing error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1 If the stop bit is not detected on completion of reception
OVE6 Status flag indicating overrun error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1
If receive data is set to the RXB6 register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
asynchronous serial interface operation mode register 6 (ASIM6).
2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop
bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
(RXB6) but discarded.
4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 33 CAUTIONS FOR WAIT.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 345
(3) Asynchronous serial interface transmission status register 6 (ASIF6)
This register indicates the status of transmission by serial interface UART6. It includes two status flag bits
(TXBF6 and TXSF6).
Transmission can be continued without disruption even during an interrupt period, by writing the next data to the
TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0.
Figure 15-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)
Address: FF55H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIF6 0 0 0 0 0 0 TXBF6 TXSF6
TXBF6 Transmit buffer data flag
0 If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)
1 If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6 Transmit shift register data flag
0
If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6
(TXB6) after completion of transfer
1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the
transmit data cannot be guaranteed.
2. To initialize the transmission unit upon completion of continuous transmission, be sure to
check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,
and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the
transmit data cannot be guaranteed.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
346
(4) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
Figure 15-8. Format of Clock Selection Register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60
Base clock (fXCLK6) selection TPS63 TPS62 TPS61 TPS60
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
0 0 0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz
0 0 0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz
0 0 1 0 fPRS/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz
0 0 1 1 fPRS/23 250 kHz 625 kHz 1.25 MHz 2.5 MHz
0 1 0 0 fPRS/24 125 kHz 312.5 kHz 625 kHz 1.25 MHz
0 1 0 1 fPRS/25 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz
0 1 1 0 fPRS/26 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
0 1 1 1 fPRS/27 15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz
1 0 0 0 fPRS/28 7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz
1 0 0 1 fPRS/29 3.906 kHz 9.77 kHz 19.53 kHz 39.06 kHz
1 0 1 0 fPRS/210 1.953 kHz 4.88 kHz 9.77 kHz 19.53 kHz
1 0 1 1 TM50 outputNote
Other than above Setting prohibited
Note Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation
(TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. f
PRS: Peripheral hardware clock frequency
2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 347
(5) Baud rate generator control register 6 (BRGC6)
This register sets the division value of the 8-bit counter of serial interface UART6.
BRGC6 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
Figure 15-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
Address: FF57H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of
8-bit counter
0 0 0 0 0 0 × × × Setting prohibited
0 0 0 0 0 1 0 0 4 fXCLK6/4
0 0 0 0 0 1 0 1 5 fXCLK6/5
0 0 0 0 0 1 1 0 6 fXCLK6/6
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 1 1 1 1 0 0 252 fXCLK6/252
1 1 1 1 1 1 0 1 253 fXCLK6/253
1 1 1 1 1 1 1 0 254 fXCLK6/254
1 1 1 1 1 1 1 1 255 fXCLK6/255
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the
MDL67 to MDL60 bits.
2. The baud rate is the output clock of the 8-bit counter divided by 2.
Remarks 1. f
XCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register
2. k: Value set by MDL67 to MDL60 bits (k = 4, 5, 6, ..., 255)
3. ×: Don’t care
<R>
<R>
<R>
<R>
<R>
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
348
(6) Asynchronous serial interface control register 6 (ASICL6)
This register controls the serial communication operations of serial interface UART6.
ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 16H.
Caution ASICL6 can be refreshed (the same value is written) by software during a communication
operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of
ASIM6 = 1). However, do not set both SBRT6 and SBTT6 to 1 by a refresh operation during SBF
reception (SBRT6 = 1) or SBF transmission (until INTST6 occurs since SBTT6 has been set (1)),
because it may re-trigger SBF reception or SBF transmission.
Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2)
Address: FF58H After reset: 16H R/WNote
Symbol <7> <6> 5 4 3 2 1 0
ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6
SBRF6 SBF reception status flag
0 If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly
1 SBF reception in progress
SBRT6 SBF reception trigger
0 −
1 SBF reception trigger
SBTT6 SBF transmission trigger
0 −
1 SBF transmission trigger
Note Bit 7 is read-only.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 349
Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)
SBL62 SBL61 SBL60 SBF transmission output width control
1 0 1 SBF is output with 13-bit length.
1 1 0 SBF is output with 14-bit length.
1 1 1 SBF is output with 15-bit length.
0 0 0 SBF is output with 16-bit length.
0 0 1 SBF is output with 17-bit length.
0 1 0 SBF is output with 18-bit length.
0 1 1 SBF is output with 19-bit length.
1 0 0 SBF is output with 20-bit length.
DIR6 First-bit specification
0 MSB
1 LSB
TXDLV6 Enables/disables inverting TXD6 output
0 Normal output of TXD6
1 Inverted output of TXD6
Cautions 1. In the case of an SBF reception error, the mode returns to the SBF reception mode. The
status of the SBRF6 flag is held (1).
2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.
After setting the SBRT6 bit to 1, do not clear it to 0 before SBF reception is completed (before
an interrupt request signal is generated).
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
reception has been correctly completed.
4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 =
1. After setting the SBTT6 bit to 1, do not clear it to 0 before SBF transmission is completed
(before an interrupt request signal is generated).
5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of
SBF transmission.
6. Do not set the SBRT6 bit to 1 during reception, and do not set the SBTT6 bit to 1 during
transmission.
7. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
350
(7) Input switch control register (ISC)
The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN
(Local Interconnect Network) reception.
The signal input from the P14/RXD6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1
are set to 1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Figure 15-11. Format of Input Switch Control Register (ISC)
Address: FF4FH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ISC 0 0 0 0 0 0 ISC1 ISC0
ISC1 TI000 input source selection
0 TI000 (P00)
1 RXD6 (P14)
ISC0 INTP0 input source selection
0 INTP0 (P120)
1 RXD6 (P14)
(8) Port mode register 1 (PM1)
This register sets port 1 input/output in 1-bit units.
When using the P13/TXD6 pin for serial interface data output, clear PM13 to 0 and set the output latch of P13 to 1.
When using the P14/RXD6 pin for serial interface data input, set PM14 to 1. The output latch of P14 at this time
may be 0 or 1.
PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 15-12. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 351
15.4 Operation of Serial Interface UART6
Serial interface UART6 has the following two modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
15.4.1 Operation stop mode
In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In
addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and
5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.
(1) Register used
The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).
ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Address: FF50H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6
POWER6 Enables/disables operation of internal operation clock
0
Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
TXE6 Enables/disables transmission
0 Disables transmission operation (synchronously resets the transmission circuit).
RXE6 Enables/disables reception
0 Disables reception (synchronously resets the reception circuit).
Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when
POWER6 = 0 during transmission.
2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to stop the operation.
To start the communication, set POWER6 to 1, and then set TXE6 or RXE6 to 1.
Remark To use the RXD6/P14 and TXD6/P13 pins as general-purpose port pins, see CHAPTER 5 PORT
FUNCTIONS.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
352
15.4.2 Asynchronous serial interface (UART) mode
In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be
performed.
A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of
baud rates.
(1) Registers used
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 1 (PM1)
• Port register 1 (P1)
The basic procedure of setting an operation in the UART mode is as follows.
<1> Set the CKSR6 register (see Figure 15-8).
<2> Set the BRGC6 register (see Figure 15-9).
<3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 15-5).
<4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 15-10).
<5> Set bit 7 (POWER6) of the ASIM6 register to 1.
<6> Set bit 6 (TXE6) of the ASIM6 register to 1. → Transmission is enabled.
Set bit 5 (RXE6) of the ASIM6 register to 1. → Reception is enabled.
<7> Write data to transmit buffer register 6 (TXB6). → Data transmission is started.
Caution Take relationship with the other party of communication when setting the port mode register
and port register.
The relationship between the register settings and pins is shown below.
Table 15-2. Relationship Between Register Settings and Pins
Pin Function POWER6 TXE6 RXE6 PM13 P13 PM14 P14 UART6
Operation TXD6/P13 RXD6/P14
0 0 0 ×Note ×Note ×Note ×Note Stop P13 P14
0 1 ×Note ×Note 1 × Reception P13 RXD6
1 0 0 1 ×Note ×Note Transmission TXD6 P14
1
1 1 0 1 1 × Transmission/
reception
TXD6 RXD6
Note Can be set as port function.
Remark ×: don’t care
POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)
TXE6: Bit 6 of ASIM6
RXE6: Bit 5 of ASIM6
PM1×: Port mode register
P1×: Port output latch
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 353
(2) Communication operation
(a) Format and waveform example of normal transmit/receive data
Figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data.
Figure 15-13. Format of Normal UART Transmit/Receive Data
1. LSB-first transmission/reception
Start
bit
Parity
bit
D0 D1 D2 D3 D4
1 data frame
Character bits
D5 D6 D7 Stop bit
2. MSB-first transmission/reception
Start
bit
Parity
bit
D7 D6 D5 D4 D3
1 data frame
Character bits
D2 D1 D0 Stop bit
One data frame consists of the following bits.
• Start bit ... 1 bit
• Character bits ... 7 or 8 bits
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface operation mode register 6 (ASIM6).
Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial
interface control register 6 (ASICL6).
Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
354
Figure 15-14. Example of Normal UART Transmit/Receive Data Waveform
1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop
3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin
inverted output
1 data frame
Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop
4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 Parity StopStop
5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 355
(b) Parity types and operation
The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
Caution Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication operation.
(i) Even parity
• Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Reception is performed assuming that there is no parity bit when data is received. Because there is no
parity bit, a parity error does not occur.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
356
(c) Normal transmission
When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit
6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit
data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to
the data.
When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,
the transmit data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the
parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is
generated.
Transmission is stopped until the data to be transmitted next is written to TXB6.
Figure 15-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt
occurs as soon as the last stop bit has been output.
Figure 15-15. Normal Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
INTST6
D0Start D1 D2 D6 D7 Stop
T
X
D6 (output) Parity
2. Stop bit length: 2
T
X
D6 (output)
INTST6
D0Start D1 D2 D6 D7 Parity Stop
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 357
(d) Continuous transmission
The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6
(TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after
transmission of one data frame, data can be continuously transmitted and an efficient communication rate
can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait
for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface
transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred.
To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and
whether the TXB6 register can be written, and then write the data.
Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register change from “10” to “11”, and to “01”
during continuous transmission. To check the status, therefore, do not use a
combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag
when executing continuous transmission.
2. When the device is use in LIN communication operation, the continuous transmission
function cannot be used. Make sure that asynchronous serial interface transmission
status register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6
(TXB6).
TXBF6 Writing to TXB6 Register
0 Writing enabled
1 Writing disabled
Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the
transmit data cannot be guaranteed.
The communication status can be checked using the TXSF6 flag.
TXSF6 Transmission Status
0 Transmission is completed.
1 Transmission is in progress.
Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure
to check that the TXSF6 flag is “0” after generation of the transmission completion
interrupt, and then execute initialization. If initialization is executed while the TXSF6
flag is “1”, the transmit data cannot be guaranteed.
2. During continuous transmission, the next transmission may complete before execution
of INTST6 interrupt servicing after transmission of one data frame. As a
countermeasure, detection can be performed by developing a program that can count
the number of transmit data and by referencing the TXSF6 flag.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
358
Figure 15-16 shows an example of the continuous transmission processing flow.
Figure 15-16. Example of Continuous Transmission Processing Flow
Write TXB6.
Set registers.
Write TXB6.
Transfer
executed necessary
number of times?
Yes
Read ASIF6
TXBF6 = 0?
No
No
Yes
Transmission
completion interrupt
occurs?
Read ASIF6
TXSF6 = 0?
No
No
No
Yes
Yes
Yes
Yes
Completion of
transmission processing
Transfer
executed necessary
number of times?
Remark TXB6: Transmit buffer register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6 (transmit buffer data flag)
TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 359
Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of
ending continuous transmission.
Figure 15-17. Timing of Starting Continuous Transmission
TXD6 Start
INTST6
Data (1)
Data (1) Data (2) Data (3)
Data (2)Data (1) Data (3)
FF
FF
Parity Stop Data (2) Parity Stop
TXB6
TXS6
TXBF6
TXSF6
Start Start
Note
Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether
writing is enabled using only the TXBF6 bit.
Remark T
XD6: TXD6 pin (output)
INTST6: Interrupt request signal
TXB6: Transmit buffer register 6
TXS6: Transmit shift register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6
TXSF6: Bit 0 of ASIF6
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
360
Figure 15-18. Timing of Ending Continuous Transmission
T
X
D6 Start
INTST6
Data (n − 1)
Data (n − 1) Data (n)
Data (n)Data (n − 1) FF
Parity
Stop Stop Data (n) Parity Stop
TXB6
TXS6
TXBF6
TXSF6
POWER6 or TXE6
Start
Remark TXD6: TXD6 pin (output)
INTST6: Interrupt request signal
TXB6: Transmit buffer register 6
TXS6: Transmit shift register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6
TXSF6: Bit 0 of ASIF6
POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6)
TXE6: Bit 6 of asynchronous serial interface operation mode register (ASIM6)
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 361
(e) Normal reception
Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial
interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is
detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the
RXD6 pin input is sampled again ( in Figure 15-19). If the RXD6 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt
(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun
error (OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of
reception.
Figure 15-19. Reception Completion Interrupt Request Timing
RXD6 (input)
INTSR6
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity
RXB6
Stop
Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise,
an overrun error will occur when the next data is received, and the reception error
status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
before reading RXB6.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
362
(f) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data
reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception
error interrupt (INTSR6/INTSRE6) servicing (see Figure 15-6).
The contents of ASIS6 are cleared to 0 when ASIS6 is read.
Table 15-3. Cause of Reception Error
Reception Error Cause
Parity error The parity specified for transmission does not match the parity of the receive data.
Framing error Stop bit is not detected.
Overrun error Reception of the next data is completed before data is read from receive buffer
register 6 (RXB6).
The reception error interrupt can be separated into reception completion interrupt (INTSR6) and error
interrupt (INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6
(ASIM6) to 0.
Figure 15-20. Reception Error Interrupt
1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are
separated)
(a) No error during reception (b) Error during reception
INTSR6
INTSRE6
INTSR6
INTSRE6
2. If ISRM6 is set to 1 (error interrupt is included in INTSR6)
(a) No error during reception (b) Error during reception
INTSRE6
INTSR6
INTSRE6
INTSR6
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 363
(g) Noise filter of receive data
The RXD6 signal is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 15-21, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Figure 15-21. Noise Filter Circuit
Internal signal B
Internal signal A
Match detector
In
Base clock
R
X
D6/P14 QIn
LD_EN
Q
(h) SBF transmission
When the device is use in LIN communication operation, the SBF (Synchronous Break Field) transmission
control function is used for transmission. For the transmission operation of LIN, see Figure 15-1 LIN
Transmission Operation.
When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TXD6 pin
outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered,
and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6
(ASICL6) to 1.
Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following
the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and
SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored.
Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6),
or until SBTT6 is set to 1.
Figure 15-22. SBF Transmission
T
X
D6
INTST6
SBTT6
1 2 3 4 5 6 7 8 9 10 11 12 13 Stop
Remark T
XD6: TXD6 pin (output)
INTST6: Transmission completion interrupt request
SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
364
(i) SBF reception
When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception
control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception
Operation.
Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6
(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6)
of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,
the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable
status.
When the start bit has been detected, reception is started, and serial data is sequentially stored in the
receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is
11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At
this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of
errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status
register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed.
In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not
performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not
occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In
this case, the SBRF6 and SBRT6 bits are not cleared.
Figure 15-23. SBF Reception
1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
RXD6
SBRT6
/SBRF6
INTSR6
1234567891011
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
R
X
D6
SBRT6
/SBRF6
INTSR6
12345678910
“0”
Remark RXD6: RXD6 pin (input)
SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)
SBRF6: Bit 7 of ASICL6
INTSR6: Reception completion interrupt request
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 365
15.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and
generates a serial clock for transmission/reception of UART6.
Separate 8-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
• Base clock
The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to
each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is
1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level
when POWER6 = 0.
• Transmission counter
This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial
interface operation mode register 6 (ASIM6) is 0.
It starts counting when POWER6 = 1 and TXE6 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6).
If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been
completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues
counting until POWER6 or TXE6 is cleared to 0.
• Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial
interface operation mode register 6 (ASIM6) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
366
Figure 15-24. Configuration of Baud Rate Generator
Selector
POWER6
8-bit counter
Match detector Baud rate
Baud rate generator
BRGC6: MDL67 to MDL60
1/2
POWER6, TXE6 (or RXE6)
CKSR6: TPS63 to TPS60
f
PRS
f
PRS
/2
f
PRS
/2
2
f
PRS
/2
3
f
PRS
/2
4
f
PRS
/2
5
f
PRS
/2
6
f
PRS
/2
7
f
PRS
/2
8
f
PRS
/2
9
f
PRS
/2
10
8-bit timer/
event counter
50 output
f
XCLK6
Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)
TXE6: Bit 6 of ASIM6
RXE6: Bit 5 of ASIM6
CKSR6: Clock selection register 6
BRGC6: Baud rate generator control register 6
(2) Generation of serial clock
A serial clock to be generated can be specified by using clock selection register 6 (CKSR6) and baud rate
generator control register 6 (BRGC6).
The clock to be input to the 8-bit counter can be set by bits 3 to 0 (TPS63 to TPS60) of CKSR6 and the division
value (fXCLK6/4 to fXCLK6/255) of the 8-bit counter can be set by bits 7 to 0 (MDL67 to MDL60) of BRGC6.
<R>
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 367
15.4.4 Calculation of baud rate
(1) Baud rate calculation expression
The baud rate can be calculated by the following expression.
• Baud rate = [bps]
fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register
k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255)
Table 15-4. Set Value of TPS63 to TPS60
Base Clock (fXCLK6) Selection TPS63 TPS62 TPS61 TPS60
f
PRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
0 0 0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz
0 0 0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz
0 0 1 0 fPRS/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz
0 0 1 1 fPRS/23 250 kHz 625 kHz 1.25 MHz 2.5 MHz
0 1 0 0 fPRS/24 125 kHz 312.5 kHz 625 kHz 1.25 MHz
0 1 0 1 fPRS/25 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz
0 1 1 0 fPRS/26 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
0 1 1 1 fPRS/27 15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz
1 0 0 0 fPRS/28 7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz
1 0 0 1 fPRS/29 3.906 kHz 9.77 kHz 19.53 kHz 39.06 kHz
1 0 1 0 fPRS/210 1.953 kHz 4.88 kHz 9.77 kHz 19.53 kHz
1 0 1 1 TM50 output
Other than above Setting prohibited
(2) Error of baud rate
The baud rate error can be calculated by the following expression.
• Error (%) = − 1 × 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the
reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Frequency of base clock = 10 MHz = 10,000,000 Hz
Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)
Target baud rate = 153600 bps
Baud rate = 10 M/(2 × 33)
= 10000000/(2 × 33) = 151,515 [bps]
Error = (151515/153600 − 1) × 100
= −1.357 [%]
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)
fXCLK6
2 × k
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
368
(3) Example of setting baud rate
Table 15-5. Set Data of Baud Rate Generator
fPRS = 2.0 MHz fPRS = 5.0 MHz fPRS = 10.0 MHz fPRS = 20.0 MHz
Baud
Rate
[bps]
TPS63-
TPS60
k Calculated
Value
ERR
[%]
TPS63-
TPS60
k Calculated
Value
ERR
[%]
TPS63-
TPS60
k Calculated
Value
ERR
[%]
TPS63-
TPS60
k Calculated
Value
ERR
[%]
300 8H 13 301 0.16 7H 65 301 0.16 8H 65 301 0.16 9H 65 301 0.16
600 7H 13 601 0.16 6H 65 601 0.16 7H 65 601 0.16 8H 65 601 0.16
1200 6H 13 1202 0.16 5H 65 1202 0.16 6H 65 1202 0.16 7H 65 1202 0.16
2400 5H 13 2404 0.16 4H 65 2404 0.16 5H 65 2404 0.16 6H 65 2404 0.16
4800 4H 13 4808 0.16 3H 65 4808 0.16 4H 65 4808 0.16 5H 65 4808 0.16
9600 3H 13 9615 0.16 2H 65 9615 0.16 3H 65 9615 0.16 4H 65 9615 0.16
19200 2H 13 19231 0.16 1H 65 19231 0.16 2H 65 19231 0.16 3H 65 19231 0.16
24000 1H 21 23810 −0.79 3H 13 24038 0.16 4H 13 24038 0.16 5H 13 24038 0.16
31250 1H 4 31250 0 4H 5 31250 0 5H 5 31250 0 6H 5 31250 0
38400 1H 13 38462 0.16 0H 65 38462 0.16 1H 65 38462 0.16 2H 65 38462 0.16
48000 0H 21 47619 −0.79 2H 13 48077 0.16 3H 13 48077 0.16 4H 13 48077 0.16
76800 0H 13 76923 0.16 0H 33 75758 −1.36 0H 65 76923 0.16 1H 65 76923 0.16
115200 0H 9 111111 −3.55 1H 11 113636 −1.36 0H 43 116279 0.94 0H 87 114943 −0.22
153600 − − − − 1H 8 156250 1.73 0H 33 151515 −1.36 1H 33 151515 −1.36
312500 − − − − 0H 8 312500 0 1H 8 312500 0 2H 8 312500 0
625000 − − − − 0H 4 625000 0 1H 4 625000 0 2H 4 625000 0
Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6))
k: Value set by MDL67 to MDL60 bits of baud rate generator control register 6
(BRGC6) (k = 4, 5, 6, ..., 255)
f
PRS: Peripheral hardware clock frequency
ERR: Baud rate error
<R>
<R>
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 369
(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 15-25. Permissible Baud Rate Range During Reception
FL
1 data frame (11 × FL)
FLmin
FLmax
Data frame length
of UART6 Start bit Bit 0 Bit 1 Bit 7 Parity bit
Minimum permissible
data frame length
Maximum permissible
data frame length
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit
Latch timing
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit
As shown in Figure 15-25, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)−1
Brate: Baud rate of UART6
k: Set value of BRGC6
FL: 1-bit data length
Margin of latch timing: 2 clocks
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD
370
Minimum permissible data frame length: FLmin = 11 × FL − × FL = FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
BRmax = (FLmin/11)−1 = Brate
Similarly, the maximum permissible data frame length can be calculated as follows.
10 k + 2 21k − 2
11 2 × k 2 × k
FLmax = FL × 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)−1 = Brate
The permissible baud rate error between UART6 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 15-6. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error
4 +2.33% −2.44%
8 +3.53% −3.61%
20 +4.26% −4.31%
50 +4.56% −4.58%
100 +4.66% −4.67%
255 +4.72% −4.73%
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
2. k: Set value of BRGC6
22k
21k + 2
× FLmax = 11 × FL − × FL = FL
21k – 2
20k
20k
21k − 2
k − 2
2k
21k + 2
2k
<R>
CHAPTER 15 SERIAL INTERFACE UART6
User’s Manual U17473EJ2V0UD 371
(5) Data frame length during continuous transmission
When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by
two clocks of base clock from the normal value. However, the result of communication is not affected because
the timing is initialized on the reception side when the start bit is detected.
Figure 15-26. Data Frame Length During Continuous Transmission
Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit
FL
1 data frame
FL FL FL FL FLFLFLstp
Start bit of
second byte
Start bit Bit 0
Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following
expression is satisfied.
FLstp = FL + 2/fXCLK6
Therefore, the data frame length during continuous transmission is:
Data frame length = 11 × FL + 2/fXCLK6
User’s Manual U17473EJ2V0UD
372
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
The
μ
PD78F0393 incorporates serial interface CSI10, and the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and
78F0397D incorporate serial interfaces CSI10 and CSI11.
16.1 Functions of Serial Interfaces CSI10 and CSI11
Serial interfaces CSI10 and CSI11 have the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial communication is not performed and can enable a reduction in the power
consumption.
For details, see 16.4.1 Operation stop mode.
(2) 3-wire serial I/O mode (MSB/LSB-first selectable)
This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK1n) and two serial data
lines (SI1n and SO1n).
The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission
and reception can be simultaneously executed.
In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can
be connected to any device.
The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial
interface.
For details, see 16.4.2 3-wire serial I/O mode.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 373
16.2 Configuration of Serial Interfaces CSI10 and CSI11
Serial interfaces CSI10 and CSI11 include the following hardware.
Table 16-1. Configuration of Serial Interfaces CSI10 and CSI11
Item Configuration
Controller Transmit controller
Clock start/stop controller & clock phase controller
Registers Transmit buffer register 1n (SOTB1n)
Serial I/O shift register 1n (SIO1n)
Control registers Serial operation mode register 1n (CSIM1n)
Serial clock selection register 1n (CSIC1n)
Port mode register 0 (PM0) or port mode register 1 (PM1)
Port register 0 (P0) or port register 1 (P1)
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Figure 16-1. Block Diagram of Serial Interface CSI10
Internal bus
SI10/P11/R
X
D0
INTCSI10
f
PRS
/2
f
PRS
/2
2
f
PRS
/2
3
f
PRS
/2
4
f
PRS
/2
5
f
PRS
/2
6
f
PRS
/2
7
SCK10/P10/TxD0
Transmit buffer
register 10 (SOTB10)
Transmit controller
Clock start/stop controller &
clock phase controller
Serial I/O shift
register 10 (SIO10)
Output
selector SO10/P12
Output latch
8
Transmit data
controller
8
Output latch
(P12) PM12
(a)
Baud rate generator
Output latch
(P10)
PM10
Selector
Remark (a): SO10 output
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
374
Figure 16-2. Block Diagram of Serial Interface CSI11
(Available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D)
88
Internal bus
Output
selector
Output latch
Transmit controller
Clock start/stop controller &
clock phase controller
SO11/P02
INTCSI11
Transmit buffer
register 11 (SOTB11)
Transmit data
controller
SI11/P03 Serial I/O shift
register 11 (SIO11)
f
PRS
/2
f
PRS
/2
2
f
PRS
/2
3
f
PRS
/2
4
f
PRS
/2
5
f
PRS
/2
6
f
PRS
/2
7
SSI11
Output latch
(P02)
PM02
(a)
Baud rate generator
Output latch
(P04)
PM04
SCK11/P04
SSI11
Selector
Remark (a): SO11 output
(1) Transmit buffer register 1n (SOTB1n)
This register sets the transmit data.
Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial
operation mode register 1n (CSIM1n) is 1.
The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and
output to the serial output pin (SO1n).
SOTB1n can be written or read by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication).
2. In the slave mode, transmission/reception is started when data is written to SOTB11 with a
low level input to the SSI11 pin. For details on the transmission/reception operation, see
16.4.2 (2) Communication operation.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 375
(2) Serial I/O shift register 1n (SIO1n)
This is an 8-bit register that converts data from parallel data into serial data and vice versa.
This register can be read by an 8-bit memory manipulation instruction.
Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n)
is 0.
During reception, the data is read from the serial input pin (SI1n) to SIO1n.
Reset signal generation sets this register to 00H.
Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication).
2. In the slave mode, reception is started when data is read from SIO11 with a low level input
to the SSI11 pin. For details on the reception operation, see 16.4.2 (2) Communication
operation.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
376
16.3 Registers Controlling Serial Interfaces CSI10 and CSI11
Serial interfaces CSI10 and CSI11 are controlled by the following four registers.
• Serial operation mode register 1n (CSIM1n)
• Serial clock selection register 1n (CSIC1n)
• Port mode register 0 (PM0) or port mode register 1 (PM1)
• Port register 0 (P0) or port register 1 (P1)
(1) Serial operation mode register 1n (CSIM1n)
CSIM1n is used to select the operation mode and enable or disable operation.
CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Figure 16-3. Format of Serial Operation Mode Register 10 (CSIM10)
Address: FF80H After reset: 00H R/WNote 1
Symbol <7> 6 5 4 3 2 1 0
CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10
CSIE10 Operation control in 3-wire serial I/O mode
0 Disables operationNote 2 and asynchronously resets the internal circuitNote 3.
1 Enables operation
TRMD10Note 4 Transmit/receive mode control
0
Note 5 Receive mode (transmission disabled).
1 Transmit/receive mode
DIR10Note 6 First bit specification
0 MSB
1 LSB
CSOT10 Communication status flag
0 Communication is stopped.
1 Communication is in progress.
Notes 1. Bit 0 is a read-only bit.
2. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default status
(00H).
3. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.
4. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication).
5. The SO10 output (see (a) in Figure 16-1) is fixed to the low level when TRMD10 is 0. Reception is
started when data is read from SIO10.
6. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication).
Caution Be sure to clear bit 5 to 0.
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 377
Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11)
Address: FF88H After reset: 00H R/WNote 1
Symbol <7> 6 5 4 3 2 1 0
CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11
CSIE11 Operation control in 3-wire serial I/O mode
0 Disables operationNote 2 and asynchronously resets the internal circuitNote 3.
1 Enables operation
TRMD11Note 4 Transmit/receive mode control
0
Note 5 Receive mode (transmission disabled).
1 Transmit/receive mode
SSE11Notes 6, 7 SSI11 pin use selection
0 SSI11 pin is not used
1 SSI11 pin is used
DIR11Note 8 First bit specification
0 MSB
1 LSB
CSOT11 Communication status flag
0 Communication is stopped.
1 Communication is in progress.
Notes 1. Bit 0 is a read-only bit.
2. To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in the
default status (00H).
3. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset.
4. Do not rewrite TRMD11 when CSOT11 = 1 (during serial communication).
5. The SO11 output (see (a) in Figure 16-2) is fixed to the low level when TRMD11 is 0. Reception is
started when data is read from SIO11.
6. Do not rewrite SSE11 when CSOT11 = 1 (during serial communication).
7. Before setting this bit to 1, fix the SSI11 pin input level to 0 or 1.
8. Do not rewrite DIR11 when CSOT11 = 1 (during serial communication).
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
378
(2) Serial clock selection register 1n (CSIC1n)
This register specifies the timing of the data transmission/reception and sets the serial clock.
CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Figure 16-5. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CSIC10 0 0 0 CKP10 DAP10 CKS102 CKS101 CKS100
CKP10 DAP10 Specification of data transmission/reception timing Type
0 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
1
0 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
2
1 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
3
1 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK10
SO10
SI10 input timing
4
CSI10 serial clock selection CKS102 CKS101 CKS100
f
PRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
Mode
0 0 0 fPRS/2 1 MHz 2.5 MHz 5 MHz Setting
prohibited
0 0 1 fPRS/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz
0 1 0 fPRS/23 250 kHz 625 kHz 1.25 MHz 2.5 MHz
0 1 1 fPRS/24 125 kHz 312.5 kHz 625 kHz 1.25 MHz
1 0 0 fPRS/25 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz
1 0 1 fPRS/26 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
1 1 0 fPRS/27 15.63 kHz 39.06 kHz 78.13 kHz 156.25 kHz
Master mode
1 1 1 External clock input to SCK10 Slave mode
Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled).
2. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIC10 in the default
status (00H).
3. The phase type of the data clock is type 1 after reset.
Remark f
PRS: Peripheral hardware clock frequency
<R>
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 379
Figure 16-6. Format of Serial Clock Selection Register 11 (CSIC11)
Address: FF89H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CSIC11 0 0 0 CKP11 DAP11 CKS112 CKS111 CKS110
CKP11 DAP11 Specification of data transmission/reception timing Type
0 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK11
SO11
SI11 input timing
1
0 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK11
SO11
SI11 input timing
2
1 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK11
SO11
SI11 input timing
3
1 1
D7 D6 D5 D4 D3 D2 D1 D0
SCK11
SO11
SI11 input timing
4
CSI11 serial clock selection CKS112 CKS111 CKS110
fPRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
Mode
0 0 0 fPRS/2 1 MHz 2.5 MHz 5 MHz Setting
prohibited
0 0 1 fPRS/22 500 kHz 1.25 MHz 2.5 MHz 5 MHz
0 1 0 fPRS/23 250 kHz 625 kHz 1.25 MHz 2.5 MHz
0 1 1 fPRS/24 125 kHz 312.5 kHz 625 kHz 1.25 MHz
1 0 0 fPRS/25 62.5 kHz 156.25 kHz 312.5 kHz 625 kHz
1 0 1 fPRS/26 31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
1 1 0 fPRS/27 15.63 kHz 39.06 kHz 78.13 kHz 156.25 kHz
Master mode
1 1 1 External clock input to SCK11 Slave mode
Cautions 1. Do not write to CSIC11 while CSIE11 = 1 (operation enabled).
2. To use P02/SO11 and P04/SCK11 as general-purpose ports, set CSIC11 in the default status
(00H).
3. The phase type of the data clock is type 1 after reset.
Remark fPRS: Peripheral hardware clock frequency
<R>
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
380
(3) Port mode registers 0 and 1 (PM0, PM1)
These registers set port 0 and 1 input/output in 1-bit units.
When using P10/SCK10 and P04/SCK11Note as the clock output pins of the serial interface, clear PM10 and PM04
to 0, and set the output latches of P10 and P04 to 1.
When using P12/SO10 and P02/SO11Note as the data output pins of the serial interface, clear PM12, PM02, and
the output latches of P12 and P02 to 0.
When using P10/SCK10 and P04/SCK11Note as the clock input pins of the serial interface, P11/SI10/RXD0 and
P03/SI11Note as the data input pins, and P05/SSI11 Note/TI001 as the chip select input pin, set PM10, PM04, PM11,
PM03, and PM05 to 1. At this time, the output latches of P10, P04, P11, P03, and P05 may be 0 or 1.
PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Note Available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
Figure 16-7. Format of Port Mode Register 0 (PM0)
7
1
6
PM06
5
PM05
4
PM04
3
PM03
2
PM02
1
PM01
0
PM00
Symbol
PM0
Address: FF20H After reset: FFH R/W
PM0n
0
1
P0n pin I/O mode selection (n = 0 to 6)
Output mode (output buffer on)
Input mode (output buffer off)
Figure 16-8. Format of Port Mode Register 1 (PM1)
7
PM17
6
PM16
5
PM15
4
PM14
3
PM13
2
PM12
1
PM11
0
PM10
Symbol
PM1
Address: FF21H After reset: FFH R/W
PM1n
0
1
P1n pin I/O mode selection (n = 0 to 7)
Output mode (output buffer on)
Input mode (output buffer off)
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 381
16.4 Operation of Serial Interfaces CSI10 and CSI11
Serial interfaces CSI10 and CSI11 can be used in the following two modes.
• Operation stop mode
• 3-wire serial I/O mode
16.4.1 Operation stop mode
Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In
addition, the P10/SCK10/TXD0, P11/SI10/RXD0, P12/SO10, P02/SO11Note, P03/SI11Note, and P04/SCK11Note pins can
be used as ordinary I/O port pins in this mode.
Note Available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
(1) Register used
The operation stop mode is set by serial operation mode register 1n (CSIM1n).
To set the operation stop mode, clear bit 7 (CSIE1n) of CSIM1n to 0.
(a) Serial operation mode register 1n (CSIM1n)
CSIM1n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets CSIM1n to 00H.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
• Serial operation mode register 10 (CSIM10)
Address: FF80H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10
CSIE10 Operation control in 3-wire serial I/O mode
0 Disables operationNote 1 and asynchronously resets the internal circuitNote 2.
Notes 1. To use P10/SCK10/TXD0 and P12/SO10 as general-purpose ports, set CSIM10 in the default
status (00H).
2. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.
• Serial operation mode register 11 (CSIM11)
Address: FF88H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11
CSIE11 Operation control in 3-wire serial I/O mode
0 Disables operationNote 1 and asynchronously resets the internal circuitNote 2.
Notes 1. To use P02/SO11, P04/SCK11, and P05/SSI11/TI001 as general-purpose ports, set CSIM11 in
the default status (00H).
2. Bit 0 (CSOT11) of CSIM11 and serial I/O shift register 11 (SIO11) are reset.
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
382
16.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial
interface.
In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and
serial input (SI1n) lines.
(1) Registers used
• Serial operation mode register 1n (CSIM1n)
• Serial clock selection register 1n (CSIC1n)
• Port mode register 0 (PM0) or port mode register 1 (PM1)
• Port register 0 (P0) or port register 1 (P1)
The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows.
<1> Set the CSIC1n register (see Figures 16-5 and 16-6).
<2> Set bits 4 to 6 (DIR1n, SSE11 (serial interface CSI11 only), and TRMD1n) of the CSIM1n register (see
Figures 16-3 and 16-4).
<3> Set bit 7 (CSIE1n) of the CSIM1n register to 1. → Transmission/reception is enabled.
<4> Write data to transmit buffer register 1n (SOTB1n). → Data transmission/reception is started.
Read data from serial I/O shift register 1n (SIO1n). → Data reception is started.
Caution Take relationship with the other party of communication when setting the port mode register
and port register.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 383
The relationship between the register settings and pins is shown below.
Table 16-2. Relationship Between Register Settings and Pins (1/2)
(a) Serial interface CSI10
Pin Function CSIE10 TRMD10 PM11 P11 PM12 P12 PM10 P10 CSI10
Operation SI10/RXD0/
P11
SO10/P12 SCK10/
TXD0/P10
0 × ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 Stop RXD0/P11 P12 TXD0/
P10Note 2
1 0 1 × ×Note 1 ×Note 1 1 × Slave
receptionNote 3
SI10 P12
SCK10
(input)Note 3
1 1 ×Note 1 ×Note 1 0 0 1 × Slave
transmissionNote 3
RXD0/P11 SO10 SCK10
(input)Note 3
1 1 1 × 0 0 1 × Slave
transmission/
receptionNote 3
SI10 SO10
SCK10
(input)Note 3
1 0 1 × ×Note 1 ×Note 1 0 1 Master reception SI10 P12 SCK10
(output)
1 1 ×Note 1 ×Note 1 0 0 0 1 Master
transmission
RXD0/P11 SO10 SCK10
(output)
1 1 1 × 0 0 0 1 Master
transmission/
reception
SI10 SO10
SCK10
(output)
Notes 1. Can be set as port function.
2. To use P10/SCK10/TXD0 as port pins, clear CKP10 to 0.
3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1.
Remark ×: don’t care
CSIE10: Bit 7 of serial operation mode register 10 (CSIM10)
TRMD10: Bit 6 of CSIM10
CKP10: Bit 4 of serial clock selection register 10 (CSIC10)
CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10
PM1×: Port mode register
P1×: Port output latch
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
384
Table 16-2. Relationship Between Register Settings and Pins (2/2)
(b) Serial interface CSI11 (Available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D)
Pin Function CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 CSI11
Operation SI11/
P03
SO11/
P02
SCK11/
P04
SSI11/
TI001/P05
0 × × ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 ×Note 1 Stop P03 P02 P04Note 2 TI001/
P05
0 ×Note 1 ×Note 1 TI001/
P05
1 0
1
1 × ×Note 1 ×Note 1 1 ×
1 ×
Slave
receptionNote 3
SI11 P02
SCK11
(input)
Note 3 SSI11
0 ×Note 1 ×Note 1 TI001/
P05
1 1
1
×Note 1 ×Note 1 0 0 1 ×
1 ×
Slave
transmissionNote 3
P03 SO11
SCK11
(input)
Note 3 SSI11
0 ×Note 1 ×Note 1 TI001/
P05
1 1
1
1 × 0 0 1 ×
1 ×
Slave
transmission/
receptionNote 3
SI11 SO11
SCK11
(input)
Note 3 SSI11
1 0 0 1
× ×Note 1 ×Note 1 0 1 ×Note 1 ×Note 1 Master
reception
SI11 P02
SCK11
(output)
TI001/
P05
1 1 0 ×Note 1 ×Note 1 0 0 0 1 ×Note 1 ×Note 1 Master
transmission
P03 SO11
SCK11
(output)
TI001/
P05
1 1 0 1
× 0 0 0 1 ×Note 1 ×Note 1 Master
transmission/
reception
SI11 SO11
SCK11
(output)
TI001/
P05
Notes 1. Can be set as port function.
2. To use P04/SCK11 as port pins, clear CKP11 to 0.
3. To use the slave mode, set CKS112, CKS111, and CKS110 to 1, 1, 1.
Remark ×: don’t care
CSIE11: Bit 7 of serial operation mode register 11 (CSIM11)
TRMD11: Bit 6 of CSIM11
CKP11: Bit 4 of serial clock selection register 11 (CSIC11)
CKS112, CKS111, CKS110: Bits 2 to 0 of CSIC11
PM0×: Port mode register
P0×: Port output latch
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 385
(2) Communication operation
In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or
received in synchronization with the serial clock.
Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1.
Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n). In addition,
data can be received when bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0.
Reception is started when data is read from serial I/O shift register 1n (SIO1n).
However, communication is performed as follows if bit 5 (SSE11) of CSIM11 is 1 when serial interface CSI11 is in
the slave mode.
<1> Low level input to the SSI11 pin
→ Transmission/reception is started when SOTB11 is written, or reception is started when SIO11 is read.
<2> High level input to the SSI11 pin
→ Transmission/reception or reception is held, therefore, even if SOTB11 is written or SIO11 is read,
transmission/reception or reception will not be started.
<3> Data is written to SOTB11 or data is read from SIO11 while a high level is input to the SSI11 pin, then a low
level is input to the SSI11 pin
→ Transmission/reception or reception is started.
<4> A high level is input to the SSI11 pin during transmission/reception or reception
→ Transmission/reception or reception is suspended.
After communication has been started, bit 0 (CSOT1n) of CSIM1n is set to 1. When communication of 8-bit data
has been completed, a communication completion interrupt request flag (CSIIF1n) is set, and CSOT1n is cleared
to 0. Then the next communication is enabled.
Cautions 1. Do not access the control register and data register when CSOT1n = 1 (during serial
communication).
2. When using serial interface CSI11, wait for the duration of at least one clock before the
clock operation is started to change the level of the SSI11 pin in the slave mode; otherwise,
malfunctioning may occur.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
386
Figure 16-9. Timing in 3-Wire Serial I/O Mode (1/2)
(a) Transmission/reception timing (Type 1: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1Note)
AAHABH 56H ADH 5AH B5H 6AH D5H
55H (communication data)
55H is written to SOTB1n.
SCK1n
SOTB1n
SIO1n
CSOT1n
CSIIF1n
SO1n
SI1n (receive AAH)
Read/write trigger
INTCSI1n
SSI11Note
Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave
mode.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 387
Figure 16-9. Timing in 3-Wire Serial I/O Mode (2/2)
(b) Transmission/reception timing (Type 2: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1Note)
ABH 56H ADH 5AH B5H 6AH D5H
SCK1n
SOTB1n
SIO1n
CSOT1n
CSIIF1n
SO1n
SI1n (input AAH)
AAH
55H (communication data)
55H is written to SOTB1n.
Read/write trigger
INTCSI1n
SSI11
Note
Note The SSE11 flag and SSI11 pin are available only for serial interface CSI11, and are used in the slave
mode.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
388
Figure 16-10. Timing of Clock/Data Phase
(a) Type 1: CKP1n = 0, DAP1n = 0, DIR1n = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK1n
SO1n
Writing to SOTB1n or
reading from SIO1n
SI1n capture
CSIIF1n
CSOT1n
(b) Type 2: CKP1n = 0, DAP1n = 1, DIR1n = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK1n
SO1n
Writing to SOTB1n or
reading from SIO1n
SI1n capture
CSIIF1n
CSOT1n
(c) Type 3: CKP1n = 1, DAP1n = 0, DIR1n = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK1n
SO1n
Writing to SOTB1n or
reading from SIO1n
SI1n capture
CSIIF1n
CSOT1n
(d) Type 4: CKP1n = 1, DAP1n = 1, DIR1n = 0
D7 D6 D5 D4 D3 D2 D1 D0
SCK1n
SO1n
Writing to SOTB1n or
reading from SIO1n
SI1n capture
CSIIF1n
CSOT1n
Remarks 1. n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
2. The above figure illustrates a communication operation where data is transmitted with the MSB first.
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 389
(3) Timing of output to SO1n pin (first bit)
When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin.
The output operation of the first bit at this time is described below.
Figure 16-11. Output Operation of First Bit (1/2)
(a) Type 1: CKP1n = 0, DAP1n = 0
SCK1n
SOTB1n
SIO1n
SO1n
Writing to SOTB1n or
reading from SIO1n
First bit 2nd bit
Output latch
(b) Type 3: CKP1n = 1, DAP1n = 0
SCK1n
SOTB1n
SIO1n
Output latch
SO1n
Writing to SOTB1n or
reading from SIO1n
First bit 2nd bit
The first bit is directly latched by the SOTB1n register to the output latch at the falling (or rising) edge of SCK1n,
and output from the SO1n pin via an output selector. Then, the value of the SOTB1n register is transferred to the
SIO1n register at the next rising (or falling) edge of SCK1n, and shifted one bit. At the same time, the first bit of
the receive data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next falling (or rising)
edge of SCK1n, and the data is output from the SO1n pin.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
390
Figure 16-11. Output Operation of First Bit (2/2)
(c) Type 2: CKP1n = 0, DAP1n = 1
SCK1n
SOTB1n
SIO1n
SO1n
Writing to SOTB1n or
reading from SIO1n
First bit 2nd bit 3rd bit
Output latch
(d) Type 4: CKP1n = 1, DAP1n = 1
First bit 2nd bit 3rd bit
SCK1n
SOTB1n
SIO1n
Output latch
SO1n
Writing to SOTB1n or
reading from SIO1n
The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n
register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the
value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and
shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling)
edge of SCK1n, and the data is output from the SO1n pin.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 391
(4) Output value of SO1n pin (last bit)
After communication has been completed, the SO1n pin holds the output value of the last bit.
Figure 16-12. Output Value of SO1n Pin (Last Bit) (1/2)
(a) Type 1: CKP1n = 0, DAP1n = 0
SCK1n
SOTB1n
SIO1n
SO1n
Writing to SOTB1n or
reading from SIO1n
( ← Next request is issued.)
Last bit
Output latch
(b) Type 3: CKP1n = 1, DAP1n = 0
Last bit
( ← Next request is issued.)
SCK1n
SOTB1n
SIO1n
Output latch
SO1n
Writing to SOTB1n or
reading from SIO1n
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD
392
Figure 16-12. Output Value of SO1n Pin (Last Bit) (2/2)
(c) Type 2: CKP1n = 0, DAP1n = 1
SCK1n
SOTB1n
SIO1n
SO1n Last bit
Writing to SOTB1n or
reading from SIO1n ( ← Next request is issued.)
Output latch
(d) Type 4: CKP1n = 1, DAP1n = 1
Last bit
( ← Next request is issued.)
SCK1n
SOTB1n
SIO1n
Output latch
SO1n
Writing to SOTB1n or
reading from SIO1n
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17473EJ2V0UD 393
(5) SO1n output (see (a) in Figures 16-1 and 16-2)
The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is
cleared to 0.
Table 16-3. SO1n Output Status
TRMD1n DAP1n DIR1n SO1n OutputNote 1
TRMD1n = 0Note 2 − − Outputs low levelNote 2
DAP1n = 0 − Value of SO1n latch
(low-level output)
DIR1n = 0 Value of bit 7 of SOTB1n
TRMD1n = 1
DAP1n = 1
DIR1n = 1 Value of bit 0 of SOTB1n
Notes 1. The actual output of the SO10/P12 or SO11/P02 pin is determined according to PM12 and P12
or PM02 and P02, as well as the SO1n output.
2. Status after reset
Caution If a value is written to TRMD1n, DAP1n, and DIR1n, the output value of SO1n changes.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
User’s Manual U17473EJ2V0UD
394
CHAPTER 17 SERIAL INTERFACE IIC0
17.1 Functions of Serial Interface IIC0
Serial interface IIC0 has the following two modes.
(1) Operation stop mode
This mode is used when serial transfers are not performed. It can therefore be used to reduce power
consumption.
(2) I2C bus mode (multimaster supported)
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCL0) line and a
serial data bus (SDA0) line.
This mode complies with the I2C bus format and the master device can generated “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus.
The slave device automatically detects these received status and data by hardware. This function can simplify
the part of application program that controls the I2C bus.
Since the SCL0 and SDA0 pins are used for open drain outputs, IIC0 requires pull-up resistors for the serial
clock line and the serial data bus line.
Figure 17-1 shows a block diagram of serial interface IIC0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 395
Figure 17-1. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0 (IICS0)
IIC control register 0 (IICC0)
Slave address
register 0 (SVA0)
Noise
eliminator
Noise
eliminator
Bus status
detector
Match
signal
IIC shift
register 0 (IIC0)
SO latch
IICE0
DQ
Set
Clear
CL01,
CL00
TRC0
DFC0
DFC0
SDA0/
P61
SCL0/
P60
Data hold
time correction
circuit
Start
condition
generator
Stop
condition
generator
ACK
generator Wake-up
controller
ACK detector
Output control
Stop condition
detector
Serial clock
counter
Interrupt request
signal generator
Serial clock
controller
Serial clock
wait controller
Prescaler
INTIIC0
IIC shift register 0 (IIC0)
IICC0.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
IICS0.MSTS0,
EXC0, COI0
fPRS
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0 SPT0
MSTS0
ALD0 EXC0 COI0 TRC0
ACKD0
STD0 SPD0
Start condition
detector
Internal bus
CLD0 DAD0 SMC0 DFC0 CL01 CL00 CLX0
IIC clock selection
register 0 (IICCL0)
STCF
IICBSY STCEN IICRSV
IIC flag register 0
(IICF0)
IIC function expansion
register 0 (IICX0)
N-ch open-
drain output
PM61
Output latch
(P61)
N-ch open-
drain output
PM60
Output latch
(P60)
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
396
Figure 17-2 shows a serial bus configuration example.
Figure 17-2. Serial Bus Configuration Example Using I2C Bus
Master CPU1
Slave CPU1
Address 0
SDA0
SCL0
Serial data bus
Serial clock
+ V
DD
+ V
DD
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
Master CPU2
Slave CPU2
Address 1
Slave CPU3
Address 2
Slave IC
Address 3
Slave IC
Address N
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 397
17.2 Configuration of Serial Interface IIC0
Serial interface IIC0 includes the following hardware.
Table 17-1. Configuration of Serial Interface IIC0
Item Configuration
Registers IIC shift register 0 (IIC0)
Slave address register 0 (SVA0)
Control registers IIC control register 0 (IICC0)
IIC status register 0 (IICS0)
IIC flag register 0 (IICF0)
IIC clock selection register 0 (IICCL0)
IIC function expansion register 0 (IICX0)
Port mode register 6 (PM6)
Port register 6 (P6)
(1) IIC shift register 0 (IIC0)
IIC0 is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial
clock. IIC0 can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to IIC0.
Cancel the wait state and start data transfer by writing data to IIC0 during the wait period.
IIC0 is set by an 8-bit memory manipulation instruction.
Reset signal generation sets IIC0 to 00H.
Figure 17-3. Format of IIC Shift Register 0 (IIC0)
Symbol
IIC0
Address: FFA5H After reset: 00H R/W
76543210
Cautions 1. Do not write data to IIC0 during data transfer.
2. Write or read IIC0 only during the wait period. Accessing IIC0 in a communication state
other than during the wait period is prohibited. When the device serves as the master,
however, IIC0 can be written only once after the communication trigger bit (STT0) is set to
1.
(2) Slave address register 0 (SVA0)
This register stores local addresses when in slave mode.
SVA0 is set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected).
Reset signal generation sets SVA0 to 00H.
Figure 17-4. Format of Slave Address Register 0 (SVA0)
Symbol
SVA0
Address: FFA7H After reset: 00H R/W
76543210
0
Note
Note Bit 0 is fixed to 0.
<R>
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
398
(3) SO latch
The SO latch is used to retain the SDA0 pin’s output level.
(4) Wake-up controller
This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the
address value set to slave address register 0 (SVA0) or when an extension code is received.
(5) Prescaler
This selects the sampling clock to be used.
(6) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
(7) Interrupt request signal generator
This circuit controls the generation of interrupt request signals (INTIIC0).
An I2C interrupt request is generated by the following two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Remark WTIM0 bit: Bit 3 of IIC control register 0 (IICC0)
SPIE0 bit: Bit 4 of IIC control register 0 (IICC0)
(8) Serial clock controller
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(11) Data hold time correction circuit
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
(12) Start condition generator
This circuit generates a start condition when the STT0 bit is set to 1.
However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released
(IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1.
(13) Stop condition generator
This circuit generates a stop condition when the SPT0 bit is set to 1.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 399
(14) Bus status detector
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCEN bit.
Remark STT0 bit: Bit 1 of IIC control register 0 (IICC0)
SPT0 bit: Bit 0 of IIC control register 0 (IICC0)
IICRSV bit: Bit 0 of IIC flag register 0
IICBSY bit: Bit 6 of IIC flag register 0
STCF bit: Bit 7 of IIC flag register 0
STCEN bit: Bit 1 of IIC flag register 0
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
400
17.3 Registers to Control Serial Interface IIC0
Serial interface IIC0 is controlled by the following six registers.
• IIC control register 0 (IICC0)
• IIC flag register 0 (IICF0)
• IIC status register 0 (IICS0)
• IIC clock selection register 0 (IICCL0)
• IIC function expansion register 0 (IICX0)
• Port mode register 6 (PM6)
• Port register 6 (P6)
(1) IIC control register 0 (IICC0)
This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations.
IICC0 is set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0
bits while IICE0 bit = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is
set from “0” to “1”.
Reset signal generation sets IICC0 to 00H.
<R>
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 401
Figure 17-5. Format of IIC Control Register 0 (IICC0) (1/4)
Address: FFA6H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
IICE0 I2C operation enable
0 Stop operation. Reset IIC status register 0 (IICS0)Note 1. Stop internal operation.
1 Enable operation.
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE0 = 0) Condition for setting (IICE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
LREL0Note 2 Exit from communications
0 Normal operation
1 This exits from the current communications and sets standby mode. This setting is automatically cleared to 0
after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
The standby mode following exit from communications remains in effect until the following communications entry conditions
are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0) Condition for setting (LREL0 = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
WREL0Note 2 Wait cancellation
0 Do not cancel wait
1 Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the
SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0) Condition for setting (WREL0 = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the
IICCL0 register are reset.
2. This flag’s signal is invalid when IICE0 = 0.
Caution The start condition is detected immediately after I2C is enabled to operate (IICE0 = 1) while the
SCL0 line is at high level and the SDA0 line is at low level. Immediately after enabling I2C to
operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory manipulation instruction.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
402
Figure 17-5. Format of IIC Control Register 0 (IICC0) (2/4)
SPIE0Note 1 Enable/disable generation of interrupt request when stop condition is detected
0 Disable
1 Enable
Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
WTIM0Note 1 Control of wait and interrupt request generation
0 Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1 Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit.
The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling
edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the
falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device has received an
extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0) Condition for setting (WTIM0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
ACKE0Notes 1, 2 Acknowledgment control
0 Disable acknowledgment.
1 Enable acknowledgment. During the ninth clock period, the SDA0 line is set to low level. However, ACK is
invalid during address transfers and other than in expansion mode.
Condition for clearing (ACKE0 = 0) Condition for setting (ACKE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
Notes 1. This flag’s signal is invalid when IICE0 = 0.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledge is generated regardless
of the set value.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 403
Figure 17-5. Format of IIC Control Register 0 (IICC0) (3/4)
STT0Note Start condition trigger
0 Do not generate a start condition.
1 When bus is released (in STOP mode):
Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is changed
from high level to low level and then the start condition is generated. Next, after the rated amount of time has
elapsed, SCL0 is changed to low level.
When a third party is communicating:
• When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start condition
after the bus is released.
• When communication reservation function is disabled (IICRSV = 1)
STCF is set to 1 and information that is set (1) to STT0 is cleared. No start condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has
been cleared to 0 and slave has been notified of final reception.
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during
the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as SPT0.
• Setting STT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1)
• Cleared by setting SST0 to 1 while communication
reservation is prohibited.
• Cleared by loss in arbitration
• Cleared after start condition is generated by master device
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Note This flag’s signal is invalid when IICE0 = 0.
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
2. IICRSV: Bit 0 of IIC flag register (IICF0)
STCF: Bit 7 of IIC flag register (IICF0)
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
404
Figure 17-5. Format of IIC Control Register 0 (IICC0) (4/4)
SPT0 Stop condition trigger
0 Stop condition is not generated.
1 Stop condition is generated (termination of master device’s transfer).
After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level. Next,
after the rated amount of time has elapsed, the SDA0 line changes from low level to high level and a stop
condition is generated.
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been
notified of final reception.
• For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it
during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as STT0.
• SPT0 can be set to 1 only when in master modeNote.
• When WTIM0 has been cleared to 0, if SPT0 is set to 1 during the wait period that follows output of eight clocks, note that a
stop condition will be generated during the high-level period of the ninth clock. WTIM0 should be changed from 0 to 1 during
the wait period following the output of eight clocks, and SPT0 should be set to 1 during the wait period that follows the output
of the ninth clock.
• Setting SPT0 to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0) Condition for setting (SPT0 = 1)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Note Set SPT0 to 1 only in master mode. However, SPT0 must be set to 1 and a stop condition generated before
the first stop condition is detected following the switch to the operation enabled status. For details, see
17.5.15 Other cautions.
Caution When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1 during the ninth
clock and wait is canceled, after which TRC0 is cleared and the SDA0 line is set to high
impedance.
Remark Bit 0 (SPT0) becomes 0 when it is read after data setting.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 405
(2) IIC status register 0 (IICS0)
This register indicates the status of I2C.
IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation sets IICS0 to 00H.
Caution If data is read from IICS0, a wait cycle is generated. Do not read data from IICS0 when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 33 CAUTIONS FOR WAIT.
Figure 17-6. Format of IIC Status Register 0 (IICS0) (1/3)
Address: FFAAH After reset: 00H R
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
MSTS0 Master device status
0 Slave device status or communication standby status
1 Master device communication status
Condition for clearing (MSTS0 = 0) Condition for setting (MSTS0 = 1)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When a start condition is generated
ALD0 Detection of arbitration loss
0 This status means either that there was no arbitration or that the arbitration result was a “win”.
1 This status indicates the arbitration result was a “loss”. MSTS0 is cleared.
Condition for clearing (ALD0 = 0) Condition for setting (ALD0 = 1)
• Automatically cleared after IICS0 is readNote
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When the arbitration result is a “loss”.
EXC0 Detection of extension code reception
0 Extension code was not received.
1 Extension code was received.
Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When the higher four bits of the received address data is
either “0000” or “1111” (set at the rising edge of the
eighth clock).
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
than IICS0. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other
bits.
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
406
Figure 17-6. Format of IIC Status Register 0 (IICS0) (2/3)
COI0 Detection of matching addresses
0 Addresses do not match.
1 Addresses match.
Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When the received address matches the local address
(slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
TRC0 Detection of transmit/receive status
0 Receive status (other than transmit status). The SDA0 line is set for high impedance.
1 Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the
falling edge of the first byte’s ninth clock).
Condition for clearing (TRC0 = 0) Condition for setting (TRC0 = 1)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Cleared by WREL0 = 1Note (wait cancel)
• When ALD0 changes from 0 to 1 (arbitration loss)
• Reset
<Master>
• When “1” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer direction
specification bit)
<When not used for communication>
<Master>
• When a start condition is generated
• When “0” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
• When “1” is input to the first byte’s LSB (transfer
direction specification bit)
Note If the wait status is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth
clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes
into a high-impedance state.
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 407
Figure 17-6. Format of IIC Status Register 0 (IICS0) (3/3)
ACKD0 Detection of acknowledge (ACK)
0 Acknowledge was not detected.
1 Acknowledge was detected.
Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• After the SDA0 line is set to low level at the rising edge of
SCL0’s ninth clock
STD0 Detection of start condition
0 Start condition was not detected.
1 Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STD0 = 0) Condition for setting (STD0 = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock following
address transfer
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When a start condition is detected
SPD0 Detection of stop condition
0 Stop condition was not detected.
1 Stop condition was detected. The master device’s communication is terminated and the bus is released.
Condition for clearing (SPD0 = 0) Condition for setting (SPD0 = 1)
• At the rising edge of the address transfer byte’s first
clock following setting of this bit and detection of a start
condition
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
• When a stop condition is detected
Remark LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
(3) IIC flag register 0 (IICF0)
This register sets the operation mode of I2C and indicates the status of the I2C bus.
IICF0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are read-
only.
The IICRSV bit can be used to enable/disable the communication reservation function (see 17.5.14
Communication reservation).
STCEN can be used to set the initial value of the IICBSY bit (see 17.5.15 Other cautions).
IICRSV and STCEN can be written only when the operation of I2C is disabled (bit 7 (IICE0) of IIC control
register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation sets IICF0 to 00H.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
408
Figure 17-7. Format of IIC Flag Register 0 (IICF0)
<7>
STCF
Condition for clearing (STCF = 0)
• Cleared by STT0 = 1
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (STCF = 1)
• Generating start condition unsuccessful and STT0
cleared to 0 when communication reservation is
disabled (IICRSV = 1).
STCF
0
1
Generate start condition
Start condition generation unsuccessful: clear STT0 flag
STT0 clear flag
IICF0
Symbol <6>
IICBSY
5
0
4
0
3
0
2
0
<1>
STCEN
<0>
IICRSV
Address: FFABH After reset: 00H R/W
Note
Condition for clearing (IICBSY = 0)
• Detection of stop condition
• When IICE0 = 0 (operation stop)
• Reset
Condition for setting (IICBSY = 1)
• Detection of start condition
• Setting of IICE0 when STCEN = 0
IICBSY
0
1
Bus release status (communication initial status when STCEN = 1)
Bus communication status (communication initial status when STCEN = 0)
I
2
C bus status flag
Condition for clearing (STCEN = 0)
• Detection of start condition
• Reset
Condition for setting (STCEN = 1)
• Set by instruction
STCEN
0
1
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
Initial start enable trigger
Condition for clearing (IICRSV = 0)
• Cleared by instruction
• Reset
Condition for setting (IICRSV = 1)
• Set by instruction
IICRSV
0
1
Enable communication reservation
Disable communication reservation
Communication reservation function disable bit
Note Bits 6 and 7 are read-only.
Cautions 1. Write to STCEN only when the operation is stopped (IICE0 = 0).
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
3. Write to IICRSV only when the operation is stopped (IICE0 = 0).
Remark STT0: Bit 1 of IIC control register 0 (IICC0)
IICE0: Bit 7 of IIC control register 0 (IICC0)
<R>
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 409
(4) IIC clock selection register 0 (IICCL0)
This register is used to set the transfer clock for the I2C bus.
IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-
only. The SMC0, CL01, and CL00 bits are set in combination with bit 0 (CLX0) of IIC function expansion
register 0 (IICX0) (see 17.3 (6) I2C transfer clock setting method).
Set IICCL0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation sets IICCL0 to 00H.
Figure 17-8. Format of IIC Clock Selection Register 0 (IICCL0)
Address: FFA8H After reset: 00H R/WNote
Symbol 7 6 <5> <4> <3> <2> 1 0
IICCL0 0 0 CLD0 DAD0 SMC0 DFC0 CL01 CL00
CLD0 Detection of SCL0 pin level (valid only when IICE0 = 1)
0 The SCL0 pin was detected at low level.
1 The SCL0 pin was detected at high level.
Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1)
• When the SCL0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SCL0 pin is at high level
DAD0 Detection of SDA0 pin level (valid only when IICE0 = 1)
0 The SDA0 pin was detected at low level.
1 The SDA0 pin was detected at high level.
Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1)
• When the SDA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SDA0 pin is at high level
SMC0 Operation mode switching
0 Operates in standard mode.
1 Operates in high-speed mode.
DFC0 Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set (1)/clear (0).
The digital filter is used for noise elimination in high-speed mode.
Note Bits 4 and 5 are read-only.
Remark IICE0: Bit 7 of IIC control register 0 (IICC0)
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
410
(5) IIC function expansion register 0 (IICX0)
This register sets the function expansion of I2C.
IICX0 is set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3,
1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) (see 17.3 (6) I2C transfer clock
setting method).
Set IICX0 while bit 7 (IICE0) of IIC control register 0 (IICC0) is 0.
Reset signal generation sets IICX0 to 00H.
Figure 17-9. Format of IIC Function Expansion Register 0 (IICX0)
Address: FFA9H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
IICX0 0 0 0 0 0 0 0 CLX0
(6) I2C transfer clock setting method
The I2C transfer clock frequency (fSCL) is calculated using the following expression.
fSCL = 1/(m × T + tR + tF)
m = 12, 18, 24, 44, 66, 86 (see Table 17-2 Selection Clock Setting)
T: 1/fW
tR: SCL0 rise time
tF: SCL0 fall time
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 411
For example, the I2C transfer clock frequency (fSCL) when fW = fPRS/2 = 4.19 MHz, m = 86, tR = 200 ns, and tF =
50 ns is calculated using following expression.
fSCL = 1/(88 × 238.7 ns + 200 ns + 50 ns) ≅ 48.1 kHz
m × T + t
R
+ t
F
m/2 × Tm/2 × T t
F
t
R
SCL0
SCL0 inversion SCL0 inversion SCL0 inversion
The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection
register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
Table 17-2. Selection Clock Setting
IICX0 IICCL0
Bit 0 Bit 3 Bit 1 Bit 0
CLX0 SMC0 CL01 CL00
Selection Clock
(fW)
Transfer Clock
(fW/m)
Settable Selection Clock
(fW) Range
Operation Mode
0 0 0 0 fPRS/2 fW/44 2.00 to 4.19 MHz
0 0 0 1 fPRS/2 fW/86
0 0 1 0 fPRS/4 fW/86
4.19 to 8.38 MHz
Normal mode
(SMC0 bit = 0)
0 0 1 1 Setting prohibited
0 1 0 × fPRS/2 fW/24
0 1 1 0 fPRS/4 fW/24
4.00 to 8.38 MHz High-speed mode
(SMC0 bit = 1)
0 1 1 1
1 0 × ×
Setting prohibited
1 1 0 × fPRS/2 fW/12
1 1 1 0 fPRS/4 fW/12
4.00 to 4.19 MHz High-speed mode
(SMC0 bit = 1)
1 1 1 1 Setting prohibited
Caution Determine the transfer clock frequency of I2C by using CLX0, SMC0, CL01, and CL00 before
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
Remarks 1. ×: don’t care
2. fPRS: Peripheral hardware clock frequency
3. fEXSCL0: External clock frequency from EXSCL0 pin
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
412
(7) Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61,
and the output latches of P60 and P61 to 0.
Set IICE0 (bit 7 of IIC control register 0 (IICC0)) to 1 before setting the output mode because the P60/SCL0
and P61/SDA0 pins output a low level (fixed) when IICE0 is 0.
PM6 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM6 to FFH.
Figure 17-10. Format of Port Mode Register 6 (PM6)
PM60PM61PM6211111
SDA0 pin I/O mode selection
Output mode (output buffer on)
Input mode (output buffer off)
PM61
0
1
01234567
PM6
Address: FF26H After reset: FFH R/W
Symbol
SCL0 pin I/O mode selection
Output mode (output buffer on)
Input mode (output buffer off)
PM60
0
1
Caution After a reset release, be sure to set PM62 to 0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 413
(8) Port register 6 (P6)
This register writes the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the
output latch is read.
When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, set the output latches of
P60 and P61 to 0.
If EEPROM is outputting a low level to the P61/SDA0 pin, output a clock pulse from the output port by using
this register.
P6 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets P6 to 00H.
Figure 17-11. Format of Port Register 6 (P6)
P60P61000000
SDA0 pin output data control
Output o or serial data
Output 1
P61
0
1
01234567
P6
Address: FF06H After reset: 00H (output latch) R/W
Symbol
Output o or serial clock
Output 1
P60
0
1
(in output mode)
SDA0 pin input data read
(in input mode)
Input low level
Input high level
Input low level
Input high level
SCL0 pin output data control
(in output mode)
SCL0 pin input data read
(in input mode)
<R>
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
414
17.4 I2C Bus Mode Functions
17.4.1 Pin configuration
The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows.
(1) SCL0....... This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
(2) SDA0 ...... This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
resistor is required.
Figure 17-12. Pin Configuration Diagram
Master device
Clock output
(Clock input)
Data output
Data input
V
SS
V
SS
SCL0
SDA0
V
DD
V
DD
(Clock output)
Clock input
Data output
Data input
V
SS
V
SS
Slave device
SCL0
SDA0
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 415
17.5 I2C Bus Definitions and Control Methods
The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus.
Figure 17-13 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the
I2C bus’s serial data bus.
Figure 17-13. I2C Bus Serial Data Transfer Timing
SCL0
SDA0
Start
condition
Address R/W ACK Data
1-7 8 9 1-8
ACK Data ACK Stop
condition
9 1-8 9
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device
that receives 8-bit data).
The serial clock (SCL0) is continuously output by the master device. However, in the slave device, the SCL0’s low
level period can be extended and a wait can be inserted.
17.5.1 Start conditions
A start condition is met when the SCL0 pin is at high level and the SDA0 pin changes from high level to low level.
The start conditions for the SCL0 pin and SDA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 17-14. Start Conditions
SCL0
SDA0
H
A start condition is output when bit 1 (STT0) of IIC control register 0 (IICC0) is set (to 1) after a stop condition has
been detected (SPD0: Bit 0 = 1 in IIC status register 0 (IICS0)). When a start condition is detected, bit 1 (STD0) of
IICS0 is set (to 1).
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
416
17.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to
the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique
address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address
data matches the data values stored in slave address register 0 (SVA0). If the address data matches the SVA0
values, the slave device is selected and communicates with the master device until the master device generates a
start condition or stop condition.
Figure 17-15. Address
SCL0
SDA0
INTIIC0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W
Address
Note
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
The slave address and the eighth bit, which specifies the transfer direction as described in 17.5.3 Transfer
direction specification below, are together written to IIC shift register 0 (IIC0) and are then output. Received
addresses are written to IIC0.
The slave address is assigned to the higher 7 bits of IIC0.
17.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of “0”, it indicates that the master device is transmitting
data to a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master
device is receiving data from a slave device.
Figure 17-16. Transfer Direction Specification
SCL0
SDA0
INTIIC0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W
Transfer direction specification
Note
Note INTIIC0 is not issued if data other than a local address or extension code is received during slave device
operation.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 417
17.5.4 Acknowledge (ACK)
ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception
side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been
detected can be checked by using bit 2 (ACKD0) of IIC status register 0 (IICS0).
When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a
slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops
transmission. If ACK is not returned, the possible causes are as follows.
<1> Reception was not performed normally.
<2> The final data item was received.
<3> The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDA0 line low at the ninth clock (indicating normal reception).
Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IIC control register 0 (IICC0) to 1. Bit 3 (TRC0)
of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set ACKE0 to 1
for reception (TRC0 = 0).
If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the
slave must inform the master, by clearing ACKE0 to 0, that it will not receive any more data.
When the master does not require the next data item during reception (TRC0 = 0), it must clear ACKE0 to 0 so that
ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any
more data (transmission will be stopped).
Figure 17-17. ACK
SCL0
SDA0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W ACK
When the local address is received, ACK is automatically generated, regardless of the value of ACKE0. When an
address other than that of the local address is received, ACK is not generated (NACK).
When an extension code is received, ACK is generated if ACKE0 is set to 1 in advance.
How ACK is generated when data is received differs as follows depending on the setting of the wait timing.
• When 8-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 0):
By setting ACKE0 to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of
the SCL0 pin.
• When 9-clock wait state is selected (bit 3 (WTIM0) of IICC0 register = 1):
ACK is generated by setting ACKE0 to 1 in advance.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
418
17.5.5 Stop condition
When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device generates to the slave device when serial transfer has been
completed. When the device is used as a slave, stop conditions can be detected.
Figure 17-18. Stop Condition
SCL0
SDA0
H
A stop condition is generated when bit 0 (SPT0) of IIC control register 0 (IICC0) is set to 1. When the stop
condition is detected, bit 0 (SPD0) of IIC status register 0 (IICS0) is set to 1 and INTIIC0 is generated when bit 4
(SPIE0) of IICC0 is set to 1.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 419
17.5.6 Wait
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or
receive data (i.e., is in a wait state).
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
canceled for both the master and slave devices, the next data transfer can begin.
Figure 17-19. Wait (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
IIC0
SCL0
Slave
IIC0
SCL0
ACKE0
Transfer lines
SCL0
SDA0
6789 123
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of ninth clock
IIC0 data write (cancel wait)
Wait after output
of eighth clock
Wait from slave Wait from master
FFH is written to IIC0 or WREL0 is set to 1
678 9 123
D2 D1 D0 D7 D6 D5ACK
H
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
420
Figure 17-19. Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
IIC0
SCL0
Slave
IIC0
SCL0
ACKE0
Transfer lines
SCL0
SDA0
H
6789 1 23
Master and slave both wait
after output of ninth clock
Wait from
master and
slave Wait from slave
IIC0 data write (cancel wait)
FFH is written to IIC0 or WREL0 is set to 1
6789 123
D2 D1 D0 ACK D7 D6 D5
Generate according to previously set ACKE0 value
Remark ACKE0: Bit 2 of IIC control register 0 (IICC0)
WREL0: Bit 5 of IIC control register 0 (IICC0)
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IIC control register 0 (IICC0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of IICC0 is set to 1 or when FFH is written
to IIC shift register 0 (IIC0), and the transmitting side cancels the wait state when data is written to IIC0.
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICC0 to 1
• By setting bit 0 (SPT0) of IICC0 to 1
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 421
17.5.7 Canceling wait
The I2C usually cancels a wait state by the following processing.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)Note
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note
Note Master only
When the above wait canceling processing is executed, the I2C cancels the wait state and communication is
resumed.
To cancel a wait state and transmit data (including addresses), write the data to IIC0.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control
register 0 (IICC0) to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IIC0 after canceling a wait state by setting WREL0 to 1, an incorrect value may be
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IIC0.
In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted,
so that the wait state can be canceled.
If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of
IICC0, so that the wait state can be canceled.
17.5.8 Interrupt request (INTIIC0) generation timing and wait control
The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
and the corresponding wait control, as shown in Table 17-3.
Table 17-3. INTIIC0 Generation Timing and Wait Control
During Slave Device Operation During Master Device Operation WTIM0
Address Data Reception Data Transmission Address Data Reception Data Transmission
0 9Notes 1, 2 8
Note 2 8
Note 2 9 8 8
1 9Notes 1, 2 9
Note 2 9
Note 2 9 9 9
Notes 1. The slave device’s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to IICC0’s bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of slave address register 0 (SVA0) and extension
code is not received, neither INTIIC0 nor a wait occurs.
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
422
(1) During address transmission/reception
• Slave device operation: Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM0 bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
the WTIM0 bit.
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)Note
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)Note
Note Master only.
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
(5) Stop condition detection
INTIIC0 is generated when a stop condition is detected (only when SPIE0 = 1).
17.5.9 Address match detection method
In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
address.
Address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local
address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave
address sent by the master device, or when an extension code has been received.
17.5.10 Error detection
In I2C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0
(IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data
to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 423
17.5.11 Extension code
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag
(EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge
of the eighth clock. The local address stored in slave address register 0 (SVA0) is not affected.
(2) If “11110××0” is set to SVA0 by a 10-bit address transfer and “11110××0” is transferred from the master device,
the results are as follows. Note that INTIIC0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match: COI0 = 1
Remark EXC0: Bit 5 of IIC status register 0 (IICS0)
COI0: Bit 4 of IIC status register 0 (IICS0)
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension
code, such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave
device, set bit 6 (LREL0) of the IIC control register 0 (IICC0) to 1 to set the standby mode for the next
communication operation.
Table 17-4. Extension Code Bit Definitions
Slave Address R/W Bit Description
0 0 0 0 0 0 0 0 General call address
0 0 0 0 0 0 0 1 Start byte
0 0 0 0 0 0 1 × C-BUS address
0 0 0 0 0 1 0 × Address that is reserved for different bus format
1 1 1 1 0 X X × 10-bit slave address specification
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
424
17.5.12 Arbitration
When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set
to 1), communication among the master devices is performed as the number of clocks are adjusted until the data
differs. This kind of operation is called arbitration.
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0)
is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high
impedance, which releases the bus.
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a
stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
For details of interrupt request timing, see 17.5.17 Timing of I2C interrupt request (INTIIC0) occurrence.
Remark STD0: Bit 1 of IIC status register 0 (IICS0)
STT0: Bit 1 of IIC control register 0 (IICC0)
Figure 17-20. Arbitration Timing Example
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
Hi-Z
Hi-Z
Master 1 loses arbitration
Master 1
Master 2
Transfer lines
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 425
Table 17-5. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration Interrupt Request Generation Timing
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK transfer period after data transmission
When restart condition is detected during data transfer
At falling edge of eighth or ninth clock following byte transferNote 1
When stop condition is detected during data transfer When stop condition is generated (when SPIE0 = 1)Note 2
When data is at low level while attempting to generate a restart
condition
At falling edge of eighth or ninth clock following byte transferNote 1
When stop condition is detected while attempting to generate a
restart condition
When stop condition is generated (when SPIE0 = 1)Note 2
When data is at low level while attempting to generate a stop
condition
When SCL0 is at low level while attempting to generate a
restart condition
At falling edge of eighth or ninth clock following byte transferNote 1
Notes 1. When WTIM0 (bit 3 of IIC control register 0 (IICC0)) = 1, an interrupt request occurs at the falling edge
of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an interrupt
request occurs at the falling edge of the eighth clock.
2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
Remark SPIE0: Bit 4 of IIC control register 0 (IICC0)
17.5.13 Wakeup function
The I2C bus slave function is a function that generates an interrupt request signal (INTIIC0) when a local address
and extension code have been received.
This function makes processing more efficient by preventing unnecessary INTIIC0 signal from occurring when
addresses do not match.
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
However, when a stop condition is detected, bit 4 (SPIE0) of IIC control register 0 (IICC0) is set regardless of the
wakeup function, and this determines whether interrupt requests are enabled or disabled.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
426
17.5.14 Communication reservation
(1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0)
To start master device communications when not currently using a bus, a communication reservation can be
made to enable transmission of a start condition when the bus is released. There are two modes under which
the bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released when bit 6 (LREL0) of IIC control register 0 (IICC0) was set to 1).
If bit 1 (STT0) of IICC0 is set to 1 while the bus is not used (after a stop condition is detected), a start condition
is automatically generated and wait state is set.
If an address is written to IIC shift register 0 (IIC0) after bit 4 (SPIE0) of IICC0 was set to 1, and it was detected
by generation of an interrupt request signal (INTIIC0) that the bus was released (detection of the stop
condition), then the device automatically starts communication as the master. Data written to IIC0 before the
stop condition is detected is invalid.
When STT0 has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................ a start condition is generated
• If the bus has not been released (standby mode)......... communication reservation
Check whether the communication reservation operates or not by using MSTS0 (bit 7 of IIC status register 0
(IICS0)) after STT0 is set to 1 and the wait time elapses.
The wait periods, which should be set via software, are listed in Table 17-6.
Table 17-6. Wait Periods
CLX0 SMC0 CL01 CL00 Wait Period
0 0 0 0 46 clocks
0 0 0 1 86 clocks
0 0 1 0 172 clocks
0 0 1 1 34 clocks
0 1 0 0
0 1 0 1
30 clocks
0 1 1 0 60 clocks
0 1 1 1 12 clocks
1 1 0 0
1 1 0 1
18 clocks
1 1 1 0 36 clocks
Figure 17-21 shows the communication reservation timing.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 427
Figure 17-21. Communication Reservation Timing
213456 21 3456789
SCL0
SDA0
Program processing
Hardware processing
Write to
IIC0
Set SPD0
and
INTIIC0
STT0 = 1
Communi-
cation
reservation
Set
STD0
Generate by master device with bus mastership
Remark IIC0: IIC shift register 0
STT0: Bit 1 of IIC control register 0 (IICC0)
STD0: Bit 1 of IIC status register 0 (IICS0)
SPD0: Bit 0 of IIC status register 0 (IICS0)
Communication reservations are accepted via the following timing. After bit 1 (STD0) of IIC status register 0
(IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IIC control register 0
(IICC0) to 1 before a stop condition is detected.
Figure 17-22. Timing for Accepting Communication Reservations
SCL0
SDA0
STD0
SPD0
Standby mode
Figure 17-23 shows the communication reservation protocol.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
428
Figure 17-23. Communication Reservation Protocol
DI
SET1 STT0
Define communication
reservation
Wait
MSTS0 = 0?
(Communication reservation)
Note
Yes
No
(Generate start condition)
Cancel communication
reservation
MOV IIC0, #××H
EI
Sets STT0 flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait period set by software (see Table 18-6).
Confirmation of communication reservation
Clear user flag
IIC0 write operation
Note The communication reservation operation executes a write to IIC shift register 0 (IIC0) when a stop
condition interrupt request occurs.
Remark STT0: Bit 1 of IIC control register 0 (IICC0)
MSTS0: Bit 7 of IIC status register 0 (IICS0)
IIC0: IIC shift register 0
(2) When communication reservation function is disabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 1)
When bit 1 (STT0) of IIC control register 0 (IICC0) is set to 1 when the bus is not used in a communication
during bus communication, this request is rejected and a start condition is not generated. The following two
statuses are included in the status where bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released when bit 6 (LREL0) of IICC0 was set to 1)
To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of IICF0).
The time shown in Table 17-7 is required until STCF is set to 1 after setting STT0 = 1. Therefore, secure the
time by software.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 429
Table 17-7. Wait Periods
CL01 CL00 Wait Period
0 0 6 clocks
0 1 6 clocks
1 0 12 clocks
1 1 3 clocks
17.5.15 Other cautions
(1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0
Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) =
1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition
has been detected to a master device communication mode, first generate a stop condition to release the bus,
then perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock selection register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
(2) When STCEN = 1
Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0
(IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other
communications.
(3) If other I2C communications are already in progress
If I2C operation is enabled and the device participates in communication already in progress when the SDA0
pin is low and the SCL0 pin is high, the macro of I2C recognizes that the SDA0 pin has gone low (detects a
start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned,
but this interferes with other I2C communications. To avoid this, start I2C in the following sequence.
<1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the
stop condition is detected.
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I2C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly
disable detection.
(4) Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 of IICL0), and CLX0 (bit 0
of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear IICE0 to 0
once.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
430
(5) Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before they are cleared to 0 is
prohibited.
(6) When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated when
the stop condition is detected. Transfer is started when communication data is written to IIC0 after the interrupt
request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops
in the wait state because the interrupt request is not generated when communication is started. However, it is
not necessary to set SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software.
17.5.16 Communication operations
The following shows three operation procedures with the flowchart.
(1) Master operation in single master system
The flowchart when using the 78K0/LG2 as the master in a single master system is shown below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial
settings at startup. If communication with the slave is required, prepare the communication and then execute
communication processing.
(2) Master operation in multimaster system
In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the 78K0/LG2 takes part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the 78K0/LG2 looses in arbitration and is specified as the slave is omitted here, and only
the processing as the master is shown. Execute the initial settings at startup to take part in a communication.
Then, wait for the communication request as the master or wait for the specification as the slave. The actual
communication is performed in the communication processing, and it supports the transmission/reception with
the slave and the arbitration with other masters.
(3) Slave operation
An example of when the 78K0/LG2 is used as the I2C bus slave is shown below.
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait
for the INTIIC0 interrupt occurrence (communication waiting). When an INTIIC0 interrupt occurs, the
communication status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
<R>
<R>
<R>
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 431
(1) Master operation in single-master system
Figure 17-24. Master Operation in Single-Master System
SPT0 = 1
SPT0 = 1
WREL0 = 1
START
END
ACKE0 = 0
WTIM0 = WREL0 = 1
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
STCEN = 1?
ACKE0 = 1
WTIM0 = 0
TRC0 = 1?
ACKD0 = 1?
ACKD0 = 1?
No
Yes
No
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
STT0 = 1
IICX0 ← 0XH
IICCL0 ← XXH
IICF0 ← 0XH
Setting STCEN, IICRSV = 0
IICC0 ← XXH
ACKE0 = WTIM0 = SPIE0 = 1
IICE0 = 1
Setting port
Initializing I
2
C bus
Note
SVA0 ← XXH
Writing IIC0
Writing IIC0
Reading IIC0
INTIIC0
interrupt occurs?
End of transfer?
End of transfer?
Restart?
Sets each pin in the I
2
C mode (see 17.3 (7) Port mode register 6 (PM6)).
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Prepares for starting communication
(generates a start condition).
Starts communication
(specifies an address and transfer
direction).
Waits for detection of acknowledge.
Waits for data transmission.
Starts transmission.
Communication processing Initial setting
Starts reception.
Waits for data
reception.
INTIIC0
interrupt occurs?
Waits for detection
of acknowledge.
Prepares for starting communication
(generates a stop condition).
Waits for detection of the stop condition.
INTIIC0
Interrupt occurs?
INTIIC0
interrupt occurs?
INTIIC0
interrupt occurs?
Note Release (SCL0 and SDA0 pins = high level) the I2C bus in conformance with the specifications of the
product that is communicating. If EEPROM is outputting a low level to the SDA0 pin, for example, set the
SCL0 pin in the output port mode, and output a clock pulse from the output port until the SDA0 pin is
constantly at high level.
Remark Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
<R>
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
432
(2) Master operation in multi-master system
Figure 17-25. Master Operation in Multi-Master System (1/3)
IICX0 ← 0XH
IICCL0 ← XXH
IICF0 ← 0XH
Setting STCEN and IICRSV
IICC0 ← XXH
ACKE0 = WTIM0 = SPIE0 = 1
IICE0 = 1
Setting port
SPT0 = 1
SVA0 ← XXH
SPIE0 = 1
START
Slave operation
Slave operation
Releases the bus for a specific period.
Bus status is
being checked.
Yes
Checking bus status
Note
Master operation
starts?
Enables reserving
communication.
Disables reserving
communication.
SPD0 = 1?
STCEN = 1?
IICRSV = 0?
A
Sets each pin in the I
2
C mode (see 17.3 (7) Port mode register 6 (PM6)).
Selects a transfer clock.
Sets a local address.
Sets a start condition.
(Communication start request)
(No communication start request)
• Waiting to be specified as a slave by other master
• Waiting for a communication start request (depends on user program)
Prepares for starting
communication
(generates a stop condition).
Waits for detection
of the stop condition.
No
Yes
Yes
No
INTIIC0
interrupt occurs?
INTIIC0
interrupt occurs?
Yes
No Yes
No
SPD0 = 1?
Yes
No
Slave operation
No
INTIIC0
interrupt occurs?
Yes
No
1
B
SPIE0 = 0
Yes
No
Waits for a communication request.
Waits for a communication Initial setting
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period
of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I2C bus (SCL0 and
SDA0 pins = high level) in conformance with the specifications of the product that is communicating.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 433
Figure 17-25. Master Operation Flowchart (Multi-Master System) (2/3)
STT0 = 1
Wait
Slave operation
Yes
MSTS0 = 1?
EXC0 = 1 or COI0 =1?
Prepares for starting communication
(generates a start condition).
Secure wait time by software
(see Table 17-6).
Waits for bus release
(communication being reserved).
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
No
INTIIC0
interrupt occurs?
Yes
Yes
No
No
A
C
STT0 = 1
Wait
Slave operation
Yes
IICBSY = 0?
EXC0 = 1 or COI0 =1?
Prepares for starting communication
(generates a start condition).
Disables reserving communication.
Enables reserving communication.
Secure wait time by software
(see Table 18-7).
Waits for bus release
Detects a stop condition.
No
No
INTIIC0
interrupt occurs?
Yes
Yes
No
Yes
STCF = 0? No
B
D
C
D
Communication processing Communication processing
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
434
Figure 17-25. Master Operation Flowchart (Multi-Master System) (3/3)
Writing IIC0
WTIM0 = 1
WREL0 = 1
Reading IIC0
ACKE0 = 1
WTIM0 = 0
WTIM0 = WREL0 = 1
ACKE0 = 0
Writing IIC0
Yes
TRC0 = 1?
Restart?
MSTS0 = 1?
Starts communication
(specifies an address and transfer direction).
Starts transmission.
No
Yes
Waits for data reception.
Starts reception.
Yes
No
INTIIC0
interrupt occurs?
Yes
No
Transfer end?
Waits for detection of ACK.
Yes
No
INTIIC0
interrupt occurs?
Waits for data transmission.
Does not participate
in communication.
Yes
No
INTIIC0
interrupt occurs?
No
Yes
ACKD0 = 1?
No
Yes
No
C
2
Yes
MSTS0 = 1? No
Yes
Transfer end?
No
Yes
ACKD0 = 1? No
2
Yes
MSTS0 = 1? No
2
Waits for detection of ACK.
Yes
No
INTIIC0
interrupt occurs?
Yes
MSTS0 = 1? No
C
2
Yes
EXC0 = 1 or COI0 = 1? No
1
2
SPT0 = 1
STT0 = 1
Slave operation
END
Communication processingCommunication processing
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission
and reception formats.
2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt
INTIIC0 has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICS0 and IICF0
registers each time interrupt INTIIC0 has occurred, and determine the processing to be performed
next.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 435
(3) Slave operation
The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that
must substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It
is also assumed that the INTIIC0 interrupt servicing only performs status transition processing, and that actual
data communication is performed by the main processing.
IIC0
Interrupt servicing
Main processing
INTIIC0 Flag
Setting
Data
Setting
Therefore, data communication processing is performed by preparing the following three flags and passing
them to the main processing instead of INTIIC0.
<1> Communication mode flag
This flag indicates the following two communication statuses.
• Clear mode: Status in which data communication is not performed
• Communication mode: Status in which data communication is performed (from valid address detection
to stop condition detection, no detection of ACK from master, address
mismatch)
<2> Ready flag
This flag indicates that data communication is enabled. Its function is the same as the INTIIC0 interrupt
for ordinary data communication. This flag is set by interrupt servicing and cleared by the main
processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag
is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted
without the flag being cleared (an address match is interpreted as a request for the next data).
<3> Communication direction flag
This flag indicates the direction of communication. Its value is the same as TRC0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
436
The main processing of the slave operation is explained next.
Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute
communication by using the communication mode flag and ready flag (processing of the stop condition and
start condition is performed by an interrupt. Here, check the status by using the flags).
The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the
master, communication is completed.
For reception, the necessary amount of data is received. When communication is completed, ACK is not
returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the
communication status occurs in this way.
Figure 17-26. Slave Operation Flowchart (1)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
WREL0 = 1
ACKD0 = 1?
No
Yes
No
Yes
No
START
Communication
mode flag = 1?
Communication
mode flag = 1?
Communication
direction flag = 1?
Ready flag = 1?
Communication
direction flag = 1?
Reading IIC0
Clearing ready flag
Clearing ready flag
Communication
direction flag = 1?
Clearing communication
mode flag
WREL0 = 1
Writing IIC0
IICC0 ← XXH
ACKE0 = WTIM0 = 1
SPIE0 = 0, IICE0 = 1
SVA0 ← XXH Sets a local address.
IICX0 ← 0XH
IICCL0 ← XXH
Selects a transfer clock.
IICF0 ← 0XH
Setting IICRSV
Sets a start condition.
Starts
transmission.
Starts
reception.
Communication
mode flag = 1?
Ready flag = 1?
Setting port Sets each pin to the I2C mode (see 17.3 (7) Port mode register 6 (PM6)).
Communication processing Initial setting
Remark Conform to the specifications of the product that is in communication, regarding the transmission and
reception formats.
<R>
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 437
An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing
is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the
following operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address
does not match. If the address matches, the communication mode is set, wait is cancelled, and
processing returns from the interrupt (the ready flag is cleared).
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus
remaining in the wait state.
Remark <1> to <3> above correspond to <1> to <3> in Figure 17-27 Slave Operation Flowchart (2).
Figure 17-27. Slave Operation Flowchart (2)
Yes
Yes
Yes
No
No
No
INTIIC0 generated
Set ready flag
Interrupt servicing completed
SPD0 = 1?
STD0 = 1?
COI0 = 1?
Communication direction flag
← TRC0
Set communication mode flag
Clear ready flag
Clear communication direction
flag, ready flag, and
communication mode flag
<1>
<2>
<3>
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
438
17.5.17 Timing of I2C interrupt request (INTIIC0) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the
IICS0 register when the INTIIC0 signal is generated are shown below.
Remark ST: Start condition
AD6 to AD0: Address
R/W: Transfer direction specification
ACK: Acknowledge
D7 to D0: Data
SP: Stop condition
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 439
(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B
3: IICS0 = 1000×000B (Sets WTIM0 to 1)Note
4: IICS0 = 1000××00B (Sets SPT0 to 1)Note
5: IICS0 = 00000001B
Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt
request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B
3: IICS0 = 1000××00B (Sets SPT0 to 1)
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
440
(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
STT0 = 1
↓
SPT0 = 1
↓
3 4 7 2 1 5 6
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)Note 1
3: IICS0 = 1000××00B (Clears WTIM0 to 0Note 2, sets STT0 to 1)
4: IICS0 = 1000×110B
5: IICS0 = 1000×000B (Sets WTIM0 to 1)Note 3
6: IICS0 = 1000××00B (Sets SPT0 to 1)
7: IICS0 = 00000001B
Notes 1. To generate a start condition, set WTIM0 to 1 and change the timing for generating the INTIIC0
interrupt request signal.
2. Clear WTIM0 to 0 to restore the original setting.
3. To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0
interrupt request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
STT0 = 1
↓
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets STT0 to 1)
3: IICS0 = 1000×110B
4: IICS0 = 1000××00B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 441
(c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1010×110B
2: IICS0 = 1010×000B
3: IICS0 = 1010×000B (Sets WTIM0 to 1)Note
4: IICS0 = 1010××00B (Sets SPT0 to 1)
5: IICS0 = 00000001B
Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIIC0 interrupt
request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1010×110B
2: IICS0 = 1010×100B
3: IICS0 = 1010××00B (Sets SPT0 to 1)
4: IICS0 = 00001001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
442
(2) Slave device operation (slave address data reception)
(a) Start ~ Address ~ Data ~ Data ~ Stop
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×100B
3: IICS0 = 0001××00B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 443
(b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, matches with SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×110B
4: IICS0 = 0001×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, matches with SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 0001×110B
4: IICS0 = 0001××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
444
(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0010×010B
4: IICS0 = 0010×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 5 6 2 1 4
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 0010×010B
4: IICS0 = 0010×110B
5: IICS0 = 0010××00B
6: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 445
(d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
446
(3) Slave device operation (when receiving extension code)
The device is always participating in communication when it receives an extension code.
(a) Start ~ Code ~ Data ~ Data ~ Stop
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010×100B
4: IICS0 = 0010××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 447
(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, matches SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0001×110B
4: IICS0 = 0001×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, matches SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 6 2 1 5
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 0001×110B
5: IICS0 = 0001××00B
6: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
448
(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×010B
4: IICS0 = 0010×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 7 2 1 5 6
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 0010×010B
5: IICS0 = 0010×110B
6: IICS0 = 0010××00B
7: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 449
(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 00100010B
2: IICS0 = 00100000B
3: IICS0 = 00000110B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 00100010B
2: IICS0 = 00100110B
3: IICS0 = 00100×00B
4: IICS0 = 00000110B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
450
(4) Operation without communication
(a) Start ~ Code ~ Data ~ Data ~ Stop
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
1
1: IICS0 = 00000001B
Remark : Generated only when SPIE0 = 1
(5) Arbitration loss operation (operation as slave after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIIC0 has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0101×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 451
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0101×110B
2: IICS0 = 0001×100B
3: IICS0 = 0001××00B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(b) When arbitration loss occurs during transmission of extension code
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0110×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
452
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 5 2 1
1: IICS0 = 0110×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010×100B
4: IICS0 = 0010××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(6) Operation when arbitration loss occurs (no communication after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIIC0 has occurred to check the arbitration result.
(a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1)
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
2 1
1: IICS0 = 01000110B
2: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 453
(b) When arbitration loss occurs during transmission of extension code
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
2 1
1: IICS0 = 0110×010B
Sets LREL0 = 1 by software
2: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(c) When arbitration loss occurs during transmission of data
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 2 1
1: IICS0 = 10001110B
2: IICS0 = 01000000B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
454
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 2 1
1: IICS0 = 10001110B
2: IICS0 = 01000100B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
(d) When loss occurs due to restart condition during data transfer
(i) Not extension code (Example: unmatches with SVA0)
ST AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 ACK SPST R/W D7 to D0 ACK
3 2 1
1: IICS0 = 1000×110B
2: IICS0 = 01000110B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 455
(ii) Extension code
ST AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 ACK SPST R/W D7 to D0 ACK
3 2 1
1: IICS0 = 1000×110B
2: IICS0 = 01100010B
Sets LREL0 = 1 by software
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
(e) When loss occurs due to stop condition during data transfer
ST AD6 to AD0 R/W ACK D7 to Dn SP
2 1
1: IICS0 = 10000110B
2: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
456
(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
STT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000×100B (Clears WTIM0 to 0)
4: IICS0 = 01000000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
STT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B (Sets STT0 to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 457
(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart
condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
STT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000××00B (Sets STT0 to 1)
4: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
STT0 = 1
↓
2 3 1
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets STT0 to 1)
3: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
458
(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets WTIM0 to 1)
3: IICS0 = 1000×100B (Clears WTIM0 to 0)
4: IICS0 = 01000100B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B (Sets SPT0 to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 459
17.6 Timing Charts
When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several
slave devices as its communication partner.
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 17-28 and 17-29 show timing charts of the data communication.
IIC shift register 0 (IIC0)’s shift operation is synchronized with the falling edge of the serial clock (SCL0). The
transmit data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin.
Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
460
Figure 17-28. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
(1) Start condition ~ address
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
L
H
H
H
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
Processing by slave device
123456789 4321
AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4D5D6D7
IIC0 ← address IIC0 ← data
IIC0 ← FFH
Transmit
Start condition
Receive
(When EXC0 = 1)
Note
Note
Note To cancel slave wait, write “FFH” to IIC0 or set WREL0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 461
Figure 17-28. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (2/3)
(2) Data
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
Processing by slave device
198 23456789 321
D7D0 D6 D5 D4 D3 D2 D1 D0 D5D6D7
IIC0 ← data
IIC0 ← FFH IIC0 ← FFH
IIC0 ← data
Transmit
Receive
Note Note
ACKACK
Note Note
Note To cancel slave wait, write “FFH” to IIC0 or set WREL0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
462
Figure 17-28. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
(3) Stop condition
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
L
H
H
H
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
Processing by slave device
123456789 21
D7 D6 D5 D4 D3 D2 D1 D0 AD5AD6
IIC0 ← data IIC0 ← address
IIC0 ← FFH Note IIC0 ← FFH Note
Stop
condition
Start
condition
Transmit
Note Note
(When SPIE0 = 1)
Receive
(When SPIE0 = 1)
ACK
Note To cancel slave wait, write “FFH” to IIC0 or set WREL0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 463
Figure 17-29. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3)
(1) Start condition ~ address
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
H
L
ACKE0
MSTS0
STT0
L
L
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
Processing by slave device
123456789 4 56321
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R D4 D3 D2D5D6D7
IIC0 ← address IIC0 ← FFH Note
Note
IIC0 ← data
Start condition
ACK
Note To cancel master wait, write “FFH” to IIC0 or set WREL0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
464
Figure 17-29. Example of Slave to Master Communication
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
(2) Data
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
H
L
L
L
L
L
L
L
H
H
L
L
L
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
Processing by slave device
1
89 23456789 321
D7
D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5D6D7
Note Note
Receive
Transmit
IIC0 ← data IIC0 ← data
IIC0 ← FFH Note IIC0 ← FFH Note
Note To cancel master wait, write “FFH” to IIC0 or set WREL0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 465
Figure 17-29. Example of Slave to Master Communication
(When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(3) Stop condition
IIC0
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
IIC0
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIIC0
TRC0
SCL0
SDA0
Processing by master device
Transfer lines
Processing by slave device
12345678 9 1
D7 D6 D5 D4 D3 D2 D1 D0 AD6
IIC0 ← address
IIC0 ← FFH Note
Note
IIC0 ← data
Stop
condition
Start
condition
(When SPIE0 = 1)
NACK
(When SPIE0 = 1)
Note To cancel master wait, write “FFH” to IIC0 or set WREL0.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD
466
17.7 Communication with LCD Controller/Driver
With the 78K0/LG2, setting to LCD controller/driver is performed via the I2C bus interface. Therefore reading and
writing to the LCD controller/driver registers can be performed.
17.7.1 System configuration
The system configuration of the LCD controller/driver in the 78K0/LG2 is illustrated in Figure 17-30.
Figure 17-30. System configuration
CPU part LCD part
78K0/LG2
P60/SCL0
P61/SDA0
SDA0 SCL0
Serial clock
Serial data bus
VDD VDD
LSCL
LSDA
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 467
17.7.2 Write operation
The processing procedure, format, and operation of writing to the LCD controller/driver via the I2C bus interface are
explained below.
The LCD controller/driver register to be accessed can be specified with the slave ID and address (see Figure 18-3).
(1) Processing procedure
Figure 17-31. Processing procedure of Write Operation
Remark ST: Start condition
RST: Restart condition
SP: Stop condition
Slave ID reception
Yes
ST detected?
ID matched?
ACK‘—M
ACK transmission
Address reception
WD reception
SP detection
End
LCD controller/driver side (slave)
Yes
No
No
Yes
No
Slave ID transmission
Address transmission
WD transmission
End
CPU side (master)
ST generation
ACK reception
Yes
ACK transmission
SP generation
No
ACK transmission
ACK reception
Yes
No
ACK reception
Yes
No
Completed?
Yes
No
Transfer direction
CHAPTER 17 SERIAL INTERFACE IIC0
468 User’s Manual U17473EJ2V0UD
(2) Communication format
Write data to each register on the LCD controller/driver starting from the start condition, slave ID, address,
write data, then stop condition in that order.
Figure 17-32. Communication Format for Write Operation (When Writing Twice)
Access
target
<1>
ST
<2>
Slave ID
<3>
R/W
<4>
ACK
<5>
Address
<6>
ACK
LCDCTL ST 0 1 1 1 0 0 0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
LCDSEG ST 0 1 1 1 0 0 1 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
<7>
Write data 1
<8>
ACK
<9>
Write data 2
<10>
ACK
<11>
SP
D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK SP
D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK SP
Note With the 78K0/LG2, the address is incremented by one based on the register read/write start address by
continuously performing read/write access from transmissions of the start condition to stop condition. With
this function, the address does not need to be set each time.
Cautions 1. Generate a stop condition if an access like the one shown below is made.
• An access made in a format other than specified
• An access made with a slave ID other than specified
2. When SDA0 is fixed at the low level output status due to noise, input 0 to P130 (bit 0 of port
register 13) to reset the LCD controller/driver.
Remark ST: Start condition
SP: Stop condition
A7 to A0: Addresses for LCDCTL or LCDSEG
Address
LCDCTL : A7, A6, A5, A4, A3, A2, A1, A0
LCDSEG: A7, A6, A5, A4, A3, A2, A1, A0
AddressNote
LCDCTL : (A7, A6, A5, A4, A3, A2, A1, A0) + 1
LCDSEG: (A7, A6, A5, A4, A3, A2, A1, A0) + 1
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 469
(3) Operation
The operation flow when transmitting write data twice is shown below.
Steps <1> to <11> correspond to <1> to <11> in Figure 17-32.
<1> The start condition is transmitted.
<2> The slave ID is transmitted (from the 1st to 7th clocks).
<3> R/W information (0) is transmitted (at the 8th clock).
<4> An acknowledge signal is received (at the rising edge of the 9th clock).
<5> The write start address is transmitted (from the 1st to 8th clocks following <4>).
<6> An acknowledge signal is received (at the rising edge of the 9th clock).
<7> Write data is transmitted (first time) (from the 1st to 8th clocks following <6>).
<8> An acknowledge signal is received (at the rising edge of the 9th clock).
<9> Write data is transmitted (second time) (from the 1st to 8th clocks following <8>).
(The address is automatically incremented by 1.)
<10> An acknowledge signal is received (at the rising edge of the 9th clock).
<11> The stop condition is transmitted.
Figures 17-33 shows the timing chart of the write operation.
Figure 17-33. Timing Chart of Write Operation
189 1
ID6 RACK 0
189 1
ID6
ACK
xxH xxHxxH xxH
xxH
xxH
xxH
Write to IIC shift register 0
Setup
89
A0
89
A0 ACK
ACK
xxH
xxH
xxH
xxH
189
189
WD0
WD0
xxHxxH xxH
xxHxxH xxH
Start condition Stop condition
Start condition
189 189 819
0
xxH
WWD7
ACK
ACKWD7
SCL
SDA
SCL0
SDA0
LSCL
LSDA
Master
IIC shift
register 0
IIC bus
Slave
IIC shift
register
Write to IIC shift register 0 Write to IIC shift register 0
Stop condition
Setup Setup
CHAPTER 17 SERIAL INTERFACE IIC0
470 User’s Manual U17473EJ2V0UD
17.7.3 Read operation
The processing procedure, format, and operation of reading the LCD controller/driver via the I2C bus interface are
explained below.
The LCD controller/driver register to be accessed can be specified with the slave ID and address (see Figure 18-3).
(1) Processing procedure
Figure 17-34. Processing procedure of Read Operation
Remark ST: Start condition
RST: Restart condition
SP: Stop condition
Slave ID reception
Yes
ST detected?
No
ID matched?
ACK‘—MACK transmission
Address reception
RST detected?
Slave ID reception
ID matched?
RD transmission
ACK reception
SP detection
End
Yes
LCD controller/driver side (slave)
No
No
Yes
Yes
No
No
Yes
No
Slave ID transmission
Address transmission
Slave ID transmission
RD reception
ACK transmission
End
Yes
CPU side (master)
Yes
No
ST generation
ACK reception
Yes
RST generation
ACK transmissionACK reception
Yes
SP generation
No
No
Transfer direction
ACK reception
Yes
No ACK transmission
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 471
(2) Communication format
Read data from each register on the LCD controller/driver starting from the start condition, slave ID, address,
restart condition, slave ID, read data, then stop condition in that order.
Figure 17-35. Communication Format for Read Operation (When Reading Twice)
Access
target
<1>
ST
<2>
Slave ID
<3>
R/W
<4>
ACK
<5>
Address
<6>
ACK
LCDCTL ST 0 1 1 1 0 0 0 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
LCDSEG ST 0 1 1 1 0 0 1 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
<7>
RST
<8>
Slave ID
<9>
R/W
<10>
ACK
<11>
Read dara 1
<12>
ACK
RST 0 1 1 1 0 0 0 1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
RST 0 1 1 1 0 0 1 1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
<13>
Read data2
<14>
ACK
<15>
SP
D7 D6 D5 D4 D3 D2 D1 D0 NAK SP
D7 D6 D5 D4 D3 D2 D1 D0 NAK SP
Note With the 78K0/LG2, the address is incremented by one based on the register read/write start address by
continuously performing read/write access from transmissions of the start condition to stop condition. With
this function, the address does not need to be set each time.
Cautions 1. Generate a stop condition if an access like the one shown below is made.
• An access made in a format other than specified
• An access made with a slave ID other than specified
2. When SDA0 is fixed at the low level output status due to noise, input 0 to P130 (bit 0 of port
register 13) to reset the LCD controller/driver.
Remark ST: Start condition
RST: Restart condition
SP: Stop condition
A7 to A0: Addresses for LCDCTL or LCDSEG
Address
LCDCTL : A7, A6, A5, A4, A3, A2, A1, A0
LCDSEG: A7, A6, A5, A4, A3, A2, A1, A0
AddressNote
LCDCTL : (A7, A6, A5, A4, A3, A2, A1, A0) + 1
LCDSEG: (A7, A6, A5, A4, A3, A2, A1, A0) + 1
CHAPTER 17 SERIAL INTERFACE IIC0
472 User’s Manual U17473EJ2V0UD
(3) Operation
The operation flow when receiving read data twice is shown below.
Steps <1> to <15> correspond to <1> to <15> in Figure 17-35.
<1> The start condition is transmitted.
<2> The slave ID is transmitted (first time) (from the 1st to 7th clocks).
<3> R/W information (0) is transmitted (at the 8th clock).
<4> An acknowledge signal is received (at the rising edge of the 9th clock).
<5> The read start address is transmitted (from the 1st to 8th clocks following <4>).
<6> An acknowledge signal is received (at the rising edge of the 9th clock).
<7> The restart condition is transmitted.
<8> The slave ID is transmitted (second time) (from the 1st to 7th clocks following <7>).
<9> R/W information (1) is transmitted (at the 8th clock).
<10> An acknowledge signal is received (at the rising edge of the 9th clock).
<11> Read data is received (first time) (from the 1st to 8th clocks following <10>).
<12> An acknowledge signal is transmitted (from the falling edge of the 8th clock to the falling edge of the 9th
clock).
<13> Read data is received (second time) (from the 1st to 8th clocks following <12>).
(The address is automatically incremented by 1.)
<14> Stop the acknowledge signal transmission. Note
<15> The stop condition is transmitted.
Note Do not transmit the acknowledge signal when completing data reception.
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17473EJ2V0UD 473
Figures 17-36 shows the timing chart of the read operation.
Figure 17-36. Timing Chart of Read Operation
(Continued from above)
SCL 12 789 12
ID6 ID5 ID0 WACK
SDA 00
SCL0 12 789 12
ID6 ID5 ID0 W
SDA0 00
LSCL
ACK
LSDA
Master
IIC shift
register 0 xxH xxH xxH xxH xxHxxH xxHxxH xxH
xxH xxHxxH
Write to IIC shift register 0
Setup
IIC bus
89
xxH xxH
A0
89
A0 ACK
xxH xxHxxH xxH xxH
ACK
12 789 1 829
Slave
Start condition Setup
Start condition
IIC shift
register
189 1
ID6 RACK RD7
189 1
ID6 R
RD7ACK
xxH xxHxxH xxH
xxH
xxH
xxH
Setup
89
RD0
89
RD0 ACK
ACK
xxH
xxH xxH
FFH
Write FFH or WREL0 = 1
xxH
189
189
RD7 RD0
RD7 RD0
xxH xxHxxH xxH xxH
xxHxxH xxHFFH
Write FFH or WREL0 = 1
Restart condition Stop condition
189 189 81
Stop condition
9
SCL
SDA
SCL0
SDA0
LSCL
LSDA
Master
IIC shift
register 0
IIC shift
register
IIC bus
Slave
Setup
Write to IIC shift register 0
Setup
Write to IIC shift register Write to IIC shift register Write to IIC shift register
Restart condition
User’s Manual U17473EJ2V0UD
474
CHAPTER 18 LCD CONTROLLER/DRIVER
With the 78K0/LG2, setting to LCD controller/driver is performed via the I2C bus interface. Therefore reading and
writing to the LCD controller/driver registers can be performed (see 17.7 Communication with LCD
Controller/Driver).
18.1 Functions of LCD Controller/Driver
The functions of the LCD controller/driver in the 78K0/LG2 are as follows.
(1) The LCD driver reference voltage generator can switch internal voltage boosting, external resistance division,
and internal resistance division.
(2) Automatic output of segment and common signals based on automatic display data memory read
(3) Five different display modes:
• Static
• 1/2 duty (1/2 bias)
• 1/3 duty (1/2 bias)
• 1/3 duty (1/3 bias)
• 1/4 duty (1/3 bias)
(4) Four different frame frequencies, selectable in each display mode
(5) Up to 40 segment signal outputs (S0 to S39) and four common signal outputs (COM0 to COM3)
Table 18-1 lists the maximum number of pixels that can be displayed in each display mode.
Table 18-1. Maximum Number of Pixels
LCD Driver Reference
Voltage Generator
Bias
Mode
Number of
Time Slices
Common Signals Used Number of
Segments
Maximum Number of
Pixels
− Static COM0 (COM1 to COM3) 40 (40 segment signals,
1 common signal)Note 1
2 COM0, COM1 80 (40 segment signals,
2 common signals)Note 2
• External resistance division
• Internal resistance division
1/2
3 COM0 to COM2
3 COM0 to COM2
120 (40 segment signals,
3 common signals)Note 3
• Internal voltage boosting
• External resistance division
• Internal resistance division
1/3
4 COM0 to COM3
40
160 (40 segment signals,
4 common signals)Note 4
Notes 1. 5-digit LCD panel, each digit having an 8-segment configuration.
2. 10-digit LCD panel, each digit having a 4-segment configuration.
3. 15-digit LCD panel, each digit having a 3-segment configuration.
4. 20-digit LCD panel, each digit having a 2-segment configuration.
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 475
18.2 Configuration of LCD Controller/Driver
The LCD controller/driver consists of the following hardware.
The LCD controller/driver includes of two blocks: LCDSEG block for controlling segments, and LCDCTL block for
controlling LCD register setting and mode setting.
Table 18-2. Configuration of LCD Controller/Driver
Item Configuration
Display outputs
(LCDSEG)
20 bytes display RAM
• 40 segment signals
• 4 common signals (COM0 to COM3)
LCD
controller/
driver
Control registers
(LCDCTL)
LCD mode setting register (LCDMD)
LCD display mode register (LCDM)
LCD clock control register (LCDC)
LCD voltage boost control register 0 (VLCG0)
CPU Control registers Clock output selection register (CKS)
Port register 13 (P13)
Port mode register 14 (PM14)
Figure 18-1. Hardware Configuration of LCD Controller/Driver
LCD Controller
LCD Driver
LCDCTL
I
2
C Bus Interface
LCDSEG
CPU
SCL0
SDA0
P13
CKS PM14
Reset Input
Clock Input
f
PCL
CHAPTER 18 LCD CONTROLLER/DRIVER
476 User’s Manual U17473EJ2V0UD
Internal bus
LCDC3 LCDC2
LCDC1
LCDC0
2
2
Prescaler
LCD
clock
selector
selector
fLCD
26
fLCD
27
fLCD
28
fLCD
29
LCD clock control
register (LCDC)
VLCON
LCDM2
LCD display mode
register (LCDM)
VLC0
Segment
driver
Common
driver
COM0 COM1 COM2 COM3
3210
32106574
LCDSEG's 00H
LCDON
Segment
driver
32106574
LCDSEG's 27H
S39
fPCL
fPCL/2
fPCL/22
S0
- - - - - - - - - -
fLCD
selector
3210
LCDON
LCDCL
LCDM1
GAIN
LCD voltage boost control
register 0 (VLCG0)
VLC2
CAPH CAPL VLC1
-------
-------
-------
-------
-------
-------
-------
Timing
controller
VLCON
LCDM0
CTSEL1
CTSEL0
LCDON
SCOC
SEGSET0
MDSET1
LCD mode setting
register (LCDMD)
MDSET0
SEGSET2
SEGSET1
LCD drive voltage controller
2
3
Selector
Clock
generator for
boosting
Booster
circuit
Segment voltage
controller
Common voltage
controller
Segment voltage
controller
Display data memory
Figure 18-2. Block Diagram of LCD Controller/Driver
Remark f
PCL
: The clock generated by the clock output controller
-------
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 477
18.3 Controlling LCD Controller/Driver
LCDCTL (operating mode control part) and LCDSEG (display part) have the individual slave ID, and control
registers and display RAM have unique addresses. The target control registers and display RAM are accessed by I2C
with these slave ID and addresses.
Table 18-3. Slave ID and Address of LCDCTL and LCDSEG
Block Control registers/Display RAM
Slave ID (7 bits) Address (8 bits)
LCD mode setting register (LCDMD) 00H
LCD display mode register (LCDM) 01H
LCD clock control register (LCDC) 02H
LCDCTL
(Control block)
0 1 1 1 0 0 0
LCD voltage boost control register 0 (VLCG0) 03H
LCDSEG
(Display block)
0 1 1 1 0 0 1 S0-S39 00H-27H
Remark For details of communication format, see 17.7 Communication with LCD Controller/Driver.
<R>
CHAPTER 18 LCD CONTROLLER/DRIVER
478 User’s Manual U17473EJ2V0UD
Figure 18-3 shows the controll register of LCD controller/driver, and Figure 18-4 shows the LCD display RAM.
Figure 18-3. Controll Register of LCD Controller/Driver
Address Bit Register
7 6 5 4 3 2 1 0
LCDCTL's 03H CTSEL1 CTSEL0 0 0 0 0 0
GAIN → VLCG0
02H 0 0 0 0
LCDC3 LCDC2 LCDC1 LCDC0 → LCDC
01H LCDON SCOC VLCON 0 0
LCDM2 LCDM1 LCDM0 → LCDM
LCDCTL's 00H SEGSET2 SEGSET1 SEGSET0 0 0 0
MDSET1 MDSET0 → LCDMD
Figure 18-4. LCD Display RAM
Address Bit Segment
7 6 5 4 3 2 1 0
LCDSEG's 27H 0 0 0 0
→ S39
26H 0 0 0 0
→ S38
25H 0 0 0 0
→ S37
24H 0 0 0 0
→ S36
23H 0 0 0 0
→ S35
22H 0 0 0 0
→ S34
21H 0 0 0 0
→ S33
20H 0 0 0 0
→ S32
1FH 0 0 0 0
→ S31
1EH 0 0 0 0
→ S30
1DH 0 0 0 0
→ S29
1CH 0 0 0 0
→ S28
1BH 0 0 0 0
→ S27
1AH 0 0 0 0
→ S26
19H 0 0 0 0
→ S25
18H 0 0 0 0
→ S24
17H 0 0 0 0
→ S23
16H 0 0 0 0
→ S22
15H 0 0 0 0
→ S21
14H 0 0 0 0
→ S20
13H 0 0 0 0
→ S19
12H 0 0 0 0
→ S18
11H 0 0 0 0
→ S17
10H 0 0 0 0
→ S16
0FH 0 0 0 0
→ S15
0EH 0 0 0 0
→ S14
0DH 0 0 0 0
→ S13
0CH 0 0 0 0
→ S12
0BH 0 0 0 0
→ S11
0AH 0 0 0 0
→ S10
09H 0 0 0 0
→ S9
08H 0 0 0 0
→ S8
07H 0 0 0 0
→ S7
06H 0 0 0 0
→ S6
05H 0 0 0 0
→ S5
04H 0 0 0 0
→ S4
03H 0 0 0 0
→ S3
02H 0 0 0 0
→ S2
01H 0 0 0 0
→ S1
LCDSEG's 00H 0 0 0 0
→ S0
Common
↑
COM3
↑
COM2
↑
COM1
↑
COM0
Remark Bits 4 to 7 are fixed to 0.
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 479
18.4 Registers Controlling LCD Controller/Driver
The following seven registers are used to control the LCD controller/driver.
• LCD mode setting register (LCDMD)
• LCD display mode register (LCDM)
• LCD clock control register (LCDC)
• LCD voltage boost control register 0 (VLCG0)
• Clock output selection register (CKS)
• Port register 13 (P13)
• Port mode register 14 (PM14)
(1) LCD mode setting register (LCDMD)
LCDMD sets the number of segments and the LCD reference voltage generator.
LCDMD is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDMD to 00H.
Figure 18-5. Format of LCD Mode Setting Register
Address: LCDCTL's 00H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
LCDMD SEGSET2 SEGSET1 SEGSET0 0 0 0 MDSET1 MDSET0
SEGSET2 SEGSET1 SEGSET0 Segment number setting
0 0 × 40
Other than above Setting prohibited
MDSET1 MDSET0 LCD reference voltage generator selection
0 0 External resistance division method
0 1 Internal resistance division method
1 × Internal voltage boosting method
Cautions 1. Bits 2 to 4 must be set to 0.
2. LCDMD can be set only once after a reset release.
CHAPTER 18 LCD CONTROLLER/DRIVER
480 User’s Manual U17473EJ2V0UD
(2) LCD display mode register (LCDM)
LCDM specifies whether to enable display operation. It also specifies whether to enable segment
pin/common pin output, booster circuit operation, and the display mode.
LCDM is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDM to 00H.
Figure 18-6. Format of LCD Display Mode Register
Address: LCDCTL's 01H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
LCDM LCDON SCOC VLCON 0 0 LCDM2 LCDM1 LCDM0
LCDON LCD display enable/disable
0 Display off (all segment outputs are deselected.)
1 Display on
SCOC Segment pin/common pin output controlNote
0 Output ground level to segment/common pin
1 Output deselect level to segment pin and LCD waveform to common pin
VLCON Booster circuit operation enable/disableNote
0 No internal voltage boosting
1 Internal voltage boosting enabled
LCD controller/driver display mode selection
Resistance division method Voltage boosting method
LCDM2 LCDM1 LCDM0
Number of
time slices
Bias mode Number of
time slices
Bias mode
0 0 0 4 1/3 4 1/3
0 0 1 3 1/3 3 1/3
0 1 0 2 1/2 4 1/3
0 1 1 3 1/2 3 1/3
1 0 0 Static Setting prohibited
Other than above Setting prohibited
Note When the LCD display panel is not used, SCOC and VLCON must be set to 0 to conserve power.
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 481
Cautions 1. Bits 3 and 4 must be set to 0.
2. When operating VLCON, follow the procedure described below.
A. To stop voltage boosting after switching display status from on to off:
1) Set to display off status by setting LCDON = 0.
2) Disable outputs of all the segment buffers and common buffers by setting
SCOC = 0.
3) Stop voltage boosting by setting VLCON = 0.
B. To stop voltage boosting during display on status:
Setting prohibited. Be sure to stop voltage boosting after setting display off.
C. To set display on from voltage boosting stop status:
1) Start voltage boosting by setting VLCON = 1, then wait for voltage boost wait time
(tVAWAIT) (see CHAPTER 30 ELECTRICAL SPECIFICATIONS).
2) Set all the segment buffers and common buffers to non-display output status
by setting SCOC = 1.
3) Set display on by setting LCDON = 1.
(3) LCD clock control register (LCDC)
LCDC specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDC to 00H.
Figure 18-7. Format of LCD Clock Control Register
Address: LCDCTL's 02H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
LCDC 0 0 0 0 LCDC3 LCDC2 LCDC1 LCDC0
LCDC3 LCDC2 LCD source clock (fLCD) selectionNote
0 × fPCL (Clock generated by clock output controller)
1 0 fPCL/2
1 1 fPCL/22
LCDC1 LCDC0 LCD clock (LCDCL) selection
0 0 fLCD/26
0 1 fLCD/27
1 0 fLCD/28
1 1 fLCD/29
Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz.
Cautions 1. Bits 4 to 7 must be set to 0.
2. Before changing the LCDC setting, be sure to stop voltage boosting (VLCON = 0).
3. Set the frame frequency to 128 Hz or lower.
CHAPTER 18 LCD CONTROLLER/DRIVER
482 User’s Manual U17473EJ2V0UD
(4) LCD voltage boost control register 0 (VLCG0)
VLCG0 controls the voltage boost level during the voltage boost operation.
VLCG0 is set with an 8-bit memory manipulation instruction.
Reset signal generation sets VLCG0 to 00H.
Figure 18-8. Format of LCD Voltage Boost Control Register 0
Address: LCDCTL's 03H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
VLCG0 CTSEL1 CTSEL0 0 0 0 0 0 GAIN
GAIN Reference voltage (VLC2) level selectionNote1
0 1.5 V (specification of the LCD panel used is 4.5 V.)
1 1.0 V (specification of the LCD panel used is 3 V.)
Contrast adjustment (TYP.) Note2
VLC0 VLC1 VLC2
CTSEL1 CTSEL0
GAIN = 0 GAIN = 1 GAIN = 0 GAIN = 1 GAIN = 0 GAIN = 1
1 0 4.89 V 3.39 V 3.27 V 2.27 V 1.63 V 1.13 V
1 1 4.71 V 3.21 V 3.13 V 2.13 V 1.57 V 1.07 V
0 0 4.50 V 3.00 V 3.00 V 2.00 V 1.50 V 1.00 V
0 1 4.29 V 2.79 V 2.87 V 1.87 V 1.43 V 0.93 V
Notes 1. Select the settings according to the specifications of the LCD panel that is used.
2. Set these bits so that LVDD after voltage boosting becomes 2.0 to 5.5 V.
Cautions 1. Bits 1 to 5 must be set to 0.
2. Before changing the VLCG0 setting, be sure to stop voltage boosting (VLCON = 0).
<R>
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 483
(5) Clock output selection register (CKS)
CKS enables/disables the clock output to the LCD controller/driver, and sets the output clock.
CKS is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets CKS to 00H.
Figure 18-9. Format of Clock Output Selection Register
Address: FF40H After reset: 00H R/W
Symbol 7 6 5 3 2 1 0
CKS 0 0 0 CLOE CCS3 CCS2 CCS1 CCS0
CLOE
PM140 Specification of enable/disable for clock output
to LCD controller/driverNote
1
0 Clock output to LCD controller/driver enabled
Other than above Clock output to LCD controller/driver disabled
LCD output clock selection
CCS3 CCS2 CCS1 CCS0
f
SUB =
32.768 kHz
fPRS =
10 MHz
fPRS =
20 MHz
0 1 1 0 fPRS/26156.25 kHz 312.5 kHz
0 1 1 1 fPRS/27
-
78.125 kHz 156.25 kHz
1 0 0 0 fSUB 32.768 kHz -
Other than above Setting prohibited
Note Enabling/disabling the PCL clock output is specified by combining the PM140 settings (see (7) Port
mode register 14 (PM14)).
Cautions 1. Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
2. Bits 5 to 7 must be set to 0.
Remarks 1. fPRS: Peripheral hardware clock oscillation frequency
2. fSUB: Subsystem clock oscillation frequency
4
CHAPTER 18 LCD CONTROLLER/DRIVER
484 User’s Manual U17473EJ2V0UD
(6) Port register 13 (P13)
P13 controls the reset for the LCD controller/driver.
When using the LCD controller/driver, set P130 to 1.
P13 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets P13 to 00H.
Figure 18-10. Format of Port Register 13
Address: FF0DH After reset: 00H (Output latch) R/W
Symbol 7 6 5 4 3 2 1 0
P13 0 0 0 0 0 0 0 P130
P130 LCD controller/driver reset control
0 Reset status set
1 Reset status released
(7) Port mode register 14 (PM14)
PM14 controls the clock output to the LCD controller/driver.
When using the LCD controller/driver, set PM140 to 0.
PM14 is set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM14 to FFH.
Figure 18-11. Format of Port Mode Register 14
Address: FF2EH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM14 1 1 1 1 1 1 PM141 PM140
PM140 Clock output control to LCD controller/driver
0 Clock output to LCD controller/driver enabled
1 Clock output to LCD controller/driver disabled
Caution After a reset release, be sure to set PM141 to 0.
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 485
18.5 Setting LCD Controller/Driver
Set the LCD controller/driver using the following procedure.
(1) Voltage boosting method
• Operation flow for transition of reset status to display status in LCD controller/driver
<1> Set P130 = 1 to release the reset status.
<2> Set the output clock using the clock output selection register (CKS).
<3> Set PM140 = 0 to set output mode.
<4> Set CLOE (bit 4 of CKS) to 1 to enable the clock output.
<5> Set MDSET1 (bit 1 of LCDMD) to 1 to set the internal voltage boosting method
(initial setting: external resistance division method)
<6> Set the initial values to the LCD display data area (bits 0 to 3) in the LCD display RAM.
<7> Set the display mode using LCDM0, LCDM1, and LCDM2 (bits 0, 1, and 2 of LCD display mode register
(LCDM)) (1/2 bias mode and static mode cannot be set).
<8> Set the LCD clock using LCD clock control register (LCDC).
<9> Set the voltage boost level and contrasts using LCD voltage boost control register 0 (VLCG0).
GAIN = 0: VLC0 = 4.5 V, VLC1 = 3 V, VLC2 = 1.5 V
GAIN = 1: VLC0 = 3 V, VLC1 = 2 V, VLC2 = 1 V
<10> Set VLCON (bit 5 of LCDM) to 1 to enable voltage boosting.
<11> Wait for voltage boost wait time (tVAWAIT) from setting of VLCON (see CHAPTER 30 ELECTRICAL
SPECIFICATIONS).
<12> Set SCOC (bit 6 of LCDM) to 1 to output the deselect voltage.
<13> Set LCDON (bit 7 of LCDM) to 1 and set data to the data memory in accordance with the display
contents, after the output corresponding to each data memory is started.
Subsequent to this procedure, set the data to be displayed in the data memory.
Remark The register can be set in 1-bit units because the I2C bus is used for setting.
CHAPTER 18 LCD CONTROLLER/DRIVER
486 User’s Manual U17473EJ2V0UD
(2) Resistance division method
• Operation flow for transition of reset status to display status in LCD controller/driver
<1> Set P130 = 1 to release the reset status.
<2> Set the output clock using the clock output selection register (CKS).
<3> Set PM140 = 0 to set output mode.
<4> Set CLOE (bit 4 of CKS) to 1 to enable the clock output.
<5> Set to the internal voltage boosting method using MDSET0 and MDSET1 (bit 0 and 1 of LCDMD).
(MDSET0, MDSET1 = 0, 0: External resistance division method,
MDSET0, MDSET1 = 0, 1: Internal resistance division method)
<6> Set the initial values to the LCD display data area (bits 0 to 3) in the LCD display RAM.
<7> Set the display mode using LCDM0, LCDM1, and LCDM2 (bits 0, 1, and 2 of LCD display mode register
(LCDM)).
<8> Set the LCD clock using LCD clock control register (LCDC).
<9> Set SCOC (bit 6 of LCDM) to 1 to output the deselect voltage.
<10> Set LCDON (bit 7 of LCDM) to 1 and set data to the data memory in accordance with the display
contents, after the output corresponding to each data memory is started.
Subsequent to this procedure, set the data to be displayed in the data memory.
Remark The register can be set in 1-bit units because the I2C bus is used for setting.
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 487
18.6 LCD Display Data Memory
The LCD display data memory is mapped at addresses 00H to 27H of LCDSEG. Data in the LCD display data
memory can be displayed on the LCD panel using the LCD controller/driver.
Figure 18-12 shows the relationship between the contents of the LCD display data memory and the
segment/common outputs.
Figure 18-12. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs
S0
LCDSEG's 00H
S1
LCDSEG's 01H
S2
LCDSEG's 02H
S3
LCDSEG's 03H
S37
LCDSEG's 25H
S38
LCDSEG's 26H
S39
LCDSEG's 27H
COM3 COM2 COM1 COM0
b7 b6 b5 b4 b3 b2 b1 b0
Address
Caution No memory is allocated to the higher 4 bits of the LCD display data memory. Be sure to set
there bits to 0.
CHAPTER 18 LCD CONTROLLER/DRIVER
488 User’s Manual U17473EJ2V0UD
18.7 Common and Segment Signals
Each pixel of the LCD panel turns on when the potential difference between the corresponding common and
segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the
potential difference becomes lower than VLCD.
Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this
problem, this LCD panel is driven by AC voltage.
(1) Common signals
Each common signal is selected sequentially according to a specified number of time slices at the timing
listed in Table 18-4. In the static display mode, the same signal is output to COM0 to COM3.
In the two-time-slice mode, leave the COM2 and COM3 pins open. In the three-time-slice mode, leave the
COM3 pin open.
Table 18-4. COM Signals
COM0 COM1 COM2 COM3COM Signal
Number of Time Slices
Static display mode
Two-time-slice mode
Three-time-slice mode
Four-time-slice mode
Open Open
Open
(2) Segment signals
The segment signals correspond to 40 bytes of LCD display data memory (00H to 27H of LCDSEG). Bits 0,
1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If a
bit is 1, it is converted to the select voltage, and if it is 0, it is converted to the deselect voltage. The
conversion results are output to the segment pins (S0 to S39).
Check, with the information given above, what combination of front-surface electrodes (corresponding to the
segment signals) and rear-surface electrodes (corresponding to the common signals) forms display patterns
in the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a
one-to-one basis.
LCD display data memory bits 1 to 3, bits 2 and 3, and bit 3 are not used for LCD display in the static display,
two-time slot, and three-time slot modes, respectively. So these bits can be used for purposes other than
display.
LCD display data memory bits 4 to 7 are fixed to 0.
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 489
(3) Output waveforms of common and segment signals
The voltages listed in Table 18-5 are output as common and segment signals.
When both common and segment signals are at the select voltage, a display on-voltage of ±VLCD is obtained.
The other combinations of the signals correspond to the display off-voltage.
Table 18-5. LCD Drive Voltage
(a) Static display mode
Segment Signal Select Signal Level Deselect Signal Level
Common Signal LVSS/VLC0 VLC0/LVSS
VLC0/LVSS –VLCD/+VLCD 0 V/0 V
(b) 1/2 bias method
Segment Signal Select Signal Level Deselect Signal Level
Common Signal LVSS/VLC0 VLC0/LVSS
Select signal level VLC0/LVSS –VLCD/+VLCD 0 V/0 V
Deselect signal level VLC1 = VLC2 – VLCD/+ VLCD + VLCD/– VLCD
(c) 1/3 bias method
Segment Signal Select Signal Level Deselect Signal Level
Common Signal LVSS/VLC0 VLC1/VLC2
Select signal level VLC0/LVSS –VLCD/+VLCD – VLCD/+ VLCD
Deselect signal level VLC2/VLC1 – VLCD/+ VLCD – VLCD/+ VLCD
1
2
1
2
1
2
1
2
1
3
1
3
1
3
1
3
1
3
1
3
CHAPTER 18 LCD CONTROLLER/DRIVER
490 User’s Manual U17473EJ2V0UD
Figure 18-13 shows the common signal waveforms, and Figure 18-14 shows the voltages and phases of the
common and segment signals.
Figure 18-13. Common Signal Waveforms
(a) Static display mode
COMn
(Static display)
T
F
= T
V
LC0
LV
SS
V
LCD
T: One LCD clock period TF: Frame frequency
(b) 1/2 bias method
COMn
(Two-time slot mode)
TF = 2 × T
VLC0
LVSS
VLCDVLC2
COMn
(Three-time slot mode)
TF = 3 × T
VLC0
LVSS
VLCDVLC2
T: One LCD clock period TF: Frame frequency
(c) 1/3 bias method
COMn
(Three-time slot mode)
T
F
= 3 × T
V
LC0
LV
SS
V
LCD
V
LC1
V
LC2
T
F
= 4 × T
COMn
(Four-time slot mode)
V
LC0
V
LCD
V
LC1
V
LC2
LV
SS
T: One LCD clock period TF: Frame frequency
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 491
Figure 18-14. Voltages and Phases of Common and Segment Signals
(a) Static display mode
Select Deselect
Common signal
Segment signal
VLC0
LVSS
VLCD
VLC0
LVSS
VLCD
TT
T: One LCD clock period
(b) 1/2 bias method
Select Deselect
Common signal
Segment signal
VLC0
LVSS
VLCD
VLC0
LVSS
VLCD
TT
VLC2
VLC2
T: One LCD clock period
(c) 1/3 bias method
Select Deselect
Common signal
Segment signal
VLC0
LVSS
VLCD
VLC0
LVSS
VLCD
TT
VLC2
VLC2
VLC1
VLC1
T: One LCD clock period
CHAPTER 18 LCD CONTROLLER/DRIVER
492 User’s Manual U17473EJ2V0UD
18.8 Display Modes
18.8.1 Static display example
Figure 18-16 shows how the five-digit LCD panel having the display pattern shown in Figure 18-15 is connected to
the segment signals (S0 to S39) and the common signal (COM0) of the 78K0/LG2 chip. This example displays data
"12.345" in the LCD panel. The contents of the display data memory (addresses 00H to 27H of LCDSEG) correspond
to this display.
The following description focuses on numeral "2." ( ) displayed in the fourth digit. To display "2." in the LCD
panel, it is necessary to apply the select or deselect voltage to the S24 to S31 pins according to Table 18-6 at the
timing of the common signal COM0; see Figure 18-15 for the relationship between the segment signals and LCD
segments.
Table 18-6. Select and Deselect Voltages (COM0)
Segment S24 S25 S26 S27 S28 S29 S30 S31
Common
COM0 Select Deselect Select Select Deselect Select Select Select
According to Table 18-6, it is determined that the bit-0 pattern of the display data memory locations (18H to 1FH of
LCDSEG) must be 10110111.
Figure 18-17 shows the LCD drive waveforms of S27 and S28, and COM0. When the select voltage is applied to
S27 at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding
LCD segment.
COM1 to COM3 are supplied with the same waveform as for COM0. So, COM0 to COM3 may be connected
together to increase the driving capacity.
Figure 18-15. Static LCD Display Pattern and Electrode Connections
S8n+3
S8n+2
S8n+5
S8n+1
S8n
S8n+4
S8n+6
S8n+7
COM0
Remark n = 0 to 4
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 493
Figure 18-16. Example of Connecting Static LCD Panel
0000011011101101101011100011011010111010
BIT 3
BIT 2
BIT 1
BIT 0
TIMING STROBE
DATA MEMORY ADDRESS
LCD PANEL
LCDSEG's 00H
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
LCDSEG's 10H
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
LCDSEG's 20H
1
2
3
4
5
6
7
S 0
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
COM 3
COM 2
COM 1
COM 0
S 24
S 25
S 26
S 27
S 28
S 29
S 30
S 31
S 32
S 33
S 34
S 35
S 36
S 37
S 38
S 39
Can be connected
together
×××××××××××××××××××××××××××
××××××××××××××××××××××××××××××××××××××××
×××××××××××××××××××××××××××
×××××××××××××
×××××××××××××
CHAPTER 18 LCD CONTROLLER/DRIVER
494 User’s Manual U17473EJ2V0UD
Figure 18-17. Static LCD Drive Waveform Examples
T
F
V
LC0
LV
SS
COM0
V
LC0
LV
SS
S27
V
LC0
LV
SS
S28
+V
LCD
0COM0-S28
-
V
LCD
+V
LCD
0COM0-S27
-
V
LCD
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 495
18.8.2 Two-time-slice display example
Figure 18-19 shows how the 10-digit LCD panel having the display pattern shown in Figure 18-18 is connected to
the segment signals (S0 to S39) and the common signals (COM0 and COM1) of the 78K0/LG2 chip. This example
displays data "123456.7890" in the LCD panel. The contents of the display data memory (addresses 00H to 27H of
LCDSEG) correspond to this display.
The following description focuses on numeral "3" ( ) displayed in the eighth digit. To display "3" in the LCD panel,
it is necessary to apply the select or deselect voltage to the S28 to S31 pins according to Table 18-7 at the timing of
the common signals COM0 and COM1; see Figure 18-18 for the relationship between the segment signals and LCD
segments.
Table 18-7. Select and Deselect Voltages (COM0 and COM1)
Segment S28 S29 S30 S31
Common
COM0 Select Select Deselect Deselect
COM1 Deselect Select Select Select
According to Table 18-7, it is determined that the display data memory location (1FH of LCDSEG) that
corresponds to S31 must contain xx10.
Figure 18-20 shows examples of LCD drive waveforms between the S31 signal and each common signal. When
the select voltage is applied to S31 at the timing of COM1, an alternate rectangle waveform, +VLCD/−VLCD, is generated
to turn on the corresponding LCD segment.
Figure 18-18. Two-Time-Slice LCD Display Pattern and Electrode Connections
;;
;;;
;;
;;
;;;
;
;;
;;
;;
;;
S
4n+2
S
4n+3
S
4n+1
S
4n
COM0
COM1
Remark n = 0 to 9
CHAPTER 18 LCD CONTROLLER/DRIVER
496 User’s Manual U17473EJ2V0UD
Figure 18-19. Example of Connecting Two-Time-Slice LCD Panel
0011101000110111010111010111111101111111
0000111011100010111011110100111001101100
BIT 3
BIT 2
BIT 1
BIT 0
TIMING STROBE
DATA MEMORY ADDRESS
LCD PANEL
LCDSEG's 00H
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
LCDSEG's
10H
1
2
3
4
5
6
7
8
9
A
B
S 0
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
S 9
S 10
S 11
S 12
S 13
S 14
S 15
S 16
S 17
S 18
S 19
S 20
S 21
S 22
S 23
S 24
S 25
S 26
S 27
COM 3
COM 2
COM 1
COM 0
OPEN
OPEN
C
D
E
F
LCDSEG's
20H
1
2
3
4
5
6
7
S 28
S 29
S 30
S 31
S 32
S 33
S 34
S 35
S 36
S 37
S 38
S 39
×××××××××××××××××××××××××××
×××××××××××××
×××××××××××××××××××××××××××
×××××××××××××
×: Can always be used to store any data because the two-time-slice mode is being used.
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 497
Figure 18-20. Two-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
T
F
V
LC0
LV
SS
COM0
V
LC0
LV
SS
V
LC0
LV
SS
S31
+V
LCD
0COM1-S31
-V
LCD
+V
LCD
0COM0-S31
-V
LCD
V
LC1,2
V
LC1,2
V
LC1,2
COM1
+1/2V
LCD
+1/2V
LCD
-1/2V
LCD
-1/2V
LCD
CHAPTER 18 LCD CONTROLLER/DRIVER
498 User’s Manual U17473EJ2V0UD
18.8.3 Three-time-slice display example
Figure 18-22 shows how the 13-digit LCD panel having the display pattern shown in Figure 18-21 is connected to
the segment signals (S0 to S38) and the common signals (COM0 to COM2) of the 78K0/LG2 chip. This example
displays data "123456.7890123" in the LCD panel. The contents of the display data memory (addresses 00H to 26H
of LCDSEG) correspond to this display.
The following description focuses on numeral "6." ( ) displayed in the eighth digit. To display "6." in the LCD
panel, it is necessary to apply the select or deselect voltage to the S21 to S23 pins according to Table 18-8 at the
timing of the common signals COM0 to COM2; see Figure 18-21 for the relationship between the segment signals and
LCD segments.
Table 18-8. Select and Deselect Voltages (COM0 to COM2)
Segment S21 S22 S23
Common
COM0 Deselect Select Select
COM1 Select Select Select
COM2 Select Select
−
According to Table 18-8, it is determined that the display data memory location (15H of LCDSEG) that
corresponds to S21 must contain x110.
Figures 18-23 and 18-24 show examples of LCD drive waveforms between the S21 signal and each common
signal in the 1/2 and 1/3 bias methods, respectively. When the select voltage is applied to S21 at the timing of COM1
or COM2, an alternate rectangle waveform, +VLCD/−VLCD, is generated to turn on the corresponding LCD segment.
Figure 18-21. Three-Time-Slice LCD Display Pattern and Electrode Connections
;;
;;
;;
;;
;
;
;;;
;;;
;;
;;
;;
;;
;;
;;
;;
S
3n+2
S
3n
COM0
COM2
S
3n+1
COM1
Remark n = 0 to 12
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 499
Figure 18-22. Example of Connecting Three-Time-Slice LCD Panel
TIMING STROBE
COM3
COM2
COM1
COM0
BIT0
BIT1
BIT2
BIT3
S0
S1
S2
S3
1
0
LCDSEG
's
00H
1
1
1
0
2
1
0
3S4
S5
S6
S7
1
1
4
0
5
1
0
6
0
0
7S8
S9
S10
S11
0
8
1
0
9
1
1
A
1
BS12
S13
S14
S15
1
0
C
1
0
D
1
E
1
0
FS16
S17
S18
S19
1
1
LCDSEG
's
10H
1
1
1
0
2
1
0
3S20
S21
S22
S23
1
4
0
1
5
1
1
6
1
7S24
S25
S26
S27
0
0
8
1
1
9
1
A
1
0
BS28
S29
S30
S31
0
0
C
1
D
1
0
E
1
1
FS32
S33
S34
S35
0
LCDSEG
's
20H
1
0
1
1
1
2
0
3S36
S37
S38
1
0
4
0
0
5
0
6
DATA MEMORY ADDRESS
LCD PANEL
OPEN
110011100101110111100111110110110011100
×××××××××××××××××××××××××××××××××××××××
×'
×'
×'
×'×'×'
×'×'
×'×'
×'
×'×'
×’: Can be used to store any data because there is no corresponding segment in the LCD panel.
×: Can always be used to store any data because the three-time-slice mode is being used.
CHAPTER 18 LCD CONTROLLER/DRIVER
500 User’s Manual U17473EJ2V0UD
Figure 18-23. Three-Time-Slice LCD Drive Waveform Examples (1/2 Bias Method)
T
F
V
LC0
LV
SS
COM0
V
LC0
LV
SS
V
LC0
LV
SS
COM2
+V
LCD
0COM1-S21
-
V
LCD
+V
LCD
0COM0-S21
-
V
LCD
V
LC1,2
V
LC1,2
V
LC1,2
COM1
+1/2V
LCD
+1/2V
LCD
-
1/2V
LCD
-
1/2V
LCD
V
LC0
LV
SS
S21 V
LC1,2
+V
LCD
0COM2-S21
-
V
LCD
+1/2V
LCD
-
1/2V
LCD
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 501
Figure 18-24. Three-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
V
LC0
V
LC2
COM0
+V
LCD
0
COM0-S21
-V
LCD
V
LC1
+1/3V
LCD
-1/3V
LCD
LV
SS
V
LC0
V
LC2
COM1 V
LC1
LV
SS
V
LC0
V
LC2
COM2 V
LC1
LV
SS
V
LC0
V
LC2
S21 V
LC1
LV
SS
+V
LCD
0
COM1-S21
-V
LCD
+1/3V
LCD
-1/3V
LCD
+V
LCD
0
COM2-S21
-V
LCD
+1/3V
LCD
-1/3V
LCD
T
F
CHAPTER 18 LCD CONTROLLER/DRIVER
502 User’s Manual U17473EJ2V0UD
18.8.4 Four-time-slice display example
Figure 18-26 shows how the 20-digit LCD panel having the display pattern shown in Figure 18-25 is connected to
the segment signals (S0 to S39) and the common signals (COM0 to COM3) of the 78K0/LG2 chip. This example
displays data "123456.78901234567890" in the LCD panel. The contents of the display data memory (addresses 00H
to 27H of LCDSEG) correspond to this display.
The following description focuses on numeral "6." ( ) displayed in the 15th digit. To display "6." in the LCD panel,
it is necessary to apply the select or deselect voltage to the S28 and S29 pins according to Table 18-9 at the timing of
the common signals COM0 to COM3; see Figure 18-25 for the relationship between the segment signals and LCD
segments.
Table 18-9. Select and Deselect Voltages (COM0 to COM3)
Segment S28 S29
Common
COM0 Select Select
COM1 Deselect Select
COM2 Select Select
COM3 Select Select
According to Table 18-9, it is determined that the display data memory location (1CH of LCDSEG) that
corresponds to S28 must contain 1101.
Figure 18-27 shows examples of LCD drive waveforms between the S28 signal and each common signal. When
the select voltage is applied to S28 at the timing of COM0, an alternate rectangle waveform, +VLCD/−VLCD, is generated
to turn on the corresponding LCD segment.
Figure 18-25. Four-Time-Slice LCD Display Pattern and Electrode Connections
Remark n = 0 to 19
;;
;;
;;
;;
;
;
;;
;;
COM0
S
2n
COM1
S
2n+1
COM2
COM3
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 503
Figure 18-26. Example of Connecting Four-Time-Slice LCD Panel
TIMING STROBE
COM3
COM2
COM1
COM0
BIT0
BIT1
BIT2
BIT3
S0
S1
S2
S3
1
1
0
LCDSEG's 00H
1
1
1
1
1
1
0
2
1
0
0
3S4
S5
S6
S7
1
1
0
4
1
1
1
5
1
1
0
6
1
0
0
7S8
S9
S10
S11
1
1
0
8
1
1
1
9
1
1
0
A
1
0
1
BS12
S13
S14
S15
0
1
0
C
1
0
0
D
1
1
0
E
0
0
1
FS16
S17
S18
S19
1
0
0
LCDSEG's 10H
0
1
1
1
0
1
0
2
0
0
0
3S20
S21
S22
S23
1
1
0
4
1
1
1
5
1
1
0
6
1
0
0
7S24
S25
S26
S27
1
1
0
8
1
1
1
9
1
1
0
A
1
0
0
BS28
S29
S30
S31
1
1
1
C
1
1
1
D
1
1
0
E
1
0
1
FS32
S33
S34
S35
0
1
0
LCDSEG's 20H
1
0
0
1
1
1
0
2
0
0
1
3S36
S37
S38
S39
1
0
0
4
0
1
1
5
0
1
0
6
0
0
0
7
DATA MEMORY ADDRESS
LCD PANEL
1011111001011111111010111110010111111110
CHAPTER 18 LCD CONTROLLER/DRIVER
504 User’s Manual U17473EJ2V0UD
Figure 18-27. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method)
V
LC0
V
LC2
COM0
+V
LCD
0
COM0-S28
-V
LCD
V
LC1
+1/3V
LCD
-1/3V
LCD
LV
SS
V
LC0
V
LC2
COM1 V
LC1
LV
SS
V
LC0
V
LC2
COM2 V
LC1
LV
SS
V
LC0
V
LC2
COM3 V
LC1
LV
SS
+V
LCD
0
COM1-S28
-V
LCD
+1/3V
LCD
-1/3V
LCD
V
LC0
V
LC2
S28 V
LC1
LV
SS
T
F
Remark The waveforms for COM2 to S28 and COM3 to S28 are omitted.
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 505
18.9 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2
With the 78K0/LG2, a LCD drive power supply can be generated using either of three types of methods: internal
resistance division method, external resistance division method, or internal voltage boosting method.
18.9.1 Internal resistance division method
The 78K0/LG2 incorporates voltage divider resistors for generating LCD drive power supplies. Using internal
voltage divider resistors, a LCD drive power supply that meet each bias method listed in Table 18-10 can be
generated, without using external voltage divider resistors.
Table 18-10. LCD Drive Voltages (with On-Chip Voltage Divider Resistors)
Bias Method No Bias (Static) 1/2 Bias Method 1/3 Bias Method
LCD Drive Voltage Pin
VLC0 VLCD VLCD VLCD
VLC1 VLCD VLCDNote VLCD
VLC2 VLCD VLCD
Note For the 1/2 bias method, it is necessary to connect the VLC1 and VLC2 pins externally.
Figure 18-28 shows examples of generating LCD drive voltages internally according to Table 18-10.
2
3
2
3
1
2
1
3
1
3
CHAPTER 18 LCD CONTROLLER/DRIVER
506 User’s Manual U17473EJ2V0UD
Figure 18-28. Examples of LCD Drive Power Connections (Internal Resistance Division Method)
(a) 1/3 bias method and static display mode
V
LC0
V
LCD
R
R
R
V
LC1
V
LC2
LV
SS
(b) 1/2 bias method
V
LC0
V
LCD
R
R
R
V
LC1
V
LC2
LV
SS
CHAPTER 18 LCD CONTROLLER/DRIVER
User’s Manual U17473EJ2V0UD 507
18.9.2 External resistance division method
The 78K0/LG2 can also use external voltage divider resistors for generating LCD drive power supplies, without
using internal resistors. Figure 18-29 shows examples of LCD drive voltage connection, corresponding to each bias
method.
Figure 18-29. Examples of LCD Drive Power Connections (External Resistance Division Method)
(a) Static display mode
(VLCD = VLC0 = VLC1 = VLC2)
(b) Static display mode
(VLC1 = VLC2 = LVSS = GND)
V
LC0
V
LCD
V
LC1
V
LC2
LV
SS
V
LC0
V
LCD
V
LC1
V
LC2
LV
SS
(c) 1/2 bias method (d) 1/3 bias method
V
LC0
V
LCD
R
V
LC1
V
LC2
LV
SS
R
V
LC0
V
LCD
R
V
LC1
V
LC2
LV
SS
R
R
<R>
CHAPTER 18 LCD CONTROLLER/DRIVER
508 User’s Manual U17473EJ2V0UD
18.9.3 Internal voltage boosting method
The 78K0/LG2 contains a booster circuit (×3 only) to generate a supply voltage to drive the LCD. The internal LCD
reference voltage is output from the VLC2 pin. A voltage two times higher than that on VLC2 is output from the VLC1 pin
and a voltage three times higher than that on VLC2 is output from the VLC0 pin.
The LCD reference voltage (VLC2) can be specified by setting LCD boost control register 0 (VLCG0).
The 78K0/LG2 requires an external capacitor (0.47 to 1
μ
F: recommended) when the internal voltage boosting
method is selected.
Table 18-11. Output Voltages of VLC0 to VLC2 Pins
VLCG0 GAIN = 0 GAIN = 1
LCD drive power supply pin
VLC0 4.5 V 3.0 V
VLC1 3.0 V 2.0 V
VLC2 (LCD reference voltage) 1.5 V 1.0 V
Cautions 1. When using the LCD function, do not leave the VLC0, VLC1, and VLC2 pins open. Refer to
Figure 18-30 for connection.
2. Since the LCD drive voltage is separate from the main power supply, a constant voltage
can be supplied regardless of VDD and LVDD fluctuation.
Figure 18-30. Example of Connecting Pins for LCD Driver
V
LC0
V
LC1
V
LC2
C2 C3 C4
CAPH
C1
External pin
C1 = C2 = C3 = C4 = 0.47 F
CAPL
μ
Remark Use a capacitor with as little leakage as possible.
In addition, make C1 a nonpolar capacitor.
<R>
User’s Manual U17473EJ2V0UD 509
CHAPTER 19 MULTIPLIER/DIVIDER
(
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
Only for the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D, the multiplier/divider is provided.
19.1 Functions of Multiplier/Divider
The multiplier/divider has the following functions.
• 16 bits × 16 bits = 32 bits (multiplication)
• 32 bits ÷ 16 bits = 32 bits, 16-bit remainder (division)
19.2 Configuration of Multiplier/Divider
The multiplier/divider includes the following hardware.
Table 19-1. Configuration of Multiplier/Divider
Item Configuration
Registers Remainder data register 0 (SDR0)
Multiplication/division data registers A0 (MDA0H, MDA0L)
Multiplication/division data registers B0 (MDB0)
Control register Multiplier/divider control register 0 (DMUC0)
Figure 19-1 shows the block diagram of the multiplier/divider.
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD
510
Figure 19-1. Block Diagram of Multiplier/Divider
Internal bus
CPU clock
Start
Clear
17-bit
adder
Controller
Multiplication/division data register B0
(MDB0 (MDB0H + MDB0L)
Remainder data register 0
(SDR0 (SDR0H + SDR0L)
6-bit
counter
DMUSEL0
Multiplier/divider control
register 0 (DMUC0)
Controller
Multiplication/division data register A0
(
MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL)
)
Controller
DMUE
MDA000 INTDMU
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 511
(1) Remainder data register 0 (SDR0)
SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the
remainder of an operation result in the division mode.
SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation sets SDR0 to 0000H.
Figure 19-2. Format of Remainder Data Register 0 (SDR0)
Address: FF60H, FF61H After reset: 0000H R
Symbol FF61H (SDR0H) FF60H (SDR0L)
SDR0 SDR
015
SDR
014
SDR
013
SDR
012
SDR
011
SDR
010
SDR
009
SDR
008
SDR
007
SDR
006
SDR
005
SDR
004
SDR
003
SDR
002
SDR
001
SDR
000
Cautions 1. The value read from SDR0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
2. SDR0 is reset when the operation is started (when DMUE is set to 1).
(2) Multiplication/division data register A0 (MDA0H, MDA0L)
MDA0 is a 32-bit register that sets a 16-bit multiplier A in the multiplication mode and a 32-bit dividend in the
division mode, and stores the 32-bit result of the operation (higher 16 bits: MDA0H, lower 16 bits: MDA0L).
Figure 19-3. Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L)
Address: FF62H, FF63H, FF64H, FF65H After reset: 0000H, 0000H R/W
Symbol FF65H (MDA0HH) FF64H (MDA0HL)
MDA0H MDA
031
MDA
030
MDA
029
MDA
028
MDA
027
MDA
026
MDA
025
MDA
024
MDA
023
MDA
022
MDA
021
MDA
020
MDA
019
MDA
018
MDA
017
MDA
016
Symbol FF63H (MDA0LH) FF62H (MDA0LL)
MDA0L MDA
015
MDA
014
MDA
013
MDA
012
MDA
011
MDA
010
MDA
009
MDA
008
MDA
007
MDA
006
MDA
005
MDA
004
MDA
003
MDA
002
MDA
001
MDA
000
Cautions 1. MDA0H is cleared to 0 when an operation is started in the multiplication mode (when
multiplier/divider control register 0 (DMUC0) is set to 81H).
2. Do not change the value of MDA0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is
executed, but the result is undefined.
3. The value read from MDA0 during operation processing (while DMUE is 1) is not guaranteed.
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD
512
The functions of MDA0 when an operation is executed are shown in the table below.
Table 19-2. Functions of MDA0 During Operation Execution
DMUSEL0 Operation Mode Setting Operation Result
0 Division mode Dividend Division result (quotient)
1 Multiplication mode Higher 16 bits: 0, Lower 16
bits: Multiplier A
Multiplication result
(product)
The register configuration differs between when multiplication is executed and when division is executed, as
follows.
• Register configuration during multiplication
<Multiplier A> <Multiplier B> <Product>
MDA0 (bits 15 to 0) × MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0)
• Register configuration during division
<Dividend> <Divisor> <Quotient> <Remainder>
MDA0 (bits 31 to 0) ÷ MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) … SDR0 (bits 15 to 0)
MDA0 fetches the calculation result as soon as the clock is input, when bit 7 (DMUE) of multiplier/divider
control register 0 (DMUC0) is set to 1.
MDA0H and MDA0L can be set by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation clears MDA0H and MDA0L to 0000H.
(3) Multiplication/division data register B0 (MDB0)
MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the
division mode.
MDB0 can be set by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation sets MDB0 to 0000H.
Figure 19-4. Format of Multiplication/Division Data Register B0 (MDB0)
Address: FF66H, FF67H After reset: 0000H R/W
Symbol FF67H (MDB0H) FF66H (MDB0L)
MDB0 MDB
015
MDB
014
MDB
013
MDB
012
MDB
011
MDB
010
MDB
009
MDB
008
MDB
007
MDB
006
MDB
005
MDB
004
MDB
003
MDB
002
MDB
001
MDB
000
Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is
executed, but the result is undefined.
2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are
stored in MDA0 and SDR0.
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 513
19.3 Register Controlling Multiplier/Divider
The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0).
(1) Multiplier/divider control register 0 (DMUC0)
DMUC0 is an 8-bit register that controls the operation of the multiplier/divider.
DMUC0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets DMUC0 to 00H.
Figure 19-5. Format of Multiplier/Divider Control Register 0 (DMUC0)
DMUE
DMUC0 0 0 0 0 0 0 DMUSEL0
Stops operation
Starts operation
DMUE
Note
0
1
Operation start/stop
Division mode
Multiplication mode
DMUSEL0
0
1
Operation mode (multiplication/division) selection
Address: FF68H After reset: 00H R/W
Symbol 4 3 2 1 06<7> 5
Note When DMUE is set to 1, the operation is started. DMUE is automatically cleared to 0 after the operation is
complete.
Cautions 1. If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result
is not guaranteed. If the operation is completed while the clearing instruction is being
executed, the operation result is guaranteed, provided that the interrupt flag is set.
2. Do not change the value of DMUSEL0 during operation processing (while DMUE is 1). If it is
changed, undefined operation results are stored in multiplication/division data register A0
(MDA0) and remainder data register 0 (SDR0).
3. If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation
processing is stopped. To execute the operation again, set multiplication/division data
register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider
control register 0 (DMUC0), and start the operation (by setting DMUE to 1).
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD
514
19.4 Operations of Multiplier/Divider
19.4.1 Multiplication operation
• Initial setting
1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register
B0 (MDB0).
2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start.
• During operation
3. The operation will be completed when 16 internal clocks have been issued after the start of the operation
(intermediate data is stored in the MDA0L and MDA0H registers during operation, and therefore the read
values of these registers are not guaranteed).
• End of operation
4. The operation result data is stored in the MDA0L and MDA0H registers.
5. DMUE is cleared to 0 (end of operation).
6. After the operation, an interrupt request signal (INTDMU) is generated.
• Next operation
7. To execute multiplication next, start from the initial setting in 19.4.1 Multiplication operation.
8. To execute division next, start from the initial setting in 19.4.2 Division operation.
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 515
Figure 19-6. Timing Chart of Multiplication Operation (00DAH × 0093H)
Operation clock
MDA0
SDR0
MDB0
123456789ABCD EF10
00
0000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000
0000
006D
0000
00DA
XXXX
00DA
XXXX
XXXX
XXXX
0049
8036 0024
C01B 005B
E00D 0077
7006 003B
B803 0067
5C01 007D
2E00 003E
9700 001F
4B80 000F
A5C0 0007
D2E0 0003
E970 0001
F4B8 0000
FA5C
0000
7D2E
0093
XXXX
Internal clock
DMUE
DMUSEL0
Counter
INTDMU
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD
516
19.4.2 Division operation
• Initial setting
1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division
data register B0 (MDB0).
2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively.
Operation will start.
• During operation
3. The operation will be completed when 32 internal clocks have been issued after the start of the operation
(intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 (SDR0) during
operation, and therefore the read values of these registers are not guaranteed).
• End of operation
4. The result data is stored in the MDA0L, MDA0H, and SDR0 registers.
5. DMUE is cleared to 0 (end of operation).
6. After the operation, an interrupt request signal (INTDMU) is generated.
• Next operation
7. To execute multiplication next, start from the initial setting in 19.4.1 Multiplication operation.
8. To execute division next, start from the initial setting in 19.4.2 Division operation.
CHAPTER 19 MULTIPLIER/DIVIDER (
μ
PD78F0394, 78F0395, 78F0396, 78F0397, AND 78F0397D ONLY)
User’s Manual U17473EJ2V0UD 517
Figure 19-7. Timing Chart of Division Operation (DCBA2586H ÷ 0018H)
Operation clock
MDA0
SDR0
MDB0
12345678 19 1A 1B 1C 1D 1E 1F 200 0
0000
0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B
0016
B974
4B0C
DCBA
2586
XXXX
XXXX
XXXX
72E8
9618
E5D1
2C30
CBA2
5860
9744
B0C1
2E89
6182
5D12
C304
BA25
8609
0C12
64D8
1824
C9B0
3049
9361
6093
26C3
C126
4D87
824C
9B0E
0499
361D
0932
6C3A
0018
XXXX
Internal clock
DMUE
DMUSEL0
Counter
INTDMU
“0”
User’s Manual U17473EJ2V0UD
518
CHAPTER 20 INTERRUPT FUNCTIONS
20.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group
and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H).
Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If
two or more interrupt requests, each having the same priority, are simultaneously generated, then they are
processed according to the priority of vectored interrupt servicing. For the priority order, see Table 20-1.
A standby release signal is generated and STOP and HALT modes are released.
External interrupt requests and internal interrupt requests are provided as maskable interrupts.
•
μ
PD78F0393
External: 7, internal: 16
•
μ
PD78F0394, 78F0395, 78F0396, 78F0397, 78F0397D
External: 7, internal: 19
(2) Software interrupt
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts
are disabled. The software interrupt does not undergo interrupt priority control.
20.2 Interrupt Sources and Configuration
The
μ
PD78F0393 has a total of 24 interrupt sources, and the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and
78F0397D have a total of 27 interrupt sources, including maskable interrupts and software interrupts. In addition, they
also have up to four reset sources (see Table 20-1).
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 519
Table 20-1. Interrupt Source List (1/2)
Interrupt Source
Interrupt
Type
Default
PriorityNote 1 Name Trigger
Internal/
External
Vector
Table
Address
Basic
Configuration
TypeNote 2
0 INTLVI Low-voltage detectionNote 3 Internal 0004H (A)
1 INTP0 0006H
2 INTP1 0008H
3 INTP2 000AH
4 INTP3 000CH
5 INTP4 000EH
6 INTP5
Pin input edge detection External
0010H
(B)
7 INTSRE6 UART6 reception error generation 0012H
8 INTSR6 End of UART6 reception 0014H
9 INTST6 End of UART6 transmission 0016H
10 INTCSI10/
INTST0
End of CSI10 communication/end of UART0
transmission
0018H
11 INTTMH1
Match between TMH1 and CMP01
(when compare register is specified)
001AH
12 INTTMH0
Match between TMH0 and CMP00
(when compare register is specified)
001CH
13 INTTM50
Match between TM50 and CR50
(when compare register is specified)
001EH
14 INTTM000
Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
0020H
15 INTTM010
Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection
(when capture register is specified)
0022H
16 INTAD End of A/D conversion 0024H
17 INTSR0 End of UART0 reception or reception error
generation
0026H
18 INTWTI Watch timer reference time interval signal 0028H
19 INTTM51
Match between TM51 and CR51
(when compare register is specified)
Internal
002AH
(A)
20 INTKR Key interrupt detection External 002CH (C)
Maskable
21 INTWT Watch timer overflow Internal 002EH (A)
Notes 1. The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 25 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1.
3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
520
Table 20-1. Interrupt Source List (2/2)
Interrupt Source
Interrupt
Type
Default
PriorityNote 1 Name Trigger
Internal/
External
Vector
Table
Address
Basic
Configuration
TypeNote 2
22 INTIIC0/
INTDMUNote 3
End of IIC0 communication/end of
multiply/divide operation
0034H
23 INTCSI11Note 3 End of CSI11 communication 0036H
24 INTTM001Note 3 Match between TM01 and CR001
(when compare register is specified),
TI011 pin valid edge detection
(when capture register is specified)
0038H
Maskable
25 INTTM011Note 3 Match between TM01 and CR011
(when compare register is specified),
TI001 pin valid edge detection
(when capture register is specified)
Internal
003AH
(A)
Software − BRK BRK instruction execution − 003EH (D)
RESET Reset input
POC Power-on clear
LVI Low-voltage detectionNote 4
Reset −
WDT WDT overflow
− 0000H −
Notes 1. The default priority is the priority applicable when two or more maskable interrupts are generated
simultaneously. 0 is the highest priority, and 25 is the lowest.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 20-1.
3. The interrupt sources INTDMU, INTCSI11, INTTM001, and INTTM011 are available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D.
4. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is set to 1.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 521
Figure 20-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal maskable interrupt
Internal bus
Interrupt
request IF
MK IE PR ISP
Priority controller Vector table
address generator
Standby release signal
(B) External maskable interrupt (INTP0 to INTP5)
Internal bus
Interrupt
request IF
MK IE PR ISP
Priority controller Vector table
address generator
Standby release signal
External interrupt edge
enable register
(EGP, EGN)
Edge
detector
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specification flag
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
522
Figure 20-1. Basic Configuration of Interrupt Function (2/2)
(C) External maskable interrupt (INTKR)
IF
MK IE PR ISP
Internal bus
Interrupt
request Priority controller Vector table
address generator
Standby release signal
Key
interrupt
detector
1 when KRMn = 1 (n = 0 to 7)
(D) Software interrupt
Internal bus
Interrupt
request Priority controller Vector table
address generator
IF: Interrupt request flag
IE: Interrupt enable flag
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specification flag
KRM: Key return mode register
20.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functions.
• Interrupt request flag register (IF0L, IF0H, IF1L, IF1H)
• Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H)
• Priority specification flag register (PR0L, PR0H, PR1L, PR1H)
• External interrupt rising edge enable register (EGP)
• External interrupt falling edge enable register (EGN)
• Program status word (PSW)
Table 20-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding
to interrupt request sources.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 523
Table 20-2. Flags Corresponding to Interrupt Request Sources
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
Interrupt
Source Register Register Register
INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L
INTP0 PIF0 PMK0 PPR0
INTP1 PIF1 PMK1 PPR1
INTP2 PIF2 PMK2 PPR2
INTP3 PIF3 PMK3 PPR3
INTP4 PIF4 PMK4 PPR4
INTP5 PIF5 PMK5 PPR5
INTSRE6 SREIF6 SREMK6 SREPR6
INTSR6 SRIF6 IF0H SRMK6 MK0H SRPR6 PR0H
INTST6 STIF6 STMK6 STPR6
INTCSI10 CSIIF10 CSIMK10 CSIPR10
INTST0 STIF0
DUALIF0
Note 1 STMK0
DUALMK0
Note 2 STPR0
DUALPR0
Note 2
INTTMH1 TMIFH1 TMMKH1 TMPRH1
INTTMH0 TMIFH0 TMMKH0 TMPRH0
INTTM50 TMIF50 TMMK50 TMPR50
INTTM000 TMIF000 TMMK000 TMPR000
INTTM010 TMIF010 TMMK010 TMPR010
INTAD ADIF IF1L ADMK MK1L ADPR PR1L
INTSR0 SRIF0 SRMK0 SRPR0
INTWTI WTIIF WTIMK WTIPR
INTTM51 TMIF51 TMMK51 TMPR51
INTKR KRIF KRMK KRPR
INTWT WTIF WTMK WTPR
INTIIC0 Note 4 IICIF0 IICMK0 IICPR0
INTDMUNotes 3, 4 DMUIFNote 3
IF1H
DMUMKNote 3
MK1H
DMUPRNote 3
PR1H
INTCSI11Note 3 CSIIF11Note 3 CSIMK11Note 3 CSIPR11Note 3
INTTM001Note 3 TMIF001Note 3 TMMK001Note 3 TMPR001Note 3
INTTM011Note 3 TMIF011Note 3 TMMK011Note 3 TMPR011Note 3
Notes 1. If either interrupt source INTCSI10 or INTST0 is generated, these flags are set (1).
2. Both interrupt sources INTCSI10 and INTST0 are supported.
3.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
4. Do not use serial interface IIC0 and multiplier/divider simultaneously, because the flags corresponding to
the interrupt request sources of serial interface IIC0 and multiplier/divider support both of these interrupt
request sources. If software which operates serial interface IIC0 is developed by CC78K0 which is C
compiler, do not select the check box of “Using Multiplier/Divider” on GUI of PM+.
<R>
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
524
(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and
IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation
instruction.
Reset signal generation sets these registers to 00H.
Figure 20-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H)
Address: FFE0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0L SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF
Address: FFE1H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1
DUALIF0
CSIIF10
STIF0
STIF6 SRIF6
Address: FFE2H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF1L 0 0 WTIF KRIF TMIF51 WTIIF SRIF0 ADIF
Address: FFE3H After reset: 00H R/W
Symbol 7 6 5 4 <3> <2> <1> <0>
IF1H 0 0 0 0 TMIF011Note TMIF001Note CSIIF11Note IICIF0
DMUIF Note
XXIFX Interrupt request flag
0 No interrupt request signal is generated
1 Interrupt request is generated, interrupt request status
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Cautions 1. Be sure to clear bits 6 and 7 of IF1L to 0.
2. Be sure to clear bits 1 to 7 of IF1H to 0 for the
μ
PD78F0393. Be sure to clear bits 4 to 7 of
IF1H to 0 for the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D.
3. When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 525
Cautions 4. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction such
as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of another bit of the same interrupt request flag register
(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared to
0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory
manipulation instruction in C language.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
526
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and
MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit
memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 20-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H)
Address: FFE4H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0L SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK
Address: FFE5H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1
DUALMK0
CSIMK0
STMK0
STMK6 SRMK6
Address: FFE6H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK1L 1 1 WTMK KRMK TMMK51 WTIMK SRMK0 ADMK
Address: FFE7H After reset: FFH R/W
Symbol 7 6 5 4 <3> <2> <1> <0>
MK1H 1 1 1 1 TMMK011Note TMMK001Note CSIMK11Note IICMK0
DMUMKNote
XXMKX Interrupt servicing control
0 Interrupt servicing enabled
1 Interrupt servicing disabled
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Cautions 1. Be sure to set bits 6 and 7 of MK1L to 1.
2. Be sure to set bits 1 to 7 of MK1H to 1 for the
μ
PD78F0393. Be sure to set bits 4 to 7 of MK1H
to 1 for the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 527
(3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority order.
PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H,
and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory
manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 20-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H)
Address: FFE8H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR0L SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 LVIPR
Address: FFE9H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR0H TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1
DUALPR0
CSIPR10
STPR0
STPR6 SRPR6
Address: FFEAH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR1L 1 1 WTPR KRPR TMPR51 WTIPR SRPR0 ADPR
Address: FFEBH After reset: FFH R/W
Symbol 7 6 5 4 <3> <2> <1> <0>
PR1H 1 1 1 1 TMPR011Note TMPR001Note CSIPR11Note IICPR0
DMUPRNote
XXPRX Priority level selection
0 High priority level
1 Low priority level
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Cautions 1. Be sure to set bits 6 and 7 of PR1L to 1.
2. Be sure to set bits 1 to 7 of PR1H to 1 for the
μ
PD78F0393. Be sure to set bits 4 to 7 of PR1H
to 1 for the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
528
(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
These registers specify the valid edge for INTP0 to INTP5.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
Figure 20-5. Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN)
Address: FF48H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP 0 0 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0
Address: FF49H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN 0 0 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0
EGPn EGNn INTPn pin valid edge selection (n = 0 to 7)
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Table 20-3 shows the ports corresponding to EGPn and EGNn.
Table 20-3. Ports Corresponding to EGPn and EGNn
Detection Enable Register Edge Detection Port Interrupt Request Signal
EGP0 EGN0 P120 INTP0
EGP1 EGN1 P30 INTP1
EGP2 EGN2 P31 INTP2
EGP3 EGN3 P32 INTP3
EGP4 EGN4 P33 INTP4
EGP5 EGN5 P16 INTP5
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Remark n = 0 to 5
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 529
(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple
interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed,
the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt
request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are
transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction.
They are restored from the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 02H.
Figure 20-6. Format of Program Status Word
<7>
IE
<6>
Z
<5>
RBS1
<4>
AC
<3>
RBS0
2
0
<1>
ISP
0
CYPSW
After reset
02H
ISP
High-priority interrupt servicing (low-priority
interrupt disabled)
IE
0
1
Disabled
Priority of interrupt currently being serviced
Interrupt request acknowledgment enable/disable
Used when normal instruction is executed
Enabled
Interrupt request not acknowledged, or low-
priority interrupt servicing (all maskable
interrupts enabled)
0
1
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
530
20.4 Interrupt Servicing Operations
20.4.1 Maskable interrupt acknowledgement
A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not
acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0).
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed
in Table 20-4 below.
For the interrupt request acknowledgement timing, see Figures 20-8 and 20-9.
Table 20-4. Time from Generation of Maskable Interrupt Until Servicing
Minimum Time Maximum TimeNote
When ××PR = 0 7 clocks 32 clocks
When ××PR = 1 8 clocks 33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 20-7 shows the interrupt request acknowledgement algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into
the PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 531
Figure 20-7. Interrupt Request Acknowledgement Processing Algorithm
Start
××IF = 1?
××MK = 0?
××PR = 0?
IE = 1?
ISP = 1?
Interrupt request held pending
Yes
Yes
No
No
Yes (interrupt request generation)
Yes
No (Low priority)
No
No
Yes
Yes
No
IE = 1?
No
Any high-priority
interrupt request among those
simultaneously generated
with ××PR = 0?
Yes (High priority)
No
Yes
Yes
No
Vectored interrupt servicing
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Vectored interrupt servicing
Any high-priority
interrupt request among
those simultaneously
generated?
Any high-priority
interrupt request among
those simultaneously generated
with ××PR = 0?
××IF: Interrupt request flag
××MK: Interrupt mask flag
××PR: Priority specification flag
IE: Flag that controls acknowledgement of maskable interrupt request (1 = Enable, 0 = Disable)
ISP: Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt
servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing)
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
532
Figure 20-8. Interrupt Request Acknowledgement Timing (Minimum Time)
8 clocks
7 clocks
Instruction Instruction
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
CPU processing
××IF
(××PR = 1)
××IF
(××PR = 0)
6 clocks
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
Figure 20-9. Interrupt Request Acknowledgement Timing (Maximum Time)
33 clocks
32 clocks
Instruction Divide instruction
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
CPU processing
××IF
(××PR = 1)
××IF
(××PR = 0)
6 clocks25 clocks
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
20.4.2 Software interrupt request acknowledgement
A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be
disabled.
If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH,
003FH) are loaded into the PC and branched.
Restoring from a software interrupt is possible by using the RETB instruction.
Caution Do not use the RETI instruction for restoring from the software interrupt.
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 533
20.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected
(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0).
Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during
interrupt servicing to enable interrupt acknowledgement.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to
interrupt priority control. Two types of priority control are available: default priority control and programmable priority
control. Programmable priority control is used for multiple interrupt servicing.
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt
currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority
lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged
for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled
state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the
pending interrupt request is acknowledged following execution of at least one main processing instruction execution.
Table 20-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 20-10
shows multiple interrupt servicing examples.
Table 20-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Maskable Interrupt Request
PR = 0 PR = 1
Multiple Interrupt Request
Interrupt Being Serviced IE = 1 IE = 0 IE = 1 IE = 0
Software
Interrupt
Request
ISP = 0 { × × × {
Maskable interrupt
ISP = 1 { × { × {
Software interrupt { × { × {
Remarks 1. : Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. ISP and IE are flags contained in the PSW.
ISP = 0: An interrupt with higher priority is being serviced.
ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower
priority is being serviced.
IE = 0: Interrupt request acknowledgement is disabled.
IE = 1: Interrupt request acknowledgement is enabled.
4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H.
PR = 0: Higher priority level
PR = 1: Lower priority level
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
534
Figure 20-10. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing INTxx servicing INTyy servicing INTzz servicing
EI EI EI
RETI RETI
RETI
INTxx
(PR = 1)
INTyy
(PR = 0)
INTzz
(PR = 0)
IE = 0 IE = 0 IE = 0
IE = 1 IE = 1
IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple
interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be
issued to enable interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing INTxx servicing INTyy servicing
INTxx
(PR = 0)
INTyy
(PR = 1)
EI
RETI
IE = 0
IE = 0
EI
1 instruction execution
RETI
IE = 1
IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower
than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending,
and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
PR = 1: Lower priority level
IE = 0: Interrupt request acknowledgment disabled
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD 535
Figure 20-10. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing INTxx servicing INTyy servicing
EI
1 instruction execution
RETI
RETI
INTxx
(PR = 0)
INTyy
(PR = 0)
IE = 0
IE = 0
IE = 1
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt
request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request
is held pending, and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
IE = 0: Interrupt request acknowledgement disabled
CHAPTER 20 INTERRUPT FUNCTIONS
User’s Manual U17473EJ2V0UD
536
20.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued for them while another instruction is being
executed, request acknowledgement is held pending until the end of execution of the next instruction. These
instructions (interrupt request hold instructions) are listed below.
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW. bit, CY
• MOV1 CY, PSW. bit
• AND1 CY, PSW. bit
• OR1 CY, PSW. bit
• XOR1 CY, PSW. bit
• SET1 PSW. bit
• CLR1 PSW. bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW. bit, $addr16
• BF PSW. bit, $addr16
• BTCLR PSW. bit, $addr16
• EI
• DI
• Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, and
PR1H registers.
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However,
the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared.
Therefore, even if a maskable interrupt request is generated during execution of the BRK
instruction, the interrupt request is not acknowledged.
Figure 20-11 shows the timing at which interrupt requests are held pending.
Figure 20-11. Interrupt Request Hold
Instruction N Instruction M PSW and PC saved, jump
to interrupt servicing
Interrupt servicing
program
CPU processing
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
User’s Manual U17473EJ2V0UD 537
CHAPTER 21 KEY INTERRUPT FUNCTION
21.1 Functions of Key Interrupt
A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling
edge to the key interrupt input pins (KR0 to KR7).
Table 21-1. Assignment of Key Interrupt Detection Pins
Flag Description
KRM0 Controls KR0 signal in 1-bit units.
KRM1 Controls KR1 signal in 1-bit units.
KRM2 Controls KR2 signal in 1-bit units.
KRM3 Controls KR3 signal in 1-bit units.
KRM4 Controls KR4 signal in 1-bit units.
KRM5 Controls KR5 signal in 1-bit units.
KRM6 Controls KR6 signal in 1-bit units.
KRM7 Controls KR7 signal in 1-bit units.
21.2 Configuration of Key Interrupt
The key interrupt includes the following hardware.
Table 21-2. Configuration of Key Interrupt
Item Configuration
Control register Key return mode register (KRM)
Figure 21-1. Block Diagram of Key Interrupt
INTKR
Key return mode register (KRM)
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
KR7
KR6
KR5
KR4
KR3
KR2
KR1
KR0
CHAPTER 21 KEY INTERRUPT FUNCTION
User’s Manual U17473EJ2V0UD
538
21.3 Register Controlling Key Interrupt
(1) Key return mode register (KRM)
This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively.
KRM is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets KRM to 00H.
Figure 21-2. Format of Key Return Mode Register (KRM)
KRM7
Does not detect key interrupt signal
Detects key interrupt signal
KRMn
0
1
Key interrupt mode control
KRM KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
Address: FF6EH After reset: 00H R/W
Symbol 765432 0
Cautions 1. If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of the
corresponding pull-up resistor register 7 (PU7) to 1.
2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and
then change the KRM register. Clear the interrupt request flag and enable interrupts.
3. The bits not used in the key interrupt mode can be used as normal ports.
User’s Manual U17473EJ2V0UD 539
CHAPTER 22 STANDBY FUNCTION
22.1 Standby Function and Configuration
22.1.1 Standby function
The standby function is designed to reduce the operating current of the system. The following two modes are
available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the
high-speed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem
clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the
operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting
operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately
upon interrupt request generation.
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
subsystem clock oscillation cannot be stopped. The HALT mode can be used when the CPU
is operating on either the main system clock or the subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
3. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the STOP instruction.
22.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For the registers that start, stop, or select the clock, see CHAPTER 6 CLOCK GENERATOR.
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD
540
(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1
clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock,
the X1 clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of
MOC register) = 1 clear OSTC to 00H.
Figure 22-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16
MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status
fX = 10 MHz fX = 20 MHz
1 0 0 0 0 211/fX min. 204.8
μ
s min. 102.4
μ
s min.
1 1 0 0 0 213/fX min. 819.2
μ
s min. 409.6
μ
s min.
1 1 1 0 0 214/fX min. 1.64 ms min. 819.2
μ
s min.
1 1 1 1 0 215/fX min. 3.27 ms min. 1.64 ms min.
1 1 1 1 1 216/fX min. 6.55 ms min. 3.27 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
a
STOP mode release
X1 pin voltage
waveform
Remark f
X: X1 clock oscillation frequency
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD 541
(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can
be checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets OSTS to 05H.
Figure 22-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection
fX = 10 MHz fX = 20 MHz
0 0 1 211/fX 204.8
μ
s 102.4
μ
s
0 1 0 213/fX 819.2
μ
s 409.6
μ
s
0 1 1 214/fX 1.64 ms 819.2
μ
s
1 0 0 215/fX 3.27 ms 1.64 ms
1 0 1 216/fX 6.55 ms 3.27 ms
Other than above Setting prohibited
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
2. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
3. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. If the STOP mode is entered and then released
while the internal high-speed oscillation clock is being used as the CPU clock,
set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
4. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
a
STOP mode release
X1 pin voltage
waveform
Remark fX: X1 clock oscillation frequency
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD
542
22.2 Standby Function Operation
22.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem
clock.
The operating statuses in the HALT mode are shown below.
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD 543
Table 22-1. Operating Statuses in HALT Mode (1/2)
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock HALT Mode Setting
Item
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fRH)
When CPU Is Operating on
X1 Clock (fX)
When CPU Is Operating on
External Main System Clock
(fEXCLK)
System clock Clock supply to the CPU is stopped
fRH Operation continues (cannot
be stopped)
Status before HALT mode was set is retained
fX Status before HALT mode
was set is retained
Operation continues (cannot
be stopped)
Status before HALT mode
was set is retained
Main system clock
fEXCLK Operates or stops by external clock input Operation continues (cannot
be stopped)
fXT Status before HALT mode was set is retained
Subsystem clock
fEXCLKS Operates or stops by external clock input
fRL Status before HALT mode was set is retained
CPU Operation stopped
Flash memory Operation stopped
RAM Status before HALT mode was set is retained
Port (latch) Status before HALT mode was set is retained
00 16-bit timer/event
counter 01Note
50 8-bit timer/event
counter 51
H0 8-bit timer
H1
Watch timer
Operable
Watchdog timer Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Clock output
A/D converter
UART0
UART6
CSI10
CSI11Note
Serial interface
IIC0
LCD controller/driver
Multiplier/dividerNote
Power-on-clear function
Low-voltage detection function
External interrupt
Operable
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Remark f
RH: Internal high-speed oscillation clock
f
X: X1 clock
f
EXCLK: External main system clock
f
XT: XT1 clock
f
EXCLKS: External subsystem clock
f
RL: Internal low-speed oscillation clock
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD
544
Table 22-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock HALT Mode Setting
Item
When CPU Is Operating on XT1 Clock (fXT) When CPU Is Operating on External
Subsystem Clock (fEXCLKS)
System clock Clock supply to the CPU is stopped
fRH
fX
Status before HALT mode was set is retained
Main system clock
fEXCLK Operates or stops by external clock input
fXT Operation continues (cannot be stopped) Status before HALT mode was set is retained
Subsystem clock
fEXCLKS Operates or stops by external clock input Operation continues (cannot be stopped)
fRL Status before HALT mode was set is retained
CPU Operation stopped
Flash memory Operation stopped
RAM Status before HALT mode was set is retained
Port (latch) Status before HALT mode was set is retained
00Note1 16-bit timer/event
counter 01Note1. 2
50Note1 8-bit timer/event
counter 51Note1
H0 8-bit timer
H1
Watch timer
Operable
Watchdog timer Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Clock output Operable
A/D converter Operable. However, operation disabled when peripheral hardware clock (fPRS) is stopped.
UART0
UART6
CSI10Note1
CSI11Note1, 2
Serial interface
IIC0Note1
LCD controller/driver
Multiplier/dividerNote2
Power-on-clear function
Low-voltage detection function
External interrupt
Operable
Notes 1. When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
2.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Remark f
RH: Internal high-speed oscillation clock
f
X: X1 clock
f
EXCLK: External main system clock
f
XT: XT1 clock
f
EXCLKS: External subsystem clock
f
RL: Internal low-speed oscillation clock
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD 545
(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt
acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is
disabled, the next address instruction is executed.
Figure 22-3. HALT Mode Release by Interrupt Request Generation
HALT
instruction Wait
Wait Operating modeHALT modeOperating mode
Oscillation
High-speed system clock,
internal high-speed oscillation clock,
or subsystem clock
Status of CPU
Standby
release signal
Interrupt
request
Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby
mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is carried out: 8 or 9 clocks
• When vectored interrupt servicing is not carried out: 2 or 3 clocks
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD
546
(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 22-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
HALT mode
Reset
period
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Normal operation
(high-speed
system clock)
Oscillation stabilization time
(2
11
/f
X
to 2
16
/f
X
)
Normal operation
(internal high-speed
oscillation clock)
Oscillation
stopped
Starting X1 oscillation is
specified by software.
Reset
processing
(11 to 45 s)
μ
(2) When internal high-speed oscillation clock is used as CPU clock
HALT
instruction
Reset signal
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock) HALT mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset
processing
(11 to 45 s)
μ
μ
(3) When subsystem clock is used as CPU clock
HALT
instruction
Reset signal
Subsystem clock
(XT1 oscillation)
Normal operation
(subsystem clock) HALT mode
Reset
period
Normal operation mode
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation
stopped
Starting XT1 oscillation is
specified by software.
Reset
processing
(11 to 45 s)
μ
Remark f
X: X1 clock oscillation frequency
<R>
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD 547
Table 22-2. Operation in Response to Interrupt Request in HALT Mode
Release Source MK×× PR×× IE ISP Operation
0 0 0 × Next address
instruction execution
0 0 1 × Interrupt servicing
execution
0 1 0 1
0 1 × 0
Next address
instruction execution
0 1 1 1
Interrupt servicing
execution
Maskable interrupt
request
1 × × × HALT mode held
Reset − − × × Reset processing
×: don’t care
22.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the main system clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
The operating statuses in the STOP mode are shown below.
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD
548
Table 22-3. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock STOP Mode Setting
Item
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fRH)
When CPU Is Operating on
X1 Clock (fX)
When CPU Is Operating on
External Main System Clock
(fEXCLK)
System clock Clock supply to the CPU is stopped
fRH
fX
Stopped
Main system clock
fEXCLK Input invalid
fXT Status before STOP mode was set is retained
Subsystem clock
fEXCLKS Operates or stops by external clock input
fRL Status before STOP mode was set is retained
CPU Operation stopped
Flash memory Operation stopped
RAM Status before STOP mode was set is retained
Port (latch) Status before STOP mode was set is retained
00 16-bit timer/event
counter 01Note
Operation stopped
50 Operable only when TI50 is selected as the count clock 8-bit timer/event
counter 51 Operable only when TI51 is selected as the count clock
H0 Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter
50 operation
8-bit timer
H1 Operable only when fRL, fRL/27, or fRL/29 is selected as the count clock
Watch timer Operable only when subsystem clock is selected as the count clock
Watchdog timer Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Clock output Operable only when subsystem clock is selected as the count clock
A/D converter Operation stopped
UART0
UART6
Operable only when TM50 output is selected as the serial clock during 8-bit timer/event counter
50 operation
CSI10
CSI11Note
Operable only when external clock is selected as the serial clock
Serial interface
IIC0 Operation stopped
LCD controller/driver Operable only when subsystem clock is selected as the count clock
Multiplier/dividerNote Operation stopped
Power-on-clear function
Low-voltage detection function
External interrupt
Operable
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
(Cautions are listed on the next page.)
Remark f
RH: Internal high-speed oscillation clock
f
X: X1 clock
f
EXCLK: External main system clock
f
XT: XT1 clock
f
EXCLKS: External subsystem clock
f
RL: Internal low-speed oscillation clock
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD 549
Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
2. Even if “internal low-speed oscillator can be stopped by software” is selected by the option
byte, the internal low-speed oscillation clock continues in the STOP mode in the status before
the STOP mode is set. To stop the internal low-speed oscillator’s oscillation in the STOP mode,
stop it by software and then execute the STOP instruction.
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the
internal high-speed oscillation clock before the next execution of the STOP instruction. Before
changing the CPU clock from the internal high-speed oscillation clock to the high-speed system
clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time
with the oscillation stabilization time counter status register (OSTC).
4. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06
to 16.12
μ
s after the STOP mode is released when the internal high-speed oscillation clock is
selected as the CPU clock, or for the duration of 160 external clocks when the high-speed
system clock (external clock input) is selected as the CPU clock.
(2) STOP mode release
Figure 22-5. Operation Timing When STOP Mode Is Released
STOP mode
STOP mode release
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
Wait for oscillation accuracy
stabilization (86 to 361 s)
μ
HALT status
(oscillation stabilization time set by OSTS)
Clock switched by software
Clock switched by software
High-speed system clock
High-speed system clock
WaitNote2
WaitNote2
Supply of the CPU clock is stopped (4.06 to 16.12 s)Note1
High-speed system clock
μ
Supply of the CPU clock is stopped (160 external clocks)Note1
Internal high-speed
oscillation clock
Notes 1. When AMPH = 1
2. The wait time is as follows:
• When vectored interrupt servicing is carried out: 8 or 9 clocks
• When vectored interrupt servicing is not carried out: 2 or 3 clocks
<R>
<R>
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD
550
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Figure 22-6. STOP Mode Release by Interrupt Request Generation
(1) When high-speed system clock is used as CPU clock
Operating mode
(high-speed
system clock)
Operating mode
(high-speed
system clock)
OscillatesOscillates
STOP
instruction
STOP mode
Wait
(set by OSTS)
Standby release signal
Oscillation stabilization wait
(HALT mode status)
Oscillation stopped
High-speed
system clock
(X1 oscillation)
Status of CPU
Oscillation stabilization time (set by OSTS)
(2) When internal high-speed oscillation clock is used as CPU clock
Normal operation
(internal high-speed
oscillation clock)
Normal operation
(internal high-speed
oscillation clock)
Oscillates
STOP
instruction
STOP mode
Standby release signal
Internal high-speed
oscillation clock
Status of CPU
Oscillation stopped Oscillates
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Remark The broken lines indicate the case when the interrupt request that has released the standby mode
is acknowledged.
<R>
CHAPTER 22 STANDBY FUNCTION
User’s Manual U17473EJ2V0UD 551
(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 22-7. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock) STOP mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation stabilization time
(2
11
/f
X
to 2
16
/f
X
)
Oscillation
stopped
Starting X1 oscillation is
specified by software.
Oscillation stopped
Reset
processing
(11 to 45 s)
μ
(2) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Reset signal
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
STOP mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Status of CPU
Oscillates
Oscillation stopped
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset
processing
(11 to 45 s)
μ
μ
Remark f
X: X1 clock oscillation frequency
Table 22-4. Operation in Response to Interrupt Request in STOP Mode
Release Source MK×× PR×× IE ISP Operation
0 0 0 × Next address
instruction execution
0 0 1 × Interrupt servicing
execution
0 1 0 1
0 1 × 0
Next address
instruction execution
0 1 1 1
Interrupt servicing
execution
Maskable interrupt
request
1 × × × STOP mode held
Reset − − × × Reset processing
×: don’t care
<R>
User’s Manual U17473EJ2V0UD
552
CHAPTER 23 RESET FUNCTION
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H when the reset signal is generated.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
circuit voltage detection, and each item of hardware is set to the status shown in Tables 23-1 and 23-2. Each pin is
high impedance during reset signal generation or during the oscillation stabilization time just after a reset release.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (see Figures 23-2 to 23-4) after reset processing. Reset by POC and LVI circuit
power supply detection is automatically released when VDD ≥ VPOC or VDD ≥ VLVI after the reset, and program
execution starts using the internal high-speed oscillation clock (see CHAPTER 24 POWER-ON-CLEAR CIRCUIT
and CHAPTER 25 LOW-VOLTAGE DETECTOR) after reset processing.
Cautions 1. For an external reset, input a low level for 10
μ
s or more to the RESET pin.
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal
low-speed oscillation clock stop oscillating. External main system clock input and external
subsystem clock input become invalid.
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
input. However, the port pins become high-impedance.
CHAPTER 23 RESET FUNCTION
User’s Manual U17473EJ2V0UD 553
Figure 23-1. Block Diagram of Reset Function
LVIRFWDTRF
Reset control flag
register (RESF)
Internal bus
Watchdog timer reset signal
RESET
Power-on-clear circuit reset signal
Low-voltage detector reset signal Reset signal
Reset signal to LVIM/LVIS register
Clear
Set
Clear
Set
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltage detection register
2. LVIS: Low-voltage detection level selection register
CHAPTER 23 RESET FUNCTION
User’s Manual U17473EJ2V0UD
554
Figure 23-2. Timing of Reset by RESET Input
Delay Delay
(5 s (TYP.))
Hi-Z
Normal operationCPU clock Reset period
(oscillation stop)
Normal operation
(internal high-speed oscillation clock)
RESET
Internal reset signal
Note
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
Reset
processing
μ
Port pin
Reset signal to
LCD controller/driver
(11 to 45 s)
μ
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Note Set P130 (bit 0 of port mode register 13) to 1 by software.
Figure 23-3. Timing of Reset Due to Watchdog Timer Overflow
Normal operation Reset period
(oscillation stop)
CPU clock
Watchdog timer
overflow
Internal reset signal
Hi-Z
Note
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Reset
processing
Port pin
Reset signal to
LCD controller/driver
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
(11 to 45 s)
μ
Note Set P130 (bit 0 of port mode register 13) to 1 by software.
Caution A watchdog timer internal reset resets the watchdog timer.
<R>
<R>
CHAPTER 23 RESET FUNCTION
User’s Manual U17473EJ2V0UD 555
Figure 23-4. Timing of Reset in STOP Mode by RESET Input
Delay
Normal
operation
CPU clock Reset period
(oscillation stop)
RESET
Internal reset signal
STOP instruction execution
Stop status
(oscillation stop)
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Hi-Z
Note
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Reset
processing
Delay
(5 s (TYP.))
μ
Port pin
Reset signal to
LCD controller/driver
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
(11 to 45 s)
μ
Note Set P130 (bit 0 of port mode register 13) to 1 by software.
Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 24 POWER-
ON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR.
<R>
CHAPTER 23 RESET FUNCTION
User’s Manual U17473EJ2V0UD
556
Table 23-1. Operation Statuses During Reset Period
Item During Reset Period
System clock Clock supply to the CPU is stopped.
fRH Operation stopped
fX Operation stopped (pin is I/O port mode)
Main system clock
fEXCLK Clock input invalid (pin is I/O port mode)
fXT Operation stopped (pin is I/O port mode)
Subsystem clock
fEXCLKS Clock input invalid (pin is I/O port mode)
fRL
CPU
Flash memory
RAM
Port (latch)
00
16-bit timer/event
counter 01Note
50
8-bit timer/event
counter 51
H0 8-bit timer
H1
Watch timer
Watchdog timer
Clock output
A/D converter
UART0
UART6
CSI10
CSI11Note
Serial interface
IIC0
LCD controller/driver
Multiplier/dividerNote
Operation stopped
Power-on-clear function Operable
Low-voltage detection function
External interrupt
Operation stopped
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
Remark f
RH: Internal high-speed oscillation clock
f
X: X1 oscillation clock
f
EXCLK: External main system clock
f
XT: XT1 oscillation clock
f
EXCLKS: External subsystem clock
f
RL: Internal low-speed oscillation clock
CHAPTER 23 RESET FUNCTION
User’s Manual U17473EJ2V0UD 557
Table 23-2. Hardware Statuses After Reset Acknowledgment (1/3)
Hardware After Reset
AcknowledgmentNote 1
Program counter (PC) The contents of the
reset vector table
(0000H, 0001H) are
set.
Stack pointer (SP) Undefined
Program status word (PSW) 02H
Data memory UndefinedNote 2 RAM
General-purpose registers UndefinedNote 2
Port registers (P0 to P3, P7, P12, P13) (output latches) 00H
Port mode registers (PM0 to PM3, PM6, PM7, PM12, PM14) FFH
Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12) 00H
Internal expansion RAM size switching register (IXS) 0CH Note 3
Internal memory size switching register (IMS) CFHNote 3
Memory bank select register (BANK) 00H
Clock operation mode select register (OSCCTL) 00H
Processor clock control register (PCC) 01H
Internal oscillation mode register (RCM) 80H
Main OSC control register (MOC) 80H
Main clock mode register (MCM) 00H
Oscillation stabilization time select register (OSTS) 05H
Oscillation stabilization time counter status register (OSTC) 00H
Timer counters 00, 01 (TM00, TM01) 0000H
Capture/compare registers 000, 010, 001, 011 (CR000, CR010, CR001, CR011) 0000H
Mode control registers 00, 01 (TMC00, TMC01) 00H
Prescaler mode registers 00, 01 (PRM00, PRM01) 00H
Capture/compare control registers 00, 01 (CRC00, CRC01) 00H
16-bit timer/event
counters 00, 01Note 4
Timer output control registers 00, 01 (TOC00, TOC01) 00H
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2. When a reset is executed in the standby mode, the pre-reset status is held even after reset.
3. The initial values of the internal memory size switching register (IMS) and internal expansion RAM size
switching register (IXS) after a reset release are constant (IMS = CFH, IXS = 0CH) in all the 78K0/LG2
products, regardless of the internal memory capacity. Therefore, after a reset is released, be sure to set
the following values for each product.
Flash Memory Version
(78K0/LG2)
IMS IXS
μ
PD78F0393 C8H 0CH
μ
PD78F0394 CCH 0AH
μ
PD78F0395 CFH 08H
μ
PD78F0396 CCH 04H
μ
PD78F0397, 78F0397D Note5 CCH 00H
4. 16-bit timer/event counter 01 is available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and
78F0397D.
5. The ROM and RAM capacities of the products with the on-chip debug function can be debugged
according to the debug target products. Set IMS and IXS according to the debug target products.
<R>
CHAPTER 23 RESET FUNCTION
User’s Manual U17473EJ2V0UD
558
Table 23-2. Hardware Statuses After Reset Acknowledgment (2/3)
Hardware Status After Reset
AcknowledgmentNote 1
Timer counters 50, 51 (TM50, TM51) 00H
Compare registers 50, 51 (CR50, CR51) 00H
Timer clock selection registers 50, 51 (TCL50, TCL51) 00H
8-bit timer/event
counters 50, 51
Mode control registers 50, 51 (TMC50, TMC51) 00H
Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) 00H
Mode registers (TMHMD0, TMHMD1) 00H
8-bit timers H0, H1
Carrier control register 1 (TMCYC1)Note 2 00H
Watch timer Operation mode register (WTM) 00H
Clock output controller Clock output selection register (CKS) 00H
Watchdog timer Enable register (WDTE) 1AH/9AHNote 3
10-bit A/D conversion result register (ADCR) 0000H
8-bit A/D conversion result register (ADCRH) 00H
Mode register (ADM) 00H
Analog input channel specification register (ADS) 00H
A/D converter
A/D port configuration register (ADPC) 00H
Receive buffer register 0 (RXB0) FFH
Transmit shift register 0 (TXS0) FFH
Asynchronous serial interface operation mode register 0 (ASIM0) 01H
Asynchronous serial interface reception error status register 0 (ASIS0) 00H
Serial interface UART0
Baud rate generator control register 0 (BRGC0) 1FH
Receive buffer register 6 (RXB6) FFH
Transmit buffer register 6 (TXB6) FFH
Asynchronous serial interface operation mode register 6 (ASIM6) 01H
Asynchronous serial interface reception error status register 6 (ASIS6) 00H
Asynchronous serial interface transmission status register 6 (ASIF6) 00H
Clock selection register 6 (CKSR6) 00H
Baud rate generator control register 6 (BRGC6) FFH
Asynchronous serial interface control register 6 (ASICL6) 16H
Serial interface UART6
Input switch control register (ISC) 00H
Transmit buffer registers 10, 11 (SOTB10, SOTB11) 00H
Serial I/O shift registers 10, 11 (SIO10, SIO11) 00H
Serial operation mode registers 10, 11 (CSIM10, CSIM11) 00H
Serial interfaces CSI10,
CSI11Note 4
Serial clock selection registers 10, 11 (CSIC10, CSIC11) 00H
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2. 8-bit timer H1 only.
3. The reset value of WDTE is determined by the option byte setting.
4. Serial interface CSI11 is available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and
78F0397D.
CHAPTER 23 RESET FUNCTION
User’s Manual U17473EJ2V0UD 559
Table 23-2. Hardware Statuses After Reset Acknowledgment (3/3)
Hardware Status After Reset
AcknowledgmentNote 1
Shift register 0 (IIC0) 00H
Control register 0 (IICC0) 00H
Slave address register 0 (SVA0) 00H
Clock selection register 0 (IICCL0) 00H
Function expansion register 0 (IICX0) 00H
Status register 0 (IICS0) 00H
Serial interface IIC0
Flag register 0 (IICF0) 00H
LCD mode setting register (LCDMD) 00H
LCD display mode register (LCDM) 00H
LCD clock control register (LCDC) 00H
LCD controller/driver
LCD voltage boost control register 0 (VLCG0) 00H
Remainder data register 0 (SDR0) 0000H
Multiplication/division data register A0 (MDA0H, MDA0L) 0000H
Multiplication/division data register B0 (MDB0) 0000H
Multiplier/dividerNote 2
Multiplier/divider control register 0 (DMUC0) 00H
Key interrupt Key return mode register (KRM) 00H
Reset function Reset control flag register (RESF) 00HNote 3
Low-voltage detection register (LVIM) 00HNote 3 Low-voltage detector
Low-voltage detection level selection register (LVIS) 00HNote 3
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H) 00H
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H) FFH
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L, PR1H) FFH
External interrupt rising edge enable register (EGP) 00H
Interrupt
External interrupt falling edge enable register (EGN) 00H
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
2. Multiplier/divider is available only in the
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D.
3. These values vary depending on the reset source.
Reset Source
Register
RESET Input Reset by POC Reset by WDT Reset by LVI
WDTRF bit Set (1) Held RESF
LVIRF bit
Cleared (0) Cleared (0)
Held Set (1)
LVIM
LVIS
Cleared (00H) Cleared (00H) Cleared (00H) Held
CHAPTER 23 RESET FUNCTION
User’s Manual U17473EJ2V0UD
560
23.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0/LG2. The reset control flag register (RESF) is used to
store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Figure 23-5. Format of Reset Control Flag Register (RESF)
Address: FFACH After reset: 00HNote R
Symbol 7 6 5 4 3 2 1 0
RESF 0 0 0 WDTRF 0 0 0 LVIRF
WDTRF Internal reset request by watchdog timer (WDT)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset request is generated.
LVIRF Internal reset request by low-voltage detector (LVI)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset request is generated.
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 23-3.
Table 23-3. RESF Status When Reset Request Is Generated
Reset Source
Flag
RESET Input Reset by POC Reset by WDT Reset by LVI
WDTRF Set (1) Held
LVIRF
Cleared (0) Cleared (0)
Held Set (1)
User’s Manual U17473EJ2V0UD 561
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
24.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions.
• Generates internal reset signal at power on.
In the 1.59 V POC mode (option byte: POCMODE = 0), the reset signal is released when the supply voltage
(VDD) exceeds 1.59 V ±0.15 V.
In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the reset signal is released when the supply
voltage (VDD) exceeds 2.7 V ±0.2 V.
• Compares supply voltage (VDD) and detection voltage (VPOC = 1.59 V ±0.15 V), generates internal reset signal
when VDD < VPOC.
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF)
is cleared to 00H.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag
that indicates the reset source is located in the reset control flag register (RESF) for when an internal
reset signal is generated by the watchdog timer (WDT) or low-voltage-detector (LVI). RESF is not
cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI.
For details of RESF, see CHAPTER 23 RESET FUNCTION.
<R>
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
User’s Manual U17473EJ2V0UD
562
24.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 24-1.
Figure 24-1. Block Diagram of Power-on-Clear Circuit
−
+
Reference
voltage
source
Internal reset signal
V
DD
V
DD
24.3 Operation of Power-on-Clear Circuit
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
• An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the
detection voltage (VPOC = 1.59 V ±0.15 V), the reset status is released.
• The supply voltage (VDD) and detection voltage (VPOC = 1.59 V ±0.15 V) are compared. When VDD < VPOC, the
internal reset signal is generated. It is released when VDD ≥ VPOC.
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
• An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the
detection voltage (VDDPOC = 2.7 V ±0.2 V), the reset status is released.
• The supply voltage (VDD) and detection voltage (VPOC = 1.59 V ±0.15 V) are compared. When VDD < VPOC, the
internal reset signal is generated. It is released when VDD ≥ VDDPOC.
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is
shown below.
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
User’s Manual U17473EJ2V0UD 563
Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Note 3 Note 3
Internal high-speed
oscillation clock (f
RH
)
High-speed
system clock (f
XH
)
(when X1 oscillation
is selected)
Starting oscillation is
specified by software.
VPOC = 1.59 V (TYP.)
VLVI
Operation
stops
Wait for voltage
stabilization
(1.93 to 5.39 ms)
Normal operation
(internal high-speed
oscillation clock)
Note 4
Operation stops
Reset period
(oscillation
stop)
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Normal operation
(internal high-speed
oscillation clock)
Note 4
Starting oscillation is
specified by software. Starting oscillation is
specified by software.
CPU
0 V
Supply voltage
(VDD)
1.8 V
Note 1
Wait for voltage
stabilization
(1.93 to 5.39 ms)
Normal operation
(internal high-speed
oscillation clock)Note 4
0.5 V/ms (MIN.)Note 2
Set LVI to be
used for reset
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Internal reset signal
Reset processing (11 to 45 s)
μ
Reset processing (11 to 45 s)
μ
Reset processing (11 to 45 s)
μ
μ
Notes 1. The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2. If the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MIN.) on power application, input a low level
to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7 V/1.59 V
POC mode by using an option byte (POCMODE = 1).
3. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
4. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 25
LOW-VOLTAGE DETECTOR).
Remark V
LVI: LVI detection voltage
V
POC: POC detection voltage
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
User’s Manual U17473EJ2V0UD
564
Figure 24-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Internal high-speed
oscillation clock (f
RH
)
High-speed
system clock (f
XH
)
(when X1 oscillation
is selected)
Starting oscillation is
specified by software.
Internal reset signal
VDDPOC = 2.7 V (TYP.)
V
POC
= 1.59 V (TYP.)
V
LVI
Operation
stops
Normal operation
(internal high-speed
oscillation clock)
Note 2
Normal operation
(internal high-speed
oscillation clock)
Note 2
Operation stops
Reset period
(oscillation
stop)
Reset period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)
Note 2
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
CPU
0 V
Supply voltage
(VDD)
1.8 V
Note 1
Reset processing (11 to 45 s)
μ
Reset processing (11 to 45 s)
μ
Reset processing (11 to 45 s)
μ
Set LVI to be
used for reset
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Notes 1. The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 25
LOW-VOLTAGE DETECTOR).
2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
Remark V
LVI: LVI detection voltage
V
POC: POC detection voltage
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
User’s Manual U17473EJ2V0UD 565
24.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 24-3. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
;Check the reset source
Note 2
Initialize the port.
Note 1
Reset
Initialization
processing <1>
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing <2>
Setting 8-bit timer H1
(to measure 50 ms)
; Setting of division ratio of system clock,
such as setting of timer or A/D converter
Yes
No
Power-on-clear
Clearing WDT
;f
PRS
= Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
Source: f
PRS
(8.4 MHz (MAX.))/2
12
,
where comparison value = 102: ≅ 50 ms
Timer starts (TMHE1 = 1).
Notes 1. If reset is generated again during this period, initialization processing <2> is not started.
2. A flowchart is shown on the next page.
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
User’s Manual U17473EJ2V0UD
566
Figure 24-3. Example of Software Processing After Reset Release (2/2)
• Checking reset source
Yes
No
Check reset source
Power-on-clear/external
reset generated
Reset processing by
watchdog timer
Reset processing by
low-voltage detector
No
WDTRF of RESF
register = 1?
LVIRF of RESF
register = 1?
Yes
User’s Manual U17473EJ2V0UD 567
CHAPTER 25 LOW-VOLTAGE DETECTOR
25.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has the following functions.
• The LVI circuit compares the supply voltage (VDD) with the detection voltage (VLVI) or the input voltage from an
external input pin (EXLVI) with the detection voltage (VEXLVI = 1.21 V (TYP.): fixed), and generates an internal
reset or internal interrupt signal.
• The supply voltage (VDD) or input voltage from an external input pin (EXLVI) can be selected by software.
• Reset or interrupt function can be selected by software.
• Detection levels (16 levels) of supply voltage can be changed by software.
• Operable in STOP mode.
The reset and interrupt signals are generated as follows depending on selection by software.
Selection of Level Detection of Supply Voltage (VDD)
(LVISEL = 0)
Selection Level Detection of Input Voltage from
External Input Pin (EXLVI) (LVISEL = 1)
Selects reset (LVIMD = 1). Selects interrupt (LVIMD = 0). Selects reset (LVIMD = 1). Selects interrupt (LVIMD = 0).
Generates an internal reset
signal when VDD < VLVI and
releases the reset signal when
VDD ≥ VLVI.
Generates an internal interrupt
signal when VDD drops lower
than VLVI (VDD < VLVI) or when
VDD becomes VLVI or higher
(VDD ≥ VLVI).
Generates an internal reset
signal when EXLVI < VEXLVI
and releases the reset signal
when EXLVI ≥ VEXLVI.
Generates an internal interrupt
signal when EXLVI drops
lower than VEXLVI (EXLVI <
VEXLVI) or when EXLVI
becomes VEXLVI or higher
(EXLVI ≥ VEXLVI).
Remark LVISEL: Bit 2 of low-voltage detection register (LVIM)
LVIMD: Bit 1 of LVIM
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
reset occurs. For details of RESF, see CHAPTER 23 RESET FUNCTION.
<R>
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
568
25.2 Configuration of Low-Voltage Detector
The block diagram of the low-voltage detector is shown in Figure 25-1.
Figure 25-1. Block Diagram of Low-Voltage Detector
LVIS1 LVIS0 LVION
−
+
Reference
voltage
source
VDD
Internal bus
N-ch
Low-voltage detection level
selection register (LVIS)
Low-voltage detection register
(LVIM)
LVIS2
LVIS3 LVIF
INTLVI
Internal reset signal
4
LVISEL
EXLVI/P120/
INTP0
LVIMD
VDD
Low-voltage detection
level selector
Selector
Selector
25.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
• Low-voltage detection register (LVIM)
• Low-voltage detection level selection register (LVIS)
• Port mode register 12 (PM12)
(1) Low-voltage detection register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears LVIM to 00H.
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD 569
Figure 25-2. Format of Low-Voltage Detection Register (LVIM)
<0>
LVIF
<1>
LVIMD
<2>
LVISEL
3
0
4
0
5
0
6
0
<7>
LVION
Symbol
LVIM
Address: FFBEH After reset: 00H R/W
Note 1
LVIONNotes 2, 3 Enables low-voltage detection operation
0 Disables operation
1 Enables operation
LVISELNote 2 Voltage detection selection
0 Detects level of supply voltage (VDD)
1 Detects level of input voltage from external input pin (EXLVI)
LVIMDNote 2 Low-voltage detection operation mode (interrupt/reset) selection
0 • LVISEL = 0: Generates an internal interrupt signal when the supply voltage (VDD) drops
lower than the detection voltage (VLVI) (VDD < VLVI) or when VDD becomes
VLVI or higher (VDD ≥ VLVI).
• LVISEL = 1: Generates an interrupt signal when the input voltage from an external
input pin (EXLVI) drops lower than the detection voltage (VEXLVI) (EXLVI <
VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI ≥ VEXLVI).
1 • LVISEL = 0: Generates an internal reset signal when the supply voltage (VDD) <
detection voltage (VLVI) and releases the reset signal when VDD ≥ VLVI.
• LVISEL = 1: Generates an internal reset signal when the input voltage from an
external input pin (EXLVI) < detection voltage (VEXLVI) and releases the
reset signal when EXLVI ≥ VEXLVI.
LVIFNote 4 Low-voltage detection flag
0 • LVISEL = 0: Supply voltage (VDD) ≥ detection voltage (VLVI), or when operation is
disabled
• LVISEL = 1: Input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI),
or when operation is disabled
1 • LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI)
• LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI)
Notes 1. Bit 0 is read-only.
2. LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset.
These are not cleared to 0 in the case of an LVI reset.
3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to wait for an operation stabilization time (10
μ
s (MAX.)) when LVION is set to 1 until
the voltage is confirmed at LVIF.
4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Cautions 1. To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
570
(2) Low-voltage detection level selection register (LVIS)
This register selects the low-voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input clears LVIS to 00H.
Figure 25-3. Format of Low-Voltage Detection Level Selection Register (LVIS)
0
LVIS0
1
LVIS1
2
LVIS2
3
LVIS3
4
0
5
0
6
0
7
0
Symbol
LVIS
Address: FFBFH After reset: 00H R/W
LVIS3 LVIS2 LVIS1 LVIS0 Detection level
0 0 0 0 VLVI0 (4.24 V ±0.1 V)
0 0 0 1 VLVI1 (4.09 V ±0.1 V)
0 0 1 0 VLVI2 (3.93 V ±0.1 V)
0 0 1 1 VLVI3 (3.78 V ±0.1 V)
0 1 0 0 VLVI4 (3.62 V ±0.1 V)
0 1 0 1 VLVI5 (3.47 V ±0.1 V)
0 1 1 0 VLVI6 (3.32 V ±0.1 V)
0 1 1 1 VLVI7 (3.16 V ±0.1 V)
1 0 0 0 VLVI8 (3.01 V ±0.1 V)
1 0 0 1 VLVI9 (2.85 V ±0.1 V)
1 0 1 0 VLVI10 (2.70 V ±0.1 V)
1 0 1 1 VLVI11 (2.55 V ±0.1 V)
1 1 0 0 VLVI12 (2.39 V ±0.1 V)
1 1 0 1 VLVI13 (2.24 V ±0.1 V)
1 1 1 0 VLVI14 (2.08 V ±0.1 V)
1 1 1 1 VLVI15 (1.93 V ±0.1 V)
Cautions 1. Be sure to clear bits 4 to 7 to “0”.
2. Do not change the value of LVIS during LVI operation.
3. When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (VEXLVI = 1.21 V (TYP.)) is fixed. Therefore, setting of LVIS is not necessary.
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD 571
(3) Port mode register 12 (PM12)
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this
time, the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM12 to FFH.
Figure 25-4. Format of Port Mode Register 12 (PM12)
0
PM120
1
PM121
2
PM122
3
PM123
4
PM124
5
1
6
1
7
1
Symbol
PM12
Address: FF2CH After reset: FFH R/W
PM12n P12n pin I/O mode selection (n = 0 to 4)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
25.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes.
(1) Used as reset (LVIMD = 1)
• If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI), generates an internal reset
signal when VDD < VLVI, and releases internal reset when VDD ≥ VLVI.
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21
V (TYP.)), generates an internal reset signal when EXLVI < VEXLVI, and releases internal reset when EXLVI ≥
VEXLVI.
(2) Used as interrupt (LVIMD = 0)
• If LVISEL = 0, compares the supply voltage (VDD) and detection voltage (VLVI). When VDD drops lower than
VLVI (VDD < VLVI) or when VDD becomes VLVI or higher (VDD ≥ VLVI), generates an interrupt signal (INTLVI).
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (VEXLVI = 1.21
V (TYP.)). When EXLVI drops lower than VEXLVI (EXLVI < VEXLVI) or when EXLVI becomes VEXLVI or higher
(EXLVI ≥ VEXLVI), generates an interrupt signal (INTLVI).
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
LVISEL: Bit 2 of LVIM
<R>
<R>
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
572
25.4.1 When used as reset
(1) When detecting level of supply voltage (VDD)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
<3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for an operation stabilization time (10
μ
s (MAX.)).
<6> Wait until it is checked that (supply voltage (VDD) ≥ detection voltage (VLVI)) by bit 0 (LVIF) of LVIM.
<7> Set bit 1 (LVIMD) of LVIM to 1 (generates reset when the level is detected).
Figure 25-5 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers
in this timing chart correspond to <1> to <7> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <4>.
2. If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIMD is set to 1, an internal reset
signal is not generated.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVIMD to 0 and then LVION to 0.
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD 573
Figure 25-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Supply Voltage (VDD)) (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Supply voltage (V
DD
)
<3>
<1>
Time
LVIMK flag
(set by software)
LVIF flag
LVIRF flag
Note 3
Note 2
LVI reset signal
POC reset signal
Internal reset signal
Cleared by
software
Not cleared Not cleared
Not cleared Not cleared
Cleared by
software
<4>
<7>
Clear
Clear
Clear
<5> Wait time
LVION flag
(set by software)
LVIMD flag
(set by software)
H
Note 1
L
LVISEL flag
(set by software)
<6>
<2>
V
LVI
V
POC
= 1.59 V (TYP.)
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23
RESET FUNCTION.
Remark <1> to <7> in Figure 25-5 above correspond to <1> to <7> in the description of “When starting
operation” in 25.4.1 (1) When detecting level of supply voltage (VDD).
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
574
Figure 25-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Supply Voltage (VDD)) (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Supply voltage (V
DD
)
V
LVI
<3>
<1>
Time
LVIMK flag
(set by software)
LVIF flag
LVIRF flag
Note 3
Note 2
LVI reset signal
POC reset signal
Internal reset signal
Cleared by
software
Not cleared Not cleared
Not cleared Not cleared
Cleared by
software
<4>
<7>
Clear
Clear
Clear
<5> Wait time
LVION flag
(set by software)
LVIMD flag
(set by software)
H
Note 1
L
LVISEL flag
(set by software)
<6>
<2>
2.7 V (TYP.)
V
POC
= 1.59 V (TYP.)
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23
RESET FUNCTION.
Remark <1> to <7> in Figure 25-5 above correspond to <1> to <7> in the description of “When starting
operation” in 25.4.1 (1) When detecting level of supply voltage (VDD).
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD 575
(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to wait for an operation stabilization time (10
μ
s (MAX.)Note).
<5> Wait until it is checked that (input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI =
1.21 V (TYP.))) by bit 0 (LVIF) of LVIM.
<6> Set bit 1 (LVIMD) of LVIM to 1 (generates reset signal when the level is detected).
Figure 25-6 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers
in this timing chart correspond to <1> to <6> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <3>.
2. If input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.))
when LVIMD is set to 1, an internal reset signal is not generated.
3. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVIMD to 0 and then LVION to 0.
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
576
Figure 25-6. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Input Voltage from External Input Pin (EXLVI))
Input voltage from
external input pin (EXLVI)
LVI detection voltage
(VEXLVI)
<1>
Time
LVIMK flag
(set by software)
LVIF flag
LVIRF flagNote 3
Note 2
LVI reset signal
Internal reset signal
Cleared by
software
Not cleared Not cleared
Not cleared Not cleared
Cleared by
software
<3>
<6>
LVION flag
(set by software)
LVIMD flag
(set by software)
HNote 1
LVISEL flag
(set by software)
<5>
<2>
Not clearedNot cleared
<4> Wait time
Not cleared
Not cleared
Not cleared
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 23
RESET FUNCTION.
Remark <1> to <6> in Figure 25-6 above correspond to <1> to <6> in the description of “When starting
operation” in 25.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD 577
25.4.2 When used as interrupt
(1) When detecting level of supply voltage (VDD)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
(VDD)) (default value).
<3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<5> Use software to wait for an operation stabilization time (10
μ
s (MAX.)).
<6> Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the falling edge of VDD, or
“supply voltage (VDD) < detection voltage (VLVI)” when detecting the rising edge of VDD, at bit 0 (LVIF) of
LVIM.
<7> Clear the interrupt request flag of LVI (LVIIF) to 0.
<8> Release the interrupt mask flag of LVI (LVIMK).
<9> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
<10> Execute the EI instruction (when vector interrupts are used).
Figure 25-7 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <9> above.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVION to 0.
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
578
Figure 25-7. Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Supply Voltage (VDD)) (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Supply voltage (V
DD
)
Time
<1>
Note 1
<8> Cleared by software
LVIMK flag
(set by software)
LVIF flag
INTLVI
LVIIF flag
Internal reset signal
<4>
<6>
<7>
Cleared by software
<5> Wait time
LVION flag
(set by software)
Note 2
Note 2
<3>
L
LVISEL flag
(set by software)
<2>
LVIMD flag
(set by software) L
<9>
V
LVI
V
POC
= 1.59 V (TYP.)
Note 2
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
Remark <1> to <9> in Figure 25-7 above correspond to <1> to <9> in the description of “When starting
operation” in 25.4.2 (1) When detecting level of supply voltage (VDD).
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD 579
Figure 25-7. Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Supply Voltage (VDD)) (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Supply voltage (V
DD
)
Time
<1>
Note 1
<8> Cleared by software
LVIMK flag
(set by software)
LVIF flag
INTLVI
LVIIF flag
Internal reset signal
<4>
<6>
<7>
Cleared by software
<5> Wait time
LVION flag
(set by software)
Note 2
Note 2
<3>
L
LVISEL flag
(set by software)
<2>
LVIMD flag
(set by software) L
<9>
V
LVI
2.7 V(TYP.)
V
POC
= 1.59 V (TYP.)
Note 2
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
Remark <1> to <9> in Figure 25-7 above correspond to <1> to <9> in the description of “When starting
operation” in 25.4.2 (1) When detecting level of supply voltage (VDD).
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
580
(2) When detecting level of input voltage from external input pin (EXLVI)
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from
external input pin (EXLVI)).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to wait for an operation stabilization time (10
μ
s (MAX.)).
<5> Confirm that “input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI = 1.21 V (TYP.)”
when detecting the falling edge of EXLVI, or “input voltage from external input pin (EXLVI) < detection
voltage (VEXLVI = 1.21 V (TYP.)” when detecting the rising edge of EXLVI, at bit 0 (LVIF) of LVIM.
<6> Clear the interrupt request flag of LVI (LVIIF) to 0.
<7> Release the interrupt mask flag of LVI (LVIMK).
<8> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
<9> Execute the EI instruction (when vector interrupts are used).
Figure 25-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in
this timing chart correspond to <1> to <8> above.
Caution Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVION to 0.
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD 581
Figure 25-8. Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Input Voltage from External Input Pin (EXLVI))
Input voltage from
external input pin (EXLVI)
V
EXLVI
Time
<1>
Note 1
<7> Cleared by software
LVIMK flag
(set by software)
LVIF flag
INTLVI
LVIIF flag
<3>
<5>
<6>
Cleared by software
<4> Wait time
LVION flag
(set by software)
Note 2
Note 2
LVISEL flag
(set by software)
<2>
LVIMD flag
(set by software) L
<8>
Note 2
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
Remark <1> to <8> in Figure 25-8 above correspond to <1> to <8> in the description of “When starting
operation” in 25.4.2 (2) When detecting level of input voltage from external input pin (EXLVI).
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
582
25.5 Cautions for Low-Voltage Detector
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage
(VLVI), the operation is as follows depending on how the low-voltage detector is used.
(1) When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set
by taking action (1) below.
(2) When used as interrupt
Interrupt requests may be frequently generated. Take (b) of action (2) below.
<Action>
(1) When used as reset
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports (see Figure 25-9).
(2) When used as interrupt
(a) Confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when detecting the falling edge of VDD, or
“supply voltage (VDD) < detection voltage (VLVI)” when detecting the rising edge of VDD, in the servicing routine
of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of
interrupt request flag register 0L (IF0L) to 0.
(b) In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait
for the supply voltage fluctuation period, confirm that “supply voltage (VDD) ≥ detection voltage (VLVI)” when
detecting the falling edge of VDD, or “supply voltage (VDD) < detection voltage (VLVI)” when detecting the rising
edge of VDD, using the LVIF flag, and clear the LVIIF flag to 0.
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
words change as follows.
• Supply voltage (VDD) → Input voltage from external input pin (EXLVI)
• Detection voltage (VLVI) → Detection voltage (VEXLVI = 1.21 VNote)
<R>
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD 583
Figure 25-9. Example of Software Processing After Reset Release (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
;Check the reset source
Note
Initialize the port.
; Setting of detection level by LVIS
The low-voltage detector operates (LVION = 1).
Reset
Initialization
processing <1>
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing <2>
Setting 8-bit timer H1
(to measure 50 ms)
; Setting of division ratio of system clock,
such as setting of timer or A/D converter
Yes
No
Setting LVI
Clearing WDT
Detection
voltage or higher
(LVIF = 0?)
Yes
LVIF = 0
Restarting timer H1
(TMHE1 = 0 → TMHE1 = 1)
No
;The low-voltage detection flag is cleared.
; The timer counter is cleared and the timer is started.
LVI reset
;f
PRS
= Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
Source: f
PRS
(8.4 MHz (MAX.))/2
12
,
Where comparison value = 102: ≅ 50 ms
Timer starts (TMHE1 = 1).
Note A flowchart is shown on the next page.
CHAPTER 25 LOW-VOLTAGE DETECTOR
User’s Manual U17473EJ2V0UD
584
Figure 25-9. Example of Software Processing After Reset Release (2/2)
• Checking reset source
Yes
No
Check reset source
Power-on-clear/external
reset generated
Reset processing by
watchdog timer
Reset processing by
low-voltage detector
Yes
WDTRF of RESF
register = 1?
LVIRF of RESF
register = 1?
No
User’s Manual U17473EJ2V0UD 585
CHAPTER 26 OPTION BYTE
26.1 Functions of Option Bytes
The flash memory at 0080H to 0084H of the 78K0/LG2 is an option byte area. When power is turned on or when
the device is restarted from the reset status, the device automatically references the option bytes and sets specified
functions. When using the product, be sure to set the following functions by using the option bytes.
When the boot swap operation is used during self-programming, 0080H to 0084H are switched to 1080H to 1084H.
Therefore, set values that are the same as those of 0080H to 0084H to 1080H to 1084H in advance.
(1) 0080H/1080H
{ Internal low-speed oscillator operation
• Can be stopped by software
• Cannot be stopped
{ Watchdog timer interval time setting
{ Watchdog timer counter operation
• Enabled counter operation
• Disabled counter operation
{ Watchdog timer window open period setting
Caution Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are
switched during the boot swap operation.
(2) 0081H/1081H
{ Selecting POC mode
• During 2.7 V/1.59 V POC mode operation (POCMODE = 1)
The device is in the reset state upon power application and until the supply voltage reaches 2.7 V (TYP.). It
is released from the reset state when the voltage exceeds 2.7 V (TYP.). After that, POC is not detected at
2.7 V but is detected at 1.59 V (TYP.).
If the supply voltage rises to 1.8 V after power application at a pace slower than 0.5 V/ms (MIN.), use of the
2.7 V/1.59 V POC mode is recommended.
• During 1.59 V POC mode operation (POCMODE = 0)
The device is in the reset state upon power application and until the supply voltage reaches 1.59 V (TYP.).
It is released from the reset state when the voltage exceeds 1.59 V (TYP.). After that, POC is detected at
1.59 V (TYP.), in the same manner as on power application.
Caution POCMODE can only be written by using a dedicated flash programmer. It cannot be set
during self-programming or boot swap operation during self-programming (at this time, 1.59
V POC mode (default) is set). However, because the value of 1081H is copied to 0081H
during the boot swap operation, it is recommended to set a value that is the same as that of
0081H to 1081H when the boot swap function is used.
<R>
CHAPTER 26 OPTION BYTE
User’s Manual U17473EJ2V0UD
586
(3) 0084H/1084H
{ On-chip debug operation control
• Disabling on-chip debug operation
• Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the on-
chip debug security ID fails
• Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of
the on-chip debug security ID fails
Cautions 1. Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not equipped
with the on-chip debug function (
μ
PD78F0393, 78F0394, 78F0395, 78F0396, and 78F0397).
Also set 00H to 1084H because 0084H and 1084H are switched at boot swapping.
2. To use the on-chip debug function with a product equipped with the on-chip debug function
(
μ
PD78F0397D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to
1084H because 0084H and 1084H are switched at boot swapping.
Caution Be sure to set 00H to 0082H and 0083H (0082H/1082H and 0083H/1083H when the boot swap
function is used).
CHAPTER 26 OPTION BYTE
User’s Manual U17473EJ2V0UD 587
26.2 Format of Option Byte
The format of the option byte is shown below.
Figure 26-1. Format of Option Byte (1/2)
Address: 0080H/1080HNote
7 6 5 4 3 2 1 0
0 WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC
WINDOW1 WINDOW0 Watchdog timer window open period
0 0 25%
0 1 50%
1 0 75%
1 1 100%
WDTON Operation control of watchdog timer counter/illegal access detection
0 Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
1 Counter operation enabled (counting started after reset), illegal access detection operation enabled
WDCS2 WDCS1 WDCS0 Watchdog timer overflow time
0 0 0 210/fRL (3.88 ms)
0 0 1 211/fRL (7.76 ms)
0 1 0 212/fRL (15.52 ms)
0 1 1 213/fRL (31.03 ms)
1 0 0 214/fRL (62.06 ms)
1 0 1 215/fRL (124.12 ms)
1 1 0 216/fRL (248.24 ms)
1 1 1 217/fRL (496.48 ms)
LSROSC Internal low-speed oscillator operation
0 Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register)
1 Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
boot swap operation.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
prohibited.
2. The watchdog timer continues its operation during self-programming and EEPROM
emulation of the flash memory. During processing, the interrupt acknowledge time is
delayed. Set the overflow time and window size taking this delay into consideration.
3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
4. Be sure to clear bit 7 to 0.
Remarks 1. fRL: Internal low-speed oscillation clock frequency
2. ( ): fRL = 264 kHz (MAX.)
CHAPTER 26 OPTION BYTE
User’s Manual U17473EJ2V0UD
588
Figure 26-1. Format of Option Byte (2/2)
Address: 0081H/1081HNotes 1, 2
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 POCMODE
POCMODE POC mode selection
0 1.59 V POC mode (default)
1 2.7 V/1.59 V POC mode
Notes 1. POCMODE can only be written by using a dedicated flash programmer. It cannot be set during self-
programming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default)
is set). However, because the value of 1081H is copied to 0081H during the boot swap operation, it is
recommended to set a value that is the same as that of 0081H to 1081H when the boot swap function
is used.
2. To change the setting for the POC mode, set the value to 0081H again after batch erasure (chip
erasure) of the flash memory. The setting cannot be changed after the memory of the specified block
is erased.
Caution Be sure to clear bits 7 to 1 to 0.
Address: 0082H/1082H, 0083H/1083HNote
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
Note Be sure to set 00H to 0082H and 0083H, as these addresses are reserved areas. Also set 00H to 1082 and
1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation is
used.
Address: 0084H/1084HNotes1, 2
7 6 5 4 3 2 1 0
0 0 0 0 0 0 OCDEN1 OCDEN0
OCDEN1 OCDEN0 On-chip debug operation control
0 0 Operation disabled
0 1 Setting prohibited
1 0 Operation enabled. Does not erase data of the flash memory in case authentication
of the on-chip debug security ID fails.
1 1 Operation enabled. Erases data of the flash memory in case authentication of the
on-chip debug security ID fails.
Notes 1. Be sure to set 00H (on-chip debug operation disabled) to 0084H for products not equipped with the on-
chip debug function (
μ
PD78F0393, 78F0394, 78F0395, 78F0396, and 78F0397). Also set 00H to
1084H because 0084H and 1084H are switched at boot swapping.
2. To use the on-chip debug function with a product equipped with the on-chip debug function
(
μ
PD78F0397D), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H
because 0084H and 1084H are switched at boot swapping.
Remark For the on-chip debug security ID, see CHAPTER 28 ON-CHIP DEBUG FUNCTION (
μ
PD78F0397D
ONLY).
CHAPTER 26 OPTION BYTE
User’s Manual U17473EJ2V0UD 589
Here is an example of description of the software for setting the option bytes.
OPT CSEG AT 0080H
OPTION: DB 30H ; Enables watchdog timer operation (illegal access detection operation),
; Window open period of watchdog timer: 50%,
; Overflow time of watchdog timer: 210/fRL,
; Internal low-speed oscillator can be stopped by software.
DB 00H ; 1.59 V POC mode
DB 00H ; Reserved area
DB 00H ; Reserved area
DB 00H ; On-chip debug operation disabled
Remark Referencing of the option byte is performed during reset processing. For the reset processing timing,
see CHAPTER 23 RESET FUNCTION.
User’s Manual U17473EJ2V0UD
590
CHAPTER 27 FLASH MEMORY
The 78K0/LG2 incorporates the flash memory to which a program can be written, erased, and overwritten while
mounted on the board.
27.1 Internal Memory Size Switching Register
The internal memory capacity can be selected using the internal memory size switching register (IMS).
IMS is set by an 8-bit memory manipulation instruction.
Reset signal generation sets IMS to CFH.
Caution Be sure to set each product to the values shown in Table 27-1 after a reset release.
Figure 27-1. Format of Internal Memory Size Switching Register (IMS)
Address: FFF0H After reset: CFH R/W
Symbol 7 6 5 4 3 2 1 0
IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0
RAM2 RAM1 RAM0 Internal high-speed RAM capacity selection
1 1 0 1024 bytes
Other than above Setting prohibited
ROM3 ROM2 ROM1 ROM0 Internal ROM capacity selection
1 0 0 0 32 KB
1 1 0 0 48 KB
1 1 1 1 60 KB
Other than above Setting prohibited
Caution To set the memory size, set IMS and then IXS. Set the memory size so that the internal ROM and
internal expansion RAM areas do not overlap.
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 591
Table 27-1. Internal Memory Size Switching Register Settings
Flash Memory Versions (78K0/LG2) IMS Setting
μ
PD78F0393 C8H
μ
PD78F0394 CCH
μ
PD78F0395 CFH
μ
PD78F0396 CCHNote 2
μ
PD78F0397, 78F0397DNote 1
CCHNote 2
Notes 1. The internal ROM and internal high-speed RAM capacities of the products with the on-chip debug
function can be debugged according to the debug target products. Set IMS and IXS according to the
debug target products.
2. The
μ
PD78F0396, 78F0397, and 78F0397D have internal ROMs of 96 KB and 128 KB, respectively.
However, the set values for the IMS of these devices is the same as those for the 48 KB product
because memory banks are used. For how to set the memory banks, see Figure 4-2 Format of
Memory Bank Select Register (BANK).
27.2 Internal Expansion RAM Size Switching Register
The internal expansion RAM capacity can be selected using the internal expansion RAM size switching register
(IXS).
IXS is set by an 8-bit memory manipulation instruction.
Reset signal generation sets IXS to 0CH.
Caution Be sure to set each product to the values shown in Table 27-2 after a reset release.
Figure 27-2. Format of Internal Expansion RAM Size Switching Register (IXS)
Address: FFF4H After reset: 0CH R/W
Symbol 7 6 5 4 3 2 1 0
IXS 0 0 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal expansion RAM capacity selection
0 1 1 0 0 0 byte
0 1 0 1 0 1024 bytes
0 1 0 0 0 2048 bytes
0 0 1 0 0 4096 bytes
0 0 0 0 0 6144 bytes
Other than above Setting prohibited
Caution To set memory size, set IMS and then IXS. Set memory size so that the internal ROM area and
internal expansion RAM area do not overlap.
<R>
<R>
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
592
Table 27-2. Internal Expansion RAM Size Switching Register Settings
Flash Memory Versions (78K0/LG2) IXS Setting
μ
PD78F0393 0CH
μ
PD78F0394 0AH
μ
PD78F0395 08H
μ
PD78F0396 04H
μ
PD78F0397, 78F0397DNote
00H
Note The internal expansion RAM capacity of the products with the on-chip debug function can be debugged
according to the debug target products. Set IXS according to the debug target products.
27.3 Writing with Flash Programmer
Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer.
(1) On-board programming
The contents of the flash memory can be rewritten after the 78K0/LG2 has been mounted on the target system.
The connectors that connect the dedicated flash programmer must be mounted on the target system.
(2) Off-board programming
Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0/LG2 is
mounted on the target system.
Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
<R>
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 593
Table 27-3. Wiring Between 78K0/LG2 and Dedicated Flash Programmer (GC Package)
Pin Configuration of Dedicated Flash Programmer With CSI10 With UART6
Signal Name I/O Pin Function Pin Name Pin No. Pin Name Pin No.
SI/RxD Input Receive signal SO10/P12 74 TxD6/P13 73
SO/TxD Output Transmit signal SI10/RxD0/P11 75 RxD6/P14 72
SCK Output Transfer clock SCK10/TxD0/P10 76 − −
CLK Output Clock to 78K0/LG2 −Note 1 − EXCLK/X2/P122Note 2 10
/RESET Output Reset signal RESET 6 RESET 6
FLMD0 Output Mode signal FLMD0 9 FLMD0 9
VDD 14 VDD 14
LVDD 65 LVDD 65
VDD I/O
VDD voltage generation/
power monitoring
AVREF 77 AVREF 77
VSS 13 VSS 13
LVSS 64 LVSS 64
GND − Ground
AVSS 78 AVSS 78
Notes 1. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
2. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When
using the clock output of the dedicated flash programmer, pin connection varies depending on the type of
the dedicated flash programmer used.
• PG-FP4, FL-PR4: Connect CLK of the programmer to EXCLK/X2/P122 (pin 10).
• PG-FPL3, FP-LITE3: Connect CLK of the programmer to X1/P121 (pin 11), and connect its inverted
signal to X2/EXCLK/P122 (pin 10).
Table 27-4. Wiring Between 78K0/LG2 and Dedicated Flash Programmer (GF Package)
Pin Configuration of Dedicated Flash Programmer With CSI10 With UART6
Signal Name I/O Pin Function Pin Name Pin No. Pin Name Pin No.
SI/RxD Input Receive signal SO10/P12 77 TxD6/P13 76
SO/TxD Output Transmit signal SI10/RxD0/P11 78 RxD6/P14 75
SCK Output Transfer clock SCK10/TxD0/P10 79 − −
CLK Output Clock to 78K0/LG2 −Note 1 − EXCLK/X2/P122Note 2 13
/RESET Output Reset signal RESET 9 RESET 9
FLMD0 Output Mode signal FLMD0 12 FLMD0 12
VDD 17 VDD 17
LVDD 68 LVDD 68
VDD I/O
VDD voltage generation/
power monitoring
AVREF 80 AVREF 80
VSS 16 VSS 16
LVSS 67 LVSS 67
GND − Ground
AVSS 81 AVSS 81
Notes 1. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
2. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When
using the clock output of the dedicated flash programmer, pin connection varies depending on the type of
the dedicated flash programmer used.
• PG-FP4, FL-PR4: Connect CLK of the programmer to EXCLK/X2/P122 (pin 13).
• PG-FPL3, FP-LITE3: Connect CLK of the programmer to X1/P121 (pin 14), and connect its inverted
signal to X2/EXCLK/P122 (pin 13).
<R>
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
594
Examples of the recommended connection when using the adapter for flash memory writing are shown below.
Figure 27-3. Example of Wiring Adapter for Flash Memory Writing
in 3-Wire Serial I/O (CSI10) Mode (GC Package)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
WRITER INTERFACE
SI SO SCK CLK /RESET FLMD0
V
DD
(2.7 to 5.5 V)
GND
GND
VDD
VDD2
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 595
Figure 27-4. Example of Wiring Adapter for Flash Memory Writing
in UART (UART6) Mode (GC Package)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
WRITER INTERFACE
SI SO SCK /RESET FLMD0
V
DD
(2.7 to 5.5 V)
GND
GND
VDD
VDD2
CLK
Note
Note The above figure illustrates an example of wiring when using the clock output from the PG-FP4 or FL-PR4.
When using the clock output from the PG-FPL3 or FP-LITE3, connect CLK to X1/P121 (pin 11), and connect
its inverted signal to X2/EXCLK/P122 (pin 10).
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
596
Figure 27-5. Example of Wiring Adapter for Flash Memory Writing
in 3-Wire Serial I/O (CSI10) Mode (GF Package)
GND
VDD
VDD2
SI SO SCK CLK /RESET FLMD0
WRITER INTERFACE
V
DD
(2.7 to 5.5 V)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 597
Figure 27-6. Example of Wiring Adapter for Flash Memory Writing
in UART (UART6) Mode (GF Package)
GND
VDD
VDD2
SI SO SCK CLK /RESET FLMD0
WRITER INTERFACE
V
DD
(2.7 to 5.5 V)
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note
Note The above figure illustrates an example of wiring when using the clock output from the PG-FP4 or FL-PR4.
When using the clock output from the PG-FPL3 or FP-LITE3, connect CLK to X1/P121 (pin 14), and connect
its inverted signal to X2/EXCLK/P122 (pin 13).
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
598
27.4 Programming Environment
The environment required for writing a program to the flash memory of the 78K0/LG2 is illustrated below.
Figure 27-7. Environment for Writing Program to Flash Memory
RS-232C
USB
78K0/LG2
FLMD0
V
DD
V
SS
RESET
CSI10/UART6
Host machine
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STAT VE
A host machine that controls the dedicated flash programmer is necessary.
To interface between the dedicated flash programmer and the 78K0/LG2, CSI10 or UART6 is used for
manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA
series) is necessary.
27.5 Communication Mode
Communication between the dedicated flash programmer and the 78K0/LG2 is established by serial
communication via CSI10 or UART6 of the 78K0/LG2.
(1) CSI10
Transfer rate: 2.4 kHz to 2.5 MHz
Figure 27-8. Communication with Dedicated Flash Programmer (CSI10)
V
DD
/LV
DD
/AV
REF
V
SS
/LV
SS
/AV
SS
RESET
SO10
SI10
SCK10
FLMD0 FLMD0
V
DD
GND
/RESET
SI/RxD
SO/TxD
SCK
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
78K0/LG2
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 599
(2) UART6
Transfer rate: 115200 bps
Figure 27-9. Communication with Dedicated Flash Programmer (UART6)
V
DD
/LV
DD
/AV
REF
V
SS
/LV
SS
/AV
SS
RESET
TxD6
RxD6
V
DD
GND
/RESET
SI/RxD
SO/TxD
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
FLMD0 FLMD0
78K0/LG2
CLK
Note
EXCLK
Note
Note The above figure illustrates an example of wiring when using the clock output from the PG-FP4 or FL-PR4.
When using the clock output from the PG-FPL3 or FP-LITE3, connect CLK to X1/P121, and connect its
inverted signal to X2/EXCLK/P122.
X1CLK
X2
The dedicated flash programmer generates the following signals for the 78K0/LG2. For details, refer to the user’s
manual for the PG-FP4, FL-PR4, PG-FPL3, or FP-LITE3.
Table 27-5. Pin Connection
FlashPro4 78K0/LG2 Connection
Signal Name I/O Pin Function Pin Name CSI10 UART6
FLMD0 Output Mode signal FLMD0
VDD I/O VDD voltage generation/power monitoring VDD, LVDD, AVREF
GND − Ground VSS, LVSS, AVSS
CLK Output Clock output to 78K0/LG2 Note 1 ×Note 2 {Note 1
/RESET Output Reset signal RESET
SI/RxD Input Receive signal SO10/TxD6
SO/TxD Output Transmit signal SI10/RxD6
SCK Output Transfer clock SCK10 ×
Notes 1. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used. When
using the clock output of the dedicated flash programmer, pin connection varies depending on the type of
the dedicated flash programmer used.
• PG-FP4, FL-PR4: Connect CLK of the programmer to EXCLK/X2/P122.
• PG-FPL3, FP-LITE3: Connect CLK of the programmer to X1/P121, and connect its inverted signal to
X2/EXCLK/P122.
2. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
Remark : Be sure to connect the pin.
{: The pin does not have to be connected if the signal is generated on the target board.
×: The pin does not have to be connected.
<R>
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
600
27.6 Handling of Pins on Board
To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on
the target system. First provide a function that selects the normal operation mode or flash memory programming
mode on the board.
When the flash memory programming mode is set, all the pins not used for programming the flash memory are in
the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately
after reset, the pins must be handled as described below.
27.6.1 FLMD0 pin
In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the VDD
write voltage is supplied to the FLMD0 pin. An FLMD0 pin connection example is shown below.
Figure 27-10. FLMD0 Pin Connection Example
78K0/LG2
FLMD0
10 kΩ (recommended)
Dedicated flash programmer connection pin
27.6.2 Serial interface pins
The pins used by each serial interface are listed below.
Table 27-6. Pins Used by Each Serial Interface
Serial Interface Pins Used
CSI10 SO10, SI10, SCK10
UART6 TxD6, RxD6
To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on
the board, care must be exercised so that signals do not collide or that the other device does not malfunction.
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 601
(1) Signal collision
If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another
device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other
device, or make the other device go into an output high-impedance state.
Figure 27-11. Signal Collision (Input Pin of Serial Interface)
Input pin Signal collision
Dedicated flash programmer
connection pin
Other device
Output pin
In the flash memory programming mode, the signal output by the device
collides with the signal sent from the dedicated flash programmer.
Therefore, isolate the signal of the other device.
78K0/LG2
(2) Malfunction of other device
If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface
connected to another device (input), a signal may be output to the other device, causing the device to malfunction.
To avoid this malfunction, isolate the connection with the other device.
Figure 27-12. Malfunction of Other Device
Pin
Dedicated flash programmer
connection pin
Other device
Input pin
If the signal output by the 78K0/LG2 in the flash memory programming
mode affects the other device, isolate the signal of the other device.
Pin
Dedicated flash programmer
connection pin
Other device
Input pin
If the signal output by the dedicated flash programmer in the flash memory
programming mode affects the other device, isolate the signal of the other
device.
78K0/LG2
78K0/LG2
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
602
27.6.3 RESET pin
If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset
signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the
reset signal generator.
If the reset signal is input from the user system while the flash memory programming mode is set, the flash
memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash
programmer.
Figure 27-13. Signal Collision (RESET Pin)
RESET
Dedicated flash programmer
connection signal
Reset signal generator
Signal collision
Output pin
In the flash memory programming mode, the signal output by the reset
signal generator collides with the signal output by the dedicated flash
programmer. Therefore, isolate the signal of the reset signal generator.
78K0/LG2
27.6.4 Port pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the
same status as that immediately after reset. If external devices connected to the ports do not recognize the port
status immediately after reset, the port pin must be connected to VDD or VSS via a resistor.
27.6.5 REGC pin
Connect the REGC pin to GND via a capacitor (0.47 to 1
μ
F: recommended) in the same manner as during normal
operation.
27.6.6 Other signal pins
Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock.
To input the operating clock from the dedicated flash programmer, however, connect as follows.
• PG-FP4, FL-PR4: Connect CLK of the programmer to EXCLK/X2/P122.
• PG-FPL3, FP-LITE3: Connect CLK of the programmer and X1/P121, and connect its inverted signal to
X2/EXCLK/P122.
Cautions 1. Only the internal high-speed oscillation clock (fRH) can be used when CSI10 is used.
2. Only the X1 clock (fX) or external main system clock (fEXCLK) can be used when UART6 is used.
3. For products without an on-chip debug function and with the flash memory of 48 KB or more
(
μ
PD78F0394, 78F0395, 78F0396, and 78F0397) , and having a product rank of “I” or “E”, and
for the product with an on-chip debug function (
μ
PD78F0397D), connect P31/INTP2/OCD1ANote
and P121/X1/OCD0ANote as follows when writing the flash memory with a flash memory
programmer.
• P31/INTP2/OCD1ANote: Connect to VSS via a resistor (10 kΩ: recommended).
• P121/X1/OCD0ANote: When using this pin as a port, connect it to VSS via a resistor (10 kΩ:
recommended) (in the input mode) or leave it open (in the output
mode).
The above connection is not necessary when writing the flash memory by means of self
programming.
Note OCD0A and OCD1A are provided to the
μ
PD78F0397D only.
Remark For the product ranks, consult an NEC Electronics sales representative.
<R>
<R>
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 603
27.6.7 Power supply
To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash p
memory rogrammer, and the VSS pin to GND of the flash memory programmer.
To use the on-board supply voltage, connect in compliance with the normal operation mode.
However, be sure to connect the VDD and VSS pins to VDD and GND of the flash memory programmer to use the
power monitor function with the flash memory programmer, even when using the on-board supply voltage.
Supply the same other power supplies (LVDD, LVSS, AVREF, and AVSS) as those in the normal operation mode.
27.7 Programming Method
27.7.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash memory.
Figure 27-14. Flash Memory Manipulation Procedure
Start
Selecting communication mode
Manipulate flash memory
End?
Yes
FLMD0 pulse supply
No
End
Flash memory programming
mode is set
27.7.2 Flash memory programming mode
To rewrite the contents of the flash memory by using the dedicated flash programmer, set the 78K0/LG2 in the
flash memory programming mode. To set the mode, set the FLMD0 pin to VDD and clear the reset signal.
Change the mode by using a jumper when writing the flash memory on-board.
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
604
Figure 27-15. Flash Memory Programming Mode
VDD
RESET
5.5 V
0 V
VDD
0 V
Flash memory programming mode
FLMD0
FLMD0 pulse
VDD
0 V
Table 27-7. Relationship Between FLMD0 Pin and Operation Mode After Reset Release
FLMD0 Operation Mode
0 Normal operation mode
VDD Flash memory programming mode
27.7.3 Selecting communication mode
In the 78K0/LG2, a communication mode is selected by inputting pulses (up to 11 pulses) to the FLMD0 pin after
the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash
programmer.
The following table shows the relationship between the number of pulses and communication modes.
Table 27-8. Communication Modes
Standard SettingNote 1 Communication
Mode Port Speed Frequency Multiply Rate
Pins Used Peripheral
Clock
Number of
FLMD0
Pulses
UART-Ext-Osc fX 0 UART
(UART6) UART-Ext-FP4CK
115,200 bpsNote 3 2 to 20 MHzNote 2 TxD6, RxD6
fEXCLK 3
3-wire serial I/O
(CSI10)
CSI-Internal-OSC 2.4 kHz to
2.5 MHz
−
1.0
SO10, SI10,
SCK10
fRH 8
Notes 1. Selection items for Standard settings on FlashPro4.
2. The possible setting range differs depending on the voltage. For details, refer to the chapter of electrical
specifications.
3. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART
communication, thoroughly evaluate the slew as well as the baud rate error.
Caution When UART6 is selected, the receive clock is calculated based on the reset command sent from the
dedicated flash programmer after the FLMD0 pulse has been received.
Remark fX: X1 clock
f
EXCLK: External main system clock
fRH: Internal high-speed oscillation clock
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 605
27.7.4 Communication commands
The 78K0/LG2 communicates with the dedicated flash programmer by using commands. The signals sent from the
flash programmer to the 78K0/LG2 are called commands, and the signals sent from the 78K0/LG2 to the dedicated
flash programmer are called response.
Figure 27-16. Communication Commands
Command
Response command
78K0/LG2
Dedicated flash
programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXXXXXXXX
XXXX
XXXX YYYY
STATVE
The flash memory control commands of the 78K0/LG2 are listed in the table below. All these commands are
issued from the programmer and the 78K0/LG2 perform processing corresponding to the respective commands.
Table 27-9. Flash Memory Control Commands
Classification Command Name Function
Verify Verify Compares the contents of a specified area of the flash memory with
data transmitted from the programmer.
Chip Erase Erases the entire flash memory. Erase
Block Erase Erases a specified area in the flash memory.
Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly
erased.
Write Programming Writes data to a specified area in the flash memory.
Status Gets the current operating status (status data).
Silicon Signature Gets 78K0/Lx2 information (such as the part number and flash memory
configuration).
Version Get Gets the 78K0/Lx2 version and firmware version.
Getting information
Checksum Gets the checksum data for a specified area.
Security Security Set Sets security information.
Reset Used to detect synchronization status of communication. Others
Oscillating Frequency Set Specifies an oscillation frequency.
The 78K0/LG2 return a response for the command issued by the dedicated flash programmer. The response
names sent from the 78K0/LG2 are listed below.
Table 27-10. Response Names
Response Name Function
ACK Acknowledges command/data.
NAK Acknowledges illegal command/data.
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
606
27.8 Security Settings
The 78K0/LG2 supports a security function that prohibits rewriting the user program written to the internal flash
memory, so that the program cannot be changed by an unauthorized person.
The operations shown below can be performed using the security set command. The security setting is valid when
the programming mode is set next.
• Disabling batch erase (chip erase)
Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is
prohibited by this setting during on-board/off-board programming. Once execution of the batch erase (chip
erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can
no longer be cancelled.
Caution After the security setting for the batch erase is set, erasure cannot be performed for the device.
In addition, even if a write command is executed, data different from that which has already
been written to the flash memory cannot be written, because the erase command is disabled.
• Disabling block erase
Execution of the block erase command for a specific block in the flash memory is prohibited during on-board/off-
board programming. However, blocks can be erased by means of self programming.
• Disabling write
Execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on-
board/off-board programming. However, blocks can be written by means of self programming.
• Disabling rewriting boot cluster 0
Execution of the batch erase (chip erase) command, block erase command, and write command on boot cluster
0 (0000H to 0FFFH) in the flash memory is prohibited by this setting.
Caution If a security setting that rewrites boot cluster 0 has been applied, boot cluster 0 of that device
will not be rewritten.
The batch erase (chip erase), block erase, write commands, and rewriting boot cluster 0 are enabled by the default
setting when the flash memory is shipped. Security can be set by on-board/off-board programming and self
programming. Each security setting can be used in combination.
Prohibition of erasing blocks and writing is cleared by executing the batch erase (chip erase) command.
Table 27-11 shows the relationship between the erase and write commands when the 78K0/LG2 security function
is enabled.
<R>
<R>
<R>
<R>
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 607
Table 27-11. Relationship Between Enabling Security Function and Command
(1) During on-board/off-board programming
Executed Command Valid Security
Batch Erase (Chip
Erase)
Block Erase Write
Prohibition of batch erase (chip erase) Cannot be erased in
batch
Can be performedNote.
Prohibition of block erase Can be performed.
Prohibition of writing
Can be erased in batch.
Blocks cannot be
erased.
Cannot be performed.
Prohibition of rewriting boot cluster 0 Cannot be erased in
batch
Boot cluster 0 cannot
be erased.
Boot cluster 0 cannot
be written.
Note Confirm that no data has been written to the write area. Because data cannot be erased after batch erase
(chip erase) is prohibited, do not write data if the data has not been erased.
(2) During self programming
Executed Command Valid Security
Block Erase Write
Prohibition of batch erase (chip erase)
Prohibition of block erase
Prohibition of writing
Blocks can be erased. Can be performed.
Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written.
Table 27-12 shows how to perform security settings in each programming mode.
Table 27-12. Setting Security in Each Programming Mode
(1) On-board/off-board programming
Security Security Setting How to Disable Security Setting
Prohibition of batch erase (chip
erase)
Cannot be disabled after set.
Prohibition of block erase
Prohibition of writing
Execute batch erase (chip erase)
command
Prohibition of rewriting boot cluster 0
Set via GUI of dedicated flash
programmer, etc.
Cannot be disabled after set.
(2) Self programming
Security Security Setting How to Disable Security Setting
Prohibition of batch erase (chip
erase)
Cannot be disabled after set.
Prohibition of block erase
Prohibition of writing
Execute batch erase (chip erase)
command during on-board/off-board
programming (cannot be disabled during
self programming)
Prohibition of rewriting boot cluster 0
Set by using information library.
Cannot be disabled after set.
<R>
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
608
27.9 Processing Time for Each Command When PG-FP4 Is Used (Reference)
The following table shows the processing time for each command (reference) when the PG-FP4 is used as a
dedicated flash memory programmer.
Table 27-13. Processing Time for Each Command When PG-FP4 Is Used (Reference) (1/2)
(1)
μ
PD78F0397, 78F0397D (internal ROM capacity: 128 KB)
Port: UART-ch0, Speed: 115,200 bps
Port: SIO-ch0,
Speed: 2.5 MHz Frequency: 2.0 MHz Frequency: 20 MHz
Command of
PG-FP4
Internal High-Speed
Oscillation clock
(fRH = 8 MHz) (TYP.))
X1 Clock (fX) External Main
System Clock
(fEXCLK)
X1 Clock (fX) External Main
System Clock
(fEXCLK)
Signature 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
Blankcheck 1 s (TYP.) 1 s (TYP.) 1 s (TYP.) 1 s (TYP.) 1 s (TYP.)
Erase 1.5 s (TYP.) 1 s (TYP.) 1.5 s (TYP.) 1 s (TYP.) 1.5 s (TYP.)
Program 9.5 s (TYP.) 18 s (TYP.) 18 s (TYP.) 18 s (TYP.) 18 s (TYP.)
Verify 4.5 s (TYP.) 13.5 s (TYP.) 13.5 s (TYP.) 13.5 s (TYP.) 13.5 s (TYP.)
E.P.V 11 s (TYP.) 19.5 s (TYP.) 19.5 s (TYP.) 19.5 s (TYP.) 19.5 s (TYP.)
Checksum 1 s (TYP.) 1 s (TYP.) 1 s (TYP.) 1 s (TYP.) 1 s (TYP.)
Security 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
(2)
μ
PD78F0395 (internal ROM capacity: 60 KB)
Port: UART-Ext-FP4CK (External main system clock (fEXCLK)),
Speed: 115,200 bps
Command of
PG-FP4
Port: CSI-Internal-OSC
(Internal high-speed
oscillation clock (fRH)),
Speed: 2.5 MHz Frequency: 2.0 MHz Frequency: 20 MHz
Signature 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
Blankcheck 1 s (TYP.) 1 s (TYP.) 1 s (TYP.)
Erase 1.5 s (TYP.) 1 s (TYP.) 1 s (TYP.)
Program 5 s (TYP.) 9 s (TYP.) 9 s (TYP.)
Verify 2 s (TYP.) 6.5 s (TYP.) 6.5 s (TYP.)
E.P.V 6 s (TYP.) 10.5 s (TYP.) 10.5 s (TYP.)
Checksum 0.5 s (TYP.) 1 s (TYP.) 1 s (TYP.)
Security 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 609
Table 27-13. Processing Time for Each Command When PG-FP4 Is Used (Reference) (2/2)
(3)
μ
PD78F0393 (internal ROM capacity: 32 KB)
Port: UART-Ext-FP4CK (External main system clock (fEXCLK)),
Speed: 115,200 bps
Command of
PG-FP4
Port: CSI-Internal-OSC
(Internal high-speed
oscillation clock (fRH)),
Speed: 2.5 MHz Frequency: 2.0 MHz Frequency: 20 MHz
Signature 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
Blankcheck 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
Erase 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
Program 2.5 s (TYP.) 5 s (TYP.) 5 s (TYP.)
Verify 1.5 s (TYP.) 4 s (TYP.) 3.5 s (TYP.)
E.P.V 3.5 s (TYP.) 6 s (TYP.) 6 s (TYP.)
Checksum 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
Security 0.5 s (TYP.) 0.5 s (TYP.) 0.5 s (TYP.)
27.10 Flash Memory Programming by Self-Writing
The 78K0/LG2 supports a self-programming function that can be used to rewrite the flash memory via a user
program. Because this function allows a user application to rewrite the flash memory by using the 78K0/Kx2 self-
programming sample library, it can be used to upgrade the program in the field.
If an interrupt occurs during self-programming, self-programming can be temporarily stopped and interrupt
servicing can be executed. To execute interrupt servicing, restore the normal operation mode after self-programming
has been stopped, and execute the EI instruction. After the self-programming mode is later restored, self-
programming can be resumed.
Remark For details of the self-programming function and the 78K0/Kx2 self-programming library, refer to
78K0/Kx2 Flash Memory Self Programming User’s Manual (U17516E).
Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem
clock.
2. Input a high level to the FLMD0 pin during self-programming.
3. Be sure to execute the DI instruction before starting self-programming.
The self-programming function checks the interrupt request flags (IF0L, IF0H, IF1L, and IF1H).
If an interrupt request is generated, self-programming is stopped.
4. Self-programming is also stopped by an interrupt request that is not masked even in the DI
status. To prevent this, mask the interrupt by using the interrupt mask flag registers (MK0L,
MK0H, MK1L, and MK1H).
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
610
Cautions 5. Allocate the entry program for self-programming in the common area of 0000H to 7FFFH.
Figure 27-17. Operation Mode and Memory Map for Self-Programming (
μ
PD78F0397)
Memory bank 1
Memory bank 4
Memory bank 3
Memory bank 5
Memory bank 2
Normal mode
Flash memory
(common area)
0000H
8000H
7FFFH
FFFFH
FB00H
FAFFH
C000H
BFFFH
F800H
F7FFH
E000H
DFFFH
FF00H
FEFFH
Internal high-
speed RAM
Internal
expansion RAM
SFR
Reserved
Reserved
Flash memory
control
firmware ROM
Disable
accessing
Flash memory
(memory bank 0)
Memory bank 1
Memory bank 4
Memory bank 3
Memory bank 5
Memory bank 2
Self-programming mode
Flash memory
(common area)
0000H
8000H
7FFFH
FFFFH
FB00H
FAFFH
C000H
BFFFH
F800H
F7FFH
E000H
DFFFH
FF00H
FEFFH
Internal high-
speed RAM
Internal
expansion RAM
SFR
Reserved
Reserved
Flash memory
control
firmware ROM
Disable
accessing
Enable
accessing
Instructions can be fetched
from common area and
selected memory bank.
Instructions can be
fetched from common
area and firmware ROM.
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 611
The procedure of self-programming is illustrated below.
Figure 27-18. Flow of Self Programming (Rewriting Flash Memory)
Start of self programming
FlashStart
FLMD0 pin
Low level
→
High level
Normal completion?
Yes
No
Setting operating environment
FlashEnv
CheckFLMD
FlashBlockBlankCheck
Erased?
Yes
Yes
No
FlashBlockErase
Normal completion?
FlashWordWrite
Normal completion?
FlashBlockVerify
Normal completion?
FlashEnd
FLMD0 pin
High level
→
Low level
End of self programming
Yes
Yes
No
No
No
Remark For details of the self programming sample library, refer to 78K0/Kx2 Flash Memory Self
Programming User’s Manual (U17516E).
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
612
The following table shows the processing time and interrupt response time for the self programming sample library.
Table 27-14. Processing Time and Interrupt Response Time for Self Programming Sample Library (1/4)
(1) When internal high-speed oscillation clock is used and entry RAM is located outside short direct
addressing range
Processing Time (
μ
s)
Normal Model of C Compiler Static Model of
C Compiler/Assembler
Interrupt Response Time (
μ
s)Library Name
Min. Max. Min. Max. Min. Max.
Self programming start library 4.25 − −
Initialize library 977.75 − −
Mode check library 753.875 753.125 − −
Block blank check library 12770.875 12765.875 391.25 1300.5
Block erase library 36909.5 356318 36904.5 356296.25 389.25 1393.5
Word write library 1214
(1214.375)
2409
(2409.375)
1207
(1207.375)
2402
(2402.375)
394.75 1289.5
Program verify library 25618.875 25613.875 390.25 1324.5
Self programming end library 4.25 − −
Get information library
(option value: 03H)
871.25
(871.375)
866
(866.125)
− −
Get information library
(option value: 04H)
863.375
(863.5)
858.125
(858.25)
− −
Get information library
(option value: 05H)
1024.75
(1043.625)
1037.5
(1038.375)
− −
Set information library 105524.75 790809.375 105523.75 790808.375 387 852.5
EEPROM write library 1496.5
(1496.875)
2691.5
(2691.875)
1489.5
(1489.875)
2684.5
(2684.875)
399.75 1395.5
Remark The value in the parentheses indicates the value when a write start address structure is located at a
place other than the internal high-speed RAM.
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 613
Table 27-14. Processing Time and Interrupt Response Time for Self Programming Sample Library (2/4)
(2) When internal high-speed oscillation clock is used and entry RAM is located in short direct addressing
range (FE20H)
Processing Time (
μ
s)
Normal Model of C Compiler Static Model of
C Compiler/Assembler
Interrupt Response Time (
μ
s)Library Name
Min. Max. Min. Max. Min. Max.
Self programming start library 4.25 − −
Initialize library 443.5 − −
Mode check library 219.625 218.875 − (
Block blank check library 12236.625 12231.625 81.25 727.5
Block erase library 36363.25 355771.75 36358.25 355750 79.25 820.5
Word write library 679.75
(680.125)
1874.75
(1875.125)
672.75
(673.125)
1867.75
(1868.125)
84.75 716.5
Program verify library 25072.625 25067.625 80.25 751.5
Self programming end library 4.25 ( (
Get information library
(option value: 03H)
337
(337.125)
331.75
(331.875)
( (
Get information library
(option value: 04H)
329.125
(239.25)
323.875
(324)
( (
Get information library
(option value: 05H)
502.25
(503.125)
497
(497.875)
( (
Set information library 104978.5 541143.125 104977.5 541142.125 77 279.5
EEPROM write library 962.25
(962.625)
2157.25
(2157.625)
955.25
(955.625)
2150.25
(2150.625)
89.75 822.5
Remark The value in the parentheses indicates the value when a write start address structure is located at a
place other than the internal high-speed RAM.
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
614
Table 27-14. Processing Time and Interrupt Response Time for Self Programming Sample Library (3/4)
(3) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located
outside short direct addressing range
Processing Time (
μ
s)
Normal Model of C Compiler Static Model of C
Compiler/Assembler
Interrupt Response Time (
μ
s)Library Name
Min. Max. Min. Max. Min. Max.
Self programming start library 34/fXH − −
Initialize library 49/fXH + 485.8125 − −
Mode check library 35/fXH + 374.75 29/fXH + 374.75 − −
Block blank check library 174/fXH + 6382.0625 134/fXH + 6382.0625 18/fXH + 192 28/fXH + 698
Block erase library 174/fXH +
31093.875
174/fXH +
298948.125
134/fXH +
31093.875
134/fXH +
298948.125
18/fXH + 186 28/fXH + 745
Word write library 318 (321)/fXH
+ 644.125
318 (321)/fXH
+ 1491.625
262 (265)/fXH
+ 644.125
262 (265)/fXH
+ 1491.625
22/fXH + 189 28/fXH + 693
Program verify library 174/fXH + 13448.5625 134/fXH + 13448.5625 18/fXH + 192 28/fXH + 709
Self programming end library 34/fXH − −
Get information library
(option value: 03H)
171 (172)/fXH + 432.4375 129 (130)/fXH + 432.4375 − −
Get information library
(option value: 04H)
181 (182)/fXH + 427.875 139 (140)/fXH + 427.875 − −
Get information library
(option value: 05H)
404 (411)/fXH + 496.125 362 (369)/fXH + 496.125 − −
Set information library 75/fXH +
79157.6875
75/fXH +
652400
67/fXH +
79157.6875
67/fXH +
652400
16/fXH + 190 28/fXH + 454
EEPROM write library 318 (321)/fXH
+ 799.875
318 (321)/fXH
+ 1647.375
262 (265)/fXH
+ 799.875
262 (265)/fXH
+ 1647.375
22/fXH + 191 28/fXH + 783
Remarks 1. The value in the parentheses indicates the value when a write start address structure is located at a
place other than the internal high-speed RAM.
2. f
XH: High-speed system clock frequency
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 615
Table 27-14. Processing Time and Interrupt Response Time for Self Programming Sample Library (4/4)
(4) When high-speed system clock (X1 oscillation or external clock input) is used and entry RAM is located
in short direct addressing range (FE20H)
Processing Time (
μ
s)
Normal Model of C Compiler Static Model of
C Compiler/Assembler
Interrupt Response Time (
μ
s)Library Name
Min. Max. Min. Max. Min. Max.
Self programming start library 34/fXH − −
Initialize library 49/fXH + 224.6875 − −
Mode check library 35/fXH + 113.625 29/fXH + 113.625 − −
Block blank check library 174/fXH + 6120.9375 134/fXH + 6120.9375 18/fXH + 55 28/fXH + 462
Block erase library 174/fXH +
30820.75
174/fXH +
298675
134/fXH +
30820.75
134/fXH +
298675
18/fXH + 49 28/fXH + 509
Word write library 318 (321)/fXH
+ 383
318 (321)/fXH
+ 1230.5
262 (265)/fXH
+ 383
262 (265)/fXH
+ 1230.5
22/fXH + 52 28/fXH + 457
Program verify library 174/fXH + 13175.4375 134/fXH + 13175.4375 18/fXH + 55 28/fXH + 473
Self programming end library 34/fXH − −
Get information library
(option value: 03H)
171 (172)/fXH + 171.3125 129 (130)/fXH + 171.3125 − −
Get information library
(option value: 04H)
181 (182)/fXH + 166.75 139 (140)/fXH + 166.75 − −
Get information library
(option value: 05H)
404 (411)/fXH + 231.875 362 (369)/fXH + 231.875 − −
Set information library 75/fXH +
78884.5625
75/fXH +
527566.875
67/fXH +
78884.5625
67/fXH +
527566.875
16/fXH +53 28/fXH +218
EEPROM write library 318 (321)/fXH
+ 538.75
318 (321)/fXH
+ 1386.25
262 (265)/fXH
+ 538.75
262 (265)/fXH
+ 1386.25
22/fXH +54 28/fXH +547
Remarks 1. The value in the parentheses indicates the value when a write start address structure is located at a
place other than the internal high-speed RAM.
2. f
XH: High-speed system clock frequency
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD
616
27.10.1 Boot swap function
If rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data
in the boot area may be lost and the program may not be restarted by resetting.
The boot swap function is used to avoid this problem.
Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to
boot cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and
boot cluster 0 by using the set information function of the firmware of the 78K0/LG2, so that boot cluster 1 is used as a
boot area. After that, erase or write the original boot program area, boot cluster 0.
As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is
executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next.
If the program has been correctly written to boot cluster 0, restore the original boot area by using the set
information function of the firmware of the 78K0/LG2.
Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function.
Boot cluster 0 (0000H to 0FFFH): Original boot program area
Boot cluster 1 (1000H to 1FFFH): Area subject to boot swap function
Figure 27-19. Boot Swap Function
Boot program
(boot cluster 0)
New boot program
(boot cluster 1)
User program Self-programming
to boot cluster 1
Self-programming
to boot cluster 0
Execution of boot
swap by firmware
Execution of boot
swap by firmware
User program
Boot program
(boot cluster 0)
User program
New boot program
(boot cluster 1)
New boot program
(boot cluster 0)
User program
New boot program
(boot cluster 1)
New boot program
(boot cluster 0)
User program
New boot program
(boot cluster 1)
Boot program
(boot cluster 0)
User program
XXXXH
XXXXH
2000H
0000H
1000H
2000H
0000H
1000H
Boot Boot
Boot
Boot
Boot
<R>
CHAPTER 27 FLASH MEMORY
User’s Manual U17473EJ2V0UD 617
Figure 27-20. Example of Executing Boot Swapping
Boot
cluster 1
Booted by boot cluster 0
Booted by boot cluster 1
Booted by boot cluster 0
Block number
Erasing block 4
Boot
cluster 0
Program
Program
Boot program
1000H
0000H
1000H
0000H
0000H
1000H
Erasing block 5
Writing blocks 5 to 7 Boot swap
Boot swap canceled
3
2
1
0
7
6
5
4
Boot program
Boot program
Boot program
Program
Program
Program
Program
Boot program
3
2
1
0
7
6
5
4
Boot program
Boot program
Boot program
Program
Program
Boot program
3
2
1
0
7
6
5
4
Boot program
Boot program
Boot program
Program
Erasing block 6 Erasing block 7
Program
Boot program
3
2
1
0
7
6
5
4
Boot program
Boot program
Boot program
Boot program
3
2
1
0
7
6
5
4
Boot program
Boot program
Boot program
Boot program
3
2
1
0
7
6
5
4
Boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
Boot program
3
2
1
0
7
6
5
4
Boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
Erasing block 0 Erasing block 1
Erasing block 2 Erasing block 3
3
2
1
0
7
6
5
4
Boot program
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
3
2
1
0
7
6
5
4
Boot program
Boot program
New boot program
New boot program
New boot program
New boot program
3
2
1
0
7
6
5
4
Boot program
New boot program
New boot program
New boot program
New boot program
3
2
1
0
7
6
5
4
New boot program
New boot program
New boot program
New boot program
Writing blocks 0 to 3
3
2
1
0
7
6
5
4
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
3
2
1
0
7
6
5
4
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
New boot program
User’s Manual U17473EJ2V0UD
618
CHAPTER 28 ON-CHIP DEBUG FUNCTION (
μ
PD78F0397D ONLY)
28.1 Connecting QB-78K0MINI to
μ
PD78F0397D
The
μ
PD78F0397D uses the VDD, FLMD0, RESET, OCD0A/X1 (or OCD1A/P31), OCD0B/X2 (or OCD1B/P32), and
VSS pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI). Whether OCD0A/X1
and OCD1A/P31, or OCD0B/X2 and OCD1B/P32 are used can be selected.
Caution The
μ
PD78F0397D has an on-chip debug function. Do not use this product for mass production
because its reliability cannot be guaranteed after the on-chip debug function has been used,
given the issue of the number of times the flash memory can be rewritten. NEC Electronics does
not accept complaints concerning this product.
Figure 28-1. Connection Example of QB-78K0MINI and
μ
PD78F0397D
(When OCD0A/X1 and OCD0B/X2 Are Used)
V
DD
PD78F0397D
P31
FLMD0
OCD0A/X1
OCD0B/X2
Target reset
RESET_IN
X2
X1
FLMD0
RESET
V
DD
RESET_OUT
GND
QB-78K0MINI target connector
GND
Note
Note
μ
Note Make pull-down resistor 470 Ω or more (10 kΩ: recommended).
Cautions 1. Input the clock from the OCD0A/X1 pin during on-chip debugging.
2. Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the OCD1A/P31 pin.
<R>
CHAPTER 28 ON-CHIP DEBUG FUNCTION (
μ
PD78F0397D ONLY)
User’s Manual U17473EJ2V0UD 619
Figure 28-2. Connection Example of QB-78K0MINI and
μ
PD78F0397D
(When OCD1A and OCD1B Are Used)
QB-78K0MINI target connector
V
DD
OCD1B/P32
FLMD0
OCD1A/P31
X2
Target reset
RESET_IN
X2
X1
FLMD0
RESET
V
DD
RESET_OUT
GND
X1
GND
Note
Note
PD78F0397D
μ
Note Make pull-down resistor 470 Ω or more (10 kΩ: recommended).
Connect the FLMD0 pin as follows when performing self programming by means of on-chip debugging.
Figure 28-3. Connection of FLMD0 Pin for Self Programming by Means of On-Chip Debugging
QB-78K0MINI target connector
FLMD0 FLMD0
PD78F0397D
Port
1 k
Ω
(recommended)
10 k
Ω
(recommended)
μ
CHAPTER 28 ON-CHIP DEBUG FUNCTION (
μ
PD78F0397D ONLY)
User’s Manual U17473EJ2V0UD
620
28.2 On-Chip Debug Security ID
The
μ
PD78F0397D has an on-chip debug operation control flag in the flash memory at 0084H (see CHAPTER 26
OPTION BYTE) and an on-chip debug security ID setting area at 0085H to 008EH.
When the boot swap function is used, also set a value that is the same as that of 1084H and 1085H to 108EH in
advance, because 0084H, 0085H to 008EH and 1084H, and 1085H to 108EH are switched.
For details on the on-chip debug security ID, refer to the QB-78K0MINI User’s Manual (U17029E).
Table 28-1. On-Chip Debug Security ID
Address On-Chip Debug Security ID
0085H to 008EH
1085H to 108EH
Any ID code of 10 bytes
User’s Manual U17473EJ2V0UD 621
CHAPTER 29 INSTRUCTION SET
This chapter lists each instruction set of the 78K0/LG2 in table form. For details of each operation and operation
code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E).
29.1 Conventions Used in Operation List
29.1.1 Operand identifiers and specification methods
Operands are written in the “Operand” column of each instruction in accordance with the specification method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as
they are. Each symbol has the following meaning.
• #: Immediate data specification
• !: Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
write the #, !, $, and [ ] symbols.
For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for specification.
Table 29-1. Operand Identifiers and Specification Methods
Identifier Specification Method
r
rp
sfr
sfrp
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbolNote
Special function register symbol (16-bit manipulatable register even addresses only)Note
saddr
saddrp
FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even address only)
addr16
addr11
addr5
0000H to FFFFH Immediate data or labels
(Only even addresses for 16-bit data transfer instructions)
0800H to 0FFFH Immediate data or labels
0040H to 007FH Immediate data or labels (even address only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RBn RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark For special function register symbols, see Table 3-7 Special Function Register List.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD
622
29.1.2 Description of operation column
A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carry flag
Z: Zero flag
RBS: Register bank select flag
IE: Interrupt request enable flag
( ): Memory contents indicated by address or register contents in parentheses
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
∧: Logical product (AND)
∨: Logical sum (OR)
∨: Exclusive logical sum (exclusive OR)
⎯⎯: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
29.1.3 Description of flag operation column
(Blank): Not affected
0: Cleared to 0
1: Set to 1
×: Set/cleared according to the result
R: Previously saved value is restored
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD 623
29.2 Operation List
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Operation ZACCY
r, #byte 2 4 − r ← byte
saddr, #byte 3 6 7 (saddr) ← byte
sfr, #byte 3 − 7 sfr ← byte
A, r Note 3 1 2 − A ← r
r, A Note 3 1 2 − r ← A
A, saddr 2 4 5 A ← (saddr)
saddr, A 2 4 5 (saddr) ← A
A, sfr 2 − 5 A ← sfr
sfr, A 2 − 5 sfr ← A
A, !addr16 3 8 9 A ← (addr16)
!addr16, A 3 8 9 (addr16) ← A
PSW, #byte 3 − 7 PSW ← byte × × ×
A, PSW 2 − 5 A ← PSW
PSW, A 2 − 5 PSW ← A × × ×
A, [DE] 1 4 5 A ← (DE)
[DE], A 1 4 5 (DE) ← A
A, [HL] 1 4 5 A ← (HL)
[HL], A 1 4 5 (HL) ← A
A, [HL + byte] 2 8 9 A ← (HL + byte)
[HL + byte], A 2 8 9 (HL + byte) ← A
A, [HL + B] 1 6 7 A ← (HL + B)
[HL + B], A 1 6 7 (HL + B) ← A
A, [HL + C] 1 6 7 A ← (HL + C)
MOV
[HL + C], A 1 6 7 (HL + C) ← A
A, r Note 3 1 2 − A ↔ r
A, saddr 2 4 6 A ↔ (saddr)
A, sfr 2 − 6 A ↔ (sfr)
A, !addr16 3 8 10 A ↔ (addr16)
A, [DE] 1 4 6 A ↔ (DE)
A, [HL] 1 4 6 A ↔ (HL)
A, [HL + byte] 2 8 10 A ↔ (HL + byte)
A, [HL + B] 2 8 10 A ↔ (HL + B)
8-bit data
transfer
XCH
A, [HL + C] 2 8 10 A ↔ (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD
624
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Operation ZACCY
rp, #word 3 6 − rp ← word
saddrp, #word 4 8 10 (saddrp) ← word
sfrp, #word 4 − 10 sfrp ← word
AX, saddrp 2 6 8 AX ← (saddrp)
saddrp, AX 2 6 8 (saddrp) ← AX
AX, sfrp 2 − 8 AX ← sfrp
sfrp, AX 2 − 8 sfrp ← AX
AX, rp Note 3 1 4 − AX ← rp
rp, AX Note 3 1 4 − rp ← AX
AX, !addr16 3 10 12 AX ← (addr16)
MOVW
!addr16, AX 3 10 12 (addr16) ← AX
16-bit data
transfer
XCHW AX, rp Note 3 1 4 − AX ↔ rp
A, #byte 2 4 − A, CY ← A + byte × × ×
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte × × ×
A, r Note 4 2 4 − A, CY ← A + r × × ×
r, A 2 4 − r, CY ← r + A × × ×
A, saddr 2 4 5 A, CY ← A + (saddr) × × ×
A, !addr16 3 8 9 A, CY ← A + (addr16) × × ×
A, [HL] 1 4 5 A, CY ← A + (HL) × × ×
A, [HL + byte] 2 8 9 A, CY ← A + (HL + byte) × × ×
A, [HL + B] 2 8 9 A, CY ← A + (HL + B) × × ×
ADD
A, [HL + C] 2 8 9 A, CY ← A + (HL + C) × × ×
A, #byte 2 4 − A, CY ← A + byte + CY × × ×
saddr, #byte 3 6 8 (saddr), CY ← (saddr) + byte + CY × × ×
A, r Note 4 2 4 − A, CY ← A + r + CY × × ×
r, A 2 4 − r, CY ← r + A + CY × × ×
A, saddr 2 4 5 A, CY ← A + (saddr) + CY × × ×
A, !addr16 3 8 9 A, CY ← A + (addr16) + C × × ×
A, [HL] 1 4 5 A, CY ← A + (HL) + CY × × ×
A, [HL + byte] 2 8 9 A, CY ← A + (HL + byte) + CY × × ×
A, [HL + B] 2 8 9 A, CY ← A + (HL + B) + CY × × ×
8-bit
operation
ADDC
A, [HL + C] 2 8 9 A, CY ← A + (HL + C) + CY × × ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD 625
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Operation ZACCY
A, #byte 2 4 − A, CY ← A − byte × × ×
saddr, #byte 3 6 8 (saddr), CY ← (saddr) − byte × × ×
A, r Note 3 2 4 − A, CY ← A − r × × ×
r, A 2 4 − r, CY ← r − A × × ×
A, saddr 2 4 5 A, CY ← A − (saddr) × × ×
A, !addr16 3 8 9 A, CY ← A − (addr16) × × ×
A, [HL] 1 4 5 A, CY ← A − (HL) × × ×
A, [HL + byte] 2 8 9 A, CY ← A − (HL + byte) × × ×
A, [HL + B] 2 8 9 A, CY ← A − (HL + B) × × ×
SUB
A, [HL + C] 2 8 9 A, CY ← A − (HL + C) × × ×
A, #byte 2 4 − A, CY ← A − byte − CY × × ×
saddr, #byte 3 6 8 (saddr), CY ← (saddr) − byte − CY × × ×
A, r Note 3 2 4 − A, CY ← A − r − CY × × ×
r, A 2 4 − r, CY ← r − A − CY × × ×
A, saddr 2 4 5 A, CY ← A − (saddr) − CY × × ×
A, !addr16 3 8 9 A, CY ← A − (addr16) − CY × × ×
A, [HL] 1 4 5 A, CY ← A − (HL) − CY × × ×
A, [HL + byte] 2 8 9 A, CY ← A − (HL + byte) − CY × × ×
A, [HL + B] 2 8 9 A, CY ← A − (HL + B) − CY × × ×
SUBC
A, [HL + C] 2 8 9 A, CY ← A − (HL + C) − CY × × ×
A, #byte 2 4 − A ← A ∧ byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) ∧ byte ×
A, r Note 3 2 4 − A ← A ∧ r ×
r, A 2 4 − r ← r ∧ A ×
A, saddr 2 4 5 A ← A ∧ (saddr) ×
A, !addr16 3 8 9 A ← A ∧ (addr16) ×
A, [HL] 1 4 5 A ← A ∧ (HL) ×
A, [HL + byte] 2 8 9 A ← A ∧ (HL + byte) ×
A, [HL + B] 2 8 9 A ← A ∧ (HL + B) ×
8-bit
operation
AND
A, [HL + C] 2 8 9 A ← A ∧ (HL + C) ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD
626
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Operation ZACCY
A, #byte 2 4 − A ← A ∨ byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) ∨ byte ×
A, r Note 3 2 4 − A ← A ∨ r ×
r, A 2 4 − r ← r ∨ A ×
A, saddr 2 4 5 A ← A ∨ (saddr) ×
A, !addr16 3 8 9 A ← A ∨ (addr16) ×
A, [HL] 1 4 5 A ← A ∨ (HL) ×
A, [HL + byte] 2 8 9 A ← A ∨ (HL + byte) ×
A, [HL + B] 2 8 9 A ← A ∨ (HL + B) ×
OR
A, [HL + C] 2 8 9 A ← A ∨ (HL + C) ×
A, #byte 2 4 − A ← A ∨ byte ×
saddr, #byte 3 6 8 (saddr) ← (saddr) ∨ byte ×
A, r Note 3 2 4 − A ← A ∨ r ×
r, A 2 4 − r ← r ∨ A ×
A, saddr 2 4 5 A ← A ∨ (saddr) ×
A, !addr16 3 8 9 A ← A ∨ (addr16) ×
A, [HL] 1 4 5 A ← A ∨ (HL) ×
A, [HL + byte] 2 8 9 A ← A ∨ (HL + byte) ×
A, [HL + B] 2 8 9 A ← A ∨ (HL + B) ×
XOR
A, [HL + C] 2 8 9 A ← A ∨ (HL + C) ×
A, #byte 2 4 − A − byte × × ×
saddr, #byte 3 6 8 (saddr) − byte × × ×
A, r Note 3 2 4 − A − r × × ×
r, A 2 4 − r − A × × ×
A, saddr 2 4 5 A − (saddr) × × ×
A, !addr16 3 8 9 A − (addr16) × × ×
A, [HL] 1 4 5 A − (HL) × × ×
A, [HL + byte] 2 8 9 A − (HL + byte) × × ×
A, [HL + B] 2 8 9 A − (HL + B) × × ×
8-bit
operation
CMP
A, [HL + C] 2 8 9 A − (HL + C) × × ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD 627
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Operation ZACCY
ADDW AX, #word 3 6 − AX, CY ← AX + word × × ×
SUBW AX, #word 3 6 − AX, CY ← AX − word × × ×
16-bit
operation
CMPW AX, #word 3 6 − AX − word × × ×
MULU X 2 16
− AX ← A × X Multiply/
divide DIVUW C 2 25
− AX (Quotient), C (Remainder) ← AX ÷ C
r 1 2
− r ← r + 1 × × INC
saddr 2 4 6 (saddr) ← (saddr) + 1 × ×
r 1 2
− r ← r − 1 × × DEC
saddr 2 4 6 (saddr) ← (saddr) − 1 × ×
INCW rp 1 4
− rp ← rp + 1
Increment/
decrement
DECW rp 1 4
− rp ← rp − 1
ROR A, 1 1 2 − (CY, A7 ← A0, Am − 1 ← Am) × 1 time ×
ROL A, 1 1 2 − (CY, A0 ← A7, Am + 1 ← Am) × 1 time ×
RORC A, 1 1 2 − (CY ← A0, A7 ← CY, Am − 1 ← Am) × 1 time ×
ROLC A, 1 1 2 − (CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time ×
ROR4 [HL] 2 10 12 A3 − 0 ← (HL)3 − 0, (HL)7 − 4 ← A3 − 0,
(HL)3 − 0 ← (HL)7 − 4
Rotate
ROL4 [HL] 2 10 12 A3 − 0 ← (HL)7 − 4, (HL)3 − 0 ← A3 − 0,
(HL)7 − 4 ← (HL)3 − 0
ADJBA 2 4
− Decimal Adjust Accumulator after Addition × × ×
BCD
adjustment ADJBS 2 4
− Decimal Adjust Accumulator after Subtract × × ×
CY, saddr.bit 3 6 7 CY ← (saddr.bit) ×
CY, sfr.bit 3 − 7 CY ← sfr.bit ×
CY, A.bit 2 4 − CY ← A.bit ×
CY, PSW.bit 3 − 7 CY ← PSW.bit ×
CY, [HL].bit 2 6 7 CY ← (HL).bit ×
saddr.bit, CY 3 6 8 (saddr.bit) ← CY
sfr.bit, CY 3 − 8 sfr.bit ← CY
A.bit, CY 2 4 − A.bit ← CY
PSW.bit, CY 3 − 8 PSW.bit ← CY × ×
Bit
manipulate
MOV1
[HL].bit, CY 2 6 8 (HL).bit ← CY
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD
628
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Operation ZACCY
CY, saddr.bit 3 6 7 CY ← CY ∧ (saddr.bit) ×
CY, sfr.bit 3 − 7 CY ← CY ∧ sfr.bit ×
CY, A.bit 2 4 − CY ← CY ∧ A.bit ×
CY, PSW.bit 3 − 7 CY ← CY ∧ PSW.bit ×
AND1
CY, [HL].bit 2 6 7 CY ← CY ∧ (HL).bit ×
CY, saddr.bit 3 6 7 CY ← CY ∨ (saddr.bit) ×
CY, sfr.bit 3 − 7 CY ← CY ∨ sfr.bit ×
CY, A.bit 2 4 − CY ← CY ∨ A.bit ×
CY, PSW.bit 3 − 7 CY ← CY ∨ PSW.bit ×
OR1
CY, [HL].bit 2 6 7 CY ← CY ∨ (HL).bit ×
CY, saddr.bit 3 6 7 CY ← CY ∨ (saddr.bit) ×
CY, sfr.bit 3 − 7 CY ← CY ∨ sfr.bit ×
CY, A.bit 2 4 − CY ← CY ∨ A.bit ×
CY, PSW. bit 3 − 7 CY ← CY ∨ PSW.bit ×
XOR1
CY, [HL].bit 2 6 7 CY ← CY ∨ (HL).bit ×
saddr.bit 2 4 6 (saddr.bit) ← 1
sfr.bit 3
− 8 sfr.bit ← 1
A.bit 2 4
− A.bit ← 1
PSW.bit 2
− 6 PSW.bit ← 1 × × ×
SET1
[HL].bit 2 6 8 (HL).bit ← 1
saddr.bit 2 4 6 (saddr.bit) ← 0
sfr.bit 3
− 8 sfr.bit ← 0
A.bit 2 4
− A.bit ← 0
PSW.bit 2
− 6 PSW.bit ← 0 × × ×
CLR1
[HL].bit 2 6 8 (HL).bit ← 0
SET1 CY 1 2
− CY ← 1 1
CLR1 CY 1 2
− CY ← 0 0
Bit
manipulate
NOT1 CY 1 2
− CY ← CY ×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD 629
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Operation ZACCY
CALL !addr16 3 7
− (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLF !addr11 2 5
− (SP − 1) ← (PC + 2)H, (SP − 2) ← (PC + 2)L,
PC15 − 11 ← 00001, PC10 − 0 ← addr11,
SP ← SP − 2
CALLT [addr5] 1 6
− (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP − 2
BRK 1 6
− (SP − 1) ← PSW, (SP − 2) ← (PC + 1)H,
(SP − 3) ← (PC + 1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP − 3, IE ← 0
RET 1 6
− PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI 1 6
− PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3
RRR
Call/return
RETB 1 6
− PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3
RRR
PSW 1 2
− (SP − 1) ← PSW, SP ← SP − 1 PUSH
rp 1 4
− (SP − 1) ← rpH, (SP − 2) ← rpL,
SP ← SP − 2
PSW 1 2
− PSW ← (SP), SP ← SP + 1 R R RPOP
rp 1 4
− rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
SP, #word 4 − 10 SP ← word
SP, AX 2 − 8 SP ← AX
Stack
manipulate
MOVW
AX, SP 2 − 8 AX ← SP
!addr16 3
6 − PC ← addr16
$addr16 2
6 − PC ← PC + 2 + jdisp8
Unconditional
branch
BR
AX 2
8 − PCH ← A, PCL ← X
BC $addr16 2
6 − PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr16 2
6 − PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr16 2
6 − PC ← PC + 2 + jdisp8 if Z = 1
Conditional
branch
BNZ $addr16 2
6 − PC ← PC + 2 + jdisp8 if Z = 0
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD
630
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Operation ZACCY
saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4 − 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8 − PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16 3 − 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1
BT
[HL].bit, $addr16 3 10 11 PC ← PC + 3 + jdisp8 if (HL).bit = 1
saddr.bit, $addr16 4 10 11 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4 − 11 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8 − PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16 4 − 11 PC ← PC + 4 + jdisp8 if PSW. bit = 0
BF
[HL].bit, $addr16 3 10 11 PC ← PC + 3 + jdisp8 if (HL).bit = 0
saddr.bit, $addr16 4 10 12 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
then reset (saddr.bit)
sfr.bit, $addr16 4 − 12 PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16 3 8 − PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16 4 − 12 PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
× × ×
BTCLR
[HL].bit, $addr16 3 10 12 PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
B, $addr16 2 6 − B ← B − 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 − C ← C −1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
Conditional
branch
DBNZ
saddr, $addr16 3 8 10 (saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
SEL RBn 2 4
− RBS1, 0 ← n
NOP 1 2
− No Operation
EI 2
− 6 IE ← 1 (Enable Interrupt)
DI 2
− 6 IE ← 0 (Disable Interrupt)
HALT 2 6
− Set HALT Mode
CPU
control
STOP 2 6
− Set STOP Mode
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD 631
29.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand
First Operand
#byte A rNote sfr saddr !addr16 PSW [DE] [HL]
[HL + byte]
[HL + B]
[HL + C]
$addr16 1 None
A ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
r MOV MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
INC
DEC
B, C DBNZ
sfr MOV MOV
saddr MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV DBNZ INC
DEC
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV ROR4
ROL4
[HL + byte]
[HL + B]
[HL + C]
MOV
X MULU
C DIVUW
Note Except “r = A”
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD
632
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
#word AX rpNote sfrp saddrp !addr16 SP None
AX ADDW
SUBW
CMPW
MOVW
XCHW
MOVW MOVW MOVW MOVW
rp MOVW MOVWNote INCW
DECW
PUSH
POP
sfrp MOVW MOVW
saddrp MOVW MOVW
!addr16 MOVW
SP MOVW MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
A.bit MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit MOV1
BT
BF
BTCLR
SET1
CLR1
CY MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
SET1
CLR1
NOT1
CHAPTER 29 INSTRUCTION SET
User’s Manual U17473EJ2V0UD 633
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
First Operand
AX !addr16 !addr11 [addr5] $addr16
Basic instruction BR CALL
BR
CALLF CALLT BR
BC
BNC
BZ
BNZ
Compound
instruction
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
User’s Manual U17473EJ2V0UD
634
CHAPTER 30 ELECTRICAL SPECIFICATIONS
Caution The
μ
PD78F0397D has an on-chip debug function. Do not use this product for mass production
because its reliability cannot be guaranteed after the on-chip debug function has been used,
given the issue of the number of times the flash memory can be rewritten. NEC Electronics does
not accept complaints concerning this product.
Absolute Maximum Ratings (TA = 25°C) (1/2)
Parameter Symbol Conditions Ratings Unit
VDD VDD = LVDD −0.3 to +6.5 V
LVDD VDD = LVDD −0.3 to +6.5 V
VSS VSS = LVSS −0.3 to +0.3 V
LVSS VSS = LVSS −0.3 to +0.3 V
AVREF −0.3 to VDD + 0.3Note V
Supply voltage
AVSS −0.3 to +0.3 V
VI1 P00 to P06, P10 to P17, P20 to P27,
P30 to P33, P70 to P77, P120 to P124,
X1, X2, XT1, XT2, FLMD0, RESET
−0.3 to VDD + 0.3Note V Input voltage
VI2 SCL0, SDA0 (N-ch open drain) −0.3 to +6.5 V
VO1 P00 to P06, P10 to P17, P20 to P27,
P30 to P33, P70 to P77, P120 to P124,
X1, X2, XT1, XT2, RESET
−0.3 to VDD + 0.3Note Output voltage
VO2 S0 to S39, COM0 to COM3 −0.3 to VLC0 + 0.3Note
V
Analog input voltage VAN ANI0 to ANI7 −0.3 to AVREF + 0.3Note
and −0.3 to VDD + 0.3Note
V
Per pin P00 to P06, P10 to P17,
P30 to P33, P70 to P77,
P120
−10 mA
P00 to P04, P120 −25 mA
Total of all pins
−80 mA P05, P06, P10 to P17,
P30 to P33, P70 to P77
−55 mA
Per pin −0.5 mA
Total of all pins
P20 to P27
−2 mA
Per pin −1 mA
Output current, high IOH
Total of all pins
P121 to P124
−4 mA
Note Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 635
Absolute Maximum Ratings (TA = 25°C) (2/2)
Parameter Symbol Conditions Ratings Unit
Per pin P00 to P06, P10 to P17,
P30 to P33, P70 to P77,
P120, SCL0, SDA0
30 mA
P00 to P04, P120 60 mA
Total of all pins
200 mA P05, P06, P10 to P17,
P30 to P33, P70 to P77,
SCL0, SDA0
140 mA
Per pin 1 mA
Total of all pins
P20 to P27
5 mA
Per pin 4 mA
Output current, low IOL
Total of all pins
P121 to P124
10 mA
In normal operation mode
Operating ambient
temperature
TA
In flash memory programming mode
−40 to +85 °C
Storage temperature Tstg −40 to +125 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
<R>
<R>
<R>
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
636
X1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 1.0
Note 2
20.0
2.7 V ≤ VDD < 4.0 V 1.0
Note 2
10.0
Ceramic
resonator
C1
X2X1
VSS
C2
X1 clock
oscillation
frequency (fX)Note 1
1.8 V ≤ VDD < 2.7 V 1.0 5.0
MHz
4.0 V ≤ VDD ≤ 5.5 V 1.0
Note 2
20.0
2.7 V ≤ VDD < 4.0 V 1.0
Note 2
10.0
Crystal
resonator
C1
X2X1
C2
VSS
X1 clock
oscillation
frequency (fX)Note 1
1.8 V ≤ VDD < 2.7 V 1.0 5.0
MHz
Note1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. It is 2.0 MHz (MIN.) when programming on the board via UART6.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the internal high-speed oscillation clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register
and oscillation stabilization time select register (OSTS) after sufficiently evaluating the
oscillation stabilization time with the resonator to be used.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 637
Internal Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
Resonator Parameter Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 7.6 8.0 8.4 MHz RSTS = 1
1.8 V ≤ VDD < 2.7 V 7.6 8.0 10.4 MHz
8 MHz internal oscillator Internal high-speed oscillation
clock frequency (fRH)Note
RSTS = 0 2.48 5.6 9.86 MHz
2.7 V ≤ VDD ≤ 5.5 V 216 240 264 kHz 240 kHz internal oscillator Internal low-speed oscillation
clock frequency (fRL) 1.8 V ≤ VDD < 2.7 V 192 240 264 kHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Remark RSTS: Bit 7 of the internal oscillation mode register (RCM))
XT1 Oscillator Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Crystal
resonator
XT1XT2
C4 C3
Rd
VSS
XT1 clock oscillation
frequency (fXT)Note
32 32.768 35 kHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and
is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore
required with the wiring method when the XT1 clock is used.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
638
DC Characteristics (1/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V
−3.0 mA
2.7 V ≤ VDD < 4.0 V −2.5 mA
Per pin for P00 to P06,
P10 to P17, P30 to P33,
P70 to P77, P120 1.8 V ≤ VDD < 2.7 V −1.0 mA
4.0 V ≤ VDD ≤ 5.5 V
−20.0 mA
2.7 V ≤ VDD < 4.0 V
−10.0 mA
TotalNote3 of P00 to P04,
P120
1.8 V ≤ VDD < 2.7 V −5.0 mA
4.0 V ≤ VDD ≤ 5.5 V
−30.0 mA
2.7 V ≤ VDD < 4.0 V
−19.0 mA
TotalNote3 of P05, P06,
P10 to P17, P30 to P33,
P70 to P77 1.8 V ≤ VDD < 2.7 V
−10.0 mA
4.0 V ≤ VDD ≤ 5.5 V
−50.0 mA
2.7 V ≤ VDD < 4.0 V
−29.0 mA
IOH1
TotalNote3 of all pins
1.8 V ≤ VDD < 2.7 V
−15.0 mA
IOH2 Per pin for P20 to P27 AVREF = VDD −0.1 mA
Output current, highNote1
IOH3 Per pin for P121 to P124 −0.1 mA
4.0 V ≤ VDD ≤ 5.5 V
8.5 mA
2.7 V ≤ VDD < 4.0 V
5.0 mA
Per pin for P00 to P06,
P10 to P17, P30 to P33,
P70 to P77, P120 1.8 V ≤ VDD < 2.7 V
2.0 mA
4.0 V ≤ VDD ≤ 5.5 V
15.0 mA
2.7 V ≤ VDD < 4.0 V
3.0 mA
Per pin for SCL0, SDA0
1.8 V ≤ VDD < 2.7 V
0.6 mA
4.0 V ≤ VDD ≤ 5.5 V
20.0 mA
2.7 V ≤ VDD < 4.0 V 15.0 mA
TotalNote3 of P00 to P04,
P120
1.8 V ≤ VDD < 2.7 V 9.0 mA
4.0 V ≤ VDD ≤ 5.5 V 45.0 mA
2.7 V ≤ VDD < 4.0 V 35.0 mA
TotalNote3 of P05, P06,
P10 to P17, P30 to P33,
P70 to P77, SCL0, SDA0 1.8 V ≤ VDD < 2.7 V
20.0 mA
4.0 V ≤ VDD ≤ 5.5 V 65.0 mA
2.7 V ≤ VDD < 4.0 V 50.0 mA
IOL1
TotalNote3 of all pins
1.8 V ≤ VDD < 2.7 V
29.0 mA
IOL2 Per pin for P20 to P27 AVREF = VDD 0.4 mA
Output current, lowNote2
IOL3 Per pin for P121 to P124 0.4 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from VDD to an output
pin.
2. Value of current at which the device operation is guaranteed even if the current flows from an output pin to
GND.
3. Specification under conditions where the duty factor is 70% (time for which current is output is 0.7 × t and
time for which current is not output is 0.3 × t, where t is a specific time). The total output current of the pins
at a duty factor of other than 70% can be calculated by the following expression.
• Where the duty factor of IOH is n%: Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where the duty factor is 50%, IOH = 20.0 mA
Total output current of pins = (20.0 × 0.7)/(50 × 0.01) = 28.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 639
DC Characteristics (2/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIH1 P02, P12, P13, P15, P121 to P124
0.7VDD
VDD V
VIH2 P00, P01, P03 to P06, P10, P11, P14, P16, P17,
P30 to P33, P70 to P77, P120, RESET
0.8VDD
VDD V
VIH3 P20 to P27
AVREF = VDD
0.7AV
REF
AVREF V
Input voltage, high
(
μ
PD78F0394, 78F0395,
78F0396, 78F0397,
78F0397D)
VIH4 SCL0, SDA0
0.7VDD
6.0 V
VIH1 P02 to P06, P12, P13, P15, P121 to P124
0.7VDD
VDD V
VIH2 P00, P01, P10, P11, P14, P16, P17, P30 to P33,
P70 to P77, P120, RESET
0.8VDD
VDD V
VIH3 P20 to P27
AVREF = VDD
0.7AV
REF
AVREF V
Input voltage, high
(
μ
PD78F0393)
VIH4 SCL0, SDA0
0.7VDD
6.0 V
VIL1 P02, P12, P13, P15, P121 to P124, SCL0, SDA0
0 0.3VDD V
VIL2 P00, P01, P03 to P06, P10, P11, P14, P16, P17,
P30 to P33, P70 to P77, P120, RESET
0 0.2VDD V
Input voltage, low
(
μ
PD78F0394, 78F0395,
78F0396, 78F0397,
78F0397D) VIL3 P20 to P27
AVREF = VDD
0
0.3AV
REF
V
VIL1 P02 to P06, P12, P13, P15, P121 to P124,
SCL0, SDA0
0 0.3VDD V
VIL2 P00, P01, P10, P11, P14, P16, P17, P30 to P33,
P70 to P77, P120, RESET
0 0.2VDD V
Input voltage, low
(
μ
PD78F0393)
VIL3 P20 to P27
AVREF = VDD
0
0.3AV
REF
V
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −3.0 mA
VDD − 0.7 V
2.7 V ≤ VDD < 4.0 V,
IOH1 = −2.5 mA
VDD − 0.5 V
VOH1 P00 to P06,
P10 to P17,
P30 to P33,
P70 to P77, P120
1.8 V ≤ VDD < 2.7 V,
IOH1 = −1.0 mA
VDD − 0.5 V
P20 to P27 AVREF = VDD,
IOH2 = −0.1 mA
VDD − 0.5 V
Output voltage, high
VOH2
P121 to P124 IOH2 = −0.1 mA VDD − 0.5 V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
<R>
<R>
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
640
DC Characteristics (3/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA
0.7 V
2.7 V ≤ VDD < 4.0 V,
IOL1 = 5.0 mA
0.7 V
1.8 V ≤ VDD < 2.7 V,
IOL1 = 2.0 mA
0.5 V
VOL1 P00 to P06,
P10 to P17,
P30 to P33,
P70 to P77, P120
1.8 V ≤ VDD < 2.7 V,
IOL1 = 0.5 mA
0.4 V
P20 to P27 AVREF = VDD,
IOL2 = 0.4 mA
0.4 V
VOL2
P121 to P124 IOL2 = 0.4 mA 0.4 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 15 mA
2.0 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 3.0 mA
0.4 V
2.7 V ≤ VDD < 4.0 V,
IOL3 = 3.0 mA
0.6 V
2.7 V ≤ VDD < 4.0 V,
IOL3 = 2.0 mA
0.4 V
Output voltage, low
VOL3 SCL0, SDA0
1.8 V ≤ VDD < 2.7 V,
IOL3 = 0.6 mA
0.5 V
ILIH1 P00 to P06,
P10 to P17,
P30 to P33,
P70 to P77, P120,
SCL0, SDA0,
FLMD0, RESET
VI = VDD 1
μ
A
ILIH2 P20 to P27 VI = AVREF = VDD 1
μ
A
I/O port mode 1
μ
A
Input leakage current, high
ILIH3 P121 to 124
(X1, X2, XT1, XT2)
VI = VDD
OSC mode 20
μ
A
ILIL1 P00 to P06,
P10 to P17,
P30 to P33,
P70 to P77, P120,
SCL0, SDA0,
FLMD0, RESET
VI = VSS −1
μ
A
ILIL2 P20 to P27 VI = VSS,
AVREF = VDD
−1
μ
A
I/O port mode −1
μ
A
Input leakage current, low
ILIL3 P121 to 124
(X1, X2, XT1, XT2)
VI = VSS
OSC mode −20
μ
A
Pull-up resistor RU VI = VSS
10 20 100 kΩ
VIL In normal operation mode
0 0.2VDD V
FLMD0 supply voltage
VIH In self-programming mode 0.8VDD VDD V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
<R>
<R>
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 641
DC Characteristics (4/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Square wave input 3.2 5.5
fXH = 20 MHzNote 2,
VDD = 5.0 V
Resonator connection 4.5 6.9
mA
Square wave input 1.6 2.8
fXH = 10 MHzNotes 2, 3,
VDD = 5.0 V Resonator connection 2.3 3.9
mA
Square wave input
1.5 2.7
fXH = 10 MHzNotes 2, 3,
VDD = 3.0 V
Resonator connection 2.2 3.2
mA
Square wave input 0.9 1.6
fXH = 5 MHzNotes 2, 3,
VDD = 3.0 V Resonator connection 1.3 2.0
mA
Square wave input
0.7 1.4
fXH = 5 MHzNotes 2, 3,
VDD = 2.0 V
Resonator connection 1.0 1.6
mA
fRH = 8 MHz, VDD = 5.0 V
1.4 2.5 mA
Square wave input 6 25
IDD1 Operating mode
fSUB = 32.768 kHzNote 4,
VDD = 5.0 V Resonator connection 15 30
μ
A
Square wave input
0.8 2.6
fXH = 20 MHzNote 2,
VDD = 5.0 V
Resonator connection 2.0 4.4
mA
Square wave input
0.4 1.3
fXH = 10 MHzNotes 2, 3,
VDD = 5.0 V
Resonator connection 1.0 2.4
mA
Square wave input
0.2 0.65
fXH = 5 MHzNotes 2, 3,
VDD = 3.0 V
Resonator connection 0.5 1.1
mA
fRH = 8 MHz, VDD = 5.0 V
0.4 1.2 mA
Square wave input
3.0 22
IDD2 HALT mode
fSUB = 32.768 kHzNote 4,
VDD = 5.0 V
Resonator connection 12 25
μ
A
VDD = 5.0 V
1 20
μ
A
Supply current
Note 1
IDD3Note 5 STOP mode
VDD = 5.0 V, TA = −40 to +70°C
1 10
μ
A
Notes 1. Total current flowing into the internal power supply (VDD, AVREF), including the peripheral operation current
and the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. However, the
current flowing into the pull-up resistors and the output current of the port are not included.
2. Not including the operating current of the 8 MHz internal oscillator, and the current flowing into the A/D
converter, watchdog timer, LVI circuit and LCD controller/driver.
3. When AMPH (bit 0 of clock operation mode select register (OSCCTL)) = 0.
4. Not including the operating current of the X1 oscillation, 8 MHz internal oscillator and 240 kHz internal
oscillator, and the current flowing into the A/D converter, watchdog timer, LVI circuit and LCD
controller/driver.
5. Not including the operating current of the 240 kHz internal oscillator and XT1 oscillation, and the current
flowing into the A/D converter, watchdog timer, LVI circuit and LCD controller/driver.
Remarks 1. f
XH: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
RH: Internal high-speed oscillation clock frequency
3. f
SUB: Subsystem clock frequency (XT1 clock oscillation frequency or external subsystem clock
frequency)
<R>
<R>
<R>
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
642
DC Characteristics (5/5)
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
A/D converter
operating current
IADCNote 1 During conversion at maximum speed 2.3 V ≤ AVREF ≤ VDD 0.86 1.9 mA
Watchdog timer
operating current
IWDTNote 2 During 240 kHz internal low-speed oscillation clock operation 5 10
μ
A
LVI operating
current
ILVINote 3 9 18
μ
A
LVDD = 5.0 V 150 330
μ
A ILCD1Note 4 When LCD (including booster circuit) is
stopped and IIC is operating LVDD = 3.0 V 75 160
μ
A
LVDD = 5.0 V 2 36
μ
A ILCD2Note 4 When only LCD booster circuit is
operating and IIC is in standby status LVDD = 3.0 V 1.5 16
μ
A
LVDD = 5.0 V 5 45
μ
A ILCD3Note 4 When LCD display is operating and IIC
is in standby status LVDD = 3.0 V 4 22
μ
A
LVDD = 5.0 V 0.1 5
μ
A
LCD operating
current
ILCD4Note 4 When LCD (including booster circuit) is
stopped and IIC is in standby status LVDD = 3.0 V 0.05 3
μ
A
Notes 1. This includes only the current that flows through the A/D converter. When the A/D converter is operating
in operation mode or HALT mode, the current value of the 78K0/LG2 is obtained by adding IADC to IDD1 or
IDD2.
2. This includes only the current that flows through the watchdog timer (including the operating current of the
240 kHz internal oscillator). When the watchdog timer is operating in HALT mode or STOP mode, the
current value of the 78K0/LG2 is obtained by adding IWDT to IDD2 or IDD3.
3. This includes only the current that flows through the LVI circuit. When the LVI circuit is operating in HALT
mode or STOP mode, the current value of the 78K0/LG2 is obtained by adding ILVI to IDD2 or IDD3.
4. This includes only the current that flows through the LCD controller/driver. The current value of the
78K0/LG2 is obtained by adding the LCD operating current (ILCD1, ILCD2, ILCD3, or ILCD4) to the supply
current (IDD1, IDD2, or IDD3).
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 643
AC Characteristics
(1) Basic operation
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 0.1 32
μ
s
2.7 V ≤ VDD < 4.0 V 0.2 32
μ
s
Main system clock (fXP)
operation
1.8 V ≤ VDD < 2.7 V 0.4Note 1 32
μ
s
Instruction cycle (minimum
instruction execution time)
TCY
Subsystem clock (fSUB) operation 114 122 125
μ
s
4.0 V ≤ VDD ≤ 5.5 V 1.0 Note 2 20.0 MHz
2.7 V ≤ VDD < 4.0 V 1.0 Note 2 10.0 MHz
External main system clock
frequency
fEXCLK
1.8 V ≤ VDD < 2.7 V 1.0 5.0 MHz
4.0 V ≤ VDD ≤ 5.5 V 24 500 ns
2.7 V ≤ VDD < 4.0 V 48 500 ns
External main system clock
input high-level width, low-level
width
tEXCLKH,
tEXCLKL
1.8 V ≤ VDD < 2.7 V 96 500 ns
External subsystem clock
frequency
fEXCLKS 32 32.768 35 kHz
External subsystem clock input
high-level width, low-level width
tEXCLKSH,
tEXCLKSL
12 ns
4.0 V ≤ VDD ≤ 5.5 V 2/fsam +
0.1Note 4
μ
s
2.7 V ≤ VDD < 4.0 V 2/fsam +
0.2Note 4
μ
s
TI000, TI010, TI001Note 3,
TI011Note 3 input high-level width,
low-level width
tTIH0,
tTIL0
1.8 V ≤ VDD < 2.7 V 2/fsam +
0.5Note 4
μ
s
4.0 V ≤ VDD ≤ 5.5 V 10 MHz
2.7 V ≤ VDD < 4.0 V 10 MHz
TI50, TI51 input frequency fTI5
1.8 V ≤ VDD < 2.7 V 5 MHz
4.0 V ≤ VDD ≤ 5.5 V 50 ns
2.7 V ≤ VDD < 4.0 V 50 ns
TI50, TI51 input high-level width,
low-level width
tTIH5,
tTIL5
1.8 V ≤ VDD < 2.7 V 100 ns
Interrupt input high-level width,
low-level width
tINTH,
tINTL
1
μ
s
Key return input low-level width tKR 250 ns
RESET low-level width tRSL 10
μ
s
Notes 1. 0.38
μ
s when operating with the 8 MHz internal oscillator.
2. It is 2.0 MHz (MIN.) when programming on the board via UART6.
3.
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
4. Selection of fsam = fPRS, fPRS/4, fPRS/256, or fPRS, fPRS/16, fPRS/64 is possible using bits 0 and 1 (PRM000,
PRM001 or PRM010, PRM011) of prescaler mode registers 00 and 01 (PRM00, PRM01). Note that when
selecting the TI000 or TI001 valid edge as the count clock, fsam = fPRS.
<R>
<R>
<R>
<R>
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
644
TCY vs. VDD (Main System Clock Operation)
5.0
1.0
2.0
0.4
0.2
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
100
0.01
1.8
32
Guaranteed
operation range
Cycle time T
CY
[ s]
Supply voltage V
DD
[V]
μ
AC Timing Test Points (Excluding External Main System Clock and External Subsystem Clock)
V
IH
V
IL
Test points V
IH
V
IL
External Main System Clock Timing, External Subsystem Clock Timing
EXCLK 0.7V
DD
(MIN.)
0.3V
DD
(MAX.)
1/f
EXCLK
t
EXCLKL
t
EXCLKH
1/f
EXCLKS
t
EXCLKSL
t
EXCLKSH
EXCLKS 0.7V
DD
(MIN.)
0.3V
DD
(MAX.)
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 645
TI Timing
TI000, TI010, TI001
Note
, TI011
Note
t
TIL0
t
TIH0
TI50, TI51
1/f
TI5
t
TIL5
t
TIH5
Interrupt Request Input Timing
INTP0 to INTP5
t
INTL
t
INTH
Key Interrupt Input Timing
KR0 to KR7
t
KR
RESET Input Timing
RESET
t
RSL
Note
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D only.
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
646
(2) Serial interface
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
(a) UART6 (Dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 625 kbps
(b) UART0 (Dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 625 kbps
(c) IIC0
Standard Mode High-Speed Mode Parameter Symbol
MIN. MAX. MIN. MAX.
Unit
SCL0 clock frequency fSCL 0 100 0 400 kHz
Setup time of start/restart conditionNote 1 tSU:STA 4.8
− 0.7 −
μ
s
Hold time tHD:STA 4.1
− 0.7 −
μ
s
Hold time when SCL0 = “L” tLOW 5.0
− 1.25 −
μ
s
Hold time when SCL0 = “H” tHIGH 5.0
− 1.25 −
μ
s
Data setup time (reception) tSU:DAT 0
− 0 −
μ
s
Data hold time (transmission)Note 2 tHD:DAT 0.47 4.0 0.23 1.00
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 647
(d) CSI1n (Master mode, SCK1n... internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 200 ns
2.7 V ≤ VDD < 4.0 V 400 ns
SCK1n cycle time tKCY1
1.8 V ≤ VDD < 2.7 V 600 ns
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 −
20Note 1
ns
2.7 V ≤ VDD < 4.0 V tKCY1/2 −
30Note 1
ns
SCK1n high-/low-level width tKH1,
tKL1
1.8 V ≤ VDD < 2.7 V tKCY1/2 −
60Note 1
ns
4.0 V ≤ VDD ≤ 5.5 V 70 ns
2.7 V ≤ VDD < 4.0 V 100 ns
SI1n setup time (to SCK1n↑) tSIK1
1.8 V ≤ VDD < 2.7 V 100 ns
SI1n hold time (from SCK1n↑) tKSI1 30 Ns
Delay time from SCK1n↓ to
SO1n output
tKSO1 C = 50 pFNote 2 40 ns
Notes 1. This value is when high-speed system clock (fXH) is used.
2. C is the load capacitance of the SCK1n and SO1n output lines.
(e) CSI1n (Slave mode, SCK1n... external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK1n cycle time tKCY2 400 ns
SCK1n high-/low-level width tKH2,
tKL2
t
KCY2/2 ns
SI1n setup time (to SCK1n↑) tSIK2 80 ns
SI1n hold time (from SCK1n↑) tKSI2 50 ns
4.0 V ≤ VDD ≤ 5.5 V 120 ns
2.7 V ≤ VDD < 4.0 V 120 ns
Delay time from SCK1n↓ to
SO1n output
tKSO2 C = 50 pF
Note
1.8 V ≤ VDD < 2.7 V 180 ns
Note C is the load capacitance of the SO1n output line.
Remark n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
648
Serial Transfer Timing
IIC0:
t
LOW
t
HIGH
t
HD:STA
Stop
condition
Start
condition
Restart
condition
Stop
condition
t
SU:DAT
t
SU:STA
t
HD:STA
t
HD:DAT
SCL0
SDA0
CSI1n:
SI1n
SO1n
tKCYm
tKLm tKHm
tSIKm tKSIm
Input data
tKSOm
Output data
SCK1n
Remark m = 1, 2
n = 0:
μ
PD78F0393
n = 0, 1:
μ
PD78F0394, 78F0395, 78F0396, 78F0397, and 78F0397D
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 649
A/D Converter Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD = LVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD, VSS = LVSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 10 bit
4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR
Overall errorNotes 1, 2 AINL
2.3 V ≤ AVREF < 2.7 V ±1.2 %FSR
4.0 V ≤ AVREF ≤ 5.5 V 6.1 36.7
μ
s
2.7 V ≤ AVREF < 4.0 V 12.2 36.7
μ
s
Conversion time tCONV
2.3 V ≤ AVREF < 2.7 V 27 66.6
μ
s
4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR
Zero-scale errorNotes 1, 2 EZS
2.3 V ≤ AVREF < 2.7 V ±0.6 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR
Full-scale errorNotes 1, 2 EFS
2.3 V ≤ AVREF < 2.7 V ±0.6 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB
2.7 V ≤ AVREF < 4.0 V ±4.5 LSB
Integral non-linearity errorNote 1 ILE
2.3 V ≤ AVREF < 2.7 V ±6.5 LSB
4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB
2.7 V ≤ AVREF < 4.0 V ±2.0 LSB
Differential non-linearity error Note 1 DLE
2.3 V ≤ AVREF < 2.7 V ±2.0 LSB
Analog input voltage VAIN AVSS AVREF V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
650
LCD Characteristics (TA = −40 to +85°C)
(1) Resistance division method
(a) Static display mode (2.0 V ≤ LVDD ≤ 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.0 LVDD V
LCD divider resistorNote 1 RLCD 60 100 150 kΩ
LCD output resistorNote 2
(Common)
RODC 40 kΩ
LCD output resistorNote 2
(Segment)
RODS 200 kΩ
Pull-up resistorNote 3
between LVDD and VLC0
RLU LVDD = 5.0 V, VLC0 = 3.0 V 7.3 kΩ
(b) 1/3 bias method (2.5 V ≤ LVDD ≤ 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.5 LVDD V
LCD divider resistorNote 1 RLCD 60 100 150 kΩ
LCD output resistorNote 2
(Common)
RODC 40 kΩ
LCD output resistorNote 2
(Segment)
RODS 200 kΩ
Pull-up resistorNote 3
between LVDD and VLC0
RLU LVDD = 5.0 V, VLC0 = 3.0 V 7.3 kΩ
(c) 1/2 bias method (2.7 V ≤ LVDD ≤ 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
LCD drive voltage VLCD 2.7 LVDD V
LCD divider resistorNote 1 RLCD 60 100 150 kΩ
TA = −10 to +85 °C 40 kΩ LCD output resistorNote 2
(Common)
RODC
TA = −40 to −10 °C 60 kΩ
LCD output resistorNote 2
(Segment)
RODS 200 kΩ
Pull-up resistorNote 3
between LVDD and VLC0
RLU LVDD = 5.0 V, VLC0 = 3.0 V 7.3 kΩ
Notes 1. When internal resistors are connected only.
2. The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2 and VSS pins, and either of
the SEG and COM pins.
3. Disconnected when LCD mode is entered by setting the LCD mode setting register (LCDMD).
Remark The figures in the above table indicate the values when a 0.47
μ
F capacitor is connected between VLC0 to
VLC2 and GND.
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 651
(2) Internal voltage boosting method (1.8 V ≤ LVDD ≤ 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CTSEL1 = 0,
CTSEL0 = 1
1.35 1.43 1.51 V
CTSEL1 = 0,
CTSEL0 = 0
1.42 1.50 1.58 V
CTSEL1 = 1,
CTSEL0 = 1
1.48 1.57 1.66 V
GAIN = 0
CTSEL1 = 1,
CTSEL0 = 0
1.54Note 3 1.63Note 3 1.72Note 3 V
CTSEL1 = 0,
CTSEL0 = 1
0.87 0.93 1.00 V
CTSEL1 = 0,
CTSEL0 = 0
0.94 1.00 1.06 V
CTSEL1 = 1,
CTSEL0 = 1
1.00 1.07 1.14 V
LCD output voltage variation range VLCD2 C1 to C4Note 1
= 0.47
μ
FNote 2
GAIN = 1
CTSEL1 = 1,
CTSEL0 = 0
1.06 1.13 1.20 V
Doubler output voltage VLCD1 C1 to C4Note 1 = 0.47
μ
FNote 2 2 VLCD2 V
Tripler output voltage VLCD0 C1 to C4Note 1 = 0.47
μ
FNote 2 3 VLCD2 V
4.5 V ≤ LVDD ≤ 5.5 V 4 s GAIN = 1
1.8 V ≤ LVDD < 4.5 V 0.5 s
Voltage boost wait timeNote 4 tVAWAIT
GAIN = 0 0.5 s
LCD output resistorNote 5 (Common) RODC 40 kΩ
LCD output resistorNote 5 (Segment) RODS 200 kΩ
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VLC0 and GND
C3: A capacitor connected between VLC1 and GND
C4: A capacitor connected between VLC2 and GND
2. When the frame frequency is 128 Hz or lower, the SEG and COM pins are left open, and (LCDON, SCOC,
VLCON) = 111B.
3. When operating voltage range is 2.0 V ≤ LVDD ≤ 5.5 V.
4. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled
(LCDON = 1).
5. The output resistor is a resistor connected between one of the VLC0, VLC1, VLC2 and VSS pins, and either of
the SEG and COM pins.
<R>
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
652
1.59 V POC Circuit Characteristics (TA = −40 to +85°C, VSS = LVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC 1.44 1.59 1.74 V
Power supply voltage rise
inclination
tPTH VDD: 0 V → change inclination of VPOC 0.5 V/ms
Minimum pulse width tPW 200
μ
s
POC Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
PTH
t
PW
Supply Voltage Rise Time (TA = −40 to +85°C, VSS = LVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Maximum time to rise to 1.8 V (VDD (MIN.))
(VDD: 0 V → 1.8 V)
tPUP1 POCMODE (option byte) = 0,
when RESET input is not used
3.6 ms
Maximum time to rise to 1.8 V (VDD (MIN.))
(releasing RESET input → VDD: 1.8 V)
tPUP2 POCMODE (option byte) = 0,
when RESET input is used
1.9 ms
Supply Voltage Rise Time Timing
• When RESET pin input is not used • When RESET pin input is used
Supply voltage
(V
DD
)
Time
1.8 V
t
PUP1
Supply voltage
(V
DD
)
Time
1.8 V
t
PUP2
V
POC
RESET pin
2.7 V POC Circuit Characteristics (TA = −40 to +85°C, VSS = LVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage on application of supply
voltage
VDDPOC POCMODE (option bye) = 1 2.50 2.70 2.90 V
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD 653
LVI Circuit Characteristics (TA = −40 to +85°C, VPOC ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.14 4.24 4.34 V
VLVI1 3.99 4.09 4.19 V
VLVI2 3.83 3.93 4.03 V
VLVI3 3.68 3.78 3.88 V
VLVI4 3.52 3.62 3.72 V
VLVI5 3.37 3.47 3.57 V
VLVI6 3.22 3.32 3.42 V
VLVI7 3.06 3.16 3.26 V
VLVI8 2.91 3.01 3.11 V
VLVI9 2.75 2.85 2.95 V
VLVI10 2.60 2.70 2.80 V
VLVI11 2.45 2.55 2.65 V
VLVI12 2.29 2.39 2.49 V
VLVI13 2.14 2.24 2.34 V
VLVI14 1.98 2.08 2.18 V
Supply voltage level
VLVI15 1.83 1.93 2.03 V
Detection
voltage
External input pinNote 1 EXLVI EXLVI < VDD, 1.8 V ≤ VDD ≤ 5.5 V 1.11 1.21 1.31 V
Minimum pulse width tLW 200
μ
s
Operation stabilization wait timeNote 2 tLWAIT 10
μ
s
Notes 1. The EXLVI/P120/INTP0 pin is used.
2. Time required from setting bit 7 (LVION) of the low-voltage detection register (LVIM) to 1 to operation
stabilization.
Remark V
LVI(n − 1) > VLVIn: n = 1 to 15
LVI Circuit Timing
Supply voltage
(V
DD
)
Time
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
LW
t
LWAIT
LVION ← 1
<R>
CHAPTER 30 ELECTRICAL SPECIFICATIONS
User’s Manual U17473EJ2V0UD
654
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.44Note 5.5 V
Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC
reset is effected, but data is not retained when a POC reset is effected.
VDD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
VDDDR
Operation mode
Flash Memory Programming Characteristics
(TA = −40 to +85°C, 2.7 V ≤ VDD = LVDD ≤ 5.5 V, VSS = LVSS = AVSS = 0 V)
• Basic characteristics
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD supply current IDD fXP = 10 MHz (TYP.), 20 MHz (MAX.) 4.5 11.0 mA
All block Teraca 20 200 ms Erase timeNotes 1, 2
Block unit Terasa 20 200 ms
Write time (in 8-bit units)Note 1 Twrwa 10 100
μ
s
Number of rewrites per chip Cerwr Retention: 10 years
1 erase + 1 write after erase = 1 rewriteNote 3
100 Times
Notes 1. Characteristic of the flash memory. For the characteristic when a dedicated flash programmer, PG-FP4,
is used and the rewrite time during self programming, see Tables 27-12 and 27-13.
2. The prewrite time before erasure and the erase verify time (writeback time) are not included.
3. When a product is first written after shipment, “erase → write” and “write only” are both taken as one
rewrite.
Remarks 1. f
XP: Main system clock oscillation frequency
2. For serial write operation characteristics, refer to 78K0/Lx2 Flash Memory Programming
(Programmer) Application Note (U18204E).
<R>
<R>
<R>
User’s Manual U17473EJ2V0UD 655
CHAPTER 31 PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
D
G
16.00±0.20
14.00±0.20
0.50 (T.P.)
1.00
J
16.00±0.20
K
C 14.00±0.20
I 0.08
1.00±0.20
L0.50±0.20
F 1.00
N
P
Q
0.08
1.40±0.05
0.10±0.05
S100GC-50-8EU, 8EA-2
S 1.60 MAX.
H 0.22+0.05
−0.04
M 0.17+0.03
−0.07
R3°+7°
−3°
125
26
50
100
76
75 51
S
SN
J
detail of lead end
C D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
CHAPTER 31 PACKAGE DRAWINGS
User’s Manual U17473EJ2V0UD
656
S
y
e
Sxb
M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.125
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
20.00 0.20
14.00 0.20
22.00 0.20
16.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.04
0.08
0.075
0.025
0.25
c
e
x
y
ZD
ZE
0.65
0.13
0.10
0.575
0.825
L
Lp
L1
0.50
0.60 0.15
5
3
1.00 0.20
P100GF-65-GAS
3
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
detail of lead end
0.30
b+
+
+
30
50
1
100 31
51
81
80
100-PIN PLASTIC LQFP (14x20)
<R>
User’s Manual U17473EJ2V0UD 657
CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, please contact an NEC Electronics
sales representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 32-1. Surface Mounting Type Soldering Conditions
• 100-pin plastic LQFP (14 × 14)
μ
PD78F0393GC-8EA-A, 78F0394GC-8EA-A, 78F0395GC-8EA-A, 78F0396GC-8EA-A, 78F0397GC-8EA-A,
78F0397DGC-8EA-A Note 1
• 100-pin plastic LQFP (14 × 20)
μ
PD78F0393GF-GAS-A, 78F0394GF-GAS-A, PD78F0395GF-GAS-A, 78F0396GF-GAS-A, 78F0397GF-GAS-A,
78F0397DGF-GAS-A Note 1
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: 3 times or less, Exposure limit: 7 daysNote 2 (after that, prebake at 125°C for
20 to 72 hours)
IR60-207-3
Partial heating Pin temperature: 350°C max., Time: 3 seconds max. (per pin row) −
Notes 1. The
μ
PD78F0397D has an on-chip debug function. Do not use this product for mass production because
its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with
respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept
complaints concerning this product.
2. After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
<R>
User’s Manual U17473EJ2V0UD
658
CHAPTER 33 CAUTIONS FOR WAIT
33.1 Cautions for Wait
This product has two internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data
may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes
processing, until the correct data is passed.
As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of
execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, see Table 33-
1). This must be noted when real-time processing is performed.
CHAPTER 33 CAUTIONS FOR WAIT
User’s Manual U17473EJ2V0UD 659
33.2 Peripheral Hardware That Generates Wait
Table 33-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait
clocks.
Table 33-1. Registers That Generate Wait and Number of CPU Wait Clocks
Peripheral
Hardware Register Access Number of Wait Clocks
Serial interface
UART0
ASIS0 Read 1 clock (fixed)
Serial interface
UART6
ASIS6 Read 1 clock (fixed)
Serial interface
IIC0
IICS0 Read 1 clock (fixed)
ADM Write
ADS Write
ADPC Write
ADCR Read
1 to 5 clocks (when fAD = fPRS/2 is selected)
1 to 7 clocks (when fAD = fPRS/3 is selected)
1 to 9 clocks (when fAD = fPRS/4 is selected)
2 to 13 clocks (when fAD = fPRS/6 is selected)
2 to 17 clocks (when fAD = fPRS/8 is selected)
2 to 25 clocks (when fAD = fPRS/12 is selected)
A/D converter
The above number of clocks is when the same source clock is selected for fCPU and fPRS. The number of wait
clocks can be calculated by the following expression and under the following conditions.
<Calculating number of wait clocks>
• Number of wait clocks = 2 fCPU
fAD + 1
* Fraction is truncated if the number of wait clocks ≤ 0.5 and rounded up if the number of wait clocks > 0.5.
fAD: A/D conversion clock frequency (fPRS/2 to fPRS/12)
fCPU: CPU clock frequency
fPRS: Peripheral hardware clock frequency
fXP: Main system clock frequency
<Conditions for maximum/minimum number of wait clocks>
• Maximum number of times: Maximum speed of CPU (fXP), lowest speed of A/D conversion clock (fPRS/12)
• Minimum number of times: Minimum speed of CPU (fSUB/2), highest speed of A/D conversion clock (fPRS/2)
Caution When the CPU is operating on the subsystem clock and the peripheral hardware clock is stopped,
do not access the registers listed above using an access method in which a wait request is issued.
Remark The clock is the CPU clock (fCPU).
User’s Manual U17473EJ2V0UD
660
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the 78K0/LG2.
Figure A-1 shows the development tool configuration.
• Support for PC98-NX series
Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX
series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.
• WindowsTM
Unless otherwise specified, “Windows” means the following OSs.
• Windows 98
• Windows NTTM
• Windows 2000
• Windows XP
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17473EJ2V0UD 661
Figure A-1. Development Tool Configuration (1/2)
(1) When using the in-circuit emulator QB-78K0LX2
Language processing software
• Assembler package
• C compiler package
• Device file
• C library source fileNote 1
Debugging software
• Integrated debugger
Host machine
(PC or EWS)
In-circuit emulatorNote 3
Emulation probe
Target system
Flash programmer
Flash memory
write adapter
Flash memory
• Software package
• Project manager
Software package
Flash memory
write environment
Control software
(Windows only)Note 2
Power supply unit
USB interface cable
Notes 1. The C library source file is not included in the software package.
2. The project manager PM+ is included in the assembler package.
The PM+ is only used for Windows.
3. In-circuit emulator QB-78K0LX2 is supplied with integrated debugger ID78K0-QB, simple flash memory
programmer PG-FPL3, power supply unit, and USB interface cable. Any other products are sold
separately.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17473EJ2V0UD
662
Figure A-1. Development Tool Configuration (2/2)
(2) When using the on-chip debug emulator QB-78K0MINI
On-chip debug emulator
Note 3
Connection cable
Language processing software
• Assembler package
• C compiler package
• Device file
• C library source file
Note 1
Debugging software
• Integrated debugger
Host machine (PC or EWS)
USB interface cable
Target connector
Target system
Flash programmer
Flash memory
writing adapter
Flash memory
• Software package
• Project manager
(Windows only)
Note 2
Software package
Flash memory
writing environment
Control software
Notes 1. The C library source file is not included in the software package.
2. The project manager PM+ is included in the assembler package.
PM+ is only used for Windows.
3. On-chip debug emulator QB-78K0MINI is supplied with integrated debugger ID78K0-QB, USB
interface cable, and connection cable. Any other products are sold separately.
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17473EJ2V0UD 663
A.1 Software Package
Development tools (software) common to the 78K/0 Series are combined in this package.
SP78K0
78K/0 Series software package Part number:
μ
S××××SP78K0
Remark ×××× in the part number differs depending on the host machine and OS used.
μ
S××××SP78K0
×××× Host Machine OS Supply Medium
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
CD-ROM
A.2 Language Processing Software
This assembler converts programs written in mnemonics into object codes executable
with a microcontroller.
This assembler is also provided with functions capable of automatically creating symbol
tables and branch instruction optimization.
This assembler should be used in combination with a device file (DF780397) (sold
separately).
<Precaution when using RA78K0 in PC environment>
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
RA78K0
Assembler package
Part number:
μ
S××××RA78K0
This compiler converts programs written in C language into object codes executable with
a microcontroller.
This compiler should be used in combination with an assembler package and device file
(both sold separately).
<Precaution when using CC78K0 in PC environment>
This C compiler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
CC78K0
C compiler package
Part number:
μ
S××××CC78K0
This file contains information peculiar to the device.
This device file should be used in combination with a tool (RA78K0, CC78K0, and
ID78K0-QB) (all sold separately).
The corresponding OS and host machine differ depending on the tool to be used.
DF780397Note 1
Device file
Part number:
μ
S××××DF780397
This is a source file of the functions that configure the object library included in the C
compiler package.
This file is required to match the object library included in the C compiler package to the
user’s specifications.
CC78K0-LNote 2
C library source file
Part number:
μ
S××××CC78K0-L
Notes 1. The DF780397 can be used in common with the RA78K0, CC78K0, and ID78K0-QB.
2. The CC78K0-L is not included in the software package (SP78K0).
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17473EJ2V0UD
664
Remark ×××× in the part number differs depending on the host machine and OS used.
μ
S××××RA78K0
μ
S××××CC78K0
μ
S××××CC78K0-L
×××× Host Machine OS Supply Medium
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
3P17 HP9000 series 700TM HP-UXTM (Rel. 10.10)
3K17 SPARCstationTM SunOSTM (Rel. 4.1.4)
SolarisTM (Rel. 2.5.1)
CD-ROM
μ
S××××DF780397
×××× Host Machine OS Supply Medium
AB13 Windows (Japanese version)
BB13
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
3.5-inch 2HD FD
A.3 Control Software
PM+
Project manager
This is control software designed to enable efficient user program development in the
Windows environment. All operations used in development of a user program, such as
starting the editor, building, and starting the debugger, can be performed from the project
manager.
<Caution>
The project manager is included in the assembler package (RA78K0).
It can only be used in Windows.
A.4 Flash Memory Writing Tools
PG-FP4, FL-PR4
Flash memory programmer
Flash memory programmer dedicated to microcontrollers with on-chip flash memory.
PG-FPL3, FP-LITE3
Simple flash memory programmer
Simple flash memory programmer dedicated to microcontrollers with on-chip flash
memory.
FA-100GC-8EU-A
FA-78F0397GC-8EU-MX
FA-78F0397GF-GAS-MX
Flash memory writing adapter
Flash memory writing adapter used connected to flash memory programmer.
• FA-100GC-8EU-A, FA-78F0397GC-8EU-MX
: For 100-pin plastic LQFP (GC-8EA type)
• FA-78F0397GF-GAS-MX
: For 100-pin plastic LQFP (GF-GAS type)
Remarks 1. FL-PR4, FP-LITE3, FA-100GC-8EU-A, FA-78F0397GC-8EU-MX, and FA-78F0397GF-GAS-MX are
products of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
2. Use the latest version of the flash memory programming adapter.
<R>
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17473EJ2V0UD 665
A.5 Debugging Tools (Hardware)
A.5.1 When using in-circuit emulator QB-78K0LX2
QB-78K0LX2Note
In-circuit emulator
This in-circuit emulator serves to debug hardware and software when developing application
systems using the 78K0/LX2. It corresponds to the integrated debugger (ID78K0-QB). This
emulator should be used in combination with a power supply unit and emulation probe, and the
USB is used to connect this emulator to the host machine.
QB-144-CA-01
Check pin adapter
This check pin adapter is used in waveform monitoring using the oscilloscope, etc.
QB-144-EP-01S
Emulation probe
This emulation probe is flexible type and used to connect the in-circuit emulator and target
system.
QB-100GC-EA-03T,
QB-100GF-EA-03T
Exchange adapter
This exchange adapter is used to perform pin conversion from the in-circuit emulator to target
connector.
• QB-100GC-EA-03T: 100-pin plastic LQFP (GC-8EA type)
• QB-100GF-EA-03T: 100-pin plastic LQFP (GF-GAS type)
QB-100GC-YS-01T,
QB-100GF-YS-01T
Space adapter
This space adapter is used to adjust the height between the target system and in-circuit emulator.
• QB-100GC-YS-01T: 100-pin plastic LQFP (GC-8EA type)
• QB-100GF-YS-01T: 100-pin plastic LQFP (GF-GAS type)
QB-100GC-YQ-01T,
QB-100GF-YQ-01T
YQ connector
This YQ connector is used to connect the target connector and exchange adapter.
• QB-100GC-YQ-01T: 100-pin plastic LQFP (GC-8EA type)
• QB-100GF-YQ-01T: 100-pin plastic LQFP (GF-GAS type)
QB-100GC-HQ-01T,
QB-100GF-HQ-03T
Mount adapter
This mount adapter is used to mount the target device with socket.
• QB-100GC-HQ-01T: 100-pin plastic LQFP (GC-8EA type)
• QB-100GF-HQ-03T: 100-pin plastic LQFP (GF-GAS type)
QB-100GC-NQ-01T,
QB-100GF-NQ-01T
Target connector
This target connector is used to mount on the target system.
• QB-100GC-NQ-01T: 100-pin plastic LQFP (GC-8EA type)
• QB-100GF-NQ-01T: 100-pin plastic LQFP (GF-GAS type)
Note The QB-78K0LX2 is supplied with integrated debugger ID78K0-QB, simple flash memory programmer
PG-FPL3, power supply unit, and USB interface cable.
Remark The packed contents differ depending on the part number, as follows.
Packed Contents
Part Number
In-Circuit
Emulator
Emulation
Probe
Exchange Adapter YQ Connector Target Connector
QB-78K0LX2-ZZZ None
QB-78K0LX2-T100GC QB-100GC-EA-03T QB-100GC-YQ-01T QB-100GC-NQ-01T
QB-78K0LX2-T100GF
QB-78K0LX2
QB-144-EP-01S
QB-100GF-EA-03T QB-100GF-YQ-01T QB-100GF-NQ-01T
APPENDIX A DEVELOPMENT TOOLS
User’s Manual U17473EJ2V0UD
666
A.5.2 When using on-chip debug emulator QB-78K0MINI
QB-78K0MININote
On-chip debug emulator
The on-chip debug emulator serves to debug hardware and software when developing
application systems using the 78K0/Lx2. It supports the integrated debugger (ID78K0-
QB) supplied with the QB-78K0MINI. This emulator uses a connection cable and a USB
interface cable that is used to connect the host machine.
Target connector specifications 10-pin general-purpose connector (2.54 mm pitch)
Note The QB-78K0MINI is supplied with integrated debugger ID78K0-QB, USB interface cable, and connection
cable.
A.6 Debugging Tools (Software)
This debugger supports the in-circuit emulators for the 78K/0 Series. The ID78K0-QB is
Windows-based software.
It has improved C-compatible debugging functions and can display the results of tracing
with the source program using an integrating window function that associates the source
program, disassemble display, and memory display with the trace result. It should be
used in combination with the device file (sold separately).
ID78K0-QB
Integrated debugger
Part number:
μ
S××××ID78K0-QB
Remark ×××× in the part number differs depending on the host machine and OS used.
μ
S××××ID78K0-QB
×××× Host Machine OS Supply Medium
AB17 Windows (Japanese version)
BB17
PC-9800 series,
IBM PC/AT compatibles Windows (English version)
CD-ROM
User’s Manual U17473EJ2V0UD 667
APPENDIX B REGISTER INDEX
B.1 Register Index (In Alphabetical Order with Respect to Register Names)
[A]
A/D converter mode register (ADM)............................................................................................................................295
A/D port configuration register (ADPC) ...............................................................................................................114, 301
Analog input channel specification register (ADS) ......................................................................................................300
Asynchronous serial interface control register 6 (ASICL6)..........................................................................................348
Asynchronous serial interface operation mode register 0 (ASIM0) .............................................................................318
Asynchronous serial interface operation mode register 6 (ASIM6) .............................................................................342
Asynchronous serial interface reception error status register 0 (ASIS0).....................................................................320
Asynchronous serial interface reception error status register 6 (ASIS6).....................................................................344
Asynchronous serial interface transmission status register 6 (ASIF6) ........................................................................345
[B]
Baud rate generator control register 0 (BRGC0).........................................................................................................321
Baud rate generator control register 6 (BRGC6).........................................................................................................347
[C]
Capture/compare control register 00 (CRC00)............................................................................................................166
Capture/compare control register 01 (CRC01)............................................................................................................166
Clock operation mode select register (OSCCTL) ........................................................................................................122
Clock output selection register (CKS) .................................................................................................................290, 483
Clock selection register 6 (CKSR6).............................................................................................................................346
[E]
8-bit A/D conversion result register (ADCRH).............................................................................................................299
8-bit timer compare register 50 (CR50).......................................................................................................................235
8-bit timer compare register 51 (CR51).......................................................................................................................235
8-bit timer counter 50 (TM50)......................................................................................................................................235
8-bit timer counter 51 (TM51)......................................................................................................................................235
8-bit timer H carrier control register 1 (TMCYC1)........................................................................................................258
8-bit timer H compare register 00 (CMP00) ................................................................................................................253
8-bit timer H compare register 01 (CMP01) ................................................................................................................253
8-bit timer H compare register 10 (CMP10) ................................................................................................................253
8-bit timer H compare register 11 (CMP11) ................................................................................................................253
8-bit timer H mode register 0 (TMHMD0)....................................................................................................................254
8-bit timer H mode register 1 (TMHMD1)....................................................................................................................254
8-bit timer mode control register 50 (TMC50) .............................................................................................................238
8-bit timer mode control register 51 (TMC51) .............................................................................................................238
External interrupt falling edge enable register (EGN)..................................................................................................528
External interrupt rising edge enable register (EGP)...................................................................................................528
[I]
IIC clock selection register 0 (IICCL0).........................................................................................................................409
IIC control register 0 (IICC0) .......................................................................................................................................400
APPENDIX B REGISTER INDEX
User’s Manual U17473EJ2V0UD
668
IIC flag register 0 (IICF0).............................................................................................................................................407
IIC function expansion register 0 (IICX0) ....................................................................................................................410
IIC shift register 0 (IIC0) ..............................................................................................................................................397
IIC status register 0 (IICS0).........................................................................................................................................405
Input switch control register (ISC) ...............................................................................................................................350
Internal expansion RAM size switching register (IXS).................................................................................................591
Internal memory size switching register (IMS).............................................................................................................590
Internal oscillation mode register (RCM) .....................................................................................................................126
Interrupt mask flag register 0H (MK0H).......................................................................................................................526
Interrupt mask flag register 0L (MK0L)........................................................................................................................526
Interrupt mask flag register 1H (MK1H).......................................................................................................................526
Interrupt mask flag register 1L (MK1L)........................................................................................................................526
Interrupt request flag register 0H (IF0H) .....................................................................................................................524
Interrupt request flag register 0L (IF0L).......................................................................................................................524
Interrupt request flag register 1H (IF1H) .....................................................................................................................524
Interrupt request flag register 1L (IF1L).......................................................................................................................524
[K]
Key return mode register (KRM) .................................................................................................................................538
[L]
LCD clock control register (LCDC) ..............................................................................................................................481
LCD display mode register (LCDM) ............................................................................................................................480
LCD mode setting register (LCDMD) ..........................................................................................................................479
LCD voltage boost control register 0 (VLCG0) ............................................................................................................482
Low-voltage detection level selection register (LVIS)..................................................................................................570
Low-voltage detection register (LVIM).........................................................................................................................568
[M]
Main clock mode register (MCM) ................................................................................................................................128
Main OSC control register (MOC) ...............................................................................................................................127
Memory bank select register (BANK) ............................................................................................................................81
Multiplication/division data register A0 (MDA0H, MDA0L) ..........................................................................................511
Multiplication/division data register B0 (MDB0) ...........................................................................................................512
Multiplier/divider control register 0 (DMUC0)...............................................................................................................513
[O]
Oscillation stabilization time counter status register (OSTC)...............................................................................129, 540
Oscillation stabilization time select register (OSTS)............................................................................................130, 541
[P]
Port mode register 0 (PM0).........................................................................................................................111, 174, 380
Port mode register 1 (PM1).................................................................................................111, 240, 258, 322, 350, 380
Port mode register 2 (PM2).................................................................................................................................111, 302
Port mode register 3 (PM3).................................................................................................................................111, 240
Port mode register 6 (PM6).................................................................................................................................111, 412
Port mode register 7 (PM7).........................................................................................................................................111
Port mode register 12 (PM12) .............................................................................................................................111, 571
APPENDIX B REGISTER INDEX
User’s Manual U17473EJ2V0UD 669
Port mode register 14 (PM14).....................................................................................................................111, 291, 484
Port register 0 (P0)......................................................................................................................................................112
Port register 1 (P1)......................................................................................................................................................112
Port register 2 (P2)......................................................................................................................................................112
Port register 3 (P3)......................................................................................................................................................112
Port register 6 (P6)..............................................................................................................................................112, 413
Port register 7 (P7)......................................................................................................................................................112
Port register 12 (P12)..................................................................................................................................................112
Port register 13 (P13)..................................................................................................................................................484
Prescaler mode register 00 (PRM00)..........................................................................................................................171
Prescaler mode register 01 (PRM01)..........................................................................................................................171
Priority specification flag register 0H (PR0H)..............................................................................................................527
Priority specification flag register 0L (PR0L) ...............................................................................................................527
Priority specification flag register 1H (PR1H)..............................................................................................................527
Priority specification flag register 1L (PR1L) ...............................................................................................................527
Processor clock control register (PCC) .......................................................................................................................124
Pull-up resistor option register 0 (PU0) .......................................................................................................................113
Pull-up resistor option register 1 (PU1) .......................................................................................................................113
Pull-up resistor option register 3 (PU3) .......................................................................................................................113
Pull-up resistor option register 7 (PU7) .......................................................................................................................113
Pull-up resistor option register 12 (PU12) ...................................................................................................................113
[R]
Receive buffer register 0 (RXB0) ................................................................................................................................317
Receive buffer register 6 (RXB6) ................................................................................................................................341
Remainder data register 0 (SDR0)..............................................................................................................................511
Reset control flag register (RESF) ..............................................................................................................................560
[S]
Serial clock selection register 10 (CSIC10).................................................................................................................378
Serial clock selection register 11 (CSIC11).................................................................................................................378
Serial I/O shift register 10 (SIO10) ..............................................................................................................................375
Serial I/O shift register 11 (SIO11) ..............................................................................................................................375
Serial operation mode register 10 (CSIM10)...............................................................................................................376
Serial operation mode register 11 (CSIM11)...............................................................................................................376
16-bit timer capture/compare register 000 (CR000)....................................................................................................159
16-bit timer capture/compare register 001 (CR001)....................................................................................................159
16-bit timer capture/compare register 010 (CR010)....................................................................................................159
16-bit timer capture/compare register 011 (CR011)....................................................................................................159
16-bit timer counter 00 (TM00)....................................................................................................................................158
16-bit timer counter 01 (TM01)....................................................................................................................................158
16-bit timer mode control register 00 (TMC00) ...........................................................................................................163
16-bit timer mode control register 01 (TMC01) ...........................................................................................................163
16-bit timer output control register 00 (TOC00)...........................................................................................................168
16-bit timer output control register 01 (TOC01)...........................................................................................................168
Slave address register 0 (SVA0).................................................................................................................................397
APPENDIX B REGISTER INDEX
User’s Manual U17473EJ2V0UD
670
[T]
10-bit A/D conversion result register (ADCR)..............................................................................................................298
Timer clock selection register 50 (TCL50)...................................................................................................................236
Timer clock selection register 51 (TCL51)...................................................................................................................236
Transmit buffer register 10 (SOTB10) .........................................................................................................................374
Transmit buffer register 11 (SOTB11) .........................................................................................................................374
Transmit buffer register 6 (TXB6)................................................................................................................................341
Transmit shift register 0 (TXS0) ..................................................................................................................................317
[W]
Watch timer operation mode register (WTM) ..............................................................................................................277
Watchdog timer enable register (WDTE).....................................................................................................................283
APPENDIX B REGISTER INDEX
User’s Manual U17473EJ2V0UD 671
B.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
[A]
ADCR: 10-bit A/D conversion result register .......................................................................................................298
ADCRH: 8-bit A/D conversion result register .........................................................................................................299
ADM: A/D converter mode register ...................................................................................................................295
ADPC: A/D port configuration register.........................................................................................................114, 301
ADS: Analog input channel specification register .............................................................................................300
ASICL6: Asynchronous serial interface control register 6......................................................................................348
ASIF6: Asynchronous serial interface transmission status register 6..................................................................345
ASIM0: Asynchronous serial interface operation mode register 0........................................................................318
ASIM6: Asynchronous serial interface operation mode register 6........................................................................342
ASIS0: Asynchronous serial interface reception error status register 0...............................................................320
ASIS6: Asynchronous serial interface reception error status register 6...............................................................344
[B]
BANK: Memory bank select register .....................................................................................................................81
BRGC0: Baud rate generator control register 0.....................................................................................................321
BRGC6: Baud rate generator control register 6.....................................................................................................347
[C]
CKS: Clock output selection register ........................................................................................................290, 483
CKSR6: Clock selection register 6 ........................................................................................................................346
CMP00: 8-bit timer H compare register 00............................................................................................................253
CMP01: 8-bit timer H compare register 01............................................................................................................253
CMP10: 8-bit timer H compare register 10............................................................................................................253
CMP11: 8-bit timer H compare register 11............................................................................................................253
CR000: 16-bit timer capture/compare register 000...............................................................................................159
CR001: 16-bit timer capture/compare register 001...............................................................................................159
CR010: 16-bit timer capture/compare register 010...............................................................................................159
CR011: 16-bit timer capture/compare register 011...............................................................................................159
CR50: 8-bit timer compare register 50 ...............................................................................................................235
CR51: 8-bit timer compare register 51 ...............................................................................................................235
CRC00: Capture/compare control register 00.......................................................................................................166
CRC01: Capture/compare control register 01.......................................................................................................166
CSIC10: Serial clock selection register 10.............................................................................................................378
CSIC11: Serial clock selection register 11.............................................................................................................378
CSIM10: Serial operation mode register 10 ...........................................................................................................376
CSIM11: Serial operation mode register 11 ...........................................................................................................376
[D]
DMUC0: Multiplier/divider control register 0...........................................................................................................513
[E]
EGN: External interrupt falling edge enable register .........................................................................................528
EGP: External interrupt rising edge enable register..........................................................................................528
APPENDIX B REGISTER INDEX
User’s Manual U17473EJ2V0UD
672
[I]
IF0H: Interrupt request flag register 0H .............................................................................................................524
IF0L: Interrupt request flag register 0L .............................................................................................................524
IF1H: Interrupt request flag register 1H .............................................................................................................524
IF1L: Interrupt request flag register 1L .............................................................................................................524
IIC0: IIC shift register 0 ....................................................................................................................................397
IICC0: IIC control register 0 ................................................................................................................................400
IICCL0: IIC clock selection register 0....................................................................................................................409
IICF0: IIC flag register 0 .....................................................................................................................................407
IICS0: IIC status register 0 .................................................................................................................................405
IICX0: IIC function expansion register 0 .............................................................................................................410
IMS: Internal memory size switching register...................................................................................................590
ISC: Input switch control register.....................................................................................................................350
IXS: Internal expansion RAM size switching register ......................................................................................591
[K]
KRM: Key return mode register .........................................................................................................................538
[L]
LCDC: LCD clock control register .......................................................................................................................481
LCDM: LCD display mode register ......................................................................................................................480
LCDMD: LCD mode setting register.......................................................................................................................479
LVIM: Low-voltage detection register.................................................................................................................568
LVIS: Low-voltage detection level selection register .........................................................................................570
[M]
MCM: Main clock mode register.........................................................................................................................128
MDA0H: Multiplication/division data register A0.....................................................................................................511
MDA0L: Multiplication/division data register A0.....................................................................................................511
MDB0: Multiplication/division data register B0.....................................................................................................512
MK0H: Interrupt mask flag register 0H ................................................................................................................526
MK0L: Interrupt mask flag register 0L.................................................................................................................526
MK1H: Interrupt mask flag register 1H ................................................................................................................526
MK1L: Interrupt mask flag register 1L.................................................................................................................526
MOC: Main OSC control register .......................................................................................................................127
[O]
OSCCTL: Clock operation mode select register ......................................................................................................122
OSTC: Oscillation stabilization time counter status register ........................................................................129, 540
OSTS: Oscillation stabilization time select register .....................................................................................130, 541
[P]
P0: Port register 0..........................................................................................................................................112
P1: Port register 1..........................................................................................................................................112
P2: Port register 2..........................................................................................................................................112
P3: Port register 3..........................................................................................................................................112
P6: Port register 6..................................................................................................................................112, 413
P7: Port register 7..........................................................................................................................................112
APPENDIX B REGISTER INDEX
User’s Manual U17473EJ2V0UD 673
P12: Port register 12........................................................................................................................................112
P13: Port register 13........................................................................................................................................484
PCC: Processor clock control register ..............................................................................................................124
PM0: Port mode register 0................................................................................................................111, 174, 380
PM1: Port mode register 1........................................................................................ 111, 240, 258, 322, 350, 380
PM2: Port mode register 2........................................................................................................................111, 302
PM3: Port mode register 3........................................................................................................................111, 240
PM6: Port mode register 6........................................................................................................................111, 412
PM7: Port mode register 7................................................................................................................................111
PM12: Port mode register 12......................................................................................................................111, 571
PM14: Port mode register 14..............................................................................................................111, 291, 484
PR0H: Priority specification flag register 0H .......................................................................................................527
PR0L: Priority specification flag register 0L........................................................................................................527
PR1H: Priority specification flag register 1H .......................................................................................................527
PR1L: Priority specification flag register 1L........................................................................................................527
PRM00: Prescaler mode register 00 .....................................................................................................................171
PRM01: Prescaler mode register 01 .....................................................................................................................171
PU0: Pull-up resistor option register 0..............................................................................................................113
PU1: Pull-up resistor option register 1..............................................................................................................113
PU3: Pull-up resistor option register 3..............................................................................................................113
PU7: Pull-up resistor option register 7..............................................................................................................113
PU12: Pull-up resistor option register 12............................................................................................................113
[R]
RCM: Internal oscillation mode register.............................................................................................................126
RESF: Reset control flag register .......................................................................................................................560
RXB0: Receive buffer register 0 .........................................................................................................................317
RXB6: Receive buffer register 6 .........................................................................................................................341
[S]
SDR0: Remainder data register 0.......................................................................................................................511
SIO10: Serial I/O shift register 10........................................................................................................................375
SIO11: Serial I/O shift register 11........................................................................................................................375
SOTB10: Transmit buffer register 10 ......................................................................................................................374
SOTB11: Transmit buffer register 11 ......................................................................................................................374
SVA0: Slave address register 0..........................................................................................................................397
[T]
TCL50: Timer clock selection register 50.............................................................................................................236
TCL51: Timer clock selection register 51.............................................................................................................236
TM00: 16-bit timer counter 00 ............................................................................................................................158
TM01: 16-bit timer counter 01 ............................................................................................................................158
TM50: 8-bit timer counter 50 ..............................................................................................................................235
TM51: 8-bit timer counter 51 ..............................................................................................................................235
TMC00: 16-bit timer mode control register 00.......................................................................................................163
TMC01: 16-bit timer mode control register 01.......................................................................................................163
TMC50: 8-bit timer mode control register 50.........................................................................................................238
APPENDIX B REGISTER INDEX
User’s Manual U17473EJ2V0UD
674
TMC51: 8-bit timer mode control register 51.........................................................................................................238
TMCYC1: 8-bit timer H carrier control register 1 ......................................................................................................258
TMHMD0: 8-bit timer H mode register 0 ...................................................................................................................254
TMHMD1: 8-bit timer H mode register 1 ...................................................................................................................254
TOC00: 16-bit timer output control register 00 ......................................................................................................168
TOC01: 16-bit timer output control register 01 ......................................................................................................168
TXB6: Transmit buffer register 6 ........................................................................................................................341
TXS0: Transmit shift register 0...........................................................................................................................317
[V]
VLCG0: LCD voltage boost control register 0 .......................................................................................................482
[W]
WDTE: Watchdog timer enable register...............................................................................................................283
WTM: Watch timer operation mode register.......................................................................................................277
User’s Manual U17473EJ2V0UD 675
APPENDIX C REVISION HISTORY
C.1 Major Revisions in This Edition
(1/5)
Page Description Classification
Addition of products
μ
PD78F0394 and 78F0396 (d)
Addition of P60 and P61 pins, port mode register 6 (PM6), and port register 6 (P6) (b)
Throughout
Extending value range of capacitor (“0.47
μ
F: target” → “0.47 to 1
μ
F: recommended) (b)
CHAPTER 1 OUTLINE
p. 18 Deletion of description concerning production process division management from 1.1 Features (d)
p. 18 Change of 1.3 Ordering Information (d)
p. 22 Addition of 1.5 Configuration (d)
p. 24 Deletion of description concerning production process division management from 1.6 78K0/Kx2
Series Lineup
(d)
p. 25 Change of 1.7 Block Diagram (d)
p. 27 Deletion of description concerning production process division management from 1.8 Outline of
Functions
(d)
CHAPTER 2 PIN FUNCTIONS
p. 39 Addition of Note 3 to Table 2-2 Pin I/O Circuit Types (1/2) (c)
p. 40 Addition of Notes 2, 3, 4, and connection of RESET pin when not used to Table 2-2 Pin I/O
Circuit Types (2/2)
(c)
CHAPTER 3 CPU ARCHITECTURE
p. 43 Addition of Caution 2 to 3.1 Memory Space (c)
p. 43 Change of and addition of Note1 to Table 3-1 Set Values of Internal Memory Size Switching
Register (IMS) and Internal Expansion RAM Size Switching Register (IXS)
(d)
p. 44 Change of numeric values in program area in Figures 3-1 Memory Map (
μ
PD78F0393) (c)
p. 45 Addition of numeric values in program area in Figures 3-2 Memory Map (
μ
PD78F0394) (d)
p. 46 Change of numeric values in program area in Figures 3-3 Memory Map (
μ
PD78F0395) (c)
p. 47 Addition of numeric values in program area in Figures 3-4 Memory Map (
μ
PD78F0396) (d)
pp. 48, 49 Change of numeric values in program area in Figures 3-5 Memory Map (
μ
PD78F0397) and 3-6
Memory Map (
μ
PD78F0397D)
(c)
p. 51 Modification of description in (3) Option byte area and (5) On-chip debug security ID setting
area (
μ
PD78F0397D only) in 3.1.1
(c)
p. 51 Modification of description in 3.1.2 Memory bank (
μ
PD78F0396, 78F0397, and 78F0397D only) (c)
pp. 56, 57 Addition of Note to Figure 3-10 Correspondence Between Data Memory and Addressing
(
μ
PD78F0396) and Figure 3-11 Correspondence Between Data Memory and Addressing
(
μ
PD78F0397, 78F0397D)
(c)
p. 67 Addition of Note 3 to Table 3-7 Special Function Register List (4/4) (c)
p. 68 Addition to description in 3.3 Instruction Address Addressing (c)
p. 69 Addition to description in 3.3.2 Immediate addressing (c)
p. 70 Addition to description in 3.3.3 Table indirect addressing (c)
p. 73 Addition to description in 3.4.3 Direct addressing (c)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
<R>
APPENDIX C REVISION HISTORY
User’s Manual U17473EJ2V0UD
676
(2/5)
Page Description Classification
CHAPTER 3 CPU ARCHITECTURE
p. 74 Modification of [Description example] in 3.4.4 Short direct addressing (c)
p. 76 Addition to description in 3.4.6 Register indirect addressing (c)
p. 77 Addition to description in 3.4.7 Based addressing (c)
p. 78 Addition to description in 3.4.8 Based indexed addressing (c)
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μ
PD78F0396, 78F0397, AND 78F0397D ONLY)
pp. 80 to 89 Addition of chapter (c)
CHAPTER 5 PORT FUNCTIONS
p. 104 Change of setting of digital input and output in Table 5-4 Setting Functions of P20/ANI0 to
P27/ANI7 Pins
(a)
p. 104 Addition of Caution to 5.2.3 Port 2 (c)
p. 112 Addition of Note to Figure 5-21 Format of Port Register (c)
p. 117 Change of setting of digital input and output in Table 5-6 Setting Functions of ANI0/P20 to
ANI7/P27 Pins
(a)
p. 118 Addition of 5.6 Cautions on 1-bit Manipulation Instruction for Port Register n (Pn) (c)
CHAPTER 6 CLOCK GENERATOR
p. 121 Addition of OR circuit to Figure 6-1 Block Diagram of Clock Generator (a)
p. 123 Change of Cautions 2 and 3 (description concerning stopping time of supplying CPU clock) in
Figure 6-2 Format of Clock Operation Mode Select Register (OSCCTL)
(b)
p. 131 Addition of description of external clock input to 6.4.1 X1 oscillator and 6.4.2 XT1 oscillator (c)
pp. 136, 137 Change of Figure 6-12 Clock Generator Operation When Power Supply Voltage Is Turned On
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
(b)
p. 137 Addition of Figure 6-13 Clock Generator Operation When Power Supply Voltage Is Turned
On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1))
(b)
pp. 139, 140 Partial change (CPU clock supply stop time when AMPH = 1) of Note in 6.6.1 (1) <1> Setting
frequency (OSCCTL register) and 6.6.1 (2) <1> Setting frequency (OSCCTL register)
(b)
p. 147 Addition of Remark to Figure 6-14 CPU Clock Status Transition Diagram (When 1.59 V POC
Mode Is Set (Option Byte: POCMODE = 0))
(c)
p. 152 Change of CPU clock supply stop time when AMPH = 1 in Table 6-6 Changing CPU Clock (b)
p. 153 Change of Remark 2 in Table 6-7 Time Required for Switchover of CPU Clock and Main
System Clock Cycle Division Factor
(a)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
pp. 156 to 232 Revision of chapter (c)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
p. 239 Change of Caution 3 in Figure 8-7 Format of 8-Bit Timer Mode Control Register 50 (TMC50)
and Figure 8-8 Format of 8-Bit Timer Mode Control Register 51 (TMC51)
(c)
p. 243 Change of set value of TMC5n in Setting <1> in 8.4.2 Operation as external event counter (a)
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS H0 AND H1
p. 253 Change of Caution in Figure 9-3 Format of 8-Bit Timer H Compare Register 0n (CMP0n) (c)
p. 253 Partial addition of description to 9.2 (2) 8-bit timer H compare register 1n (CMP1n) (c)
pp. 256, 257 Change of Caution 1 of Figure 9-5 Format of 8-Bit Timer H Mode Register 0 (TMHMD0) and
Figure 9-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
(c)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
APPENDIX C REVISION HISTORY
User’s Manual U17473EJ2V0UD 677
(3/5)
Page Description Classification
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS H0 AND H1
p. 258 Partial change of description of RMC1 and NRZB1 bits in and addition of Caution to Figure 9-7
Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)
(c)
p. 261 Change of (c) Operation when CMP0n = 00H in Figure 9-10 Timing of Interval Timer/Square-
Wave Output Operation
(a)
p. 268 Partial change of description of RMC1 and NRZB1 bits in 9.4.3 (2) Carrier output control (c)
CHAPTER 11 WATCHDOG TIMER
pp. 285, 286 Change of Caution 5 in 11.4.1 Controlling operation of watchdog timer and Caution 2 in Table
11-3 Setting of Overflow Time of Watchdog Timer and Table 11-4 Setting Window Open
Period of Watchdog Timer
(c)
CHAPTER 12 CLOCK OUTPUT CONTROLLER
p. 290 Change of Figure 12-2 Format of Clock Output Selection Register (CKS) (a)
CHAPTER 13 A/D CONVERTER
p. 302 Change of setting of digital input and output in Table 13-3 Setting Functions of ANI0/P20 to
ANI7/P27 Pins
(a)
CHAPTER 14 SERIAL INTERFACE UART0
p. 314 Change of maximum transfer rate in 14.1 Functions of Serial Interface UART0 (b)
p. 332 Addition of setting data when target baud rate is 312500 bps and 625000 bps to Table 14-5 Set
Data of Baud Rate Generator
(b), (c)
CHAPTER 15 SERIAL INTERFACE UART6
p. 335 Change of maximum transfer rate in 15.1 Functions of Serial Interface UART6 (b)
p. 347 Change of output clock selection range and Remark 2 in Figure 15-9 Format of Baud Rate
Generator Control Register 6 (BRGC6)
(b)
p. 366 Partial change of description in 15.4.3 (2) Generation of serial clock (b)
p. 368 Addition of data to be set where target baud rate is 625000 bps to and change of Remark in Table
15-5 Set Data of Baud Rate Generator
(b), (c)
p. 370 Addition of error if division ratio (k) is 4 to Table 15-6 Maximum/Minimum Permissible Baud
Rate Error
(b)
CHAPTER 16 SERIAL INTERFACE CSI10 AND CSI11
p. 378 Change of Figure 16-5 Format of Serial Clock Selection Register 10 (CSIC10) (b)
p. 379 Change of Figure 16-6 Format of Serial Clock Selection Register 11 (CSIC11) (b)
CHAPTER 17 SERIAL INTERFACE IIC0
p. 397 Addition of Port register 6 to Table 17-1 Configuration of Serial Interface IIC0 (c)
p. 400 Addition of Port register 6 to 17.3 Registers to Control Serial Interface IIC0 (c)
p. 408 Partial change of condition in which STCEN bit is cleared in Figure 17-7 Format of IIC Flag
Register 0 (IICF0)
(a)
p. 413 Addition of 17.3 (8) Port register 6 (P6) (c)
p. 430 Addition of descriptions (1) Master operation in single master system, (2) Master operation in
multimaster system, and (3) Slave operation to 17.5.16 Communication operations
(c)
p. 431 Partial change of Figure 17-24 Master Operation in Single-Master System (c)
p. 436 Partial change of Figure 17-26 Slave Operation Flowchart (1) (c)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
APPENDIX C REVISION HISTORY
User’s Manual U17473EJ2V0UD
678
(4/5)
Page Description Classification
CHAPTER 18 LCD CONTROLLER/DRIVER
p. 477 Addition of 18.3 Controlling LCD Controller/Driver (c)
p. 482 Change of Figure 18-8 Format of LCD Voltage Boost Control Register 0 (a)
p. 507 Change of Figure 18-29 Examples of LCD Drive Power Connections (External Resistance
Division Method)
(c)
CHAPTER 20 INTERRUPT FUNCTIONS
p. 523 Addition of Note 4 to Table 20-2 Flags Corresponding to Interrupt Request Sources (c)
CHAPTER 22 STANDBY FUNCTION
p. 546 Change of Figure 22-4 HALT Mode Release by Reset (c)
p. 549 Change of Caution 4 in 22.2.2 (1) STOP mode setting and operating statuses (b), (c)
p. 549 Change of Figure 22-5 Operation Timing When STOP Mode Is Released (b), (c)
p. 550 Change of Figure 22-6 STOP Mode Release by Interrupt Request Generation (c)
p. 551 Change of Figure 22-7 STOP Mode Release by Reset (c)
CHAPTER 23 RESET FUNCTION
pp. 554, 555 Change of Figures 23-2 Timing of Reset by RESET Input to 23-4 Timing of Reset in STOP
Mode by RESET Input
(c)
p. 557 Addition of Note 5 to Table 23-2 Hardware Statuses After Reset Acknowledgment (1/3) (c)
CHAPTER 24 POWER-ON-CLEAR CIRCUIT
pp. 561 to 566 Revision of chapter (c)
CHAPTER 25 LOW-VOLTAGE DETECTOR
p. 567 Change and addition of description in 25.1 Functions of Low-Voltage Detector (a), (c)
p. 569 Change of description of LVIMD bit in Figure 25-2 Format of Low-Voltage Detection Register
(LVIM)
(a)
p. 571 Change and addition of description in 25.4 Operation of Low-Voltage Detector (a), (c)
p. 577 Change of <6> of (1) When detecting level of supply voltage (VDD) in 25.4.2 When used as
interrupt
(c)
pp. 578, 579 Change of (1) In 1.59 V POC mode (option byte: POCMODE = 0) in and addition of (2) In 2.7
V/1.59 V POC mode (option byte: POCMODE = 1) to Figure 25-7 Timing of Low-Voltage
Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD))
(c)
p. 580 Change of <5> of (2) When detecting level of input voltage from external input pin (EXLVI) in
25.4.2 When used as interrupt
(c)
p. 581 Addition of Figure 25-8 Timing of Low-Voltage Detector Interrupt Signal Generation (Detects
Level of Input Voltage from External Input Pin (EXLVI))
(a)
p. 582 Addition of (1) and (2) to (2) When used as interrupt of <Action> to 25.5 Cautions for Low-
Voltage Detector
(c)
CHAPTER 26 OPTION BYTE
pp. 585 to 589 Revision of chapter (c)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
APPENDIX C REVISION HISTORY
User’s Manual U17473EJ2V0UD 679
(5/5)
Page Description Classification
CHAPTER 27 FLASH MEMORY
p. 591 Change of and addition of Note 1 to Table 27-1 Internal Memory Size Switching Register
Settings
(c, d)
p. 591 Change of and addition of Note to Figure 27-2 Format of Internal Expansion RAM Size
Switching Register (IXS)
(c, d)
p. 592 Change of Table 27-2 Internal Expansion RAM Size Switching Register Settings (d)
p. 593 Change of Note 2 in Table 27-3 Wiring Between 78K0/LG2 and Dedicated Flash Programmer
(GC Package) and Table 27-4 Wiring Between 78K0/LG2 and Dedicated Flash Programmer
(GF Package)
(c)
pp. 595, 597 Addition of Note to Figure 27-4 Example of Wiring Adapter for Flash Memory Writing in
UART (UART6) Mode (GC Package) and Figure 27-6 Example of Wiring Adapter for Flash
Memory Writing in UART (UART6) Mode (GF Package)
(c)
p. 599 Addition of Note to Figure 27-9 Communication with Dedicated Flash Programmer (UART6) (c)
p. 599 Change of Note 1 in Table 27-5 Pin Connection (c)
p. 600 Change of Figure 27-10 FLMD0 Pin Connection Example (a)
p. 602 Partial change of and addition of Caution 3 to description in 27.6.6 Other signal pins (c)
p. 603 Addition of description in 27.6.7 Power supply (a)
p. 604 Change of Table 27-8 Communication Modes (a)
p. 605 Change of Table 27-9 Flash Memory Control Commands (c)
p. 606 Partial change of description in 27.8 Security Settings (a), (c)
p. 607 Change of Table 27-11 Relationship Between Enabling Security Function and Command (a), (c)
p. 607 Change of Table 27-12 Setting Security in Each Programming Mode (a), (c)
p. 608 Addition of 27.9 Processing Time for Each Command When PG-FP4 Is Used (Reference) (c)
p. 609 Deletion of Caution 5 from 27.10 Flash Memory Programming by Self-Programming (c)
p. 611 Change of Figure 27-18 Flow of Self Programming (Rewriting Flash Memory) (c)
pp. 612 to 615 Addition of Table 27-14 Processing Time and Interrupt Response Time for Self Programming
Sample Library
(c)
p. 616 Partial change of boot start position in Figure 27-19 Boot Swap Function (a)
CHAPTER 28 ON-CHIP DEBUG FUNCTION (
μ
PD78F0397D ONLY)
pp. 618 to 620 Revision of chapter (c)
CHAPTER 30 ELECTRICAL SPECIFICATIONS
pp. 634 to 654 Change of target spec to formal spec (b)
CHAPTER 31 PACKAGE DRAWINGS
p. 656 Change of 100-pin plastic QFP (14x20) to 100-pin plastic LQFP (14x20) (d)
CHAPTER 32 RECOMMENDED SOLDERING CONDITIONS
p. 657 Addition of chapter (c)
APPENDIX A DEVELOPMENT TOOLS
p. 609 Addition of FA-78F0376GC-UBT-MX, FA-78F0386GC-UBT-MX, FA-78F0376GK-8EU-MX, and
FA-78F0386GK-8EU-MX to A.4 Flash Memory Writing Tools
(b)
p. 664 Addition of FP-LITE3, FA-78F0397GC-8EU-MX and FA-78F0397GF-GAS-MX and Remark 2 to
and deletion of FA-100GF-3BA-A in A.4 Flash Memory Programming Tools
(b)
APPENDIX C REVISION HISTORY
pp. 675 to 679 Addition of chapter (b)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
NEC Electronics Corporation
1753, Shimonumabe, Nakahara-ku,
Kawasaki, Kanagawa 211-8668,
Japan
Tel: 044-435-5111
http://www.necel.com/
[America]
NEC Electronics America, Inc.
2880 Scott Blvd.
Santa Clara, CA 95050-2554, U.S.A.
Tel: 408-588-6000
800-366-9782
http://www.am.necel.com/
[Asia & Oceania]
NEC Electronics (China) Co., Ltd
7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian
District, Beijing 100083, P.R.China
Tel: 010-8235-1155
http://www.cn.necel.com/
NEC Electronics Shanghai Ltd.
Room 2509-2510, Bank of China Tower,
200 Yincheng Road Central,
Pudong New Area, Shanghai P.R. China P.C:200120
Tel: 021-5888-5400
http://www.cn.necel.com/
NEC Electronics Hong Kong Ltd.
12/F., Cityplaza 4,
12 Taikoo Wan Road, Hong Kong
Tel: 2886-9318
http://www.hk.necel.com/
Seoul Branch
11F., Samik Lavied’or Bldg., 720-2,
Yeoksam-Dong, Kangnam-Ku,
Seoul, 135-080, Korea
Tel: 02-558-3737
NEC Electronics Taiwan Ltd.
7F, No. 363 Fu Shing North Road
Taipei, Taiwan, R. O. C.
Tel: 02-8175-9600
http://www.tw.necel.com/
NEC Electronics Singapore Pte. Ltd.
238A Thomson Road,
#12-08 Novena Square,
Singapore 307684
Tel: 6253-8311
http://www.sg.necel.com/
For further information,
please contact:
G06.8A
[Europe]
NEC Electronics (Europe) GmbH
Arcadiastrasse 10
40472 Düsseldorf, Germany
Tel: 0211-65030
http://www.eu.necel.com/
Hanover Office
Podbielskistrasse 166 B
30177 Hannover
Tel: 0 511 33 40 2-0
Munich Office
Werner-Eckert-Strasse 9
81829 München
Tel: 0 89 92 10 03-0
Stuttgart Office
Industriestrasse 3
70565 Stuttgart
Tel: 0 711 99 01 0-0
United Kingdom Branch
Cygnus House, Sunrise Parkway
Linford Wood, Milton Keynes
MK14 6NP, U.K.
Tel: 01908-691-133
Succursale Française
9, rue Paul Dautier, B.P. 52180
78142 Velizy-Villacoublay Cédex
France
Tel: 01-3067-5800
Sucursal en España
Juan Esplandiu, 15
28007 Madrid, Spain
Tel: 091-504-2787
Tyskland Filial
Täby Centrum
Entrance S (7th floor)
18322 Täby, Sweden
Tel: 08 638 72 00
Filiale Italiana
Via Fabio Filzi, 25/A
20124 Milano, Italy
Tel: 02-667541
Branch The Netherlands
Steijgerweg 6
5616 HS Eindhoven
The Netherlands
Tel: 040 265 40 10
