© Semiconductor Components Industries, LLC, 2014
December, 2014 − Rev. 13 1Publication Order Number:
CAT93C86/D
CAT93C86
16 Kb Microwire Serial
EEPROM
Description
The CAT93C86 is a 16 Kb Serial EEPROM memory device which
is configured as either registers of 16 bits (ORG pin at VCC) or 8 bits
(ORG pin at GND). Each register can be written (or read) serially by
using the DI (or DO) pin. The CAT93C86 is manufactured using
ON Semiconductor’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000 program/erase
cycles and has a data retention of 100 years. The device is available in
8−pin DIP and 8−pin SOIC packages.
Features
•High Speed Operation: 3 MHz / VCC = 5 V
•Low Power CMOS Technology
•1.8 V to 5.5 V Operation
•Selectable x8 or x16 Memory Organization
•Self−timed Write Cycle with Auto−clear
•Hardware and Software Write Protection
•Power−up Inadvertent Write Protection
•Sequential Read
•Program Enable (PE) Pin
•1,000,000 Program/Erase Cycles
•100 Year Data Retention
•Industrial and Extended Temperature Ranges
•8−lead PDIP and SOIC Packages
•These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
ORG
DO
CAT93C86
SK
GND
VCC
Figure 1. Functional Symbol
PE
CS
DI
Note: When the ORG pin is connected to VCC, the x16 organization
is selected. When it is connected to ground, the x8 pin is selected. If
the ORG pin is left unconnected, then an internal pull−up device will
select the x16 organization.
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PIN CONFIGURATION
DO
DI
SK
CS 1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
SOIC−8
V, W SUFFIX
CASE 751BD
PDIP (L), SOIC (V, X)
PDIP−8
L SUFFIX
CASE 646AA
Chip SelectCS
Clock InputSK
Serial Data InputDI
Serial Data OutputDO
Power SupplyVCC
GroundGND
FunctionPin Name
PIN FUNCTION
Memory OrganizationORG
Program EnablePE
SOIC−8
X SUFFIX
CASE 751BE
GND
ORG
PE
VCC
SK
CS
VCC
PE 1
DI
DO
GND
ORG
SOIC (W)*
* Not Recommended for New Designs
CAT93C86
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Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Temperature Under Bias −55 to +125 °C
Storage Temperature −65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) −2.0 to +VCC +2.0 V
VCC with Respect to Ground −2.0 to +7.0 V
Package Power Dissipation Capability (TA = 25°C) 1.0 W
Lead Soldering Temperature (10 seconds) 300 °C
Output Short Circuit Current (Note 2) 100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
Symbol Parameter Reference Test Method Min Units
NEND (Note 3) Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte
TDR (Note 3) Data Retention MIL−STD−883, Test Method 1008 100 Years
VZAP (Note 3) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 V
ILTH (Notes 3, 4) Latch−Up JEDEC Standard 17 100 mA
3. These parameters are tested initially and after a design or process change that af fects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC +1 V.
Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +1.8 V to +5.5 V unless otherwise specified.)
Symbol Parameter Test Conditions Min Typ Max Units
ICC1 Power Supply Current (Write) fSK = 1 MHz; VCC = 5.0 V 3 mA
ICC2 Power Supply Current (Read) fSK = 1 MHz; VCC = 5.0 V 500 mA
ISB1 Power Supply Current
(Standby) (x8 Mode) CS = 0 V ORG = GND 10 mA
ISB2 Power Supply Current
(Standby) (x16 Mode) CS = 0 V ORG = Float or VCC 0 10 mA
ILI Input Leakage Current VIN = 0 V to VCC 1mA
ILO Output Leakage Current
(Including ORG pin) VOUT = 0 V to VCC, CS = 0 V 1mA
VIL1 Input Low Voltage 4.5 V ≤ VCC < 5.5 V −0.1 0.8 V
VIH1 Input High Voltage 4.5 V ≤ VCC < 5.5 V 2 VCC + 1 V
VIL2 Input Low Voltage 1.8 V ≤ VCC < 4.5 V 0 VCC x 0.2 V
VIH2 Input High Voltage 1.8 V ≤ VCC < 4.5 V VCC x 0.7 VCC + 1 V
VOL1 Output Low Voltage 4.5 V ≤ VCC < 5.5 V; IOL = 2.1 mA 0.4 V
VOH1 Output High Voltage 4.5 V ≤ VCC < 5.5 V; IOH = −400 mA2.4 V
VOL2 Output Low Voltage 1.8 V ≤ VCC < 4.5 V; IOL = 1 mA 0.2 V
VOH2 Output High Voltage 1.8 V ≤ VCC < 4.5 V; IOH = −100 mAVCC − 0.2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
CAT93C86
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Table 4. PIN CAPACITANCE (Note 5)
Symbol Test Conditions Min Typ Max Units
COUT Output Capacitance (DO) VOUT = 0 V 5 pF
CIN Input Capacitance (CS, SK, DI, ORG) VIN = 0 V 5 pF
Table 5. POWER−UP TIMING (Notes 5, 6)
Symbol Parameter Max Units
tPUR Power−up to Read Operation 1 ms
tPUW Power−up to Write Operation 1 ms
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times ≤ 50 ns
Input Pulse Voltages 0.4 V to 2.4 V 4.5 V ≤ VCC ≤ 5.5 V
Timing Reference Voltages 0.8 V, 2.0 V 4.5 V ≤ VCC ≤ 5.5 V
Input Pulse Voltages 0.2 x VCC to 0.7 x VCC 1.8 V ≤ VCC ≤ 4.5 V
Timing Reference Voltages 0.5 x VCC 1.8 V ≤ VCC ≤ 4.5 V
Table 7. A.C. CHARACTERISTICS
Symbol Parameter Test Conditions
VCC =
1.8 V − 5.5 V VCC =
2.5 V − 5.5 V VCC =
4.5 V − 5.5 V
Units
Min Max Min Max Min Max
tCSS CS Setup Time 200 100 50 ns
tCSH CS Hold Time 0 0 0 ns
tDIS DI Setup Time 200 100 50 ns
tDIH DI Hold Time 200 100 50 ns
tPD1 Output Delay to 1 1 0.5 0.15 ms
tPD0 Output Delay to 0 CL = 100 pF (Note 7) 1 0.5 0.15 ms
tHZ (Note 5) Output Delay to High−Z 400 200 100 ns
tEW Program/Erase Pulse Width 5 5 5 ms
tCSMIN Minimum CS Low Time 1 0.5 0.15 ms
tSKHI Minimum SK High Time 1 0.5 0.15 ms
tSKLOW Minimum SK Low Time 1 0.5 0.15 ms
tSV Output Delay to Status Valid 1 0.5 0.1 ms
SKMAX Maximum Clock Frequency DC 500 DC 1000 DC 3000 kHz
5. These parameters are tested initially and after a design or process change that af fects the parameter.
6. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
7. The input levels and timing reference points are shown in the “A.C. Test Conditions” table.
CAT93C86
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Table 8. INSTRUCTION SET
Instruction Start
Bit Opcode
Address Data
Comments
x8 x16 x8 x16
READ 1 10 A10−A0 A9−A0 Read Address AN– A0
ERASE 1 11 A10−A0 A9−A0 Clear Address AN– A0
WRITE 1 01 A10−A0 A9−A0 D7−D0 D15−D0 Write Address AN– A0
EWEN 1 00 11XXXXXXXXX 11XXXXXXXX Write Enable
EWDS 1 00 00XXXXXXXXX 00XXXXXXXX Write Disable
ERAL 1 00 10XXXXXXXXX 10XXXXXXXX Clear All Addresses
WRAL 1 00 01XXXXXXXXX 01XXXXXXXX D7−D0 D15−D0 Write All Addresses
Device Operation
The CAT93C86 is a 16,384−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C86 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
14−bit instructions control the reading, writing and erase
operations of the device. The CAT93C86 operates on a
single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally i n a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The D O
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 or ganizations).
Note: The Write, Erase, Write all and Erase all instructions
require PE = 1. If PE is left floating, 93C86 is in Program
Enabled mode. For Write Enable and Write Disable
instruction PE = don’t care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
device will automatically increment to the next address and
shift out the next data word in a sequential READ mode. A s
long as CS is continuously asserted and SK continues to
toggle, the device will keep incrementing to the next address
automatically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ mode,
only the initial data word is preceeded by a dummy zero bit.
All subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of t CSMIN. The falling edge of CS will start the self clocking
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
CAT93C86
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Figure 2. Synchronous Data Timing
SK
DI
CS
DO
VALID VALID
DATA VALID
tCSS
tDIS
tSKHI tSKLOW
tDIS
tDIH
tCSH
tCSMIN
tPD0, tPD1
Figure 3. Read Instruction Timing
SK
CS
DI
DO HIGH−Z
11 0
Dummy 0
Don’t Care
ANAN−1 A0
Address + n
D15 . . .
or
D7 . . .
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
D15 . . . D0
or
D7 . . . D0
111111111111111
Figure 4. Write Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−Z
HIGH−Z
101
BUSY
READY
STATUS
tHZ
tEW
tSV
VERIFY
AN−1
ANA0D0
DN
tCSMIN
CAT93C86
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Erase
Upon receiving an ERASE command and address, the C S
(Chip Select) pin must be deasserted for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT93C86
can be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Erase/Write Enable and Disable
The CAT93C86 powers up in the write disable state. Any
writing after power−up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAT93C86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The falling
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of t h e
CAT93C86 can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
Figure 5. Erase Instruction Timing
SK
CS
DI
DO
STANDBY
HIGH−Z
HIGH−Z
1
BUSY READY
STATUS
11
VERIFY
tHZ
ANAN−1 A0tCS
tSV
tEW
CAT93C86
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PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
E1
D
A
L
eb
b2
A1
A2
E
eB
c
TOP VIEW
SIDE VIEW END VIEW
PIN # 1
IDENTIFICATION
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
SYMBOL MIN NOM MAX
A
A1
A2
b
b2
c
D
e
E1
L
0.38
2.92
0.36
6.10
1.14
0.20
9.02
2.54 BSC
3.30
5.33
4.95
0.56
7.11
1.78
0.36
10.16
eB 7.87 10.92
E 7.62 8.25
2.92 3.80
3.30
0.46
6.35
1.52
0.25
9.27
7.87
CAT93C86
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PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0º 8º
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
CAT93C86
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PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
E1
eb
SIDE VIEW
TOP VIEW
E
D
PIN#1 IDENTIFICATION
END VIEW
A1
A
Lc
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
q
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
0º 8º
0.05
0.36
0.19
5.13
7.75
5.13
1.27 BSC
2.03
0.25
0.48
0.25
5.33
8.26
5.38
L0.51 0.76
CAT93C86
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ORDERING INFORMATION
OPN Specific Device
Marking* Pkg Type Temperature Range Lead
Finish Shipping
CAT93C86LI−G 93C86D PDIP−8 I = Industrial
(−40°C to +85°C) NiPdAu Tube, 50 Units / Tube
CAT93C86VI−G 93C86D SOIC−8, JEDEC I = Industrial
(−40°C to +85°C) NiPdAu Tube, 100 Units / Tube
CAT93C86VI−GT3 93C86D SOIC−8, JEDEC I = Industrial
(−40°C to +85°C) NiPdAu Tape & Reel,
3000 Units / Reel
CAT93C86WI−GT3
(Note 10) 93C86D SOIC−8, JEDEC I = Industrial
(−40°C to +85°C) NiPdAu Tape & Reel,
3000 Units / Reel
CAT93C86XI−T2 93C86D SOIC−8, EIAJ I = Industrial
(−40°C to +85°C) Matte−Tin Tape & Reel,
2000 Units / Reel
*Marking for new product Revision D.
8. All packages are RoHS−compliant (Lead−free, Halogen−free).
9. The standard lead finish is NiPdAu.
10.Not recommended for new designs.
11.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
12.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
13.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf . S CILLC reserves t he right to m ake changes wit hout further notice to any products h erein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all l iabilit y, including without limitation special, consequent ial o r i ncident al d amages. “Typical” parameters which may be provided in S CILLC d at a sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application b y c ust omer’s technical e xperts. SCILLC does not c onvey a ny license under its p atent r ights n or t he r ights o f o t hers. S CILLC p roducts a re n ot d esigned, i ntended,
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the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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P
UBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
CAT93C86/D
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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