S-25A010A/020A/040A FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM www.ablic.com www.ablicinc.com Rev.5.2_02 (c) ABLIC Inc., 2008-2014 2 This IC is a SPI serial E PROM which operates under the high temperature, at high speed, with the wide range operation for automotive components. This IC has the capacity of 1 K-bit, 2 K-bit, 4 K-bit and the organization of 128 words 8-bit, 256 words 8-bit, 512 words 8-bit. Page write and Sequential read are available. Caution Before using the product in automobile control unit or medical equipment, contact to ABLIC Inc. is indispensable. Features Packages Operating voltage range Read: 2.5 V to 5.5 V Write: 2.5 V to 5.5 V Operation frequency: 6.5 MHz max. Write time: 4.0 ms max. SPI mode (0, 0) and (1, 1) Page write: 16 bytes / page Sequential read Write protect: Software, Hardware Protect area: 25%, 50%, 100% Monitoring of a write memory state by the status register Function to prevent malfunction by monitoring clock pulse Write protect function during the low power supply voltage CMOS schmitt input ( CS , SCK, SI, WP , HOLD ) Endurance*1: 106 cycle / word*2 (Ta = 25C) 5 105 cycle / word*2 (Ta = 125C) Data retention: 100 years (Ta = 25C) 50 years (Ta = 125C) Memory capacity S-25A010A: 1 K-bit S-25A020A: 2 K-bit S-25A040A: 4 K-bit Initial delivery state: FFh, BP1 = 0, BP0 = 0 Burn-in specification: Wafer level burn-in Operation temperature range: Ta = 40C to 125C Lead-free (Sn 100%), halogen-free*3 AEC-Q100 qualified*4 *1. *2. *3. *4. Refer to " Endurance" for details. For each address (Word: 8-bit) Refer to " Product Name Structure" for details. Contact our sales office for details. Remark Refer to "3. 8-Pin SOP (JEDEC) 5 8 4 1 (5.0 6.0 t1.75 mm) 8-Pin TSSOP 8 5 1 4 (3.0 6.4 t1.1 mm) TMSOP-8 8 5 4 1 (2.9 4.0 t0.8 mm) Product name list" in " Product Name Structure" for details of package and product. 1 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Block Diagram Step-up Circuit Voltage Detector SCK SI HOLD WP Clock Counter Mode Decoder Data Register Address Register Output Control Circuit SO Status Register Read Circuit VCC GND Figure 1 2 X Decoder Input Control Circuit CS Page Latch Memory Cell Array Status Memory Cell Array Y Decoder FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 AEC-Q100 Qualified This IC supports AEC-Q100 for operation temperature grade 1. Contact our sales office for details of AEC-Q100 reliability specification. Product Name Structure 1. Product name S-25AxxxA 0A xxxx U D Burn-in specification D: Wafer level burn-in Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and IC packing specification*1 J8T2: 8-Pin SOP (JEDEC), Tape T8T2: 8-Pin TSSOP, Tape K8T2: TMSOP-8, Tape Fixed Product name S-25A010A: S-25A020A: S-25A040A: *1. 2. Refer to the tape drawing. Packages Table 1 Package Name 8-Pin SOP (JEDEC) 8-Pin TSSOP TMSOP-8 3. 1 K-bit 2 K-bit 4 K-bit Package Drawing Codes Dimension Tape Reel FJ008-A-P-SD FT008-A-P-SD FM008-A-P-SD FJ008-D-C-SD FT008-E-C-SD FM008-A-C-SD FJ008-D-R-SD FT008-E-R-SD FM008-A-R-SD Product name list Table 2 Product Name Capacity Package Quantity S-25A010A0A-J8T2UD 1 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel S-25A010A0A-T8T2UD 1 K bit 8-Pin TSSOP 3000 pcs / reel S-25A010A0A-K8T2UD 1 K bit TMSOP-8 4000 pcs / reel S-25A020A0A-J8T2UD 2 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel S-25A020A0A-T8T2UD 2 K bit 8-Pin TSSOP 3000 pcs / reel S-25A020A0A-K8T2UD 2 K bit TMSOP-8 4000 pcs / reel S-25A040A0A-J8T2UD 4 K bit 8-Pin SOP (JEDEC) 2000 pcs / reel S-25A040A0A-T8T2UD 4 K bit 8-Pin TSSOP 3000 pcs / reel S-25A040A0A-K8T2UD 4 K bit TMSOP-8 4000 pcs / reel Remark 1. Please contact our sales office for products with product name structure other than those specified above. 2. This IC is wafer level burn-in specification. 3 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Pin Configurations 1. 8-Pin SOP (JEDEC) Table 3 Top view Pin No. 8 2 7 2 SO 3 6 3 4 5 6 WP GND SI*1 SCK*1 7 HOLD *1 8 VCC 4 5 Figure 2 2. Symbol 1 1 CS *1 *1 Write protect input Ground Serial data input Serial clock input Hold input Power supply 8-Pin TSSOP Table 4 1 2 3 4 8 7 6 5 Figure 3 Pin No. 1 Symbol CS *1 2 SO 3 4 5 6 WP GND SI*1 SCK*1 7 HOLD *1 8 VCC Description Chip select input Serial data output *1 Write protect input Ground Serial data input Serial clock input Hold input Power supply TMSOP-8 Table 5 Top view 1 2 3 4 8 7 6 5 Figure 4 *1. 4 Chip select input Serial data output Top view 3. Description Do not use it in "High-Z". Pin No. 1 Symbol CS *1 Description Chip select input 2 SO Serial data output 3 4 5 6 WP *1 GND SI*1 SCK*1 Ground Serial data input Serial clock input 7 HOLD *1 8 VCC Write protect input Hold input Power supply FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Absolute Maximum Ratings Table 6 Item Symbol Absolute Maximum Rating Unit Power supply voltage VCC 0.3 to 7.0 V Input voltage VIN 0.3 to 7.0 V Output voltage VOUT 0.3 to VCC 0.3 V Operation ambient temperature Topr 40 to 125 C Storage temperature Tstg 65 to 150 C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Table 7 Item Symbol Power supply voltage VCC High level input voltage Low level input voltage VIH VIL Condition Read Write VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Ta = 40C to 125C Min. Max. 2.5 5.5 2.5 5.5 0.7 VCC VCC 1.0 0.3 0.3 VCC Unit V V V V Pin Capacitance Table 8 Item Symbol Condition (Ta = 25C, f = 1.0 MHz, VCC = 5.0 V) Min. Max. Unit Input capacitance CIN VIN = 0 V ( CS , SCK, SI, WP , HOLD ) 8 pF Output capacitance COUT VOUT = 0 V (SO) 10 pF Endurance Table9 Item Endurance *1. Symbol Operation Ambient Temperature Ta = 40C to 85C Ta = 40C to 105C Ta = 40C to 125C NW Min. 6 10 8 105 5 105 Max. Unit *1 cycle / word *1 cycle / word *1 cycle / word Max. Unit For each address (Word: 8-bit) Data Retention Table 10 Item Data retention Symbol Operation Ambient Temperature Ta = 25C Ta = 40C to 125C Min. 100 50 year year 5 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 DC Electrical Characteristics Table 11 Item Symbol Current consumption ICC1 (read) Condition No load at SO pin Ta = 40C to 125C VCC = 2.5 V to 3.0 V VCC = 3.0 V to 4.5 V VCC = 4.5 V to 5.5 V fSCK = 3.5 MHz fSCK = 5.0 MHz fSCK = 6.5 MHz Min. Max. Min. Max. Min. Max. 1.5 2.0 2.5 Unit mA Table 12 Item Symbol Current consumption ICC2 (write) Condition No load at SO pin VCC = 2.5 V to 3.0 V fSCK = 3.5 MHz Min. Max. Ta = 40C to 125C VCC = 3.0 V to 4.5 V VCC = 4.5 V to 5.5 V fSCK = 5.0 MHz fSCK = 6.5 MHz Min. Max. Min. Max. 2.0 2.5 3.0 Unit mA Table 13 Item Standby current consumption Input leakage current Output leakage current Low level output voltage High level output voltage 6 Symbol Condition Ta = 40C to 85C Ta = 85C to 125C VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 4.5 V to 5.5 V Unit Min. Max. Min. Max. Min. Max. Min. Max. ISB CS = VCC, SO = Open Other inputs are VCC or GND 2.0 3.0 8.0 10.0 A ILI VIN = GND to VCC 1.0 1.0 2.0 2.0 A ILO VOUT = GND to VCC 1.0 1.0 2.0 2.0 A VOL1 VOL2 IOL = 2.0 mA IOL = 1.5 mA 0.4 0.4 0.4 0.4 0.4 0.4 V V VOH1 IOH = 2.0 mA V VOH2 IOH = 0.4 mA 0.8 VCC 0.8 VCC V 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 AC Electrical Characteristics Table 14 Measurement Conditions Input pulse voltage Output reference voltage Output load 0.2 VCC to 0.8 VCC 0.5 VCC 100 pF Table 15 SCK clock frequency Ta = 40C to 125C Symbol VCC = 2.5 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 4.5 V to 5.5 V Unit Min. Max. Min. Max. Min. Max. fSCK 3.5 5.0 6.5 MHz CS setup time during CS falling tCSS.CL 90 90 65 ns CS setup time during CS rising tCSS.CH 90 90 65 ns CS deselect time tCDS 160 140 110 ns 90 90 65 ns ns Item tCSH.CL CS hold time during CS falling CS hold time during CS rising tCSH.CH 90 90 65 SCK clock time "H"*1 SCK clock time "L"*1 Rising time of SCK clock*2 Falling time of SCK clock*2 SI data input setup time SI data input hold time tHIGH tLOW tRSK tFSK tDS tDH 125 125 20 30 1 1 95 95 20 30 1 1 65 65 20 30 1 1 ns ns s s ns ns SCK "L" hold time during HOLD rising tSKH.HH 70 70 45 ns 40 40 30 ns 0 0 0 ns ns tSKH.HL SCK "L" hold time during HOLD falling tSKS.HL SCK "L" setup time during HOLD falling SCK "L" setup time during HOLD rising tSKS.HH 0 0 0 Disable time of SO output*2 Delay time of SO output Hold time of SO output Rising time of SO output*2 Falling time of SO output*2 tOZ tOD tOH tRO tFO 0 100 120 80 80 0 100 90 80 80 0 75 60 50 50 ns ns ns ns ns tOZ.HL 100 100 75 ns Delay time of SO output during HOLD rising tOD.HH 80 80 60 ns WP setup time tWS1 0 0 0 ns WP hold time tWH1 0 0 0 ns 0 0 0 ns 150 150 100 Disable time of SO output during HOLD falling*2 *2 WP release / setup time tWS2 ns WP release / hold time *1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested. tWH2 7 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Table 16 SCK clock frequency Ta = 40C to 105C Symbol VCC = 2.5 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 4.5 V to 5.5 V Unit Min. Max. Min. Max. Min. Max. fSCK 3.5 5.0 6.5 MHz CS setup time during CS falling tCSS.CL 90 90 65 ns CS setup time during CS rising tCSS.CH 90 90 65 ns CS deselect time tCDS 160 140 110 ns CS hold time during CS falling tCSH.CL 90 90 65 ns Item CS hold time during CS rising tCSH.CH 90 90 65 ns SCK clock time "H"*1 SCK clock time "L"*1 Rising time of SCK clock*2 Falling time of SCK clock*2 SI data input setup time SI data input hold time tHIGH tLOW tRSK tFSK tDS tDH 125 125 20 30 1 1 95 95 20 30 1 1 65 65 20 30 1 1 ns ns s s ns ns SCK "L" hold time during HOLD rising tSKH.HH 70 70 45 ns SCK "L" hold time during HOLD falling tSKH.HL 40 40 30 ns SCK "L" setup time during HOLD falling tSKS.HL 0 0 0 ns SCK "L" setup time during HOLD rising tSKS.HH 0 0 0 ns Disable time of SO output*2 Delay time of SO output Hold time of SO output Rising time of SO output*2 Falling time of SO output*2 tOZ tOD tOH tRO tFO 0 100 120 80 80 0 100 90 70 70 0 75 60 50 50 ns ns ns ns ns tOZ.HL 100 100 75 ns tOD.HH 80 80 60 ns ns Disable time of SO output during HOLD falling*2 *2 Delay time of SO output during HOLD rising WP setup time tWS1 0 0 0 WP hold time tWH1 0 0 0 ns WP release / setup time tWS2 0 0 0 ns 150 150 100 ns tWH2 WP release / hold time *1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested. 8 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Table 17 SCK clock frequency Ta = 40C to 85C Symbol VCC = 2.5 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 4.5 V to 5.5 V Unit Min. Max. Min. Max. Min. Max. fSCK 4.0 5.0 7.0 MHz CS setup time during CS falling tCSS.CL 90 80 60 ns CS setup time during CS rising tCSS.CH 90 80 60 ns CS deselect time tCDS 150 120 100 ns CS hold time during CS falling tCSH.CL 90 80 60 ns Item CS hold time during CS rising tCSH.CH 90 80 60 ns SCK clock time "H"*1 SCK clock time "L"*1 Rising time of SCK clock*2 Falling time of SCK clock*2 SI data input setup time SI data input hold time tHIGH tLOW tRSK tFSK tDS tDH 115 115 20 30 1 1 90 90 20 30 1 1 60 60 20 30 1 1 ns ns s s ns ns SCK "L" hold time during HOLD rising tSKH.HH 70 60 40 ns SCK "L" hold time during HOLD falling tSKH.HL 40 40 30 ns SCK "L" setup time during HOLD falling tSKS.HL 0 0 0 ns SCK "L" setup time during HOLD rising tSKS.HH 0 0 0 ns Disable time of SO output*2 Delay time of SO output Hold time of SO output Rising time of SO output*2 Falling time of SO output*2 tOZ tOD tOH tRO tFO 0 100 110 80 80 0 100 85 50 50 0 70 55 40 40 ns ns ns ns ns tOZ.HL 100 100 70 ns tOD.HH 80 75 55 ns ns Disable time of SO output during HOLD falling*2 *2 Delay time of SO output during HOLD rising WP setup time tWS1 0 0 0 WP hold time tWH1 0 0 0 ns WP release / setup time tWS2 0 0 0 ns 150 150 100 ns tWH2 WP release / hold time *1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing the SCK clock cycle time. *2. These are values of sample and not 100% tested. 9 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Table 18 Item Symbol Write time tPR Ta = 40C to 125C VCC = 2.5 V to 5.5 V Min. Max. 4.0 Unit ms tCDS CS tCSH.CL tCSS.CH tCSH.CH tCSS.CL SCK tDS SI SO tDH tRSK MSB IN tFSK LSB IN High-Z Figure 5 Serial Input Timing CS tSKS.HL tSKH.HL tSKH.HH SCK tSKS.HH SI tOZ.HL tOD.HH SO HOLD Figure 6 10 Hold Timing FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 tSCK CS tOZ tHIGH SCK tLOW ADDR SI LSB IN tOD tOH tOD tOH SO LSB OUT tRO tFO Figure 7 Serial Output Timing tWS1 tWH1 CS WP Figure 8 Valid Timing in Write Protect tWS2 tWH2 CS WP Figure 9 Invalid Timing in Write Protect 11 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Pin Functions 1. CS (chip select input) pin This is an input pin to set a chip in the select status. In the "H" input level, this IC is in the non-select status and its output is "High-Z". This IC is in standby as long as it is not in write inside. This IC goes in active by setting the chip select to "L". Input any instruction code after power-on and a falling of chip select. 2. SI (serial data input) pin This pin is to input serial data. This pin receives an instruction code, an address and write data. This pin latches data at rising edge of serial clock. 3. SO (serial data output) pin This pin is to output serial data. The data output changes at falling edge of serial clock. 4. SCK (serial clock input) pin This is a clock input pin to set the timing of serial data. An instruction code, an address and write data are received at a rising edge of clock. Data is output during falling edge of clock. 5. WP (write protect input) pin This is an input pin to protect memory data when write instruction (WRITE, WRSR) is being input. By setting this pin to "L", the WEL bit in the status register is set to "L". Therefore this IC does not write to the E2PROM, however, it accepts other instructions. Fix this pin "H" or "L" not to set it in the floating state. Refer to " Protect Operation" for details. 6. HOLD (hold input) pin This pin is used to pause serial communications without setting this IC in the non-select status. In the hold status, the serial output goes in "High-Z", the serial input and the serial clock go in "Don't care". During the hold operation, be sure to set this IC in active by setting the chip select ( CS pin) to "L". Refer to " Hold Operation" for details. Initial Delivery State Initial delivery state of all addresses is "FFh". Moreover, initial delivery state of the status register nonvolatile memory is as follows. 12 BP1 = 0 BP0 = 0 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Instruction Sets Table 19 and Table 20 are the list of instruction for this IC. The instruction is able to be input by changing the CS "H" to "L". Input the instruction in the MSB first. Each instruction code is organized with 1-byte as shown below. If this IC receives any invalid instruction code, this IC goes in the non-select status. 1. S-25A010A/020A Table 19 Instruction Operation Instruction Set Instruction Code Address Data SCK Input Clock 1 to 8 SCK Input Clock 9 to 16 b7 to b0 output*1 b7 to b0 input A7*2 to A0 A7*2 to A0 SCK Input Clock 17 to 24 D7 to D0 output*3 D7 to D0 input Instruction Code Address Data SCK Input Clock 1 to 8 SCK Input Clock 9 to 16 b7 to b0 output*1 b7 to b0 input A7 to A0 A7 to A0 SCK Input Clock 17 to 24 D7 to D0 output*3 D7 to D0 input WREN Write enable 0000 X110 WRDI Write disable 0000 X100 RDSR Read the status register 0000 X101 WRSR Write in the status register 0000 X001 READ Read memory data 0000 X011 WRITE Write memory data 0000 X010 *1. Sequential data reading is possible. *2. In the S-25A010A, A7 = Don't care because the address range is A6 to A0. *3. After outputting data in the specified address, data in the following address is output. Remark X = Don't care. 2. S-25A040A Table 20 Instruction Operation Instruction Set WREN Write enable 0000 X110 WRDI Write disable 0000 X100 RDSR Read the status register 0000 X101 WRSR Write in the status register 0000 X001 0000 [A8*2]011 READ Read memory data 0000 [A8*2]010 WRITE Write memory data *1. Sequential data reading is possible. *2. In the S-25A040A, assign bit A8 in the address into the fifth bit in an instruction code. *3. After outputting data in the specified address, data in the following address is output. Remark X = Don't care. 13 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Operation 1. Status register The status register's organization is below. The status register can write and read by a specific instruction. b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 BP1 BP0 WEL WIP Block Protect Write Enable Latch Write In Progress Figure 10 Organization of Status Register The status / control bits of the status register are as follows. 1. 1 BP1, BP0 (b3, b2) : Block Protect Bit BP1 and BP0 are composed of the nonvolatile memory. The area size of Software Protect with respect to WRITE instructions is defined by the BP1 and BP0 bits. Rewriting these bits is possible by the WRSR instruction. To protect the memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to "1". Rewriting bit BP1 and BP0 is possible unless they are in Hardware Protect mode. Refer to " Protect Operation" for details of Block Protect. 1. 2 WEL (b1) : Write Enable Latch Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is "1", this is the status that Write Enable Latch is set. If bit WEL is "0", Write Enable Latch is in reset, so that this IC does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations; 14 The power supply voltage is dropping At power-on After performing WRDI After the completion of write operation by the WRSR instruction After the completion of write operation by the WRITE instruction After setting WP pin to "L" FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 1. 3 WIP (b0) : Write In Progress Bit WIP is a read only bit. It indicates whether the internal memory is in the write operation or not by the WRITE or WRSR instruction. Bit WIP is "1" during the write operation but "0" during any other status. Figure 11 shows the usage example. CS WRITE or WRSR instruction RDSR instruction D2 D1 D0 SI RDSR instruction RDSR RDSR RDSR BB PP 1 0 SO RDSR instruction 1111 BB PP 1 0 BB PP 1 0 1111 11 1111 11 WEL, WIP WEL, WIP 00 WEL, WIP tPR Figure 11 2. Usage Example of WEL, WIP Bits during Write Write enable (WREN) Before writing data (WRITE and WRSR), be sure to set bit Write Enable Latch (WEL). This instruction is to set bit WEL. Its operation is below. After selecting this IC by the chip select ( CS ), input the instruction code from serial data input (SI). To set bit WEL, set this IC in the non-select status by CS at the 8th clock of the serial clock (SCK). To cancel the WREN instruction, input the clock different from a specified value (n = 8 clock) while CS is in "L". CS WP SCK High 1 2 3 4 5 6 7 8 Instruction SI X High-Z SO Remark X = Don't care. Figure 12 WREN Operation 15 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A 3. Rev.5.2_02 Write disable (WRDI) The WRDI instruction is one of ways to reset bit Write Enable Latch (WEL). After selecting this IC by the chip select ( CS ), input the instruction code from serial data input (SI). To reset bit WEL, set this IC in the non-select status by CS at the 8th clock of the serial clock. To cancel the WRDI instruction, input the clock different from a specified value (n = 8 clock) while CS is in "L". Bit WEL is reset after the operations shown below. The power supply voltage is dropping At power-on After performing WRDI After the completion of write operation by the WRSR instruction After the completion of write operation by the WRITE instruction After setting WP pin to "L" CS WP SCK High / Low 1 2 3 4 5 Instruction X SI High-Z SO Remark X = Don't care. Figure 13 16 WRDI Operation 6 7 8 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 4. Read the status register (RDSR) Reading data in the status register is possible by the RDSR instruction. During the write operation, it is possible to confirm the progress by checking bit WIP. Set the chip select ( CS ) "L" first. After that, input the instruction code from serial data input (SI). The status of bit in the status register is output from serial data output (SO). Sequential read is available for the status register. To stop the read cycle, set CS to "H". It is possible to read the status register always. The bits in it are valid and can be read by RDSR even in the write cycle. The 2 bits WEL and WIP are updated during the write cycle. The updated nonvolatile bits BP1 and BP0 can be acquired by performing a new RDSR instruction after verifying the completion of the write cycle. b7, b6, b5, and b4 are "1" when they are read by the RDSR instruction. CS WP SCK High / Low 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Instruction X SI Outputs Data in the Status Register SO High-Z b7 b6 b5 b4 b3 b2 b1 b0 b7 Remark X = Don't care. Figure 14 RDSR Operation 17 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A 5. Rev.5.2_02 Write in the status register (WRSR) The values of status register (BP1, BP0) can be rewritten by inputting the WRSR instruction. But b7, b6, b5, b4, b1, b0 of status register cannot be rewritten. b7 to b4 are always "1" when reading the status register. Before inputting the WRSR instruction, set bit WEL by the WREN instruction. The operation of WRSR is shown below. Set the chip select ( CS ) "L" first. After that, input the instruction code and data from serial data input (SI). To start WRSR write (tPR), set the chip select ( CS ) to "H" after inputting data or before inputting a rising of the next serial clock. It is possible to confirm the operation status by reading the value of bit WIP during WRSR write. Bit WIP is "1" during write, "0" during any other status. Bit WEL is reset when write is completed. With the WRSR instruction, the values of BP1 and BP0; which determine the area size the users can handle as the read only memory; can be changed. When WP pin is "L", however, the WRSR instruction is not be performed (Refer to " Protect Operation"). Bits BP1 and BP0 keep the value which is the one prior to the WRSR instruction during the WRSR instruction. The newly updated value is changed when the WRSR instruction has completed. To cancel the WRSR instruction, input the clock different from a specified value (n = 16 clock) while CS is in "L". CS WP SCK High 1 2 3 4 5 6 7 8 9 Instruction X SI 10 11 12 13 14 15 16 Inputs Data in the Status Register b7 b6 b5 b4 b3 b2 b1 b0 High-Z SO Remark X = Don't care. Figure 15 6. WRSR Operation Read memory data (READ) The READ operation is shown below. Input the instruction code and the address from serial data input (SI) after inputting "L" to the chip select ( CS ). The input address is loaded to the internal address counter, and data in the address is output from the serial data output (SO). Next, by inputting the serial clock (SCK) keeping the chip select ( CS ) in "L", the address is automatically incremented so that data in the following address is sequentially output. The address counter rolls over to the first address by increment in the last address. To finish the read cycle, set CS to "H". It is possible to raise the chip select always during the cycle. During write, the READ instruction code is not be accepted or operated. 18 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 CS WP High / Low SCK 1 2 3 4 5 6 7 9 8 10 12 13 14 15 16 17 18 19 20 21 22 23 24 8-bit Address Instruction SI 11 A7*1 A6 A5 A4 A3 A2 A1 A0 X Outputs the Second Outputs the First Byte High-Z SO *1 D7 D6 D5 D4 D3 D2 D1 D0 D7 In the S-25A010A, A7 = Don't care because the address range is A6 to A0. Remark X = Don't care. Figure 16 READ Operation (S-25A010A/020A) CS WP SCK High / Low 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8-bit Address Instruction SI 9 A7 A6 A5 A4 A3 A2 A1 A0 A8*1 Outputs the First Byte SO *1 High-Z D7 D6 D5 D4 D3 D2 D1 D0 Outputs the Second D7 In the S-25A040A, assign bit A8 in the address into the fifth bit in an instruction code. Figure 17 READ Operation (S-25A040A) 19 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A 7. Rev.5.2_02 Write memory data (WRITE) Figure 18 and Figure 19 show the timing chart when inputting 1-byte data. Input the instruction code, the address and data from serial data input (SI) after inputting "L" to the chip select ( CS ). To start WRITE (tPR), set the chip select ( CS ) to "H" after inputting data or before inputting a rising of the next serial clock. Bit WIP and WEL are reset to "0" when write has completed. This IC can Page write of 16 bytes. Its function to transmit data is as same as Byte write basically, but it operates Page write by receiving sequential 8-bit write data as much data as page size has. Input the instruction code, the address and data from serial data input (SI) after inputting "L" in CS , as the WRITE operation (page) shown in Figure 20 and Figure 21. Input the next data while keeping CS in "L". After that, repeat inputting data of 8-bit sequentially. At the end, by setting CS to "H", the WRITE operation starts (tPR). 4 of the lower bits in the address are automatically incremented every time when receiving write data of 8-bit. Thus, even if write data exceeds 16 bytes, the higher bits in the address do not change. And 4 of lower bits in the address roll over so that write data which is previously input is overwritten. These are cases when the WRITE instruction is not accepted or operated. Bit WEL is not set to "1" (not set to "1" beforehand immediately before the WRITE instruction) During WRITE operation The address to be written is in the protect area by BP1 and BP0 WP pin is set to "L" To cancel the WRITE instruction, input the clock different from a specified value (n = 16 m 8 clock) while CS is in "L". 20 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 CS WP High SCK 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 A7*1 A6 A5 X 19 20 21 22 23 24 Data Byte 1 8-bit Address Instruction SI 11 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 High-Z SO *1 In the S-25A010A, A7 = Don't care because the address range is A6 to A0. Remark X = Don't care. Figure 18 WRITE Operation (1 Byte) (S-25A010A/020A) CS WP High SCK 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 8-bit Address Instruction SI 9 A7 A6 A5 A8*1 19 20 21 22 23 24 Data Byte 1 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 High-Z SO *1 In the S-25A040A, assign bit A8 in the address into the fifth bit in an instruction code. Figure 19 WRITE Operation (1 Byte) (S-25A040A) 21 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 CS WP High 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK SI Data Byte (n) 8-bit Address Instruction A7*1 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X Data Byte (n+x) D4 D3 D2 D1 D0 High-Z SO *1 In the S-25A010A, A7 = Don't care because the address range is A6 to A0. Remark X = Don't care. Figure 20 WRITE Operation (Page) (S-25A010A/020A) CS WP High 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCK 8-bit Address Instruction SI A8*1 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 High-Z SO *1 In the S-25A040A, assign bit A8 in the address into the fifth bit in an instruction code. Figure 21 22 Data Byte (n) WRITE Operation (Page) (S-25A040A) Data Byte (n + x) D4 D3 D2 D1 D0 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Protect Operation Table 21 shows the block settings of write protect. Setting value in Protect Bits (BP1, BP0) in the status register protect data in the area of all / 50% / 25% of the memory address. Setting WP pin to "L" provides the following settings. Write protect for the WRITE, WRSR instructions Reset bit WEL The timing during the cycle write to the status register is showed in "Figure 8 "Figure 9 Invalid Timing in Write Protect". Table 21 Status Register BP1 BP0 0 0 0 1 1 0 1 1 Valid Timing in Write Protect" and Block Settings of Write Protect Area of Write Protect 0% 25% 50% 100% S-25A010A None 60h to 7Fh 40h to 7Fh 00h to 7Fh Address of Write Protect Block S-25A020A S-25A040A None None C0h to FFh 180h to 1FFh 80h to FFh 100h to 1FFh 00h to FFh 000h to 1FFh Hold Operation The hold operation is used to pause serial communications without setting this IC in the non-select status. In the hold status, the serial data output goes in "High-Z", and both of the serial data input and the serial clock go in "Don't care". Be sure to set the chip select ( CS ) to "L" to set this IC in the select status during the hold status. Generally, during the hold status, this IC holds the select status. But if setting this IC in the non-select status, the users can finish the operation even in progress. Figure 22 shows the hold operation. These are two statuses when the serial clock (SCK) is set to "L". If setting hold ( HOLD ) to "L", hold ( HOLD ) is switched at the same time the hold status starts. If setting hold ( HOLD ) to "H", hold ( HOLD ) is switched at the same time the hold status ends. These are two statuses when the serial clock (SCK) is set to "H". If setting hold ( HOLD ) to "L", the hold status starts when the serial clock goes in "L" after hold ( HOLD ) is switched. If setting hold ( HOLD ) to "H", the hold status ends when the serial clock goes in "L" after hold ( HOLD ) is switched. Hold status Hold status SCK HOLD Figure 22 Hold Operation 23 FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 Write Protect Function during the Low Power Supply Voltage This IC has a built-in detection circuit which operates with the low power supply voltage. This IC cancels the write operation (WRITE, WRSR) when the power supply voltage drops and power-on, at the same time, goes in the write protect status (WRDI) automatically to reset bit WEL. The detection voltage is 1.20 V typ., the release voltage is 1.35 V typ., and its hysteresis is approx. 0.15 V (Refer to Figure 23). To operate write, after the power supply voltage dropped once but rose to the voltage level which allows write again, be sure to set the Write Enable Latch bit (WEL) before operating write (WRITE, WRSR). In the write operation, data in the address written during the low power supply voltage is not assured. Hysteresis approx. 0.15 V Power supply voltage Detection voltage (-VDET) 1.20 V typ. Release voltage (+VDET) 1.35 V typ. Cancel the write instruction Set in write protect (WRDI) automatically Figure 23 Operation during the Low Power Supply Voltage Input Pin and Output Pin 1. Connection of input pin All input pins in this IC have the CMOS structure. Do not set these pins in "High-Z" during operation when you design. Especially, set the CS input pin in the non-select status "H" during power-on/off and standby. The error write does not occur as long as the CS pin is in the non-select status "H". Set the CS pin to VCC via a resistor (the pull-up resistor of 10 k to 100 k). If the CS pin and the SCK pin change from "L" to "H" simultaneously, data may be input from the SI pin. To prevent the error for sure, it is recommended to pull down the SCK pin to GND. In addition, it is recommended to pull up the SI pin, the WP pin and the HOLD pin to VCC, or pull down these pins to GND, respectively. Connecting the WP pin and the HOLD pin to VCC directly is also possible when these pins are not in use. 2. Equivalent circuit of input pin and output pin Figure 24 and Figure 25 show the equivalent circuits of input pins in this IC. A pull-up and pull-down elements are not included in each input pin, pay attention not to set it in the floating state when you design. Figure 26 shows the equivalent circuit of the output pin. This pin has the tri-state output of "H" / "L" / "High-Z". 2. 1 Input pin CS, SCK Figure 24 24 CS , SCK Pin FOR AUTOMOTIVE 125C OPERATION SPI SERIAL E2PROM S-25A010A/020A/040A Rev.5.2_02 SI, WP, HOLD Figure 25 2. 2 SI, WP , HOLD Pin Output pin VCC SO Figure 26 SO Pin Precautions Absolute maximum ratings: Do not operate these ICs in excess of the absolute maximum ratings (as listed on the data sheet). Exceeding the supply voltage rating can cause latch-up. Perform operations after confirming the detailed operation condition in the data sheet. Operations with moisture on this IC's pins may occur malfunction by short-circuit between pins. Especially, in occasions like picking this IC up from low temperature tank during the evaluation. Be sure that not remain frost on this IC's pins to prevent malfunction by short-circuit. Also attention should be paid in using on environment, which is easy to dew for the same reason. Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party. 25 5.020.2 8 5 1 4 1.27 0.200.05 0.40.05 No. FJ008-A-P-SD-2.2 TITLE SOP8J-D-PKG Dimensions FJ008-A-P-SD-2.2 No. ANGLE UNIT mm ABLIC Inc. 4.00.1(10 pitches:40.00.2) 2.00.05 o1.550.05 0.30.05 o2.00.05 8.00.1 2.10.1 6.70.1 1 8 4 5 Feed direction No. FJ008-D-C-SD-1.1 TITLE SOP8J-D-Carrier Tape No. FJ008-D-C-SD-1.1 ANGLE UNIT mm ABLIC Inc. 60 20.5 13.50.5 Enlarged drawing in the central part o210.8 20.5 o130.2 No. FJ008-D-R-SD-1.1 TITLE SOP8J-D-Reel No. FJ008-D-R-SD-1.1 QTY. ANGLE UNIT mm ABLIC Inc. 2,000 +0.3 3.00 -0.2 8 5 1 4 0.170.05 0.20.1 0.65 No. FT008-A-P-SD-1.2 TITLE TSSOP8-E-PKG Dimensions No. FT008-A-P-SD-1.2 ANGLE UNIT mm ABLIC Inc. 4.00.1 2.00.05 o1.550.05 0.30.05 +0.1 8.00.1 o1.55 -0.05 (4.4) +0.4 6.6 -0.2 1 8 4 5 Feed direction No. FT008-E-C-SD-1.0 TITLE TSSOP8-E-Carrier Tape FT008-E-C-SD-1.0 No. ANGLE UNIT mm ABLIC Inc. 13.41.0 17.51.0 Enlarged drawing in the central part o210.8 20.5 o130.5 No. FT008-E-R-SD-1.0 TITLE TSSOP8-E-Reel No. FT008-E-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 3,000 2.900.2 8 5 1 4 0.130.1 0.20.1 0.650.1 No. FM008-A-P-SD-1.2 TITLE TMSOP8-A-PKG Dimensions No. FM008-A-P-SD-1.2 ANGLE UNIT mm ABLIC Inc. 2.000.05 4.000.1 4.000.1 1.000.1 +0.1 1.5 -0 1.050.05 0.300.05 3.250.05 4 1 5 8 Feed direction No. FM008-A-C-SD-2.0 TITLE TMSOP8-A-Carrier Tape FM008-A-C-SD-2.0 No. ANGLE UNIT mm ABLIC Inc. 16.5max. 13.00.3 Enlarged drawing in the central part 130.2 (60) (60) No. FM008-A-R-SD-1.0 TITLE TMSOP8-A-Reel No. FM008-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 4,000 Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. 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In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com