ASAHI KASEI [AK5353] AK5353 96kHz 24Bit ADC with Single-ended Input GENERAL DESCRIPTION The AK5353 is a stereo A/D Converter with wide sampling rate of 4kHz96kHz and is suitable for multimedia audio system. The AK5353 achieves high accuracy and low cost by using Enhanced dual bit techniques. The AK5353 requires no external components because the analog inputs are single-ended. The audio interface has two formats (MSB justified, I2S) and can correspond to many systems like Karaoke, surround. FEATURES Stereo ADC On-Chip Digital Anti-Alias Filtering Single-ended Input Digital HPF for DC-Offset cancel S/(N+D): 84dB@5V, 80dB@3V for 48kHz DR: 96dB@5V, 92dB@3V for 48kHz S/N: 96dB@5V, 92dB@3V for 48kHz Sampling Rate Ranging from 4kHz to 96kHz Master Clock: 256fs/384fs/512fs (48kHz) 256fs/384fs (96kHz) Low Power Dissipation: 70mW Small 16pin TSSOP Package Power Supply: 2.75.5V (48kHz) 4.55.5V (96kHz) Ta=-4085C Input level: TTL/CMOS selectable Output format: 24bit MSB justified / I2S selectable VA AGND VD DGND MCLK Clock Divider AINL AINR VCOM Modulator Decimation Filter Modulator Decimation Filter LRCK SCLK Serial I/O Interface Voltage Reference SDTO VREF TST PDN M0067-E-02 DIF TTL 2004/01 -1- ASAHI KASEI [AK5353] Ordering Guide AK5353VT AKD5353 -40 +85C Evaluation Board 16pin TSSOP Pin Layout AINR 1 16 TST AINL 2 15 TTL VREF 3 14 DIF VCOM 4 13 PDN AGND 5 12 SCLK VA 6 11 MCLK VD 7 10 LRCK DGND 8 9 SDTO Top View M0067-E-02 2004/01 -2- ASAHI KASEI [AK5353] PIN/FUNCTION No. 1 2 3 Pin Name AINR AINL VREF I/O I I O 4 VCOM O 5 6 7 8 9 AGND VA VD DGND SDTO O 10 LRCK I 11 12 MCLK SCLK I I 13 PDN I 14 DIF I 15 TTL I 16 TST I Description Rch Analog Input Pin Lch Analog Input Pin Voltage Reference Output Pin Normally connected to AGND with a 0.1F ceramic capacitor in parallel with an electrolytic capacitor less than 4.7F. Common Voltage Output Pin Normally connected to AGND with a 0.1F ceramic capacitor in parallel with an electrolytic capacitor less than 4.7F. Analog Ground Pin, 0V Analog Power Supply Pin, +2.7 +5.5V Digital Power Supply Pin, +2.7 +5.5V Digital Ground Pin, 0V Serial Data Output Pin Data bits are presented MSB first, in 2's complement format. This pin is "L" in the power-down mode. Left/Right Channel Select Pin The fs clock is input to this pin. Master Clock Input Pin Serial Data Input Pin Output data is clocked out on the falling edge of SCLK. Power-Down Pin When "L", the circuit is in power-down mode. The AK5353 should always be reset upon power-up. Serial Interface Format Pin "L": MSB justified, "H": I2S Digital Input Level Select Pin "L": CMOS level (VA, VD=2.7 5.5V), "H": TTL level (VA, VD=4.5 5.5V) Test Pin (Internal pull-down pin) This pin should be left floating. Note: All input pins except pull-down pins should not be left floating. M0067-E-02 2004/01 -3- ASAHI KASEI [AK5353] ABSOLUTE MAXIMUM RATINGS (AGND, DGND=0V; Note 1) Parameter Symbol min Power Supplies Analog (VA pin) VA -0.3 Digital (VD pin) VD -0.3 |AGND - DGND| GND Input Current (any pins except for supplies) IIN Analog Input Voltage (AINL, AINR pins) VINA -0.3 Digital Input Voltage VIND -0.3 Ambient Temperature Ta -40 Storage Temperature Tstg -65 max 6.0 6.0 0.3 10 VA+0.3 VD+0.3 85 150 Units V V V mA V V C C Note: 1. All voltages with respect to ground. 2. AGND and DGND must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (fs=48kHz) (AGND, DGND=0V; Note 1) Parameter Symbol min typ Power Supplies Analog VA 2.7 5.0 (Note 3) Digital VD 2.7 5.0 Sampling Rate fs 4 max 5.5 VA 48 Units V V kHz max 5.5 VA 96 Units V V kHz Note: 1. All voltages with respect to ground. 3. The power up sequence between VA and VD is not critical. RECOMMENDED OPERATING CONDITIONS (fs=96kHz) (AGND, DGND=0V; Note 1) Parameter Symbol min typ Power Supplies Analog VA 4.5 5.0 (Note 3) Digital VD 4.5 5.0 Sampling Rate fs 4 Note: 1. All voltages with respect to ground. 3. The power up sequence between VA and VD is not critical. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. M0067-E-02 2004/01 -4- ASAHI KASEI [AK5353] ANALOG CHARACTERISTICS (Ta=25C; VA, VD=5V; fs=48kHz; I/F format=Mode 0; Signal Frequency =1kHz; Measurement band width=20Hz20kHz; unless otherwise specified) Parameter min typ max ADC Analog Input Characteristics: Analog source impedance=470 (BW=40Hz40kHz at fs=96kHz) Resolution 24 84 75 S/(N+D) (-1dBFS) (Note 4) fs=48kHz, VA=5V 84 75 fs=48kHz, VA=3V 84 fs=96kHz, VA=5V 90 96 DR (-60dBFS) (Note 5) fs=48kHz, VA=5V, A-weighted fs=48kHz, VA=3V, A-weighted 86 92 fs=96kHz, VA=5V 93 S/N fs=48kHz, VA=5V, A-weighted 90 96 fs=48kHz, VA=3V, A-weighted 86 92 fs=96kHz, VA=5V 93 Interchannel Isolation 78 90 DC Accuracy Interchannel Gain Mismatch 0.1 0.3 Gain Drift 100 150 Input Voltage (Note 6) 2.7 3.0 3.3 Input Resistance (Note 7) 40 60 Power Supply Rejection (Note 8) 30 Power Supplies Power Supply Current Normal Operation (PDN="H") 21 14 VA+VD (Note 9) Power-Down Mode (PDN="L") 100 10 VA+VD Units Bits dB dB dB dB dB dB dB dB dB dB dB ppm/C Vpp k dB mA A Note: 4. The ratio of the rms value of the signal to the rms sum of all the spectral components less than 20kHz bandwidth, including distortion components. 5. S/(N+D) which is measured with an input signal of -60dB below full-scale. 6. This value is the full scale(0dB) of the input voltage. Input voltage is proportional to VA. (Vin=0.6xVA) 7. 40k(typ) and 25k(min) at fs=96kHz. 8. PSR is applied to VA, VD with 1kHz, 50mVpp. 9. VA=11mA; VD=3mA@48kHz,5V, 1.5mA@48kHz,3V, 6mA@96kHz,5V (typ). M0067-E-02 2004/01 -5- ASAHI KASEI [AK5353] FILTER CHARACTERISTICS (fs=48kHz) (Ta=25C; VA, VD=2.75.5V; fs=48kHz) Parameter Symbol min Digital Filter (Decimation LPF) PB 0 Passband (Note 10) 0.1dB -0.2dB -1.0dB -3.0dB Stopband (Note 10) SB 29.4 Stopband Attenuation SA 65 Group Delay Distortion GD Group Delay (Note 11) GD Digital Filter (HPF) FR Frequency Response: -3dB -0.5dB -0.1dB typ max Units 20.0 21.8 23.0 18.9 - kHz kHz kHz kHz 0 17.0 - kHz dB s 1/fs 4 11 24 - Hz Hz Hz Note: 10. The passband and stopband frequencies scale with fs. 11. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register for ADC. FILTER CHARACTERISTICS (fs=96kHz) (Ta=25C; VA, VD=4.55.5V; fs=96kHz) Parameter Symbol min Digital Filter (Decimation LPF) Passband (Note 10) 0.1dB PB 0 -0.2dB -1.0dB -3.0dB Stopband Stopband Attenuation Group Delay Distortion Group Delay Digital Filter (HPF) Frequency Response: (Note 10) (Note 11) -3dB -0.5dB -0.1dB typ max Units 40.0 43.6 46.0 37.8 - kHz kHz kHz kHz SB SA GD GD 58.8 65 - 0 17.0 - kHz dB s 1/fs FR - 8 22 48 - Hz Hz Hz Note: 10. The passband and stopband frequencies scale with fs. 11. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register for ADC. M0067-E-02 2004/01 -6- ASAHI KASEI [AK5353] DIGITAL CHARACTERISTICS (CMOS level input) (Ta=25C; VA, VD=2.75.5V; TTL="L") Parameter Symbol min typ High-Level input voltage VIH 0.7xVD Low-Level input voltage VIL VOH VD-0.5 High-Level output voltage (Iout=-100A) VOL Low-Level output voltage (Iout=100A) Input leakage current (exclude TST pin) Iin - Max 0.3xVD 0.5 10 Units V V V V A DIGITAL CHARACTERISTICS (TTL level input; except for TTL pin) (Ta=25C; VA, VD=4.55.5V; TTL="H") Parameter Symbol min typ Max High-Level input voltage (TTL pin) VIH 0.7xVD (All pins except for TTL pin) VIH 2.2 Low-Level input voltage (TTL pin) VIL 0.3xVD (All pins except for TTL pin) VIL 0.8 VOH High-Level output voltage (Iout=-100A) VD-0.5 0.5 VOL Low-Level output voltage (Iout=100A) Input leakage current (exclude TST pin) Iin 10 Units V V V V V V A M0067-E-02 2004/01 -7- ASAHI KASEI [AK5353] SWITCHING CHARACTERISTICS (VD=4.55.5V) (Ta=25C; VA, VD=4.55.5V; CL=20pF) Parameter Symbol min typ Control Clock Frequency 12.288 1.024 fCLK Master Clock 256fs: 16 tCLKL Pulse Width Low 16 tCLKH Pulse Width High 18.432 1.536 fCLK 384fs: 10 fCLKL Pulse Width Low 10 fCLKH Pulse Width High 24.576 2.048 fCLK 512fs: 16 fCLKL Pulse Width Low 16 fCLKH Pulse Width High fSLK SCLK Frequency 48 4 fs LRCK Frequency (Note 12) Serial Interface Timing 160 tSLK SCLK Period 65 tSLKL SCLK Pulse Width Low 65 tSLKH Pulse Width High 30 tLRSH LRCK Edge to SCLK "" (Note 13) 30 tSHLR SCLK "" to LRCK Edge (Note 13) tDLR LRCK Edge to SDTO Valid (Note 14) tDSS SCLK "" to SDTO Valid Power-Down & Reset Timing PDN Pulse Width tPDW 150 tPDV 4129 PDN "" to SDTO delay (Note 15) max Units 24.576 6.144 96 MHz ns ns MHz ns ns MHz ns ns MHz kHz 50 50 ns ns ns ns ns ns ns 36.864 24.576 ns 1/fs Note: 12. Refer to the operating overview section "Serial Data Interface". 13. SCLK rising edge must not occur at the same time as LRCK edge. 14. In case of MSB justified format. 15. These cycles are the number of LRCK rising from PDN falling. M0067-E-02 2004/01 -8- ASAHI KASEI [AK5353] SWITCHING CHARACTERISTICS (VD=2.74.5V) (Ta=25C; VA=2.75.5V, VD=2.74.5V; CL=20pF) Parameter Symbol min typ Control Clock Frequency 1.024 fCLK Master Clock 256fs: 32 tCLKL Pulse Width Low 32 tCLKH Pulse Width High 1.536 fCLK 384fs: 21 fCLKL Pulse Width Low 21 fCLKH Pulse Width High 2.048 fCLK 512fs: 16 fCLKL Pulse Width Low 16 fCLKH Pulse Width High fSLK SCLK Frequency 4 fs LRCK Frequency (Note 12) Serial Interface Timing 160 tSLK SCLK Period 65 tSLKL SCLK Pulse Width Low 65 tSLKH Pulse Width High 30 tLRSH LRCK Edge to SCLK "" (Note 13) 30 tSHLR SCLK "" to LRCK Edge (Note 13) tDLR LRCK Edge to SDTO Valid (Note 14) tDSS SCLK "" to SDTO Valid Power-Down & Reset Timing PDN Pulse Width tPDW 150 tPDV 4129 PDN "" to SDTO delay (Note 15) max Units 12.288 6.144 48 MHz ns ns MHz ns ns MHz ns ns MHz kHz 50 50 ns ns ns ns ns ns ns 18.432 24.576 ns 1/fs Note: 12. Refer to the operating overview section "Serial Data Interface". 13. SCLK rising edge must not occur at the same time as LRCK edge. 14. In case of MSB justified format. 15. These cycles are the number of LRCK rising from PDN falling. M0067-E-02 2004/01 -9- ASAHI KASEI [AK5353] Timing Diagram 1/fCLK VIH MCLK VIL tCLKH tCLKL 1/fs VIH LRCK VIL tSLK VIH SCLK VIL tSLKL tSLKH Clock Timing VIH LRCK VIL tSHLR tLRSH VIH SCLK VIL tDLR tDSS SDTO 50%VD Serial Interface Timing tPDW VIH PDN VIL tPDV SDTO 50%VD Power-down & Reset Timing M0067-E-02 2004/01 - 10 - ASAHI KASEI [AK5353] OPERATION OVERVIEW System Clock Input The external clocks which are required to operate the AK5353 are MCLK (256fs/384fs/512fs), LRCK (1fs), SCLK. MCLK should be synchronized with LRCK but the phase is not critical. When 384fs or 512fs clock is input to MCLK pin, the internal master clock becomes 256fs(=384fs*2/3=512fs*1/2). Table 1 illustrates standard audio word rates and corresponding frequencies used in the AK5353. All external clocks (MCLK, SCLK, LRCK) should always be present whenever the AK5353 is in normal operation mode (PDN="H"). If these clocks are not provided, the AK5353 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK5353 should be in the power-down mode (PDN="L"). After exiting reset at power-up etc., the AK5353 is in the power-down mode until MCLK and LRCK are input. fs 32.0kHz 44.1kHz 48.0kHz 96.0kHz 256fs 8.1920MHz 11.2896MHz 12.2880MHz 24.5760MHz MCLK 384fs 512fs 32fs 12.2880MHz 16.3840MHz 1.0240MHz 16.9344MHz 22.5792MHz 1.4112MHz 18.4320MHz 24.5760MHz 1.5360MHz 36.8640MHz N/A 3.0720MHz Table 1. Example of System Clock SCLK 64fs 2.0480MHz 2.8224MHz 3.0720MHz 6.1440MHz 128fs 4.0960MHz 5.6448MHz 6.1440MHz N/A Serial Data Interface 2 kinds of data format can be selected by DIF pin. The data is clocked out via the SDTO pin by SCLK corresponding to the setting of DIF pin. The format of output data is 2's complement MSB first. Mode 0 1 DIF 0 1 Format 24bit, MSB justified, L/R, SCLK 48fs (16bit, MSB justified, L/R, SCLK 32fs) 24bit, I2S, SCLK 48fs (16bit, I2S, SCLK 32fs) Table 2. Audio Serial Interface Formats M0067-E-02 2004/01 - 11 - ASAHI KASEI [AK5353] LRCK 0 1 22 2 23 25 24 31 0 1 22 2 23 25 24 31 0 1 SCLK SDTO 23 22 21 1 0 23 22 21 23:MSB, 0:LSB 1 0 23 22 23:MSB, 0:LSB Lch Data Rch Data Figure 1. Mode 0 Timing LRCK 0 1 2 22 23 24 25 31 0 1 2 22 23 24 25 31 0 1 SCLK SDTO 23 22 2 1 0 23 22 23:MSB, 0:LSB 2 1 0 23 23:MSB, 0:LSB Lch Data Rch Data Figure 2. Mode 1 Timing M0067-E-02 2004/01 - 12 - ASAHI KASEI [AK5353] Power down The AK5353 is placed in the power-down mode by bringing PDN "L" and the digital filter is also reset at the same time. This reset should always be done after power-up. In the power-down mode, the VREF and VCOM are AGND level. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 4129 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2's complement "0". The ADC outputs settle in the data corresponding to the input signals after the end of initialization (Settling approximately takes the group delay time). 4129/fs(86.021ms@fs=48kHz) PDN Internal State Normal Operation Power-down Initialize Normal Operation GD (1) GD A/D In (Analog) A/D Out (Digital) Clock In MCLK,LRCK,SCLK (2) "0"data Idle Noise "0"data Idle Noise (3) Notes: (1) Digital output corresponding to analog input has the group delay (GD). (2) A/D output is "0" data at the power-down state. (3) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5353 should be in the power-down state. Figure 3. Power-down/up sequence example System Reset The AK5353 should be reset once by bringing PDN "L" after power-up. The internal timing starts clocking by the rising edge (falling edge at mode1) of LRCK upon exiting from reset. M0067-E-02 2004/01 - 13 - ASAHI KASEI [AK5353] SYSTEM DESIGN Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. 4.7u Rch In 470 + 2.2n 4.7u Lch In 470 + 2.2n 4.7u 0.1u + 4.7u AINR TST 16 2 AINL TTL 15 3 VREF DIF 14 4 VCOM 5 AGND Top View SCLK 12 6 VA MCLK 11 7 VD LRCK 10 8 DGND SDTO AK5353 0.1u + 10u + Analog 5V 1 10u + Mode Control Power-down Control PDN 13 0.1u Controller 0.1u 9 Analog Ground System Ground Figure 4. Typical Connection Diagram Note: The value of electrolytic capacitor at VCOM depends on the low-frequency noise of power supply. Digital Ground Analog Ground System Controller 1 AINR TST 16 2 AINL TTL 15 3 VREF 4 VCOM DIF 14 AK5353 PDN 13 5 AGND SCLK 12 6 VA MCLK 11 7 VD LRCK 10 8 DGND SDTO 9 Figure 5. Ground Layout Note: AGND and DGND must be connected to the same analog ground plane. M0067-E-02 2004/01 - 14 - ASAHI KASEI [AK5353] 1. Grounding and Power Supply decoupling The AK5353 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is not critical. AGND and DGND of the AK5353 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5353 as possible, with the small value ceramic capacitor being the nearest. 2. On-chip voltage reference The voltage input to VA sets the analog input range. VREF and VCOM are 55%VA and normally connected to VA with a 0.1F ceramic capacitor. An electrolytic capacitor 4.7F parallel with a 0.1F ceramic capacitor attached to VREF and VCOM pins eliminates the effects of high frequency noise. No load current may be drawn from these pins. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the AK5353. 3. Analog Inputs The ADC inputs are single-ended and internally biased to the common voltage (55%VA) with 100k (typ) resistance. The input signal range scales with the supply voltage and nominally 0.6xVA Vpp. The ADC output data format is 2's complement. The output code is 7FFFFFH(@24bit) for input above a positive full scale and 800000H(@24bit) for input below a negative full scale. The ideal code is 000000H(@24bit) with no input signal. The DC offset is removed by the internal HPF. The AK5353 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. A simple RC filter (fc=150kHz) may be used to attenuate any noise around 64fs and most audio signals do not have significant energy at 64fs. M0067-E-02 2004/01 - 15 - ASAHI KASEI [AK5353] PACKAGE 16pin TSSOP (Unit: mm) *5.0 16 1.10max 9 *4.4 6.40.2 A 1 0.220.1 8 0.65 0.170.05 0.10.1 0.50.2 Detail A Seating Plane 1.0 0.10 NOTE: Dimension "*" does not include mold flash. 0-10 Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder plate M0067-E-02 2004/01 - 16 - ASAHI KASEI [AK5353] MARKING AKM 5353VT XXYYY 1) 2) 3) 4) Pin #1 indication Date Code : XXYYY (5 digits) XX: lot# YYY: Date Code Marketing Code : 5353VT Asahi Kasei Logo IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. M0067-E-02 2004/01 - 17 -