ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 1 -
GENERAL DESCRIPTION
The AK5353 is a stereo A/D Converter with wi de sampling rate of 4kHz∼96kHz and is suitable for
multimedi a audio system. The AK5353 achieves high ac curacy and low cost by using Enhanced du al bit
∆Σ techniques. The AK5353 requires no external components because the analog in puts are
single-ended. The audio interface has two formats (MSB justified, I2S) and can correspond to many
systems li ke Karaoke, surround.
FEATURES
Stereo ∆Σ ADC
On-Chip Digital Anti-Alias Filtering
Single-ended Input
Digital HPF for DC-Offs e t cancel
S/(N+D): 84dB@5V, 80dB@3V for 48kHz
DR: 96dB@5V, 92dB@3V for 48kHz
S/N: 96dB@5V, 92dB@3V for 48kHz
Sampling Rate Ranging from 4kHz to 96kHz
Master Clock:
256fs/384fs/512fs (∼48kHz)
256fs/384fs (∼96kHz)
Low Power Dissipation: 70mW
Small 16pin TSSOP Package
Pow er Supply: 2.7∼5.5V (∼48kHz)
4.5∼5.5V (∼96kHz)
Ta=-40∼85°C
Input level: TTL/CMOS selectable
Output format: 24bit MSB justified / I2S selectable
∆Σ
Modulator
MCLK
AINL LRCK
SCLK
SDTO
PDN DIF
VCOM
Clock Divider
AINR
AGND VA
Decimation
Filter
Serial I/O
Interface
Voltage Reference
TTL
DGNDVD
TST
VREF
∆Σ
Modulator Decimation
Filter
96kHz 24Bit ∆Σ ADC with Single–ended Input
AK5353
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 2 -
Ordering Guide
AK5353VT −40 ∼ +85°C 16pin TSSOP
AKD5353 Evaluation Board
Pin Layout
1
A
INR
A
INL
VCOM
VREF
A
GND
VA
VD
DGND
Top
View
2
3
4
5
6
7
8
TST
TTL
PDN
DIF
SCLK
MCLK
LRCK
SDTO
16
15
14
13
12
11
10
9
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 3 -
PIN/FUNCTION
No. Pin Name I/O Description
1 AINR I Rch Analog Input Pin
2 AINL I Lch Analog Input Pin
3 VREF O Voltage Reference Output Pin
Normally connected to AGND with a 0.1µF ceramic capacitor
in parallel with an el ec trolytic capacitor less than 4.7µF.
4 VCOM O Common Voltage Output Pin
Normally connected to AGND with a 0.1µF ceramic capacitor
in parallel with an electrolytic capaci tor less than 4.7µF.
5 AGND - Analog Ground Pin, 0V
6 VA - Analog Power Supply Pin, +2.7 ∼ +5.5V
7 VD - Digital Power Supply Pin, +2.7 ∼ +5.5V
8 DGND - Digital Ground Pin, 0V
9 SDTO O Serial Data Output Pin
Data bits are presented MSB first, in 2’s complement format.
This pin is “L” in the power-down mode.
10 LRCK I Left/Right Channel Select Pin
The fs clock is input to this pin.
11 MCLK I Master Clock Input Pin
12 SCLK I Serial Data Input Pin
Output data is clocked out on the falling edge of SCLK.
13 PDN I Power-Down Pin
When “L”, the circuit is in power-down mode.
The AK5353 should always be reset upon power-up.
14 DIF I Serial Interface Format Pin
“L”: MSB justified, “H”: I2S
15 TTL I Digital Input Level Sele ct Pin
“L”: CMOS level (VA, VD=2.7 ∼ 5.5V), “H”: TTL level (VA, VD=4.5 ∼ 5.5V)
16 TST I Test Pin (Internal pull-down pin)
This pin should be left floating.
Note: All input pins except pull-down pins should not be left floating.
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 4 -
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND=0V; Note 1)
Parameter Symbol min max Units
Power Supplies
Analog (VA pin)
Digital (VD pin)
|AGND − DGND|
VA
VD
∆GND
−0.3
−0.3
-
6.0
6.0
0.3
V
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Analog Input Voltage (AINL, AINR pins) VINA −0.3 VA+0.3 V
Digital Input Voltage VIND −0.3 VD+0.3 V
Ambient Temperature Ta −40 85 °C
Storage Tem perature Tstg −65 150 °C
Note: 1. All voltages with respect to ground.
2. AGND and DGND must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (fs=48kHz)
(AGND, DGND=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies
(Note 3) Analog
Digital VA
VD 2.7
2.7 5.0
5.0 5.5
VA V
V
Sampling Rate fs 4 48 kHz
Note: 1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
RECOMMENDED OPERATING CONDITIONS (fs=96kHz)
(AGND, DGND=0V; Note 1)
Parameter Symbol min typ max Units
Power Supplies
(Note 3) Analog
Digital VA
VD 4.5
4.5 5.0
5.0 5.5
VA V
V
Sampling Rate fs 4 96 kHz
Note: 1. All voltages with respect to ground.
3. The power up sequence between VA and VD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 5 -
ANALOG CHARACTERISTICS
(Ta=25°C; VA, VD=5V; fs=48kHz; I/F format=Mode 0; Signal Frequency =1kHz;
Measurement band width=20Hz∼20kHz; unless otherwise specified)
Parameter min typ max Units
ADC Analog Input Characteristics: Analog source impedance=470Ω (BW=40Hz∼40kHz at fs=96kHz)
Resolution 24 Bits
S/(N+D) (−1dBFS) (Note 4) fs=48kHz, VA=5V
fs=48kHz, VA=3V
fs=96kHz, VA=5V
75
75
-
84
84
84
dB
dB
dB
DR (−60dBFS) (Note 5) fs=48kHz, VA=5V, A-weighted
fs=48kHz, VA=3V, A-weighted
fs=96kHz, VA=5V
90
86
-
96
92
93
dB
dB
dB
S/N fs=48kHz, VA=5V, A-weighted
fs=48kHz, VA=3V, A-weighted
fs=96kHz, VA=5V
90
86
-
96
92
93
dB
dB
dB
Interchannel Isolat ion 78 90 dB
DC Accuracy
Interchannel Gain Mismatch 0.1 0.3 dB
Gain Drift 100 150 ppm/°C
Input Voltage (Note 6) 2.7 3.0 3.3 Vpp
Input Resistance (Note 7) 40 60 kΩ
Power Supply Rejection (Note 8) - 30 dB
Power Supplies
Power Supply Current
Normal Operation (PDN=“H”)
VA+VD (Note 9)
Power-Down Mode (PDN=“L”)
VA+VD
14
10
21
100
mA
µA
Note: 4. The ratio of the rm s value of the si gnal to the rm s sum of all the spectral com ponents less than 20kHz bandwidth,
including distortion com ponents.
5. S/(N+D) which is measured with an input signal of −60dB below full-scale.
6. This value is the full scale(0dB) of the input voltage.
Input voltage is proportional to VA. (Vin=0.6xVA)
7. 40kΩ(typ) and 25kΩ(min) at fs=96kHz.
8. PSR is applied to VA, VD with 1kHz, 50mVpp.
9. VA=11mA; VD=3mA@48kHz,5V, 1.5mA@48kHz,3V, 6mA@96kHz,5V (typ).
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 6 -
FILTER CHARACTERISTICS (fs=48kHz)
(Ta=25°C; VA, VD=2.7∼5.5V; fs=48kHz)
Parameter Symbol min typ max Units
Digital Filter (Decimation LPF)
Passband (Note 10) ±0.1dB
−0.2dB
−1.0dB
−3.0dB
PB 0
-
-
-
20.0
21.8
23.0
18.9
-
-
-
kHz
kHz
kHz
kHz
Stopband (Note 10) SB 29.4 kHz
Stopband Attenuation SA 65 dB
Group Delay Distortion ∆GD 0
µs
Group Delay (Note 11) GD - 17.0 - 1/fs
Digital Filter (HPF)
Frequency Response: −3dB
−0.5dB
−0.1dB
FR -
-
-
4
11
24
-
-
-
Hz
Hz
Hz
Note: 10. The passband and stopband frequencies scale with fs.
11. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal
to setting the 24bit data of both channels to the output register for ADC.
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25°C; VA, VD=4.5∼5.5V; fs=96kHz)
Parameter Symbol min typ max Units
Digital Filter (Decimation LPF)
Passband (Note 10) ±0.1dB
−0.2dB
−1.0dB
−3.0dB
PB 0
-
-
-
40.0
43.6
46.0
37.8
-
-
-
kHz
kHz
kHz
kHz
Stopband (Note 10) SB 58.8 kHz
Stopband Attenuation SA 65 dB
Group Delay Distortion ∆GD 0
µs
Group Delay (Note 11) GD - 17.0 - 1/fs
Digital Filter (HPF)
Frequency Response: −3dB
−0.5dB
−0.1dB
FR -
-
-
8
22
48
-
-
-
Hz
Hz
Hz
Note: 10. The passband and stopband frequencies scale with fs.
11. The calculating delay time which occurred by digital filtering. This tim e is from the input of analog signal
to setting the 24bit data of both channels to the output register for ADC.
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 7 -
DIGITAL CHARACTERISTICS (CMOS level input)
(Ta=25°C; VA, VD=2.7∼5.5V; TTL=“L”)
Parameter Symbol min typ Max Units
High-Level input volt age
Low-Level input voltage VIH
VIL 0.7xVD
- -
- -
0.3xVD V
V
High-Level output voltage (Iout=−100µA)
Low-Level output voltage (Iout=100µA) VOH
VOL VD−0.5
- -
- -
0.5 V
V
Input leakage current (exclude TST pin) Iin - - ±10 µA
DIGITAL CHARACTERISTICS (TTL level input; except for TTL pin)
(Ta=25°C; VA, VD=4.5∼5.5V; TTL=“H”)
Parameter Symbol min typ Max Units
High-Level input vol tage (TTL pin)
(All pins except for TTL pin)
Low-Level input volt age (TTL pin)
(All pins except for TTL pin)
VIH
VIH
VIL
VIL
0.7xVD
2.2
-
-
-
-
-
-
-
-
0.3xVD
0.8
V
V
V
V
High-Level output voltage (Iout=−100µA)
Low-Level output voltage (Iout=100µA) VOH
VOL VD−0.5
- -
- -
0.5 V
V
Input leakage current (exclude TST pin) Iin - - ±10 µA
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 8 -
SWITCHING CHARACTERISTICS (VD=4.5∼5.5V)
(Ta=25°C; VA, VD=4.5∼5.5V; CL=20pF)
Parameter Symbol min typ max Units
Control Clock Frequency
Master Clock 256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
SCLK Frequency
LRCK Frequency
fCLK
tCLKL
tCLKH
fCLK
fCLKL
fCLKH
fCLK
fCLKL
fCLKH
fSLK
fs
1.024
16
16
1.536
10
10
2.048
16
16
4
12.288
18.432
24.576
48
24.576
36.864
24.576
6.144
96
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
kHz
Serial Interface Timing (Note 12)
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑” (Note 13)
SCLK “↑” to LRCK Edge (Note 13)
LRCK Edge to SDTO Valid (Note 14)
SCLK “↓” to SDTO Valid
tSLK
tSLKL
tSLKH
tLRSH
tSHLR
tDLR
tDSS
160
65
65
30
30
50
50
ns
ns
ns
ns
ns
ns
ns
Power-Down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO delay (Note 15)
tPDW
tPDV
150
4129
ns
1/fs
Note: 12. Refer to the operating overview section “Serial Data Interface”.
13. SCLK rising edge must not occur at the same time as LRCK edge.
14. In case of MSB justified format.
15. These cycles are the number of LRCK rising from PDN falling.
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 9 -
SWITCHING CHARACTERISTICS (VD=2.7∼4.5V)
(Ta=25°C; VA=2.7∼5.5V, VD=2.7∼4.5V; CL=20pF)
Parameter Symbol min typ max Units
Control Clock Frequency
Master Clock 256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
SCLK Frequency
LRCK Frequency
fCLK
tCLKL
tCLKH
fCLK
fCLKL
fCLKH
fCLK
fCLKL
fCLKH
fSLK
fs
1.024
32
32
1.536
21
21
2.048
16
16
4
12.288
18.432
24.576
6.144
48
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
kHz
Serial Interface Timing (Note 12)
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK “↑” (Note 13)
SCLK “↑” to LRCK Edge (Note 13)
LRCK Edge to SDTO Valid (Note 14)
SCLK “↓” to SDTO Valid
tSLK
tSLKL
tSLKH
tLRSH
tSHLR
tDLR
tDSS
160
65
65
30
30
50
50
ns
ns
ns
ns
ns
ns
ns
Power-Down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTO delay (Note 15)
tPDW
tPDV
150
4129
ns
1/fs
Note: 12. Refer to the operating overview section “Serial Data Interface”.
13. SCLK rising edge must not occur at the same time as LRCK edge.
14. In case of MSB justified format.
15. These cycles are the number of LRCK rising from PDN falling.
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 10 -
Timing Diagram 1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
1/fs
VIH
LRCK VIL
tSLK
tSLKL
VIH
tSLKH
SCLK VIL
Clock Timing
tSHLR
VIH
LRCK VIL
tLRSH
VIH
SCLK VIL
tDLR
SDTO
tDSS
50%VD
Serial Interface Timing
tPDW
VIL
PDN
tPDV
SDTO 50%VD
VIH
Power-down & Reset Timing
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 11 -
OPERATION OVERVIEW
System Clock Input
The external clocks whi ch are required to operate the AK5353 are MCLK (256fs/384fs/512fs), LRCK (1fs), SCLK.
MCLK should be synchronized with LRC K but the phase is not criti cal. When 384fs or 512fs clock is input to MCLK pin,
the internal m aster clock becomes 256fs(=384fs*2/3=512fs*1/2). Table 1 illustrates standard audio word rates and
corresponding frequencies used in the AK5353.
All externa l clocks (M CLK, SCLK, LRCK) should always be present whenever the AK5353 is i n normal opera tion mode
(PDN=“H”). If thes e clocks are not provided, the AK5353 may draw excess current and may not possibly operate
properly beca use the device util izes dynami c refreshed logic internall y. If the external clocks are not present, the AK5353
should be in the power-down mode (PDN=“L”). After exiting reset at power-up etc., the AK5353 is in the power-down
mode until M CLK and LRCK are input.
MCLK SCLK
fs 256fs 384fs 512fs 32fs 64fs 128fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 1.0240MHz 2.0480MHz 4.0960MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 1.4112MHz 2.8224MHz 5.6448MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 1.5360MHz 3.0720MHz 6.1440MHz
96.0kHz 24.5760MHz 36.8640MHz N/A 3.0720MHz 6.1440MHz N/A
Table 1. Example of System Clock
Serial Data Interface
2 kinds of data format can be selected by DIF pin. The data is clocked out via the SDTO pin by SCLK corresponding to
the setting of DIF pin. The format of output data is 2’s complement MSB first.
Mode DIF Format
0 0
24bit, MSB justified, L/R, SCLK ≥48fs (16bit, MSB justified, L/R, SCLK ≥32fs)
1 1
24bit, I2S, SCLK ≥48fs (16bit, I2S, SCLK ≥32fs)
Table 2. Audio Serial Interface Formats
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
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SDTO
Lch Data
SCLK
LRCK
23 22 21 1 0 1 0 23 2223 22 21
01 22 23
224 25 31 01 22 23
224 25 31 01
23:MSB, 0:LSB
Rch Data
23:M SB, 0:LSB
Figure 1. Mode 0 Timing
SDTO
Lch Data
SCLK
LRCK
23 22 2 1 0 1 0 2323 22 2
01 22 23
224 25 31 01 22 23
224 25 31 01
23:MSB, 0:LSB
Rch Data
23:MSB, 0:LSB
Figure 2. Mode 1 Timing
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 13 -
Power down
The AK5353 is plac ed i n t he power-down mode by bri ngi ng PDN “ L ” and the di gi ta l fi l te r is a lso reset at the sa m e ti m e .
This reset should always be done after power-up. In the power-down mode, the VREF and VCOM are AGND level. An
analog initia lizat ion cycl e sta rts after exit ing the powe r-down mode. Therefore, t he output dat a SDTO becomes avai lable
after 4129 cycles of LR CK clock. During ini t ial iz at ion, t he ADC digit a l dat a outputs of both channel s are forced to a 2’s
complement “0”. The ADC outputs settle in the data corresponding to the input signals after the end of initialization
(Settling approximately takes the group delay time).
Normal Operation
Internal
State
PDN
Power-down Initialize Normal Operation
4129/fs(86.021ms@fs=48kHz)
Idle N o is e
GD GD
“0”data
A
/D In
(Analog)
A
/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(1)
(2)
(3)
“0”data Idle No ise
Notes:
(1) Digital output corresponding to analog input has the group delay (GD).
(2) A/D output is “0” data at the power-down state.
(3) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5353 should be in the power-down state.
Figure 3. Power-down/up sequence example
System Reset
The AK5353 should be reset once by bri nging P DN “L” after power-up. The i nt ernal t iming start s cloc king by the risi ng
edge (falling edge at mode1) of LRCK upon exiting from reset.
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
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SYSTEM DESIGN
Figure 4 shows the syste m connecti on diagram. An e valuation board is avail able which demonst rates application ci rcuits,
the optimum layout, power supply arrangements and measurement results.
A
INR1
4.7u
2.2n
470
A
INL2
VREF3
VCOM4
A
GND5
VA6
VD7
DGND8
16
15
14
13
12
11
10
9
TST
TTL
DIF
PDN
SCLK
MCLK
LRCK
SDTO
AK5353
Top View
4.7u
2.2n
470
+
+
0.1u
4.7u
0.1u
4.7u ++
+
+
0.1u
10u
0.1u
10u
Rch In
Lch In
Analog 5V
Mode Control
Controller
Sy stem GroundAnalog Ground
Power-down Control
Figure 4. Typical Connection Diagram
Note: The value of electrolytic capacitor at VCOM depends on the low-frequency noise of power supply.
Analog GroundDigital Ground
System
Controller
A
INR1
A
INL2
VREF3
VCOM4
A
GND5
V
A
6
VD7
DGND8
16
15
14
13
12
11
10
9
TST
TTL
DIF
PDN
SCLK
MCLK
LRCK
SDTO
AK5353
Figure 5. Ground Layout
Note: AGND and DGND must be connected to the same analog ground plane.
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
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1. Grounding and Power Supply decoupling
The AK5353 requires careful att e ntion to power supply and grounding arrangements. VA and VD are usually supplied
from anal og suppl y in system. Alternat i vel y i f VA a nd VD are suppl ie d sepa ratel y , t he power up sequenc e i s not c riti c al .
AGND and DGND of the AK5353 must be connected to analog ground p lan e. System analog ground and digital
ground should be connected toget her near to where the supplies are brought onto the printed ci rcuit board. Decoupling
capacitors should be as near to the AK5353 as possible, with the smal l value ceram ic capacitor being the nearest.
2. On-chip voltage reference
The voltage i nput to VA se ts t he ana log input range. VR EF and V COM a re 55%VA and norm a ll y c onnected t o VA wit h
a 0.1µF cerami c capacitor. An elec trolyti c capacitor 4.7µF paralle l with a 0.1µF cera mi c capa citor att ached t o VREF and
VCOM pins eliminates the effects of high frequency noise. No load current may be drawn from these pins. All signals,
especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the
AK5353.
3. Analog Inputs
The ADC inputs are single-ended and internally biased to the common voltage (55%VA) with 100kΩ (typ) resistance.
The input signal range sca les with the supply voltage a nd nominally 0.6xVA Vpp. The ADC output data format is 2’s
complem e nt . The output code i s 7FF FFFH(@24bi t) for input above a posit ive full scale and 800000H(@24bit) for i nput
below a negative full scale. The ideal code is 000000H(@24bit) wi th no input signal. The DC offset is removed by the
internal HPF.
The AK5353 samples the analog inputs at 64fs. The digital fi lter rejects noise above the stop band except for m ultiples of
64fs. A sim ple RC filte r (fc=150kHz) m ay be use d to att enuate any noise around 64fs and m ost audio si gnals do not ha ve
significant energy at 64fs.
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 16 -
PACKAGE
0.1±0.1
0-10°
Detail A
Seating Plane
NOTE: Dimension "*" does not include mold flash.
0.10
0.17
±
0.05
0.22±0.1 0.65
*5.0 1.10max
A
18
916
16
p
in TSSOP
(
Unit: mm
)
*4.4
6.4±0.2
0.5±0.2
1.0
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
ASAHI KASEI [AK5353]
M0067-E-02 2004/01
- 17 -
MARKING
AKM
5353VT
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: lot#
YYY: Date Code
3) Marketing Code : 5353VT
4) Asahi Kasei Logo
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or applic ation, consult the As ahi Kasei M icros ystems Co., Lt d. (A KM) s ales of fice or author ized
distr ibutor concerni ng their current s tatus.
• AKM as sumes no liability f or infringement of any patent, intellec tual property, or ot her right in the
applicat ion or use of any informat ion contained herein.
• Any export of thes e products, or devices or systems containing them, may require an export li cense
or other official approval under the law and regulations of the country of export pertaining to customs
and tarif fs, currenc y exchange, or st rategic materi als.
• AKM product s are neither int ended nor authorized f or use as crit ical component s in any safet y, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the expres s written consent of the Represent ative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safet y or for applicati ons in medicine, aerospace, nuc lear energy, or other fie lds, in which it s
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to per son or property.
b. A critical compon ent is one whose fail ure to functi on or perf orm may reas onably be expec ted t o
result , whether direc tly or indirect ly, in the loss of the safety or ef fectivenes s of the devic e or
syst em containing it, and which must theref ore meet very high st andards of perform ance and
reliability.
• It is the respons ibility of the buyer or dis tributor of an AKM pro duct who dist ributes, dispo ses of , or
otherwise places the product with a third party to notify that party in advance of the above content and
conditi ons, and the buyer or dist ributor agrees to as sume any and all respons ibility and liabi lity for
and hold AKM harmles s from any and all claims ar ising from the us e of said product in the absence
o f s u ch notification.
