General Description
The MAX17017 is a quad-output controller for ultra-
mobile portable computers (UMPCs) that rely on a low-
power architecture. The MAX17017 provides a compact,
low-cost controller capable of providing four indepen-
dent regulators—a main stage, a 3AP-P internal step-
down, a 5AP-P internal step-down, and a 2A source/sink
linear regulator.
The main regulator can be configured as either a step-
down converter (for 2 to 4 Li+ cell applications) or as a
step-up converter (for 1 Li+ cell applications). The inter-
nal switching regulators include 5V synchronous
MOSFETs that can be powered directly from a single Li+
cell or from the main 3.3V/5V power stages. Finally, the
linear regulator is capable of sourcing and sinking 2A to
support DDR termination requirements or to generate a
fixed output voltage.
The step-down converters use a peak current-mode,
fixed-frequency control scheme—an easy to implement
architecture that does not sacrifice fast-transient
response. This architecture also supports peak current-
limit protection and pulse-skipping operation to maintain
high efficiency under light-load conditions.
Separate enable inputs and independent open-drain
power-good outputs allow flexible power sequencing. A
soft-start function gradually ramps up the output volt-
age to reduce the inrush current. Disabled regulators
enter high-impedance states to avoid negative output
voltage created by rapidly discharging the output
through the low-side MOSFET. The MAX17017 also
includes output undervoltage, output overvoltage, and
thermal-fault protection.
The MAX17017 is available in a 48-pin, 6mm x 6mm
thin QFN package.
Applications
1-to-4 Li+ Cell Battery-Powered Devices
Low-Power Architecture
Ultra-Mobile PC (UMPC)
Portable Gaming
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
Features
oFixed-Frequency, Current-Mode Controllers
o5.5V to 28V Input Range (Step-Down) or 3V to 5V
Input Range (Step-Up)
o1x Step-Up or Step-Down Controller
o1x Internal 5AP-P Step-Down Regulator
o1x Internal 3AP-P Step-Down Regulator
o1x 2A Source/Sink Linear Regulator with Dynamic
REFIN
oInternal BST Diodes
oInternal 5V, 50mA Linear Regulator
oFault Protection—Undervoltage, Overvoltage,
Thermal, Peak Current Limit
oIndependent Enable Inputs and Power-Good
Outputs
oVoltage-Controlled Soft-Start
oHigh-Impedance Shutdown
o10µA (typ) Shutdown Current
MAX17017
Quad-Output Controller for
Low-Power Architecture
________________________________________________________________
Maxim Integrated Products
1
MAX17017
36 35 34 33 32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
16
15
14
13
CSPA
CSNA
AGND
REF
FREQ
UP/DN
INA
VCC
BYP
LDO5
INLDO
SHDN
ONB
SYNC
ONA
INBC
INBC
INBC
INBC
VDD
POKD
OND
ONC
FBC
37
38
39
40
41
42
43
44
45
46
47
48
1
POKC
BSTC
LXC
LXC
LXC
LXC
OUTD
OUTD
IND
FBD
VTTR
REFIND
FBB
POKB
BSTB
LXB
LXB
LXB
DLA
BSTA
LXA
DHA
POKA
FBA
+2 3 4 5 6 7 8 9 10 11 12
EXPOSED PAD = GND
THIN QFN
TOP VIEW
Pin Configuration
Ordering Information
19-4121; Rev 2; 6/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX17017GTM+ -40°C to +105°C 48 TQFN-EP*
MAX17017
Quad-Output Controller for
Low-Power Architecture
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless other-
wise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
INLDO, SHDN to GND............................................-0.3V to +28V
LDO5, INA, VDD, VCC to GND..................................-0.3V to +6V
DHA to LXA .............................................-0.3V to (VBSTA + 0.3V)
ONA, ONB, ONC, OND to GND ...............................-0.3V to +6V
POKA, POKB, POKC, POKD to GND.........-0.3V to (VCC + 0.3V)
REF, REFIND, FREQ, UP/DN,
SYNC to GND ........................................-0.3V to (VCC + 0.3V)
FBA, FBB, FBC, FBD to GND.....................-0.3V to (VCC + 0.3V)
BYP to GND ............................................-0.3V to (VLDO5 + 0.3V)
CSPA, CSNA to GND .................................-0.3V to (VCC + 0.3V)
DLA to GND................................................-0.3V to (VDD + 0.3V)
INBC, IND to GND....................................................-0.3V to +6V
OUTD to GND............................................-0.3V to (VIND + 0.3V)
VTTR to GND.............................................-0.3V to (VBYP + 0.3V)
LXB, LXC to GND ....................................-1.0V to (VINBC + 0.3V)
BSTB to GND ....................................(VDD - 0.3V) to (VLXB + 6V)
BSTC to GND....................................(VDD - 0.3V) to (VLXC + 6V)
BSTA to GND ....................................(VDD - 0.3V) to (VLXA + 6V)
REF Short-Circuit Current......................................................1mA
Continuous Power Dissipation (TA = +70°C)
Multilayer PCB: 48-Pin 6mm x 6mm2TQFN
(T4866-2 derated 37mW/°C above +70°C) ....................2.9W
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
TA = 0°C to +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
UP/DN = GND (step-up), INA 3.0 5.0
Input Voltage Range UP/DN = LDO5 (step-down), INLDO,
INA = LDO5 5.5 24 V
UP/DN = GND (step-up), INA = INLDO,
rising edge hysteresis = 100mV 2.5 2.7 2.9
INA Undervoltage Threshold VINA
(
UVLO
)
UP/DN = LDO5 (step-down), INA = VCC,
rising edge, hysteresis = 160mV 4.0 4.2 4.4
V
INBC Input Voltage Range 2.3 5.5 V
Minimum Step-Up Startup
Voltage UP/DN = GND (step-up) 2.9 3.0 V
SUPPLY CURRENTS
VINLDO Shutdown Supply Current IIN
(
SHDN
)
VIN = 5.5V to 26V, SHDN = GND 10 15 μA
VINLDO Suspend Supply Current IIN(SUS) VINLDO = 5.5V to 26V, ON_ = GND,
SHDN = INLDO 50 80 μA
VCC Shutdown Supply Current SHDN = ONA = ONB = ONC = OND =
GND, TA = +25°C 0.1 1 μA
VDD Shutdown Supply Current SHDN = ONA = ONB = ONC = OND =
GND, TA = +25°C 0.1 1 μA
INA Shutdown Current IINA
SHDN = ONA = ONB = ONC = OND =
GND, UP/DN = VCC 710μA
VCC Supply Current
Main Step-Down Only
ONA = VCC, ONB = ONC = OND = GND;
does not include switching losses,
measured from VCC
210 300 μA
MAX17017
Quad-Output Controller for
Low-Power Architecture
_______________________________________________________________________________________ 3
TA = 0°C to +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
C C
S up p l y C ur r ent
M ai n S tep - D ow n and Reg ul ator B
ONA = ONB = VCC, ONC = OND = GND;
does not include switching losses,
measured from VCC
280 350 μA
V
C C
S up p l y C ur r ent
M ai n S tep - D ow n and Reg ul ator C
ONA = ONC = VCC, ONB = OND = GND;
does not include switching losses,
measured from VCC
280 350 μA
V
C C
S up p l y C ur r ent
M ai n S tep - D ow n and Reg ul ator D
ONA = OND = VCC, ONB = ONC = GND;
does not include switching losses;
measured from VCC
2.2 3 mA
INA Supply Current (Step-Down) IINA ONA = VCC, UP/DN = VCC (step-down) 40 60 μA
IN A + V
C C
S tep - U p S up p l y C ur r ent IINA ONA = VCC, UP/DN = GND (step-up) 320 410 μA
5V LINEAR REGULATOR (LDO5)
LDO5 Output Voltage VLDO5 VINLDO = 5.5V to 26V, ILDO5 = 0 to 50mA,
BYP = GND 4.8 5.0 5.2 V
LDO5 Short-Circuit Current Limit LDO5 = BYP = GND 70 160 250 mA
BYP Switchover Threshold VBYP Rising edge 4.65 V
LDO5-to-BYP Switch Resistance RBYP LDO5 to BYP, VBYP = 5V, ILDO5 = 50mA 1.5 4 _
1.25V REFERENCE
Reference Output Voltage VREF No load 1.237 1.25 1.263 V
Reference Load Regulation _VREF IREF = -1μA to +50μA 3 10 mV
Reference Undervoltage Lockout VREF
(
UVLO
)
1.0 V
OSCILLATOR
FREQ = VCC 500
FREQ = REF 750 kHz
Oscillator Frequency fOSC
FREQ = GND 0.9 1.0 1.1 MHz
fSWA Main step-up/step-down (regulator A) 1/2 fOSC
fSWB Regulator B fOSC
Switching Frequency
fSWC Regulator C 1/2 fOSC
MHz
Maximum Duty Cycle
(All Switching Regulators) DMAX 90 93.5 %
FREQ = VCC or GND 90
Minimum On-Time
(All Switching Regulators) tON(MIN) FREQ = REF 75 ns
REGULATOR A (Main Step-Up/Step-Down)
Step-up configuration (UP/DN = GND) 3.0 VCC +
0.3
Output-Voltage Adjust Range
Step-down configuration (UP/DN = VCC) 1.0 VCC +
0.3
V
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless other-
wise noted. Typical values are at TA= +25°C.) (Note 1)
MAX17017
Quad-Output Controller for
Low-Power Architecture
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless other-
wise noted. Typical values are at TA= +25°C.) (Note 1)
TA = 0°C to +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Step-up configuration (UP/DN = GND),
VCSPA - VCSNA = 0 to 20mV, 90% duty
cycle
0.975 0.99 1.013
FBA Regulation Voltage VFBA
Step-down configuration (UP/DN = VCC),
VCSPA - VCSNA = 0mV, 90% duty cycle 0.968 0.97 1.003
V
Step-up configuration (UP/DN = GND),
VCSPA - VCSNA = 0mV, 90% duty cycle 0.959 1.013
FBA Regulation Voltage
(Overload) VFBA Step-down configuration (UP/DN = VCC),
VCSPA - VCSNA = 0 to 20mV, 90% duty
cycle
0.930 1.003
V
Step-up configuration (UP/DN = GND),
VCSPA - VCSNA = 0 to 20mV -20
FBA Load Regulation ΔVFBA Step-down configuration (UP/DN = VCC),
VCSPA - VCSNA = 0 to 20mV -40
mV
Step-up (UP/DN =
GND) 51016
FBA Line Regulation
UP/DN = GND
or VCC,
0 to 100% duty
cycle
Step-down (UP/DN
= VCC)10 16 22
mV
FBA Input Current IFBA
UP/DN = GND or VCC,
TA = +25°C -100 -5 +100 nA
Current-Sense Input Common-
Mode Range VCSA 0VCC +
0.3V V
Current-Sense Input Bias Current ICSA TA = +25°C 40 60 μA
Current-Limit Threshold (Positive) VILIMA 18 20 22 mV
Idle Mode™ Threshold VIDLEA 4mV
Zero-Crossing Threshold VIZX 1mV
DHA Gate Driver On-Resistance RDH DHA forced high and low 2.5 5 Ω
DLA forced high 2.5 5
DLA Gate Driver On-Resistance RDL DLA forced low 1.5 3 Ω
DHA Gate Driver Source/Sink
Current IDH DHA forced to 2.5V 0.7 A
IDL(SRC) DLA forced to 2.5V 0.7
DLA Gate Driver Source/Sink
Current IDL(SNK) DLA forced to 2.5V 1.5 A
BSTA Switch On-Resistance RBSTA 5Ω
Idle Mode is a trademark of Maxim Integrated Products, Inc.
MAX17017
Quad-Output Controller for
Low-Power Architecture
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless other-
wise noted. Typical values are at TA= +25°C.) (Note 1)
TA = 0°C to +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REGULATOR B (Internal 3A Step-Down Converter)
FBB Regulation Voltage ILXB = 0% duty cycle (Note 2) 0.747 0.755 0.762 V
FBB Reg ul ati on V ol tag e ( Over l oad ) VFBB ILXB = 0 to 2.5A, 0% duty cycle (Note 2) 0.720 0.762 V
FBB Load Regulation ΔVFBB/ΔILXB ILXB = 0 to 2.5A -5 mV/A
FBB Line Regulation 0 to 100% duty cycle 7 8 10 mV
FBB Input Current IFBB TA = +25°C -100 -5 +100 nA
High-side n-channel 75 150
Internal MOSFET On-Resistance Low-side n-channel 40 80 mΩ
LXB Peak Current Limit IPKB 3.0 3.45 4.0 A
LXB Idle-Mode Trip Level IIDLEB 0.8 A
LXB Zero-Crossing Trip Level IZXB 100 mA
LXB Leakage Current ILXB ONB = GND, VLXB = GND or 5V;
VINBC = 5V at TA = +25°C -20 +20 μA
REGULATOR C (Internal 5A Step-Down Converter)
FBC Regulation Voltage ILXC = 0A, 0% duty cycle (Note 2) 0.747 0.755 0.762 V
FBC Reg ul ati on V ol tag e ( Over l oad ) VFBC ILXC = 0 to 4A, 0% duty cycle (Note 2) 0.710 0.762 V
FBC Load Regulation ΔVFBC/ΔILXC ILXC = 0 to 4A -7 mV/A
FBC Line Regulation 0 to 100% duty cycle 12 14 16 mV
FBC Input Current IFBC TA = +25°C -100 -5 +100 nA
High-side n-channel 50 100
Internal MOSFET On-Resistance Low-side n-channel 25 40 mΩ
LXC Peak Current Limit IPKC 5.0 5.75 6.5 A
LXC Idle-Mode Trip Level IIDLEC 1.2 A
LXC Zero-Crossing Trip Level IZXC 100 mA
LXC Leakage Current ILXC ONC = GND, VLXC = GND or 5V;
VINBC = 5V at TA = +25°C -20 +20 μA
REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer)
IND Input Voltage Range VIND 1 2.8 V
IND Supply Current OND = VCC 10 50 μA
IND Shutdown Current OND = GND, TA = +25°C 10 μA
REFIND Input Range 0.5 1.5 V
REFIND Input Bias Current VREFIND = 0 to 1.5V, TA = +25°C -100 +100 nA
OUTD Output Voltage Range VOUTD 0.5 1.5 V
VFBD with respect to VREFIND, OUTD =
FBD, IOUTD = +50μA (source load) -10 0
FBD Output Accuracy VFBD VFBD with respect to VREFIND,
OUTD = FBD, IOUTD = -50μA (sink load) 0 +10
mV
FBD Load Regulation IOUTD = ±1A -17 -13 mV/A
MAX17017
Quad-Output Controller for
Low-Power Architecture
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless other-
wise noted. Typical values are at TA= +25°C.) (Note 1)
TA = 0°C to +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FBD Line Regulation VIND = 1.0V to 2.8V, IOUTD = ±200mA 1 mV
FBD Input Current VFBD = 0 to 1.5V, TA = +25°C 0.1 0.5 μA
Source load +2 +4
OUTD Linear Regulator Current
Limit Sink load -2 -4 A
Current-Limit Soft-Start Time With respect to internal OND signal 160 μs
High-side on-resistance 120 250
Internal MOSFET On-Resistance Low-side on-resistance 180 450 mΩ
IVTTR = ±0.5mA -10 +10
VTTR Output Accuracy REFIND to VTTR IVTTR = ±3mA -20 +20 mV
VTTR Maximum Current Rating ±5 mA
FAULT PROTECTION
Upper threshold
rising edge, hysteresis = 50mV 91214
SMPS POK and Fault Thresholds Lower threshold
falling edge, hysteresis = 50mV -14 -12 -9
%
Upper threshold
rising edge, hysteresis = 50mV 61216
VTT LDO POKD and Fault
Threshold Lower threshold
falling edge, hysteresis = 50mV -16 -12 -6
%
POK Propagation Delay tPOK FB_ forced 50mV beyond POK_ trip
threshold 5μs
Overvoltage Fault Latch Delay tOVP FB_ forced 50mV above POK_ upper trip
threshold 5μs
SMPS Undervoltage Fault
Latch Delay tUVP FBA, FBB, or FBC forced 50mV below
POK_ lower trip threshold 5μs
VTT LDO Undervoltage Fault
Latch Delay tUVP FBD forced 50mV below POKD lower trip
threshold 5000 μs
POK Output Low Voltage VPOK ISINK = 3mA 0.4 V
POK Leakage Currents IPOK
V
F B A = 1.05V , V
F B B = V
F B C
= 0.8V , V
F B D
=
V
R E FI N D
+ 50m V ( P O K hi g h i m p ed ance) ;
POK_ forced to 5V, TA = +25°C
1μA
Thermal-Shutdown Threshold TSHDN Hysteresis = 15°C 160 °C
GENERAL LOGIC LEVELS
SHDN Input Logic Threshold Hysteresis = 20mV 0.5 1.6 V
SHDN Input Bias Current TA = +25°C -1 +1 μA
ON_ Input Logic Threshold Hysteresis = 170mV 0.5 1.6 V
ON_ Input Bias Current TA = +25°C -1 +1 μA
UP/DN Input Logic Threshold 0.5 1.6 V
UP/DN Input Bias Current TA = +25°C -1 +1 μA
MAX17017
Quad-Output Controller for
Low-Power Architecture
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= 0°C to +85°C, unless other-
wise noted. Typical values are at TA= +25°C.) (Note 1)
TA = 0°C to +85°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
High (VCC)V
CC - 0.4V
Unconnected/REF 1.65 3.8
FREQ Input Voltage Levels
Low (GND) 0.5
V
FREQ Input Bias Current TA = +25°C -2 +2 μA
SYNC Input Logic Threshold 1.5 3.5 V
SYNC Input Bias Current TA = +25°C -1 +1 μA
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= -40°C to +105°C.) (Note 1)
TA = -40°C to +105°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
UP/DN = GND (step-up), INA 3.0 5.0
Input Voltage Range UP/DN = LDO5 (step-down), INLDO,
INA = LDO5 5.5 24 V
UP/DN = GND (step-up), INA = INLDO,
rising edge, hysteresis = 100mV 2.4 3.0
INA Undervoltage Threshold VINA(UVLO
)UP/DN = LDO5 (step-down), INA = VCC,
rising edge, hysteresis = 160mV 3.9 4.5
V
INBC Input Voltage Range 2.3 5.5 V
Minimum Step-Up Startup Voltage UP/DN = GND (step-up) 3.0 V
SUPPLY CURRENTS
VINLDO Shutdown Supply Current IIN
(
SHDN
)
VIN = 5.5V to 26V, SHDN = GND 15 μA
VINLDO Suspend Supply Current IIN
(
SUS
)
VINLDO = 5.5V to 26V, ON_ = GND,
SHDN = INLDO 80 μA
INA Shutdown Current IINA
SHDN = ONA = ONB = ONC = OND =
GND, UP/DN = VCC 10 μA
VCC Supply Current
Main Step-Down Only
ONA = VCC, ONB = ONC = OND = GND;
does not include switching losses,
measured from VCC
350 μA
V
C C
S up p l y C ur r ent
M ai n S tep - D ow n and Reg ul ator B
ONA = ONB = VCC, ONC = OND = GND;
does not include switching losses,
measured from VCC
400 μA
V
C C
S up p l y C ur r ent
M ai n S tep - D ow n and Reg ul ator C
ONA = ONC = VCC, ONB = OND = GND,
does not include switching losses,
measured from VCC
400 μA
MAX17017
Quad-Output Controller for
Low-Power Architecture
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= -40°C to +105°C.) (Note 1)
TA = -40°C to +105°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
C C
S up p l y C ur r ent
M ai n S tep - D ow n and Reg ul ator D
ONA = OND = VCC, ONB = ONC = GND,
does not include switching losses,
measured from VCC
3.5 mA
INA Supply Current (Step-Down) IINA ONA = VCC, UP/DN = VCC (step-down) 75
IN A + V
C C S tep - U p S up p l y C ur r ent IINA ONA = VCC, UP/DN = GND (step-up) 475 μA
5V LINEAR REGULATOR (LDO5)
LDO5 Output Voltage VLDO5 VINLDO = 5.5V to 26V, ILDO5 = 0 to 50mA,
BYP = GND 4.75 5.25 V
LDO5 Short-Circuit Current Limit LDO5 = BYP = GND 55 mA
1.25V REFERENCE
Reference Output Voltage VREF No load 1.237 1.263 V
Reference Load Regulation ΔVREF IREF = -1μA to +50μA 12 mV
OSCILLATOR
Oscillator Frequency fOSC FREQ = GND 0.9 1.1 MHz
Maximum Duty Cycle
(All Switching Regulators) DMAX 89 %
REGULATOR A (Main Step-Up/Step-Down)
Step-up configuration (UP/DN = GND) 3.0 VCC +
0.3V
Output-Voltage Adjust Range
Step-down configuration (UP/DN = VCC) 1.0 VCC +
0.3V
V
Step-up configuration,
VCSPA - VCSNA = 0mV, 90% duty cycle 0.970 1.018
FBA Regulation Voltage Step-down configuration,
VCSPA - VCSNA = 0mV, 90% duty cycle 0.963 1.008
V
Step-up configuration (UP/DN = GND),
V
C S P A - V
C S N A = 0 to 20m V , 90% d uty cycl e0.954 1.018
FBA Regulation Voltage
(Overload) VFBA Step-down configuration (UP/DN = VCC),
V
C S P A - V
C S N A = 0 to 20m V , 90% d uty cycl e0.925 1.008
V
Step-up (UP/DN = GND) 5 19
FBA Line Regulation Step-down (UP/DN = VCC)1023
mV
Current-Sense Input Common-
Mode Range VCSA 0VCC +
0.3V V
Current-Limit Threshold (Positive) VILIMA 17 23 mV
MAX17017
Quad-Output Controller for
Low-Power Architecture
_______________________________________________________________________________________ 9
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= -40°C to +105°C.) (Note 1)
TA = -40°C to +105°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REGULATOR B (Internal 3A Step-Down Converter)
FBB Reg ul ati on V ol tag eI
LXB = 0A, 0% duty cycle (Note 2) 0.742 0.766 V
FBB Reg ul ati on V ol tag e ( Over l oad ) VFBB ILXB = 0 to 2.5A , 0% duty cycle (Note 2) 0.715 0.766 V
FBB Line Regulation 612mV
LXB Peak Current Limit IPKB 2.7 4.2 A
REGULATOR C (Internal 5A Step-Down Converter)
FBC Reg ul ati on V ol tag eI
LXC = 0A, 0% duty cycle (Note 2) 0.742 0.766 V
FBC Reg ul ati on V ol tag e ( Over l oad ) VFBC ILXC = 0 to 4A, 0% duty cycle (Note 2) 0.705 0.766 V
FBC Line Regulation 11 20 mV
LXC Peak Current Limit IPKC 5.0 6.5 A
REGULATOR D (Source/Sink Linear Regulator and VTTR Buffer)
IND Input Voltage Range VIND 1 2.8 V
IND Supply Current OND = VCC 70 μA
REFIND Input Range 0.5 1.5 V
OUTD Output Voltage Range VOUTD 0.5 1.5 V
V
F BD
w i th r esp ect to V
R E F IN D
,
O U TD = FBD , IOU T D = + 50μA ( sour ce l oad ) -12 0
FBD Output Accuracy VFBD VFBD with respect to VREFIND,
OUTD = FBD, IOUTD = -50μA (sink load) 0 +12
mV
FBD Load Regulation IOUTD = ±1A -20 mV/A
Source load +2 +4
OUTD Linear Regulator Current
Limit Sink load -2 -4 A
High-side on-resistance 300
Internal MOSFET On-Resistance Low-side on-resistance 475 mΩ
VTTR Output Accuracy REFIND to VTTR IVTTR = ±3mA -20 +20 mV
MAX17017
Quad-Output Controller for
Low-Power Architecture
10 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1 (step-down), VINLDO = 12V, VINA = VINBC = VDD = VCC = VBYP = VCSPA = VCSNA = 5V, VIND = 1.8V, VSHDN =
VONA = VONB = VONC = VOND = 5V, IREF = ILDO5 = IOUTD = no load, FREQ = GND, UP/DN = VCC, TA= -40°C to +105°C.) (Note 1)
TA = -40°C to +105°C
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS
FAULT PROTECTION
Upper threshold rising edge,
hysteresis = 50mV 8 16
SMPS POK and Fault Thresholds
Lower threshold falling edge,
hysteresis = 50mV -16 -8
%
Upper threshold rising edge,
hysteresis = 50mV 6 16
VTT LDO POKD and Fault
Threshold Lower threshold falling edge,
hysteresis = 50mV -16 -6
%
POK Output Low Voltage VPOK ISINK = 3mA 0.4 V
GENERAL LOGIC LEVELS
SHDN Input Logic Threshold Hysteresis = 20mV 0.5 1.6 V
ON_ Input Logic Threshold Hysteresis = 170mV 0.5 1.6 V
UP/DN Input Logic Threshold 0.5 1.6 V
High (VCC) VCC - 0.4V
Unconnected/REF 1.65 3.8
FREQ Input Voltage Levels
Low (GND) 0.5
V
SYNC Input Logic Threshold 1.5 3.5 V
Note 1: Limits are 100% production tested at TA= +25°C. Maximum and minimum limits are guaranteed by design and
characterization.
Note 2: Regulation voltage tested with slope compensation. The typical value is equivalent to 0% duty cycle. In real application, the
regulation voltage is higher due to the line regulation times the duty cycle.
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________
11
SMPS REGULATOR A EFFICIENCY
vs. LOAD CURRENT
MAX17017 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.01
55
60
65
70
75
80
85
90
95
100
50
0.001 10
VIN = 20V
VIN = 12V
VIN = 8V
SMPS REGULATOR A OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17017 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
4.54.03.53.02.52.01.51.00.5
4.80
4.85
4.90
4.95
5.00
5.05
4.75
0 5.0
VIN = 20V
VIN = 12V
VIN = 8V
SMPS REGULATOR B EFFICIENCY
vs. LOAD CURRENT
MAX17017 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.01
55
60
65
70
75
80
85
90
95
100
50
0.001 10
VIN = 3.3V
VIN = 5V
VIN = 2.5V
SMPS REGULATOR B OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17017 toc04
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
1.5 2.0 2.51.00.5
1.77
1.82
1.72
0 3.0
VIN = 3.3V
VIN = 5V
VIN = 2.5V
SMPS REGULATOR C EFFICIENCY
vs. LOAD CURRENT
MAX17017 toc05
LOAD CURRENT (A)
EFFICIENCY (%)
10.10.01
55
60
65
70
75
80
85
90
50
0.001 10
VIN = 3.3V
VIN = 5V
VIN = 2.5V
SMPS REGULATOR C OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17017 toc06
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
4.54.03.53.02.52.01.51.00.5
0.99
1.00
1.01
1.02
1.03
1.04
1.05
0.98
05.0
VIN = 3.3V
VIN = 5V
VIN = 2.5V
REGULATOR D VOLTAGE
vs. SOURCE/SINK LOAD CURRENT
MAX17017 toc07
LOAD CURRENT (A)
VTT VOLTAGE (V)
1.51.00 0.5-1.0 -0.5-1.5
0.885
0.890
0.895
0.900
0.905
0.910
0.915
0.920
0.925
0.930
0.880
-2.0 2.0
Typical Operating Characteristics
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
MAX17017
Quad-Output Controller for
Low-Power Architecture
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
REG B STARTUP WAVEFORM
(HEAVY LOAD)
MAX17017 toc10
400μs/div
ONB
OUTB
POKB
ILB
LXB
ONB: 5V/div
OUTB: 2V/div
POKB: 5V/div
ILB: 2A/div
LXB: 5V/div
RLOAD = 1.01Ω
REG B SHUTDOWN WAVEFORM
MAX17017 toc11
400μs/div
ONB
OUTB
POKB
ILB
LXB
ONB: 5V/div
OUTB: 2V/div
POKB: 5V/div
ILB: 2A/div
LXB: 5V/div
RLOAD = 0.8Ω
REG C STARTUP WAVEFORM
(HEAVY LOAD)
MAX17017 toc12
400μs/div
ONC
OUTC
POKC
ILC
LXC
ONC: 5V/div
OUTC: 1V/div
POKC: 5V/div
ILC: 5A/div
LXC: 5V/div
RLOAD = 0.25Ω
REG C SHUTDOWN
MAX17017 toc13
100μs/div
ONC
OUTC
POKC
ILC
LXC
ONC: 5V/div
OUTC: 1V/div
POKC: 5V/div
ILC: 5A/div
LXC: 5V/div
RLOAD = 0.25Ω
REG A STARTUP WAVEFORM
(HEAVY LOAD)
MAX17017 toc08
400μs/div
ONA
OUTA
POKA
ILA
LXA
ONA: 5V/div
OUTA: 5V/div
POKA: 5V/div
ILA: 5A/div
LXA: 10V/div
RLOAD = 1.6Ω
REG A SHUTDOWN WAVEFORM
MAX17017 toc09
400μs/div
ONA
OUTA
POKA
ILA
LXA
ONA: 5V/div
OUTA: 5V/div
POKA: 5V/div
ILA: 5A/div
LXA: 10V/div
RLOAD = 2.5Ω
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 13
REG A LOAD TRANSIENT (1A TO 3.2A)
MAX17017 toc14
20μs/div
OUTA
IOUTA
ILA
LXA
OUTA: 100mV/div
LXA: 10V/div
ILA: 2A/div
IOUTA: 2A/div
VINA = 12V, LOAD TRANSIENT
IS FROM 1A TO 3.2A
REG B LOAD TRANSIENT (0.4A TO 2A)
MAX17017 toc15
20μs/div
OUTB
IOUTB
ILB
LXB
OUTB: 50mV/div
LXB: 5V/div
ILB: 1A/div
IOUTB: 2A/div
VINBC = 5V, 0.4A TO 2.0A
LOAD TRANSIENT
REG C LOAD TRANSIENT (0.8A TO 3A)
MAX17017 toc16
20μs/div
OUTC
IOUTC
ILC
LXC
OUTC: 50mV/div
LXC: 5V/div
ILC: 2A/div
IOUTC: 2A/div
VINBC = 5V, 0.8A TO 3.0A
LOAD TRANSIENT
REG D LOAD TRANSIENT (SOURCE/SINK)
MAX17017 toc17
20μs/div
IOUTD
OUTD
OUTD: 20mV/div
IOUTD: 1A/div
IND = 1.8V, REFIND = 0.9V,
COUT = 2 x 10μF, LOAD TRANSIENT
IS FROM 1A SOURCING TO 1A SINKING
REG D LOAD TRANSIENT (SINK)
MAX17017 toc18
20μs/div
IOUTD
OUTD
OUTD: 10mV/div
IOUTD: 1A/div
IND = 1.8V, REFIND = 0.9V,
COUT = 2 x 10μF, LOAD TRANSIENT
IS FROM 0 TO 1A SINKING
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)
REG D LOAD TRANSIENT (SOURCE)
MAX17017 toc19
20μs/div
IOUTD
OUTD
OUTD: 10mV/div
IOUTD: 1A/div
IND = 1.8V, REFIND = 0.9V,
COUT = 2 x 10μF, LOAD TRANSIENT
IS FROM 0 TO 1A SOURCING
MAX17017
Quad-Output Controller for
Low-Power Architecture
14 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1POKC
Open-Drain Power-Good Output for the Internal 5A Step-Down Converter. POKC is low if FBC is more than
12% (typ) above or below the nominal 0.75V feedback regulation threshold. POKC is held low during
startup and in shutdown. POKC becomes high impedance when FBC is in regulation.
2 BSTC
Boost Flying Capacitor Connection for the Internal 5A Step-Down Converter. The MAX17017 includes an
internal boost switch/diode connected between VDD and BSTC. Connect to an external capacitor as shown
in Figure 1.
3–6 LXC Inductor Connection for the Internal 5A Step-Down Converter. Connect LXC to the switched side of the
inductor.
7, 8 OUTD
Source/Sink Linear Regulator Output. Bypass OUTD with 2x 10μF or greater ceramic capacitors to ground.
Dropout needs additional output capacitance (see the VTT LDO Output Capacitor Selection (COUTD)
section).
9INDS our ce/S i nk Li near Reg ul ator Inp ut. Byp ass IN D w i th a 10μF or g r eater cer am i c cap aci tor to g r ound .
10 FBD Feedback Input for the Internal Source/Sink Linear Regulator. FBD tracks and regulates to the REFIND
voltage.
11 VTTR Ouput of Reference Buffer. Bypass with 0.22μF for ±3mA of output current.
12 REFIND Dynamic Reference Input Voltage for the Source/Sink Linear Regulator and the Reference Buffer. The linear
regulator feedback threshold (FBD) tracks the REFIND voltage.
13 SHDN
Shutdown Control Input. The device enters its 5μA supply current shutdown mode if VSHDN is less than the
SHDN input falling edge trip level and does not restart until VSHDN is greater than the SHDN input rising
edge trip level. Connect SHDN to VINLDO for automatic startup of LDO5.
14 INLDO
Input of the Startup Circuitry and the LDO5 Internal 5V Linear Regulator. Bypass to GND with a 0.1μF or
greater ceramic capacitor close to the controller.
In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply.
Connect BYP and INLDO to the system’s 5V supply to effectively disable the linear regulator.
15 LDO5
5V Internal Linear Regulator Output. Bypass with a 4.7μF or greater ceramic capacitor. The 5V linear
regulator provides the bias power for the gate drivers (VDD) and analog control circuitry (VCC). The linear
regulator sources up to 50mA (max guaranteed). When BYP exceeds 4.65V (typ), the MAX17017 bypasses
the linear regulator through a 1.5_ bypass switch. When the linear regulator is bypassed, LDO5 supports
loads up to 100mA.
In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply.
Bypass SHDN to ground and leave LDO5 unconnected. Connect BYP and INLDO to effectively disable the
linear regulator.
16 BYP
Linear Regulator Bypass Input. When BYP exceeds 4.65V, the controller shorts LDO5 to BYP through a 1.5_
bypass switch and disables the linear regulator. When BYP is low, the linear regulator remains active.
The BYP input also serves as the VTTR buffer supply, allowing VTTR to remain active even when the
source/sink linear regulator (OUTD) has been disabled under system standby/suspend conditions.
In the single-cell step-up applications, the 5V linear regulator is no longer necessary for the 5V bias supply.
Bypass LDO5 to ground with a 1μF capacitor and leave this output unconnected. Connect BYP and INLDO
to the system’s 5V supply to effectively disable the linear regulator.
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 15
Pin Description (continued)
PIN NAME FUNCTION
17 VCC
5V Analog Bias Supply. VCC powers all the analog control blocks (error amplifiers, current-sense amplifiers,
fault comparators, etc.) and control logic. Connect VCC to the 5V system supply with a series 10_ resistor,
and bypass to analog ground using a 1μF or greater ceramic capacitor.
18 INA Input to the Circuit in Reg A in Boost Mode. Connect INA to the input in step-up mode (UP/DN = GND) and
connect INA to LDO5 in step-down mode (UP/DN = VCC).
19 UP/DN
Converter Configuration Selection Input for Regulator A. When UP/DN is pulled high (UP/DN = VCC),
regulator A operates as a step-down converter (Figure 1). When UP/DN is pulled low (UP/DN = GND),
regulator A operates as a step-up converter.
20 FREQ
Trilevel Oscillator Frequency Selection Input.
FREQ = VCC: RegA = 250kHz, RegB = 500kHz, RegC = 250kHz
FREQ = REF: RegA = 375kHz, RegB = 750kHz, RegC = 375kHz
FREQ = GND: RegA = 500kHz, RegB = 1MHz, RegC = 500kHz
21 REF
1.25V Reference-Voltage Output. Bypass REF to analog ground with a 0.1μF ceramic capacitor. The
reference sources up to 50μA for external loads. Loading REF degrades output voltage accuracy according
to the REF load-regulation error. The reference shuts down when the system pulls SHDN low in buck mode
(UP/DN = GND) or when the system pulls ONA low in boost mode (UP/DN = VCC).
22 AGND Analog Ground
23 CSNA N eg ati ve C ur r ent- S ense Inp ut for the M ai n S w i tchi ng Reg ul ator . C onnect to the neg ati ve ter m i nal of the cur r ent-
sense r esi stor . D ue to the C S N A b i as cur r ent r eq ui r em ents, l i m i t the ser i es i m p ed ance to l ess than 10Ω.
24 CSPA P osi ti ve C ur r ent- S ense Inp ut for the M ai n S w i tchi ng Reg ul ator . C onnect to the p osi ti ve ter m i nal of the cur r ent-
sense r esi stor . D ue to the C S P A b i as cur r ent r eq ui r em ents, l i m i t the ser i es i m p ed ance to l ess than 10Ω.
25 FBA Feedback Input for the Main Switching Regulator. FBA regulates to 1.0V.
26 POKA
Open-Drain Power-Good Output for the Main Switching Regulator. POKA is low if FBA is more than 12% (typ)
above or below the nominal 1.0V feedback regulation point. POKA is held low during soft-start and in
shutdown. POKA becomes high impedance when FBA is in regulation.
27 DHA High-Side Gate-Driver Output for the Main Switching Regulator. DHA swings from LXA to BSTA.
28 LXA Inductor Connection of Converter A. Connect LXA to the switched side of the inductor.
29 BSTA Boost Fl yi ng C ap aci tor C onnecti on of C onver ter A. The M AX 17017 i ncl ud es an i nter nal b oost sw i tch/d i od e
connected b etw een V
DD and BS TA. C onnect to an exter nal cap aci tor as show n i n Fi g ur e 1.
30 DLA Low-Side Gate-Driver Output for the Main Switching Regulator. DLA swings from GND to VDD.
31, 32,
33 LXB Inductor Connection for the Internal 3A Step-Down Converter. Connect LXB to the switched side of the
inductor.
34 BSTB
Boost Flying Capacitor Connection for the Internal 3A Step-Down Converter. The MAX17017 includes an
internal boost switch/diode connected between VDD and BSTB. Connect to an external capacitor as shown
in Figure 1.
35 POKB
Open-Drain Power-Good Output for the Internal 3A Step-Down Converter. POKB is low if FBB is more than
12% (typ) above or below the nominal 0.75V feedback-regulation threshold. POKB is held low during soft-
start and in shutdown. POKB becomes high impedance when FBB is in regulation.
MAX17017
Quad-Output Controller for
Low-Power Architecture
16 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
36 FBB Feedback Input for the Internal 3A Step-Down Converter. FBB regulates to 0.75V.
37 ONB Switching Regulator B Enable Input. When ONB is pulled low, LXB is high impedance. When ONB is driven
high, the controller enables the 3A internal switching regulator.
38 SYNC External Synchronization Input. Used to override the internal switching frequency.
39 ONA Switching Regulator A Enable Input. When ONA is pulled low, DLA and DHA are pulled low. When ONA is
driven high, the controller enables the step-up/step-down converter.
40–43 INBC
Input for Regulators B and C. Power INBC from a 2.5V to 5.5V supply. Internally connected to the drain of
the high-side MOSFETs for both regulator B and regulator C. Bypass to PGND with 2x 10μF or greater
ceramic capacitors to support the RMS current.
44 VDD 5V Bias Supply Input for the Internal Switching Regulator Drivers. Bypass with a 1μF or greater ceramic
capacitor. Provides power for the BSTB and BSTC driver supplies.
45 POKD
Open-Drain Power-Good Output for the Internal Source/Sink Linear Regulator. POKD is low if FBD is more
than 10% (typ) above or below the REFIND regulation threshold. POKD is held low during soft-start and in
shutdown. POKD becomes high impedance when FBD is in regulation.
46 OND S our ce/S i nk Li near Reg ul ator ( Reg ul ator D ) and Refer ence Buffer E nab l e Inp ut. W hen O N D i s p ul l ed l ow , O U TD
i s hi g h i m p ed ance. W hen O N D i s d r i ven hi g h, the contr ol l er enab l es the sour ce/si nk l i near r eg ul ator .
47 ONC Switching Regulator C Enable Input. When ONC is pulled low, LXC is high impedance. When ONC is driven
high, the controller enables the 5A internal switching regulator.
48 FBC Feedback Input for the Internal 5A Step-Down Converter. FBC regulates to 0.75V.
EP PGND
Power Ground. The source of the low-side MOSFETs (REG B and REG C), the drivers for all switching
regulators, and the sink MOSFET of the VTT LDO are all internally connected to the exposed pad.
Connect the exposed backside pad to system power ground planes through multiple vias.
Detailed Description
The MAX17017 standard application circuit (Figure 1)
provides a 5V/5AP-P main stage, a 1.8V/3AP-P VDDQ
and 0.9A/2A VTT outputs for DDR, and a 1.05V/5AP-P
chipset supply.
The MAX17017 supports four power outputs—one high-
voltage step-down controller, two internal MOSFET
step-down switching regulators, and one high-current
source/sink linear regulator. The step-down switching
regulators use a current-mode fixed-frequency architec-
ture compensated by the output capacitance. An inter-
nal 50mA 5V linear regulator provides the bias supply
and driver supplies, allowing the controller to power up
from input supplies greater than 5.5V.
Fixed 5V Linear Regulator (LDO5)
An internal linear regulator produces a preset 5V low-
current output from INLDO. LDO5 powers the gate dri-
vers for the external MOSFETs, and provides the bias
supply required for the SMPS analog controller, refer-
ence, and logic blocks. LDO5 supplies at least 50mA
for external and internal loads, including the MOSFET
gate drive, which typically varies from 5mA to 15mA
per switching regulator, depending on the switching
frequency. Bypass LDO5 with a 4.7μF or greater
ceramic capacitor to guarantee stability under the full-
load conditions.
The MAX17017 switch-mode step-down switching reg-
ulators require a 5V bias supply in addition to the main-
power input supply. This 5V bias supply is generated
by the controller’s internal 5V linear regulator (LDO5).
This boot-strappable LDO allows the controller to
power up independently. The gate-driver VDD input
supply is typically connected to the fixed 5V linear reg-
ulator output (LDO5). Therefore, the 5V LDO supply
must provide LDO5 (PWM controller) and the gate-
drive power during power-up.
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 17
C6
0.1μF,
6V
0402
C18
10μF, 6V
0805
R7
3.01kΩ
1%, 0402
R8
10.0kΩ
1%, 0402
1.05V,
4A
C16
330μF
18mΩ, 2.5V,
B2 CASE
C23
2200pF, 6V
0402
AGND AGND
PWR
C19
10μF, 6V
0805
PWR
C20
10μF, 6V
0805
PWR
C17
1μF, 6V
0402
PWR
L3
1.0μH, H6.8A, 14.2mΩ
5.8mm x 8.2mm x 3.0mm
(NEC/TOKIN: MPLC0525L1R0)
NL1
NH1
0.9A,
±1A
C5
0.1μF, 6V
0402
C7
1μF, 16V
0603
C4
0.1μF, 6V
0402
C1
4.7μF, 6V
0603
C2
1.0μF, 6V
0402
C3
0.1μF, 6V
0402
C23
0.1μF,
6V
0402
C8
4.7μF, 16V
1206
C10
22μF, 16V
C-CASE
16TQC22M
C14
150μF, 35mΩ, 6V
B2 CASE
R5
14kΩ
1%, 0402
R6
10.0kΩ
1%, 0402
1.8V,
2.5A
C14
330μF
18mΩ, 2.5V, B2 CASE
C22
1000pF, 6V
0402
AGND AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND AGNDPWR
FBD
AGND
2x OUTD
IND
FBC
4x LXC
BSTC
FBB
3x LXB
BSTB
4x INBC
BYP
FBA
CSNA
CSPA
DLA
LXA
DHA
BSTA
INLDO
LDO5
VDD
UP/DN
VCC
INA
ONA
ONB
ONC
OND
POKA
POKB
POKC
POKD
FREQ
SYNC
REF
VTTR
REFIND
SHDN
AGND
ON OFF
L2
1.0μH, 6.8A, 14.2mΩ
5.8mm x 6.2mm x 3.0mm
(NEC/TOKIN: MPLC0525L1RO)
L1
3.3μH, 6A, 30mΩ
6.7mm x 7.7mm x 3.0mm
(NEC/TOKIN:
MPLC0730L3R3)
R15
4mΩ
1%
R1
10Ω
5%, 0402
R9
100kΩ
5%,
0402
R10
100kΩ
5%,
0402
R11
100kΩ
5%,
0402
R12
100kΩ
5%,
0402
R2
0Ω
1%, 0402
R13
15kΩ
1%, 0402
R14
15.0kΩ
1%, 0402
1.8V SMPS
OUTPUT
5V SMPS
OUTPUT
R3
40kΩ
1%, 0402
R4
10kΩ
1%, 0402
C21
680pF, 6V
0402
C21
OPEN
0402
C16
OPEN
0402
C13
10μF, 6V
0805
C12
1μF, 16V
0402
5V,
4A
6V TO 16V
PWR
PWR
PWR
PWR
PWRPWR
PWR
C9
4.7μF, 16V
1206
PWR
PWR
PWR
PWR
ON OFF
ON OFF
ON OFF
13
15
44
19
17
18
37
39
47
46
26
35
1
45
20
38
21
11
12 10
7, 8
9
48
3-6
2
36
31, 32, 33
34
40-43
16
25
27
29
30
28
23
24
14
22
MAX17017
PGND
Figure 1. Standard Application Circuit
MAX17017
Quad-Output Controller for
Low-Power Architecture
18 ______________________________________________________________________________________
MAX17017
SHDN
REFOK
INLDO
LDO5
LDO5
TSDN
SW
DRV
UVLO
CSB
EN
BIAS
EN
BYP
BYP_OK
VCC_OK
VDD
UP/DN
UP/DN = VCC [BUCK],
LOW BUCK MODE
REF_OK
ONLDO
VCC
REF
PGOOD AND
FAULT
PROTECTION
EN
EN
VCC
OSC
REG A
ANALOG
EN
VCC
REG D
ANALOG
VCC VCC
VCC
TSDN
VCC
REF SYNC
*ONA (SHDN)
IND
PGND REG D PWR
OUTD
OND
FBD
REFIND
REFIND
ON_VTTR
VTTR
BYP
ONA
*BUCK REF ENABLED BY SHDN;
BOOST REF ENABLED BY ONA.
+SSDA ONLY USED IN STEP-UP MODE. SSDA = HIGH IN STEP-DOWN MODE.
ONB
ONC
OND
POKX
FAULTX
ONX
VCCOK
UVLO
INBC_OK
INA
VCC
BSTA
DHA
DLA
VDD
CSPA
CSNA ONA
FBA
REG B
ANALOG
FBB
SSDA+
LXA
BSTB
VDD
EN
EN
LXB
INBC
CSC
REG C
ANALOG
FBC
BSTC
VDD
EN
LXC
INBC
INBC
ONB
INBC_OK
ONC
INBC_OK
FB
-
+
Figure 2. MAX17017 Block Diagram
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 19
LDO5 Bootstrap Switchover
When the bypass input (BYP) exceeds the LDO5 boot-
strap switchover threshold for more than 500μs, an
internal 1.5Ω(typ) p-channel MOSFET shorts BYP to
LDO5, while simultaneously disabling the LDO5 linear
regulator. This bootstraps the controller, allowing power
for the internal circuitry and external LDO5 loading to
be generated by the output of a 5V switching regulator.
Bootstrapping reduces power dissipation due to driver
and quiescent losses by providing power from a
switch-mode source, rather than from a much-less-effi-
cient linear regulator. The current capability increases
from 50mA to 100mA when the LDO5 output is
switched over to BYP. When BYP drops below the boot-
strap threshold, the controller immediately disables the
bootstrap switch and reenables the 5V LDO.
Reference (REF)
The 1.25V reference is accurate to ±1% over temperature
and load, making REF useful as a precision system refer-
ence. Bypass REF to GND with a 0.1μF or greater ceram-
ic capacitor. The reference sources up to 50μA and sinks
5μA to support external loads. If highly accurate specifi-
cations are required for the main SMPS output voltages,
the reference should not be loaded. Loading the refer-
ence slightly reduces the output voltage accuracy
because of the reference load-regulation error.
SMPS Detailed Description
Fixed-Frequency, Current-Mode
PWM Controller
The heart of each current-mode PWM controller is a
multi-input, open-loop comparator that sums multiple
signals: the output-voltage error signal with respect to
the reference voltage, the current-sense signal, and the
slope compensation ramp (Figure 3). The MAX17017
uses a direct-summing configuration, approaching
ideal cycle-to-cycle control over the output voltage
without a traditional error amplifier and the phase shift
associated with it.
Frequency Selection (FREQ)
The FREQ input selects the PWM mode switching fre-
quency. Table 1 shows the switching frequency based
on the FREQ connection. High-frequency (FREQ =
GND) operation optimizes the application for the small-
est component size, trading off efficiency due to higher
switching losses. This might be acceptable in ultra-
portable devices where the load currents are lower.
Low-frequency (FREQ = 5V) operation offers the best
overall efficiency at the expense of component size and
board space.
FB_
REF
CSH_
CSL_
SLOPE COMPENSATION
VL
I1
R1 R2
TO PWM
LOGIC
OUTPUT DRIVER
UNCOMPENSATED
HIGH-SPEED
LEVEL TRANSLATOR
AND BUFFER
I2 I3 VBIAS
Figure 3. PWM Comparator Functional Diagram
MAX17017
Quad-Output Controller for
Low-Power Architecture
20 ______________________________________________________________________________________
Light-Load Operation Control
The MAX17017 uses a light-load pulse-skipping operat-
ing mode for all switching regulators. The switching
regulators turn off the low-side MOSFETs when the cur-
rent sense detects zero inductor current. This keeps the
inductor from discharging the output capacitors and
forces the switching regulator to skip pulses under
light-load conditions to avoid overcharging the output.
Idle-Mode Current-Sense Threshold
When pulse-skipping mode is enabled, the on-time of
the step-down controller terminates when the output
voltage exceeds the feedback threshold and when the
current-sense voltage exceeds the idle-mode current-
sense threshold. Under light-load conditions, the on-
time duration depends solely on the idle-mode
current-sense threshold. This forces the controller to
source a minimum amount of power with each cycle. To
avoid overcharging the output, another on-time cannot
begin until the output voltage drops below the feed-
back threshold. Since the zero-crossing comparator
prevents the switching regulator from sinking current,
the MAX17017 switching regulators must skip pulses.
Therefore, the controller regulates the valley of the out-
put ripple under light-load conditions.
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to PFM
takes place at light loads. This switchover is affected by
a comparator that truncates the low-side switch on-time
at the inductor current’s zero crossing. The zero-crossing
comparator senses the inductor current during the off-
time. For regulator A, once VCSPA - VCSNA drops below
the 1mV zero-crossing current-sense threshold, the com-
parator turns off the low-side MOSFET (DLA pulled low).
For regulators B and C, once the current through the low-
side MOSFET drops below 100mA, the zero-crossing
comparator turns off the low-side MOSFET.
The minimum idle-mode current requirement causes
the threshold between pulse-skipping PFM operation
and constant PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation (also known as the critical
conduction point). The load-current level at which
PFM/PWM crossover occurs (ILOAD(SKIP)) is equivalent
to half the idle-mode current threshold (see the
Electrical Characteristics
table for the idle-mode thresh-
olds of each regulator). The switching waveforms can
appear noisy and asynchronous when light loading
causes pulse-skipping operation, but this is a normal
operating condition that results in high light-load effi-
ciency. Trade-offs in PFM noise vs. light-load efficiency
are made by varying the inductor value. Generally, low
inductor values produce a broader efficiency vs. load
curve, while higher values result in higher full-load effi-
ciency (assuming that the coil resistance remains fixed)
and less output voltage ripple. Penalties for using high-
er inductor values include larger physical size and
degraded load-transient response (especially at low
input-voltage levels).
Table 1. FREQ Table
REG A AND REG C REG B
SWITCHING
FREQUENCY SOFT-START TIME
STARTUP
BLANKING
TIME
SWITCHING
FREQUENCY
SOFT-START
TIME
STARTUP
BLANKING
TIME
PIN
SELECT
fSWA AND fSWC REG A: 1200/fSWA
REG C: 900/fSWC 1500/fSWA fSWB 1800/fSWB 3000/fSWB
LDO5 250kHz REG A: 4.8ms
REG C: 3.6ms 6ms 500kHz 3.6ms 6ms
REF 375kHz REG A: 3.2ms
REG C: 2.4ms 4ms 750kHz 2.4ms 4ms
GND 500kHz REG A: 2.4ms
REG C: 1.8ms 3ms 1MHz 1.8ms 3ms
SYNC 0.5 x fSYNC ——f
SYNC ——
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 21
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCC rises above
approximately 1.9V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are pulled low
until the SMPS controllers are activated. The VCC input
undervoltage lockout (UVLO) circuitry prevents the
switching regulators from operating if the 5V bias supply
(VCC and VDD) is below its 4.2V UVLO threshold.
Regulator A Startup
Once the 5V bias supply rises above this input UVLO
threshold and ONA is pulled high, the main step-down
controller (regulator A) is enabled and begins switch-
ing. The internal voltage soft-start gradually increments
the feedback voltage by 10mV every 12 switching
cycles. Therefore, OUTA reaches its nominal regulation
voltage 1200/fSWA after regulator A is enabled (see the
REG A Startup Waveform (Heavy Load) graph in the
Typical Operating Characteristics
).
Regulator B and C Startup
The internal step-down controllers start switching and the
output voltages ramp up using soft-start. If the bias sup-
ply voltage drops below the UVLO threshold, the controller
stops switching and disables the drivers (LX_ becomes
high impedance) until the bias supply voltage recovers.
Once the 5V bias supply and INBC rise above their
respective input UVLO thresholds (SHDN must be
pulled high to enable the reference), and ONB or ONC
is pulled high, the respective internal step-down con-
troller (regulator B or C) becomes enabled and begins
switching. The internal voltage soft-start gradually
increments the feedback voltage by 10mV every 24
switching cycles for regulator B or every 12 switching
cycles for regulator C. Therefore, OUTB reaches its
nominal regulation voltage 1800/fSWB after regulator B
is enabled, and OUTC reaches its nominal regulation
voltage 900/fSWC after regulator C is enabled (see the
REG B Startup Waveform (Heavy Load) and REG C
Startup Waveform (Heavy Load) graphs in the
Typical
Operating Characteristics
).
SMPS Power-Good Outputs (POK)
POKA, POKB, and POKC are the open-drain outputs of
window comparators that continuously monitor each
output for undervoltage and overvoltage conditions.
POK_ is actively held low in shutdown (SHDN = GND),
standby (ONA = ONB = ONC = GND), and soft-start.
Once the soft-start sequence terminates, POK_
becomes high impedance as long as the output remains
within ±8% (min) of the nominal regulation voltage set
by FB_. POK_ goes low once its corresponding output
drops 12% (typ) below its nominal regulation point, an
output overvoltage fault occurs, or the output is shut
down. For a logic-level POK_ output voltage, connect an
external pullup resistor between POK_ and LDO5. A
100kΩpullup resistor works well in most applications.
SMPS Fault Protection
Output Overvoltage Protection (OVP)
If the output voltage rises above 112% (typ) of its nomi-
nal regulation voltage, the controller sets the fault latch,
pulls POK_ low, shuts down the respective regulator,
and immediately pulls the output to ground through its
low-side MOSFET. Turning on the low-side MOSFET
with 100% duty cycle rapidly discharges the output
capacitors and clamps the output to ground. However,
this commonly undamped response causes negative
output voltages due to the energy stored in the output
LC at the instant the OVP occurs. If the load cannot tol-
erate a negative voltage, place a power Schottky diode
across the output to act as a reverse-polarity clamp. If
the condition that caused the overvoltage persists
(such as a shorted high-side MOSFET), the input
source also fails (short-circuit fault). Cycle VCC below
1V or toggle the respective enable input to clear the
fault latch and restart the regulator.
Output Undervoltage Protection (UVP)
Each MAX17017 includes an output undervoltage
(UVP)-protection circuit that begins to monitor the out-
put once the startup blanking period has ended. If any
output voltage drops below 88% (typ) of its nominal
regulation voltage, the UVP protection immediately sets
the fault latch, pulls the respective POK output low,
forces the high-side and low-side MOSFETs into high-
impedance states (DH = DL = low), and shuts down the
respective regulator. Cycle VCC below 1V or toggle the
respective enable input to clear the fault latch and
restart the regulator.
Thermal-Fault Protection
The MAX17017 features a thermal-fault-protection cir-
cuit. When the junction temperature rises above
+160°C, a thermal sensor activates the fault latch, pulls
all POK outputs low, and shuts down all regulators.
Toggle SHDN to clear the fault latch and restart the
controllers after the junction temperature cools by 15°C.
MAX17017
Quad-Output Controller for
Low-Power Architecture
22 ______________________________________________________________________________________
VTT LDO Detailed Description
VTT LDO Power-Good Output (POKD)
POKD is the open-drain output of a window comparator
that continuously monitors the VTT LDO output for
undervoltage and overvoltage conditions. POKD is
actively held low when the VTT LDO is disabled (OND
= GND) and soft-start. Once the startup blanking time
expires, POKD becomes high impedance as long as
the output remains within ±6% (min) of the nominal reg-
ulation voltage set by REFIND. POKD goes low once its
corresponding output drops or rises 12% (typ) beyond
its nominal regulation point or the output is shut down.
For a logic-level POKD output voltage, connect an
external pullup resistor between POKD and LDO5. A
100kΩpullup resistor works well in most applications.
VTT LDO Fault Protection
LDO Output Overvoltage Protection (OVP)
If the output voltage rises above 112% (typ) of its nomi-
nal regulation voltage, the controller sets the fault latch,
pulls POKD low, shuts down the source/sink linear reg-
ulator, and immediately pulls the output to ground
through its low-side MOSFET. Turning on the low-side
MOSFET with 100% duty cycle rapidly discharges the
output capacitors and clamps the output to ground.
Cycle VCC below 1V or toggle OND to clear the fault
latch and restart the linear regulator.
LDO Output Undervoltage Protection (UVP)
Each MAX17017 includes an output undervoltage pro-
tection (UVP) circuit that begins to monitor the output
once the startup blanking period has ended. If the
source/sink LDO output voltage drops below 88% (typ)
of its nominal REFIND regulation voltage for 5ms, the
UVP protection sets the fault latch, pulls the POKD out-
put low, forces the output into a high-impedance state,
and shuts down the linear regulator. Cycle VCC below
1V or toggle OND to clear the fault latch and restart the
regulator.
SMPS Design Procedure
(Step Down Regulators)
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
•Input voltage range. The maximum value (VIN(MAX))
must accommodate the worst-case, high AC-
adapter voltage. The minimum value (VIN(MIN)) must
account for the lowest battery voltage after drops
due to connectors, fuses, and battery selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
•Maximum load current. There are two values to
consider. The peak load current (ILOAD(MAX)) deter-
mines the instantaneous component stresses and fil-
tering requirements and thus drives output capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (ILOAD) determines the thermal stresses and
thus drives the selection of input capacitors,
MOSFETs, and other critical heat-contributing com-
ponents.
•Switching frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and VIN2.
•Inductor operating point. This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency, higher output
ripple, and lower maximum load current, and due to
increased ripple currents. The minimum practical
inductor value is one that causes the circuit to oper-
ate at the edge of critical conduction (where the
inductor current just touches zero with every cycle at
maximum load). Inductor values lower than this
grant no further size-reduction benefit. The optimum
operating point is usually found between 20% and
50% ripple current. When pulse skipping (light
loads), the inductor value also determines the load-
current value at which PFM/PWM switchover occurs.
Step-Down Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Most
inductor manufacturers provide inductors in standard
values, such as 1.0μH, 1.5μH, 2.2μH, 3.3μH, etc. Also
look for nonstandard values, which can provide a better
compromise in LIR across the input voltage range. If
using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values. For
LVVV
Vf I LIR
OUT IN OUT
IN SW LOAD MAX
=
()
−
()
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 23
the selected inductance value, the actual peak-to-peak
inductor ripple current (ΔIINDUCTOR) is defined by:
Ferrite cores are often the best choice, although soft sat-
urating molded core inductors are inexpensive and can
work well at 500kHz. The core must be large enough not
to saturate at the peak inductor current (IPEAK):
SMPS Output Capacitor Selection
The output filter capacitor selection requires careful
evaluation of several different design requirements—
stability, transient response, and output ripple volt-
age—that place limits on the output capacitance and
ESR. Based on these requirements, the typical applica-
tion requires a low-ESR polymer capacitor (lower cost
but higher output-ripple voltage) or bulk ceramic
capacitors (higher cost but low output-ripple voltage).
SMPS Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the loop
gain. This reduces the output capacitance requirement
(stability and transient) and output power dissipation
requirements as well. The load-line is generated by sens-
ing the inductor current through the high-side MOSFET
on-resistance, and is internally preset to -5mV/A (typ) for
regulator B and -7mV/A (typ) for regulator C. The load-
line ensures that the output voltage remains within the
regulation window over the full-load conditions.
The load line of the internal SMPS regulators also pro-
vides the AC ripple voltage required for stability. To
maintain stability, the output capacitive ripple must be
kept smaller than the internal AC ripple voltage, and
crossover must occur before the Nyquist pole—
(2fSW)/(1+D) occurs. Based on these loop requirements,
a minimum output capacitance can be determined from
the following:
When using only ceramic capacitors on the output, the
required output capacitance is:
where RDROOP is 2RSENSE for regulator A, 5mV/A for
regulator B, or 7mV/A for regulator C as defined in the
Electrical Characteristics
table, and fSW is the switching
frequency selected by the FREQ setting (see Table 1).
When using only polymer capacitors on the output, the
additional ESR of the output (RESR) must be taken into
consideration.
For duty cycles less than 40% using polymer capacitors:
For duty cycles above 40% using polymer capacitors, the
ESR and COUT must meet the conditions listed below:
When the ESR condition described above is not satis-
fied, or when using a mix of ceramic and polymer
capacitors on the output, an additional feedback pole-
capacitor from FB to analog ground (CFB) is necessary
to cancel the output capacitor ESR zero:
where RFB is the parallel impedance of the FB resistive
divider.
SMPS Output Ripple Voltage
With polymer capacitors, the effective series resistance
(ESR) dominates and determines the output ripple volt-
age. The step-down regulator’s output ripple voltage
(VRIPPLE) equals the total inductor ripple current
(ΔIINDUCTOR) multiplied by the output capacitor’s ESR.
Therefore, the maximum ESR to meet the output ripple
voltage requirement is:
where fSW is the switching frequency. The actual capa-
citance value required relates to the physical case size
needed to achieve the ESR requirement, as well as to
the capacitor chemistry. Thus, polymer capacitor selec-
tion is usually limited by ESR and voltage rating rather
than by capacitance value. Alternatively, combining
ceramics (for the low ESR) and polymers (for the bulk
capacitance) helps balance the output capacitance vs.
output ripple voltage requirements.
RVf L
VV V V
ESR
IN SW
IN OUT OUT RIPPLE
≤
()
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
−
CCOUTR
RFB
FB ESR
>⎛
⎝
⎜⎞
⎠
⎟
RR V
V
CfR
V
V
V
V
ESR DROOP OUT
FB
OUT
SW DROOP
FB
OUT
OUT
IN
<
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⎜⎞
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21
CfR R xV V
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SW DROOP ESR FB OUT
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II I
PEAK LOAD MAX INDUCTOR
=+
⎛
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()
Δ
2
ΔIVVV
Vf L
INDUCTOR OUT IN OUT
IN SW
=
()
−
MAX17017
Quad-Output Controller for
Low-Power Architecture
24 ______________________________________________________________________________________
Internal SMPS Transient Response
The load-transient response depends on the overall
output impedance over frequency, and the overall
amplitude and slew rate of the load step. In applica-
tions with large, fast load transients (load step > 80% of
full load and slew rate > 10A/μs), the output capacitor’s
high-frequency response—ESL and ESR—needs to be
considered. To prevent the output voltage from spiking
too low under a load-transient event, the ESR is limited
by the following equation (ignoring the sag due to finite
capacitance):
where VSTEP is the allowed voltage drop, ΔILOAD(MAX) is
the maximum load step, and RPCB is the parasitic board
resistance between the load and output capacitor.
The capacitance value dominates the midfrequency
output impedance and dominates the load-transient
response as long as the load transient’s slew rate is
less than two switching cycles. Under these conditions,
the sag and soar voltages depend on the output
capacitance, inductance value, and delays in the tran-
sient response. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from or added to the output filter capacitors by a sud-
den load step, especially with low differential voltages
across the inductor. The sag voltage (VSAG) that occurs
after applying the load current can be estimated by the
following:
where DMAX is the maximum duty factor (see the
Electrical Characteristics
table), T is the switching peri-
od (1/fOSC), and ΔT equals VOUT/VIN x T when in PWM
mode, or L x IIDLE/(VIN - VOUT) when in pulse-skipping
mode. The amount of overshoot voltage (VSOAR) that
occurs after load removal (due to stored inductor ener-
gy) can be calculated as:
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent VSOAR from causing problems during
load transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot at
the rising load edge is no longer a problem.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
The IRMS requirements of an individual regulator can be
determined by the following equation:
The worst-case RMS current requirement occurs when
operating with VIN = 2VOUT. At this point, the above
equation simplifies to IRMS = 0.5 x ILOAD. However, the
MAX17017 uses an interleaved fixed-frequency archi-
tecture, which helps reduce the overall input RMS cur-
rent on the INBC input supply.
For the MAX17017 system (INA) supply, nontantalum
chemistries (ceramic, aluminum, or OS-CON) are pre-
ferred due to their resistance to inrush surge currents
typical of systems with a mechanical switch or connector
in series with the input. For the MAX17017 INBC input
supply, ceramic capacitors are preferred on input due to
their low parasitic inductance, which helps reduce the
high-frequency ringing on the INBC supply when the
internal MOSFETs are turned off. Choose an input
capacitor that exhibits less than +10°C temperature rise
at the RMS input current for optimal circuit longevity.
BST Capacitors
The boost capacitors (CBST) must be selected large
enough to handle the gate charging requirements of
the high-side MOSFETs. For these low-power applica-
tions, 0.1μF ceramic capacitors work well.
Regulator A Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN)
should be roughly equal to the losses at VIN(MAX), with
lower losses in between. If the losses at VIN(MIN) are
significantly higher, consider increasing the size of NH.
Conversely, if the losses at VIN(MAX) are significantly
higher, consider reducing the size of NH. If VIN does
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (NH) that
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (NL) that has the lowest
possible on-resistance (RDS(ON)), comes in a moder-
ate-sized package (i.e., 8-pin SO, DPAK, or D2PAK),
II
VVVV
RMS LOAD
IN OUT IN OUT
=⎛
⎝
⎜⎞
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−
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CV
SOAR
LOAD MAX
OUT OUT
≈
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2
2
VLI
CVD V
ITT
C
SAG
LOAD MAX
OUT IN MAX OUT
LOAD MAX
OUT
=
()
×
()
+
()
−
−
ΔΔΔ
() ()
2
2
RV
IR
ESR STEP
LOAD MAX PCB
≤⎛
⎝
⎜⎞
⎠
⎟
−
Δ()
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 25
and is reasonably priced. Ensure that the MAX17017
DLA gate driver can supply sufficient current to support
the gate charge and the current injected into the para-
sitic drain-to-gate capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction prob-
lems might occur. Switching losses are not an issue for
the low-side MOSFET since it is a zero-voltage
switched device when used in the step-down topology.
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worst-
case power dissipation due to resistance occurs at
minimum input voltage:
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
RDS(ON) required to stay within package power-dissi-
pation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
the conduction (RDS(ON)) losses. High-side switching
losses do not become an issue until the input is greater
than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (NH) due to switching losses is difficult, since
it must allow for difficult-to-quantify factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PC board (PCB) layout charac-
teristics. The following switching loss calculation pro-
vides only a very rough estimate and is no substitute for
breadboard evaluation, preferably including verification
using a thermocouple mounted on NH:
where COSS is the output capacitance of NH, QG(SW) is
the charge needed to turn on the NH MOSFET, and
IGATE is the peak gate-drive source/sink current (1A typ).
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied, due to the squared term in the switching-
loss equation (C x VIN2x fSW). If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when subjected to
VIN(MAX), consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL) the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overload conditions that are
greater than ILOAD(MAX), but are not high enough to
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the cir-
cuit to tolerate:
where ILIMIT is the peak current allowed by the current-
limit circuit, including threshold tolerance and sense-
resistance variation. The MOSFETs must have a relatively
large heatsink to handle the overload power dissipation.
Choose a Schottky diode (DL) with a forward voltage
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3 the load current. This diode is optional and
can be removed if efficiency is not critical.
Regulator A Step-Up
Converter Configuration
Regulator A can be configured as a step-up converter
(Figure 4). When UP/DN is pulled low, regulator A oper-
ates as a step-up converter (for 1 Li+ cell applications). It
typically generates a 5V output voltage from a 3V to 5V
battery input voltage. The step-up converter uses a cur-
rent-mode architecture; the difference between the feed-
back voltage and a 1V reference signal generates an error
signal that programs the peak inductor current to regulate
the output voltage. The step-up converter is internally com-
pensated, reducing external component requirements.
When regulator A is configured as a step-up converter,
SHDN should be connected to GND. ONA is the master
enable switch. ONA rising enables REF and the bias
block. Connect LDO5 and INLDO together with OUTA
and connect BYP to either OUTA or INA.
At light loads, efficiency is enhanced by an idle mode
in which switching occurs only as needed to service the
load. This idle-mode threshold is determined by com-
paring the current-sense signal to an internal reference.
In idle mode, the synchronous rectifier shuts off once
the current-sense voltage (CSPA - CSNA) drops below
1mV, preventing negative inductor current.
II I
LOAD LIMIT INDUCTOR
=⎛
⎝
⎜⎞
⎠
⎟
−Δ
2
PD N sistive V
VIR
LOUT
IN MAX LOAD DS ON
Re
() ()
()
=⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
()
−12
PD N Switching
IQ
I
CV
H
LOAD G SW
GATE
OSS IN M() (
()
=
+AAX IN MAX SW
Vf
)()
2
⎛
⎝
⎜⎞
⎠
⎟
PD N sistive V
VIR
HOUT
IN LOAD DS ON
Re ()
()
=⎛
⎝
⎜⎞
⎠
⎟
()
2
MAX17017
Quad-Output Controller for
Low-Power Architecture
26 ______________________________________________________________________________________
C6
0.1μF, 6V
0402
C20
10μF, 6V
0805
R7
6.04kΩ
1%, 0402
R8
15.0kΩ
1%, 0402
1.05V,
4A
C16
220μF
18mΩ,
2.5V, B2
CASE
C18
2200pF, 6V
0402
AGND AGND
PWR
C17
10μF, 6V
0805
PWR
C21
10μF, 6V
0805
PWR
C22
10μF, 6V
0805
PWR
C19
1μF, 6V
0402
PWR
L3
1.0μH, 6.8A, 14.2mΩ
5.8mm x 8.2mm x 3.0mm
(NEC/TOKIN: MPLC0525L1R0)
0.9A,
±1A
C5
0.1μF, 6V
0402
C7
1μF, 16V
0603
C2
1.0μF, 6V
0402
C1
4.7μF, 6V
0603
C3
10nF , 6V
0402
C4
0.1μF,
6V
0402
C8
4.7μF, 16V
1206
C9
150μF, 35mΩ
6V
B2 CASE
C11
220μF,
35mΩ 6V
B2 C4SE
R5
21.0kΩ
1%, 0402
R6
15.0kΩ
1%, 0402
1.8V,
2.5A
C14
220μF
18mΩ, 2.5V, B2 CASE
C15
1000pF, 6V
0402
AGND
AGND
AGND AGND
AGND
AGND
AGND
AGND
AGND AGNDPWR
FBD
AGND
2x OUTD
IND
FBC
4x LXC
BSTC
FBB
3x LXB
BSTB
4x INBC
BYP
FBA
DHA
BSTA
DLA
LXA
CSNA
CSPA
INA
SYNC
LDO5
INLDO
VDD
VCC
ONA
ONB
ONC
OND
POKA
POKB
POKC
POKD
FREQ
REF
VTTR
REFIND
AGND
ON OFF
L2
1.0μH, 6.8A, 14.2mΩ
6.7mm x 7.7mm x 3.0mm
(NEC/TOKIN: MPLC0730L3R3)
L1
3.3μH, 6.8A, 14.2mΩ
5.8mm x 6.2mm x 3.0mm
(NEC/TOKIN:
MPLC0525L1R0)
R1
10Ω
5%, 0402
R9
100kΩ
5%,
0402
R10
100kΩ
5%,
0402
R11
100kΩ
5%,
0402
R12
100kΩ
5%,
0402
R2
0Ω
1%, 0402
R13
15kΩ
1%, 0402
R14
15.0kΩ
1%, 0402
1.8V SMPS
OUTPUT
5V SMPS
OUTPUT
5V SMPS
OUTPUT
R3
40kΩ
1%, 0402
R15
0.01Ω
1%, 0612
R4
10kΩ
1%, 0402
C11
680pF, 6V
0402
C10
0.1μF,
6V, 0402
C13
10μF, 6V
0805
C12
1μF, 16V
0402
5V,
1A
3V TO 4.5V
PWR
PWR
PWR
PWRPWR
PWR
PWR
PWR
PWR
NH1
PWR
ON OFF
ON OFF
ON OFF
13
14
15
19
38
44
17
37
39
47
46
26
35
1
45
20
21
11
12 10
7, 8
9
48
3-6
2
36
31, 32, 33
34
40-43
16
25
27
29
30
28
23
24
18
22
SHDN
UP/DN
NL1
MAX17017
PGND
Figure 4. Standard Application Circuit 2, Regulator A Configured as Step-Up Converter
MAX17017
Step-Up Configuration Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage VIN(MIN) using con-
servation of energy:
Calculate the ripple current at that operating point and
the peak current required for the inductor:
The inductor’s saturation current rating and the
MAX17017’s LXA current limit should exceed IPEAK and
the inductor’s DC current rating should exceed
IVIN(DC,MAX). For good efficiency, choose an inductor
with less than 0.1Ωseries resistance.
Step-Up Configuration Output
Capacitor Selection
For boost converter, during continuous operation, the
output capacitor has a trapezoidal current profile. The
large RMS ripple current in the output capacitor must
be rated to handle the current. The RMS current is
greatest at ILOAD(MAX) and minimum input working volt-
age. Therefore, the output capacitor should be chosen
with a rating at least ICOUT(RMS).The RMS current into
the capacitor is then given by:
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the resistive ripple
due to the capacitor’s equivalent series resistance (ESR):
and:
where IPEAK is the peak inductor current. For polymer
capacitors, the output voltage ripple is typically domi-
nated by resistive ripple voltage. The voltage rating and
temperature characteristics of the output capacitor
must also be considered. The output ripple voltage due
to the frequency-dependent term can be compensated
by using capacitors of very low ESR to maintain low rip-
ple voltage. Note that all ceramic capacitors typically
have large temperature coefficient and bias voltage
coefficients. The actual capacitor value in circuit is typi-
cally significantly less than the stated value.
Step-Up Configuration Loop Compensation
The boost converter small-signal model contains a right
half-plane (RHP) zero. The presence of an RHP zero
tends to destabilize wide-bandwidth feedback loop
because during a transient, the output initially changes
in the wrong direction. Also when an RHP zero is pre-
sent, it is difficult to obtain an adequate phase margin.
RHP is determined by inductance L, duty cycle Dup,
and load R. The RHP is:
To maintain stability, crossover must occur before the
RHP. To make sure the phase margin is big enough to
stabilize the circuit, the converter crossover must be
kept 4 ~ 10 times slower than the RHP zero. A minimum
output capacitance is determined from the following:
where ASTEP-UP is equal to 1.25, which is the error amplifi-
er gain divided by the current-sense gain; RCS is the cur-
rent-sensing resistor.
Additionally, an additional feedback pole—capacitor
from FB to analog ground (CFB)—might be necessary to
cancel the unwanted ESR zero of the output capacitor.
CA
R
V
VDR
L
OUT STEP UP
CS
REF
OUT UP
>⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜
41
-
-()
⎞⎞
⎠
⎟
fDR
L
RHP UP
=()1
2
2
-
π
VIR
RIPPLE ESR PEAK ESR()
≈
VI
C
VV
Vf
RIPPLE C OUT
OUT
OUT IN
OUT SW
()
≈⎛
⎝
⎜⎞
⎠
⎟
-
VV V
RIPPLE RIPPLE C RIPPLE ESR
=+
() ( )
II
VV
V
COUT RMS LOAD OUT IN
IN
()
≅-
II I
PEAK LOAD MAX INDUCTOR
=+
⎛
⎝
⎜⎞
⎠
⎟
()
Δ
2
ΔIVV V
VfL
INDUCTOR IN OUT IN
OUT SW
=
()
-
IIV
V
VIN DC MAX LOAD MAX OUT
IN MIN
(, ) ()
()
=
LV
V
VV
IfLIR
IN
OUT
OUT VIN
LOAD MAX SW
=⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
2-
()
⎜⎜ ⎞
⎠
⎟
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 27
MAX17017
Quad-Output Controller for
Low-Power Architecture
28 ______________________________________________________________________________________
In general, if the ESR zero occurs before the Nyquist
pole, then canceling the ESR zero is recommended:
If:
then:
where RFB is the parallel impedance of the FB resistive
divider.
Step-Up Configuration Input
Capacitor Selection
The current in the boost converter input capacitor does
not contain large square-wave currents as found in the
output capacitor. Therefore, the input capacitor selec-
tion is less critical due to the output capacitor. However,
a low ESR is recommended.
The RMS input ripple current for a boost converter is:
VTT LDO Design Procedure
IND Input Capacitor Selection (CIND)
The value of the IND bypass capacitor is chosen to limit
the amount of ripple and noise at IND, and the amount of
voltage sag during a load transient. Typically, IND con-
nects to the output of a step-down switching regulator,
which already has a large bulk output capacitor.
Nevertheless, a ceramic capacitor equivalent to half the
VTT output capacitance should be added and placed as
close as possible to IND. The necessary capacitance
value must be increased with larger load current, or if the
trace from IND to the power source is long and results in
relatively high input impedance.
VTT LDO Output Voltage (FBD)
The VTT output stage is powered from the IND input.
The VTT output voltage is set by the REFIND input.
REFIND sets the VTT LDO feedback regulation voltage
(VFBD = VREFIND) and the VTTR output voltage. The
VTT LDO (FBD voltage) and VTTR track the REFIND
voltage over a 0.5V to 1.5V range. This reference input
feature makes the MAX17017 ideal for memory applica-
tions in which the termination supply must track the
supply voltage.
VTT LDO Output Capacitor
Selection (COUTD)
A minimum value of 20μF or greater ceramic is needed
to stabilize the VTT output (OUTD). This value of capac-
itance limits the switching regulator’s unity-gain band-
width frequency to approximately 1.2MHz (typ) to allow
adequate phase margin for stability. To keep the
capacitor acting as a capacitor within the switching
regulator’s bandwidth, it is important that ceramic
capacitors with low ESR and ESL be used.
Since the gain bandwidth is also determined by the
transconductance of the output MOSFETs, which
increases with load current, the output capacitor might
need to be greater than 20μF if the load current
exceeds 1.5A, but can be smaller than 20μF if the maxi-
mum load current is less than 1.5A. As a guideline,
choose the minimum capacitance and maximum ESR
for the output capacitor using the following:
and:
RESR value is measured at the unity-gain-bandwidth
frequency given by approximately:
Once these conditions for stability are met, additional
capacitors, including those of electrolytic and tantalum
types, can be connected in parallel to the ceramic
capacitor (if desired) to further suppress noise or volt-
age ripple at the output.
VTTR Output Capacitor Selection
The VTTR buffer is a scaled-down version of the VTT
regulator, with much smaller output transconductance.
Therefore, the VTTR compensation requirements also
scale. For typical applications requiring load currents
up to ±3mA, a 0.22μF or greater ceramic capacitor is
recommended (RESR < 0.3Ω).
fC
I
A
GBW OUT
LOAD
=×
36
15.
Rm
I
A
ESR MAX LOAD
_.
=×515
Ω
CμF
I
A
OUT MIN LOAD
_.
=×20 15
IVD
Lf
CIN RMS IN MIN MAX
SW
() ()
.
≈03
CC ESR
R
FB OUT
FB
>⎛
⎝
⎜⎞
⎠
⎟
ESR GV
DAV
CS OUT
REF
>⎛
⎝
⎜⎞
⎠
⎟
()1-
VTT LDO Power Dissipation
Power loss in the MAX17017 VTT LDO is significant and
can become a limiting design factor in the overall
MAX17017 design:
PDVTT = 2A x 0.9V = 1.8W
The 1.8W total power dissipation is within the 40-pin
TQFN multilayer board power-dissipation specification
of 2.9W. The typical DDR termination application does
not actually continuously source or sink high currents.
The actual VTT current typically remains around 100mA
to 200mA under steady-state conditions. VTTR is down
in the microampere range, though the Intel specifica-
tion requires 3mA for DDR1 and 1mA for DDR2. True
worst-case power dissipation occurs on an output
short-circuit condition with worst-case current limit.
MAX17017 does not employ any foldback current limit-
ing, and relies on the internal thermal shutdown for pro-
tection. Both the VTT and VTTR output voltages are
referenced to the same REFIND input.
Applications Information
Minimum Input Voltage
The minimum input operating voltage (dropout voltage) is
restricted by the maximum duty-cycle specification (see
the
Electrical Characteristics
table). For the best dropout
performance, use the slowest switching frequency setting
(FREQ = GND). However, keep in mind that the transient
performance gets worse as the step-down regulators
approach the dropout voltage, so bulk output capaci-
tance must be added (see the voltage sag and soar
equations in the
Design Procedure
section). The absolute
point of dropout occurs when the inductor current ramps
down during the off-time (ΔIDOWN) as much as it ramps
up during the on-time (ΔIUP). This results in a minimum
operating voltage defined by the following equation:
where VCHG and VDIS are the parasitic voltage drops in
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
Maximum Input Voltage
The MAX17017 controller includes a minimum on-time
specification, which determines the maximum input
operating voltage that maintains the selected switching
frequency (see the
Electrical Characteristics
table).
Operation above this maximum input voltage results in
pulse skipping to avoid overcharging the output. At the
beginning of each cycle, if the output voltage is still
above the feedback threshold voltage, the controller
does not trigger an on-time pulse, effectively skipping a
cycle. This allows the controller to maintain regulation
above the maximum input voltage, but forces the con-
troller to effectively operate with a lower switching fre-
quency. This results in an input threshold voltage at
which the controller begins to skip pulses (VIN(SKIP)):
where fOSC is the switching frequency selected by
FREQ.
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
the power components on the top side of the board,
with their ground terminals flush against one another.
Follow the MAX17017 Evaluation Kit layout and use the
following guidelines for good PCB layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mil-
liohm of excess trace resistance causes a measur-
able efficiency penalty.
• Minimize current-sensing errors by connecting
CSPA and CSNA directly across the current-sense
resistor (RSENSE_).
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
• Route high-speed switching nodes (BST_, LX_,
DHA, and DLA) away from sensitive analog areas
(REF, REFIND, FB_, CSPA, CSNA).
VV
ft
IN SKIP OUT OSC ON MIN
() ()
=⎛
⎝
⎜⎞
⎠
⎟
1
VVVh
DVV
IN MIN OUT CHG MAX OUT DIS()
=++
⎛
⎝
⎜⎞
⎠
⎟+
()
−
11
MAX17017
Quad-Output Controller for
Low-Power Architecture
______________________________________________________________________________________ 29
MAX17017
Quad-Output Controller for
Low-Power Architecture
30 ______________________________________________________________________________________
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 TQFN T4866-2 21-0141
MAX17017
Quad-Output Controller for
Low-Power Architecture
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
31
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/08 Initial release —
1 9/08 Updated Electrical Characteristics and added Regulator Step-Up Converter Configuration
section
4, 5, 8, 9, 23,
25–29
2 6/09
Status changed from silent to public; added leakage current specification and updated
Note 2 in Electrical Characteristics; updated Figures 1, 2, and 4; updated SMPS Loop
Compensation section
1–6, 8–23,
25, 26, 29,
30
