16-Channel
Short Haul T1/E1/J1
Line Interface Unit
IDT82P20416
Version -
December 17, 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775
Printed in U.S.A.
© 2009 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-
sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-
cuted between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents 3 December 17, 2009
TABLE OF CONTENTS ........................................................................................................................................................... 3
LIST OF TABLES .................................................................................................................................................................... 6
LIST OF FIGURES ................................................................................................................................................................... 7
FEATURES............................................................................................................................................................................... 8
APPLICATIONS........................................................................................................................................................................ 9
DESCRIPTION.......................................................................................................................................................................... 9
BLOCK DIAGRAM ................................................................................................................................................................. 10
1 PIN ASSIGNMENT .......................................................................................................................................................... 11
2 PIN DESCRIPTION ......................................................................................................................................................... 12
3 FUNCTIONAL DESCRIPTION ........................................................................................................................................ 20
3.1 T1 / E1 / J1 MODE SELECTION .............................................................................................................................. 20
3.2 RECEIVE PATH ....................................................................................................................................................... 20
3.2.1 Rx Termination ............................................................................................................................................ 20
3.2.1.1 Receive Differential Mode ........................................................................................................... 20
3.2.2 Equalizer ..................................................................................................................................................... 22
3.2.2.1 Line Monitor ................................................................................................................................ 22
3.2.2.2 Receive Sensitivity ...................................................................................................................... 22
3.2.3 Slicer ........................................................................................................................................................... 23
3.2.4 Rx Clock & Data Recovery ......................................................................................................................... 23
3.2.5 Decoder ...................................................................................................................................................... 23
3.2.6 Receive System Interface ........................................................................................................................... 23
3.2.7 Receiver Power Down ................................................................................................................................ 24
3.3 TRANSMIT PATH .................................................................................................................................................... 24
3.3.1 Transmit System Interface .......................................................................................................................... 24
3.3.2 Tx Clock Recovery ...................................................................................................................................... 25
3.3.3 Encoder ....................................................................................................................................................... 25
3.3.4 Waveform Shaper ....................................................................................................................................... 25
3.3.4.1 Preset Waveform Template ........................................................................................................ 25
3.3.4.2 User-Programmable Arbitrary Waveform .................................................................................... 27
3.3.5 Line Driver ................................................................................................................................................... 29
3.3.5.1 Transmit Over Current Protection ............................................................................................... 29
3.3.6 Tx Termination ............................................................................................................................................ 29
3.3.6.1 Transmit Differential Mode .......................................................................................................... 29
3.3.7 Transmitter Power Down ............................................................................................................................ 31
3.3.8 Output High-Z on TTIP and TRING ............................................................................................................ 31
3.4 JITTER ATTENUATOR (RJA & TJA) ....................................................................................................................... 32
3.5 DIAGNOSTIC FACILITIES ....................................................................................................................................... 33
3.5.1 Bipolar Violation (BPV) / Code Violation (CV) Detection and BPV Insertion .............................................. 33
Table of Contents
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Table of Contents 4 December 17, 2009
3.5.1.1 Bipolar Violation (BPV) / Code Violation (CV) Detection ............................................................. 33
3.5.1.2 Bipolar Violation (BPV) Insertion ................................................................................................. 33
3.5.2 Excessive Zeroes (EXZ) Detection ............................................................................................................. 33
3.5.3 Loss of Signal (LOS) Detection ................................................................................................................... 34
3.5.3.1 Line LOS (LLOS) ......................................................................................................................... 34
3.5.3.2 System LOS (SLOS) ................................................................................................................... 35
3.5.3.3 Transmit LOS (TLOS) ................................................................................................................. 36
3.5.4 Alarm Indication Signal (AIS) Detection and Generation ............................................................................ 37
3.5.4.1 Alarm Indication Signal (AIS) Detection ...................................................................................... 37
3.5.4.2 (Alarm Indication Signal) AIS Generation ................................................................................... 37
3.5.5 PRBS, QRSS, ARB and IB Pattern Generation and Detection ................................................................... 38
3.5.5.1 Pattern Generation ...................................................................................................................... 38
3.5.5.2 Pattern Detection ........................................................................................................................ 39
3.5.6 Error Counter .............................................................................................................................................. 40
3.5.6.1 Automatic Error Counter Updating .............................................................................................. 40
3.5.6.2 Manual Error Counter Updating .................................................................................................. 41
3.5.7 Loopback .................................................................................................................................................... 42
3.5.7.1 Analog Loopback ........................................................................................................................ 42
3.5.7.2 Remote Loopback ....................................................................................................................... 43
3.5.7.3 Digital Loopback .......................................................................................................................... 44
3.5.8 Channel 0 Monitoring .................................................................................................................................. 45
3.5.8.1 G.772 Monitoring ......................................................................................................................... 45
3.5.8.2 Jitter Measurement (JM) ............................................................................................................. 46
3.6 CLOCK INPUTS AND OUTPUTS ............................................................................................................................ 47
3.6.1 Free Running Clock Outputs on CLKT1/CLKE1 ......................................................................................... 47
3.6.2 MCLK, Master Clock Input .......................................................................................................................... 48
3.6.3 XCLK, Internal Reference Clock Input ........................................................................................................ 48
3.7 INTERRUPT SUMMARY ......................................................................................................................................... 49
4 MISCELLANEOUS .......................................................................................................................................................... 51
4.1 RESET ..................................................................................................................................................................... 51
4.1.1 Power-On Reset ......................................................................................................................................... 52
4.1.2 Hardware Reset .......................................................................................................................................... 52
4.1.3 Global Software Reset ................................................................................................................................ 52
4.1.4 Per-Channel Software Reset ...................................................................................................................... 52
4.2 MICROPROCESSOR INTERFACE ......................................................................................................................... 52
4.3 POWER UP .............................................................................................................................................................. 53
4.4 HITLESS PROTECTION SWITCHING (HPS) SUMMARY ...................................................................................... 53
5 PROGRAMMING INFORMATION ................................................................................................................................... 56
5.1 REGISTER MAP ...................................................................................................................................................... 56
5.1.1 Global Register ........................................................................................................................................... 56
5.1.2 Per-Channel Register ................................................................................................................................. 57
5.2 REGISTER DESCRIPTION ..................................................................................................................................... 60
5.2.1 Global Register ........................................................................................................................................... 60
5.2.2 Per-Channel Register ................................................................................................................................. 65
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Table of Contents 5 December 17, 2009
6 JTAG ............................................................................................................................................................................... 95
6.1 JTAG INSTRUCTION REGISTER (IR) .................................................................................................................... 95
6.2 JTAG DATA REGISTER .......................................................................................................................................... 95
6.2.1 Device Identification Register (IDR) ............................................................................................................ 95
6.2.2 Bypass Register (BYP) ............................................................................................................................... 95
6.2.3 Boundary Scan Register (BSR) .................................................................................................................. 95
6.3 TEST ACCESS PORT (TAP) CONTROLLER ......................................................................................................... 95
7 THERMAL MANAGEMENT ............................................................................................................................................ 97
7.1 JUNCTION TEMPERATURE ................................................................................................................................... 97
7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................. 97
7.3 HEATSINK EVALUATION ....................................................................................................................................... 97
8 PHYSICAL AND ELECTRICAL SPECIFICATIONS ....................................................................................................... 98
8.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................... 98
8.2 RECOMMENDED OPERATING CONDITIONS ...................................................................................................... 99
8.3 DEVICE POWER CONSUMPTION AND DISSIPATION (TYPICAL) 1 ................................................................. 100
8.4 DEVICE POWER CONSUMPTION AND DISSIPATION (MAXIMUM) 1 ............................................................... 101
8.5 D.C. CHARACTERISTICS ..................................................................................................................................... 102
8.6 E1 RECEIVER ELECTRICAL CHARACTERISTICS ............................................................................................. 103
8.7 T1/J1 RECEIVER ELECTRICAL CHARACTERISTICS ......................................................................................... 105
8.8 E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ...................................................................................... 106
8.9 T1/J1 TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................. 107
8.10 TRANSMITTER AND RECEIVER TIMING CHARACTERISTICS ......................................................................... 108
8.11 CLKE1 TIMING CHARACTERISTICS ................................................................................................................... 110
8.12 JITTER ATTENUATION CHARACTERISTICS ...................................................................................................... 111
8.13 MICROPROCESSOR INTERFACE TIMING ......................................................................................................... 114
8.13.1 Serial Microprocessor Interface ................................................................................................................ 114
8.14 JTAG TIMING CHARACTERISTICS ..................................................................................................................... 116
GLOSSARY ......................................................................................................................................................................... 117
INDEX .................................................................................................................................................................................. 119
ORDERING INFORMATION ................................................................................................................................................ 121
List of Tables 6 December 17, 2009
Table-1 Operation Mode Selection ........................................................................................................................................................................... 20
Table-2 Impedance Matching Value in Receive Differential Mode ........................................................................................................................... 21
Table-3 Multiplex Pin Used in Receive System Interface ......................................................................................................................................... 23
Table-4 Multiplex Pin Used in Transmit System Interface ........................................................................................................................................ 25
Table-5 PULS[3:0] Setting in T1/J1 Mode ................................................................................................................................................................. 26
Table-6 PULS[3:0] Setting in E1 Mode ..................................................................................................................................................................... 26
Table-7 Transmit Waveform Value for T1 0 ~ 133 ft ................................................................................................................................................. 28
Table-8 Transmit Waveform Value for T1 133 ~ 266 ft ............................................................................................................................................. 28
Table-9 Transmit Waveform Value for T1 266 ~ 399 ft ............................................................................................................................................. 28
Table-10 Transmit Waveform Value for T1 399 ~ 533 ft ............................................................................................................................................. 28
Table-11 Transmit Waveform Value for T1 533 ~ 655 ft ............................................................................................................................................. 28
Table-12 Transmit Waveform Value for E1 75 ohm .................................................................................................................................................... 28
Table-13 Transmit Waveform Value for E1 120 ohm .................................................................................................................................................. 28
Table-14 Transmit Waveform Value for J1 0 ~ 655 ft ................................................................................................................................................. 28
Table-15 Impedance Matching Value in Transmit Differential Mode .......................................................................................................................... 29
Table-16 EXZ Definition .............................................................................................................................................................................................. 33
Table-17 LLOS Criteria ............................................................................................................................................................................................... 34
Table-18 SLOS Criteria ............................................................................................................................................................................................... 35
Table-19 TLOS Detection Between Two Channels .................................................................................................................................................... 36
Table-20 AIS Criteria ................................................................................................................................................................................................... 37
Table-21 Clock Output on CLKT1 ............................................................................................................................................................................... 47
Table-22 Clock Output on CLKE1 ............................................................................................................................................................................... 47
Table-23 Interrupt Summary ....................................................................................................................................................................................... 49
Table-24 After Reset Effect Summary ........................................................................................................................................................................ 51
List of Tables
List of Figures 7 December 17, 2009
Figure-1 Functional Block Diagram ............................................................................................................................................................................ 10
Figure-2 484-Pin Fine Pitch BGA (Top View) ............................................................................................................................................................. 11
Figure-3 Switch between Impedance Matching Modes .............................................................................................................................................. 20
Figure-4 Receive Differential Line Interface with Twisted Pair Cable (with transformer) ........................................................................................... 21
Figure-5 Receive Differential Line Interface with Coaxial Cable (with transformer) ................................................................................................... 21
Figure-6 Receive Differential Line Interface with Twisted Pair Cable (transformer-less, non standard compliant) .................................................... 22
Figure-7 Receive Path Monitoring .............................................................................................................................................................................. 22
Figure-8 Transmit Path Monitoring ............................................................................................................................................................................. 22
Figure-9 DSX-1 Waveform Template ......................................................................................................................................................................... 25
Figure-10 T1 Waveform Template Measurement Circuit ............................................................................................................................................. 25
Figure-11 E1 Waveform Template ............................................................................................................................................................................... 26
Figure-12 E1 Waveform Template Measurement Circuit ............................................................................................................................................ 26
Figure-13 Transmit Differential Line Interface with Twisted Pair Cable (with Transformer) ........................................................................................ 30
Figure-14 Transmit Differential Line Interface with Coaxial Cable (with transformer) ................................................................................................. 30
Figure-15 Transmit Differential Line Interface with Twisted Pair Cable (transformer-less, non standard compliant) .................................................. 30
Figure-16 Jitter Attenuator ........................................................................................................................................................................................... 32
Figure-17 LLOS Indication on Pins .............................................................................................................................................................................. 34
Figure-18 TLOS Detection Between Two Channels .................................................................................................................................................... 36
Figure-19 Pattern Generation (1) ................................................................................................................................................................................. 38
Figure-20 Pattern Generation (2) ................................................................................................................................................................................. 38
Figure-21 PRBS / ARB Detection ................................................................................................................................................................................ 39
Figure-22 IB Detection ................................................................................................................................................................................................. 40
Figure-23 Automatic Error Counter Updating .............................................................................................................................................................. 41
Figure-24 Manual Error Counter Updating .................................................................................................................................................................. 41
Figure-25 Priority Of Diagnostic Facilities During Analog Loopback ........................................................................................................................... 42
Figure-26 Priority Of Diagnostic Facilities During Manual Remote Loopback ............................................................................................................. 43
Figure-27 Priority Of Diagnostic Facilities During Digital Loopback ............................................................................................................................ 44
Figure-28 G.772 Monitoring ......................................................................................................................................................................................... 45
Figure-29 Automatic JM Updating ............................................................................................................................................................................... 46
Figure-30 Manual JM Updating ................................................................................................................................................................................... 46
Figure-31 Interrupt Service Process ............................................................................................................................................................................ 50
Figure-32 Reset ........................................................................................................................................................................................................... 51
Figure-33 1+1 HPS Scheme, Differential Interface (Shared Common Transformer) .................................................................................................. 53
Figure-34 1:1 HPS Scheme, Differential Interface (Individual Transformer) ............................................................................................................... 54
Figure-35 1+1 HPS Scheme, E1 75 ohm Single-Ended Interface (Shared Common Transformer) ........................................................................... 55
Figure-36 JTAG Architecture ....................................................................................................................................................................................... 95
Figure-37 JTAG State Diagram ................................................................................................................................................................................... 96
Figure-38 Transmit Clock Timing Diagram ................................................................................................................................................................ 109
Figure-39 Receive Clock Timing Diagram ................................................................................................................................................................. 109
Figure-40 CLKE1 Clock Timing Diagram ................................................................................................................................................................... 110
Figure-41 E1 Jitter Tolerance Performance ............................................................................................................................................................... 112
Figure-42 T1/J1 Jitter Tolerance Performance .......................................................................................................................................................... 112
Figure-43 E1 Jitter Transfer Performance ................................................................................................................................................................. 113
Figure-44 T1/J1 Jitter Transfer Performance ............................................................................................................................................................. 113
Figure-45 Read Operation in Serial Microprocessor Interface .................................................................................................................................. 114
Figure-46 Write Operation in Serial Microprocessor Interface ................................................................................................................................... 114
Figure-47 Timing Diagram ......................................................................................................................................................................................... 115
Figure-48 JTAG Timing ............................................................................................................................................................................................. 116
List of Figures
8 December 17, 2009
IDT82P20416
2009 Integrated Device Technology, Inc. DSC-7263/--
16-Channel
Short Haul T1/E1/J1 Line
Interface Unit
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
FEATURES
Integrates 16 channels T1/E1/J1 short haul line interface units
for 100 Ω T1, 120 Ω E1, 110 Ω J1 twisted pair cable and 75 Ω
E1 coaxial cable applications
Per-channel configurable Line Interface options
• Fully integrated and software selectable receive and transmit
termination
–Option 1: Fully Internal Impedance Matching with integrated receive
termination resistor
–Option 2: Partially Internal Impedance Matching with common external
resistor for improved device power dissipation
–Option 3: External impedance Matching termination
• Supports global configuration and per-channel configuration to
T1, E1 or J1 mode
Per-channel programmable features
• Provides T1/E1/J1 short haul waveform templates and user-
programmable arbitrary waveform templates
• Provides two JAs (Jitter Attenuator) for each channel of receiver
and transmitter
• Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) encoding
and decoding
Per-channel System Interface options
• Supports Single Rail, Dual Rail with clock or without clock and
sliced system interface
• Integrated Clock Recovery for the transmit interface to recover
transmit clock from system transmit data
Per-channel system and diagnostic functions
• Provides transmit driver over-current detection and protection
with optional automatic high impedance of transmit interface
• Detects and generates PRBS (Pseudo Random Bit Sequence),
ARB (Arbitrary Pattern) and IB (Inband Loopback) in either
receive or transmit direction
• Provides defect and alarm detection in both receive and transmit
directions.
–Defects include BPV (Bipolar Violation) /CV (Code Violation) and EXZ
(Excessive Zeroes)
–Alarms include LLOS (Line LOS), SLOS (System LOS), TLOS
(Transmit LOS) and AIS (Alarm Indication Signal)
• Programmable LLOS detection /clear levels. Compliant with ITU
and ANSI specifications
• Various pattern, defect and alarm reporting options
–Serial hardware LLOS reporting (LLOS, LLOS0) for all 16 channels
–Register access to individual registers or 16-bit error counters
• Supports Analog Loopback, Digital Loopback and Remote
Loopback
• Supports T1.102 line monitor
Hitless Protection Switching (HPS) without external Relays
• Supports 1+1 and 1:1 hitless protection switching
• Asynchronous hardware control (OE, RIM) for fast global high
impedance of receiver and transmitter (hot switching between
working and backup board)
• High impedance transmitter and receiver while powered down
• Per-channel register control for high impedance, independent for
receiver and transmitter
Clock Inputs and Outputs
• Flexible master clock (N x 1.544 MHz or N x 2.048 MHz) (1 ≤ N ≤
8, N is an integer number)
• Integrated clock synthesizer can multiply or divide the reference
clock to a wide range of frequencies: 8 KHz, 64 KHz, 2.048 MHz,
4.096 MHz, 8.192 MHz, 19.44 MHz and 32.768 MHz
Microprocessor Interface
• Supports Serial microprocessor interface
Other Key Features
• IEEE1149.1 JTAG boundary scan
• Two general purpose I/O pins
• 3.3 V I/O with 5 V tolerant inputs
• 3.3 V and 1.8 V power supply
• Package: 484-pin Fine Pitch BGA (19 mm X 19 mm)
Applicable Standards
• AT&T Pub 62411 Accunet T1.5 Service
• ANSI T1.102, T1.403 and T1.231
• Bellcore TR-TSY-000009, GR-253-CORE and GR-499-CORE
• ETSI CTR12/13
• ETS 300166 and ETS 300 233
• G.703, G.735, G.736, G.742, G.772, G.775, G.783 and G.823
• O.161
• ITU I.431 and ITU O.171
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Applications 9 December 17, 2009
APPLICATIONS
SDH/SONET multiplexers
Central office or PBX (Private Branch Exchange)
Digital access cross connects
Remote wireless modules
Microwave transmission systems
DESCRIPTION
The IDT82P20416 is a 16-channel high-density T1/E1/J1 short haul
Line Interface Unit. Each channel of the IDT82P20416 can be indepen-
dently configured. The configuration is performed through a Serial
microprocessor interface.
In the receive path, through a Single Ended or Differential line inter-
face, the received signal is processed by an adaptive Equalizer and then
sent to a Slicer. Clock and data are recovered from the digital pulses
output from the Slicer. After passing through an enabled or disabled
Receive Jitter Attenuator, the recovered data is decoded using B8ZS/
AMI/HDB3 line code rule in Single Rail NRZ Format mode and output to
the system, or output to the system without decoding in Dual Rail NRZ
Format mode and Dual Rail RZ Format mode.
In the transmit path, the data to be transmitted is input on TDn in
Single Rail NRZ Format mode or TDPn/TDNn in Dual Rail NRZ Format
mode and Dual Rail RZ Format mode, and is sampled by a transmit
reference clock. The clock can be supplied externally from TCLKn or
recovered from the input transmit data by an internal Clock Recovery. A
selectable JA in Tx path is used to de-jitter gapped clocks. To meet T1/
E1/J1 waveform standards, five preset T1 templates, two E1 templates
and one J1 template, as well as an arbitrary waveform generator are
provided. The data through the Waveform Shaper, the Line Driver and
the Tx Transmitter is output on TTIPn and TRINGn.
Alarms (including LOS, AIS) and defects (including BPV, EXZ) are
detected in both receive line side and transmit system side. AIS alarm,
PRBS, ARB and IB patterns can be generated /detected in receive /
transmit direction for testing purpose. Analog Loopback, Digital Loop-
back and Remote Loopback are all integrated for diagnostics.
A line monitor function per T1.102 is available to provide a Non-Intru-
sive Monitoring of channels of other devices.
JTAG per IEEE 1149.1 is also supported by the IDT82P20416.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Block Diagram 10 December 17, 2009
BLOCK DIAGRAM
Figure-1 Functional Block Diagram
Rx
Terminator Amplifier Slicer
Rx Clock &
Data
Recovery
RJA Decoder
Defect/Alarm
Detector
RTIP[15:0]
RRING[15:0]
LLOS
RCLK[15:0]
RDN[15:0]
RD[15:0]/RDP[15:0]
LLOS0
Tx Clock
Recovery
EncoderTJA
Waveform
Shaper
Tx
Terminator
Line
Driver
TTIP[15:0]
TRING[15:0]
TCLK[15:0]/TDN[15:0]
TDN[15:0]
TD[15:0]/TDP[15:0]
Analog
Loopback
Alarm
Generator
Digital Loopback
Remote Loopback
Defect/Alarm
Detector
G.772
Monitor
VDDIO
VDDA
GNDA
VDDD
GNDD
GNDT
VDDT
VDDR
Clock Generator
MCLK
MCKSEL[3:0]
CLKT1
CLKE1
CLKA
CLKB
JTAG
TRST
TMS
TCK
TDI
TDO
CS
INT
SDO
SCLK
SDI
MCU InterfaceCommon Control
OE
TEHWE
TEHW
REF
RST
GPIO[1:0]
RIM
VCOM[1:0]
VCOMEN
Pattern
Generator/
Detector
RCLK[15:0]
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Assignment 11 December 17, 2009
1 PIN ASSIGNMENT
Figure-2 484-Pin Fine Pitch BGA (Top View)
NC NC NC NC RD15/
RDP15 TDN14 RCLK1
4TDN13 RCLK1
3TDN12 TDN11 RCLK1
0TDN10 RCLK9 TDN9 RCLK8 NC NC NC NC
INT LLOS NC CLKE1
NC NC NC NC TCLK15
/TDN15
TD14/
TDP14 RDN14 TD13/
TDP13 NC NC NC NC
GNDD RD10/
RDP10 GNDD RD9/
RDP9
TRING
12 NC NC NC TD15/
TDP15 GNDD GNDD GNDD GNDD GNDD GNDD GNDD TDN8 NC NC NC NC
TDN3 RCLK3 TDN4 RD4/
RDP4
TTIP12 NC NC NC TDN15 RDN15 TCLK14
/TDN14 VDDIO TCLK13
/TDN13 GNDD TCLK12
/TDN12
TCLK11
/TDN11 VDDIO VDDIO TCLK9/
TDN9 VDDIO TD8/
TDP8 NC NC NC NC
TD0/
TDP0 TDN0 RCLK0 TRST
TRING
13 GNDA GNDA GNDA
TTIP13 NC GNDA GNDA
TRING
14 NC RTIP12 RRING
12
TTIP14 NC RTIP13 RRING
13
TRING
15 NC RTIP14 RRING
14
TTIP15 NC RTIP15 RRING
15
TRING
0NC RTIP0 RRING
0
TTIP0 NC RTIP1 RRING
1
TRING
1NC RTIP2 RRING
2
TTIP1 NC RTIP3 RRING
3
TRING
2NC RTIP4 RRING
4
TTIP2 NC GNDA GNDA
TRING
3NC GNDA GNDA
TTIP3 NC GNDA TD1/
TDP1
TRING
4NC TCLK1/
TDN1 RCLK1
TTIP4 RD1/
RDP1 TDN1 NC
GNDD GNDD GNDD
VDDR1
1
VDDR9 GNDT VDDR1
0GNDT
VDDT GNDT VDDT
GNDT VDDR7
NC RCLK1
5
RD14/
RDP14 GNDD
VDDD GNDD GNDD VDDD
GNDD GNDD
GNDD GNDD
RD13/
RDP13 VDDIO
NC NC
NC VDDD
RDN1 TCLK2/
TDN2
GNDD GNDD
TDN2 TD2/
TDP2
GNDD GNDD
NC NC
NC VDDD VDDD GNDD
TCLK3/
TDN3
TCLK4/
TDN4 RDN0 GPIO0
RDN2 RDN3 RDN4 TCLK0/
TDN0
NC NC NC NC
GNDD GNDD GNDD GNDD
OE TEHWE CS CLKB
TMS TCK SDI NC
NC NC NC NC
GNDD GNDD
VDDT NC
MCK
SEL3
TCLK6/
TDN6
VDDIO NC
CLKT1 MCKSE
L1
GNDD VDDD
NC NC
GNDD GNDD
VDDT VDDT
TDO TEHW RIM SCLK
GNDA GNDA NC TRING
11
GNDA GNDA NC TTIP11
RRING
11 RTIP11 NC TRING
10
RRING
10 RTIP10 NC TTIP10
RRING
9RTIP9 NC TRING
9
RRING
8RTIP8 NC TTIP9
VCOM
EN REF NC TRING
8
VCOM1 VCOM0 GNDA TTIP8
RRING
7RTIP7 VDDA TRING
7
RRING
6RTIP6 NC TTIP7
RRING
5RTIP5 NC TRING
6
VDDT GNDA NC TTIP6
GNDA GNDA NC TRING
5
TD6/
TDP6 GNDA GNDA TTIP5
RDN5 IC NC NC
NC GNDD NC NC
TDN5 RD5/
RDP5 TDN6 RCLK6
VDDT VDDR6
GNDD GNDT
VDDD VDDIO
RDN6 VDDD
RCLK1
2
RCLK1
1
TD10/
TDP10
RDN10
TD11/
TDP11
RDN11RDN12
TD12/
TDP12
RDN13
GNDD GNDD GNDD GNDD GNDD
TCLK10
/TDN10
GNDD
GNDD GNDD GNDD GNDD
GNDT GNDT GNDT
GNDT
GNDA GNDT
VDDD VDDD
NC VDDR1
2
RD8/
RDP8
TD9/
TDP9
RDN9
GNDT GNDT GNDT GNDT GNDT GNDT
VDDT VDDT GNDT VDDR1
3
VDDR0 VDDR1
5VDDT GNDT
VDDT VDDT VDDR2 GNDT
VDDT VDDT VDDR3 GNDT
VDDT VDDT GNDT VDDR4
VDDT VDDT NC NC
NC NC VDDIO VDDD
GNDD VDDIO VDDIO VDDD
VDDD GNDD GNDD GNDD
GNDT GNDT GNDT VDDA
GNDD GNDD NC GNDD
VDDT GNDT GNDT GNDT
VDDR1 VDDT GNDT VDDA
VDDR1
4GNDT GNDT GNDT
11098765432122221201918171615141311
A
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RDN8 TCLK8/
TDN8
VDDD VDDD
GNDD NC
GNDD NC
VDDT VDDT
VDDT VDDT
VDDR8 NC
VDDT VDDA
VDDT VDDT
VDDR5 NC
GNDD NC
GNDD VDDT
GNDD NC
TD7/
TDP7 RDN7
TCLK5/
TDN5 RCLK7
NC NC
MCKSE
L0 MCLK
RD12/
RDP12
RD11/
RDP11
VDDD GNDD
GNDD GNDD
VDDD VDDD VDDD VDDD
GNDD VDDIO
LLOS0 CLKA MCKSE
L2
TD5/
TDP5
NC RD2/
RDP2 RCLK2 TD3/
TDP3
RD3/
RDP3
TD4/
TDP4 RCLK4 RD0/
RDP0 TDI GPIO1 RST SDO TDN7 TCLK7/
TDN7
RD7/
RDP7 NC
RCLK5 RD6/
RDP6
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description 12 December 17, 2009
2 PIN DESCRIPTION
Name I / O Pin No. 1Description
Line Interface
RTIPn
RRINGn
(n=0~15)
Input L3, M3, N3, P3, R3, R20, P20, N20,
K20, J20, H20, G20, G3, H3, J3, K3
L4, M4, N4, P4, R4, R19, P19, N19,
K19, J19, H19, G19, G4, H4, J4, K4
RTIPn / RRINGn: Receive Bipolar Tip/Ring for Channel 0 ~ 15
The receive line interface supports both Receive Differential mode and Receive Single Ended
mode.
In Receive Differential mode, the received signal is coupled into RTIPn and RRINGn via a 1:1
transformer or without a transformer (transformer-less).
In Receive Single Ended mode, RRINGn should be left open. The received signal is input on
RTIPn via a 2:1 (step down) transformer or without a transformer (transformer-less).
These pins will become High-Z globally or channel specific in the following conditions:
• Global High-Z:
- Connecting the RIM pin to low;
- Loss of MCLK
- During and after power-on reset, hardware reset or global software reset;
• Per-channel High-Z
- Receiver power down by writing ‘1’ to the R_OFF bit (b5, RCF0,...)
TTIPn
TRINGn
(n=0~15)
Output M1, P1, T1, V1, Y1, V22, T22, P22,
M22, K22, H22, F22, D1, F1, H1, K1
L1, N1, R1, U1, W1, U22, R22, N22,
L22, J22, G22, E22, C1, E1, G1, J1
TTIPn / TRINGn: Transmit Bipolar Tip /Ring for Channel 0 ~ 15
The transmit line interface supports both Transmit Differential mode and Transmit Single
Ended mode.
In Transmit Differential mode, TTIPn outputs a positive differential pulse while TRINGn out-
puts a negative differential pulse. The pulses are coupled to the line side via a 1:2 (step up)
transformer or without a transformer (transformer-less).
In Transmit Single Ended mode, TRINGn should be left open (it is shorted to ground inter-
nally). The signal presented at TTIPn is output to the line side via a 1:2 (step up) transformer.
These pins will become High-Z globally or channel specific in the following conditions:
• Global High-Z:
- Connecting the OE pin to low;
- Loss of MCLK;
- During and after power-on reset, hardware reset or global software reset;
• Per-channel High-Z
- Writing ‘0’ to the OE bit (b6, TCF0,...) 2;
- Loss of TCLKn in Transmit Single Rail NRZ Format mode or Transmit Dual Rail NRZ
Format mode, except that the channel is in Remote Loopback or transmit internal pat-
tern with XCLK 3;
- Transmitter power down by writing ‘1’ to the T_OFF bit (b5, TCF0,...);
- Per-channel software reset;
- The THZ_OC bit (b4, TCF0,...) is set to ‘1’ and the transmit driver over-current is
detected.
Refer to Section 3.3.8 Output High-Z on TTIP and TRING for details.
Note:
1. The pin number of the pins with the footnote ‘n’ is listed in order of channel (CH0 ~ CH15).
2. The content in the brackets indicates the position and the register name of the preceding bit. After the register name, if the punctuation ‘,...’ is followed, this bit is in a per-channel register.
The addresses and details are included in Chapter 5 Programming Information.
3. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz in E1 mode.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description 13 December 17, 2009
Name I / O Pin No. Description
System Interface
RDn / RDPn
(n=0~15)
Output AA8, Y2, AA2, AA5, AB4, AB20,
AA18, AA21, B18, E16, E14, E12,
E11, E9, E7, A5
RDn: Receive Data for Channel 0 ~ 15
When the receive system interface is configured to Single Rail NRZ Format mode, this multi-
plex pin is used as RDn.
The decoded NRZ data is updated on the active edge of RCLKn. The active level on RDn is
selected by the RD_INV bit (b3, RCF1,...).
When the receiver is powered down, RDn will be in High-Z state or low, as selected by the
RHZ bit (b6, RCF0,...).
RDPn: Positive Receive Data for Channel 0 ~ 15
When the receive system interface is configured to Dual Rail NRZ Format mode, Dual Rail RZ
Format mode or Dual Rail Sliced mode, this multiplex pin is used as RDPn.
In Receive Dual Rail NRZ Format mode, the un-decoded NRZ data is output on RDPn and
RDNn and updated on the active edge of RCLKn.
In Receive Dual Rail RZ Format mode, the un-decoded RZ data is output on RDPn and RDNn
and updated on the active edge of RCLKn.
In Receive Dual Rail Sliced mode, the raw RZ sliced data is output on RDPn and RDNn.
For Receive Differential line interface, an active level on RDPn indicates the receipt of a posi-
tive pulse on RTIPn and a negative pulse on RRINGn; while an active level on RDNn indi-
cates the receipt of a negative pulse on RTIPn and a positive pulse on RRINGn.
For Receive Single Ended line interface, an active level on RDPn indicates the receipt of a
positive pulse on RTIPn; while an active level on RDNn indicates the receipt of a negative
pulse on RTIPn.
The active level on RDPn and RDNn is selected by the RD_INV bit (b3, RCF1,...).
When the receiver is powered down, RDPn and RDNn will be in High-Z state or low, as
selected by the RHZ bit (b6, RCF0,...).
RDNn
(n=0~15)
Output V9, V5, W7, W8, W9, W19, T15,
V18, E17, B16, B14, B12, B11, B9,
B7, D6
RDNn: Negative Receive Data for Channel 0 ~ 15
When the receive system interface is configured to Dual Rail NRZ Format mode, Dual Rail RZ
Format mode or Dual Rail Sliced mode, this multiplex pin is used as RDNn.
(Refer to the description of RDPn for details).
RCLKn
(n=0~15)
Output AB7, W4, AA3, AB2, AA7, AA17,
AB22, W18, A18, A16, A14, A12,
A11, A9, A7, E6
RCLKn: Receive Clock for Channel 0 ~ 15
When the receive system interface is configured to Single Rail NRZ Format mode, Dual Rail
NRZ Format mode or Dual Rail RZ Format mode, this multiplex pin is used as RCLKn.
RCLKn outputs a 1.544 MHz (in T1/J1 mode) or 2.048 MHz (in E1 mode) clock which is
recovered from the received signal.
The data output on RDPn/RDNn (in Receive Dual Rail NRZ Format mode, Receive Dual Rail
RZ Format mode and Receive Dual Rail Sliced) is updated on the active edge of RCLKn. The
active edge is selected by the RCK_ES bit (b4, RCF1,...).
In LLOS condition, RCLKn output high or XCLK, as selected by the RCKH bit (b7,
RCF0,...) (refer to Section 3.5.3.1 Line LOS (LLOS) for details).
When the receiver is powered down, RCLKn will be in High-Z state or low, as selected by the
RHZ bit (b6, RCF0,...).
LLOS Output AB14 LLOS: Receive Line Loss Of Signal
LLOS synchronizes with the output of CLKE1 and can indicate the LLOS (Line LOS) status of
all 16 channels in a serial format.
When the clock output on CLKE1 is enabled, LLOS indicates the LLOS status of the 16 chan-
nels in a serial format and repeats every seventeen cycles. The start filler is positioned by
LLOS0. Refer to the description of LLOS0 below for details.
LLOS is updated on the rising edge of CLKE1 and is always active high.
When the clock output of CLKE1 is disabled, LLOS will be held in High-Z state.
(Refer to Section 3.5.3.1 Line LOS (LLOS) for details.)
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description 14 December 17, 2009
LLOS0 Output AA13 LLOS0: Receive Line Loss Of Signal for Start Position
LLOS0 can indicate the start position on the LLOS pin.
When the clock output on CLKE1 is enabled, LLOS0 pulses high for one CLKE1 clock cycle to
indicate the start position on the LLOS pin. When CLKE1 outputs 8 KHz clock, LLOS0 pulses
high for one 8 KHz clock cycle (125 µs) every seventeen 8 KHz clock cycles; when CLKE1
outputs 2.048 MHz clock, LLOS0 pulses high for one 2.048 MHz clock cycle (488 ns) every
seventeen 2.048 MHz clock cycles. LLOS0 is updated on the rising edge of CLKE1.
When the clock output on CLKE1 is disabled, LLOS0 will be held in High-Z state.
(Refer to Section 3.5.3.1 Line LOS (LLOS) for details.)
TDn / TDPn
(n=0~15)
Input AB5, V4, W6, AA4, AA6, AA16,
V19, V17, D18, B17, B15, B13,
B10, B8, B16, C5
TDn: Transmit Data for Channel 0 ~ 15
When the transmit system interface is configured to Single Rail NRZ Format mode, this multi-
plex pin is used as TDn.
TDn accepts Single Rail NRZ data. The data is sampled into the device on the active edge of
TCLKn.
The active level on TDn is selected by the TD_INV bit (b3, TCF1,...).
TDPn: Positive Transmit Data for Channel 0 ~ 15
When the transmit system interface is configured to Dual Rail NRZ Format mode or Dual Rail
RZ Format mode, this multiplex pin is used as TDPn.
In Transmit Dual Rail NRZ Format mode, the pre-encoded NRZ data is input on TDPn and
TDNn and sampled on the active edge of TCLKn.
In Transmit Dual Rail RZ Format mode, the pre-encoded RZ data is input on TDPn and TDNn.
The line code is as follows (when the TD_INV bit (b3, TCF1,...) is ‘0’):
The active level on TDPn and TDNn is selected by the TD_INV bit (b3, TCF1,...).
TDNn
(n=0~15)
Input / Output AB6, Y3, W5, AB1, AB3, AB19,
AB21, AA19, C18, A17, A15, A13,
A10, A8, A6, D5
TDNn: Negative Transmit Data for Channel 0 ~ 15
When the transmit system interface is configured to Dual Rail NRZ Format mode, this multi-
plex pin is used as TDNn.
(Refer to the description of TDPn for details).
TCLKn / TDNn
(n=0~15)
Input W10, W3, V6, V7, V8, W17, V16,
AA20, E18, D16, D14, D12, D11,
D9, D7, B5
TCLKn: Transmit Clock for Channel 0 ~ 15
When the transmit system interface is configured to Single Rail NRZ Format mode or Dual
Rail NRZ Format mode, this multiplex pin is used as TCLKn.
TCLKn inputs a 1.544 MHz (in T1/J1 mode) or 2.048 MHz (in E1 mode) clock.
The data input on TDn (in Transmit Single Rail NRZ Format mode) or TDPn/TDNn (in Trans-
mit Dual Rail NRZ Format mode) is sampled on the active edge of TCLKn.
TDNn: Negative Transmit Data for Channel 0 ~ 15
When the transmit system interface is configured to Dual Rail RZ Format mode, this multiplex
pin is used as TDNn.
(Refer to the description of TDPn for details).
Name I / O Pin No. Description
TDPn TDNn Output Pulse on TTIPn Output Pulse on TRINGn *
0 0 Space Space
0 1 Negative Pulse Positive Pulse
1 0 Positive Pulse Negative Pulse
1 1 Space Space
Note:
* For Transmit Single Ended line interface, TRINGn should be open.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description 15 December 17, 2009
Clock
MCLK Input AB18 MCLK: Master Clock Input
MCLK provides a stable reference timing for the IDT82P20416. MCLK should be a clock with
+/-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1 mode) accuracy. The clock frequency of MCLK
is informed to the device by MCKSEL[3:0].
If MCLK misses (duty cycle is less than 30% for 10 µs) and then recovers, the device will be
reset automatically.
MCKSEL[0]
MCKSEL[1]
MCKSEL[2]
MCKSEL[3]
Input AB17
W16
AA15
V15
MCKSEL[3:0]: Master Clock Selection
These four pins inform the device of the clock frequency input on MCLK:
CLKT1 Output W15 CLKT1: 8 KHz / T1 Clock Output
The output on CLKT1 can be enabled or disabled, as determined by the CLKT1_EN bit (b1,
CLKG).
When the output is enabled, CLKT1 outputs an 8 KHz or 1.544 MHz clock, as selected by the
CLKT1 bit (b0, CLKG). The output is locked to MCLK.
When the output is disabled, CLKT1 is in High-Z state.
CLKE1 Output AB16 CLKE1: 8 KHz / E1 Clock Output
The output on CLKE1 can be enabled or disabled, as determined by the CLKE1_EN bit (b3,
CLKG).
When the output is enabled, CLKE1 outputs an 8 KHz or 2.048 MHz clock, as selected by the
CLKE1 bit (b2, CLKG). The output is locked to MCLK.
When the output is disabled, CLKE1 is in High-Z state.
Name I / O Pin No. Description
MCKSEL[3:0]*Frequency (MHz)
0000 1.544
0001 1.544 X 2
0010 1.544 X 3
0011 1.544 X 4
0100 1.544 X 5
0101 1.544 X 6
0110 1.544 X 7
0111 1.544 X 8
1000 2.048
1001 2.048 X 2
1010 2.048 X 3
1011 2.048 X 4
1100 2.048 X 5
1101 2.048 X 6
1110 2.048 X 7
1111 2.048 X 8
Note:
0: GNDD
1: VDDIO
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description 16 December 17, 2009
CLKA Input AA14 CLKA: External T1/E1 Clock Input A
External T1/J1 (1.544 MHz) or E1 (2.048 MHz) clock is input on this pin.
When not used, this pin should be connected to GNDD.
CLKB Input V14 CLKB: External T1/E1 Clock Input B
External T1/J1 (1.544 MHz) or E1 (2.048 MHz) clock is input on this pin.
When not used, this pin should be connected to GNDD.
Common Control
VCOM[0]
VCOM[1]
Output M20
M19
VCOM: Voltage Common Mode [1:0]
These pins are used only when the receive line interface is in Receive Differential mode and
connected without a transformer (transformer-less).
To enable these pins, the VCOMEN pin must be connected high. Refer to Figure-6 for the
connection.
When these pins are not used, they should be left open.
VCOMEN Input
(Pull-Down)
L19 VCOMEN: Voltage Common Mode Enable
This pin should be connected high only when the receive line interface is in Receive Differen-
tial mode and connected without a transformer (transformer-less).
When not used, this pin should be left open.
REF - L20 REF: Reference Resistor
An external resistor (10 KΩ, ±1%) is used to connect this pin to ground to provide a standard
reference current for internal circuit. This resistor is required to ensure correct device opera-
tion.
RIM Input
(Pull-Down)
AB11 RIM: Receive Impedance Matching
In Receive Differential mode, when RIM is low, all 16 receivers become High-Z and only exter-
nal impedance matching is supported. In this case, the per-channel impedance matching con-
figuration bits - the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4, RCF0,...) - are
ignored.
In Receive Differential mode, when RIM is high, impedance matching is configured on a per-
channel basis by the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4, RCF0,...).
This pin can be used to control the receive impedance state for Hitless Protection applica-
tions. Refer to Section 4.4 Hitless Protection Switching (HPS) Summary for details.
In Receive Single Ended mode, this pin should be left open.
OE Input V11 OE: Output Enable
OE enables or disables all Line Drivers globally.
A high level on this pin enables all Line Drivers while a low level on this pin places all Line
Drivers in High-Z state and independent from related register settings.
Note that the functionality of the internal circuit is not affected by OE.
If this pin is not used, it should be tied to VDDIO.
This pin can be used to control the transmit impedance state for Hitless protection applica-
tions. Refer to Section 4.4 Hitless Protection Switching (HPS) Summary for details.
TEHWE Input
(Pull-Up)
V12 TEHWE: Hardware T1/J1 or E1 Mode Selection Enable
When this pin is open, the T1/J1 or E1 operation mode is selected by TEHW globally.
When this pin is low, the T1/J1 or E1 operation mode is selected by the T1E1 bit (b0,
CHCF,...) on a per-channel basis.
TEHW Input
(Pull-Up)
AB10 TEHW: Hardware T1/J1 or E1 Mode Selection
When TEHWE is open, this pin selects the T1/J1 or E1 operation mode globally:
Low - E1 mode;
Open - T1/J1 mode.
When TEHWE is low, the input on this pin is ignored.
Name I / O Pin No. Description
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description 17 December 17, 2009
GPIO[0]
GPIO[1]
Output / Input V10
AA10
GPIO: General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (b1~0, GPIO)
respectively.
When the pins are input, their polarities are indicated by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
When the pins are output, their polarities are controlled by the LEVEL[1:0] bits (b3~2, GPIO)
respectively.
RST Input AA11 RST: Reset (Active Low)
A low pulse on this pin resets the device. This hardware reset process completes in 2 µs max-
imum. Refer to Section 4.1 Reset for an overview on reset options.
MCU Interface
INT Output AB13 INT: Interrupt Request
This pin indicates interrupt requests for all unmasked interrupt sources.
The output characteristics (open drain or push-pull internally) and the active level are deter-
mined by the INT_PIN[1:0] bits (b3~2, GCF).
CS Input V13 CS: Chip Select (Active Low)
This pin must be asserted low to enable the microprocessor interface.
A transition from high to low must occur on this pin for each Read/Write operation and CS
should remain low until the operation is over.
SCLK Input AB12 SCLK: Shift Clock
In Serial microprocessor interface, this multiplex pin is used as SCLK.
SCLK inputs the shift clock for the Serial microprocessor interface. Data on SDI is sampled by
the device on the rising edge of SCLK. Data on SDO is updated on the falling edge of SCLK.
SDI Input W13 SDI: Serial Data Input
In Serial microprocessor interface, this multiplex pin is used as SDI.
Address and data on this pin are serially clocked into the device on the rising edge of SCLK.
SDO Output AA12 SDO: Serial Data Output
In Serial microprocessor interface, this multiplex pin is used as SDO.
Data on this pin is serially clocked out of the device on the falling edge of SCLK.
JTAG (per IEEE 1149.1)
TRST Input
Pull-Down
AB8 TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. To ensure deterministic operation of the test
logic, TMS should be held high when the signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-down resistor.
TMS Input
Pull-up
W11 TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK. To ensure deterministic operation of the test logic, TMS should be held high when the
signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-up resistor.
TCK Input W12 TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
When TCK is idle at low state, all stored-state devices contained in the test logic shall retain
their state indefinitely.
This pin should be connected to GNDD when JTAG is not used.
Name I / O Pin No. Description
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description 18 December 17, 2009
TDI Input
Pull-up
AA9 TDI: JTAG Test Data Input
The test data is input on this pin. It is clocked into the device on the rising edge of TCK. This
pin has an internal pull-up resistor.
This pin may be left unconnected when JTAG is not used.
TDO Output AB9 TDO: JTAG Test Data Output
The test data is output on this pin. It is clocked out of the device on the falling edge of TCK.
TDO is a High-Z output signal except during the process of data scanning.
Power & Ground
VDDIO D8, D13, D15, D17, E10, F12, P13,
R10, R11, R16, T7
VDDIO: 3.3 V I/O Power Supply
VDDA N21, M12, N12, M18 VDDA: 3.3 V Analog Core Power Supply
VDDD F5, F8, F10, F13, F14, F15, F16,
F17, F18, G5, G6, G11, R12, R14,
R15, T8, T9, T16, U8, U9
VDDD: 1.8 V Digital Core Power Supply
VDDRn
(N=0~15)
H6, J16, K8, K9, K13, K15, L5, L6,
L17, M7, M9, M16, N7, N16, P8,
P17
VDDRn: 3.3 V Power Supply for Receiver
VDDT J5, J6, J17, J18, K5, K6, K17, K18,
L7, L9, L13, L16, M5, M6, M10,
M17, N5, N6, N13, N15, N17, N18,
P5, P6, R5, R6, T18, T19
VDDT: 3.3 V Power Supply for Transmitter Driver
GNDA E2, E3, E4, E19, E20, F3, F4, F19,
F20, M13, M21, T3, T4, T20, U3,
U4, U19, U20, V3, V20, V21
GNDA: GND for Analog Core / Receiver
GNDD C6, C7, C8, C9, C10, C11, C12,
C13, C14, C15, C16, C17, D10, E8,
E13, E15, F6, F7, F11, G7, G8, G9,
G10, G12, G13, G14, G15, G16,
G17, H7, H8, H9, H10, H11, H12,
H13, H14, H15, H16, H17, P9, P10,
P12, P15, R9, R13, R17, T10, T11,
T12, T13, T14, T17, U10, U11, U12,
U13, U14, U15, U16, U17, Y20
GNDD: Digital GND
GNDT J7, J8, J9, J10, J11, J12, J13, J14,
J15, K7, K10, K11, K12, K14, K16,
L8, L10, L11, L12, L14, L15, M8,
M11, M14, M15, N8, N9, N10, N11,
P7, P16
GNDT: Analog GND for Transmitter Driver
Name I / O Pin No. Description
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Pin Description 19 December 17, 2009
TEST
NC - A1, A2, A3, A4, A19, A20, A21,
A22, B1, B2, B3, B4, B19, B20,
B21, B22, C2, C3, C4, C19, C20,
C21, C22, D2, D3, D4, D19, D20,
D21, D22, E5, E21, F2, F9, F21,
G2, G18, G21, H2, H5, H18, H21,
J2, J21, K2, K21, L2, L18, L21, M2,
N2, N14, P2, P11, P14, P18, P21,
R2, R7, R8, R18, R21, T2, T5, T6,
T21, U2, U5, U6, U7, U18, U21, V2,
W2, W21, W22, Y4, Y5, Y6, Y7, Y8,
Y9, Y10, Y11, Y12, Y13, Y14, Y15,
Y16, Y17, Y18, Y19, Y21, Y22,
AA1, AA22, AB15, W14
NC: No Connected
These pins should be left open.
Others
IC W20 IC: Internal Connected
This pin is for IDT use only and should be connected to GNDD.
Name I / O Pin No. Description
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 20 December 17, 2009
3 FUNCTIONAL DESCRIPTION
3.1 T1 / E1 / J1 MODE SELECTION
The IDT82P20416 can be configured to T1/J1 mode or E1 mode
globally or on a per-channel basis. The configuration is determined by
the TEHWE pin, the TEHW pin and the T1E1 bit (b0, CHCF,...). Refer to
Table-1 for details of the operation mode selection.
3.2 RECEIVE PATH
3.2.1 RX TERMINATION
The receive line interface supports Receive Differential mode. In
Receive Differential mode, both RTIPn and RRINGn are used to receive
signal from the line side.
In Receive Differential mode, the line interface can be connected
with T1 100 Ω, J1 110 Ω or E1 120 Ω twisted pair cable or E1 75 Ω
coaxial cable.
The receive impedance matching is realized by using internal imped-
ance matching or external impedance matching for each channel in
different applications.
3.2.1.1 Receive Differential Mode
In Receive Differential mode, three kinds of impedance matching are
supported: Fully Internal Impedance Matching, Partially Internal Imped-
ance Matching and External Impedance Matching. Figure-3 shows an
overview of how these Impedance Matching modes are switched.
Fully Internal Impedance Matching circuit uses an internal program-
mable resistor (IM) only and does not use an external resistor. This
configuration saves external components and supports 1:1 Hitless
Protection Switching (HPS) applications without relays. Refer to
Section 4.4 Hitless Protection Switching (HPS) Summary.
Partially Internal Impedance Matching circuit consists of an internal
programmable resistor (IM) and a value-fixed 120 Ω external resistor
(Rr). Compared with Fully Internal Impedance Matching, this configura-
tion provides considerable savings in power dissipation of the device.
For example, In E1 120 Ω PRBS mode, the power savings would be
0.44 W. For power savings in other modes, please refer to Chapter 8
Physical And Electrical Specifications.
External Impedance Matching circuit uses an external resistor (Rr)
only.
Figure-3 Switch between Impedance Matching Modes
To support some particular applications, such as hot-swap or Hitless
Protection Switch (HPS) hot-switchover, RTIPn/RRINGn must be forced
to enter high impedance state (i.e., External Impedance Matching). For
hot-swap, RTIPn/RRINGn must be always held in high impedance state
during /after power up; for HPS hot-switchover, RTIPn/RRINGn must
enter high impedance state immediately after switchover. Though each
channel can be individually configured to External Impedance Matching
through register access, it is too slow for hitless switch. Therefore, a
hardware pin - RIM - is provided to globally control the high impedance
for all 16 receivers.
When RIM is low, only External Impedance Matching is supported for
all 16 receivers and the per-channel impedance matching configuration
bits - the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4,
RCF0,...) - are ignored.
Table-1 Operation Mode Selection
Global Programming Per-Channel Programming
TEHWE Pin Open Low
TEHW Pin Open Low (The configuration of this pin is ignored)
T1E1 Bit (The configuration of this bit is ignored). 0 1
Operation Mode T1/J1 E1 T1/J1 E1
IM
RTIP
RRING
RIN
R_TERM2
10
01
Receive
path
R_TERM[1:0]
RIM
R120IN
Rr = 120 Ω
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 21 December 17, 2009
When RIM is high, impedance matching is configured on a per-
channel basis. Three kinds of impedance matching are all supported
and selected by the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN
bit (b4, RCF0,...). The R_TERM[2] bit (b2, RCF0,...) should be set to
match internal or external impedance. If the R_TERM[2] bit (b2,
RCF0,...) is ‘0’, internal impedance matching is enabled. The R120IN bit
(b4, RCF0,...) should be set to select Partially Internal Impedance
Matching or Fully Internal Impedance Matching. The internal program-
mable resistor (IM) is determined by the R_TERM[1:0] bits (b1~0,
RCF0,...). If the R_TERM[2] bit (b2, RCF0,...) is ‘1’, external impedance
matching is enabled. The configuration of the R120IN bit (b4, RCF0,...)
and the R_TERM[1:0] bits (b1~0, RCF0,...) is ignored.
A twisted pair cable can be connected with a 1:1 transformer or
without a transformer (transformer-less), while a coaxial cable must be
connected with a 1:1 transformer. Table 2 lists the recommended imped-
ance matching value in different applications. Figure-4 to Figure-6 show
the connection for one channel.
The transformer-less connection will offer a termination option with
reduced cost and board space. However, the waveform amplitude is not
standard compliant, and surge protection and common mode depres-
sion should be enhanced depending on equipment environment.
Figure-4 Receive Differential Line Interface with Twist-
ed Pair Cable (with transformer) Figure-5 Receive Differential Line Interface with Coax-
ial Cable (with transformer)
Table-2 Impedance Matching Value in Receive Differential Mode
Cable Condition
Partially Internal Impedance Matching
(R120IN = 0) 1
Fully Internal Impedance Matching
(R120IN = 1) 1, 2 External Impedance Matching
R_TERM[2:0] Rr R_TERM[2:0] Rr R_TERM[2:0] 3Rr
T1 100 Ω twisted pair (with transformer) 000
120 Ω
000
(open)
1XX
100 Ω
J1 110 Ω twisted pair (with transformer) 001 001 110 Ω
E1 120 Ω twisted pair (with transformer) 010 010 120 Ω
E1 75 Ω coaxial (with transformer) 011 011 75 Ω
T1 100 Ω twisted pair (transformer-less4)000
(not supported)
100 Ω
J1 110 Ω twisted pair (transformer-less) 001 110 Ω
E1 120 Ω twisted pair (transformer-less) 010 120 Ω
Note:
1. Partially Internal Impedance Matching and Fully Internal Impedance Matching are not supported when RIM is low.
2. Fully Internal Impedance Matching is not supported in transformer-less applications.
3. When RIM is low, the setting of the R_TERM[2:0] bits is ignored.
4. In transformer-less applications, the device should be protected against overvoltage. There are three important standards for overvoltage protection:
• UL1950 and FCC Part 68;
• Telcordia (Bellcore) GR-1089
• ITU-T K.20, K.21 and K.41
1:1
Rr
RTIPn
RRINGn
IM
6.0 Vpp
1:1
Rr
RTIPn
RRINGn
IM
4.74 Vpp
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 22 December 17, 2009
Figure-6 Receive Differential Line Interface with Twist-
ed Pair Cable (transformer-less, non standard compli-
ant)
3.2.2 EQUALIZER
The equalizer compensates high frequency attenuation to enhance
receive sensitivity.
3.2.2.1 Line Monitor
In both T1/J1 and E1 short haul applications, the Protected Non-
Intrusive Monitoring per T1.102 can be performed between two devices.
The monitored channel of one device is in normal operation, and the
monitoring channel of the other device taps the monitored one through a
high impedance bridging circuit (refer to Figure-7 and Figure-8).
After the high resistance bridging circuit, the signal arriving at RTIPn/
RRINGn of the monitoring channel is dramatically attenuated. To
compensate this bridge resistive attenuation, Monitor Gain can be used
to boost the signal by 20 dB, 26 dB or 32 dB, as selected by the MG[1:0]
bits (b1~0, RCF2,...). For normal operation, the Monitor Gain should be
set to 0 dB, i.e., the Monitor Gain of the monitored channel should be 0
dB.
The monitoring channel can be configured to any of the External,
Partially Internal or Fully Internal Impedance Matching mode. Here the
external r or internal IM is used for voltage division, not for impedance
matching. That is, the r (IM) and the two R make up of a resistance
bridge. The resistive attenuation of this bridge is 20lg(r/(2R+r)) dB.
Note that line monitor is only available in differential line interface.
3.2.2.2 Receive Sensitivity
The receive sensitivity is the minimum range of receive signal level
for which the receiver recovers data error-free with -18 dB interference
signal added.
For Receive Differential line interface, the receive sensitivity is -15
dB.
For Receive Single Ended line interface, the receive sensitivity is -12
dB.
Figure-7 Receive Path Monitoring
Figure-8 Transmit Path Monitoring
IM
6.0Vpp
RTIPn
RRINGn
Rr/2
Rr/2
VCOM1
10 µF
1. Two Rr/2 resistors should be connected to VCOM[1:0] that are
coupled to ground via a 10 µF capacitor, which provide 60 Ω
common mode input resistance.
2. In this mode, lightning protection should be enhanced.
3. The maximum input dynamic range of RTIP/TRING pin is
-0.3 V ~3.6 V (in line monitor mode it is -0.3 V ~ 2 V)
Note:
VCOM0
RTIPn
RRINGn
RTIPn
RRINGn
monitored channel
monitoring channel
DSX cross
connect point
R
monitor gain
= 20/26/32 dB
monitor gain
= 0 dB
R
r
TTIPn
TRINGn
RTIPn
RRINGn
monitored channel
monitoring channel
DSX cross
connect point
R
monitor gain
= 20/26/32 dB
monitor gain
= 0 dB
R
r
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 23 December 17, 2009
3.2.3 SLICER
The Slicer is used to generate a standard amplitude mark or a space
according to the amplitude of the input signals. The input signal is sliced
at 50% of the peak value.
3.2.4 RX CLOCK & DATA RECOVERY
The Rx Clock & Data Recovery is used to recover the clock signal
from the received data. It is accomplished by an integrated Digital Phase
Locked Loop (DPLL). The recovered clock tracks the jitter in the data
output from the Slicer and keeps the phase relationship between data
and clock during the absence of the incoming pulse.
3.2.5 DECODER
The Decoder is used only when the receive system interface is in
Single Rail NRZ Format mode. When the receive system interface is in
other modes, the Decoder is bypassed automatically. (Refer to
Section 3.2.6 Receive System Interface for the description of the receive
system interface).
In T1/J1 mode, the received signal is decoded by AMI or B8ZS line
code rule. In E1 mode, the received signal is decoded by AMI or HDB3
line code rule. The line code rule is selected by the R_CODE bit (b2,
RCF1,...).
3.2.6 RECEIVE SYSTEM INTERFACE
The received data can be output to the system side in four modes:
Single Rail NRZ Format mode, Dual Rail NRZ Format mode, Dual Rail
RZ Format mode and Dual Rail Sliced mode, as selected by the
R_MD[1:0] bits (b1~0, RCF1).
If data is output on RDn in NRZ format and the recovered clock is
output on RCLKn, the receive system interface is in Single Rail NRZ
Format mode. In this mode, the data is decoded and updated on the
active edge of RCLKn. RCLKn outputs a 1.544 MHz (in T1/J1 mode) or
2.048 MHz (in E1 mode) clock.
If data is output on RDPn and RDNn in NRZ format and the recov-
ered clock is output on RCLKn, the receive system interface is in Dual
Rail NRZ Format mode. In this mode, the data is un-decoded and
updated on the active edge of RCLKn. RCLKn outputs a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) clock.
If data is output on RDPn and RDNn in RZ format and the recovered
clock is output on RCLKn, the receive system interface is in Dual Rail
RZ Format mode. In this mode, the data is un-decoded and updated on
the active edge of RCLKn. RCLKn outputs a 1.544 MHz (in T1/J1 mode)
or 2.048 MHz (in E1 mode) clock.
If data is output on RDPn and RDNn in RZ format directly after
passing through the Slicer, the receive system interface is in Dual Rail
Sliced mode. In this mode, the data is raw sliced and un-decoded.
Table-3 summarizes the multiplex pin used in different receive
system interface.
Table-3 Multiplex Pin Used in Receive System Interface
Receive System
Interface
Multiplex Pin Used On Receive System
Interface
RDn / RDPn RDNn RCLKn
Single Rail NRZ Format RDn 1RCLKn 2
Dual Rail NRZ Format RDPn 1RDNn 1RCLKn 2
Dual Rail RZ Format RDPn 1RDNn 1RCLKn 2
Dual Rail Sliced RDPn 1RDNn 1
Note:
1. The active level on RDn, RDPn and RDNn is selected by the RD_INV bit (b3,
RCF1,...).
2. The active edge of RCLKn is selected by the RCK_ES bit (b4, RCF1,...).
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 24 December 17, 2009
3.2.7 RECEIVER POWER DOWN
Set the R_OFF bit (b5, RCF0,...) to ‘1’ will power down the corre-
sponding receiver.
In this way, the corresponding receive circuit is turned off and the
RTIPn/RRINGn pins are forced to High-Z state. The pins on receive
system interface (including RDn/RDPn, RDNn, RCLKn) will be in High-Z
state if the RHZ bit (b6, RCF0,...) is ‘1’ or in low level if the RHZ bit (b6,
RCF0,...) is ‘0’.
After clearing the R_OFF bit (b5, RCF0,...), it will take 1 ms for the
receiver to achieve steady state, i.e., to return to the previous configura-
tion and performance.
3.3 TRANSMIT PATH
3.3.1 TRANSMIT SYSTEM INTERFACE
The data from the system side is input to the device in three modes:
Single Rail NRZ Format mode, Dual Rail NRZ Format mode and Dual
Rail RZ Format mode, as selected by the T_MD[1:0] bits (b1~0,
TCF1,...).
If data is input on TDn in NRZ format and a 1.544 MHz (in T1/J1
mode) or 2.048 MHz (in E1 mode) clock is input on TCLKn, the transmit
system interface is in Single Rail NRZ Format mode. In this mode, the
data is encoded and sampled on the active edge of TCLKn.
If data is input on TDPn and TDNn in NRZ format and a 1.544 MHz
(in T1/J1 mode) or 2.048 MHz (in E1 mode) clock is input on TCLKn, the
transmit system interface is in Dual Rail NRZ Format mode. In this
mode, the data is pre-encoded and sampled on the active edge of
TCLKn.
If data is input on TDPn and TDNn in RZ format and no transmit
clock is input, the transmit system interface is in Dual Rail RZ Format
mode. In this mode, the data is pre-encoded.
Table-4 summarizes the multiplex pin used in different transmit
system interface.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 25 December 17, 2009
3.3.2 TX CLOCK RECOVERY
The Tx Clock Recovery is used only when the transmit system inter-
face is in Dual Rail RZ Format mode. When the transmit system inter-
face is in other modes, the Tx Clock Recovery is bypassed
automatically.
The Tx Clock Recovery is used to recover the clock signal from the
data input on TDPn and TDNn.
3.3.3 ENCODER
The Encoder is used only when the transmit system interface is in
Single Rail NRZ Format mode. When the transmit system interface is in
other modes, the Encoder is bypassed automatically.
In T1/J1 mode, the data to be transmitted is encoded by AMI or
B8ZS line code rule. In E1 mode, the data to be transmitted is encoded
by AMI or HDB3 line code rule. The line code rule is selected by the
T_CODE bit (b2, TCF1,...).
3.3.4 WAVEFORM SHAPER
The IDT82P20416 provides two ways to manipulate the pulse shape
before data is transmitted:
• Preset Waveform Template;
• User-Programmable Arbitrary Waveform.
3.3.4.1 Preset Waveform Template
In T1/J1 applications, the waveform template meets T1.102. The T1
template is shown in Figure-9. It is measured in the far end, as shown in
Figure-10. The J1 template is measured in the near end line side.
In T1 applications, to meet the template, five preset waveform
templates are provided according to five grades of cable length. The
selection is made by the PULS[3:0] bits (b3~0, PULS,...). In J1 applica-
tions, the PULS[3:0] bits (b3~0, PULS,...) should be set to ‘0111’. Refer
to Table-5 for details.
Figure-9 DSX-1 Waveform Template
Figure-10 T1 Waveform Template Measurement Circuit
Table-4 Multiplex Pin Used in Transmit System Interface
Transmit System
Interface
Multiplex Pin Used On Transmit System
Interface
TDn / TDPn TDNn TCLKn / TDNn
Single Rail NRZ Format TDn 1TCLKn 2
Dual Rail NRZ Format TDPn 1TDNn 1TCLKn 2
Dual Rail RZ Format TDPn 1TDNn 1
Note:
1. The active level on TDn, TDPn and TDNn is selected by the TD_INV bit (b3,
TCF1,...).
2. The active edge of TCLKn is selected by the TCK_ES bit (b4, TCF1,...). If TCLKn is
missing, i.e., no transition for more than 64 T1/E1 clock cycles, the TCKLOS_S bit (b3,
STAT0,...) will be set. A transition from ‘0’ to ‘1’ on the TCKLOS_S bit (b3, STAT0,...) or
any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TCKLOS_S bit (b3, STAT0,...) will
set the TCKLOS_IS bit (b3, INTS0,...) to ‘1’, as selected by the TCKLOS_IES bit (b3,
INTES,...). When the TCKLOS_IS bit (b3, INTS0,...) is ‘1’, an interrupt will be reported
by INT if not masked by the TCKLOS_IM bit (b3, INTM0,...).
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0 250 500 750 1000 1250
Time (ns)
Normalized Amplitude
IDT82P20416
TTIPn
TRINGn
Cable
RLOAD VOUT
Note: RLOAD = 100 Ω + 5%
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 26 December 17, 2009
In E1 applications, the waveform template meets G.703, as shown in
Figure-11. It is measured in the near end line side, as shown in Figure-
12.
In E1 applications, the PULS[3:0] should be set to ‘0000’ if differential
signals (output from TTIP and TRING) are coupled to a 75 Ω coaxial
cable using Internal Impedance matching mode; the PULS[3:0] should
be set to ‘0001’ for other E1 interfaces. Refer to Table-6 for details.
Figure-11 E1 Waveform Template
Figure-12 E1 Waveform Template Measurement Circuit
After one of the preset waveform templates is selected, the preset
waveform amplitude can be adjusted to get the desired waveform.
In T1 mode, the standard value of the SCAL[5:0] bits (b5~0,
SCAL,...) is ‘110110’ which is also the default value. The adjusting is
made by increasing or decreasing by ‘1’ from the standard value to scale
up or down at a percentage ratio of 2% against the preset waveform
amplitude.
In E1 mode, the SCAL[5:0] bits (b5~0, SCAL,...) should be set to
‘100001’ to get the standard amplitude. The adjusting is made by
increasing or decreasing by ‘1’ from the standard value to scale up or
down at a percentage ratio of 3%.
In summary, do the following step by step, the desired waveform will
be got based on the preset waveform template:
• Select one preset waveform template by setting the PULS[3:0] bits
(b3~0, PULS,...);
• Write ‘100001 to the SCAL[5:0] bits (b5~0, SCAL,...) if E1 mode is
selected.
• Write the scaling value to the SCAL[5:0] bits (b5~0, SCAL,...) to
scale the amplitude of the selected preset waveform template (-
this step is optional).
Table-5 PULS[3:0] Setting in T1/J1 Mode
Cable Conditions PULS[3:0]
DSX1 - 0 ~ 133 ft 0010
DSX1 - 133 ~ 266 ft 0011
DSX1 - 266 ~ 399 ft 0100
DSX1 - 399 ~ 533 ft 0101
DSX1 - 533 ~ 655 ft 0110
J1 - 0 ~ 655 ft 0111
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
Normalized Amplitude
Time in Unit Intervals
Table-6 PULS[3:0] Setting in E1 Mode
Interface Conditions PULS[3:0]
E1 75 Ω differential interface,
Internal Impedance matching mode
0000
Other E1 interface 0001
IDT82P20416 VOUT
RLOAD
TTIPn
TRINGn
Note: RLOAD = 75 Ω or 120 Ω (+ 5%)
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 27 December 17, 2009
3.3.4.2 User-Programmable Arbitrary Waveform
When the PULS[3:0] bits (b3~0, PULS,...) are set to ‘1XXX’, user-
programmable arbitrary waveform will be used in the corresponding
channel.
Each waveform shape can extend up to UIs (Unit Interval), and is
divided into 20 sub-phases that are addressed by the SAMP[4:0] bits
(b4~0, AWG0,...). The waveform amplitude of each phase is repre-
sented by a binary byte, within the range from +63 to -63, stored in the
WDAT[6:0] bits (b6~0, AWG1,...) in signed magnitude form. The
maximum number +63 (D) represents the maximum positive amplitude
of the transmit pulse while the most negative number -63 (D) represents
the maximum negative amplitude of the transmit pulse. Therefore, up to
20 bytes are used.
There are eight standard templates which are stored in a local ROM.
One of them can be selected as reference and made some changes to
get the desired waveform.
To do this, the first step is to choose a set of waveform value from the
standard templates. The selected waveform value should be the most
similar to the desired waveform shape. Table 7 to Table 14 list the
sample data of each template.
Then modify the sample data to get the desired transmit waveform
shape. By increasing or decreasing by ‘1’ from the standard value in the
SCAL[5:0] bits (b5~0, SCAL,...), the waveform amplitude will be scaled
up or down.
In summary, do the following for the write operation:
• Modify the sample data in the AWG1 register;
• Write the AWG0 register to implement the write operation, includ-
ing:
- Write the sample address to the SAMP[4:0] bits (b4~0,
AWG0,...);
- Write ‘0’ to the RW bit (b5, AWG0,...);
- Write ‘1’ to the DONE bit (b6, AWG0,...).
Do the following for the read operation:
• Write the AWG0 register, including:
- Write sample address to the SAMP[4:0] bits (b4~0, AWG0,...);
- Write ‘1’ to the RW bit (b5, AWG0,...);
- Write ‘1’ to the DONE bit (b6, AWG0,...);
• Read the AWG1 register to get the sample data.
When the write operation is completed, write the scaling value to the
SCAL[5:0] bits (b5~0, SCAL,...) to scale the amplitude of the selected
standard waveform (- this step is optional).
When more than one UI is used to compose the waveform template
and the waveform amplitude is not set properly, the overlap of the two
consecutive waveforms will make the waveform amplitude overflow (i.e.,
exceed the maximum limitation). This overflow is captured by the
DAC_IS bit (b7, INTS0,...) and will be reported by the INT pin if enabled
by the DAC_IM bit (b7, INTM0,...).
Refer to application note AN-513 ‘User-Programmable Arbitrary
Waveform for DSX1’ for more details.
11
4
---
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 28 December 17, 2009
Table-7 Transmit Waveform Value for T1 0 ~ 133 ft
SAMP[4:0] 1234567891011121314151617181920
WDAT[6:0] 17H 27H 27H 26H 25H 25H 25H 24H 23H 4AH 4AH 49H 47H 45H 44H 43H 42H 41H 00H 00H
Table-8 Transmit Waveform Value for T1 133 ~ 266 ft
SAMP[4:0] 1234567891011121314151617181920
WDAT[6:0] 1BH 2EH 2CH 2AH 29H 28H 27H 26H 25H 50H 4FH 4DH 4AH 48H 46H 44H 43H 42H 41H 00H
Table-9 Transmit Waveform Value for T1 266 ~ 399 ft
SAMP[4:0] 1234567891011121314151617181920
WDAT[6:0] 1FH 34H 2FH 2CH 2BH 2AH 29H 28H 25H 57H 53H 50H 4BH 48H 46H 44H 43H 42H 41H 00H
Table-10 Transmit Waveform Value for T1 399 ~ 533 ft
SAMP[4:0] 1234567891011121314151617181920
WDAT[6:0] 20H 3BH 35H 2FH 2EH 2DH 2CH 2AH 28H 58H 58H 53H 4CH 48H 46H 44H 43H 42H 41H 00H
Table-11 Transmit Waveform Value for T1 533 ~ 655 ft
SAMP[4:0] 1234567891011121314151617181920
WDAT[6:0] 20H 3FH 38H 33H 2FH 2EH 2DH 2CH 29H 5FH 5EH 57H 4FH 49H 47H 44H 43H 42H 41H 00H
Table-12 Transmit Waveform Value for E1 75 ohm
SAMP[4:0] 1234567891011121314151617181920
WDAT[6:0] 00H 00H 00H 0CH 30H 30H 30H 30H 30H 30H 30H 30H 00H 00H 00H 00H 00H 00H 00H 00H
Table-13 Transmit Waveform Value for E1 120 ohm
SAMP[4:0] 1234567891011121314151617181920
WDAT[6:0] 00H 00H 00H 0FH 3CH 3CH 3CH 3CH 3CH 3CH 3CH 3CH 00H 00H 00H 00H 00H 00H 00H 00H
Table-14 Transmit Waveform Value for J1 0 ~ 655 ft
SAMP[4:0] 1234567891011121314151617181920
WDAT[6:0] 17H 27H 27H 26H 25H 25H 25H 24H 23H 4AH 4AH 49H 47H 45H 44H 43H 42H 41H 00H 00H
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 29 December 17, 2009
3.3.5 LINE DRIVER
The Line Driver can be set to High-Z for protection or in redundant
applications.
The following two ways will set the Line Driver to High-Z:
• Setting the OE pin to low will globally set all the Line Drivers to
High-Z;
• Setting the OE bit (b6, TCF0,...) to ‘0’ will set the corresponding
Line Driver to High-Z.
By these ways, the functionality of the internal circuit is not affected
and TTIPn and TRINGn will enter High-Z state immediately.
3.3.5.1 Transmit Over Current Protection
The Line Driver monitors the Transmit Over Current (TOC) on the
line interface. When TOC is detected, the driver’s output (i.e., output on
TTIPn/TRINGn) is determined by the THZ_OC bit (b4, TCF0,...). If the
THZ_OC bit (b4, TCF0,...) is ‘0’, the driver’s output current (peak to
peak) is limited to 100 mA; if the THZ_OC bit (b4, TCF0,...) is ‘1’, the
driver’s output will enter High-Z. TOC is indicated by the TOC_S bit (b4,
STAT0,...). A transition from ‘0’ to ‘1’ on the TOC_S bit (b4, STAT0,...) or
any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TOC_S bit (b4,
STAT0,...) will set the TOC_IS bit (b4, INTS0,...) to ‘1’, as selected by the
TOC_IES bit (b4, INTES,...). When the TOC_IS bit (b4, INTS0,...) is ‘1’,
an interrupt will be reported by INT if not masked by the TOC_IM bit (b4,
INTM0,...).
3.3.6 TX TERMINATION
The transmit line interface supports Transmit Differential mode and
Transmit Single Ended mode, as selected by the T_SING bit (b3,
TCF0,...). In Transmit Differential mode, both TTIPn and TRINGn are
used to transmit signals to the line side. In Transmit Single Ended mode,
only TTIPn is used to transmit signal.
The line interface can be connected with T1 100 Ω, J1 110 Ω or E1
120 Ω twisted pair cable or E1 75 Ω coaxial cable.
The transmit impedance matching is realized by using internal
impedance matching or external impedance matching for each channel
in different applications.
3.3.6.1 Transmit Differential Mode
In Transmit Differential mode, different applications have different
impedance matching. For T1/J1 applications, only Internal Impedance
Matching is supported. For E1 applications, both Internal and External
Impedance Matching are supported.
Internal Impedance Matching circuit uses an internal programmable
resistor (IM) only.
External Impedance Matching circuit uses an external resistor (Rt)
only.
A twisted pair cable can be connected with a 1:2 (step up) trans-
former or without a transformer (transformer-less), while a coaxial cable
must be connected with a 1:2 transformer.
The T_TERM[2:0] bits (b2~0, TCF0,...) should be set according to
different cable conditions, whether a transformer is used, and what kind
of Impedance Matching is selected.
Table-15 lists the recommended impedance matching value in
different applications. Figure-13 to Figure-15 show the connection for
one channel in different applications.
The transformer-less connection will offer a termination option with
reduced cost and board space. However, the waveform amplitude is not
standard compliant, and surge protection and common mode depres-
sion should be enhanced depending on equipment environment..
Table-15 Impedance Matching Value in Transmit Differential Mode
Cable Condition
Internal Impedance Matching External Impedance Matching
T_TERM[2:0] Rt PULS[3:0] T_TERM[2:0] Rt PULS[3:0]
T1 100 Ω twisted pair (with transformer) 000
0
Table-5
(not supported)
J1 110 Ω twisted pair (with transformer) 001 0111
E1 120 Ω twisted pair (with transformer) 010 0001 111 10 Ω0000
E1 75 Ω coaxial (with transformer) 011 0000 0000
T1 100 Ω twisted pair (transformer-less) 100 Table-5
(not supported)J1 110 Ω twisted pair (transformer-less) 101 0111
E1 120 Ω twisted pair (transformer-less) 110 0001
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 30 December 17, 2009
Figure-13 Transmit Differential Line Interface with
Twisted Pair Cable (with Transformer) Figure-14 Transmit Differential Line Interface with Co-
axial Cable (with transformer)
Figure-15 Transmit Differential Line Interface with
Twisted Pair Cable (transformer-less, non standard
compliant)
1:2
Rt
TTIPn
TRINGn
IM 6.0 Vpp
Rt
1:2
Rt
TTIPn
TRINGn
IM 4.74 Vpp
Rt
TTIPn
TRINGn
IM 3.0Vpp
In this mode, port protection
should be enhanced.
Note:
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 31 December 17, 2009
3.3.7 TRANSMITTER POWER DOWN
Set the T_OFF bit (b5, TCF0,...) to ‘1’ will power down the corre-
sponding transmitter.
In this way, the corresponding transmit circuit is turned off. The pins
on the transmit line interface (including TTIPn and TRINGn) will be in
High-Z state. The input on the transmit system interface (including TDn,
TDPn, TDNn and TCLK) is ignored. The output on the transmit system
interface will be in High-Z state.
After clearing the T_OFF bit (b5, TCF0,...), it will take 1 ms for the
transmitter to achieve steady state, i.e., return to the previous configura-
tion and performance.
3.3.8 OUTPUT HIGH-Z ON TTIP AND TRING
TTIPn and TRINGn can be set to High-Z state globally or on a per-
channel basis.
The following three conditions will set TTIPn and TRINGn to High-Z
state globally:
• Connecting the OE pin to low;
• Loss of MCLK (i.e., no transition on MCLK for more than 1 ms);
• Power on reset, hardware reset by pulling RST to low for more
than 2 µs or global software reset by writing the RST register.
The following six conditions will set TTIPn and TRINGn to High-Z
state on a per-channel basis:
• Writing ‘0’ to the OE bit (b6, TCF0,...);
• Loss of TCLKn in Transmit Single Rail NRZ Format mode or
Transmit Dual Rail NRZ Format mode (i.e., no transition on TCLKn
for more than 64 XCLK1 cycles) except that the channel is in
Remote Loopback or transmit internal pattern with XCLK;
• Transmitter power down;
• Per-channel software reset by writing ‘1’ to the CHRST bit (b1,
CHCF,...);
• Setting the THZ_OC bit (b4, TCF0,...) to ‘1’ when transmit driver
over-current is detected.
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
in E1 mode.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 32 December 17, 2009
3.4 JITTER ATTENUATOR (RJA & TJA)
Two Jitter Attenuators are provided for each channel of receiver and
transmitter. Each Jitter Attenuator can be enabled or disabled, as deter-
mined by the RJA_EN/TJA_EN bit (b3, RJA/TJA,...) respectively.
Each Jitter Attenuator consists of a FIFO and a DPLL, as shown in
Figure-16.
Figure-16 Jitter Attenuator
The FIFO is used as a pool to buffer the jittered input data, then the
data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the RJA_DP[1:0]/
TJA_DP[1:0] bits (b2~1, RJA/TJA,...). Accordingly, the typical delay
produced by the Jitter Attenuator is 16 bits, 32 bits or 64 bits. The 128-
bit FIFO is used when large jitter tolerance is expected, while the 32-bit
FIFO is used in delay sensitive applications.
The DPLL is used to generate a de-jittered clock to clock out the data
stored in the FIFO. The DPLL can only attenuate the incoming jitter
whose frequency is above Corner Frequency (CF) by 20 dB per decade
falling off. The jitter whose frequency is lower than the CF passes
through the DPLL without any attenuation. In T1/J1 applications, the CF
of the DPLL is 5 Hz or 1.26 Hz. In E1 applications, the CF of the DPLL is
6.77 Hz or 0.87 Hz. The CF is selected by the RJA_BW/TJA_BW bit (b0,
RJA/TJA,...). The lower the CF is, the longer time is needed to achieve
synchronization.
If the incoming data moves faster than the outgoing data, the FIFO
will overflow. If the incoming data moves slower than the outgoing data,
the FIFO will underflow. The overflow and underflow are both captured
by the RJA_IS/TJA_IS bit (b5/6, INTS0,...). The occurrence of overflow
or underflow will be reported by the INT pin if enabled by the RJA_IM/
TJA_IM bit (b5/6, INTM0,...).
To avoid overflow or underflow, the JA-Limit function can be enabled
by setting the RJA_LIMT/TJA_LIMT bit (b4, RJA/TJA,...). When the JA-
Limit function is enabled, the speed of the outgoing data will be adjusted
automatically if the FIFO is 2-bit close to its full or emptiness. Though
the JA-Limit function can reduce the possibility of FIFO overflow and
underflow, the quality of jitter attenuation is deteriorated.
The performance of the Jitter Attenuator meets ITUT I.431, G.703,
G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/13, AT&T
TR62411, TR43802, TR-TSY 009, TR-TSY 253 and TR-TRY 499. Refer
to Section 8.12 Jitter Attenuation Characteristics for the jitter perfor-
mance.
FIFO
32/64/128
DPLL
Jittered Data De-jittered Data
Jittered Clock De-jittered Clock
write
clock
read
clock
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 33 December 17, 2009
3.5 DIAGNOSTIC FACILITIES
The diagnostic facilities include:
• BPV (Bipolar Violation) / CV (Code Violation) detection and BPV
insertion;
• EXZ (Excessive Zero) detection;
• LOS (Loss Of Signal) detection;
• AIS (Alarm Indication Signal) detection and generation;
• Pattern generation and detection, including PRBS (Pseudo Ran-
dom Bit Sequence), ARB (Arbitrary Pattern) and IB (Inband Loop-
back).
The above defects, alarms or patterns can be counted by an internal
Error Counter, indicated by the respective interrupt bit.
3.5.1 BIPOLAR VIOLATION (BPV) / CODE VIOLATION (CV)
DETECTION AND BPV INSERTION
3.5.1.1 Bipolar Violation (BPV) / Code Violation (CV) Detection
BPV/CV is monitored in both the receive path and the transmit path.
BPV is detected when the data is AMI coded and CV is detected when
the data is B8ZS/HDB3 coded. If the transmit system interface is in
Transmit Single Rail NRZ Format mode, the BPV/CV detection is
disabled in the transmit path automatically.
A BPV is detected when two consecutive pulses of the same polarity
are received.
A CV is detected when two consecutive BPVs of the same polarity
that are not a part of the B8ZS/HDB3 zero substitution are received.
When BPV/CV is detected in the receive path, the Line Bipolar Viola-
tion LBPV_IS bit (b4, INTS2,...) will be set and an interrupt will be
reported by INT if not masked by the LBPV_IM bit (b4, INTM2,...).
When BPV/CV is detected in the transmit path, the System Bipolar
Violation SBPV_IS bit (b5, INTS2,...) will be set and an interrupt will be
reported by INT if not masked by the SBPV_IM bit (b5, INTM2,...).
3.5.1.2 Bipolar Violation (BPV) Insertion
The BPV can only be inserted in the transmit path.
A BPV will be inserted on the next available mark in the data stream
to be transmitted by writing a ‘1’ to the BPV_INS bit (b6, ERR,...). This
bit will be reset once BPV insertion is done.
3.5.2 EXCESSIVE ZEROES (EXZ) DETECTION
EXZ is monitored in both the receive path and the transmit path.
Different line code has different definition of the EXZ. The
IDT82P20416 provides two standards of EXZ definition for each kind of
line code rule. The standards are ANSI and FCC, as selected by the
EXZ_DEF bit (b7, ERR,...). Refer to Table-16 for details.
When EXZ is detected in the receive path, the LEXZ_IS bit (b2,
INTS2,...) will be set and an interrupt will be reported by INT if not
masked by the LEXZ_IM bit (b2, INTM2,...).
When EXZ is detected in the transmit path, the SEXZ_IS bit (b3,
INTS2,...) will be set and an interrupt will be reported by INT if not
masked by the SEXZ_IM bit (b3, INTM2,...).
EXZ may be counted by an internal Error Counte. Refer to
Chapter 3.5.6 Error Counter.
Table-16 EXZ Definition
Line Code
Rule
Definition
ANSI (EXZ_DEF = 0) FCC (EXZ_DEF = 1)
AMI An EXZ is detected when
any string of more than 15
consecutive ‘0’s are
received.
T1/J1 - An EXZ is detected
when any string of more
than 80 consecutive ‘0’s are
received.
E1 - An EXZ is detected
when any string of more
than 15 consecutive ‘0’s are
received.
B8ZS An EXZ is detected when
any string of more than 7
consecutive ‘0’s are
received.
An EXZ is detected when
any string of more than 7
consecutive ‘0’s are
received.
HDB3 An EXZ is detected when
any string of more than 3
consecutive ‘0’s are
received.
An EXZ is detected when
any string of more than 3
consecutive ‘0’s are
received.
Note:
If the transmit system interface is in Transmit Single Rail NRZ Format mode, the EXZ is
detected according to the standard of AMI.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 34 December 17, 2009
3.5.3 LOSS OF SIGNAL (LOS) DETECTION
The IDT82P20416 detects three kinds of LOS:
• LLOS: Line LOS, detected in the receive path;
• SLOS: System LOS, detected in the transmit system side;
• TLOS: Transmit LOS, detected in the transmit line side.
3.5.3.1 Line LOS (LLOS)
The amplitude and density of the data received from the line side are
monitored. When the amplitude of the data is less than Q Vpp for N
consecutive pulse intervals, LLOS is declared. When the amplitude of
the data is more than P Vpp and the average density of marks is at least
12.5% for M consecutive pulse intervals starting with a mark, LLOS is
cleared. Here Q is defined by the ALOS[2:0] bits (b6~4, LOS,...). P is the
sum of Q and 250 mVpp. N and M are defined by the LAC bit (b7,
LOS,...). Refer to Table-17 for details.
In T1/J1 mode, LLOS detection supports ANSI T1.231 and I.431. In
E1 mode, LLOS detection supports G.775 and ETSI 300233/I.431. The
criteria are selected by the LAC bit (b7, LOS,...).
When LLOS is detected, the LLOS_S bit (b0, STAT0,...) will be set. A
transition from ‘0’ to ‘1’ on the LLOS_S bit (b0, STAT0,...) or any transi-
tion (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LLOS_S bit (b0, STAT0,...) will
set the LLOS_IS bit (b0, INTS0,...) to ‘1’, as selected by the LOS_IES bit
(b1, INTES,...). When the LLOS_IS bit (b0, INTS0,...) is ‘1’, an interrupt
will be reported by INT if not masked by the LLOS_IM bit (b0, INTM0,...).
Two pins (LLOS0 and LLOS) are dedicated to LLOS indication.
Whether LLOS is detected in channel 0 or not, LLOS0 is high for a
CLKE1 clock cycle to indicate the start position on LLOS. LLOS indi-
cates LLOS status of all 16 channels in a serial format and repeats every
17 cycles. Refer to Figure-17. LLOS0 and LLOS are updated on the
rising edge of CLKE1. When the clock output on CLKE1 is disabled,
LLOS0 and LLOS will be held in High-Z state. The output on CLKE1 is
controlled by the CLKE1_EN bit (b3, CLKG) and the CLKE1 bit (b2,
CLKG). Refer to section 8.11 on page 110 for CLKE1 timing characteris-
tics.
LLOS may be counted by an internal Error Counte. Refer to
Section 3.5.6 Error Counter.
During LLOS, in Receive Single Rail NRZ Format mode, Receive
Dual Rail NRZ Format mode and Receive Dual Rail RZ Format mode,
RDPn/RDNn output low level. In Receive Dual Rail Sliced mode RDPn/
RDNn still output sliced data. RCLKn (if available) outputs high level or
XCLK1, as selected by the RCKH bit (b7, RCF0,...).
During LLOS, if any of AIS, pattern generation in the receive path or
Digital Loopback is enabled or automatic digital loopback happens,
RDPn/RDNn and RCLKn output corresponding data and clock, and the
setting of the RCKH bit (b7, RCF0,...) is ignored. Refer to the corre-
sponding chapters for details.
Figure-17 LLOS Indication on Pins
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
in E1 mode.
Table-17 LLOS Criteria
Operation
Mode LAC Criteria LLOS Declaring LLOS Clearing
T1/J1
0 ANSI T1.231 below Q Vpp, N = 175 bits above P Vpp, 12.5% mark density with less than 100 consecutive zeros, M = 175 bits
1 ANSI I.431 below Q Vpp, N = 1544 bits above P Vpp, 12.5% mark density with less than 100 consecutive zeros, M = 175 bits
E1
0 G.775 below Q Vpp, N = 32 bits above P Vpp, 12.5% mark density with less than 16 consecutive zeros, M = 32 bits
1 ETSI 300233/
I.431
below Q Vpp, N = 2048 bits above P Vpp, 12.5% mark density with less than 16 consecutive zeros, M = 32 bits
One LLOS Indication Cycle
LLOS
LLOS0
CLKE1
CH0 CH1 CH14 CH15
012314150
CH0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 35 December 17, 2009
3.5.3.2 System LOS (SLOS)
SLOS can only be detected when the transmit system interface is in
Dual Rail NRZ Format mode or in Dual Rail RZ Format mode.
The amplitude and density of the data input from the transmit system
side are monitored. When the input ‘0’s are equal to or more than N
consecutive pulse intervals, SLOS is declared. When the average
density of marks is at least 12.5% for M consecutive pulse intervals
starting with a mark, SLOS is cleared. Here N and M are defined by the
LAC bit (b7, LOS,...). Refer to Table-18 for details.
In T1/J1 mode, SLOS detection supports ANSI T1.231 and I.431. In
E1 mode, SLOS detection supports G.775 and ETSI 300233/I.431. The
criteria are selected by the LAC bit (b7, LOS,...).
When SLOS is detected, the SLOS_S bit (b1, STAT0,...) will be set. A
transition from ‘0’ to ‘1’ on the SLOS_S bit (b1, STAT0,...) or any transi-
tion (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the SLOS_S bit (b1, STAT0,...) will
set the SLOS_IS bit (b1, INTS0,...) to ‘1’, as selected by the LOS_IES bit
(b1, INTES,...). When the SLOS_IS bit (b1, INTS0,...) is ‘1’, an interrupt
will be reported by INT if not masked by the SLOS_IM bit (b1, INTM0,...).
SLOS may be counted by an internal Error Counter. Refer to
Section 3.5.6 Error Counter.
Table-18 SLOS Criteria
Operation
Mode LAC Criteria SLOS Declaring 1SLOS Clearing 1
T1/J1
0 ANSI T1.231 no pulse detected for N consecutive pulse intervals,
N = 175 bits
12.5% mark density with less than 100 consecutive
zeros for M consecutive pulse intervals,
M = 175 bits
1 ANSI I.431 no pulse detected for N consecutive pulse intervals,
N = 1544 bits
12.5% mark density with less than 100 consecutive
zeros for M consecutive pulse intervals,
M = 175 bits
E1
0 G.775 no pulse detected for N consecutive pulse intervals,
N = 32 bits
12.5% mark density with less than 16 consecutive
zeros for M consecutive pulse intervals,
M = 32 bits
1 ETSI 300233/
I.431
no pulse detected for N consecutive pulse intervals,
N = 2048 bits
12.5% mark density with less than 16 consecutive
zeros for M consecutive pulse intervals,
M = 32 bits
Note:
1. System input ports are schmitt-trigger inputs)
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 36 December 17, 2009
3.5.3.3 Transmit LOS (TLOS)
The amplitude and density of the data output on the transmit line side
are monitored. When the amplitude of the data is less than a certain
voltage for a certain period, TLOS is declared. The voltage is defined by
the TALOS[1:0] bits (b3~2, LOS,...). The period is defined by the
TDLOS[1:0] bits (b1~0, LOS,...). When a valid pulse is detected, i.e., the
amplitude is above the setting in the TALOS[1:0] bits (b3~2, LOS,...),
TLOS is cleared.
When TLOS is detected, the TLOS_S bit (b2, STAT0,...) will be set. A
transition from ‘0’ to ‘1’ on the TLOS_S bit (b2, STAT0,...) or any transi-
tion (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TLOS_S bit (b2, STAT0,...) will
set the TLOS_IS bit (b2, INTS0,...) to ‘1’, as selected by the TLOS_IES
bit (b2, INTES,...). When the TLOS_IS bit (b2, INTS0,...) is ‘1’, an inter-
rupt will be reported by INT if not masked by the TLOS_IM bit (b2,
INTM0,...).
TLOS may be counted by an internal Error Counter. Refer to
Section 3.5.6 Error Counter.
TLOS can be used to monitor the LOS in the transmit line side
between two channels. The connection between the two channels is
shown in Figure-18. The two channels can be of the same device or
different devices on the premises that the transmit line interfaces are in
the same mode and at least the output of one channel is in High-Z state.
Table-19 lists each results in this case. In the left two columns, the OE
bit (b6, TCF0,...) of the two channels controls the output status in the
transmit line side to ensure that at least one channel is in High-Z state.
The middle two columns list the internal operation status. In the right two
columns, the TLOS_S bit (b2, STAT0,...) of the two channels indicates
the TLOS status in the transmit line side.
Figure-18 TLOS Detection Between Two Channels
Line
Driver
TLOS
Line
Driver
TLOS
TTIPn
TRINGn
TTIPn
TRINGn
Channel #1
Channel #2
TLOS
Detector
TLOS
Detector
Table-19 TLOS Detection Between Two Channels
Output Status ~ Controlled By the OE Bit Internal Operation Status TLOS Status ~ Indicated By the TLOS_S Bit
Channel #1 Channel #2 Channel #1 Channel #2 Channel #1 Channel #2
Normal ~ 1 High-Z ~ 0 Normal (don’t-care) No TLOS ~ 0 No TLOS ~ 0
Normal ~ 1 High-Z ~ 0 Failure Normal TLOS Detected ~ 1 * TLOS Detected ~ 1
High-Z ~ 0 Normal ~ 1 (don’t-care) Normal No TLOS ~ 0 No TLOS ~ 0
High-Z ~ 0 Normal ~ 1 Normal Failure TLOS Detected ~ 1 TLOS Detected ~ 1 *
High-Z ~ 0 High-Z ~ 0 (don’t-care) (don’t-care) TLOS Detected ~ 1 TLOS Detected ~ 1
Note:
* The TLOS_S bit (b2, STAT0,...) may not be set if there is any catastrophic failure in the channel.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 37 December 17, 2009
3.5.4 ALARM INDICATION SIGNAL (AIS) DETECTION AND GEN-
ERATION
3.5.4.1 Alarm Indication Signal (AIS) Detection
AIS is monitored in both the receive path and the transmit path.
When the mark density in the received data or in the data input from
the transmit system side meets certain criteria, AIS is declared or
cleared. In T1/J1 mode, the criteria are in compliance with ANSI T1.231.
In E1 mode, the criteria are in compliance with ITU G.775 or ETSI
300233, as selected by the LAC bit (b7, LOS,...). Refer to Table-20 for
details.
When AIS is detected in the receive path, the LAIS_S bit (b6,
STAT1,...) will be set. A transition from ‘0’ to ‘1’ on the LAIS_S bit (b6,
STAT1,...) or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LAIS_S
bit (b6, STAT1,...) will set the LAIS_IS bit (b6, INTS1,...) to ‘1’, as
selected by the AIS_IES bit (b6, INTES,...). When the LAIS_IS bit (b6,
INTS1,...) is ‘1’, an interrupt will be reported by INT if not masked by the
LAIS_IM bit (b6, INTM1,...).
When AIS is detected in the transmit path, the SAIS_S bit (b7,
STAT1,...) will be set. A transition from ‘0’ to ‘1’ on the SAIS_S bit (b7,
STAT1,...) or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the
SAIS_S bit (b7, STAT1,...) will set the SAIS_IS bit (b7, INTS1,...) to ‘1’,
as selected by the AIS_IES bit (b6, INTES,...). When the SAIS_IS bit
(b7, INTS1,...) is ‘1’, an interrupt will be reported by INT if not masked by
the SAIS_IM bit (b7, INTM1,...).
AIS may be counted by an internal Error Counte. Refer to
Section 3.5.6 Error Counter.
3.5.4.2 (Alarm Indication Signal) AIS Generation
AIS can be generated automatically in the receive path and the
transmit path.
In the receive path, when the ASAIS_LLOS bit (b2, AISG,...) is set,
AIS will be generated automatically once LLOS is detected. When the
ASAIS_SLOS bit (b3, AISG,...) is set, AIS will be generated automati-
cally once SLOS is detected. When AIS is generated, RDPn/RDNn
output all ‘1’s. RCLKn (if available) outputs XCLK.
In the transmit path, when the ALAIS_LLOS bit (b0, AISG,...) is set,
AIS will be generated automatically once LLOS is detected. When the
ALAIS_SLOS bit (b1, AISG,...) is set, AIS will be generated automati-
cally once SLOS is detected. When AIS is generated, TTIPn/TRINGn
output all ‘1’s.
In the transmit path, the AIS transmission is controled by the TXAIS
bit (b4, AISG,...). When the TXAIS bit (b4, AISG,...) is set to ‘1’, all ‘1’s
pattern is transmitted at TTIPn/TRINGn.
AIS generation uses XCLK1 as reference clock.
If pattern (including PRBS, ARB and IB) is generated in the same
direction, the priority of pattern generation is higher. The generated
pattern will overwrite automatic AIS. Refer to Section 3.5.5.1 Pattern
Generation for the output data and clock.
Table-20 AIS Criteria
ITU G.775 for E1 (LAC = 0) ETSI 300233 for E1 (LAC = 1) ANSI T1.231 for T1 (LAC = 0 or 1)
AIS Declaring Less than 3 zeros are received in each of two
consecutive 512-bit data streams.
Less than 3 zeros are received
in a 512-bit data stream.
Less than 9 zeros are received in a 8192-bit stream, i.e., less
than 99.9% of marks in a period of 5.3 ms are received.
AIS Clearing 3 or more zeros are received in each of two
consecutive 512-bit data streams.
3 or more zeros are received in
a 512-bit data stream.
9 or more zeros are received in a 8192-bit data stream.
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
in E1 mode.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 38 December 17, 2009
3.5.5 PRBS, QRSS, ARB AND IB PATTERN GENERATION AND
DETECTION
The pattern includes: Pseudo Random Bit Sequence (PRBS), Quasi-
Random Signal Source (QRSS), Arbitrary Pattern (ARB) and Inband
Loopback (IB).
3.5.5.1 Pattern Generation
The pattern can be generated in the receive path or the transmit
path, as selected by the PG_POS bit (b3, PG,...).
The pattern to be generated is selected by the PG_EN[1:0] bits
(b5~4, PG,...).
If PRBS is selected, three kinds of PRBS patterns with maximum
zero restriction according to ITU-T O.151 and AT&T TR62411 are
provided. They are: (2^20 - 1) QRSS per O.150-4.5, (2^15 - 1) PRBS
per O.152 and (2^11 - 1) PRBS per O.150, as selected by the
PRBG_SEL[1:0] bits (b1~0, PG,...).
If ARB is selected, the content is programmed in the ARB[23:0] bits
(b7~0, ARBH~ARBM~ARBL,...).
If IB is selected, the IB generation is in compliance with ANSI T1.403.
The length of the IB code can be 3 to 8 bits, as determined by the
IBGL[1:0] bits (b5~4, IBL,...). The content is programmed in the IBG[7:0]
bits (b7~0, IBG,...).
The selected pattern is transmitted repeatedly until the PG_EN[1:0]
bits (b5~4, PG,...) is set to ‘00’.
When pattern is generated in the receive path, the reference clock is
XCLK or the recovered clock from the received signal, as selected by
the PG_CK bit (b6, PG,...). The selected reference clock is also output
on RCLKn (if available).
When pattern is generated in the transmit path, the reference clock is
XCLK1 or the transmit clock, as selected by the PG_CK bit (b6, PG,...).
The transmit clock refers to the clock input on TCLKn (in Transmit Single
Rail NRZ Format mode and in Transmit Dual Rail NRZ Format mode) or
the clock recovered from the data input on TDPn and TDNn (in Transmit
Dual Rail RZ Format mode).
In summary, do the followings step by step to generate pattern:
• Select the generation direction by the PG_POS bit (b3, PG,...);
• Select the reference clock by the PG_CK bit (b6, PG,...);
• Select the PRBS pattern by the PRBG_SEL[1:0] bits (b1~0, PG,...)
when PRBS is to be generated; program the ARB pattern in the
ARB[23:0] bits (b7~0, ARBH~ARBM~ARBL,...) when ARB is to be
generated; or set the length and the content of the IB code in the
IBGL[1:0] bits (b5~4, IBL,...) and in the IBG[7:0] bits (b7~0, IBG,...)
respectively when IB is to be generated;
• Set the PG_EN[1:0] bits (b5~4, PG,...) to generate the pattern.
If PRBS or ARB is selected to be generated, the following two steps
can be optionally implemented after the pattern is generated:
• Insert a single bit error by writing ‘1’ to the ERR_INS bit (b5,
ERR,...);
• Invert the generated pattern by setting the PAG_INV bit (b2,
PG,...).
If pattern is generated in the receive path, the generated pattern
should be encoded by using AMI or B8ZS (for T1/J1) / HDB3 (for E1) in
Receive Dual Rail NRZ Format mode, Receive Dual Rail RZ Format
mode and Receive Dual Rail Sliced mode. The encoding rule is selected
by the R_CODE bit (b2, RCF1,...).
If pattern is generated in the transmit path, the generated pattern
should be encoded by using AMI or B8ZS (for T1/J1) / HDB3 (for E1).
The encoding rule is selected by the T_CODE bit (b2, TCF1,...).
The pattern generation is shown in Figure-19 and Figure-20.
Figure-19 Pattern Generation (1)
Figure-20 Pattern Generation (2)
The priority of pattern generation is higher than that of AIS genera-
tion. If they are generated in the same direction, the generated pattern
will overwrite the generated AIS.
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
in E1 mode.
PRBS/ARB/IB
pattern generator
PG_POS
CHn
TDPn/TDNn/TCLKn
RDPn/RDNn/RCLKn
TTIPn/TRINGn
RTIPn/RRINGn
XCLK
PG_EN[1:0]
TCLK/RCLK
PG_CK
PRBS generation
2^11-1
2^15-1
2^20-1
invert
ERR_INS
PAG_INV
Single bit error
insert
24 bits ARB
ARB[23:0]
PG_EN[1:0]
PRBG_SEL[1:0]
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 39 December 17, 2009
3.5.5.2 Pattern Detection
Data received from the line side or data input from the transmit
system side may be extracted for pattern detection. The direction of data
extraction is determined by the PD_POS bit (b3, PD,...). One of PRBS or
ARB pattern is selected for detection and IB detection is always active.
If data is extracted from the receive path, before pattern detection the
data should be decoded by using AMI or B8ZS (for T1/J1) / HDB3 (for
E1). The decoding rule is selected by the R_CODE bit (b2, RCF1,...).
If data is extracted from the transmit path, before pattern detection
the data should be decoded by using AMI or B8ZS (for T1/J1) / HDB3
(for E1) in Transmit Dual Rail NRZ Format mode and Transmit Dual Rail
RZ Format mode. The decoding rule is selected by the T_CODE bit (b2,
TCF1,...).
Pseudo Random Bit Sequence (PRBS) /Arbitrary Pattern (ARB)
Detection
The extracted data can be optionally inverted by the PAD_INV bit
(b2, PD,...) before PRBS/ARB detection.
The extracted data is used to compare with the desired pattern. The
desired pattern is re-generated from the extracted data if the desired
pattern is (2^20 - 1) QRSS per O.150-4.5, (2^15 - 1) PRBS per O.152 or
(2^11 - 1) PRBS per O.150; or the desired pattern is programmed in the
ARB[23:0] bits (b7~0, ARBH~ARBM~ARBL,...) if the desired pattern is
ARB. The desired pattern is selected by the PAD_SEL[1:0] bits (b1~0,
PD,...).
In summary, do the followings step by step to detect PRBS/ARB:
• Select the detection direction by the PD_POS bit (b3, PD,...);
• Set the ARB[23:0] bits (b7~0, ARBH~ARBM~ARBL,...) if the ARB
pattern is desired - this step is omitted if the PRBS pattern is
desired;
• Select the desired PRBS/ARB pattern by the PAD_SEL[1:0] bits
(b1~0, PD,...).
The priority of decoding, data inversion, pattern re-generation, bit
programming and pattern comparison is shown in Figure-21.
Figure-21 PRBS / ARB Detection
During comparison, if the extracted data coincides with the re-gener-
ated PRBS pattern or the programmed ARB pattern for more than 64-bit
hopping window, the pattern is synchronized and the PA_S bit (b5,
STAT1,...) will be set.
In synchronization state, if more than 6 PRBS/ARB errors are
detected in a 64-bit hopping window, the pattern is out of synchroniza-
tion and the PA_S bit (b5, STAT1,...) will be cleared.
In synchronization state, each mismatched bit will generate a PRBS/
ARB error. When a PRBS/ARB error is detected during the synchroniza-
tion, the ERR_IS bit (b1, INTS2,...) will be set and an interrupt will be
reported by INT if not masked by the ERR_IM bit (b1, INTM2,...). The
PRBS/ARB error may be counted by an internal Error Counter. Refer to
Section 3.5.6 Error Counter.
A transition from ‘0’ to ‘1’ on the PA_S bit (b5, STAT1,...) or any tran-
sition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the PA_S bit (b5, STAT1,...) will
set the PA_IS bit (b5, INTS1,...) to ‘1’, as selected by the PA_IES bit (b5,
INTES,...). When the PA_IS bit (b5, INTS1,...) is ‘1’, an interrupt will be
reported by INT if not masked by the PA_IM bit (b5, INTM1,...).
from Rx path
or Tx path Decoding Data
Inversion
PRBS Re-
Generation
Comparison
ARB[23:0]
Programming
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 40 December 17, 2009
Inband Loopback (IB) Detection
The IB detection is in compliance with ANSI T1.403.
The extracted data is used to compare with the target IB code. The
length of the target activate/deactivate IB code can be 3 to 8 bits, as
determined by the IBAL[1:0]/IBDL[1:0] bits (b3~2/b1~0, IBL,...). The
content of the target activate/deactivate IB code is programmed in the
IBA[7:0]/IBD[7:0] bits (b7~0, IBDA/IBDD,...). Refer to Figure-22.
Figure-22 IB Detection
During comparison, if the extracted data coincides with the target
activate/deactivate IB code with no more than 10-2 bit error rate for a
certain period, the IB code is detected. The period depends on the
setting of the AUTOLP bit (b3, LOOP,...).
If the AUTOLP bit (b3, LOOP,...) is ‘0’, Automatic Digital/Remote
Loopback is disabled. In this case, when the activate IB code is detected
for more than 40 ms, the IBA_S bit (b1, STAT1,...) will be set to indicate
the activate IB code detection; when the deactivate IB code is detected
for more than 40 ms (T1/J1 mode) / 30 ms (E1 mode), the IBD_S bit (b0,
STAT1,...) will be set to indicate the deactivate IB code detection.
If the AUTOLP bit (b3, LOOP,...) is ‘1’, Automatic Digital/Remote
Loopback is enabled. In this case, when the activate IB code is detected
for more than 5.1 seconds, the IBA_S bit (b1, STAT1,...) will be set to
indicate the activate IB code detection. The detection of the activate IB
code in the receive path will activate Remote Loopback or the detection
of the activate IB code in the transmit path will activate Digital Loopback
(refer to Section 3.5.7.2 Remote Loopback & Section 3.5.7.3 Digital
Loopback). When the deactivate IB code is detected for more than 5.1
seconds, the IBD_S bit (b0, STAT1,...) will be set to indicate the deacti-
vate IB code detection. The detection of the deactivate IB code in the
receive path will deactivate Remote Loopback or the detection of the
deactivate IB code in the transmit path will deactivate Digital Loopback
(refer to Section 3.5.7.2 Remote Loopback & Section 3.5.7.3 Digital
Loopback).
A transition from ‘0’ to ‘1’ on the IBA_S/IBD_S bit (b1/b0, STAT1,...)
or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the IBA_S/IBD_S bit
(b1/b0, STAT1,...) will set the IBA_IS/IBD_IS bit (b1/b0, INTS1,...) to ‘1’
respectively, as selected by the IB_IES bit (b0, INTES,...). When the
IBA_IS/IBD_IS bit (b1/b0, INTS1,...) is ‘1’, an interrupt will be reported
on INT if not masked by the IBA_IM/IBD_IM bit (b1/b0, INTM1,...).
3.5.6 ERROR COUNTER
An internal 16-bit Error Counter is used to count one of the following
errors:
• LBPV: BPV/CV detected in the receive path (line side);
• LEXZ: EXZ detected in the receive path (line side);
• LBPV + LEXZ: BPV/CV and EXZ detected in the receive path (line
side);
• SBPV: BPV/CV detected in the transmit path (system side) (dis-
abled in Transmit Single Rail NRZ Format mode);
• SEXZ: EXZ detected in the transmit path (system side);
• SBPV + SEXZ: BPV/CV and EXZ detected in the transmit path
(system side) (disabled in Transmit Single Rail NRZ Format
mode);
• PRBS/ARB error.
The CNT_SEL[2:0] bits (b4~2, ERR,...) select one of the above
errors to be counted.
The Error Counter is buffered. It is updated automatically or manu-
ally, as determined by the CNT_MD bit (b1, ERR,...).
The Error Counter is accessed by reading the ERRCH and ERRCL
registers.
3.5.6.1 Automatic Error Counter Updating
When the CNT_MD bit (b1, ERR,...) is ‘1’, the Error Counter is
updated every one second automatically.
The one-second timer uses MCLK as clock reference. The expiration
of each one second will set the TMOV_IS bit (b0, INTTM) and induce an
interrupt reported by INT if not masked by the TMOV_IM bit (b0, GCF).
When each one second expires, the Error Counter transfers the
accumulated error numbers to the ERRCH and ERRCL registers and
the Error Counter will be cleared to start a new round counting. The
ERRCH and ERRCL registers should be read in the next second, other-
wise they will be overwritten.
When the ERRCH and ERRCL registers are all ‘1’s and there is still
error to be accumulated, the registers will be overflowed. The overflow is
indicated by the CNTOV_IS bit (b0, INTS2,...) and will induce an inter-
rupt reported by INT if not masked by the CNTOV_IM (b0, INTM2,...).
The process of automatic Error Counter updating is illustrated in
Figure-23.
from Rx path
or Tx path Decoding
Target code -
length & content
programming
Comparison
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 41 December 17, 2009
Figure-23 Automatic Error Counter Updating
3.5.6.2 Manual Error Counter Updating
When the CNT_MD bit (b1, ERR,...) is ‘0’, the Error Counter is
updated manually.
When there is a transition from ‘0’ to ‘1’ on the CNT_STOP bit (b0,
ERR,...), the Error Counter transfers the accumulated error numbers to
the ERRCH and ERRCL registers and the Error Counter will be cleared
to start a new round counting. The ERRCH and ERRCL registers should
be read in the next round of error counting, otherwise they will be over-
written.
When the ERRCH and ERRCL registers are all ‘1’s and there is still
error to be accumulated, the registers will be overflowed. The overflow is
indicated by the CNTOV_IS bit (b0, INTS2,...) and will induce an inter-
rupt reported by INT if not masked by the CNTOV_IM (b0, INTM2,...).
The process of manual Error Counter updating is illustrated in
Figure-24.
Figure-24 Manual Error Counter Updating
Read the ERRCH & ERRCL
registers in the next second
TMOV_IS is cleared after a '1' is
written to it
Data in the Error Counter transfers
to the ERRCH & ERRCL registers
The Error Counter is cleared
One second expired?
(TMOV_IS = 1 ?)
Counting
Automatic Error Counter Updating
(CNT_MD = 1)
No
Yes
repeat the
same process
in the next
second
Read the ERRCH & ERRCL
registers in the next round
Data in the Error Counter transfers
to the ERRCH & ERRCL registers
The Error Counter is cleared
A transition from '0' to
'1' on CNT_STOP ?
Counting
Manual Error Counter Updating
(CNT_MD = 0)
No
Yes
repeat the
same
process in
the next
round
(CNT_STOP
must be
cleared
before the
next round)
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 42 December 17, 2009
3.5.7 LOOPBACK
There are four kinds of loopback:
• Analog Loopback
• Remote Loopback
• Digital Loopback
Refer to Figure-1 for loopback location.
3.5.7.1 Analog Loopback
Analog Loopback is enabled by the ALP bit (b0, LOOP,...). The data
stream to be transmitted on the TTIPn/TRINGn pins is internally looped
to the RTIPn/RRINGn pins.
In Analog Loopback mode, the data stream to be transmitted is still
output to the line side, while the data stream received from the line side
is covered by the Analog Loopback data.
Anytime when Analog Loopback is set, the other loopbacks (i.e.,
Digital Loopback and Remote Loopback) are disabled.
In Analog Loopback, the priority of the diagnostic facilities in the
receive path is: pattern generation > looped data. AIS generation is
disabled in both the receive path and the transmit path. Refer to Figure-
25.
Figure-25 Priority Of Diagnostic Facilities During Analog Loopback
Tx path
BPV/CV, EXZ,
SLOS, AIS, pattern
detection
Pattern generation
Auto AIS
generation
X
Rx path
LLOS detection AIS generation
X
BPV/CV, EXZ,
AIS, pattern
detection
Pattern generation
Analog
Loopback
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 43 December 17, 2009
3.5.7.2 Remote Loopback
Remote Loopback can be configured manually or automatically.
Either manual Remote Loopback configuration or automatic Remote
Loopback configuration will enable Remote Loopback.
Manual Remote Loopback is enabled by the RLP bit (b1, LOOP,...).
Automatic Remote Loopback is enabled when the pattern detection
is assigned in the receive path (i.e., the PD_POS bit (b3, PD,...) is ‘0’)
and the AUTOLP bit (b3, LOOP,...) is ‘1’. The corresponding channel will
enter Remote Loopback when the activate IB code is detected in the
receive path for more than 5.1 sec.; and will return from Remote Loop-
back when the deactivate IB code is detected in the receive path for
more than 5.1 sec. Refer to section Inband Loopback (IB) Detection on
page 40 for details. When automatic Remote Loopback is active, setting
the AUTOLP bit (b3, LOOP,...) back to ‘0’ will also stop automatic
Remote Loopback. The setting of the PD_POS bit (b3, PD,...) should not
be changed during automatic Remote Loopback. The AUTOLP_S bit
(b7, STAT0,...) indicates the automatic Remote Loopback status.
In Remote Loopback mode, the data stream output from the RJA (if
enabled) is internally looped to the Waveform Shaper. The data stream
received from the line side is still output to the system side, while the
data stream input from the system side is covered by the Remote Loop-
back data and the status on TCLKn does not affect the Remote Loop-
back. However, the BPV/CV, EXZ, SLOS, AIS and pattern detection in
the transmit path still monitors the data stream input from the system
side.
In Remote Loopback mode, the priority of the diagnostic facilities in
the receive path is: pattern generation > AIS generation; the priority of
the diagnostic facilities in the transmit path is: pattern generation >
looped data. AIS generation is disabled in the transmit path. Refer to
Figure-26.
Figure-26 Priority Of Diagnostic Facilities During Manual Remote Loopback
Tx path
BPV/CV, EXZ, SLOS,
AIS, pattern detection
Pattern generation
Auto AIS
generation
X
Rx path
LLOS, AIS
detection AIS generation BPV/CV, EXZ,
pattern detection Pattern generation
Remote
Loopback
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 44 December 17, 2009
3.5.7.3 Digital Loopback
The Digital Loopback can be configured manually or automatically.
Either manual Digital Loopback configuration or automatic Digital Loop-
back configuration will enable Digital Loopback.
Manual Digital Loopback is enabled by the DLP bit (b2, LOOP,...).
Automatic Digital Loopback is enabled when the pattern detection is
assigned in the transmit path (i.e., the PD_POS bit (b3, PD,...) is ‘1’) and
the AUTOLP bit (b3, LOOP,...) is ‘1’. The corresponding channel will
enter Digital Loopback when the activate IB code is detected in the
transmit path for more than 5.1 sec.; and will return from Digital Loop-
back when the deactivate IB code is detected in the transmit path for
more than 5.1 sec. Refer to section Inband Loopback (IB) Detection on
page 40 for details. When automatic Digital Loopback is active, setting
the AUTOLP bit (b3, LOOP,...) back to ‘0’ will also stop automatic Digital
Loopback. The setting of the PD_POS bit (b3, PD,...) should not be
changed during automatic Digital Loopback. The AUTOLP_S bit (b7,
STAT0,...) indicates the automatic Digital Loopback status.
In Digital Loopback mode, the data stream output from the TJA (if
enabled) is internally looped to the Decoder (if enabled). The data
stream to be transmitted is still output to the line side, while the data
stream received from the line side is covered by the Digital Loopback
data. However, LLOS and AIS detection in the receive path still monitors
the data stream received from the line side.
In Digital Loopback mode, the priority of the diagnostic facilities in the
receive path is: pattern generation > looped data; the priority of the diag-
nostic facilities in the transmit path is: pattern generation > looped data >
AIS generation. AIS generation is disabled in the receive path.
Figure-27 Priority Of Diagnostic Facilities During Digital Loopback
Tx path
BPV/CV, EXZ,
SLOS, AIS, pattern
detection
Pattern generation
Auto AIS
generation
Rx path
LLOS, AIS
detection AIS generation
X
BPV/CV, EXZ,
AIS, pattern
detection
Pattern generation
Digital
Loopback
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 45 December 17, 2009
3.5.8 CHANNEL 0 MONITORING
Channel 0 can be used as a monitoring channel when not used as a
regular channel. Channel 0 support G.772 Monitoring and Jitter
Measurements.
3.5.8.1 G.772 Monitoring
Selected by the MON[5:0] bits (b5~0, MON), any receiver or trans-
mitter of the other 15 channels can be monitored by channel 0 (as
shown in Figure-28).
When the G.772 Monitoring is implemented (the MON[5:0] bits
(b5~0, MON) is not ‘0’), the registers of the receiver of channel 0 should
be the same as those of the selected receiver /transmitter except the
line interface related registers.
Once the G.772 Monitoring is implemented, the receiver of channel 0
switches to External Impedance Matching mode automatically, and the
setting in the R_TERM[2:0] bits (b2~0, RCF0,...) of channel 0 is ignored.
During the G.772 Monitoring, channel 0 processes as normal after
data is received from the selected path and the operation of the moni-
tored path is not effected.
The signal which is monitored goes through the Clock & Data
Recovery of monitoring channel (channel 0). The monitored clock can
output on RCLK0. The monitored data can be observed digitally on the
output pin of RCLK0, RD0/RDP0 and RDN0. LOS detector is still in use
in channel 0 for the monitored signal.
In monitoring mode, channel 0 can be configured to Remote Loop-
back. The signal which is being monitored will output on TTIP0 and
TRING0. The output signal can then be connected to a standard test
equipment for non-intrusive monitoring.
Figure-28 G.772 Monitoring
RDN0
RCLK0
RTIP0
RRING0
TCLK0/TDN0
TDN0
TD0/TDP0
RDn/RDPn
RDNn
RCLKn
RTIPn
RRINGn
TCLKn/TDNn
TDNn
TDn/TDPn
CH 0
G.772 Monitoring
TTIPn
TRINGn
TTIP0
TRING0
RD0/RDP0
Any of the
Remaining Channels
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 46 December 17, 2009
3.5.8.2 Jitter Measurement (JM)
The RJA of channel 0 consists of a Jitter Measurement (JM) module.
When the RJA is enabled in channel 0, the JM is used to measure the
positive and negative peak value of the demodulated jitter signal of the
received data stream. The bandwidth of the measured jitter is selected
by the JM_BW bit (b0, JM).
The greatest positive peak value monitored in a certain period is indi-
cated by the JIT_PH and JIT_PL registers, while the greatest negative
peak value monitored in the same period is indicated by the JIT_NH and
JIT_NL registers. The relationship between the greatest positive /nega-
tive peak value and the indication in the corresponding registers is:
Positive Peak = [JIT_PH, JIT_PL] / 16 (UIpp);
Negative Peak = [JIT_NH, JIT_NL] / 16 (UIpp).
The period is determined by the JM_MD bit (b1, JM).
When the JM_MD bit (b1, JM) is ‘1’, the period is one second auto-
matically. The one-second timer uses MCLK as clock reference. The
expiration of each one second will set the TMOV_IS bit (b0, INTTM) and
induce an interrupt reported by INT if not masked by the TMOV_IM bit
(b0, GCF). The TMOV_IS bit (b0, INTTM) is cleared after a ‘1’ is written
to this bit. When each one second expires, internal buffers transfer the
greatest positive/negative peak value accumulated in this one second to
the JIT_PH and JIT_PL / JIT_NH and JIT_NL registers respectively and
the internal buffers will be cleared to start a new round measurement.
The registers should be read in the next second, otherwise they will be
overwritten. Refer to Figure-29 for the process.
When the JM_MD bit (b1, JM) is ‘0’, the period is controlled by the
JM_STOP bit (b2, JM) manually. When there is a transition from ‘0’ to ‘1’
on the JM_STOP bit (b2, JM), the internal buffers transfer the greatest
positive/negative peak value accumulated in this period to the JIT_PH
and JIT_PL / JIT_NH and JIT_NL registers respectively and the internal
buffers will be cleared to start a new round measurement. The registers
should be read in the next round of jitter measurement, otherwise they
will be overwritten. Refer to Figure-30 for the process.
Figure-29 Automatic JM Updating
Figure-30 Manual JM Updating
Read the JIT_PH, JIT_PL & JIT_NH,
JIT_NL registers in the next second
TMOV_IS is cleared after a '1' is written to it
The greatest peak value in the internal
buffers transfers to the JIT_PH & JIT_PL /
JIT_NH & JIT_NL registers respectively
The internal buffers are cleared
One second expired?
(TMOV_IS = 1 ?)
Peak jitter measurement
Automatic JM Updating
(JM_MD = 1)
No
Yes
repeat the
same
process in
the next
second
Read the JIT_PH, JIT_PL & JIT_NH,
JIT_NL registers in the next round
The greatest peak value in the internal
buffers transfers to the JIT_PH & JIT_PL
/ JIT_NH & JIT_NL registers respectively
The internal buffers are cleared
A transition from '0' to
'1' on JM_STOP ?
Peak jitter measurement
Manual JM Updating
(JM_MD = 0)
No
Yes
repeat the
same
process in
the next
round
(JM_STOP
must be
cleared
before the
next round)
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 47 December 17, 2009
3.6 CLOCK INPUTS AND OUTPUTS
The IDT82P20416 provides two kinds of clock outputs:
• Free running clock outputs on CLKT1 and CLKE1
The following Clock Input is provided:
• MCLK as programmable reference timing for the IDT82P20416.
3.6.1 FREE RUNNING CLOCK OUTPUTS ON CLKT1/CLKE1
An internal clock generator uses MCLK as reference to generate all
the clocks required by internal circuits and CLKT1/CLKE1 outputs.
MCLK should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm
(in E1 mode) accuracy. The clock frequency of MCLK is 1.544/2.048 X N
MHz (1 ≤ N ≤ 8, N is an integer number), as determined by
MCKSEL[3:0]. Refer to Chapter 2 Pin Description for details.
The outputs on CLKT1 and CLKE1 are free running (locking to
MCLK). The output of CLKT1 is determined by the CLKT1_EN bit (b1,
CLKG) and the CLKT1 bit (b0, CLKG). Refer to Table-21. The output of
CLKE1 is determined by the CLKE1_EN bit (b3, CLKG) and the CLKE1
bit (b2, CLKG). Refer to Table-22.
Table-21 Clock Output on CLKT1
Control Bits
Clock Output On CLKT1
CLKT1_EN CLKT1
0 (don’t-care) High-Z
1
08 KHz
1 1.544 KHz
Table-22 Clock Output on CLKE1
Control Bits
Clock Output On CLKE1
CLKE1_EN CLKE1
0 (don’t-care) High-Z
1
08 KHz
1 2.048 KHz
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 48 December 17, 2009
3.6.2 MCLK, MASTER CLOCK INPUT
MCLK provides a stable reference timing for the IDT82P20416.
MCLK should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm
(in E1 mode) accuracy. The clock frequency of MCLK is set by pins
MCKSEL[3:0] and can be N x 1.544 MHz or N x 2.048 MHz with 1 ≤ N ≤
8 (N is an integer number). Refer to MCKSEL[3:0] pin description for
details.
If there is a loss of MCLK (duty cycle is less than 30% for 10 µs), the
device will enter power down. In this case, both the receive and transmit
circuits are turned off. The pins on the line interface will be in High-Z
state. The pins on receive system interface will be in High-Z state or in
low level, as selected by the RHZ bit (b6, RCF0,...). The input on the
transmit system interface is ignored and the output on the transmit
system interface will be in High-Z state. Refer to Section 3.2.7 Receiver
Power Down and Section 3.3.7 Transmitter Power Down for details.
If MCLK recovers after loss of MCLK the device will be reset auto-
matically.
3.6.3 XCLK, INTERNAL REFERENCE CLOCK INPUT
XCLK is derived from MCLK. For the respective channel, it is 1.544
MHz in T1/J1 mode or 2.048 MHz in E1 mode. XCLK is used as select-
able reference clock for
• pattern /AIS generation
• RCLKn in LLOS
• Loss of TCLKn to determine Transmit Output High-Z.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 49 December 17, 2009
3.7 INTERRUPT SUMMARY
There are altogether 20 kinds of interrupt sources as listed in Table-
23. Among them, No.1 to No.19 are per-channel interrupt sources, while
No. 20 is a global interrupt source.
For interrupt sources from No.1 to No.10, the occurrence of the event
will cause the corresponding Status bit to be set to ‘1’. And selected by
the Interrupt Trigger Edges Select bit, either a transition from ‘0’ to ‘1’ or
any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ of the Status bit will cause
the Interrupt Status bit to be set to ‘1’, which indicates the occurrence of
an interrupt event.
For interrupt sources from No.11 to No.20, the occurrence of the
event will cause the corresponding Interrupt Status Bit to be set to ‘1’.
All the interrupt can be masked by the GLB_IM bit (b1, GCF) globally
or by the corresponding interrupt mask bit individually. For all the inter-
rupt sources, if not masked, the occurrence of the interrupt event will
trigger an interrupt indicated by the INT pin. For per-channel interrupt
sources, if not masked, the occurrence of the interrupt event will also
cause the corresponding INT_CHn bit (INTCH1~3) to be set ‘1’.
An interrupt event is cleared by writing ‘1’ to the corresponding Inter-
rupt Status bit. The INT_CHn bit (INTCH1~3) will not be cleared until all
the interrupts in the corresponding channel are acknowledged. The INT
pin will be inactive until all the interrupts are acknowledged. Refer to
Figure-31 for interrupt service flow.
Table-23 Interrupt Summary
No. Interrupt Source Status Bit Interrupt Trigger Edges
Select Bit Interrupt Status Bit Interrupt Mask Bit
1 TCLKn is missing. TCKLOS_S (b3,
STAT0,...)
TCKLOS_IES (b3,
INTES,...)
TCKLOS_IS (b3,
INTS0,...)
TCKLOS_IM (b3,
INTM0,...)
2 LLOS is detected. LLOS_S (b0, STAT0,...) LOS_IES (b1, INTES,...) LLOS_IS (b0, INTS0,...) LLOS_IM (b0, INTM0,...)
3 SLOS is detected. SLOS_S (b1, STAT0,...) LOS_IES (b1, INTES,...) SLOS _IS (b1, INTS0,...) SLOS_IM (b1, INTM0,...)
4 TLOS is detected. TLOS_S (b2, STAT0,...) TLOS_IES (b2, INTES,...) TLOS_IS (b2, INTS0,...) TLOS_IM (b2, INTM0,...)
5 LAIS is detected. LAIS_S (b6, STAT1,...) AIS_IES (b6, INTES,...) LAIS_IS (b6, INTS1,...) LAIS_IM (b6, INTM1,...)
6 SAIS is detected. SAIS_S (b7, STAT1,...) AIS_IES (b6, INTES,...) SAIS_IS (b7, INTS1,...) SAIS_IM (b7, INTM1,...)
7 TOC is detected. TOC_S (b4, STAT0,...) TOC_IES (b4, INTES,...) TOC_IS (b4, INTS0,...) TOC_IM (b4, INTM0,...)
8 The PRBS/ARB pattern is detected syn-
chronized.
PA_S (b5, STAT1,...) PA_IES (b5, INTES,...) PA_IS (b5, INTS1,...) PA_IM (b5, INTM1,...)
9 Activate IB code is detected. IBA_S (b1, STAT1,...) IB_IES (b0, INTES,...) IBA_IS (b1, INTS1,...) IBA_IM (b1, INTM1,...)
10 Deactivate IB code is detected. IBD_S (b0, STAT1,...) IB_IES (b0, INTES,...) IBD_IS (b0, INTS1,...) IBD_IM (b0, INTM1,...)
11 The FIFO of the RJA is overflow or
underflow.
- - RJA_IS (b5, INTS0,...) RJA_IM (b5, INTM0,...)
12 The FIFO of the TJA is overflow or
underflow.
- - TJA_IS (b6, INTS0,...) TJA_IM (b6, INTM0,...)
13 Waveform amplitude is overflow. - - DAC_IS (b7, INTS0,...) DAC_IM (b7, INTM0,...)
14 SBPV is detected. - - SBPV_IS (b5, INTS2,...) SBPV_IM (b5, INTM2,...)
15 LBPV is detected. - - LBPV_IS (b4, INTS2,...) LBPV_IM (b4, INTM2,...)
16 SEXZ is detected. - - SEXZ_IS (b3, INTS2,...) SEXZ_IM (b3, INTM2,...)
17 LEXZ is detected. - - LEXZ_IS (b2, INTS2,...) LEXZ_IM (b2, INTM2,...)
18 PRBS/ARB error is detected. - - ERR_IS (b1, INTS2,...) ERR_IM (b1, INTM2,...)
19 The ERRCH and ERRCL registers are
overflowed.
- - CNTOV_IS (b0, INTS2,...) CNTOV_IM (b0, INTM2,...)
20 One second time is over. - - TMOV_IS (b0, INTTM) TMOV_IM (b0, GCF)
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Functional Description 50 December 17, 2009
Figure-31 Interrupt Service Process
INT active
Read TMOV_IS Read INT_CHn
TMOV_IS = 1 ?
Yes
Serve the interrupt.
Write '1' to clear TMOV_IS.
INT_CHn = 1 ?
Yes
Read the interrupt status bits
in the corresponding channel.
Find the interrupt source and
serve it.
Write '1' to clear the
corresponding interrupt status bit.
INT_CHn is cleared when all
interrupts in the corresponding
channel are cleared.
No
No
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Miscellaneous 51 December 17, 2009
4 MISCELLANEOUS
4.1 RESET
The reset operation resets all registers, state machines as well as I/O
pins to their default value or status.
The IDT82P20416 provides 4 kinds of reset:
• Power-on reset;
• Hardware reset;
• Global software reset;
• Per-channel software reset.
The Power-on, Hardware and Global software reset operations reset
all the common blocks (including clock generator/synthesizer and micro-
processor interface) and channel-related parts. The Per-channel soft-
ware reset operation resets the channel-related parts. Figure-32 shows
a general overview of the reset options.
During reset, all the line interface pins (i.e., TTIPn/TRINGn and
RTIPn/RRINGn) are in High-Z state.
After reset, all the items listed in Table-24 are true.
Figure-32 Reset
clock generator/
synthesizer
microprocessor
interface
channel
Hardware reset Global software resetPower-on reset
Per-channel software reset
Table-24 After Reset Effect Summary
Effect On ... Power-On Reset, Hardware Reset and Global Software Reset Per-Channel Software Reset
TTIPn/TRINGn & RTIPn/
RRINGn
All TTIPn/TRINGn & RTIPn/RRINGn pins are in High-Z state. Only TTIPn/TRINGn & RTIPn/RRINGn in the corresponding chan-
nel are in High-Z.
Line Interface Mode All channels are reset to T1/J1 mode. Only the corresponding channel is reset to T1/J1 mode.
System interface All channels are in Dual Rail NRZ Format. Only the corresponding channel is in Dual Rail NRZ Format.
General I/O pins (i.e.,
D[7:0] and GPIO[1:0])
As input pins. (No effect)
INT Open drain output. (No effect)
CLKT1, CLKE1 Output enable. (No effect)
LLOS, LLOS0 Output enable. (No effect)
TDO, SDO/ACK/RDY High-Z. (No effect)
state machines All state machines are reset. The state machines in the corresponding channel are reset.
Interrupt sources All interrupt sources are masked. The interrupt sources in the corresponding channel are masked.
Registers All registers are reset to their default value. The registers in the corresponding channel are reset to their
default value except that there is no effect on the T1E1 bit.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Miscellaneous 52 December 17, 2009
4.1.1 POWER-ON RESET
Power-on reset is initiated during power-up. When all VDD inputs
(1.8V and 3.3V) reach approximately 60% of the standard value of VDD,
power-on reset begins. If MCLK is applied, power-on reset will complete
within 1 ms maximum; if MCLK is not applied, the device remains in
reset state.
4.1.2 HARDWARE RESET
Pulling the RST pin to low will initiate hardware reset. The reset cycle
should be more than 1 µs. If the RST pin is held low continuously, the
device remains in reset state.
4.1.3 GLOBAL SOFTWARE RESET
Writing the RST register will initiate global software reset. Once initi-
ated, global software reset completes in 1 µs maximum.
4.1.4 PER-CHANNEL SOFTWARE RESET
Writing a ‘1’ to the CHRST bit (b1, CHCF,...) will initiate per-channel
software reset. Once initiated, per-channel software reset completes in 1
µs maximum and the CHRST bit (b1, CHCF,...) is self cleared.
This reset is different from other resets, for:
• It does not reset the T1E1 bit (b0, CHCF,...). That is, the operation
mode of each channel is not changed;
• It does not reset the global registers, state machines and common
pins (including the pins of clock generator, microprocessor inter-
face and JTAG interface);
• It does not reset the other channels.
4.2 MICROPROCESSOR INTERFACE
The microprocessor interface provides access to read and write the
registers in the device. The interface consists of:
• Serial microprocessor interface;
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Miscellaneous 53 December 17, 2009
4.3 POWER UP
No power up sequencing for the VDD inputs (1.8 V and 3.3 V) has to
be provided for the IDT82P20416. A Power-on reset will be initiated
during power up. Refer to Section 4.1 Reset.
4.4 HITLESS PROTECTION SWITCHING (HPS) SUM-
MARY
In today’s telecommunication systems, ensuring no traffic loss is
becoming increasingly important. To combat these problems, redun-
dancy protection must be built into the systems carrying this traffic.
There are many types of redundancy protection schemes, including 1+1
and 1:1 hardware protection without the use of external relays. Refer to
Figure-33, Figure-34 and Figure-35 for different protection schemes.
The IDT82P20416 provides an enhanced architecture to support both
protection schemes.
IDT82P20416 highlights for HPS support:
• Independent programmable receive and transmit high impedance
for Tip and Ring inputs and outputs to support 1+1 and 1:1 redun-
dancy
• Fully integrated receive termination, required to support 1:1 redun-
dancy
• Enhanced internal architecture to guarantee High Impedance for
Tip and Ring Inputs and Outputs during Power Off or Power Fail-
ure
• Asynchronous hardware control (OE, RIM) for fast global high
impedance of receiver and transmitter (hot switching between
working and backup board)
Figure-33 1+1 HPS Scheme, Differential Interface (Shared Common Transformer)
1:2
Tx
LIU on primary line card
LIU on backup line card backplane interface card
1:1
Tx
Rx
Rx
120 Ω
OE
RIM
OE
RIM
Hot switch control
VDDTn
•
VDDTn
•
•
VDDRn
•
VDDRn
VDDTn
•
VDDTn
•
•
VDDRn
•
VDDRn
Rx: Partially Internal Impedance Matching mode. A fixed external 120 Ω resistor is placed on the backplane and provides a common termination for
T1/J1/E1 applications. The R_TERM[2:0] bits (b2~0, RCF0,...) setting is as follows: ‘000’ for T1 100 Ω twisted pair cable, ‘001’ for J1 110 Ω twisted
pair cable, ‘010’ for E1 120 Ω twisted pair cable and ‘011’ for E1 75 Ω coaxial cable.
Tx: Internal Impedance Matching mode. The T_TERM[2:0] bits (b2~0, TCF0,...) setting is as follows: ‘000’ for T1 100Ω twisted pair cable, ‘001’
for J1 110 Ω twisted pair cable, ‘010’ for E1 120 Ω twisted pair cable and ‘011’ for E1 75 Ω coaxial cable.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Miscellaneous 54 December 17, 2009
Figure-34 1:1 HPS Scheme, Differential Interface (Individual Transformer)
Tx
primary card
backup card
Tx
Rx
Rx
OE
RIM
OE
RIM
Hot switch control
1:2
1:2
1:1
1:1
VDDTn
•
VDDTn
•
•
VDDRn
•
VDDRn
VDDTn
•
VDDTn
•
•
VDDRn
•
VDDRn
Rx: Fully Internal Impedance Matching mode. In this mode, there is no external resistor required. The R_TERM[2:0] bits (b2~0, RCF0,...)
setting is as follows: ‘000’ for T1 100Ω twisted pair cable, ‘001’ for J1 110 Ω twisted pair cable, ‘010’ for E1 120 Ω twisted pair cable and
‘011’ for E1 75 Ω coaxial cable.
Tx: Internal Impedance Matching mode. The T_TERM[2:0] bits (b2~0, TCF0,...) setting is as follows: ‘000’ for T1 100 Ω twisted pair
cable, ‘001’ for J1 110 Ω twisted pair cable, ‘010’ for E1 120 Ω twisted pair cable and ‘011’ for E1 75 Ω coaxial cable.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Miscellaneous 55 December 17, 2009
Figure-35 1+1 HPS Scheme, E1 75 ohm Single-Ended Interface (Shared Common Transformer)
Rx: 75 Ω External Impedance Matching mode. In this mode, there is no external resistor required. The RIM pin should be left open and the configuration
of the R_TERM[2:0] bits (b2~0, RCF0,...) is ignored.
Tx: 75 Ω Internal Impedance Matching mode. The T_TERM[2:0] bits (b2~0, TCF0,...) should be set to ‘011’.
primary line card
backup line card
Tx
Tx
Rx
Rx
OE
RIM
OE
RIM
Hot switch control
4.7 µF
19 Ω
0.47 µF
1:2
1:2
VDDTn
•
•
VDDRn
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 56 December 17, 2009
5 PROGRAMMING INFORMATION
5.1 REGISTER MAP
5.1.1 GLOBAL REGISTER
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
Common Control
000 ID - Device ID Register ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 P 60
040 RST - Global Reset Register RST7 RST6 RST5 RST4 RST3 RST2 RST1 RST0 P 60
080 GCF - Global Configuration
Register
- - - COPY INT_PIN1 INT_PIN0 GLB_IM TMOV_IM P 61
0C0 MON - G.772 Monitor Configura-
tion Register
- - MON5 MON4 MON3 MON2 MON1 MON0 P 61
100 GPIO - General Purpose I/O Pin
Definition Register
- - - - LEVEL1 LEVEL0 DIR1 DIR0 P 62
Reference Clock Timing Option
1C0 CLKG - CLKT1 & CLKE1 Gener-
ation Control Register
- - - - CLKE1_EN CLKE1 CLKT1_EN CLKT1 P 63
Interrupt Indication
2C0 INTCH1 - Interrupt Requisition
Source Register 1
INT_CH8 INT_CH7 INT_CH6 INT_CH5 INT_CH4 INT_CH3 INT_CH2 INT_CH1 P 63
300 INTCH2 - Interrupt Requisition
Source Register 2
- INT_CH15 INT_CH14 INT_CH13 INT_CH12 INT_CH11 INT_CH10 INT_CH9 P 64
380 INTCH3 - Interrupt Requisition
Source Register 3
INT_CH0------ -P64
3C0 INTTM - One Second Timer
Interrupt Status Register
-------TMOV_ISP64
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 57 December 17, 2009
5.1.2 PER-CHANNEL REGISTER
Only the address of channel 1 is listed in the ‘Address (Hex)’ column
of the following table. For the addresses of the other channels, refer to
the description of each register.
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
Channel Control
001 CHCF - Channel Configuration
Register
- - - - - - CHRST T1E1 P 65
JA Configuration
002 TJA - Transmit Jitter Attenuation
Configuration Register
- - - TJA_LIMT TJA_EN TJA_DP1 TJA_DP0 TJA_BW P 65
003 RJA - Receive Jitter Attenuation
Configuration Register
- - - RJA_LIMT RJA_EN RJA_DP1 RJA_DP0 RJA_BW P 66
Transmit Path Configuration
004 TCF0 - Transmit Configuration
Register 0
- OE T_OFF THZ_OC T_SING T_TERM2 T_TERM1 T_TERM0 P 67
005 TCF1 - Transmit Configuration
Register 1
- - - TCK_ES TD_INV T_CODE T_MD1 T_MD0 P 68
006 PULS - Transmit Pulse Configu-
ration Register
- - - - PULS3 PULS2 PULS1 PULS0 P 69
007 SCAL - Amplitude Scaling Con-
trol Register
- - SCAL5 SCAL4 SCAL3 SCAL2 SCAL1 SCAL0 P 70
008 AWG0 - Arbitrary Waveform
Generation Control Register 0
- DONE RW SAMP4 SAMP3 SAMP2 SAMP1 SAMP0 P 70
009 AWG1 - Arbitrary Waveform
Generation Control Register 1
- WDAT6 WDAT5 WDAT4 WDAT3 WDAT2 WDAT1 WDAT0 P 71
Receive Path Configuration
00A RCF0 - Receive Configuration
Register 0
RCKH RHZ R_OFF R120IN R_SING R_TERM2 R_TERM1 R_TERM0 P 72
00B RCF1 - Receive Configuration
Register 1
- - - RCK_ES RD_INV R_CODE R_MD1 R_MD0 P 73
00C RCF2 - Receive Configuration
Register 2
------MG1MG0P73
Diagnostics
00D LOS - LOS Configuration Regis-
ter
LAC ALOS2 ALOS1 ALOS0 TALOS1 TALOS0 TDLOS1 TDLOS0 P 74
00E ERR - Error Detection & Inser-
tion Control Register
EXZ_DEF BPV_INS ERR_INS CNT_SEL2 CNT_SEL1 CNT_SEL0 CNT_MD CNT_STOP P 75
00F AISG - AIS Generation Control
Register
- - - TXAIS ASAIS_SL
OS
ASAIS_LLO
S
ALAIS_SLO
S
ALAIS_LLO
S
P76
010 PG - Pattern Generation Control
Register
- PG_CK PG_EN1 PG_EN0 PG_POS PAG_INV PRBG_SEL
1
PRBG_SEL
0
P77
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 58 December 17, 2009
011 PD - Pattern Detection Control
Register
- - - - PD_POS PAD_INV PAD_SEL1 PAD_SEL0 P 78
012 ARBL - Arbitrary Pattern Gener-
ation / Detection Low-Byte Reg-
ister
ARB7 ARB6 ARB5 ARB4 ARB3 ARB2 ARB1 ARB0 P 79
013 ARBM - Arbitrary Pattern Gen-
eration / Detection Middle-Byte
Register
ARB15 ARB14 ARB13 ARB12 ARB11 ARB10 ARB9 ARB8 P 79
014 ARBH - Arbitrary Pattern Gener-
ation / Detection High-Byte Reg-
ister
ARB23 ARB22 ARB21 ARB20 ARB19 ARB18 ARB17 ARB16 P 79
015 IBL - Inband Loopback Control
Register
- - IBGL1 IBGL0 IBAL1 IBAL0 IBDL1 IBDL0 P 80
016 IBG - Inband Loopback Genera-
tion Code Definition Register
IBG7 IBG6 IBG5 IBG4 IBG3 IBG2 IBG1 IBG0 P 80
017 IBDA - Inband Loopback Detec-
tion Target Activate Code Defini-
tion Register
IBA7 IBA6 IBA5 IBA4 IBA3 IBA2 IBA1 IBA0 P 81
018 IBDD - Inband Loopback Detec-
tion Target Deactivate Code
Definition Register
IBD7 IBD6 IBD5 IBD4 IBD3 IBD2 IBD1 IBD0 P 81
019 LOOP - Loopback Control Reg-
ister
- - - - AUTOLP DLP RLP ALP P 82
Interrupt Edge Selection
01A INTES - Interrupt Trigger Edges
Select Register
- AIS_IES PA_IES TOC_IES TCKLOS_I
ES
TLOS_IES LOS_IES IB_IES P 83
Interrupt Mask
01B INTM0 - Interrupt Mask Register
0
DAC_IM TJA_IM RJA_IM TOC_IM TCKLOS_I
M
TLOS_IM SLOS_IM LLOS_IM P 84
01C INTM1 - Interrupt Mask Register
1
SAIS_IM LAIS_IM PA_IM - - - IBA_IM IBD_IM P 85
01D INTM2 - Interrupt Mask Register
2
- - SBPV_IM LBPV_IM SEXZ_IM LEXZ_IM ERR_IM CNTOV_IM P 86
Status Indication
01E STAT0 - Status Register 0 AUTOLP_S - - TOC_S TCKLOS_S TLOS_S SLOS_S LLOS_S P 87
01F STAT1 - Status Register 1 SAIS_S LAIS_S PA_S - - - IBA_S IBD_S P 88
Interrupt Status Indication
020 INTS0 - Interrupt Status Regis-
ter 0
DAC_IS TJA_IS RJA_IS TOC_IS TCKLOS_I
S
TLOS_IS SLOS_IS LLOS_IS P 89
021 INTS1 - Interrupt Status Regis-
ter 1
SAIS_IS LAIS_IS PA_IS - - - IBA_IS IBD_IS P 90
022 INTS2 - Interrupt Status Regis-
ter 2
- - SBPV_IS LBPV_IS SEXZ_IS LEXZ_IS ERR_IS CNTOV_IS P 91
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 59 December 17, 2009
Counter
023 ERRCL - Error Counter Low-
Byte Register
ERRC7 ERRC6 ERRC5 ERRC4 ERRC3 ERRC2 ERRC1 ERRC0 P 92
024 ERRCH - Error Counter High-
Byte Register
ERRC15 ERRC14 ERRC13 ERRC12 ERRC11 ERRC10 ERRC9 ERRC8 P 92
Jitter Measurement (channel 0 Only)
7E5 JM - Jitter Measurement Config-
uration For Channel 0 Register
- - - - - JM_STOP JM_MD JM_BW P 93
7E6 JIT_PL - Positive Peak Jitter
Measurement Low-Byte Regis-
ter
JIT_P7 JIT_P6 JIT_P5 JIT_P4 JIT_P3 JIT_P2 JIT_P1 JIT_P0 P 93
7E7 JIT_PH - Positive Peak Jitter
Measurement High-Byte Regis-
ter
- - - - JIT_P11 JIT_P10 JIT_P9 JIT_P8 P 93
7E8 JIT_NL - Negative Peak Jitter
Measurement Low-Byte Regis-
ter
JIT_N7 JIT_N6 JIT_N5 JIT_N4 JIT_N3 JIT_N2 JIT_N1 JIT_N0 P 94
7E9 JIT_NH - Negative Peak Jitter
Measurement High-Byte Regis-
ter
- - - - JIT_N11 JIT_N10 JIT_N9 JIT_N8 P 94
Address
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference
Page
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 60 December 17, 2009
5.2 REGISTER DESCRIPTION
5.2.1 GLOBAL REGISTER
ID - Device ID Register
RST - Global Reset Register
Address: 000H
Type: Read
Default Value: 7xH
Bit Name Description
7 - 0 ID[7:0] The ID[7:0] bits are pre-set, where the ID[3:0] bits ‘x’ represent the current version number (‘0000’ is for the first version).
Address: 040H
Type: Write
Default Value: 00H
Bit Name Description
7 - 0 RST[7:0] Writing this register will initiate global software reset. This reset completes in 1 µs maximum.
76543210
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
76543210
RST7 RST6 RST5 RST4 RST3 RST2 RST1 RST0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 61 December 17, 2009
GCF - Global Configuration Register
MON - G.772 Monitor Configuration Register
Address: 080H
Type: Read / Write
Default Value: 03H
Bit Name Description
7 - 5 - Reserved.
4 COPY When the per-channel register of one channel is written, this bit determines whether the written value is copied to the same reg-
ister of the other channels simultaneously.
0: Disable. (default)
1: Enable.
3 - 2 INT_PIN[1:0] These two bits control the output on the INT pin.
X0: Open drain, active low. (default)
01: Push-pull, active low.
11: Push-pull, active high.
1 GLB_IM This bit is a global configuration interrupt mask bit.
0: The per-channel interrupt will be generated when the per-channel interrupt mask bit is ‘0’ and the corresponding interrupt sta-
tus bit is ‘1’.
1: Mask all the per-channel interrupts. None per-channel interrupts can be generated. (default)
0 TMOV_IM This bit controls whether the interrupt is generated when one second time is over. This one second timer is locked to MCLK.
0: Enable.
1: Mask. (default)
Address: 0C0H
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 6 - Reserved.
5 - 0 MON[5:0] These bits determine whether the G.772 Monitor is implemented. When the G.772 Monitor is implemented, these bits select one
transmitter or receiver to be monitored by channel 0.
000000: No transmitter or receiver is monitored. (default)
000001: The receiver of channel 1 is monitored.
000010: The receiver of channel 2 is monitored.
......
001111: The receiver of channel 15 is monitored.
010000: The receiver of channel 16 is monitored.
010001 ~ 011111: Reserved.
100000: No transmitter or receiver is monitored.
100001: The transmitter of channel 1 is monitored.
100010: The transmitter of channel 2 is monitored.
......
101111: The transmitter of channel 15 is monitored.
110000 ~ 111111: Reserved.
76543210
- - - COPY INT_PIN1 INT_PIN0 GLB_IM TMOV_IM
76543210
- - MON5 MON4 MON3 MON2 MON1 MON0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 62 December 17, 2009
GPIO - General Purpose I/O Pin Definition Register
Address: 100H
Type: Read / Write
Default Value: 0FH
Bit Name Description
7 - 4 - Reserved.
3 LEVEL1 When the GPIO1 pin is defined as output, this bit determines the output level on GPIO1 and can be read and written.
0: Output low level.
1: Output high level. (default)
When the GPIO1 pin is defined as input, this bit indicates the input level on GPIO1 and can only be read.
0: Input low level.
1: Input high level. (default)
2 LEVEL0 When the GPIO0 pin is defined as output, this bit determines the output level on GPIO0 and can be read and written.
0: Output low level.
1: Output high level.
When the GPIO0 pin is defined as input, this bit indicates the input level on GPIO0 and can only be read.
0: Input low level.
1: Input high level. (default)
1 DIR1 This bit determines whether the GPIO1 pin is used as output or input.
0: Output.
1: Input. (default)
0 DIR0 This bit determines whether the GPIO0 pin is used as output or input.
0: Output.
1: Input. (default)
76543 2 1 0
- - - - LEVEL1 LEVEL0 DIR1 DIR0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 63 December 17, 2009
CLKG - CLKT1 & CLKE1 Generation Control Register
INTCH1 - Interrupt Requisition Source Register 1
Address: 1C0H
Type: Read / Write
Default Value: 0FH
Bit Name Description
7 - 4 - Reserved.
3 CLKE1_EN This bit controls whether the output on the CLKE1 pin is enabled.
0: The output is disabled. CLKE1 is in High-Z state.
1: The output is enabled. The frequency of CLKE1 is determined by the CLKE1 bit (b2, CLKG). (default)
2 CLKE1 This bit is valid only when the CLKE1_EN bit (b3, CLKG) is ‘1’. This bit selects the clock frequency output on the CLKE1 pin.
0: 8 KHz.
1: 2.048 MHz. (default)
1 CLKT1_EN This bit controls whether the output on the CLKT1 pin is enabled.
0: The output is disabled. CLKT1 is in High-Z state.
1: The output is enabled. The frequency of CLKT1 is determined by the CLKT1 bit (b0, CLKG). (default)
0 CLKT1 This bit is valid only when the CLKT1_EN bit (b1, CLKG) is ‘1’. This bit selects the clock frequency output on the CLKT1 pin.
0: 8 KHz.
1: 1.544 MHz. (default)
Address: 2C0H
Type: Read
Default Value: 00H
Bit Name Description
7 - 0 INT_CH[8:1] These bits indicate whether there is an interrupt generated in the corresponding channel. The INT_CH[8:1] bits correspond to
channel 8 to 1 respectively.
0: No interrupt is generated or all the interrupts are cleared in the corresponding channel. (default)
1: At least one interrupt is generated in the corresponding channel.
76543210
- - - - CLKE1_EN CLKE1 CLKT1_EN CLKT1
76543210
INT_CH8 INT_CH7 INT_CH6 INT_CH5 INT_CH4 INT_CH3 INT_CH2 INT_CH1
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 64 December 17, 2009
INTCH2 - Interrupt Requisition Source Register 2
INTCH3 - Interrupt Requisition Source Register 3
INTTM - One Second Timer Interrupt Status Register
Address: 300H
Type: Read
Default Value: 00H
Bit Name Description
7-Reserved.
6 - 0 INT_CH[15:9] These bits indicate whether there is an interrupt generated in the corresponding channel. The INT_CH[16:9] bits correspond to
channel 16 to 9 respectively.
0: No interrupt is generated or all the interrupts are cleared in the corresponding channel. (default)
1: At least one interrupt is generated in the corresponding channel.
Address: 380H
Type: Read
Default Value: 00H
Bit Name Description
7 INT_CH0 This bit indicates whether there is an interrupt generated in channel 0.
0: No interrupt is generated or all the interrupts are cleared in channel 0. (default)
1: At least one interrupt is generated in channel 0.
6 - 0 - Reserved.
Address: 3C0H
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 1 - Reserved.
0 TMOV_IS This bit is valid only when the TMOV_IM bit (b0, GCF) is ‘0’. This bit indicates the interrupt status of one second time over.
0: No one second time over interrupt is generated; or a ‘1’ is written to this bit. (default)
1: One second time over interrupt is generated and is reported by the INT pin.
76543210
- INT_CH15 INT_CH14 INT_CH13 INT_CH12 INT_CH11 INT_CH10 INT_CH9
76543210
INT_CH0-------
76543210
-------TMOV_IS
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 65 December 17, 2009
5.2.2 PER-CHANNEL REGISTER
CHCF - Channel Configuration Register
TJA - Transmit Jitter Attenuation Configuration Register
Address: 001H, 041H, 081H, 0C1H, 101H, 141H, 181H, 1C1H, (CH1~CH8)
201H, 241H, 281H, 2C1H, 301H, 341H, 381H, (CH9~CH15)
7C1H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 2 - Reserved.
1 CHRST Writing a ‘1’ to this bit will initiate per-channel software reset. Once initiated, per-channel software reset completes in 1 µs maxi-
mum.
This bit is self cleared.
0 T1E1 This bit is valid only when the TEHWE pin is low. This bit selects T1/J1 or E1 operation mode.
0: T1/J1. (default)
1: E1.
This bit can not be reset by per-channel software reset.
Address: 002H, 042H, 082H, 0C2H, 102H, 142H, 182H, 1C2H, (CH1~CH8)
202H, 242H, 282H, 2C2H, 302H, 342H, 382H, (CH9~CH15)
7C2H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 5 - Reserved.
4 TJA_LIMT This bit determines whether the JA-Limit function is enabled in the TJA.
0: Disable. (default)
1: Enable. The speed of the TJA outgoing data will be adjusted automatically if the FIFO in the TJA is 2-bit close to its full or emp-
tiness.
3 TJA_EN This bit controls whether the TJA is enabled to use.
0: Disable. (default)
1: Enable.
2 - 1 TJA_DP[1:0] These bits select the depth of the TJA FIFO.
00: 128-bit. (default)
01: 64-bit.
1X: 32-bit.
0 TJA_BW This bit selects the Corner Frequency for the TJA.
0: 5 Hz (in T1/J1 mode) / 6.77 Hz (in E1 mode). (default)
1: 1.26 Hz (in T1/J1 mode) / 0.87 Hz (in E1 mode).
765432 1 0
----- -CHRSTT1E1
76543210
- - - TJA_LIMT TJA_EN TJA_DP1 TJA_DP0 TJA_BW
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 66 December 17, 2009
RJA - Receive Jitter Attenuation Configuration Register
Address: 003H, 043H, 083H, 0C3H, 103H, 143H, 183H, 1C3H, (CH1~CH8)
203H, 243H, 283H, 2C3H, 303H, 343H, 383H, (CH9~CH15)
7C3H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 5 - Reserved.
4 RJA_LIMT This bit determines whether the JA-Limit function is enabled in the RJA.
0: Disable. (default)
1: Enable. The speed of the RJA outgoing data will be adjusted automatically if the FIFO in the RJA is 2-bit close to its full or
emptiness.
3 RJA_EN This bit controls whether the RJA is enabled to use.
0: Disable. (default)
1: Enable.
2 - 1 RJA_DP[1:0] These bits select the depth of the RJA FIFO.
00: 128-bit. (default)
01: 64-bit.
1X: 32-bit.
0 RJA_BW This bit selects the Corner Frequency for the RJA.
0: 5 Hz (in T1/J1 mode) / 6.77 Hz (in E1 mode). (default)
1: 1.26 Hz (in T1/J1 mode) / 0.87 Hz (in E1 mode).
76543210
- - - RJA_LIMT RJA_EN RJA_DP1 RJA_DP0 RJA_BW
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 67 December 17, 2009
TCF0 - Transmit Configuration Register 0
Address: 004H, 044H, 084H, 0C4H, 104H, 144H, 184H, 1C4H, (CH1~CH8)
204H, 244H, 284H, 2C4H, 304H, 344H, 384H, (CH9~CH15)
7C4H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7-Reserved.
6 OE This bit determines the output of the Line Driver, i.e., the output on the TTIPn and TRINGn pins.
0: High-Z. (default)
1: Normal operation.
5 T_OFF This bit determines whether the transmitter is powered down.
0: Normal operation. (default)
1: Power down.
4 THZ_OC This bit determines the output of the Line Driver, i.e., the output on the TTIPn and TRINGn pins when TOC is detected.
0: The output current is limited to 100 mAp-p. (default)
1: The output current is limited to 100 mAp-p within the first 1 ms after the TOC is detected and then the output is in High-Z state
when the TOC is detected for more than 1 ms.
3 T_SING This bit determines the transmit line interface.
0: Transmit Differential line interface. Both TTIPn and TRINGn are used to transmit signal to the line side. (default)
1: Transmit Single Ended line interface. Only TTIPn is used to transmit signal. TRINGn should be left open.
2 - 0 T_TERM[2:0] These bits select the impedance matching mode of the transmit path to match the cable impedance.
000: The 100 Ω internal impedance matching is selected for T1 100 Ω twisted pair cable (with transformer). (default)
001: The 110 Ω internal impedance matching is selected for J1 110 Ω twisted pair cable (with transformer).
010: The 120 Ω internal impedance matching is selected for E1 120 Ω twisted pair cable (with transformer).
011: The 75 Ω internal impedance matching is selected for E1 75 Ω coaxial cable (with transformer).
100: The 100 Ω internal impedance matching is selected for T1 100 Ω twisted pair cable (transformer-less).
101: The 110 Ω internal impedance matching is selected for J1 110 Ω twisted pair cable (transformer-less).
110: The 120 Ω internal impedance matching is selected for E1 120 Ω twisted pair cable (transformer-less).
111: The external impedance matching is selected for E1 120 Ω twisted pair cable or E1 75 Ω coaxial cable (with transformer).
76543210
- OE T_OFF THZ_OC T_SING T_TERM2 T_TERM1 T_TERM0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 68 December 17, 2009
TCF1 - Transmit Configuration Register 1
Address: 005H, 045H, 085H, 0C5H, 105H, 145H, 185H, 1C5H, (CH1~CH8)
205H, 245H, 285H, 2C5H, 305H, 345H, 385H, (CH9~CH15)
7C5H (CH0)
Type: Read / Write
Default Value: 01H
Bit Name Description
7 - 5 - Reserved.
4 TCK_ES This bit selects the active edge of the TCLKn pin.
0: Falling edge. (default)
1: Rising edge.
3 TD_INV This bit determines the active level on the TDn, TDPn and TDNn pins.
0: Active high. (default)
1: Active low.
2 T_CODE This bit selects the line code rule for the transmit path.
0: B8ZS (in T1/J1 mode) / HDB3 (in E1 mode). (default)
1: AMI.
1 - 0 T_MD[1:0] These bits determines the transmit system interface.
00: Transmit Single Rail NRZ Format system interface. The data is input on TDn in NRZ format and a 1.544 MHz (in T1/J1 mode)
or 2.048 MHz (in E1 mode) clock is input on TCLKn.
01: Transmit Dual Rail NRZ Format system interface. The data is input on TDPn and TDNn in NRZ format and a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) clock is input on TCLKn. (default)
10: Transmit Dual Rail RZ Format system interface. The data is input on TDPn and TDNn in RZ format.
11: Reserved.
76543210
- - - TCK_ES TD_INV T_CODE T_MD1 T_MD0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 69 December 17, 2009
PULS - Transmit Pulse Configuration Register
Address: 006H, 046H, 086H, 0C6H, 106H, 146H, 186H, 1C6H, (CH1~CH8)
206H, 246H, 286H, 2C6H, 306H, 346H, 386H, (CH9~CH15)
7C6H (CH0)
Type: Read / Write
Default Value: 02H
Bit Name Description
7 - 4 - Reserved.
3 - 0 PULS[3:0] These bits select one of the eight preset waveform templates for short haul application or enable user-programmable arbitrary
waveform.
76543210
----PULS3PULS2PULS1PULS0
PULS[3:0] Operation
Mode
Transmit
Clock Cable Impedance Cable Range Cable Loss
0000 E1 2.048 MHz E1 75 Ω- 0 ~ 12 dB
0001 E1 2.048 MHz E1 120 Ω- 0 ~ 12 dB
0010 (default) DSX1 1.544 MHz 100 Ω0 ~ 133 ft 0 ~ 0.6 dB
0011 DSX1 1.544 MHz 100 Ω133 ~ 266 ft 0.6 ~ 1.2 dB
0100 DSX1 1.544 MHz 100 Ω266 ~ 399 ft 1.2 ~ 1.8 dB
0101 DSX1 1.544 MHz 100 Ω399 ~ 533 ft 1.8 ~ 2.4 dB
0110 DSX1 1.544 MHz 100 Ω533 ~ 655 ft 2.4 ~ 3.0 dB
0111 J1 1.544 MHz 110 Ω- 0 ~ 12 dB
1XXX User-programmable arbitrary waveform
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 70 December 17, 2009
SCAL - Amplitude Scaling Control Register
AWG0 - Arbitrary Waveform Generation Control Register 0
Address: 007H, 047H, 087H, 0C7H, 107H, 147H, 187H, 1C7H, (CH1~CH8)
207H, 247H, 287H, 2C7H, 307H, 347H, 387H, (CH9~CH15)
7C7H (CH0)
Type: Read / Write
Default Value: 36H
Bit Name Description
7 - 6 - Reserved.
5 - 0 SCAL[5:0] These bits specify a scaling factor to be applied to the amplitude of the waveform to be transmitted.
In T1/J1 mode, the standard value is ‘110110’ for the waveform amplitude. If necessary, increasing or decreasing by ‘1’ from the
standard value will result in 2% scaling up or down against the waveform amplitude. The scale range is from +20% to -100%.
In E1 mode, the standard value is ‘100001’ for the waveform amplitude. If necessary, increasing or decreasing by ‘1’ from the
standard value will result in 3% scaling up or down against the waveform amplitude. The scale range is from +100% to -100%.
Note: The default value for SCAL[5:0] is ‘110110’ which is the T1/J1 standard value. Therefore, if E1 mode is used, ‘100001’
should be written to these bits to indicate the E1 standard value.
Address: 008H, 048H, 088H, 0C8H, 108H, 148H, 188H, 1C8H, (CH1~CH8)
208H, 248H, 288H, 2C8H, 308H, 348H, 388H, (CH9~CH15)
7C8H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7-Reserved.
6 DONE This bit is valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...) are set
to ‘1XXX’). This bit determines whether to enable the data writing/reading from RAM.
0: Disable. (default)
1: Enable.
5 RW This bit is valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...) are set
to ‘1XXX’). This bit determines read/write direction.
0: Write data to RAM. (default)
1: Read data from RAM.
4 - 0 SAMP[4:0] These bits are valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...)
are set to ‘1XXX’). These bits specify the RAM sample address.
00000: The RAM sample address is 0. (default)
00001: The RAM sample address is 1.
00010: The RAM sample address is 2.
......
10001: The RAM sample address is 17.
10010: The RAM sample address is 18.
10011 ~ 11111: The RAM sample address is 19.
76543210
- - SCAL5 SCAL4 SCAL3 SCAL2 SCAL1 SCAL0
76543210
- DONE RW SAMP4 SAMP3 SAMP2 SAMP1 SAMP0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 71 December 17, 2009
AWG1 - Arbitrary Waveform Generation Control Register 1
Address: 009H, 049H, 089H, 0C9H, 109H, 149H, 189H, 1C9H, (CH1~CH8)
209H, 249H, 289H, 2C9H, 309H, 349H, 389H, (CH9~CH15)
7C9H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7-Reserved.
6 - 0 WDAT[6:0] These bits are valid only when the user-programmable arbitrary waveform is enabled (i.e., the PULS[3:0] bits (b3~0, PULS,...)
are set to ‘1XXX’).
These bits contain the template sample data to be stored in RAM which address is specified by the SAMP[4:0] bits (b4~0,
AWG0,...). They are not updated until new template sample data is written.
76543210
- WDAT6 WDAT5 WDAT4 WDAT3 WDAT2 WDAT1 WDAT0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 72 December 17, 2009
RCF0 - Receive Configuration Register 0
Address: 00AH, 04AH, 08AH, 0CAH, 10AH, 14AH, 18AH, 1CAH, (CH1~CH8)
20AH, 24AH, 28AH, 2CAH, 30AH, 34AH, 38AH, (CH9~CH15)
7CAH (CH0)
Type: Read / Write
Default Value: 47H
Bit Name Description
7 RCKH This bit determines the output on RCLKn when LLOS is detected. This bit is valid only when LLOS is detected and the AIS and
pattern generation is disabled in the receive path.
0: XCLK. (default)
1: High level.
6 RHZ This bit determines the output of all receive system interfaced pins (including RDPn, RDNn and RCLKn) when the corresponding
receiver is powered down.
0: Low level.
1: High-Z. (default)
5 R_OFF This bit determines whether the receiver is powered down.
0: Normal operation. (default)
1: Power down.
4 R120IN This bit is valid only when the receive line interface is in Receive Differential mode and per-channel internal impedance matching
configuration is enabled. This bit selects the internal impedance matching mode.
0: Partially Internal Impedance Matching mode. An internal programmable resistor (IM) and a value-fixed external resistor (Rr)
are used. (default)
1: Fully Internal Impedance Matching mode. Only an internal programmable resistor (IM) is used.
3 R_SING This bit determines the receive line interface.
0: Receive Differential line interface. Both RTIPn and RRINGn are used to receive signal from the line side. (default)
2 - 0 R_TERM[2:0] These bits are valid only when impedance matching is configured on a per-channel basis. These bits select the impedance
matching mode of the receive path to match the cable impedance.
In Receive Differential mode:
000: The 100 Ω internal impedance matching is selected for T1 100 Ω twisted pair cable.
001: The 110 Ω internal impedance matching is selected for J1 110 Ω twisted pair cable.
010: The 120 Ω internal impedance matching is selected for E1 120 Ω twisted pair cable.
011: The 75 Ω internal impedance matching is selected for E1 75 Ω coaxial cable.
1XX: External impedance matching is selected for T1 100 Ω, J1 110 Ω, E1 120 Ω twisted pair cable and E1 75 Ω coaxial cable.
In Receive Single Ended mode, only External Impedance Matching is supported and the setting of these bits is a don’t-care.
(default)
76543210
RCKH RHZ R_OFF R120IN R_SING R_TERM2 R_TERM1 R_TERM0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 73 December 17, 2009
RCF1 - Receive Configuration Register 1
RCF2 - Receive Configuration Register 2
Address: 00BH, 04BH, 08BH, 0CBH, 10BH, 14BH, 18BH, 1CBH, (CH1~CH8)
20BH, 24BH, 28BH, 2CBH, 30BH, 34BH, 38BH, (CH9~CH15)
7CBH (CH0)
Type: Read / Write
Default Value: 01H
Bit Name Description
7 - 5 - Reserved.
4 RCK_ES This bit selects the active edge of the RCLKn pin.
0: Rising edge. (default)
1: Falling edge.
3 RD_INV This bit determines the active level on the RDPn and RDNn pins.
0: Active high. (default)
1: Active low.
2 R_CODE This bit selects the line code rule for the receive path.
0: B8ZS (in T1/J1 mode) / HDB3 (in E1 mode). (default)
1: AMI.
1 - 0 R_MD[1:0] These bits determines the receive system interface.
01: Receive Dual Rail NRZ Format system interface. The data is output on RDPn and RDNn in NRZ format and a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn. (default)
10: Receive Dual Rail RZ Format system interface. The data is output on RDPn and RDNn in RZ format and a 1.544 MHz (in T1/
J1 mode) or 2.048 MHz (in E1 mode) recovered clock is output on RCLKn.
11: Receive Dual Rail Sliced system interface. The data is output on RDPn and RDNn in RZ format directly after passing through
the Slicer.
Address: 00CH, 04CH, 08CH, 0CCH, 10CH, 14CH, 18CH, 1CCH, (CH1~CH8)
20CH, 24CH, 28CH, 2CCH, 30CH, 34CH, 38CH, (CH9~CH15)
7CCH (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 2 - Reserved.
1 - 0 MG[1:0] These bits select the Monitor Gain.
00: 0 dB. (default)
01: 20 dB.
10: 26 dB.
11: 32 dB.
76543210
- - - RCK_ES RD_INV R_CODE R_MD1 R_MD0
76543210
------MG1MG0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 74 December 17, 2009
LOS - LOS Configuration Register
Address: 00DH, 04DH, 08DH, 0CDH, 10DH, 14DH, 18DH, 1CDH, (CH1~CH8)
20DH, 24DH, 28DH, 2CDH, 30DH, 34DH, 38DH, (CH9~CH15)
7CDH (CH0)
Type: Read / Write
Default Value: 15H
Bit Name Description
7 LAC This bit selects the LLOS, SLOS and AIS criteria.
0: T1.231 (in T1/J1 mode) / G.775 (in E1 mode). (default)
1: I.431 (in T1/J1 mode) / ETSI 300233 & I.431 (in E1 mode).
6 - 4 ALOS[2:0] These bits select the amplitude threshold (Q). When the amplitude of the data is less than Q Vpp for N consecutive pulse inter-
vals, LLOS is declared. The consecutive pulse intervals (N) are determined by the LAC bit (b7, LOS,...).
The ALOS[2:0] settings for Normal Receive mode and Line Monitor mode are different. Refer to below tables.
3 - 2 TALOS[1:0] These bits select the amplitude threshold. When the amplitude of the data is less than the threshold for a certain period, TLOS is
declared. The period is determined by the TDLOS bits (b1~0, LOS,...). When the amplitude of a pulse is above the threshold,
TLOS is cleared.
For Differential line interface:
00: 1.2 Vp.
01: 0.9 Vp. (default)
10: 0.6 Vp.
11: 0.4 Vp.
For Single Ended line interface:
00: 0.61 Vp.
01: 0.48 Vp. (default)
10: 0.32 Vp.
11: 0.24 Vp.
76543210
LAC ALOS2 ALOS1 ALOS0 TALOS1 TALOS0 TDLOS1 TDLOS0
ALOS[2:0] Setting in Normal Receive Mode
ALOS[2:0] Q (Vpp) vs. 6.0 Vpp (dB) vs. 4.74 Vpp (dB)
000 0.5 21.58 19.54
001 (default) 0.7 18.66 16.61
010 0.9 16.48 14.43
011 1.2 13.98 11.93
100 1.4 12.64 10.59
101 1.6 11.48 9.43
110 1.8 10.46 8.41
111 2.0 9.54 7.49
ALOS[2:0] Setting in Line Monitor Mode
ALOS[2:0] Q (Vpp) vs. 6.0 Vpp (dB) vs. 4.74 Vpp (dB)
000 1.0 15.56 13.52
001 (default) 1.4 12.64 10.59
010 1.8 10.46 8.41
011 2.2 8.71 6.67
1xx reserved.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 75 December 17, 2009
ERR - Error Detection & Insertion Control Register
1 - 0 TDLOS[1:0] These bits select the period. When the amplitude of the data is less than a certain voltage for the period, TLOS is declared. The
voltage is determined by the TALOS bits (b3~2, LOS,...).
00: 16-pulse.
01: 32-pulse. (default)
1X: 64-pulse.
Address: 00EH, 04EH, 08EH, 0CEH, 10EH, 14EH, 18EH, 1CEH, (CH1~CH8)
20EH, 24EH, 28EH, 2CEH, 30EH, 34EH, 38EH, (CH9~CH15)
7CEH (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 EXZ_DEF This bit selects the EXZ definition standard.
0: ANSI. (default)
1: FCC.
6 BPV_INS This bit controls whether to insert a bipolar violation (BPV) to the transmit path.
Writing ‘1’ to this bit will insert a BPV on the next available mark in the data stream to be transmitted.
This bit is cleared once the BPV insertion is completed.
5 ERR_INS This bit controls whether to insert a single bit error to the generated PRBS/ARB pattern.
A transition from ‘0’ to ‘1’ on this bit will insert a single bit error to the generated PRBS/ARB pattern.
This bit is cleared once the single bit error insertion is completed.
4 - 2 CNT_SEL[2:0] These bits select what kind of error to be counted by the internal Error Counter.
000: Disable. (default)
001: LBPV.
010: LEXZ.
011: LBPV + LEXZ.
100: SBPV.
101: SEXZ.
110: SBPV + SEXZ.
111: PRBS/ARB error.
1 CNT_MD This bit determines whether the ERRCH & ERRCL registers are updated automatically or manually.
0: Manually by setting the CNT_STOP bit (b0, ERR,...). (default)
1: Every-one second automatically.
0 CNT_STOP This bit is valid only when the CNT_MD bit (b1, ERR,...) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit updates the ERRCH & ERRCL registers.
This bit must be cleared before the next round.
76543210
EXZ_DEF BPV_INS ERR_INS CNT_SEL2 CNT_SEL1 CNT_SEL0 CNT_MD CNT_STOP
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 76 December 17, 2009
AISG - AIS Generation Control Register
Address: 00FH, 04FH, 08FH, 0CFH, 10FH, 14FH, 18FH, 1CFH, (CH1~CH8)
20FH, 24FH, 28FH, 2CFH, 30FH, 34FH, 38FH, (CH9~CH15)
7CFH (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 5 - Reserved.
4 TXAIS This bit controls the transmission of AIS in the transmit path.
0: Disable. (default)
1: Transmit all ones pattern at TTIPn/TRINGn.
In remote loopback, this bit is ignored.
3 ASAIS_SLOS This bit controls the AIS generation in the receive path once SLOS is detected.
0: Disable. (default)
1: Enable.
2 ASAIS_LLOS This bit controls the AIS generation in the receive path once LLOS is detected.
0: Disable. (default)
1: Enable.
1 ALAIS_SLOS This bit controls the AIS generation in the transmit path once SLOS is detected.
0: Disable. (default)
1: Enable.
0 ALAIS_LLOS This bit controls the AIS generation in the transmit path once LLOS is detected.
0: Disable. (default)
1: Enable.
76543210
- - - TXAIS ASAIS_SLOS ASAIS_LLOS ALAIS_SLOS ALAIS_LLOS
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 77 December 17, 2009
PG - Pattern Generation Control Register
Address: 010H, 050H, 090H, 0D0H, 110H, 150H, 190H, 1D0H, (CH1~CH8)
210H, 250H, 290H, 2D0H, 310H, 350H, 390H, (CH9~CH15)
7D0H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7-Reserved.
6 PG_CK This bit selects the reference clock when the pattern (including PRBS, ARB & IB) is generated.
When the pattern is generated in the receive path:
0: XCLK. (default)
1: Recovered clock from the received signal.
When the pattern is generated in the transmit path:
0: XCLK. (default)
1: Transmit clock, i.e., the clock input on TCLKn (in Transmit Single Rail NRZ Format mode and in Transmit Dual Rail NRZ For-
mat mode) or the clock recovered from the data input on TDPn and TDNn (in Transmit Dual Rail RZ Format mode)
5 - 4 PG_EN[1:0] These bits select the pattern to be generated.
00: Disable. (default)
01: PRBS.
10: ARB.
11: IB.
3 PG_POS This bit selects the pattern (including PRBS, ARB & IB) generation direction.
0: Transmit path. (default)
1: Receive path.
2 PAG_INV This bit controls whether to invert the generated PRBS/ARB pattern.
0: Normal. (default)
1: Invert.
1 - 0 PRBG_SEL[1:0] These bits are valid only when the PRBS pattern is generated. They select the PRBS pattern.
00: 220 - 1 QRSS. (default)
01: 215 - 1 PRBS.
1X: 211 - 1 PRBS.
76543210
- PG_CK PG_EN1 PG_EN0 PG_POS PAG_INV PRBG_SEL1 PRBG_SEL0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 78 December 17, 2009
PD - Pattern Detection Control Register
Address: 011H, 051H, 091H, 0D1H, 111H, 151H, 191H, 1D1H, (CH1~CH8)
211H, 251H, 291H, 2D1H, 311H, 351H, 391H, (CH9~CH15)
7D1H (CH0)
Type: Read / Write
Default Value: 03H
Bit Name Description
7 - 4 - Reserved.
3 PD_POS This bit selects the pattern (including PRBS, ARB & IB) detection direction.
0: Receive path. (default)
1: Transmit path.
2 PAD_INV This bit controls whether to invert the data before PRBS/ARB detection.
0: Normal. (default)
1: Invert.
1 - 0 PAD_SEL[1:0] These bits select the desired PRBS/ARB pattern to be detected.
00: 220 - 1 QRSS.
01: 215 - 1 PRBS.
10: 211 - 1 PRBS.
11: ARB. (default)
76543210
- - - - PD_POS PAD_INV PAD_SEL1 PAD_SEL0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 79 December 17, 2009
ARBL - Arbitrary Pattern Generation / Detection Low-Byte Register
ARBM - Arbitrary Pattern Generation / Detection Middle-Byte Register
ARBH - Arbitrary Pattern Generation / Detection High-Byte Register
Address: 012H, 052H, 092H, 0D2H, 112H, 152H, 192H, 1D2H, (CH1~CH8)
212H, 252H, 292H, 2D2H, 312H, 352H, 392H, (CH9~CH15)
7D2H (CH0)
Type: Read / Write
Default Value: 55H
Bit Name Description
7 - 0 ARB[7:0] These bits, together with the ARB[23:8] bits, define the ARB pattern to be generated or detected. The ARB23 bit is the first bit to
be generated or detected and the ARB0 bit is the last bit to be generated or detected.
Address: 013H, 053H, 093H, 0D3H, 113H, 153H, 193H, 1D3H, (CH1~CH8)
213H, 253H, 293H, 2D3H, 313H, 353H, 393H, (CH9~CH15)
7D3H (CH0)
Type: Read / Write
Default Value: 55H
Bit Name Description
7 - 0 ARB[15:8] (Refer to the description of the ARBL register.)
Address: 014H, 054H, 094H, 0D4H, 114H, 154H, 194H, 1D4H, (CH1~CH8)
214H, 254H, 294H, 2D4H, 314H, 354H, 394H, (CH9~CH15)
7D4H (CH0)
Type: Read / Write
Default Value: 55H
Bit Name Description
7 - 0 ARB[23:16] (Refer to the description of the ARBL register.)
76543210
ARB7 ARB6 ARB5 ARB4 ARB3 ARB2 ARB1 ARB0
76543210
ARB15 ARB14 ARB13 ARB12 ARB11 ARB10 ARB9 ARB8
76543210
ARB23 ARB22 ARB21 ARB20 ARB19 ARB18 ARB17 ARB16
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 80 December 17, 2009
IBL - Inband Loopback Control Register
IBG - Inband Loopback Generation Code Definition Register
Address: 015H, 055H, 095H, 0D5H, 115H, 155H, 195H, 1D5H, (CH1~CH8)
215H, 255H, 295H, 2D5H, 315H, 355H, 395H, (CH9~CH15)
7D5H (CH0)
Type: Read / Write
Default Value: 01H
Bit Name Description
7 - 6 - Reserved.
5 - 4 IBGL[1:0] These bits define the length of the valid IB generation code programmed in the IBG[7:0] bits (b7~0, IBG,...).
00: 5-bit long in the IBG[4:0] bits (b4~0, IBG,...). (default)
01: 6-bit long in the IBG[5:0] bits (b5~0, IBG,...).
10: 7-bit long in the IBG[6:0] bits (b6~0, IBG,...).
11: 8-bit long in the IBG[7:0] bits (b7~0, IBG,...).
3 - 2 IBAL[1:0] These bits define the length of the valid target activate IB detection code programmed in the IBA[7:0] bits (b7~0, IBDA,...).
00: 5-bit long in the IBA[4:0] bits (b4~0, IBDA,...). (default)
01: 6-bit long in the IBA[5:0] bits (b5~0, IBDA,...).
10: 7-bit long in the IBA[6:0] bits (b6~0, IBDA,...).
11: 8-bit long in the IBA[7:0] bits (b7~0, IBDA,...).
1 - 0 IBDL[1:0] These bits define the length of the valid target deactivate IB detection code programmed in the IBD[7:0] bits (b7~0, IBDD,...).
00: 5-bit long in the IBD[4:0] bits (b4~0, IBDD,...).
01: 6-bit long in the IBD[5:0] bits (b5~0, IBDD,...). (default)
10: 7-bit long in the IBD[6:0] bits (b6~0, IBDD,...).
11: 8-bit long in the IBD[7:0] bits (b7~0, IBDD,...).
Address: 016H, 056H, 096H, 0D6H, 116H, 156H, 196H, 1D6H, (CH1~CH8)
216H, 256H, 296H, 2D6H, 316H, 356H, 396H, (CH9~CH15)
7D6H (CH0)
Type: Read / Write
Default Value: 01H
Bit Name Description
7 - 0 IBG[7:0] The IBG[X:0] bits define the content of the IB generation code. The ‘X’ is determined by the IBGL[1:0] bits (b5~4, IBL,...). The
IBG0 bit is the last bit to be generated. The code is generated repeatedly until the IB generation is stopped.
76543210
- - IBGL1 IBGL0 IBAL1 IBAL0 IBDL1 IBDL0
76543210
IBG7 IBG6 IBG5 IBG4 IBG3 IBG2 IBG1 IBG0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 81 December 17, 2009
IBDA - Inband Loopback Detection Target Activate Code Definition Register
IBDD - Inband Loopback Detection Target Deactivate Code Definition Register
Address: 017H, 057H, 097H, 0D7H, 117H, 157H, 197H, 1D7H, (CH1~CH8)
217H, 257H, 297H, 2D7H, 317H, 357H, 397H, (CH9~CH15)
7D7H (CH0)
Type: Read / Write
Default Value: 01H
Bit Name Description
7 - 0 IBA[7:0] The IBA[X:0] bits define the content of the target activate IB detection code. The ‘X’ is determined by the IBAL[1:0] bits (b3~2,
IBL,...). The IBA0 bit is the last bit to be detected.
Address: 018H, 058H, 098H, 0D8H, 118H, 158H, 198H, 1D8H, (CH1~CH8)
218H, 258H, 298H, 2D8H, 318H, 358H, 398H, (CH9~CH15)
7D8H (CH0)
Type: Read / Write
Default Value: 09H
Bit Name Description
7 - 0 IBD[7:0] The IBD[X:0] bits define the content of the target deactivate IB detection code. The ‘X’ is determined by the IBDL[1:0] bits (b1~0,
IBL,...). The IBD0 bit is the last bit to be detected.
76543210
IBA7 IBA6 IBA5 IBA4 IBA3 IBA2 IBA1 IBA0
76543210
IBD7 IBD6 IBD5 IBD4 IBD3 IBD2 IBD1 IBD0
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 82 December 17, 2009
LOOP - Loopback Control Register
Address: 019H, 059H, 099H, 0D9H, 119H, 159H, 199H, 1D9H, (CH1~CH8)
219H, 259H, 299H, 2D9H, 319H, 359H, 399H, (CH9~CH15)
7D9H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 4 - Reserved.
3 AUTOLP This bit determines whether automatic Digital/Remote Loopback is enabled.
0: Automatic Digital/Remote Loopback is disabled. (default)
1: Automatic Digital/Remote Loopback is enabled. The corresponding channel will enter Digital/Remote Loopback when the acti-
vate IB code is detected in the transmit/receive path for more than 5.1 sec.; and will return from Digital/Remote Loopback when
the deactivate IB code is detected in the transmit/receive path for more than 5.1 sec.
2 DLP This bit controls whether Digital Loopback is enabled.
0: Disable. (default)
1: Enable.
1 RLP This bit controls whether Remote Loopback is enabled.
0: Disable. (default)
1: Enable.
0 ALP This bit controls whether Analog Loopback is enabled.
0: Disable. (default)
1: Enable.
76543210
----AUTOLPDLPRLPALP
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 83 December 17, 2009
INTES - Interrupt Trigger Edges Select Register
Address: 01AH, 05AH, 09AH, 0DAH, 11AH, 15AH, 19AH, 1DAH, (CH1~CH8)
21AH, 25AH, 29AH, 2DAH, 31AH, 35AH, 39AH, (CH9~CH15)
7DAH (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7-Reserved.
6 AIS_IES This bit selects the transition edge of the LAIS_S bit (b6, STAT1,...) and the SAIS_S bit (b7, STAT1,...).
0: A transition from ‘0’ to ‘1’ on the LAIS_S bit (b6, STAT1,...) / the SAIS_S bit (b7, STAT1,...) will set the LAIS_IS bit (b6,
INTS1,...) / the SAIS_IS bit (b7, INTS1,...) to ‘1’ respectively. (default)
1: Any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the LAIS_S bit (b6, STAT1,...) / the SAIS_S bit (b7, STAT1,...) will set the
LAIS_IS bit (b6, INTS1,...) / the SAIS_IS bit (b7, INTS1,...) to ‘1’ respectively.
5 PA_IES This bit selects the transition edge of the PA_S bit (b5, STAT1,...).
0: A transition from ‘0’ to ‘1’ on the PA_S bit (b5, STAT1,...) will set the PA_IS bit (b5, INTS1,...) to ‘1’. (default)
1: Any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the PA_S bit (b5, STAT1,...) will set the PA_IS bit (b5, INTS1,...) to ‘1’.
4 TOC_IES This bit selects the transition edge of the TOC_S bit (b4, STAT0,...).
0: A transition from ‘0’ to ‘1’ on the TOC_S bit (b4, STAT0,...) will set the TOC_IS bit (b4, INTS0,...) to ‘1’. (default)
1: Any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the TOC_S bit (b4, STAT0,...) will set the TOC_IS bit (b4, INTS0,...) to ‘1’.
3 TCKLOS_IES This bit selects the transition edge of the TCKLOS_S bit (b3, STAT0,...).
0: A transition from ‘0’ to ‘1’ on the TCKLOS_S bit (b3, STAT0,...) will set the TCKLOS_IS bit (b3, INTS0,...) to ‘1’. (default)
1: Any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the TCKLOS_S bit (b3, STAT0,...) will set the TCKLOS_IS bit (b3, INTS0,...) to
‘1’.
2 TLOS_IES This bit selects the transition edge of the TLOS_S bit (b2, STAT0,...).
0: A transition from ‘0’ to ‘1’ on the TLOS_S bit (b2, STAT0,...) will set the TLOS_IS bit (b2, INTS0,...) to ‘1’. (default)
1: Any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the TLOS_S bit (b2, STAT0,...) will set the TLOS_IS bit (b2, INTS0,...) to ‘1’.
1 LOS_IES This bit selects the transition edge of the LLOS_S bit (b0, STAT0,...) and the SLOS_S bit (b1, STAT0,...).
0: A transition from ‘0’ to ‘1’ on the LLOS_S bit (b0, STAT0,...) / the SLOS_S bit (b1, STAT0,...) will set the LLOS_IS bit (b0,
INTS0,...) / the SLOS_IS bit (b1, INTS0,...) to ‘1’ respectively. (default)
1: Any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the LLOS_S bit (b0, STAT0,...) / the SLOS_S bit (b1, STAT0,...) will set the
LLOS_IS bit (b0, INTS0,...) / the SLOS_IS bit (b1, INTS0,...) to ‘1’ respectively.
0 IB_IES This bit selects the transition edge of the IBA_S bit (b1, STAT1,...) and the IBD_S bit (b0, STAT1,...).
0: A transition from ‘0’ to ‘1’ on the IBA_S bit (b1, STAT1,...) / the IBD_S bit (b0, STAT1,...) will set the IBA_IS bit (b1, INTS1,...) /
the IBD_IS bit (b0, INTS1,...) to ‘1’ respectively. (default)
1: Any transition from ‘0’ to ‘1’ or from ‘1’ to ‘0’ on the IBA_S bit (b1, STAT1,...) / the IBD_S bit (b0, STAT1,...) will set the IBA_IS
bit (b1, INTS1,...) / the IBD_IS bit (b0, INTS1,...) to ‘1’ respectively.
76543210
- AIS_IES PA_IES TOC_IES TCKLOS_IES TLOS_IES LOS_IES IB_IES
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 84 December 17, 2009
INTM0 - Interrupt Mask Register 0
Address: 01BH, 05BH, 09BH, 0DBH, 11BH, 15BH, 19BH, 1DBH, (CH1~CH8)
21BH, 25BH, 29BH, 2DBH, 31BH, 35BH, 39BH, (CH9~CH15)
7DBH (CH0)
Type: Read / Write
Default Value: FFH
Bit Name Description
7 DAC_IM This bit is the waveform amplitude overflow interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
6 TJA_IM This bit is the TJA FIFO overflow and underflow interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
5 RJA_IM This bit is the RJA FIFO overflow and underflow interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
4 TOC_IM This bit is the Line Driver TOC interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
3 TCKLOS_IM This bit is the TCLKn missing interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
2 TLOS_IM This bit is the TLOS interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
1 SLOS_IM This bit is the SLOS interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
0 LLOS_IM This bit is the LLOS interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
76543210
DAC_IM TJA_IM RJA_IM TOC_IM TCKLOS_IM TLOS_IM SLOS_IM LLOS_IM
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 85 December 17, 2009
INTM1 - Interrupt Mask Register 1
Address: 01CH, 05CH, 09CH, 0DCH, 11CH, 15CH, 19CH, 1DCH, (CH1~CH8)
21CH, 25CH, 29CH, 2DCH, 31CH, 35CH, 39CH, (CH9~CH15)
7DCH (CH0)
Type: Read / Write
Default Value: EFH
Bit Name Description
7 SAIS_IM This bit is the SAIS interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
6 LAIS_IM This bit is the LAIS interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
5 PA_IM This bit is the PRBS/ARB pattern synchronization interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
4 - 2 - Reserved.
1 IBA_IM This bit is the activate IB code interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
0 IBD_IM This bit is the deactivate IB code interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
76543210
SAIS_IM LAIS_IM PA_IM - - - IBA_IM IBD_IM
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 86 December 17, 2009
INTM2 - Interrupt Mask Register 2
Address: 01DH, 05DH, 09DH, 0DDH, 11DH, 15DH, 19DH, 1DDH, (CH1~CH8)
21DH, 25DH, 29DH, 2DDH, 31DH, 35DH, 39DH, (CH9~CH15)
7DDH (CH0)
Type: Read / Write
Default Value: 3FH
Bit Name Description
7 - 6 - Reserved.
5 SBPV_IM This bit is the SBPV interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
4 LBPV_IM This bit is the LBPV interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
3 SEXZ_IM This bit is the SEXZ interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
2 LEXZ_IM This bit is the LEXZ interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
1 ERR_IM This bit is the PRBS/ARB error interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
0 CNTOV_IM This bit is the ERRCH and ERRCL registers overflow interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
76543210
- - SBPV_IM LBPV_IM SEXZ_IM LEXZ_IM ERR_IM CNTOV_IM
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 87 December 17, 2009
STAT0 - Status Register 0
Address: 01EH, 05EH, 09EH, 0DEH, 11EH, 15EH, 19EH, 1DEH, (CH1~CH8)
21EH, 25EH, 29EH, 2DEH, 31EH, 35EH, 39EH, (CH9~CH15)
7DEH (CH0)
Type: Read
Default Value: 00H
Bit Name Description
7 AUTOLP_S This bit indicates the automatic Digital/Remote Loopback status.
0: Out of automatic Digital/Remote Loopback. (default)
1: In automatic Digital/Remote Loopback.
6 - 5 - Reserved.
4 TOC_S This bit indicates the TOC status.
0: No TOC is detected. (default)
1: TOC is detected.
3 TCKLOS_S This bit indicates the TCLKn missing status.
0: TCLKn is not missing. (default)
1: TCLKn is missing.
2 TLOS_S This bit indicates the TLOS status.
0: No TLOS is detected. (default)
1: TLOS is detected.
1 SLOS_S This bit indicates the SLOS status.
0: No SLOS is detected. (default)
1: SLOS is detected.
0 LLOS_S This bit indicates the LLOS status.
0: No LLOS is detected. (default)
1: LLOS is detected.
76543210
AUTOLP_S - - TOC_S TCKLOS_S TLOS_S SLOS_S LLOS_S
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 88 December 17, 2009
STAT1 - Status Register 1
Address: 01FH, 05FH, 09FH, 0DFH, 11FH, 15FH, 19FH, 1DFH, (CH1~CH8)
21FH, 25FH, 29FH, 2DFH, 31FH, 35FH, 39FH, (CH9~CH15)
7DFH (CH0)
Type: Read
Default Value: 00H
Bit Name Description
7 SAIS_S This bit indicates the SAIS status.
0: No SAIS is detected. (default)
1: SAIS is detected.
6 LAIS_S This bit indicates the LAIS status.
0: No LAIS is detected. (default)
1: LAIS is detected.
5 PA_S This bit indicates the PRBS/ARB pattern synchronization status.
0: The PRBS/ARB pattern is out of synchronization. (default)
1: The PRBS/ARB pattern is in synchronization.
4 - 2 - Reserved.
1 IBA_S This bit indicates the activate IB code status.
0: No activate IB code is detected. (default)
1: Activate IB code is detected for more than 40 ms when the AUTOLP bit (b3, LOOP,...) is ‘0’ or activate IB code is detected for
more than 5.1 sec. when the AUTOLP bit (b3, LOOP,...) is ‘1’.
0 IBD_S This bit indicates the deactivate IB code status.
0: No deactivate IB code is detected. (default)
1: Deactivate IB code is detected for more than 40 ms (in T1/J1 mode) / 30 ms (in E1 mode) when the AUTOLP bit (b3, LOOP,...)
is ‘0’ or deactivate IB code is detected for more than 5.1 sec. when the AUTOLP bit (b3, LOOP,...) is ‘1’.
76543210
SAIS_S LAIS_S PA_S - - - IBA_S IBD_S
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 89 December 17, 2009
INTS0 - Interrupt Status Register 0
Address: 020H, 060H, 0A0H, 0E0H, 120H, 160H, 1A0H, 1E0H, (CH1~CH8)
220H, 260H, 2A0H, 2E0H, 320H, 360H, 3A0H, (CH9~CH15)
7E0H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 DAC_IS This bit indicates the interrupt status of the waveform amplitude overflow.
0: No waveform amplitude overflow interrupt is generated; or a ‘1’ is written to this bit. (default)
1: Waveform amplitude overflow interrupt is generated and is reported by the INT pin.
6 TJA_IS This bit indicates the interrupt status of the TJA FIFO overflow or underflow.
0: No TJA FIFO overflow or underflow interrupt is generated; or a ‘1’ is written to this bit. (default)
1: TJA FIFO overflow or underflow interrupt is generated and is reported by the INT pin.
5 RJA_IS This bit indicates the interrupt status of the RJA FIFO overflow or underflow.
0: No RJA FIFO overflow or underflow interrupt is generated; or a ‘1’ is written to this bit. (default)
1: RJA FIFO overflow or underflow interrupt is generated and is reported by the INT pin.
4 TOC_IS This bit indicates the interrupt status of the Line Driver TOC.
0: No TOC interrupt is generated; or a ‘1’ is written to this bit. (default)
1: TOC interrupt is generated and is reported by the INT pin. When the TOC_IES bit (b4, INTES,...) is ‘0’, a transition from ‘0’ to
‘1’ on the TOC_S bit (b4, STAT0,...) set this bit to ‘1’; when the TOC_IES bit (b4, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or
from ‘1’ to ‘0’) on the TOC_S bit (b4, STAT0,...) set this bit to ‘1’.
3 TCKLOS_IS This bit indicates the interrupt status of the TCLKn missing.
0: No TCLKn missing interrupt is generated; or a ‘1’ is written to this bit. (default)
1: TCLKn missing interrupt is generated and is reported by the INT pin. When the TCKLOS_IES bit (b3, INTES,...) is ‘0’, a transi-
tion from ‘0’ to ‘1’ on the TCKLOS_S bit (b3, STAT0,...) set this bit to ‘1’; when the TCKLOS_IES bit (b3, INTES,...) is ‘1’, any tran-
sition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TCKLOS_S bit (b3, STAT0,...) set this bit to ‘1’.
2 TLOS_IS This bit indicates the interrupt status of TLOS.
0: No TLOS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: TLOS interrupt is generated and is reported by the INT pin. When the TLOS_IES bit (b2, INTES,...) is ‘0’, a transition from ‘0’
to ‘1’ on the TLOS_S bit (b2, STAT0,...) set this bit to ‘1’; when the TLOS_IES bit (b2, INTES,...) is ‘1’, any transition (from ‘0’ to
‘1’ or from ‘1’ to ‘0’) on the TLOS_S bit (b2, STAT0,...) set this bit to ‘1’.
1 SLOS_IS This bit indicates the interrupt status of the SLOS.
0: No SLOS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: SLOS interrupt is generated and is reported by the INT pin. When the LOS_IES bit (b1, INTES,...) is ‘0’, a transition from ‘0’ to
‘1’ on the SLOS_S bit (b1, STAT0,...) set this bit to ‘1’; when the LOS_IES bit (b1, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or
from ‘1’ to ‘0’) on the SLOS_S bit (b1, STAT0,...) set this bit to ‘1’.
0 LLOS_IS This bit indicates the interrupt status of the LLOS.
0: No LLOS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: LLOS interrupt is generated and is reported by the INT pin. When the LOS_IES bit (b1, INTES,...) is ‘0’, a transition from ‘0’ to
‘1’ on the LLOS_S bit (b0, STAT0,...) set this bit to ‘1’; when the LOS_IES bit (b1, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or
from ‘1’ to ‘0’) on the LLOS_S bit (b0, STAT0,...) set this bit to ‘1’.
76543210
DAC_IS TJA_IS RJA_IS TOC_IS TCKLOS_IS TLOS_IS SLOS_IS LLOS_IS
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 90 December 17, 2009
INTS1 - Interrupt Status Register 1
Address: 021H, 061H, 0A1H, 0E1H, 121H, 161H, 1A1H, 1E1H, (CH1~CH8)
221H, 261H, 2A1H, 2E1H, 321H, 361H, 3A1H, (CH9~CH15)
7E1H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 SAIS_IS This bit indicates the interrupt status of the SAIS.
0: No SAIS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: SAIS interrupt is generated and is reported by the INT pin. When the AIS_IES bit (b6, INTES,...) is ‘0’, a transition from ‘0’ to ‘1’
on the SAIS_S bit (b7, STAT1,...) set this bit to ‘1’; when the AIS_IES bit (b6, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or from
‘1’ to ‘0’) on the SAIS_S bit (b7, STAT1,...) set this bit to ‘1’.
6 LAIS_IS This bit indicates the interrupt status of the LAIS.
0: No LAIS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: LAIS interrupt is generated and is reported by the INT pin. When the AIS_IES bit (b6, INTES,...) is ‘0’, a transition from ‘0’ to ‘1’
on the LAIS_S bit (b6, STAT1,...) set this bit to ‘1’; when the AIS_IES bit (b6, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or from
‘1’ to ‘0’) on the LAIS_S bit (b6, STAT1,...) set this bit to ‘1’.
5 PA_IS This bit indicates the interrupt status of the PRBS/ARB pattern synchronization.
0: No PRBS/ARB pattern synchronization interrupt is generated; or a ‘1’ is written to this bit. (default)
1: PRBS/ARB pattern synchronization interrupt is generated and is reported by the INT pin. When the PA_IES bit (b5, INTES,...)
is ‘0’, a transition from ‘0’ to ‘1’ on the PA_S bit (b5, STAT1,...) set this bit to ‘1’; when the PA_IES bit (b5, INTES,...) is ‘1’, any
transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the PA_S bit (b5, STAT1,...) set this bit to ‘1’.
4 - 2 - Reserved.
1 IBA_IS This bit indicates the interrupt status of the activate IB code.
0: No activate IB code interrupt is generated; or a ‘1’ is written to this bit. (default)
1: Activate IB code interrupt is generated and is reported by the INT pin. When the IB_IES bit (b0, INTES,...) is ‘0’, a transition
from ‘0’ to ‘1’ on the IBA_S bit (b1, STAT1,...) set this bit to ‘1’; when the IB_IES bit (b0, INTES,...) is ‘1’, any transition (from ‘0’ to
‘1’ or from ‘1’ to ‘0’) on the IBA_S bit (b1, STAT1,...) set this bit to ‘1’.
0 IBD_IS This bit indicates the interrupt status of the deactivate IB code.
0: No deactivate IB code interrupt is generated; or a ‘1’ is written to this bit. (default)
1: Deactivate IB code interrupt is generated and is reported by the INT pin. When the IB_IES bit (b0, INTES,...) is ‘0’, a transition
from ‘0’ to ‘1’ on the IBD_S bit (b0, STAT1,...) set this bit to ‘1’; when the IB_IES bit (b0, INTES,...) is ‘1’, any transition (from ‘0’ to
‘1’ or from ‘1’ to ‘0’) on the IBD_S bit (b0, STAT1,...) set this bit to ‘1’.
76543210
SAIS_IS LAIS_IS PA_IS - - - IBA_IS IBD_IS
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 91 December 17, 2009
INTS2 - Interrupt Status Register 2
Address: 022H, 062H, 0A2H, 0E2H, 122H, 162H, 1A2H, 1E2H, (CH1~CH8)
222H, 262H, 2A2H, 2E2H, 322H, 362H, 3A2H, (CH9~CH15)
7E2H (CH0)
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 6 - Reserved.
5 SBPV_IS This bit indicates the interrupt status of the SBPV.
0: No SBPV interrupt is generated; or a ‘1’ is written to this bit. (default)
1: SBPV interrupt is generated and is reported by the INT pin.
4 LBPV_IS This bit indicates the interrupt status of the LBPV.
0: No LBPV interrupt is generated; or a ‘1’ is written to this bit. (default)
1: LBPV interrupt is generated and is reported by the INT pin.
3 SEXZ_IS This bit indicates the interrupt status of the SEXZ.
0: No SEXZ interrupt is generated; or a ‘1’ is written to this bit. (default)
1: SEXZ interrupt is generated and is reported by the INT pin.
2 LEXZ_IS This bit indicates the interrupt status of the LEXZ.
0: No LEXZ interrupt is generated; or a ‘1’ is written to this bit. (default)
1: LEXZ interrupt is generated and is reported by the INT pin.
1 ERR_IS This bit indicates the interrupt status of the PRBS/ARB error.
0: No PRBS/ARB error interrupt is generated; or a ‘1’ is written to this bit. (default)
1: PRBS/ARB error interrupt is generated and is reported by the INT pin.
0 CNTOV_IS This bit indicates the interrupt status of the ERRCH and ERRCL registers overflow.
0: No ERRCH or ERRCL register overflow interrupt is generated; or a ‘1’ is written to this bit. (default)
1: ERRCH and ERRCL registers overflow interrupt is generated and is reported by the INT pin.
76543210
- - SBPV_IS LBPV_IS SEXZ_IS LEXZ_IS ERR_IS CNTOV_IS
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 92 December 17, 2009
ERRCL - Error Counter Low-Byte Register
ERRCH - Error Counter High-Byte Register
Address: 023H, 063H, 0A3H, 0E3H, 123H, 163H, 1A3H, 1E3H, (CH1~CH8)
223H, 263H, 2A3H, 2E3H, 323H, 363H, 3A3H, (CH9~CH15)
7E3H (CH0)
Type: Read
Default Value: 00H
Bit Name Description
7 - 0 ERRC[7:0] These bits, together with the ERRC[15:8] bits, reflect the accumulated error number in the internal Error Counter. They are
updated automatically or manually, as determined by the CNT_MD bit (b1, ERR,...). They should be read in the next round of
error counting; otherwise, they will be overwritten.
Address: 024H, 064H, 0A4H, 0E4H, 124H, 164H, 1A4H, 1E4H, (CH1~CH8)
224H, 264H, 2A4H, 2E4H, 324H, 364H, 3A4H, (CH9~CH15)
7E4H (CH0)
Type: Read
Default Value: 00H
Bit Name Description
7 - 0 ERRC[15:8] (Refer to the description of the ERRCL register.)
76543210
ERRC7 ERRC6 ERRC5 ERRC4 ERRC3 ERRC2 ERRC1 ERRC0
76543210
ERRC15 ERRC14 ERRC13 ERRC12 ERRC11 ERRC10 ERRC9 ERRC8
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 93 December 17, 2009
JM - Jitter Measurement Configuration For Channel 0 Register
JIT_PL - Positive Peak Jitter Measurement Low-Byte Register
JIT_PH - Positive Peak Jitter Measurement High-Byte Register
Address: 7E5H
Type: Read / Write
Default Value: 00H
Bit Name Description
7 - 3 - Reserved.
2 JM_STOP This bit is valid only when the JM_MD bit (b1, JM) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit updates the JIT_PH, JIT_PL and JIT_NH, JIT_NL registers.
This bit must be cleared before the next round.
1 JM_MD This bit selects the jitter measurement period.
0: The period is determined manually by setting the JM_STOP bit (b2, JM). (default)
1: The period is one second automatically.
0 JM_BW This bit selects the bandwidth of the measured jitter.
0: 10 Hz ~ 40 KHz (in T1/J1 mode) / 20 Hz ~ 100 KHz (in E1 mode). (default)
1: 8 KHz ~ 40 KHz (in T1/J1 mode) / 18 KHz ~ 100 KHz (in E1 mode).
Address: 7E6H
Type: Read
Default Value: 00H
Bit Name Description
7 - 0 JIT_P[7:0] These bits, together with the JIT_P[11:8] bits, reflect the greatest positive peak value of the demodulated jitter signal which is
measured by channel 0. They are updated automatically or manually, as determined by the JM_MD bit (b1, JM). They should be
read in the next round of jitter measurement; otherwise, they will be overwritten.
The relationship between the greatest positive peak value and the indication in these bits is:
Positive Peak = [JIT_PH, JIT_PL] / 16 (UIpp)
Address: 7E7H
Type: Read
Default Value: 00H
Bit Name Description
7 - 4 - Reserved.
3 - 0 JIT_P[11:8] (Refer to the description of the JIT_PL register.)
76543 2 1 0
-----JM_STOPJM_MDJM_BW
76543210
JIT_P7 JIT_P6 JIT_P5 JIT_P4 JIT_P3 JIT_P2 JIT_P1 JIT_P0
76543 2 1 0
- - - - JIT_P11 JIT_P10 JIT_P9 JIT_P8
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Programming Information 94 December 17, 2009
JIT_NL - Negative Peak Jitter Measurement Low-Byte Register
JIT_NH - Negative Peak Jitter Measurement High-Byte Register
Address: 7E8H
Type: Read
Default Value: 00H
Bit Name Description
7 - 0 JIT_N[7:0] These bits, together with the JIT_N[11:8] bits, reflect the greatest negative peak value of the demodulated jitter signal which is
measured by channel 0. They are updated automatically or manually, as determined by the JM_MD bit (b1, JM). They should be
read in the next round of jitter measurement; otherwise, they will be overwritten.
The relationship between the greatest negative peak value and the indication in these bits is:
Negative Peak = [JIT_NH, JIT_NL] / 16 (UIpp)
Address: 7E9H
Type: Read
Default Value: 00H
Bit Name Description
7 - 4 - Reserved.
3 - 0 JIT_N[11:8] (Refer to the description of the JIT_NL register.)
76543 2 1 0
JIT_N7 JIT_N6 JIT_N5 JIT_N4 JIT_N3 JIT_N2 JIT_N1 JIT_N0
76543 2 1 0
- - - - JIT_N11 JIT_N10 JIT_N9 JIT_N8
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
JTAG 95 December 17, 2009
6JTAG
The IDT82P20416 supports the digital Boundary Scan Specification
as described in the IEEE 1149.1 standards.
The boundary scan architecture consists of data and instruction
registers plus a Test Access Port (TAP) controller. The control of the TAP
is achieved through signals applied to the Test Mode Select (TMS) and
Test Clock (TCK) input pins. Data is shifted into the registers via the Test
Data Input (TDI) pin, and shifted out of the registers via the Test Data
Output (TDO) pin. Both TDI and TDO are clocked at a rate determined
by TCK.
The JTAG boundary scan registers include BSR (Boundary Scan
Register), DIR (Device Identification Register), BR (Bypass Register)
and IR (Instruction Register). These will be described in the following
pages. Refer to Figure-36 for architecture.
Figure-36 JTAG Architecture
6.1 JTAG INSTRUCTION REGISTER (IR)
The IR with instruction decode block is used to select the test to be
executed or the data register to be accessed or both.
The instructions include: EXTEST, SAMPLE/PRELOAD, IDCODE,
BYPASS, CLAMP and HIGHZ.
6.2 JTAG DATA REGISTER
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR)
The IDR can be set to define the Version, the Part Number, the
Manufacturer Identity and a fixed bit.
6.2.2 BYPASS REGISTER (BYP)
The BYP consists of a single bit. It can provide a serial path between
the TDI input and the TDO output. Bypassing the BYR will reduce test
access times.
6.2.3 BOUNDARY SCAN REGISTER (BSR)
The bidirectional ports interface to 2 boundary scan cells:
- In cell: The input cell is observable only.
- Out cell: The output cell is controllable and observable.
6.3 TEST ACCESS PORT (TAP) CONTROLLER
The TAP controller is a 16-state synchronous state machine. The
states include: Test Logic Reset, Run-Test/Idle, Select-DR-Scan,
Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR, Update-DR,
Select-IR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR.
Figure-37 shows the state diagram. Note that the figure contains two
main branches to access either the data or instruction registers. The
value shown next to each state transition in this figure states the value
present at TMS at each rising edge of TCK.
BSR (Boundary Scan Register)
DIR (Device Identification Register)
BR (Bypass Register)
IR (Instruction Register)
MUX
TDO
TDI
TCK
TMS
TRST
Control
MUX
Select
Output Enable
TAP
(Test Access
Port) Controller
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
JTAG 96 December 17, 2009
Figure-37 JTAG State Diagram
Test-logic Reset
Run Test/Idle Select-DR Select-IR
Capture-DR Capture-IR
Shift-DR Shift-IR
Exit1-DR Exit1-IR
Pause-DR Pause-IR
Exit2-DR Exit2-IR
Update-DR Update-IR
1
0
0
111
00
00
0
0
11
1
0
1
0
1
1
1010
1
0
1
1
0
0
0
1
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Thermal Management 97 December 17, 2009
7 THERMAL MANAGEMENT
The device is designed to operate over the industry temperature
range -40°C ~ +85°C. To ensure the functionality and reliability of the
device, the maximum junction temperature, Tjmax, should not exceed
125°C. In some applications, the device will consume more power and a
thermal solution should be provided to ensure the junction temperature
Tj does not exceed Tjmax. Below is a table listing thermal data for the
IDT82P20416.
7.1 JUNCTION TEMPERATURE
Junction temperature Tj is the temperature of package typically at the
geographical center of the chip where the device's electrical circuits are.
It can be calculated as follows:
Equation 1: Tj = TA + P *
θ
JA
Where:
θ
JA = Junction-to-Ambient Thermal Resistance of the package
Tj = Junction Temperature
TA = Ambient Temperature
P = Device Power Consumption
For the IDT82P20416, the above values are:
θ
JA = 23.7 °C/W (when airflow rate is 0 m/s. See the above table )
Tjmax = 125 °C
TA = - 40 °C ~ 85 °C
P = Refer to Section 8.3 Device Power Consumption and Dissipation
(Typical) 1
7.2 EXAMPLE OF JUNCTION TEMPERATURE CAL-
CULATION
Assume:
TA = 85 °C
θ
JA = 23.7 °C/W (airflow: 0 m/s)
P = 1.46 W (E1 120 Ω, 100% ones, External Impedance matching)
The junction temperature Tj can be calculated as follows:
Tj = TA + P *
θ
JA = 85 °C + 1.46 W X 23.7 °C/W = 119.6 °C
The junction temperature of 119.6 °C is below the maximum junction
temperature of 125 °C, so no extra heat enhancement is required.
In some operation environments, the calculated junction temperature
might exceed the maximum junction temperature of 125 °C and an
external thermal solution such as a heatsink is required.
7.3 HEATSINK EVALUATION
A heatsink is expanding the surface area of the device to which it is
attached.
θ
JA is now a combination of device case and heatsink thermal
resistance, as the heat flowing from the die junction to ambient goes
through the package and the heatsink. θJA can be calculated as follows:
Equation 2:
θ
JA =
θ
JC +
θ
HA
Where:
θ
JC = Junction-to-Case (heatsink) Thermal Resistance
θ
HA = Heatsink-to-Ambient Thermal Resistance
For the IDT82P20416, θJC is 4.2 °C/W.
θHA determines which heatsink can be selected to ensure the junc-
tion temperature does not exceed Tjmax. According to Equation 1 and 2,
the heatsink-to-ambient thermal resistance θHA can be calculated as
follows:
Equation 3:
θ
HA = (Tj - TA) / P -
θ
JC
Assume:
Tj = 125 °C (Tjmax)
TA = 85 °C
P = 2.72 W (E1 75 Ω, 100% ones, Fully Internal Impedance matching)
θ
JC = 4.2 °C/W
The Heatsink-to-Ambient thermal resistance θHA can be calculated
as follows:
θ
HA = (125 °C - 85 °C ) / 2.72 W - 4.2 °C/W = 10.51°C/W
That is, if a heatsink whose heatsink-to-ambient thermal resistance
θHA is below or equal to 10.51 °C/W is used in such operation environ-
ment, the junction temperature will not exceed the maximum junction
temperature.
Package θJC (°C/W) 1θJB (°C/W) 2θJA (°C/W) 3Airflow (m/s)
484-pin BF
4.2 5.3
23.7 0
18.7 1
17.0 2
16.1 3
15.5 4
15.0 5
Note:
1. Junction-to-Case Thermal Resistance
2. Junction-to-Board Thermal Resistance
3. Junction-to-Ambient Thermal Resistance
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 98 December 17, 2009
8 PHYSICAL AND ELECTRICAL SPECIFICATIONS
8.1 ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Min Max Unit
VDDD Digital Core Power Supply -0.5 2.2 V
VDDA Analog Core Power Supply -0.5 4.6 V
VDDIO I/O Power Supply -0.5 4.6 V
VDDT0~15 Power Supply for Transmitter Driver -0.5 4.6 V
VDDR0~15 Power Supply for Receiver -0.5 4.6 V
Vin
Input Voltage, Any Digital Pin GND - 0.5 6 V
Input Voltage, Any RTIP and RRING pin 1GND - 0.5 VDDR + 0.5 V
ESD Voltage, Any Pin 22000 V
Iin
Transient Latch-up Current, Any Pin 100 mA
Input Current, Any Digital Pin 3-10 10 mA
DC Input Current, Any Analog Pin 3±100 mA
Pd Maximum Power Dissipation in Package 1.68 4W
Tj Junction Temperature 125 °C
TsStorage Temperature -65 +150 °C
Note:
1. Reference to ground.
2. Human body model.
3. Constant input current.
4. If device power consumption exceeds this value, a heatsink or a fan must be used. Refer to Chapter 7 Thermal Management.
Caution:
Exceeding the above values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended
period may affect device reliability.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 99 December 17, 2009
8.2 RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ. Max Unit
Top Operating Temperature Range -40 85 1°C
VDDIO Digital I/O Power Supply 3.13 3.3 3.47 V
VDDA Analog Core Power Supply 3.13 3.3 3.47 V
VDDD Digital Core Power Supply 1.71 1.8 1.89 V
VDDT Power Supply for Transmitter Driver 3.13 3.3 3.47 V
VDDR Power Supply for Receiver 3.13 3.3 3.47 V
VIL Input Low Voltage -0.5 0.8 V
VIH Input High Voltage 2.0 VDDIO+0.5 V
Note:
1. An external thermal solution such as heatsink may be required depending on the mode of operation. Refer to Chapter 7 Thermal Management.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 100 December 17, 2009
8.3 DEVICE POWER CONSUMPTION AND DISSIPATION (TYPICAL) 1
Mode Parameter
Total Consumption (W) Total Device Power Dissipation
(for Thermal Consideration, W)
Per-Channel
Power Down Saving (mW) 2
1.8 V 3.3 V Total
Fully
Internal
R120IN=1 3
Partially
Internal
R120IN=0 4
External 5
Fully
Internal
R120IN=1 3
Partially
Internal
R120IN=0 4
External 5
E1/120 ΩPRBS 0.18 1.73 1.91 1.91 1.48 1.20 80 60 40
100% ones 0.18 2.31 2.49 2.49 1.87 1.46 130 90 70
E1/75 ΩPRBS 0.18 1.86 2.04 2.04 1.77 0.98 90 60 50
100% ones 0.18 2.54 2.72 2.72 2.33 1.32 150 120 80
T1/100 ΩQRSS 0.14 1.93 2.07 2.07 1.66 1.57 100 80 60
100% ones 0.14 2.79 2.93 2.93 2.32 2.24 160 120 90
J1/110 ΩQRSS 0.14 1.87 2.01 2.01 1.59 1.56 100 70 60
100% ones 0.14 2.64 2.78 2.78 2.17 2.17 150 110 90
Note:
1. Test conditions: VDDx (typical) at 25 °C operating temperature (ambient).
2. The R_OFF bit (b5, RCF0,...) and T_OFF bit (b5, TCF0,...) are set to ‘1’ to enable per-channel power down.
3. The transmitter is in Internal Impedance Matching mode and the receiver is in Fully Internal Impedance Matching mode. That is, the R120IN bit (b4, RCF0,...) is set to ‘1’. And the
T_TERM[2:0] bits (b2~0, TCF0,...) and R_TERM[2:0] bits (b2~0, RCF0,...) are set according to different cable conditions.
4. The transmitter is in Internal Impedance Matching mode and the receiver is in Partially Internal Impedance Matching mode. That is, the R120IN bit (b4, RCF0,...) is set to ‘0’. And the
T_TERM[2:0] bits (b2~0, TCF0,...) and R_TERM[2:0] bits (b2~0, RCF0,...) are set according to different cable conditions.
5. For E1 mode, both the transmitter and the receiver are in External Impedance Matching mode. That is, the T_TERM[2:0] bits (b2~0, TCF0,...) are set to ‘111’ and the R_TERM[2:0]
bits (b2~0, RCF0,...) are set to ‘1xx’. For T1/J1 mode, as the transmitter External Impedance Matching mode is not supported, the transmitter is in Internal Impedance Matching mode
and the receiver is in Internal Impedance Matching mode. That is, the T_TERM[2:0] bits (b2~0, TCF0,...) are set according to different cable conditions and the R_TERM[2:0] bits (b2~0,
RCF0,...) are set to ‘1xx’.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 101 December 17, 2009
8.4 DEVICE POWER CONSUMPTION AND DISSIPATION (MAXIMUM) 1
Mode Parameter
Total Consumption (W) Total Device Power Dissipation
(for Thermal Consideration, W)
1.89 V 3.47 V Total Fully Internal
R120IN=1 2
Partially Internal
R120IN=0 3 External 4
E1/120 ΩPRBS 0.22 1.82 2.04 2.04 1.68 1.40
100% ones 0.22 2.43 2.65 2.65 2.08 1.67
E1/75 ΩPRBS 0.22 1.95 2.17 2.17 1.98 0.98
100% ones 0.22 2.67 2.89 2.89 2.53 1.37
T1/100 ΩQRSS 0.17 2.03 2.20 2.20 1.84 1.65
100% ones 0.17 2.93 3.10 3.10 2.53 2.34
J1/110 ΩQRSS 0.17 1.96 2.13 2.13 1.78 1.63
100% ones 0.17 2.78 2.95 2.95 2.38 2.28
Note:
1. Test conditions: VDDx (maximum) at 85 °C operating temperature (ambient).
2. The transmitter is in Internal Impedance Matching mode and the receiver is in Fully Internal Impedance Matching mode. That is, the R120IN bit (b4, RCF0,...) is set to ‘1’. And the
T_TERM[2:0] bits (b2~0, TCF0,...) and R_TERM[2:0] bits (b2~0, RCF0,...) are set according to different cable conditions.
3. The transmitter is in Internal Impedance Matching mode and the receiver is in Partially Internal Impedance Matching mode. That is, the R120IN bit (b4, RCF0,...) is set to ‘0’. And the
T_TERM[2:0] bits (b2~0, TCF0,...) and R_TERM[2:0] bits (b2~0, RCF0,...) are set according to different cable conditions.
4. For E1 mode, both the transmitter and the receiver are in External Impedance Matching mode. That is, the T_TERM[2:0] bits (b2~0, TCF0,...) are set to ‘111’ and the R_TERM[2:0]
bits (b2~0, RCF0,...) are set to ‘1xx’. For T1/J1 mode, as the transmitter External Impedance Matching mode is not supported, the transmitter is in Internal Impedance Matching mode
and the receiver is in Internal Impedance Matching mode. That is, the T_TERM[2:0] bits (b2~0, TCF0,...) are set according to different cable conditions and the R_TERM[2:0] bits (b2~0,
RCF0,...) are set to ‘1xx’.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 102 December 17, 2009
8.5 D.C. CHARACTERISTICS
@ TA = -40 to +85 °C, VDDIO = 3.3 V ± 5%, VDDD = 1.8 V ± 5%
Symbol Parameter Min Typ. Max Unit Test Conditions
VOL Output Low Voltage 0.40 V VDDIO = 3.13 V, IOL = 4 mA, 8 mA
VOH Output High Voltage 2.4 VDDIO V VDDIO = 3.13 V, IOH = 4 mA, 8 mA
VT+ Schmitt Trigger Input Low to High Threshold 1.47 V
VT- Schmitt Trigger Input High to Low Threshold 0.89 V
Rpu Internal Pull-up /Pull-down Resistor 50 70 115 KΩ
IIL Input Low Current -1 0 +1 µA VIL = GNDD
IIH Input High Current -1 0 +1 µA VIH = VDDIO
Cin Input Digital Pin Capacitance 10 pF
Cout Output Load Capacitance 50 pF
Cout Output Load Capacitance (bus pins) 100 pF
IZL Leakage Current of Digital Output in High-Z mode -10 10 µA GNDIO < VO < VDDIO
ZOH Output High-Z on TTIPn, TRINGn pins 10 KΩ
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 103 December 17, 2009
8.6 E1 RECEIVER ELECTRICAL CHARACTERISTICS
Parameter Min Typ. Max Unit Test Conditions
Receiver Sensitivity of Receive Differen-
tial mode with Cable Loss @ 1024 KHz
15 dB
with Nominal Pulse Amplitude of 3.0 V for 120 Ω
and 2.37 V for 75 Ω termination, adding -18 dB
interference signal.
Receiver Sensitivity of Receive Single
Ended mode with Cable Loss @ 1024
kHz
12 dB
Signal to Noise Interference Margin -16 dB @cable loss 0-6 dB
Analog LOS Level
(Normal Mode)
ALOS[2:0]
000
001 (default)
010
011
100
101
110
111
0.5
0.7
0.9
1.2
1.4
1.6
1.8
2.0
Vpp In Differential mode, measured between RTIP and
RRING pins.
In Singled Ended mode, measured between RTIP
and GNDA pins
Refer to Table-17 for LLOS Criteria Declare and
Clear.
LOS hysteresis 0.25
Analog LOS Level
(Line Monitor Mode)
ALOS[2:0]
000
001 (default)
010
011
1xx (reserved)
1.0
1.4
1.8
2.2
Vpp Measured on the line with the monitor gain set by
the MG[1:0] bits (b1~0, RCF2,...) equal to the
resistive attenuation. Refer to Table-17 for LLOS
Criteria Declare and Clear.
LOS hysteresis 0.41
Allowable Consecutive Zeros before LOS:
G.775
I.431 / ETSI300233
32
2048
LOS Reset 12.5 % ones G.775, ETSI 300233
Receive Intrinsic Jitter 0.05 U.I. JA disabled; wide band
Input Jitter Tolerance:
1 Hz ~ 20 Hz
20 Hz ~ 2.4 KHz
18 KHz ~ 100 KHz
80
10
0.6
Refer to Fig-
ure-41
U.I.
U.I.
U.I.
G.823, with 6 dB Cable Attenuation
Receiver Differential Input Impedance 2.6 KΩ
@1024 KHz; Rx port is high-Z
Receiver Common Mode Input Imped-
ance to GND
1.6 KΩ
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 104 December 17, 2009
Receiver Single Ended mode Input
Impedance to GND
3.1 KΩThe RRINGn pins are open.
Receive Return Loss:
51 KHz ~ 102 KHz
102 KHz ~ 2.048 MHz
2.048 MHz ~ 3.072 MHz
12
18
14
dB
dB
dB
G.703
Receive Path Delay:
Single Rail
Dual Rail NRZ
Dual Rail RZ
6.6
1.8
1.5
U.I.
U.I.
U.I.
JA Disabled
Parameter Min Typ. Max Unit Test Conditions
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 105 December 17, 2009
8.7 T1/J1 RECEIVER ELECTRICAL CHARACTERISTICS
Parameter Min Typ. Max Unit Test Conditions
Receiver Sensitivity of Receive Differen-
tial mode with Cable Loss @ 772 KHz
15 dB
with Nominal Pulse Amplitude of 3.0 V for 100 Ω ter-
mination, adding -18 dB interference signal.
Receiver Sensitivity of Receive Single
Ended mode with Cable Loss @ 772 KHz
12 dB
Signal to Noise Interference Margin -16 dB
Analog LOS Level
(Normal Mode)
ALOS[2:0]
000
001 (default)
010
011
100
101
110
111
0.5
0.7
0.9
1.2
1.4
1.6
1.8
2.0
Vpp In Differential mode, measured between RTIP and
RRING pins.
In Singled Ended mode, measured between RTIP
and GNDA pins
Refer to Table-17 for LLOS Criteria Declare and
Clear.
LOS hysteresis 0.25
Analog LOS Level
(Line Monitor Mode)
ALOS[2:0]
000
001 (default)
010
011
1xx (reserved)
1.0
1.4
1.8
2.2
Vpp Measured on the line with the monitor gain set by
the MG[1:0] bits (b1~0, RCF2,...) equal to the
resistive attenuation. Refer to Table-17 for LLOS
Criteria Declare and Clear.
LOS hysteresis 0.41
Allowable Consecutive Zeros before LOS:
T1.231 - 1993
I.431
175
1544
LOS Reset 12.5 % ones G.775, ETSI 300233
Receive Intrinsic Jitter 0.05 U.I. JA disabled; Wide band
Input Jitter Tolerance:
0.1 Hz ~ 1 Hz
4.9 Hz ~ 300 Hz
10 KHz ~ 100 KHz
138.0
28.0
0.4
U.I.
U.I.
U.I.
AT&T62411
Receiver Differential Input Impedance 3.1 KΩ
@772 KHz; Rx port is high-Z
Receiver Common Mode Input Imped-
ance to GND
2.2 KΩ
Receiver Single Ended mode Input
Impedance to GND
4KΩThe RRINGn pins are open.
Receive Return Loss:
39 KHz ~ 77 KHz
77 KHz ~ 1.544 MHz
1.544 MHz ~ 2.316 MHz
20
20
20
dB
dB
dB
G.703
Receive Path Delay:
Single Rail
Dual Rail NRZ
Dual Rail RZ
6.5
2.5
1.4
U.I.
U.I.
U.I.
JA Disabled
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 106 December 17, 2009
8.8 E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
Parameter Min Typ. Max Unit Test Conditions
Output Pulse Amplitude:
E1, 75 Ω load
E1, 120 Ω load
2.14
2.7
2.37
3.0
2.60
3.3
V
V
Differential Line Inter-
face mode
Zero (Space) Level:
E1, 75 Ω load
E1, 120 Ω load
-0.237
-0.3
+0.237
0.3
V
V
Differential Line Inter-
face mode
Transmit Amplitude Variation with Supply -1 +1 %
Difference between Pulse Sequences for 17 consecutive pulses
(T1.102)
200 mV
Output Pulse Width at 50% of Nominal Amplitude 232 244 256 ns
Ratio of the Amplitudes of Positive and Negative Pulses at the
Center of the Pulse Interval (G.703)
0.95 1.05
Ratio of the Width of Positive and Negative Pulses at the Center
of the Pulse Interval (G.703)
0.95 1.05
Transmit Analog LOS Level (TALOS)
(Differential line interface)
TALOS[1:0]
00
01 (default)
10
11
1.2
0.9
0.6
0.4
VpMeasured on the TTIP
and TRING pins.
TALOS hysteresis 0.08
Transmit Analog LOS Level (TALOS)
(Single Ended line interface)
TALOS[1:0]
00
01 (default)
10
11
0.61
0.48
0.32
0.24
VpMeasured on the TTIP
pin.
TALOS hysteresis 0.04
Transmit Return Loss (G.703):
51 KHz ~ 102 KHz
102 KHz ~ 2.048 MHz
2.048 MHz ~ 3.072 MHz
8
14
10
dB
dB
dB
Internal Impedance
Matching
Intrinsic Transmit Jitter
20 Hz ~ 100 KHz 0.050 U.I.
TCLK is jitter free
Transmit Path Delay:
Single Rail
Dual Rail NRZ
Dual Rail RZ
8.5
4.5
4.4
U.I.
U.I.
U.I.
JA is disabled
Line Short Circuit Current 100 mAp Measured on pin
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 107 December 17, 2009
8.9 T1/J1 TRANSMITTER ELECTRICAL CHARACTERISTICS
Parameter Min Typ. Max Unit Test Conditions
Output Pulse Amplitude 2.4 3.0 3.6 V Differential Line
Interface mode
Zero (Space) Level -0.15 0.15 V
Transmit Amplitude Variation with Supply -1 +1 %
Difference between Pulse Sequences for 17 consecutive pulses
(T1.102)
200 mV
Output Pulse Width at 50% of Nominal Amplitude 338 350 362 ns
Pulse Width Variation at the Half Amplitude (T1.102) 20 ns
Imbalance between Positive and Negative Pulses Amplitude
(T1.102)
0.95 1.05
Output Power Levels (T1.102-1993):
@772 KHz
@1544 KHz (Referenced to Power at 772 KHz)
12.6
-29
17.9 dBm
dBm
Transmit Analog LOS Level (TALOS)
(Differential line interface)
TALOS[1:0]
00
01 (default)
10
11
1.2
0.9
0.6
0.4
VpMeasured on the
TTIP and TRING
pins.
TALOS hysteresis 0.08
Transmit Analog LOS Level (TALOS)
(Single Ended line interface)
TALOS[1:0]
00
01 (default)
10
11
0.61
0.48
0.32
0.24
VpMeasured on the
TTIP pin.
TALOS hysteresis 0.04
Transmit Return Loss (G.703):
39 KHz ~ 77 KHz
77 KHz ~ 1.544 MHz
1.544 MHz ~ 2.316 MHz
8
14
10
dB
dB
dB
Internal Impedance
Matching
Intrinsic Transmit Jitter:
10 Hz ~ 8 KHz
8 KHz ~ 40 KHz
10 Hz ~ 40 KHz
Wide Band
0.020
0.025
0.025
0.050
U.I.p-p
U.I.p-p
U.I.p-p
U.I.p-p
TCLK is jitter free
Transmit Path Delay (JA is disabled):
Single Rail
Dual Rail NRZ
Dual Rail RZ
8.2
4.1
4.3
U.I.
U.I.
U.I.
JA is disabled
Line Short Circuit Current 100 mAp Measure on pin
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 108 December 17, 2009
8.10 TRANSMITTER AND RECEIVER TIMING CHARACTERISTICS
Symbol Parameter Min Typ. Max Unit
MCLK Frequency:
E1
T1/J1
2.048 X n
1.544 X n
(n = 1 ~ 8)
MHz
MHz
MCLK Tolerance -100 100 ppm
MCLK Duty Cycle 30 70 %
Transmit Path
TCLK Frequency:
E1
T1/J1
2.048
1.544
MHz
MHz
TCLK Tolerance -50 +50 ppm
TCLK Duty Cycle 10 90 %
t1 Transmit Data Setup Time 40 ns
t2 Transmit Data Hold Time 40 ns
Delay Time of OE low to Driver High-Z 1 µs
Receive Path
Clock Recovery Capture Range 1:
E1
T1/J1
+80 / -80
+180 / -180
ppm
ppm
RCLK Duty Cycle 240 50 60 %
t4 RCLK Pulse Width 2:
E1
T1/J1
457
607
488
648
519
689
ns
ns
t5 RCLK Pulse Width Low Time:
E1
T1/J1
203
259
244
324
285
389
ns
ns
t6 RCLK Pulse Width High Time:
E1
T1/J1
203
259
244
324
285
389
ns
ns
Rise/Fall Time 320 ns
t7 Receive Data Setup Time:
E1
T1/J1
200
200
244
324
ns
ns
t8 Receive Data Hold Time:
E1
T1/J1
200
200
244
324
ns
ns
Note:
1. Relative to nominal frequency, MCLK = +100 or -100 ppm.
2. RCLK duty cycle width will vary depending on extent of the received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2 UI
displacement for E1 per ITU G.823).
3. For all digital outputs. Cload = 15 pF.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 109 December 17, 2009
Figure-38 Transmit Clock Timing Diagram
Figure-39 Receive Clock Timing Diagram
TDNn
TDn/TDPn
TCLKn
t1 t2
t4
t6
t7
t5
t8
t7 t8
RCLK
RDn/RDPn
(RCK_ES = 0)
RDNn
RDn/RDPn
(RCK_ES = 1)
RDNn
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 110 December 17, 2009
8.11 CLKE1 TIMING CHARACTERISTICS
Figure-40 CLKE1 Clock Timing Diagram
Symbol Parameter Min Typ. Max Unit
CLKE1 outputs 2.048 MHz clock
t1 CLKE1 Pulse Width 488 ns
t2 CLKE1 Pulse Width High Time 232 244 256 ns
t3 CLKE1 Pulse Width Low Time 232 244 256 ns
t4 LLOS Data Setup Time 217 244 271 ns
t5 LLOS Data Hold Time 217 244 271 ns
CLKE1 outputs 8kHz clock
t1 CLKE1 Pulse Width 125 µs
t2 CLKE1 Pulse Width High Time 62.4 62.5 62.6 µs
t3 CLKE1 Pulse Width Low Time 62.4 62.5 62.6 µs
t4 LLOS Data Setup Time 62.38 62.5 62.62 µs
t5 LLOS Data Hold Time 62.38 62.5 62.62 µs
CLKE1
t1
t2
t4
t3
t5
LLOS
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 111 December 17, 2009
8.12 JITTER ATTENUATION CHARACTERISTICS
Parameter Min Typ. Max Unit
Jitter Transfer Function Corner (-3 dB) Frequency:
E1, 32/64/128-bit FIFO
T1/J1, 32/64/128-bit FIFO
JA_BW = 0
JA_BW = 1
JA_BW = 0
JA_BW = 1
6.63
0.87
5
1.28
Hz
Hz
Hz
Hz
Jitter Attenuator:
E1 (G.736)
T1/J1 (AT&T pub.62411)
@ 3 Hz
@ 40 Hz
@ 400 Hz
@ 100 KHz
@ 1 Hz
@ 20 Hz
@ 1 KHz
@ 1.4 KHz
@ 70 KHz
-0.5
-0.5
+19.5
+19.5
0
0
+33.3
40
40
dB
dB
dB
dB
dB
dB
dB
dB
dB
Jitter Attenuator Latency Delay:
32-bit FIFO
64-bit FIFO
128-bit FIFO
16
32
64
U.I.
U.I.
U.I.
Input Jitter Tolerance before FIFO Overflow or
Underflow:
32-bit FIFO
64-bit FIFO
128-bit FIFO
28
56
120
U.I.
U.I.
U.I.
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 112 December 17, 2009
Figure-41 E1 Jitter Tolerance Performance
Figure-42 T1/J1 Jitter Tolerance Performance
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 113 December 17, 2009
Figure-43 E1 Jitter Transfer Performance
Figure-44 T1/J1 Jitter Transfer Performance
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 114 December 17, 2009
8.13 MICROPROCESSOR INTERFACE TIMING
8.13.1 SERIAL MICROPROCESSOR INTERFACE
A falling transition on CS indicates the start of a read/write operation,
and a rising transition indicates the end of the operation. After CS is set
to low, a 5-bit instruction on SDI is input to the device on the rising edge
of SCLK. If the MSB is ‘1’, it is a read operation. If the MSB is ‘0’, it is a
write operation. Following the instruction, an 11-bit address is clocked in
on SDI to specify the register. If the device is in a read operation, the
data read from the specified register is output on SDO on the falling
edge of SCLK (refer to Figure-45). If the device is in a write operation,
the data written to the specified register is input on SDI following the
address byte (refer to Figure-46).
Figure-45 Read Operation in Serial Microprocessor Interface
Figure-46 Write Operation in Serial Microprocessor Interface
CS
SCLK
SDI
SDO
100 1 2 3 4 5 6 7 8 9 11121314151617181920212223
A0A7 A6 A5 A4 A3 A2 A1
Instruction Register Address
High-Z
D0D7 D6 D5 D4 D3 D2 D1
Don't-CareA9
R/W Don't Care A10 A8
CS
SCLK
SDI
SDO
100 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 22 23
A0A7 A6 A5 A4 A3 A2 A1
Instruction Data Byte
High-Z
D0D7 D6 D5 D4 D3 D2 D1
Register Address
A8R/W Don't Care A10 A9
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 115 December 17, 2009
Figure-47 Timing Diagram
Symbol Description Min. Max. Units
fOP SCLK Frequency 2.0 MHz
tCSH Minimum CS High Time 100 ns
tCSS CS Setup Time 50 ns
tCSD CS Hold Time 100 ns
tCLD Clock Disable Time 50 ns
tCLH Clock High Time 205 ns
tCLL Clock Low Time 205 ns
tDIS Data Setup Time 50 ns
tDIH Data Hold Time 150 ns
tPD Output Delay 150 ns
tDF Output Disable Time 50 ns
CS
SCLK
SDI
SDO
tCSH
tCSS
High-Z High-Z
tCSD
tCLH tCLL
tDIS tDIH
tPD tDF
Valid Input
Valid Output
tCLD
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Physical And Electrical Specifications 116 December 17, 2009
8.14 JTAG TIMING CHARACTERISTICS
Figure-48 JTAG Timing
Symbol Parameter Min Typ. Max Unit
t1 TCK Period 100 ns
t2 TMS to TCK Setup Time; TDI to TCK Setup Time 25 ns
t3 TCK to TMS Hold Time; TCK to TDI Hold Time 25 ns
t4 TCK to TDO Delay Time 50 ns
t1
t2 t3
t4
TCK
TMS
TDI
TDO
Glossary 117 December 17, 2009
AIS — Alarm Indication Signal
AMI — Alternate Mark Inversion
ARB — Arbitrary Pattern
B8ZS — Binary 8 Zero Substitution
BPV — Bipolar Violation
CF — Corner Frequency
CV — Code Violation
DPLL — Digital Phase Locked Loop
EXZ — Excessive Zeroes
FIFO — First In First Out
HDB3 — High Density Bipolar 3
HPS — Hitless Protection Switching
IB — Inband Loopback
LAIS — Line Alarm Indication Signal
LBPV — Line Bipolar Violation
LEXZ — Line Excessive Zeroes
LLOS — Line Loss of Signal
LOS — Loss Of Signal
NRZ — Non-Return to Zero
PBX — Private Branch Exchange
PRBS — Pseudo Random Bit Sequence
QRSS — Quasi-Random Signal Source
RJA — Receive Jitter Attenuator
RZ — Return to Zero
SAIS — System Alarm Indication Signal
SBPV — System Bipolar Violation
SDH — Synchronous Digital Hierarchy
Glossary
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Glossary 118 December 17, 2009
SEXZ — System Excessive Zeroes
SLOS —System LOS
SONET — Synchronous Optical Network
TEPBGA — Thermally Enhanced Plastic Ball Grid Array
TJA — Transmit Jitter Attenuator
TLOS — Transmit Loss of Signal
TOC — Transmit Over Current
Index 119 December 17, 2009
A
Alarm Indication Signal (AIS) ............................................................. 37
B
Bipolar Violation (BPV) ....................................................................... 33
C
cable
coaxial cable ........................................................................ 20, 29
twisted pair cable ................................................................. 20, 29
clock input
MCLK ......................................................................................... 48
XCLK .......................................................................................... 48
clock output
CLKT1/CLKE1 ............................................................................ 47
Code Violation (CV) ............................................................................ 33
common control .................................................................................. 16
Corner Frequency (CF) ...................................................................... 32
D
decoder .............................................................................................. 23
E
encoder .............................................................................................. 25
error counter ....................................................................................... 40
Excessive Zeroes (EXZ) ..................................................................... 33
F
free running ........................................................................................ 47
G
G.772 Monitoring ................................................................................ 45
H
heatsink .............................................................................................. 97
high impedance ........................................................12, 20, 24, 29, 31
Hitless Protection Switch (HPS) ......................................................... 20
hitless switch ...................................................................................... 20
hot-swap ............................................................................................. 20
hot-switchover .................................................................................... 20
I
impedance matching
receive
External Impedance Matching ................................................ 20
Fully Internal Impedance Matching .......................................... 20
Partially Internal Impedance Matching ..................................... 20
transmit
External Impedance Matching ................................................ 29
Internal Impedance Matching ................................................. 29
Interrupt .............................................................................................. 49
J
JA-Limit .............................................................................................. 32
Jitter Measurement (JM) .................................................................... 46
JTAG ............................................................................................17, 95
L
line interface .......................................................................... 12, 20, 29
receive
Differential ............................................................................ 20
transmit
Differential ............................................................................ 29
line monitor ........................................................................................ 22
loopback
Analog Loopback ....................................................................... 42
Digital Loopback ........................................................................ 44
Remote Loopback ...................................................................... 43
Loss of Signal (LOS) .......................................................................... 34
Line LOS (LLOS) ....................................................................... 34
System LOS (SLOS) .................................................................. 35
Transmit LOS (TLOS) ................................................................ 36
M
microprocessor interface ..............................................................17, 52
monitoring
G.772 monitoring ....................................................................... 45
line monitor ................................................................................ 22
P
pattern
ARB ......................................................................................38, 39
Inband Loopback (IB) ...........................................................38, 40
PRBS ...................................................................................38, 39
Index
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
Index 120 December 17, 2009
power down ................................................................................. 24, 31
receiver ....................................................................................... 24
transmitter ................................................................................... 31
Protected Non-Intrusive Monitoring .................................................... 22
R
receive sensitivity ............................................................................... 22
reset
global software reset .................................................................. 52
hardware reset ............................................................................ 52
power-on reset ............................................................................ 52
Rx clock & data recovery .................................................................... 23
S
slicer ................................................................................................... 23
system interface .................................................................... 13, 23, 24
receive
Dual Rail NRZ Format ........................................................... 23
Dual Rail RZ Format .............................................................. 23
Dual Rail Sliced .................................................................... 23
Single Rail NRZ Format ......................................................... 23
transmit
Dual Rail NRZ Format ........................................................... 24
Dual Rail RZ Format .............................................................. 24
Single Rail NRZ Format ......................................................... 24
T
T1 / E1 / J1 mode selection ............................................................... 20
Transmit Over Current (TOC) ............................................................ 29
W
waveform template ............................................................................. 25
IDT82P20416 HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
IDT82P20416 16-CHANNEL SHORT HAUL T1/E1/J1 LINE INTERFACE UNIT
121
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ORDERING INFORMATION
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Device Type Package Process/Temperature Range
BLANK Industrial (-40 °C to +85 °C)
BF Fine Pitch Ball Grid Array
(484-pin Fine Pitch BGA, BF484)
BFG Green Fine Pitch Ball Grid Array
(484-pin Fine Pitch BGA, BFG484)
82P20416 16 High-Density T1/E1/J1 Line Interface Unit
82P20416D 16 High-Density T1/E1/J1 Line Interface Unit
(Gold Bond Wire)
