©2001 Fairchild Semiconductor Corporation JANSR2N7439 Rev. A
JANSR2N7439
Formerly Available As FSL923A0R4,
Radiation Hardened, SEGR Resistant,
P-Channel Power MOSFETs
The Discrete Products Operation of Intersil has developed a
series of Radiation Hardened MOSFETs specifically
designed for commercial and military space applications.
Enhanced Power MOSFET immunity to Single Event Effects
(SEE), Single Event Gate Rupture (SEGR) in particular, is
combined with 100K RADS of total dose hardness to provide
devices which are ideally suited to harsh space
environments. The dose rate and neutron tolerance
necessary for military applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS)
structure. It is specially designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, motor drives,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.
Also available at other radiation and screening levels. See us
on the web, Intersil’ home page:
http://www.semi.intersil.com. Contact your local Intersil
Sales Office for additional information.
Die Family TA17797.
MIL-PRF-19500/658.
Features
• 5A, -200V, r
DS(ON)
= 0.670
Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
2
with
V
DS
up to 80% of Rated Breakdown and
V
GS
of 10V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
DM
• Photo Current
- 3.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
2
- Usable to 1E14 Neutrons/cm
2
Symbol
Packaging
TO-205AF
Ordering Information
PART NUMBER PACKAGE BRAND
JANSR2N7439 TO-205AF JANSR2N7439
G
D
S
S
G
D
Data Sheet January 1999 File Number
4639
[ /Title
(JANS
R2N74
39)
/Sub-
ject
(For-
merly
Avail-
able
As
FSL92
3A0R4
, Radi-
ation
Hard-
ened,
SEGR
Resis-
tant,
P-Chan-
nel
Power
MOS-
FETs)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Semi-
con-
ductor,
FSL92
3A0R4
, Radi-
©2001 Fairchild Semiconductor Corporation JANSR2N7439 Rev. A
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
JANSR2N7439 UNITS
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
DS
-200 V
Drain to Gate Voltage (R
GS
= 20k
Ω
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
-200 V
Continuous Drain Current
T
C
= 25
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
5A
T
C
= 100
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
3A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
15 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
±
20 V
Maximum Power Dissipation
T
C
= 25
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
25 W
T
C
= 100
o
C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
10 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.20 W/
o
C
Single Pulsed Avalanche Current, L = 100
µ
H, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .I
AS
15 A
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
S
5A
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
15 A
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
-55 to 150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
300
1.0
o
C
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 1mA, V
GS
= 0V -200 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C---7.0V
T
C
= 25
o
C -2.0 - -6.0 V
T
C
= 125
o
C-1.0--V
Zero Gate Voltage Drain Current I
DSS
V
DS
= -160V,
V
GS
= 0V
T
C
= 25
o
C--25
µ
A
T
C
= 125
o
C--250
µ
A
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V T
C
= 25
o
C - - 100 nA
T
C
= 125
o
C--200nA
Drain to Source On-State Voltage V
DS(ON)
V
GS
= -12V, I
D
= 5A - - -3.7 V
Drain to Source On Resistance r
DS(ON)12
I
D
= 3A,
V
GS
= -12V
T
C
= 25
o
C - 0.560 0.670
Ω
T
C
= 125
o
C - - 1.20
Ω
Turn-On Delay Time t
d(ON)
V
DD
= -100V, I
D
= 5A,
R
L
=
20Ω
, V
GS
= -12V,
R
GS
=
7.5Ω
- - 30 ns
Rise Time t
r
- - 30 ns
Turn-Off Delay Time t
d(OFF)
- - 60 ns
Fall Time t
f
- - 35 ns
Total Gate Charge (Not on slash sheet) Q
g(TOT)
V
GS
= 0V to -20V V
DD
= -100V,
I
D
= 5A
- - 60 nC
Gate Charge at 12V Q
g(12)
V
GS
= 0V to -12V - 36 40 nC
Threshold Gate Charge (Not on slash sheet) Q
g(TH)
V
GS
= 0V to -2V - - 2.4 nC
Gate Charge Source Q
gs
- 6.0 7.6 nC
Gate Charge Drain Q
gd
-1618nC
Thermal Resistance Junction to Case R
θ
JC
--5
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
- - 175
o
C/W
JANSR2N7439
©2001 Fairchild Semiconductor Corporation JANSR2N7439 Rev. A
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage V
SD
I
SD
= 5A -0.6 - -1.8 V
Reverse Recovery Time t
rr
I
SD
= 5A,dI
SD
/dt = 100A/
µ
s - - 190 ns
Electrical Specifications up to 100K RAD
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS
Drain to Source Breakdown Volts (Note 3) BV
DSS
V
GS
= 0, I
D
= 1mA -200 - V
Gate to Source Threshold Volts (Note 3) V
GS(TH)
V
GS
= V
DS
, I
D
= 1mA -2.0 -6.0 V
Gate to Body Leakage (Notes 2, 3) I
GSS
V
GS
=
±
20V, V
DS = 0V - 100 nA
Zero Gate Leakage (Note 3) IDSS VGS = 0, VDS = -160V - 25 µA
Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = -12V, ID = 5A - -3.7 V
Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = -12V, ID = 3A - 0.670 Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = -12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS.
Single Event Effects (SEB, SEGR) Note 4
TEST SYMBOL
ENVIRONMENT (NOTE 5) APPLIED
VGS BIAS
(V)
(NOTE 6)
MAXIMUM
VDS BIAS (V)
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
Single Event Effects Safe Operating Area SEESOA Ni 26 43 20 -200
Br 37 36 5 -200
Br 37 36 10 -160
Br 37 36 15 -100
Br 37 36 20 -40
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO IAS
-120
-80
-40
0
0101520255
VGS (V)
VDS (V)
-160
-200
TEMP = 25oC
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
LET = 37MeV/mg/cm2, RANGE = 36µ
LET = 26MeV/mg/cm2, RANGE = 43µ
-300-100-10
LIMITING INDUCTANCE (HENRY)
DRAIN SUPPLY (V)
-1000
ILM = 10A
300A
1E-4
1E-5
1E-6
-30
100A
30A
1E-3
1E-7
JANSR2N7439
©2001 Fairchild Semiconductor Corporation JANSR2N7439 Rev. A
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
Typical Performance Curves Unless Otherwise Specified (Continued)
ID, DRAIN (A)
TC, CASE TEMPERATURE (oC)
150100500-50
0
2
4
6
1
3
5
7
10
1
-1
0.1
ID, DRAIN CURRENT (A)
-10 -100
100µs
10ms
100ms
1ms
50
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
TC = 25oC
-500
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
CHARGE
QGD
QG
VG
QGS
-12V
2.5
2.0
1.5
1.0
0.5
0.0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED rDS(ON)
PULSE DURATION = 250ms, VGS = -12V, ID = 3A
10
1
0.1
0.01
10-5 10-4 10-3 10-2 10-1 100101
t, RECTANGULAR PULSE DURATION (s)
THERMAL RESPONSE (ZθJC)
0.001
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
0.5
PDM
t1
t2
JANSR2N7439
©2001 Fairchild Semiconductor Corporation JANSR2N7439 Rev. A
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Typical Performance Curves Unless Otherwise Specified (Continued)
10
11100.1
IAS , AVALANCHE CURRENT (A)
tAV , TIME IN AVALANCHE (ms)
0.01
30
IF R ≠ 0
STARTING TJ = 25oC
tAV = (L/R) ln [(IAS*R) /
IF R = 0
tAV = (L) (IAS) /
STARTING TJ = 150oC
(1.3 RATED BVDSS - VDD)
(1.3 RATED BVDSS - VDD) + 1]
IF R ≠ 0
Test Circuits and Waveforms
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
tP
VGS ≤ 20V
L
+
-
VDS
VDD
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
50Ω
50Ω
50V-150V
IAS
+
-
ELECTRONIC SWITCH OPENS
WHEN IAS IS REACHED
CURRENT
TRANSFORMER
VDD
VDS
BVDSS
tP
IAS
tAV
VDD
RL
VDS
DUT
RGS
0V
VGS = -12V
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%50%
10% PULSE WIDTH
VGS
tON
JANSR2N7439
©2001 Fairchild Semiconductor Corporation JANSR2N7439 Rev. A
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table)
Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Gate to Source Leakage Current IGSS VGS = ±20V ±20 (Note 7) nA
Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value ±25 (Note 7) µA
Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID±20% (Note 8) Ω
Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 8) V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST JANS
Gate Stress VGS = -30V, t = 250µs
Pind Required
Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate
Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours
PDA 5%
Final Electrical Tests (Note 9) MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = -160V, t = 10ms 0.71 A
Unclamped Inductive Switching IAS VGS(PEAK) = -15V, L = 0.1mH 15 A
Thermal Response ∆VSD tH = 10ms; VH = -25V; IH = 1A 60 mV
Thermal Impedance ∆VSD tH = 500ms; VH = -25V; IH = 1A 230 mV
JANSR2N7439
©2001 Fairchild Semiconductor Corporation JANSR2N7439 Rev. A
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
I. Group D - Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
JANSR2N7439
©2001 Fairchild Semiconductor Corporation JANSR2N7439 Rev. A
JANSR2N7439
TO-205AF
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE
L
A
Øb
ØD1
ØD
h
1
2
3
e
e1
SEATING
PLANE
90o
e2
jk
P
45o
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.160 0.180 4.07 4.57 -
Øb 0.016 0.021 0.41 0.53 2, 3
ØD 0.350 0.370 8.89 9.39 -
ØD10.315 0.335 8.01 8.50 -
e 0.095 0.105 2.42 2.66 4
e10.190 0.210 4.83 5.33 4
e20.095 0.105 2.42 2.66 4
h 0.010 0.020 0.26 0.50 -
j 0.028 0.034 0.72 0.86 -
k 0.029 0.045 0.74 1.14 -
L 0.500 0.560 12.70 14.22 3
P 0.075 - 1.91 - 5
NOTES:
1. These dimensions are within allowable dimensions of Rev. E of
JEDEC TO-205AF outline dated 11-82.
2. Lead dimension (without solder).
3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of seating plane.
5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).
6. Lead no. 3 butt welded to stem base.
7. Controlling dimension: Inch.
8. Revision 3 dated 6-94.
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not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICA TION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS P ATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
PACMAN™
POP™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART ST ART™
Star* Power™
Stealth™
FAST
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
Rev. H1
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
F ACT Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
UltraFET
VCX™
