a FEATURES 4- or 8-Analog Input Channels Built-In Track/Hold Function 10 kHz Signal Handling on Each Channel Fast Microprocessor Interface Single 5 V Supply Low Power: 50 mW Fast Conversion Rate, 2.5 s/Channel Tight Error Specification: 1/2 LSB LC2MOS High Speed 4- & 8-Channel 8-Bit ADCs AD7824/AD7828 FUNCTIONAL BLOCK DIAGRAM VREF (+) AIN 1 AIN 4 DB7 DB6 DB5 DB4 4-BIT FLASH ADC (4MSB) VREF (-) VREF (+) 16 AIN 8 THREE STATE DRIVERS 4-BIT DAC MUX* DB3 DB2 DB1 DB0 4-BIT FLASH ADC (4LSB) ADDRESS LATCH DECODE TIMING AND CONTROL CIRCUITRY A0 A1 A2** RDY CS INT RD *AD7824 - 4-CHANNEL MUX **AD7828 - 8-CHANNEL MUX A2 - AD7828 ONLY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7824 and AD7828 are high-speed, multichannel, 8-bit ADCs with a choice of 4 (AD7824) or 8 (AD7828) multiplexed analog inputs. A half-flash conversion technique gives a fast conversion rate of 2.5 s per channel and the parts have a builtin track/hold function capable of digitizing full-scale signals of 10 kHz (157 mV/s slew rate) on all channels. The AD7824 and AD7828 operate from a single 5 V supply and have an analog input range of 0 V to 5 V, using an external 5 V reference. 1. 4- or 8-channel input multiplexer gives cost-effective spacesaving multichannel ADC system. Microprocessor interfacing of the parts is simple, using standard Chip Select (CS) and Read (RD) signals to initiate the conversion and read the data from the three-state data outputs. The half-flash conversion technique means that there is no need to generate a clock signal for the ADC. The AD7824 and AD7828 can be interfaced easily to most popular microprocessors. 4. Tight total unadjusted error spec and channel-to-channel matching eliminate the need for user trims. 2. Fast conversion rate of 2.5 s/channel features a per channel sampling frequency of 100 kHz for the AD7824 or 50 kHz for the AD7828. 3. Built-in track-hold function allows handling of 4- or 8channels up to 10 kHz bandwidth (157 mV/s slew rate). 5. Single 5 V supply simplifies system power requirements. 6. Fast, easy-to-use digital interface allows connection to most popular microprocessors with minimal external components. No clock signal is required for the ADC. The AD7824 and AD7828 are fabricated in an advanced, all ion-implanted, linear-compatible CMOS process (LC2MOS) and have low power dissipation of 40 mW (typ). The AD7824 is available in a 0.3" wide, 24-lead "skinny" DIP, while the AD7828 is available in a 0.6" wide, 28-lead DIP and in 28terminal surface mount packages. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000 (V = 5 V, V (+) = 5 V, V AD7824/AD7828-SPECIFICATIONS noted. All specifications T to T unless otherwise noted. Specifications apply for Mode 0.) DD MIN Parameter ACCURACY Resolution Total Unadjusted Error2 Minimum Resolution for which No Missing Codes Are Guaranteed Channel-to-Channel Mismatch REFERENCE INPUT Input Resistance VREF(+) Input Voltage Range VREF(-) Input Voltage Range ANALOG INPUT Input Voltage Range Input Leakage Current Input Capacitance3 LOGIC INPUTS RD, CS, A0, A1 & A2 VINH VINL IINH IINL Input Capacitance3 LOGIC OUTPUTS DB0-DB7 & INT VOH VOL IOUT (DB0-DB7) Output Capacitance3 RDY VOL4 IOUT Output Capacitance SLEW RATE, TRACKING3 POWER SUPPLY VDD IDD5 Power Dissipation Power Supply Sensitivity REF REF(-) = GND = O V unless otherwise MAX K Version1 L Version B, T Versions C, U Versions Unit 8 1 8 1/2 8 1 8 1/2 Bits LSB max 8 1/4 8 1/4 8 1/4 8 1/4 Bits LSB max 1.0/4.0 VREF(-)/ VDD GND/ VREF(+) 1.0/4.0 VREF(-)/ VDD GND/ VREF(+) 1.0/4.0 VREF(-)/ VDD GND/ VREF(+) 1.0/4.0 VREF(-)/ VDD GND/ VREF(+) k min/k max V min/V max VREF(-)/ VREF(+) 3 45 VREF(-)/ VREF(+) 3 45 VREF(-)/ VREF(+) 3 45 VREF(- )/ VREF(+) 3 45 A max pF typ Analog Input Any Channel 0 V to 5 V 2.4 0.8 1 -1 8 2.4 0.8 1 -1 8 2.4 0.8 1 -1 8 2.4 0.8 1 -1 8 V min V max A max A max pF max Typically 5 pF 4.0 0.4 3 8 4.0 0.4 3 8 4.0 0.4 3 8 4.0 0.4 3 8 V min V max A max pF max ISOURCE = 360 A ISINK = 1.6 mA Floating State Leakage Typically 5 pF 0.4 3 8 0.4 3 8 0.4 3 8 0.4 3 8 V max A max pF max ISINK = 2.6 mA Floating State Leakage Typically 5 pF 0.7 0.157 0.7 0.157 0.7 0.157 0.7 0.157 V/s typ V/s max 5 5 5 5 Volts 16 50 80 1/4 16 50 80 1/4 20 50 100 1/4 20 50 100 1/4 mA max mW typ mW max LSB max Conditions/Comments V min/V max V min/V max 5% for Specified Performance CS = RD = 2.4 V 1/16 LSB typ VDD = 5 V 5% NOTES 1 Temperature ranges are as follows: K, L Versions; 0C to 70C B, C Versions; -40C to +85C T, U Versions; -55C to +125C 2 Total Unadjusted Error includes offset, full-scale and linearity errors. 3 Sample tested at 25C by Product Assurance to ensure compliance. 4 RDY is an open drain output. 5 See Typical Performance Characteristics. Specifications subject to change without notice. -2- REV. D AD7824/AD7828 TIMING CHARACTERISTICS1 (V DD = 5 V; VREF(+) = 5 V; VREF(-) = GND = 0 V unless otherwise noted) Parameter Limit at 25C (All Grades) Limit at TMIN, TMAX (K, L, B, C Grades) Limit at TMIN, TMAX (T, U Grades) Unit Conditions/Comments tCSS tCSH tAS tAH tRDY2 0 0 0 30 40 0 0 0 35 60 0 0 0 40 60 ns min ns min ns min ns min ns max tCRD tACC13 tACC23 tlNTH2 2.0 85 50 40 75 60 500 60 600 2.4 110 60 65 100 70 500 80 500 2.8 120 70 70 100 70 600 80 400 s max ns max ns max ns typ ns max ns max ns min ns min ns max CS to RD Setup Time CS to RD Hold Time Multiplexer Address Setup Time Multiplexer Address Hold Time CS to RDY Delay. Pull-Up Resistor 5 k. Conversion Time, Mode 0 Data Access Time after RD Data Access Time after INT, Mode 0 RD to INT Delay tDH4 tP tRD Data Hold Time Delay Time between Conversions Read Pulsewidth, Mode 1 NOTES 1 Sample tested at 25C to ensure compliance. All input control signals are specified with tr = tf = 20 ns (10 % to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 CL = 50 pF. 3 Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 4 Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2. Specifications subject to change without notice. Test Circuits Figure 2. Load Circuits for Data Hold Time Test Figure 1. Load Circuits for Data Access Time Test REV. D -3- AD7824/AD7828 Operating Temperature Range Commercial (K, L Versions) . . . . . . . . . . . . . . 0C to 70C Industrial (B, C Versions) . . . . . . . . . . . . . -25C to +85C Extended (T, U Versions) . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300C Power Dissipation (Any Package) to 75C . . . . . . . . . 450 mW Derates above 75C by . . . . . . . . . . . . . . . . . . . . . . 6 mW/C ABSOLUTE MAXIMUM RATINGS* (TA = 25C unless otherwise noted) VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V Digital Input Voltage to GND (RD, CS, A0, A1 & A2) . . . . . . . . . . . . -0.3 V, VDD + 0.3 V Digital Output Voltage to GND (DB0, DB7, RDY & INT) . . . . . . . . . . -0.3 V, VDD + 0.3 V VREF (+) to GND . . . . . . . . . . . . . . . . . . VREF (-), VDD + 0.3 V VREF (-) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VREF (+) Analog Input (Any Channel) . . . . . . . . . . -0.3 V, VDD + 0.3 V *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS WARNING! ESD SENSITIVE DEVICE LCCC DIP/SOIC/SSOP ORDERING GUIDE PLCC Model Temperature Range Total Unadjusted Package Error (LSBs) Option AD7824KN AD7824LN AD7824KR AD7824BQ AD7824CQ AD7824TQ* AD7824UQ* 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 1 1/2 1 1 1/2 1 1/2 N-24 N-24 R-24 Q-24 Q-24 Q-24 Q-24 AD7828KN AD7828LN AD7828KP AD7828LP AD7828BQ AD7828CQ AD7828BR AD7828BRS AD7828TQ* AD7828UQ* AD7828TE* AD7828UE* 0C to 70C 0C to 70C 0C to 70C 0C to 70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C 1 1/2 1 1/2 1 1/2 +1 +1 1 1/2 1 1/2 N-28 N-28 P-28A P-28A Q-28 Q-28 R-28 RS-28 Q-28 Q-28 E-28A E-28A *Available to /883B processing only. Contact our local sales office for military data sheet. For U.S. Standard Military Drawing (SMD) see DESC Drawing #5692-88764. -4- REV. D Typical Performance Characteristics-AD7824/AD7828 TPC 4. Power Supply Current vs. Temperature (Not Including Reference Ladder) TPC 1. Conversion Time vs. Temperature TPC 2. Accuracy vs. VREF [VREF = VREF(+) - VREF(-)] TPC 5. Accuracy vs. tP TPC 3. Signal-Noise Ratio vs. Input Frequency TPC 6. Output Current vs. Temperature REV. D -5- AD7824/AD7828 OPERATIONAL DIAGRAM APPLYING THE AD7824/AD7828 The AD7824 is a 4-channel 8-bit A/D converter and the AD7828 is an 8-channel 8-bit A/D converter. Operational diagrams for both of these devices are shown in Figures 3 and 4. The addition of just a 5 V reference allows the devices to perform the analog-to-digital function. REFERENCE AND INPUT The two reference inputs on the AD7824/AD7828 are fully differential and define the zero to full-scale input range of the A/D converter. As a result, the span of the analog input voltage for all channels can easily be varied. By reducing the reference span, VREF (+) - VREF (-), to less than 5 V the sensitivity of the converter can be increased (e.g., if VREF = 2 V then 1 LSB = 7.8 mV). The input/reference arrangement also facilitates ratiometric operation. This reference flexibility also allows the input channel voltage span to be offset from zero. The voltage at VREF (-) sets the input level for all channels which produces a digital output of all zeroes. Therefore, although the analog inputs are not themselves differential, they have nearly differential-input capability in most measurement applications because of the reference design. Figures 5 to 7 show some of the configurations that are possible. Figure 3. AD7824 Operational Diagram Figure 5. Power Supply as Reference Figure 6. External Reference Using the AD580, Full-Scale Input is 2.5 V Figure 4. AD7828 Operational Diagram CIRCUIT INFORMATION BASIC DESCRIPTION The AD7824/AD7828 uses a half-flash conversion technique whereby two 4-bit flash A/D converters are used to achieve an 8-bit result. Each 4-bit flash ADC contains 15 comparators which compare the unknown input to a reference ladder to get a 4-bit result. For a full 8-bit reading to be realized, the upper 4-bit flash, the most significant (MS) flash, performs a conversion to provide the 4 most significant data bits. An internal DAC, driven by the 4 MSBs, then recreates an analog approximation of the input voltage. This analog result is subtracted from the input, and the difference is converted by the lower flash ADC, the least significant (LS) flash, to provide the 4 least significant bits of the output data. -6- Figure 7. Input Not Referenced to GND REV. D AD7824/AD7828 INPUT CURRENT INHERENT SAMPLE-HOLD Due to the novel conversion techniques employed by the AD7824/ AD7828, the analog input behaves somewhat differently than in conventional devices. The ADC's sampled-data comparators take varying amounts of input current depending on which cycle the conversion is in. A major benefit of the AD7824's and AD7828's analog input structure is its ability to measure a variety of high-speed signals without the help of an external sample-and-hold. In a conventional SAR type converter, regardless of its speed, the input must remain stable to at least 1/2 LSB throughout the conversion process if rated accuracy is to be maintained. Consequently, for many high-speed signals, this signal must be externally sampled and held stationary during the conversion. The AD7824/AD7828 input comparators, by nature of their input switching inherently accomplish this sample-and-hold function. Although the conversion time for AD7824/AD7828 is 2 s, the time for which any selected analog input must be 1/2 LSB stable is much smaller. The AD7824/AD7828 tracks the selected input channel for approximately 1 s after conversion start. The value of the analog input at that instant (1 s from conversion start) is the measured value. This value is then used in the least significant flash to generate the lower 4-bits of data. The equivalent input circuit of the AD7824/AD7828 is shown in Figure 8. When a conversion starts (CS and RD going low), all input switches close, and the selected input channel is connected to the most significant and least significant comparators. Therefore, the analog input is connected to thirty-one 1 pF input capacitors at the same time. SINUSOIDAL INPUTS Figure 8. AD7824/AD7828 Equivalent Input Circuit The AD7824/AD7828 can measure input signals with slew rates as high as 157 mV/s to the rated specifications. This means that the analog input frequency can be up to 10 kHz without the aid of an external sample and hold. Furthermore, the AD7828 can measure eight 10 kHz signals without a sample and hold. The Nyquist criterion requires that the sampling rate be twice the input frequency (i.e., 2 x 10 kHz). This requires an ideal antialiasing filter with an infinite roll-off. To ease the problem of antialiasing filter design, the sampling rate is usually much greater than the Nyquist criterion. The maximum sampling rate (FMAX) for the AD7824/AD7828 can be calculated as follows: The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 3 k to 6 k). In addition, about 14 pF of input stray capacitance must be charged. The analog input for any channel can be modelled as an RC network as shown in Figure 9. As RS increases, it takes longer for the input capacitance to charge. 1 FMAX = t CRD + t P FMAX = 1 = 400 kHz 2E - 6 + 0.5E - 6 tCRD = AD7824/AD7828 Conversion Time tP = Minimum Delay Between Conversion This permits a maximum sampling rate of 50 kHz for each of the 8 channels when using the AD7828 and 100 kHz for each of the 4 channels when using the AD7824. Figure 9. RC Network Model The time for which the input comparators track the analog input is approximately 1 s at the start of conversion. Because of input transients on the analog inputs, it is recommended that a source impedance of not greater than 100 ohms be connected to the analog inputs. The output impedance of an op amp is equal to the open loop output impedance divided by the loop gain at the frequency of interest. It is important that the amplifier driving the AD7824/AD7828 analog inputs have sufficient loop gain at the input signal frequency as to make the output impedance low. Suitable op amps for driving the AD7824/AD7828 are the AD544 or AD644. REV. D -7- AD7824/AD7828 UNIPOLAR OPERATION The analog input range for any channel of the AD7824/ AD7828 is 0 V to 5 V as shown in the unipolar operational diagram of Figure 10. Figure 11 shows the designed code transitions which occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is Natural Binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV. Figure 12. AD7824/AD7828 Bipolar 4 V Operation Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation Figure 13. Ideal Input/Output Transfer Characteristic for 4 V Operation TIMING AND CONTROL The AD7824/AD7828 has two digital inputs for timing and control. These are Chip Select (CS) and Read (RD). A READ operation brings CS and RD low which starts a conversion on the channel selected by the multiplexer address inputs (see Table I). There are two modes of operation as outlined by the timing diagrams of Figures 14 and 15. Mode 0 is designed for microprocessors which can be driven into a WAIT state. A READ operation (i.e., CS and RD are taken low) starts a conversion and data is read when conversion is complete. Mode l does not require microprocessor WAIT states. A READ operation initiates a conversion and reads the previous conversion results. Figure 11. Ideal Input/Output Transfer Characteristic for Unipolar 0 V to 5 V Operation BIPOLAR OPERATION The circuit of Figure 12 is designed for bipolar operation. An AD544 op-amp conditions the signal input (VIN) so that only positive voltages appear at AIN 1. The closed loop transfer function of the op amp for the resistor values shown is given below: Table I. Truth Table for Input Channel Selection AD7824 A1 A0 AIN 1 = (2.5 - 0.625 VIN) Volts The analog input range is 4 V and the LSB size is 31.25 mV. The output code is complementary offset binary. The ideal input/output characteristic is shown in Figure 13. 0 0 1 1 -8- 0 1 0 1 A2 0 0 0 0 1 1 1 1 AD7828 A1 A0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Channel AIN 1 AIN 2 AIN 3 AIN 4 AIN 5 AIN 6 AIN 7 AIN 8 REV. D AD7824/AD7828 MODE 0 MODE 1 Figure 14 shows the timing diagram for Mode 0 operation. This mode can only be used for microprocessors which have a WAIT state facility, whereby a READ instruction cycle can be extended to accommodate slow memory devices. A READ operation brings CS and RD low which starts a conversion. The analog multiplexer address inputs must remain valid while CS and RD are low. The data bus (DB7-DB0) remains in the three-state condition until conversion is complete. There are two converter status outputs on the AD7824/AD7828, interrupt (INT) and ready (RDY) which can be used to drive the microprocessor READY/ WAIT input. The RDY is an open drain output (no internal pull-up device) which goes low on the falling edge of CS and goes high impedance at the end of conversion, when the 8-bit conversion result appears on the data outputs. If the RDY status is not required, then the external pull-up resistor can be omitted and the RDY output tied to GND. The INT goes low when conversion is complete and returns high on the rising edge of CS or RD. Mode 1 operation is designed for applications where the microprocessor is not forced into a WAIT state. A READ operation takes CS and RD low which triggers a conversion (see Figure 15). The multiplexer address inputs are latched on the rising edge of RD. Data from the previous conversion is read from the three-state data outputs (DB7-DB0). This data may be disregarded if not required. Note, the RDY output (open drain output) does not provide any status information in this mode and must be connected to GND. At the end of conversion INT goes low. A second READ operation is required to access the new conversion result. This READ operation latches a new address into the multiplexer inputs and starts another conversion. INT returns high at the end of the second READ operation, when CS or RD returns high. A delay of 2.5 s must be allowed between READ operations. Figure 14. Mode 0 Timing Diagram Figure 15. Mode 1 Timing Diagram REV. D -9- AD7824/AD7828 MICROPROCESSOR INTERFACING MC68000 MICROPROCESSOR The AD7824/AD7828 is designed to interface to microprocessors as Read Only Memory (ROM). Analog channel selection, conversion start and data read operations are controlled by CS, RD and the channel address inputs. These signals are common to all memory peripheral devices. Figure 17 shows a MC68000 interface. The AD7824/AD7828 is operating in Mode 0. Assume the ADC is again assigned a memory block starting at address C000. A MOVE instruction to any of the addresses in Table II starts a conversion and reads the conversion result. MOVE*B $C000,D0 Z80 MICROPROCESSOR Figure 16 shows a typical AD7824/AD7828-Z80 interface. The AD7824/AD7828 is operating in Mode 0. Assume the ADC is assigned a memory block starting at address C000. The following LOAD instruction to any of the addresses listed in Table II will start a conversion of the selected channel and read the conversion result. Once conversion has begun, the MC68000 inserts WAIT states, until INT goes low asserting DTACK at the end of conversion. The microprocessor then places the conversion results in the D0 register. LD B, (C000) At the beginning of the instruction cycle when the ADC address is selected, RDY asserts the WAIT input, so that the Z80 is forced into a WAIT state. At the end of conversion RDY returns high and the conversion result is placed in the B register of the microprocessor. Figure 17. AD7824/AD7828-MC68000 Interface TMS32010 MICROCOMPUTER A TMS32010 interface is shown in Figure 18. The AD7824/ AD7828 is operating in Mode 1 (i.e., no P WAIT states). The ADC is mapped at a port address. The following I/O instruction starts a conversion and reads the previous conversion result into the accumulator. Figure 16. AD7824/AD7828-Z80 lnterface Table II. Address Channel Selection Address C000 C001 C002 C003 C004 C005 C006 C007 AD7824 Channel AD7828 Channel 1 2 3 4 1 2 3 4 5 6 7 8 IN, A PA (PA = PORT ADDRESS) The port address (000 to 111) selects the analog channel to be converted. When conversion is complete a second I/O instruction (IN, A PA) reads the up-to-date data into the accumulator and starts another conversion. A delay of 2.5 s must be allowed between conversions. Figure 18. AD7824/AD7828-TMS32010 Interface -10- REV. D AD7824/AD7828 +5V BANDPASS FILTER 1 CS SAMPLE PULSE +5V +15V +10V RD BANDPASS FILTER 2 SPEECH INPUT VDD AIN 1 AIN 2 VDD AD7828 DATA BANDPASS FILTER 7 AIN 7 DB0 BANDPASS FILTER 8 AIN 8 A2 A1 A0 +5V VREF (+) RD AD7824 VREF (+) VREF (-) GND VREF (-) GND Figure 19. Speech Analysis Using Real-Time Filtering VDD WR INT AIN 1 AIN 2 AIN 3 AIN 4 DB7 AMP CS VREF AD7226 DB7 DB7 DB0 DB0 A1 A1 A0 A0 VOUT A VOUT B VOUT C VOUT D VSS VO1 VO 2 VO 3 VO 4 DGND AGND Figure 20. 4-Channel Fast Infinite Sample-and-Hold OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Lead Plastic DIP (N-24) 24-Lead Small Outline Package (R-24) 1.228 (31.19) 1.226 (31.14) 24 0.6141 (15.60) 0.5985 (15.20) 13 1 12 0.260 0.001 (6.61 0.03) 0.32 (8.128) 0.30 (7.62) 24 13 0.2992 (7.60) 0.2914 (7.40) PIN 1 0.130 (3.30) 0.128 (3.25) 1 0.4193 (10.65) 0.3937 (10.00) 12 SEATING PLANE 0.011 (0.28) 0.02 (0.5) 0.11 (2.79) 0.07 (1.78) 15 0.009 (0.23) 0 0.05 (1.27) 0.016 (0.41) 0.09 (2.28) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN/LEAD PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC 24-Lead Cerdip (Q-24)1 13 PIN 1 1 12 0.295 (7.493) MAX 8 0 0.0192 (0.49) SEATING 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 28-Lead Plastic DIP (N-28) 1.290 (32.77) MAX 24 0.0291 (0.74) 45 0.0098 (0.25) 1.45 (36.83) 1.44 (36.58) 0.320 (8.128) 0.290 (7.366) 0.070 (1.778) 0.180 0.225 0.020 (0.508) (4.572) (5.715) MAX MAX 0.125 (3.175) SEATING PLANE MIN 0.012 (0.305) 0.021 (0.533) 0.110 (2.794) 0.065 (1.651) 15 0.008 (0.203) 0.015 (0.381) 0.090 (2.286) 0.055 (1.397) 0 TYP TYP TYP LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH CERDIP LEADS WILL BE EITHER TIN/LEAD PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 28 15 0.55 (13.97) 0.53 (13.47) 1 PIN 1 14 0.16 (4.07) 0.15 (3.56) 0.2 (5.08) MAX 0.175 (4.45) 0.12 (3.05) 0.065 (1.66) 0.02 (0.508) 0.105 (2.67) 0.045 (1.15) 0.015 (0.381) 0.095 (2.42) SEATING PLANE 0.606 (15.4) 0.594 (15.09) 15 0 0.012 (0.305) 0.008 (0.203) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH PLASTIC LEADS WILL BE EITHER SOLDER DIPPED OR TIN/LEAD PLATED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS NOTE 1 Analog Devices reserves the right to ship either cerdip (Q-24, Q-28) or ceramic (D-24A, D-28) hermetic packages. REV. D -11- AD7824/AD7828 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Cerdip (Q-28)1 28-Lead Shrink Small Outline Package (RS-28) 1.490 (37.84) MAX 15 0.407 (10.34) 0.397 (10.08) 0.525 (13.33) 0.515 (13.08) 14 0.62 (15.74) 0.59 (14.93) GLASS SEALANT 0.22 (5.59) MAX 0.125 (3.175) MIN 0.02 (0.5) 0.06 (1.52) SEATING 0.016 (0.406) 0.05 (1.27) PLANE 0.11 (2.79) 0.099 (2.28) 15 0 28 15 1 14 0.311 (7.9) 0.301 (7.64) 1 0.212 (5.38) 0.205 (5.21) PIN 1 0.18 (4.57) MAX C01323c-0-8/00 (rev. D) 28 0.012 (0.305) 0.008 (0.203) 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) PIN 1 0.068 (1.73) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH CERDIP LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 28-Lead Small Outline Package (R-28) 8 0.015 (0.38) 0 SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127) 28-Terminal LCCC (E-28A) 0.100 (2.54)1 0.064 (1.63) 0.7125 (18.10) 0.6969 (17.70) 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) REF 19 28 15 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.458 (11.63)2 0.442 (11.23) 0.4193 (10.65) 0.3937 (10.00) 14 PIN 1 25 26 18 0.2992 (7.60) 0.2914 (7.40) 1 0.03 (0.762) 0.022 (0.558) 0.040 45 (1.02 45) REF 3 PLCS BOTTOM VIEW 0.028 (0.71) 0.022 (0.56) 28 1 NO. 1 PIN INDEX 4 0.020 45 (0.51 45) REF 1 THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS 2 APPLIES TO ALL FOUR SIDES ALL TERMINALS ARE GOLD PLATED 0.0291 (0.74) 45 0.0098 (0.25) 8 0 0.0192 (0.49) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.050 0.005 (1.27 0.13) 12 11 5 0.0500 (1.27) 0.0157 (0.40) 28-Leaded PLCC (P-28A) 0.180 (4.51) 0.165 (4.20) 0.495 (12.57) SQ 0.485 (12.32) PIN 1 IDENTIFIER 26 25 0.050 0.005) (1.27 0.13) TOP VIEW (PINS DOWN) 11 12 0.021 (0.533) 0.013 (0.331) 0.032 (0.812) 0.026 (0.661) 19 18 0.456 (11.582) SQ 0.450 (11.430) 0.430 (10.5) 0.390 (9.9) PRINTED IN U.S.A. 4 5 0.120 (3.04) 0.090 (2.29) NOTE 1 Analog Devices reserves the right to ship either cerdip (Q-24, Q-28) or ceramic ( D-24A, D-28) hermetic packages. -12- REV. D Package/Price Information High Speed, 4-Channel, 8-Bit CMOS ADC Package Description Pin Count Temperature Range Price* (100-499) Model Status 5962-8876401LX PRODUCTION CERDIP GLASS SEAL 24 MILITARY $63.38 5962-8876402LX PRODUCTION CERDIP GLASS SEAL 24 MILITARY $79.80 AD7824BCHIPS PRODUCTION CHIPS/DIE SALES 24 COMMERCIAL $10.87 AD7824BQ PRODUCTION CERDIP GLASS SEAL 24 INDUSTRIAL $19.40 AD7824CQ PRODUCTION CERDIP GLASS SEAL 24 INDUSTRIAL $25.12 AD7824KN PRODUCTION PLASTIC/EPOXY DIP 24 COMMERCIAL $10.87 AD7824KR PRODUCTION NO CONVERSION DATA FROM COS 24 COMMERCIAL $10.87 AD7824KR-REEL PRODUCTION STD S.O. PKG (SOIC) 24 COMMERCIAL AD7824LN PRODUCTION PLASTIC/EPOXY DIP 24 COMMERCIAL $15.03 AD7824UQ PRODUCTION CERDIP GLASS SEAL 24 MILITARY $63.33 - * This price is provided for budgetary purposes as recommended list price in U.S. Dollars per unit in the stated volume. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing. 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