S2068TBI - Applied Micro Circuits Corporation

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

S2068

DUAL GIGABIT ETHERNET TRANSCEIVER

DEVICE

SPECIFICATION

FEATURES

• Functionally compliant with IEEE 802.3z Gigabit

Ethernet Applications

• 1250 MHz (Gigabit Ethernet) operating rate

– Half rate operation

• Dual Transmitter incorporating phase-locked

loop (PLL) clock synthesis from low speed

reference

• Dual Receiver PLL provides clock and data

recovery

• Internally series terminated TTL outputs

• Low-jitter serial PECL interface

• Local Loopback

• Interfaces with coax, twinax, or fiber optics

• Single +3.3V supply, 1.37W power dissipation

• Compact 21mm x 21mm 156 TBGA package

APPLICATIONS

High-speed data communications

• Ethernet Backbones

• Multi-port Gigabit Ethernet Cards

• Switched networks

• Data broadcast environments

GENERAL DESCRIPTION

The S2068 dual transmitter and receiver chip is de-

signed to provide two channels of high-speed serial

data transmission over fiber optic or copper interfaces

conforming to the requirements of the IEEE 802.3z

Gigabit Ethernet specification. The chip runs at

1250.0 Mbps serial data rate with an associated

10-bit parallel data word. The chip provides two sepa-

rate receive PLLs which can be operated asynchro-

nously at slightly different frequencies.

Each bi-directional channel provides parallel to serial

and serial-to-parallel conversion, clock generation

and recovery, and framing. The on-chip transmit PLL

synthesizes the high-speed clock from a low-speed

reference. The on-chip dual receive PLL is used for

clock recovery and data re-timing on the two inde-

pendent data inputs. The transmitter and receiver

each support differential PECL-compatible I/O for

copper or fiber optic component interfaces and pro-

vide excellent signal integrity. Local loopback mode

allows for system diagnostics. The chip requires a

3.3V power supply and dissipates 1.37 watts.

Figure 1 shows the use of the S2062 and S2068 in a

Gigabit Ethernet application. Figure 2 summarizes

the input/output signals of the device. Figures 3 and

4 show the transmit and receive block diagrams, re-

spectively.

Figure 1. Typical Dual Gigabit Ethernet Application

MAC

(ASIC)

S2062

DUAL

GIGABIT

ETHERNET

INTERFACE MAC

(ASIC)

TO SERIAL

BACKPLANE

S2068

GE INTERFACE SERIAL BP DRIVER

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 2. S2068 Input/Output Diagram

REFCLK

RATE

RESET

TCLKO

TXAP/N

TXBP/N

RXAP/N

RXBP/N

DINA[0:9]

DINB[0:9]

TBCA

TBCB

RBC1/0A

RBC1/0B

DOUTA[0:9]

DOUTB[0:9]

CLKSEL

TMODE

COM_DETA

COM_DETB

LPEN

CMODE

TESTMODE1

TESTMODE

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 3. Transmitter Block Diagram

DINA[0:9]

TMODE

Shift

Reg

DINB[0:9] 10

Shift

Reg

TBCB

DIN PLL

10x/20x

REFCLK

CLKSEL

RATE REFCLK

TCLKO

FIFO

(input)

FIFO

(input)

TBCA

TXAP

TXAN

TXABP

TXBP

TXBN

TXBBP

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 4. Receiver Block Diagram

DOUT CRU

Serial-

Parallel

DOUT CRU

Serial-

Parallel

DOUTA[0:9] RXAP

RXAN

RXBP

RXBN

DOUTB[0:9]

FIFO

(output)

TXBBP

TXABP

REFCLK

RBC1/0A 2

RBC1/0B 2

CMODE

RATE

FIFO

(output) 10

COM_DETA

COM_DETB

LPEN

TMODE

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

TRANSMITTER DESCRIPTION

The transmitter section of the S2068 contains a

single PLL which is used to generate the serial rate

transmit clock for all transmitters. Transmitter

functionalities shown schematically in Figure 3. Two

channels are provided with a variety of options re-

garding input clocking and loopback. The transmit-

ters operate at 1.250 GHz, 10 or 20 times the

reference clock frequency.

Data Input

The S2068 has been designed to simplify the paral-

lel interface data transfer and provides flexibility in

the clocking of parallel data. Prior implementations

of this function have either forced the user to syn-

chronize transmit data to the reference clock or to

provide the output clock as a reference to the PLL,

resulting in increased jitter at the serial interface.

The S2068 incorporates a unique FIFO structure

which enables the user to provide a “clean” refer-

ence source for the PLL and to accept a separate

external clock which is used exclusively to reliably

clock data into the device.

The S2068 also provides a system clock output,

TCLKO, which is derived from the internal VCO. The

frequency of this output is constant at the parallel

word rate, 1/10 the serial data rate, regardless of

whether the reference is provided at 1/10 or 1/20 the

serial data rate. This clock can be used by upstream

circuitry as a system clock. See Table 1.

Data to be input to the S2068 should be coded to

ensure transition density and DC balance. Data is

input to each channel of the S2068 as a 10 bit wide

word. An input FIFO and a clock input, TBCx, are

provided for each channel of the S2068. This device

can operate in two different modes. The S2068 can

be configured to use either the TBCx (TBC MODE)

input or the REFCLK input (REFCLK MODE). Table

2 provides a summary of the input modes for the

S2068.

Operation in the TBC MODE makes it easier for us-

ers to meet the relatively narrow setup and hold time

window required by the 125 Mbit/sec 10 bit interface.

The TBC signal is used to clock the data into an

internal holding register and the S2068 synchronizes

its internal data flow to ensure stable operation.

REFCLK, not TBCx, is used as the reference for the

transmit PLL. This ensures minimum jitter on the

high speed serial data stream.

ETARLESKLC KLCFER ycneuqerF tuptuOlaireS etaR 0KLCT ycneuqerF

00 01/RDSspbM052101/RDS

01 02/RDSspbM052101/RDS

10 01/RDSspbM52601/RDS

11 02/RDSspbM52601/RDS

Table 1. Operating Rates

REFCLK

S2068

125 MHz or 62.5 MHz

TBCx

DINx[0:9]

REF

OSCILLATOR

MAC

ASIC

TCLKO

PLL

Figure 5. DIN Clocking with TBC

Note that internal synchronization of FIFOs is performed upon

de-assertion of RESET.

EDOMTnoitarepO

0atadkcolcotdesuKLCFER.edoMKLCFER .slennahcllarofsOFIFotni

1sOFIFotniatadkcolcotdesuxCBT.edoMCBT .slennahcllarof

Table 2. Input Modes

Note: SDR = Serial Data Rate.

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

The TBC must be frequency locked to REFCLK, but

may have an arbitrary but fixed phase relationship.

Adjustment of internal timing of the S2068 is per-

formed during reset. Once synchronized, the S2068

can tolerate up to ±3ns of phase drift between TBC

and REFCLK.

Figure 5 demonstrates the flexibility afforded by the

S2068. A low jitter reference is provided directly to

the S2068 at either 1/10 or 1/20 the serial data rate.

This insures minimum jitter in the synthesized clock

used for serial data transmission. A system clock

output at the parallel word rate, TCLKO, is derived

from the PLL and provided to the upstream circuit as

a system clock. This clock can be buffered as re-

quired without concern about added delay. There is

no phase requirement placed upon TCLKO and the

TBCx clock, which is provided back to the S2068,

other than that they remain within ± 3ns of the phase

relationship established at reset.

The S2068 also supports the traditional REFCLK

clocking found in many Gigabit Ethernet applications

and is illustrated in Figure 6.

Half Rate Operation

The S2068 supports full and half rate operation for

all modes of operation. When RATE is LOW, the

S2068 serial data rate equals the VCO frequency.

When RATE is HIGH, the VCO is divided by two

before being provided to the chip. Thus, the S2068

can support Gigabit Ethernet and serial backplane

functions at full and half the VCO rate.

Parallel to Serial Conversion

The 10-bit parallel data handled by the S2068 device

should be from a DC-balanced encoding scheme,

such as the 8B/10B transmission code, in which in-

formation to be transmitted is encoded, 8 bits at a

time, into a 10-bit transmission character and must

be compliant with IEEE 802.3z Gigabit Ethernet.

The 8B/10B transmission code includes serial en-

coding and decoding rules, special characters, and

error control. Information is encoded, 8 bits at a time,

into a 10 bit transmission character. The characters

defined by this code ensure that short run lengths

and enough transitions are present in the serial bit

stream to make clock recovery possible at the re-

ceiver. The encoding also greatly increases the like-

lihood of detecting any single or multiple errors that

might occur during the transmission and reception of

data1.

Table 3 identifies the mapping of the 8B/10B charac-

ters to the data inputs of the S2068. The S2068 will

serialize the parallel data for each channel and will

transmit bit “a” or DIN[0] first.

Frequency Synthesizer (PLL)

The S2068 synthesizes a serial transmit clock from

the reference signal provided. The S2068 will obtain

phase and frequency lock within 2500 bit times after

the start of receiving reference clock inputs. Reliable

locking of the transmit PLL is assured, but a lock-

detect output is NOT provided.

Reference Clock Input

The reference clock input must be supplied with a

low-jitter clock source. All reference clocks in a sys-

tem must be within 200 ppm of each other to insure

that the clock recovery units can lock to the serial

data.

etyBataD

]9:0[TUODro]9:0[NID 0123456789

.rper.hplaB01/B8 abcdeifghj

Table 3. Data to 8B/10B Alphabetic Representation

1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-

anced (0,4) 8B/10B Transmission Code," IBM Research Report

RC9391, May 1982.

Figure 6. GE DIN Clocking with REFCLK

REFCLK

S2068

TBCx

DINx[0:9]

REF

OSCILLATOR

MAC

ASIC

TCLKO PLL

125 MHz

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

The frequency of the reference clock must be either

1/10 the serial data rate, CLKSEL = 0, or 1/20 the

serial data rate, CLKSEL = 1. Note that in both

cases, the frequency of the parallel word rate output,

TCLKO, is constant at 1/10 the serial data rate.

Serial Data Outputs

The S2068 provides LVPECL level serial outputs.

Each high speed output should be provided with a

resistor to VSS (Gnd) near the device. A value of

4.5KΩ provides optimal performance with minimum

impact on power dissipation. The resistance may be

as low as 450 Ω, but will dissipate additional power

with no substantive performance improvement.

Transmit FIFO Initialization

The transmit FIFO must be initialized after stable de-

livery of data and TBC to the parallel interface, and

before entering the normal operational state of the

circuit. FIFO initialization is performed upon the de-

assertion of the RESET signal. The TCLKO output will

operate normally even when RESET is asserted and

is available for use as an upstream clock source.

RECEIVER DESCRIPTION

Each receiver channel is designed to implement the

IEEE 802.3z Gigabit Ethernet receiver function

through the physical layer. A block diagram showing

the basic function is provided in Figure 4.

Whenever a signal is present, the receiver attempts

to recover the serial clock from the received data

stream. After acquiring bit synchronization, the

S2068 searches the serial bit stream for the occur-

rence of a K28.5 character on which to perform word

synchronization. Once synchronization on both bit

and word boundaries is achieved, the receiver pro-

vides the word-aligned data on its parallel outputs.

Data Input

A differential input receiver is provided for each

channel of the S2068. Each channel has a loopback

mode in which the serial data from the transmitter

replaces external serial data. The loopback function

for the two channels is controlled by the loopback

enable signal, LPEN.

The high speed serial inputs to the S2068 are inter-

nally biased to VDD-1.3V. This facilities AC-coupling

of the differential inputs and termination with a single

differential termination.

Clock Recovery Function

Clock recovery is provided for each channel of the

S2068. The receiver PLL has been optimized for the

needs of Gigabit Ethernet systems. A simple state

machine in the clock recovery macro decides whether

to acquire lock from the serial data input or from the

reference clock. The decision is based upon the fre-

quency and run length of the serial data inputs.

The run-length requirements insure that the S2068

will respond appropriately and quickly to a loss of

signal. The run-length checker looks for a minimum

of 120 consecutive ones or zeros. The checking is

done in parallel, thus 12 parallel words are exam-

ined.

An off-frequency detection circuit in the S2068 moni-

tors the receiver VCO frequency to insure that the

input signal is at a valid data rate. The data stream

must be within 200 ppm of the appropriate rate for

reliable locking of the CRU to the data stream.

If both the off-frequency test and the run-length test

are satisfied, the CRU will attempt to lock to the

incoming data. Note that if the run length test is sat-

isfied due to noise on the inputs, and no signal is

present, the receiver VCO will maintain frequency

accuracy to within 100 ppm of the target rate as

determined by the REFCLK.

In any transfer of PLL control from the serial data to

the reference clock, the RBC1/0x outputs remain

phase continuous and glitch free, assuring the integ-

rity of downstream clocking.

If at any time, the frequency or run length checks are

violated, the state machine forces the VCO to lock to

the reference clock. This is required to guarantee

that the VCO maintains the correct frequency in the

absence of data.

Reference Clock Input

The reference clock must be provided from a low

jitter clock source. The frequency of the received

data stream (divided by 10 or 20) must be within 200

ppm of the reference clock to insure reliable locking

of the receiver PLL. A single reference clock is pro-

vided to both the transmitter and the receiver of the

S2068.

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Serial-to-Parallel Conversion

Once bit synchronization has been attained by the

S2068 CRU, the S2068 must synchronize to the 10

bit word boundary. Word synchronization in the

S2068 is accomplished by detecting and aligning to

the 8B/10B K28.5 codeword. The S2068 will detect

and byte-align to either polarity of the K28.5. Each

channel of the S2068 will detect and align to a K28.5

anywhere in the data stream. The presence of a

K28.5 is indicated for each channel by the assertion

of the COM_DETx (Comma Detect) signal.

Data Output

Data is output on the DOUTx[0:9] outputs. The

COM_DETx signal is used to indicate the reception

of a valid K28.5 character and is driven concurrent

with the K28.5 character on the DOUTx[0:9] outputs.

The S2068 TTL outputs are optimized to drive 65Ω

line impedences. Internal source matching provides

good performance on unterminated lines of reason-

able length.

Parallel Output Clock Rate

Two output clock modes are supported. When

CMODE is HIGH, a complementary TTL clock at the

data rate is provided on the RBC1/0x outputs. Data

should be clocked on the rising edge of RBC1x.

When CMODE is LOW, the S2068 outputs a

complementary TTL clock at 1/2 the data rate in

compliance with the the Gigabit Ethernet Physical

Media Attachment (PMA) specification. Data should

be latched on the rising edge of RBC1x and the

rising edge of RBC0x.

If consecutive K28.5 characters are received, the

S2068 RBC1/0x clock operates without glitches or

loss of cycles.

edoMEDOMC.qerFx0/1CBR

edoMkcolCflaH0zHM5.26

edoMkcolClluF1zHM521

Table 4. Output Clock Modes

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

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PAXT NAXT .ffiD LCEPVL O61D 51E .AlennahCrofstuptuolairesdeepshgiH

PBXT NBXT .ffiD LCEPVL O51G 61G .BlennahCrofstuptuolairesdeepshgiH

OKLCTLTTO 41KrofdedivorpsikcolcsihT.etaratadlellarapehttakcolCtuptuOLTT .yrtiucricmaerts-puybesu

Table 6. Transmitter Output Signals Assignment and Descriptions

emaNniPleveLO/I#niPnoitpircseD

9ANID 8ANID 7ANID 6ANID 5ANID 4ANID 3ANID 2ANID 1ANID 0ANID

LTTI 51T 31R 21P 41T 21R 11P 31T 11R 21T 01P

dekcolcsisubsihtnoatadlellaraP.AlennahCrofataDtimsnarT .KLCFERroACBTfoegdegnisirehtnoni

ACBTLTTI 01Rdesusilangissiht,hgiHsiEDOMTnehW.AkcolCetyBtimsnarT ,woLsiEDOMTnehW.8602Sehtotni]9:0[ANIDnoataDkcolcot .derongisiACBT

9BNID 8BNID 7BNID 6BNID 5BNID 4BNID 3BNID 2BNID 1BNID 0BNID

LTTI51L 41L 61M 51M 41M 61N 51N 41N 61P 51P

nidekcolcsisubsihtnoatadlellaraP.BlennahCrofataDtimsnarT .KLCFERroBCBTfoegdegnisirehtno

BCBTLTTI 61Rdesusilangissiht,hgiHsiEDOMTnehW.BkcolCetyBtimsnarT ,woLsiEDOMTnehW.8602Sehtotni]9:0[BNIDnoataDkcolcot .derongisiBCBT

Table 5. Transmitter Input Signals Assignment and Descriptions

Note: All TTL inputs except REFCLK have internal pull-up networks.

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Table 7. Receiver Output Signals Assignment and Descriptions

emaNniPleveLO/I#niPnoitpircseD

9ATUOD 8ATUOD 7ATUOD 6ATUOD 5ATUOD 4ATUOD 3ATUOD 2ATUOD 1ATUOD 0ATUOD

LTTO2J2G2L1L2K1K3J1J3H2H

dilavsisubsihtnoatadlellaraP.stuptuOataDrevieceRAlennahC ehtnodilavdnaedomkcolcllufniA1CBRfoegdegnisirehtno .edomkcolcflahniA0CBRdnaA1CBRhtobfoegdegnisir

ATED_MOCLTTO1GatahtsetacidnituptuosihtnohgiHA.tceteDammoCAlennahC atadlellarapehtnotneserpsidnadetcetedneebsah5.82Kdilav .]9:0[ATUODstuptuo

A1CBR A0CBR LTTO1M3L dna]9:0[ATUOD,atadeviecerlellaraP.skcolCetyBevieceR llufninehwA1CBRfoegdegnisirehtnodilaveraATED_MOC dnaA1CBRhtobfoegdegnisirehtnodilavdnaedomkcolc .edomkcolcflahniA0CBR

9BTUOD 8BTUOD 7BTUOD 6BTUOD 5BTUOD 4BTUOD 3BTUOD 2BTUOD 1BTUOD 0BTUOD

LTTO4P1R8P5T6R6P5R3T5P3R

dilavsisubsihtnoatadlellaraP.stuptuOataDrevieceRBlennahC ehtnodilavdnaedomkcolcllufniB1CBRfoegdegnisirehtno .edomkcolcflahniB0CBRdnaB1CBRhtobfoegdegnisir

BTED_MOCLTTO2PatahtsetacidnituptuosihtnohgiHA.tceteDammoCBlennahC atadlellarapehtnotneserpsidnadetcetedneebsah5.82Kdilav .]9:0[BTUODstuptuo

B1CBR B0CBR LTTO7R7P dna]9:0[BTUOD,atadeviecerlellaraP.skcolCetyBevieceR llufninehwB1CBRfoegdegnisirehtnodilaveraBTED_MOC dnaB1CBRhtobfoegdegnisirehtnodilavdnaedomkcolc .edomkcolcflahniB0CBR

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

emaNniPleveLO/I#niPnoitpircseD

EDOMTSETLTTI3D.noitarepolamronrofwoLpeeK.lortnoCedoMtseT

1EDOMTSETLTTI61L.noitarepolamronrofwoLpeeK.lortnoCedoMtseT

EDOMTLTTI 31AdesusiKLCFER,woLsiEDOMTnehW.lortnoCedoMtimsnarT siEDOMTnehW.8602Sehtotni]9:0[xNIDnoatadkcolcot .8602SehtotniatadkcolcotdesusixCBT,hgiH

LESKLCLTTI 11BehtrofLLPehtserugifnoclangissihT.tupnItceleSKLCFER KLCFEReht,0=LESKLCnehW.ycneuqerfKLCFERetairporppa nehW.etardrowlellarapehtlauqedluohsycneuqerf lellarapeht2/1ebdluohsycneuqerfKLCFEReht,1=LESKLC .etaratad

KLCFERLTTI51JycneuqerfdnaOCVtimsnartehtrofdesusikcolCecnerefeR .atadlairesreviecerehtmorfderevocerkcolcehtrofkcehc

TESERLTTI 51BdecrofsiLLPreviecerehT.tesernidlehsi8602Seht,woLnehW egdegnisirehtnodezilaitinierasOFIFehT.KLCFERehtotkcolot .yllamronsetarepo8602Seht,hgiHnehW.TESERfo

ETARLTTI 11Clauqeetartuptuolairesehthtiwsetarepo8602Seht,woLnehW ehthtiwsetarepo8602Seht,hgiHnehW.ycneuqerfOCVehtot .snoitcnufllarof2ybdedividyllanretniOCV

Table 10. Mode Control Signal Assignment and Descriptions

Table 8. Receiver Input Signals Assignment and Descriptions

emaNniPleveLO/I#niPnoitpircseD

PAXR NAXR .ffiD LCEPVL I5B4A ehtsiPAXR.AlennahcrofstupnielbitapmocLCEPVLlaitnereffiD DDVotdesaibyllanretnI.evitagenehtsiNAXR,tupnievitisop .snoitacilppadelpuocCArofV3.1-

PBXR NBXR .ffiD LCEPVL I01B 11A ehtsiPBXR.BlennahcrofstupnielbitapmocLCEPVLlaitnereffiD DDVotdesaibyllanretnI.evitagenehtsiNBXR,tupnievitisop .snoitacilppadelpuocCArofV3.1-

Table 9. Receiver Control Signals Assignment and Descriptions

emaNniPleveLO/I#niPnoitpircseD

NEPLLTTI 41Cehtsilennahchcaerofecruostupni,woLnehW.elbanEkcabpooL hcaeroftuptuolaireseht,hgiHnehW.tuptuolairesdeepshgih .tupnistiotkcabdepoolsilennahc

EDOMCLTTI2Cskcolctuptuolellarapeht,woLnehW.lortnoCedoMkcolC lellarapeht,hgiHnehW.etaratadeht2/1slauqeetar)x0/1CBR( .etaratadehtotlauqesietar)x0/1CBR(skcolctuptuo

Note: All TTL inputs except REFCLK have internal pull-up networks.

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

emaNniP.ytQ#niPnoitpircseD

ADDV3 5C31B8B.esionwol)DDV(rewoPgolanA

ASSV3 31C4B8A.)SSV(dnuorGgolanA

DDV3 6C21B01A.)DDV(yrtiucricdeepshgihrofrewoP

SSV BUSSSV 821A7A5A3A 21C01C8C41A .)SSV(yrtiucricdeepshgihrofdnuorG

RWPLCEP2 61J41G.)DDV(rewoPLCEP

DNGLCEP3 61F51D61C.)SSV(dnuorGLCEP

RWPGID5 1N61K2D1C2B.)DDV(rewoPyrtiucriceroC

DNGGID8 41J3E2E1D3C 1T1P51K .)SSV(dnuorGyrtiucriceroC

RWPLTT9 3N2M1H3G1F 7T8R4R9P .)DDV(O/ILTTrofrewoP

DNGLTT113M3K3F2F1E 8T4T2T3P2N 11T

.)SSV(O/ILTTrofdnuorG

RWP4 9B1B61A2A.rewoP

DNG9 9C6B3B9A6A 61H51H51F61E .dnuorG

1PAC 2PAC 251A 41B .roticapacretlifpoollanretxerofsniP

CN027C4C61B7B1A 41F41E41D51C 2R41P31P41H 6T51R41R9R 61T01T9T

.tcennoCtoNoD.sniPtseTsadesU.detcennoctoN

Table 11. Power and Ground Signals Assignment and Descriptions

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 7. S2068 Pinout (Bottom View)

A B C D E F G H J K L M N P R T

1CNRWPRWPGIDDNGGIDDNGLTTRWPLTT _MOC ATED RWPLTT2ATUOD4ATUOD6ATUODA1CBRRWPGIDDNGGID8BTUODDNGGID

2RWPRWPGIDEDOMCRWPGIDDNGGIDDNGLTT8ATUOD0ATUOD9ATUOD5ATUOD7ATUODRWPLTTDNGLTT _MOC BTED CNDNGLTT

3BUSSSVDNGDNGGID TSET EDOM DNGGIDDNGLTTRWPLTT1ATUOD3ATUODDNGLTTA0CBRDNGLTTRWPLTTDNGLTT0BTUOD2BTUOD

4NAXRASSVCN 9BTUODRWPLTTDNGLTT

5SSVPAXRADDV 1BTUOD3BTUOD6BTUOD

6DNGDNGDDV 4BTUOD5BTUODCN

7BUSSSVCNCN B0CBRB1CBRRWPLTT

8ASSVADDVBUSSSV 7BTUODRWPLTTDNGLTT

9DNGRWPDNG RWPLTTCNCN

01 DDVPBXRSSV 0ANIDACBTCN

11 NBXRLESKLCETAR 4ANID2ANIDDNGLTT

21 BUSSSVDDVBUSSSV 7ANID5ANID1ANID

31 EDOMTADDVASSV CN8ANID3ANID

41 SSV2PACNEPLCNCNCNLCEP RWP CNDNGGIDOKLCT8BNID5BNID2BNIDCNCN6ANID

51 1PACTESERCNLCEP DNG NAXTDNGPBXTDNGKLCFERDNGGID9BNID6BNID3BNID0BNIDCN9ANID

61 RWPCNDNGLCEPPAXTDNG LCEP DNG NBXTDNG LCEP RWP RWPGID TSET 1EDOM 7BNID4BNID1BNIDBCBTCN

Note: NC used as Test Pins. Do Not Connect.

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 8. S2068 Pinout (Top View)

T R P N M L K J H G F E D C B A

DNGGID8BTUODDNGGIDRWPGIDA1CBR6ATUOD4ATUOD2ATUODRWPLTT _MOC ATED RWPLTTDNGLTTDNGGIDRWPGIDRWPCN1

DNGLTTCN_MOC BTED DNGLTTRWPLTT7ATUOD5ATUOD9ATUOD0ATUOD8ATUODDNGLTTDNGGIDRWPGIDEDOMCRWPGIDRWP 2

2BTUOD0BTUODDNGLTTRWPLTTDNGLTTA0CBRDNGLTT3ATUOD1ATUODRWPLTTDNGLTTDNGGID TSET EDOM DNGGIDDNGBUSSSV 3

DNGLTTRWPLTT9BTUOD CNASSVNAXR 4

6BTUOD3BTUOD1BTUOD ADDVPAXRSSV 5

CN5BTUOD4BTUOD DDVDNGDNG 6

RWPLTTB1CBRB0CBR CNCNBUSSSV 7

DNGLTTRWPLTT7BTUOD BUSSSVADDVASSV 8

CNCNRWPLTT DNGRWPDNG 9

CNACBT0ANID SSVPBXRDDV 01

DNGLTT2ANID4ANID ETARLESKLCNBXR 11

1ANID5ANID7ANID BUSSSVDDVBUSSSV 21

3ANID8ANIDCN ASSVADDVEDOMT 31

6ANIDCNCN2BNID5BNID8BNIDOKLCTDNGGIDCNLCEP RWP CNCNCNNEPL2PACSSV 41

9ANIDCN0BNID3BNID6BNID9BNIDDNGGIDKLCFERDNGPBXTDNGNAXT LCEP DNG CNTESER1PAC 51

CNBCBT1BNID4BNID7BNID TSET 1EDOM RWPGID LCEP RWP DNGNBXT LCEP DNG DNGPAXTDNGLCEPCNRWP 61

Note: NC used as Test Pins. Do Not Connect.

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 9. 156 TBGA Package

Device

S2068 19.8˚C/W

Θja

3.5˚C/W

Θjc

Thermal Management

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 11. Transmitter Timing (TBC Mode, TMODE = 1)

Table 13. S2068 Transmitter Timing (TBC Mode, TMODE = 1)

TBCx

DINx[0:9]

SERIAL DATA OUT

sretemaraPnoitpircseDniMxaMstinUsnoitidnoC

CBT.t.r.wputeSataD0.1sn.1etoNeeS

CBT.t.r.wdloHataD5.0sn

xCBTneewtebtfirdesahP KLCFERdna 3–3+sn

1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or

output data levels (.8V or 2.0V).

Figure 10. Transmitter Timing (REFCLK Mode, TMODE = 0)

Table 12. S2068 Transmitter Timing (REFCLK Mode, TMODE = 0)

1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or

output data levels (.8V or 2.0V).

REFCLK

DINx[0:9]

SERIAL DATA OUT

sretemaraPnoitpircseDniMxaMstinUsnoitidnoC

KLCFER.t.r.wputeSataD5.0sn.1etoNeeS

KLCFER.t.r.wdloHataD3.1sn

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

sretemaraPnoitpircseDniMxaMstinUsnoitidnoC

KLCFER.t.r.wOKLCT25.7sn

elcyCytuDOKLCT%04%06%

Note: Measurements are made at 1.4V level of clocks.

Table 15. S2068 Transmitter (TCLKO Timing)

REFCLK

TCLKO

Figure 12. TCLKO Timing

sretemaraPnoitpircseDniMxaMstinUsnoitidnoC

RDS

FDS

llaFdnaesiRataDlaireS003sp.sisabelpmasnodetset,%08-%02 k5.4 Ω.dnuorgot

rettijlatottuptuOataDlaireS )p-p( 291spelpmasnoderusaem,kaep-ot-kaeP 2ro5.82K±htiwderusaeM.sisab

.zHG52.1tanrettap

tuptuOataDlaireS )p-p(rettijcitsinimreted 08spelpmasanodetset,kaep-ot-kaeP nrettap5.82K±htiwderusaeM.sisab .zHG52.1ta

Table 14. Transmitter Timing

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 13. Receiver Timing (Full Clock Mode, CMODE = 1)

Table 16. S2068 Receiver Timing (Full Clock Mode, CMODE = 1)

Figure 14. Receiver Timing (Half Clock Mode, CMODE = 0)

Table 17. S2068 Receiver Timing (Half Clock Mode, CMODE = 0)

RBC0x

DOUTx[0:9],

COM_DETx

SERIAL DATA IN

RBC1x

1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or

output data levels (.8V or 2.0V).

RBC0x

DOUTx[0:9],

COM_DETx

SERIAL DATA IN

RBC1x

sretemaraPnoitpircseDniMxaMstinUsnoitidnoC

x1CBR.t.r.wputeSataD57.2sn.1etoNeeS

x1CBR.t.r.wdloHataD0.2sn

elcyCytuDx0/1CBR0406%

sretemaraPnoitpircseDniMxaMstinUsnoitidnoC

x0/1CBR.t.r.wputeSataD5.2sn.1etoNeeS

x0/1CBR.t.r.wdloHataD0.2sn

otesiRx1CBRmorfemiT esiRx0CBR 8.728.8sn

elcyCytuDx0/1CBR0406%

1. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or

output data levels (.8V or 2.0V).

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

OTHER OPERATING MODES

Loopback Mode

When loopback mode is enabled, the serial data

from the transmitter is provided to the serial input of

the receiver. Loopback mode can be simultaneously

enabled for both channels using the loopback-en-

able input, LPEN.

The loopback mode provides the ability to perform

system diagnostics and off-line testing of the inter-

face to guarantee the integrity of the serial channel

before enabling the transmission medium.

Note that the high speed outputs are disabled during

loopback operation.

Test Modes

The RESET pin is used to initialize the transmit

FIFOs and must be asserted (LOW) prior to entering

the normal operational state (see section Transmit

FIFO Initialization).

Operating Frequency Rate

The S2068 is designed to operate at the Gigabit

Ethernet rate of 1.250 GHz.

output

disabled

CRU

CSU

Figure 15. S2068 Diagnostic Loopback Operation

Table 18. S2068 Receiver Timing

sretemaraPnoitpircseDniMxaMstinUsnoitidnoC

RCR

FCR

emiTllaFdnaesiR0CBR,1CBR0.3sneeS.V0.2+otV8.+derusaeM .71erugiF

emiTllaFdnaesiRtuptuOataD0.3sneeS.V0.2+otV8.+derusaeM .61erugiF

KCOL

)ycneuqerF( emiTkcoLnoitisiuqcAycneuqerF )spbG52.1()kcoLfossoL( 571sµ.purewopretfA

ecnareloTrettiJtupnIlatoT995sp.z3.208EEEInideificepssA

ecnareloTrettiJtupnIcitsinimreteD073sp.z3.208EEEInideificepssA

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Table 19. Absolute Maximum Ratings

Table 20. Recommended Operating Conditions

Table 21. Reference Clock Requirements

retemaraPniMpyTxaMstinU

saiBrednUerutarepmeTesaC55–521C˚

saiBrednUerutarepmeTnoitcnuJ55–051C˚

erutarepmeTegarotS56–051C˚

DNGottcepseRhtiwDDVnoegatloV5.0–0.7+V

niPtupnILTTynanoegatloV5.0–74.3V

niPtupnILCEPynanoegatloV0DDVV

tnerruCkniStuptuOLTT8Am

tnerruCecruoStuptuOLTT8Am

tnerruCecruoStuptuOLCEPdeepShgiH03Am

O/ILTT,egatloVegrahcsiDcitatS0002V

O/ILCEP,egatloVegrahcsiDcitatS0051V

retemaraPniMpyTxaMstinU

saiBrednUerutarepmeTtneibmA007C˚

saiBrednUerutarepmeTnoitcnuJ031C˚

ottcepserhtiwniPrewoPynanoegatloV SSV/DNG 31.33.374.3V

niPtupnILTTynanoegatloV074.3V

niPtupnILCEPynanoegatloV DDV V2- DDVV

sretemaraPnoitpircseDniMxaMstinUsnoitidnoC

TFecnareloTycneuqerF001–001+mpp

2-1

yrtemmyS0406% .tp%05taelcyCytuD

RCR

FCR

emiTllaFdnaesiRKLCFER2sn.%08–%02

—rettiJ08sp.eyeatad%77,kaeP-ot-kaeP

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Table 22. DC Characteristics

sretemaraPnoitpircseDniMpyTxaMstinUsnoitidnoC

)LTT(egatloVhgiHtuptuO4.28.2DDVV Inim=DDV

Am4–=

)LTT(egatloVwoLtuptuODNG520.5.0V Inim=DDV

Am4=

)LTT(egatloVhgiHtupnI0.2V

)LTT(egatloVwoLtupnIDNG8.0V

)LTT(tnerruChgiHtupnI04AµV

xaM=DDV,V4.2=

)LTT(tnerruCwoLtupnI006AµV

xaM=DDV,V8.0=

DDItnerruCylppuS514335Am.nrettaP0101

noitapissiDrewoP73.148.1W .nrettaP0101

FFID

gniwsegatlovtupnilaitnereffid.niM stupniLCEPlaitnereffidrof 0010022Vm.91erugiFeeS

∆V

TUO

egatloVtuptuOlaireSlaitnereffiD gniwS 005100910022Vm

k5.4htiwdelpuocCA Ω

001dnanwodllup ΩeeS.noitanimretlaitnereffid .81erugiF

ecnaticapaCtupnI3fp

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

OUTPUT LOAD

The S2068 serial outputs require a resistive load to

set the output current. The recommended resistor

value is 4.5 kΩ to ground. This value can be varied

to adjust drive current, signal voltage swing, and

power usage on the board.

ACQUISITION TIME

With the input eye diagram shown in Figure 21, the

S2068 will recover data with a ≤1E-9 BER within the

time specified by TLOCK in Table 18 after an instan-

taneous phase shift of the incoming data.

Figure 19. High Speed Differential Inputs

Figure 16. Serial Input/Output Rise and Fall Time Figure 20. Receiver Input Eye Diagram Jitter Mask

Figure 17. TTL Input/Output Rise and Fall Time

Figure 18. Serial Output Load Figure 21. Acquisition Time Eye Diagram

80%

20%

50%

80%

20%

50%

+2.0V

+0.8V

+2.0V

+0.8V

4.5 kΩ

0.01 µf

Vcc -1.3 V

100 Ω

0.01 µf

Vcc - 1.3 V

Bit Time

Amplitude

24%

1.3

Normalized Amplitude

Normalized Time

1.0

0.0

0.2

0.3

0.5

0.7

0.8

0.1

0.6

0.4

0.3

0.7

0.9

1.0

0.0

S2068DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

Figure 22. Loop Filter Capacitor Connections

CAP1

270Ω

22 nf

CAP2

270Ω

S2068

S2068 DUAL GIGABIT ETHERNET TRANSCEIVER

October 13, 2000 / Revision D

AMCC is a registered trademark of Applied Micro Circuits Corporation.

D56/R248

AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and

advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied

on is current.

AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it

convey any license under its patent rights nor the rights of others.

AMCC reserves the right to ship devices of higher grade in place of those of lower grade.

AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR

USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121

Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885

http://www.amcc.com

Ordering Information

XXXXX X

Prefix Device Package

XIFERPECIVEDEGAKCAP

tiucriCdetargetnI–S8602AGBT651–BT