DATA SHEET MOS INTEGRATED CIRCUIT PD78P0308, 78P0308Y 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The PD78P0308 and 78P0308Y are members of the PD780308 and 780308Y Subseries of the 78K/0 Series, in which the on-chip mask ROM of the PD780308 and 780308Y is replaced with a one-time PROM. Because this device can be programmed by users, it is ideally suited for system evaluation, small-scale and multiple-device production, and early development and time-to-market. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD780308, 780308Y Subseries User's Manual: U11377E 78K/0 Series Instructions User's Manual: U12326E FEATURES * Pin-compatible with mask ROM version (except VPP pin) * Program memory (one-time PROM): 60 KBNote * Internal high-speed RAM: 1024 bytes * Internal expansion RAM: 1024 bytes * LCD display RAM: 40 x 4 bits * Supply voltage: VDD = 2.0 to 5.5 V Note The internal PROM capacity can be changed by setting the internal memory size switching register (IMS). Remark Refer to 1. DIFFERENCES BETWEEN PD78P0308, 78P0308Y AND MASK ROM VERSIONS for the difference between the one-time PROM and mask ROM versions. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U11776EJ2V1DS00 (2nd edition) Date Published August 2005 N CP(K) Printed in Japan The mark shows major revised points. 1996, 2003 PD78P0308, 78P0308Y ORDERING INFORMATION Part Number Package Internal ROM PD78P0308GC-8EU 100-pin plastic LQFP (fine pitch) (14 x 14) One-time PROM PD78P0308GC-8EU-A 100-pin plastic LQFP (fine pitch) (14 x 14) One-time PROM PD78P0308YGC-8EU 100-pin plastic LQFP (fine pitch) (14 x 14) One-time PROM PD78P0308YGC-8EU-A 100-pin plastic LQFP (fine pitch) (14 x 14) One-time PROM PD78P0308GF-3BA 100-pin plastic QFP (14 x 20) One-time PROM PD78P0308GF-3BA-A 100-pin plastic QFP (14 x 20) One-time PROM PD78P0308YGF-3BA 100-pin plastic QFP (14 x 20) One-time PROM PD78P0308YGF-3BA-A 100-pin plastic QFP (14 x 20) One-time PROM Remark Products that have the part numbers suffixed by "-A" are lead-free products. 2 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control EMI-noise reduced version of the PD78078 PD78075B PD78078 PD78070A PD78078Y PD78054 with timer and enhanced external interface PD78070AY 80-pin PD780058 PD780018AY PD780058Y ROMless version of the PD78078 PD78078Y with enhanced serial I/O and limited functions 80-pin PD78058F PD78054 PD780065 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 64-pin PD780078 64-pin 64-pin 52-pin PD780034A PD780024A PD780034AS 52-pin 64-pin PD780024AS PD78014H 64-pin 42/44-pin PD78018F PD78083 64-pin PD780988 PD78058FY PD78054 with enhanced serial I/O EMI-noise reduced version of the PD78054 PD78018F with UART and D/A converter, and enhanced I/O PD780024A with expanded RAM PD780034A with timer and enhanced serial I/O PD780078Y PD780034AY PD780024A with enhanced A/D converter PD780024AY PD78018F with enhanced serial I/O 52-pin version of the PD780034A PD78054Y 52-pin version of the PD780024A EMI-noise reduced version of the PD78018F PD78018FY Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V) Inverter control On-chip inverter controller and UART. EMI-noise reduced. VFD drive 78K/0 Series 100-pin PD780208 PD78044F with enhanced I/O and VFD C/D. Display output total: 53 80-pin For panel control. On-chip VFD C/D. Display output total: 53 80-pin PD780232 PD78044H 80-pin PD78044F Basic subseries for driving VFD. Display output total: 34 PD78044F with N-ch open-drain I/O. Display output total: 34 LCD drive PD780354 PD780344 PD780354Y PD780344 with enhanced A/D converter PD780344Y PD780308Y 100-pin PD780318 PD780308 PD78064B PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD780308 with enhanced display function and timer. PD78064 with enhanced SIO, and expanded ROM and RAM EMI-noise reduced version of the PD78064 100-pin PD78064 PD78064Y Basic subseries for driving LCDs, on-chip UART 100-pin 100-pin 120-pin 120-pin 120-pin 100-pin PD780338 PD780328 Segment signal output: 40 pins max. Segment signal output: 40 pins max. Segment signal output: 32 pins max. Segment signal output: 24 pins max. Bus interface supported 100-pin 80-pin PD780948 PD78098B PD78054 with IEBusTM controller PD780702Y PD780703AY PD780833Y 80-pin 80-pin 80-pin 64-pin On-chip CAN controller PD780816 On-chip IEBus controller On-chip CAN controller On-chip controller compliant with J1850 (Class 2) Specialized for CAN controller function Meter control 100-pin PD780958 80-pin PD780852 PD780828B 80-pin For industrial meter control On-chip automobile meter controller/driver For automobile meter driver. On-chip CAN controller Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. Data Sheet U11776EJ2V1DS 3 PD78P0308, 78P0308Y The major functional differences between the subseries are shown below. * Subseries without the suffix Y Function Subseries Name ROM Timer Capacity 8-Bit 16-Bit Watch WDT A/D A/D 4 ch 8 ch - PD78075B 32 KB to 40 KB Control PD78078 PD78070A 1 ch VDD External MIN. Expansion Value 1 ch 1 ch 88 1.8 V 61 2.7 V 3 ch (time-division UART: 1 ch) 68 1.8 V 3 ch (UART: 1 ch) 69 2.7 V Serial Interface D/A 2 ch 3 ch (UART: 1 ch) Yes 48 KB to 60 KB - PD780058 24 KB to 60 KB 2 ch PD78058F 48 KB to 60 KB PD78054 I/O 8-Bit 10-Bit 8-Bit 16 KB to 60 KB 2.0 V PD780065 40 KB to 48 KB - PD780078 48 KB to 60 KB 2 ch PD780034A 8 KB to 32 KB 1 ch - 8 ch PD780024A 8 ch - PD780034AS - 4 ch PD780024AS 4 ch - PD78014H 8 ch 4 ch (UART: 1 ch) 60 2.7 V 3 ch (UART: 2 ch) 52 1.8 V 3 ch (UART: 1 ch) 51 39 - 2 ch 53 Yes 1 ch (UART: 1 ch) 33 - PD78018F 8 KB to 60 KB PD78083 Inverter 8 KB to 16 KB - PD780988 16 KB to 60 KB 3 ch Note PD780208 32 KB to 60 KB 2 ch PD780232 16 KB to 24 KB PD78044H 32 KB to 48 KB - - 1 ch - 8 ch - 3 ch (UART: 2 ch) 47 4.0 V Yes 1 ch 1 ch 1 ch 8 ch - - 2 ch 74 2.7 V - 3 ch - - 4 ch 40 4.5 V 2 ch 1 ch 1 ch 8 ch 68 2.7 V 3 ch (UART: 1 ch) 66 1.8 V 10 ch 1 ch 2 ch (UART: 1 ch) 54 control VFD drive 1 ch PD78044F 16 KB to 40 KB LCD drive PD780354 24 KB to 32 KB 2 ch 4 ch 1 ch 1 ch 1 ch PD780344 PD780338 48 KB to 60 KB 3 ch 2 ch - 8 ch 8 ch - - - PD780328 62 PD780318 70 PD780308 48 KB to 60 KB 2 ch 1 ch 8 ch - - PD78064B 32 KB PD78064 Bus 3 ch (time-division UART: 1 ch) - 57 2.0 V 79 4.0 V Yes 69 2.7 V - 2 ch (UART: 1 ch) 16 KB to 32 KB PD780948 60 KB 2 ch 2 ch interface PD78098B 40 KB to 60 KB 1 ch supported PD780816 32 KB to 60 KB 2 ch 1 ch 1 ch 8 ch - - 3 ch (UART: 1 ch) 2 ch 12 ch - 2 ch (UART: 1 ch) 46 4.0 V Meter control PD780958 48 KB to 60 KB 4 ch 2 ch - 1 ch - - - 2 ch (UART: 1 ch) 69 2.2 V - Dashboard PD780852 32 KB to 40 KB 3 ch 1 ch 1 ch 1 ch 5 ch - - 3 ch (UART: 1 ch) 56 4.0 V - control PD780828B 32 KB to 60 KB Note 16-bit timer: 2 channels 59 10-bit timer: 1 channel 4 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y * Subseries with the suffix Y Function Subseries Name Control PD78078Y PD78070AY ROM Capacity 48 KB to 60 KB Timer 8-Bit 10-Bit 8-Bit 8-Bit 16-Bit Watch WDT A/D A/D 4 ch 8 ch - 1 ch 1 ch 1 ch I2C: 1 ch) PD780018AY 48 KB to 60 KB 24 KB to 60 KB PD78058FY - 2 ch Bus 3 ch (I2C: 1 ch) 88 1.8 V 61 2.7 V 48 KB to 60 KB 3 ch (UART: 1 ch, 2.7 V PD78054Y 16 KB to 60 KB I2C: 1 ch) PD780078Y 48 KB to 60 KB - 2 ch 8 KB to 60 KB PD780354Y 24 KB to 32 KB 4 ch 1 ch 1 ch PD780344Y 1 ch - 8 ch PD780308Y 48 KB to 60 KB PD78064Y 16 KB to 32 KB PD780702Y 60 KB - 1 ch 8 ch PD78018FY 8 ch Yes 69 2.0 V 4 ch (UART: 2 ch, I2C: 1 ch) 52 3 ch (UART: 1 ch, 51 1.8 V I2C: 1 ch) - 8 ch External 88 1.8 V PD780024AY drive VDD 2 ch 3 ch (time-division 68 UART: 1 ch, I2C: 1 ch) PD780034AY 8 KB to 32 KB LCD I/O MIN. Value Expansion 2 ch 3 ch (UART: 1 ch, - PD780058Y Serial Interface D/A - 2 ch (I2C: 1 ch) 53 4 ch (UART: 1 ch, 66 1.8 V 3 ch (time-division 57 UART: 1 ch, I2C: 1 ch) 2.0 V - I2C: 1 ch) - 2 ch 2 ch (UART: 1 ch, I2C: 1 ch) 3 ch 2 ch 1 ch 1 ch 16 ch - - 4 ch (UART: 1 ch, 67 3.5 V 65 4.5 V - I2C: 1 ch) interface PD780703AY 59.5 KB supported PD780833Y 60 KB Remark The functions of the subseries without the suffix Y and the subseries with the suffix Y are the same, except for the serial interface (if a subseries without the suffix Y is available). Data Sheet U11776EJ2V1DS 5 PD78P0308, 78P0308Y OVERVIEW OF FUNCTIONS PD78P0308 Item Internal memory One-time PROM 60 KBNote High-speed RAM 1024 bytes Expansion RAM 1024 bytes LCD display RAM 40 x 4 bits General-purpose registers Minimum instruction execution time When main system PD78P0308Y 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time variable function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (@ 5.0 MHz operation) clock is selected When subsystem 122 s (@ 32.768 kHz operation) clock is selected Instruction set * 16-bit operation * Multiply/divide (8 bits x 8 bits, 16 bits / 8 bits) * Bit manipulation (set, reset, test, Boolean operation) * BCD adjustment, etc. I/O ports (Segment signal output pins included) A/D converter LCD controller/driver Total: 57 * CMOS input: 2 * CMOS I/O: 55 8-bit resolution x 8 channels * Segment signal output: 40 pins maximum * Common signal output: 4 pins maximum * Bias: Serial interface 1/2,1/3 bias convertible * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable: 1 channel * 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable: 1 channel * 3-wire serial I/O/UART mode selectable: 1 channel * 3-wire serial I/O mode: Timer 1 channel * 16-bit timer/event counter: 1 channel * 8-bit timer/event counter: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel Timer output 3 pins (14-bit PWM output enable: 1 pin) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0 MHz operation with main system clock) 32.768 kHz (@ 32.768 kHz operation with subsystem clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz (@ 5.0 MHz operation with main system clock) Note The internal PROM capacity can be changed by setting the internal memory size switching register (IMS). 6 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y PD78P0308 Item Vectored Maskable interrupt sources Non-maskable Internal: 1 Software 1 PD78P0308Y Internal: 13, External: 6 Test input Internal: 1, External: 1 Supply voltage VDD = 2.0 to 5.5 V Package * 100-pin plastic LQFP (fine pitch) (14 x 14) * 100-pin plastic QFP (14 x 20) Data Sheet U11776EJ2V1DS 7 PD78P0308, 78P0308Y PIN CONFIGURATIONS (TOP VIEW) (1) Normal operating mode P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P16/ANI6 P17/ANI7 VDD0 AVREF P100 P101 VSS1 P102 P103 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 COM0 COM1 COM2 P110/S13 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1/TI01 P00/INTP0/TI00 RESET XT2 XT1/P07 VDD1 X1 X2 VPP P72/SCK2/ASCK P71/SO2/TXD P10/ANI0 AVSS P117 P116 P115 P114/RXD P113/TXD P112/SCK3 P111/SO3 * 100-pin plastic LQFP (fine pitch) (14 x 14) 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 14 63 62 15 61 16 60 17 59 18 58 19 57 20 21 56 55 22 23 54 53 24 52 25 51 P70/SI2/RxD P27/SCK0[/SCL] P26/SO0/SB1[/SDA1] P25/SI0/SB0[/SDA0] P80/S39 P81/S38 P82/S37 P83/S36 P84/S35 P85/S34 P86/S33 P87/S32 P90/S31 P91/S30 P92/S29 P93/S28 P94/S27 P95/S26 P96/S25 P97/S24 S23 S22 S21 S20 S19 Cautions 1. 2. S18 S11 S12 S13 S14 S15 S16 S17 S9 S10 VLC2 VSS0 S0 S1 S2 S3 S4 S5 S6 S7 S8 COM3 BIAS VLC0 VLC1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Connect the VPP pin directly to VSS0 or VSS1. Connect the AVSS pin to VSS0. Remarks 1. [ ]: PD78P0308Y only 2. When the device is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. 8 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y S22 S21 S23 P97/S24 P96/S25 P95/S26 P94/S27 P93/S28 P92/S29 P91/S30 P90/S31 P87/S32 P86/S33 P85/S34 P84/S35 P83/S36 P82/S37 P81/S38 P80/S39 P25/SI0/SB0[/SDA0] * 100-pin plastic QFP (14 x 20) P26/SO0/SB1[/SDA1] 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 P27/SCK0[/SCL] 2 79 P70/SI2/RXD 3 78 S19 S18 S20 S11 11 70 S10 RESET 12 69 S9 P00/INTP0/TI00 13 68 S8 P01/INTP1/TI01 14 67 S7 P02/INTP2 15 66 S6 P03/INTP3 16 65 S5 P04/INTP4 17 64 S4 P05/INTP5 18 63 S3 P110/SI3 19 62 S2 P111/SO3 20 61 S1 P112/SCK3 21 60 S0 P113/TXD 22 59 VSS0 P114/RXD 23 58 VLC2 P115 24 57 VLC1 P116 25 56 VLC0 P117 26 55 BIAS AVSS 27 54 COM3 P10/ANI0 28 53 COM2 P11/ANI1 29 52 COM1 P12/ANI2 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 COM0 Cautions 1. 2. P37 71 P36/BUZ 10 P35/PCL S12 XT1/P07 XT2 P34/TI2 72 P33/TI1 9 P31/TO1 P32/TO2 S13 VDD1 P30/TO0 73 P103 8 P102 S14 X1 VSS1 X2 P101 S15 74 P100 75 7 AVREF 6 VDD0 VPP P17/ANI7 S16 P16/ANI6 S17 76 P15/ANI5 77 5 P14/ANI4 4 P13/ANI3 P71/SO2/TXD P72/SCK2/ASCK Connect the VPP pin directly to VSS0 or VSS1. Connect the AVSS pin to VSS0. Remarks 1. [ ]: PD78P0308Y only 2. When the device is used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. Data Sheet U11776EJ2V1DS 9 PD78P0308, 78P0308Y ANI0 to ANI7: Analog input RxD: Receive data ASCK: Asynchronous serial clock S0 to S39: Segment output AVREF: Analog reference voltage SB0, SB1: Serial bus AVSS: Analog ground SCK0, SCK2, SCK3: Serial clock BIAS: LCD power supply bias control SCL: Serial clock BUZ: Buzzer clock SDA0, SDA1: Serial data SI0, SI2, SI3: Serial input INTP0 to INTP5: External interrupt input SO0, SO2, SO3: Serial output P00 to P05, P07: Port 0 TI00, TI01: Timer input P10 to P17: Port 1 TI1, TI2: Timer input P25 to P27: Port 2 TO0 to TO2: Timer output P30 to P37: Port 3 TxD: Transmit data P70 to P72: Port 7 VDD0, VDD1: Power supply COM0 to COM3: Common output P80 to P87: Port 8 VLC0 to VLC2: LCD power supply P90 to P97: Port 9 VPP: Programming power supply P100 to P103: Port 10 VSS0, VSS1: Ground P110 to P117: Port 11 X1, X2: Crystal (main system clock) PCL: Programmable clock XT1, XT2: Crystal (subsystem clock) RESET: Reset 10 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y (2) PROM programming mode (L) VDD VDD (L) VSS (L) D0 D1 D2 D3 D4 D5 D6 D7 (L) (L) VDD (L) Open VPP RESET Open (L) PGM (L) A9 (L) CE OE (L) * 100-pin plastic LQFP (fine pitch) (14 x 14) 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 14 63 62 15 61 16 60 17 59 18 58 19 57 20 21 56 55 22 23 54 53 24 52 25 51 (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) (L) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Cautions 1. (L): Independently connect to VSS via a pull-down resistor. 2. VSS: Connect to GND. 3. RESET: Set to low level. 4. Open: Leave open. Data Sheet U11776EJ2V1DS 11 PD78P0308, 78P0308Y (L) (L) A0 A1 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 A14 A15 (L) * 100-pin plastic QFP (14 x 20) 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 2 79 3 78 74 8 73 9 72 10 71 11 70 RESET A9 (L) 12 69 13 68 14 67 PGM 15 66 16 65 17 64 18 63 OE 19 62 CE 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (L) (L) (L) Cautions 1. (L): Independently connect to VSS via a pull-down resistor. 2. VSS: Connect to GND. 3. RESET: Set to low level. 4. Open: 12 (L) D0 D1 D2 D3 D4 D5 D6 D7 75 7 (L) 6 VPP Open (L) VDD (L) Open VSS 76 (L) 77 5 VDD VDD 4 Leave open. A0 to A16: Address bus RESET: Reset CE: Chip enable VDD: Power supply D0 to D7: Data bus VPP: Programming power supply OE: Output enable VSS: Ground PGM: Program Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y BLOCK DIAGRAM TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 P00 16-bit timer/ event counter Port 0 P01 to P05 P07 TO1/P31 TI1/P33 TO2/P32 TI2/P34 8-bit timer/event counter 1 Port 1 P10 to P17 Port 2 P25 to P27 Port 3 P30 to P37 Port 7 P70 to P72 Port 8 P80 to P87 Port 9 P90 to P97 8-bit timer/event counter 2 Watchdog timer Watch timer SI0/SB0[/SDA0]/P25 SO0/SB1[/SDA1]/P26 Serial interface 0 SCK0[/SCL]/P27 78K/0 CPU core SI2/RxD/P70 SO2/TxD/P71 RxD/P114 PROM (60 KB) Serial interface 2 TxD/P113 SCK2/ASCK/P72 SI3/P110 SO3/P111 Port 10 P100 to P103 Port 11 P110 to P117 Serial interface 3 SCK3/P112 S0 to S23 RAM (2048 bytes) ANI0/P10 to ANI7/P17 AVSS A/D converter S24/P97 to S31/P90 S32/P87 to S39/P80 LCD controller/driver AVREF COM0 to COM3 VLC0 to VLC2 INTP0/P00 to INTP5/P05 Interrupt control BUZ/P36 Buzzer output PCL/P35 Clock output control BIAS fLCD System control VDD0, VDD1 VSS0, VSS1 VPP RESET X1 X2 XT1/P07 XT2 Remark [ ]: PD78P0308Y only Data Sheet U11776EJ2V1DS 13 PD78P0308, 78P0308Y CONTENTS 1. DIFFERENCES BETWEEN PD78P0308, 78P0308Y AND MASK ROM VERSIONS ................. 15 2. PIN FUNCTIONS ............................................................................................................................ 2.1 Pins in Normal Operating Mode ......................................................................................... 2.2 Pins in PROM Programming Mode ..................................................................................... 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ................................... 16 16 19 20 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ......................................................... 24 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ........................................... 25 5. PROM PROGRAMMING ................................................................................................................ 5.1 Operating Modes .................................................................................................................. 5.2 PROM Write Procedure........................................................................................................ 5.3 PROM Read Procedure ........................................................................................................ 26 26 28 32 6. ONE-TIME PROM VERSION SCREENING ................................................................................... 32 7. ELECTRICAL SPECIFICATIONS .................................................................................................. 33 8. PACKAGE DRAWINGS ................................................................................................................. 61 9. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 63 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 65 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 71 14 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y 1. DIFFERENCES BETWEEN PD78P0308, 78P0308Y AND MASK ROM VERSIONS The PD78P0308 and 78P0308Y are single-chip microcontrollers with an on-chip one-time PROM to which a program can be written only once. It is possible to make all the functions except for the PROM specifications and the mask option of LCD drive power supply dividing resistor the same as those of mask ROM versions by setting the internal memory size switching register (IMS). Differences between the one-time PROM versions (PD78P0308, 78P0308Y) and mask ROM versions (PD780306, 780308, 780306Y, 780308Y) are shown in Table 1-1. Table 1-1. Differences Between PD78P0308, 78P0308Y and Mask ROM Versions PD78P0308 Item PD78P0308Y Mask ROM Versions PD780308 Subseries PD780308Y Subseries Internal ROM configuration One-time PROM Mask ROM Internal ROM capacity 60 KB PD780306, 780306Y: 48 KB Internal ROM capacity change PossibleNote Impossible No Yes PD780308, 780308Y: 60 KB by the internal memory size switching register (IMS) IC pin VPP pin Yes No Mask options of LCD drive None Available power supply dividing resistor Serial interface (SBI) Provided Not provided Provided Not provided Serial interface (I2C) Not provided Provided Not provided Provided Electrical specifications, Refer to the data sheet of the individual product. recommended soldering conditions Note The internal PROM capacity is set to 60 KB by RESET input. Caution There are differences in noise immunity and noise radiation between the one-time PROM and mask ROM versions. When pre-producing an application set with a one-time PROM version and then mass-producing it with a mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering samples (ES)) of the mask ROM version. Data Sheet U11776EJ2V1DS 15 PD78P0308, 78P0308Y 2. PIN FUNCTIONS 2.1 Pins in Normal Operating Mode (1) Port pins (1/2) Pin Name I/O Function After Reset Alternate Function P00 Input Port 0 Input only Input INTP0/TI00 P01 I/O 7-bit I/O port Input/output can be specified Input INTP1/TI01 P02 in 1-bit units. When used as INTP2 P03 the input port, on-chip pull-up INTP3 P04 resistor connection can be INTP4 P05 specified by software settings. P07Note 1 Input P10 to P17 I/O Input only Port 1 INTP5 Input XT1 Input ANI0 to ANI7 Input SI0/SB0[/SDA0] 8-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings.Note 2 P25 I/O Port 2 3-bit I/O port P26 SO0/SB1[/SDA1] Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor P27 SCK0[/SCL] connection can be specified by software settings. P30 I/O Port 3 Input TO0 P31 8-bit I/O port TO1 P32 Input/output can be specified in 1-bit units. TO2 P33 When used as the input port, on-chip pull-up resistor TI1 P34 connection can be specified by software settings. TI2 P35 PCL P36 BUZ P37 -- Notes 1. When the P07/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to 1, and be sure not to use the feedback resistor of the subsystem clock oscillator. 2. When the P10/ANI0 to P17/ANI7 pins are used as the analog inputs for the A/D converter, shift port 1 to input mode. The on-chip pull-up resistors are automatically disabled. Remark [ ]: PD78P0308Y only 16 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y (1) Port pins (2/2) Pin Name P70 I/O I/O Function Port 7 After Reset Input Alternate Function SI2/RXD 3-bit I/O port P71 SO2/TXD Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor P72 SCK2/ASCK connection can be specified by software settings. P80 to P87 I/O Port 8 Input S39 to S32 Input S31 to S24 Input -- 8-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. The I/O port/segment signal output function is specifiable in 2-bit units by the LCD display control register (LCDC). P90 to P97 I/O Port 9 8-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. The I/O port/segment signal output function is specifiable in 2-bit units by the LCD display control register (LCDC). P100 to P103 I/O Port 10 4-bit I/O port Input/output can be specified in 1-bit units. When used as the input port, on-chip pull-up resistor connection can be specified by software settings. It is possible to directly drive LEDs. P110 I/O Port 11 Input SI3 P111 8-bit I/O port SO3 P112 Input/output can be specified in 1-bit units. SCK3 P113 When used as the input port, on-chip pull-up resistor T XD P114 connection can be specified by software settings. R XD P115 to P117 Falling edge detection is possible. Data Sheet U11776EJ2V1DS -- 17 PD78P0308, 78P0308Y (2) Non-port pins (1/2) Pin Name INTP0 I/O Input Function After Reset External interrupt request input for which the valid edge Input Alternate Function P00/TI00 INTP1 (rising edge, falling edge, or both rising and falling edges) P01/TI01 INTP2 can be specified. P02 INTP3 P03 INTP4 P04 INTP5 SI0 P05 Input Serial interface serial data input. Input P25/SB0[/SDA0] SI2 P70/RxD SI3 SO0 P110 Output Serial interface serial data output. Input P26/SB1[/SDA1] SO2 P71/TxD SO3 SB0 P111 I/O Serial interface serial data input/output. Input P25/SI0[/SDA0] SB1 P26/SO0[/SDA1] PD78P0308Y only SDA0 P25/SI0/SB0 SDA1 SCK0 P26/SO0/SB1 I/O Serial interface serial clock input/output. Input P27[/SCL] SCK2 P72/ASCK SCK3 P112 PD78P0308Y only SCL RxD Input TxD ASCK TI00 P27/SCK0 Asynchronous serial interface serial data input. Input P70/SI2, P114 Output Asynchronous serial interface serial data output. Input P71/SO2, P113 Input Asynchronous serial interface serial clock input. Input P72/SCK2 Input External count clock input to 16-bit timer (TM0). Input P00/INTP0 TI01 Capture trigger signal input to capture register (CR00). P01/INTP1 TI1 External count clock input to 8-bit timer (TM1). P33 TI2 External count clock input to 8-bit timer (TM2). P34 TO0 Output TO1 TO2 PCL 16-bit timer (TM0) output (also used for 14-bit PWM output). Input P30 8-bit timer (TM1) output. P31 8-bit timer (TM2) output. Output Clock output (for main system clock, subsystem clock P32 Input P35 P36 trimming). BUZ Output Buzzer output. Input S0 to S23 Output LCD controller/driver segment signal output. Output S24 to S31 Input -- P97 to P90 S32 to S39 P87 to P80 COM0 to COM3 Output LCD controller/driver common signal output. VLC0 to VLC2 -- LCD drive voltage. -- -- BIAS -- LCD drive power supply. -- -- Remark [ ]: PD78P0308Y only 18 Data Sheet U11776EJ2V1DS Output -- PD78P0308, 78P0308Y (2) Non-port pins (2/2) Pin Name I/O Function ANI0 to ANI7 Input A/D converter analog input. AVREF Input A/D converter reference voltage input After Reset Input Alternate Function P10 to P17 -- -- A/D converter ground potential. Set to the same potential as VSS0. -- -- -- (also used for analog power supply). AVSS -- RESET Input System reset input. -- X1 Input Crystal resonator connection for main system clock -- -- X2 -- oscillation. -- -- XT1 Input XT2 -- Crystal resonator connection for subsystem clock oscillation. Input P07 VDD0 -- Positive power supply for ports. -- -- VSS0 -- Ground potential for ports. -- -- VDD1 -- Positive power supply (except for ports and analog). -- -- VSS1 -- Ground potential (except for ports and analog). -- -- VPP -- High voltage application in program write/verify mode. -- -- -- -- Connect directly to VSS0 or VSS1 in normal operating mode. 2.2 Pins in PROM Programming Mode Pin Name RESET I/O Input Function PROM programming mode setting. When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode. VPP Input PROM programming mode setting and high voltage application during program write/verification. A0 to A16 Input Address bus. D0 to D7 I/O Data bus. CE Input PROM enable input/program pulse input. OE Input Read strobe input to PROM. PGM Input Program/program inhibit input in PROM programming mode. VDD -- Positive power supply. VSS -- Ground potential. Data Sheet U11776EJ2V1DS 19 PD78P0308, 78P0308Y 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The types of pin I/O circuits and the recommended connection of unused pins are shown in Table 2-1. For the configuration of each type of I/O circuit, see Figure 2-1. Table 2-1. Type of I/O Circuit of Each Pin (1/2) Pin Name I/O Circuit Type P00/INTP0/TI00 2 P01/INTP1/TI01 8-C I/O Recommended Connection of Unused Pins Input Connect to VSS0. I/O Input: P02/INTP2 Independently connect to VSS0 via a resistor. Output: Leave open. P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 16 P10/ANI0 to P17/ANI7 11-B P25/SI0/SB0[/SDA0] 10-B Input Connect to VDD0. I/O Input: Independently connect to VDD0 or VSS0 via a resistor. Output: Leave open. P26/SO0/SB1[/SDA1] P27/SCK0[/SCL] P30/TO0 5-H P31/TO1 P32/TO2 P33/TI1 8-C P34/TI2 P35/PCL 5-H P36/BUZ P37 P70/SI2/RXD 8-C P71/SO2/TXD 5-H P72/SCK2/ASCK 8-C P80/S39 to P87/S32 17-C P90/S31 to P97/S24 P100 to P103 5-H P110/SI3 8-C Input: P111/SO3 Independently connect to VDD0 via a resistor. Output: Leave open. P112/SCK3 P113/TXD P114/RXD P115 to P117 S0 to S23 17-B COM0 to COM3 18-A Output Leave open. Remark [ ]: PD78P0308Y only 20 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y Table 2-1. Type of I/O Circuit of Each Pin (2/2) Pin Name I/O Circuit Type I/O -- -- RESET 2 Input XT2 16 -- Leave open. AVREF -- -- Connect to VSS0. VLC0 to VLC2 Recommended Connection of Unused Pins Leave open. BIAS -- AVSS VPP Connect directly to VSS0 or VSS1. Data Sheet U11776EJ2V1DS 21 PD78P0308, 78P0308Y Figure 2-1. List of Pin I/O Circuits (1/2) Type 2 Type 10-B VDD0 Pull-up enable P-ch IN VDD0 Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Open drain Output disable N-ch VSS0 VDD0 Type 5-H Pull-up enable Pull-up enable P-ch VDD0 Data P-ch VDD0 P-ch Data IN/OUT P-ch IN/OUT Output disable VDD0 Type 11-B Output disable N-ch P-ch N-ch Comparator VSS0 VSS0 + - AVSS N-ch VREF (threshold voltage) Input enable Input enable Type 8-C Type 16 VDD0 Pull-up enable Feedback cut-off P-ch P-ch VDD0 Data P-ch IN/OUT Output disable N-ch VSS0 22 XT1 Data Sheet U11776EJ2V1DS XT2 PD78P0308, 78P0308Y Figure 2-1. List of Pin I/O Circuits (2/2) Type 17-C Type 17-B VDD0 VLC0 P-ch VLC1 Pull-up enable N-ch P-ch P-ch VDD0 SEG data OUT P-ch Data P-ch N-ch IN/OUT VLC2 Output disable N-ch N-ch VSS0 VSS1 Input enable Type 18-A VLC0 P-ch VLC0 VLC1 VLC1 P-ch N-ch P-ch N-ch COM data P-ch N-ch N-ch P-ch SEG data OUT P-ch N-ch VLC2 N-ch P-ch VLC2 N-ch VSS1 VSS1 Data Sheet U11776EJ2V1DS 23 PD78P0308, 78P0308Y 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) This is a register used to disable use of part of the internal memory by software. By setting the internal memory size switching register (IMS), it is possible to get the same memory map as that of the mask ROM versions with a different internal memory (ROM) capacity. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 3-1. Format of Internal Memory Size Switching Register Symbol IMS 7 6 5 4 3 2 1 0 Address RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 FFF0H After reset CFH R/W R/W ROM3 ROM2 ROM1 ROM0 Internal ROM capacity selection 1 1 0 0 48 KB 1 1 1 1 60 KB Other than above RAM2 RAM1 RAM0 1 1 0 Other than above Setting prohibited Internal high-speed RAM capacity selection 1024 bytes Setting prohibited Table 3-1 shows the setting values of IMS that make the memory mapping the same as that of the mask ROM versions. Table 3-1. Internal Memory Size Switching Register Setting Values Target Mask ROM Versions 24 IMS Setting Value PD780306, 780306Y CCH PD780308, 780308Y CFH Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) This register is used to set the internal expansion RAM capacity by software. By setting the internal expansion RAM size switching register (IXS), it is possible to get the same memory map as that of the mask ROM versions with a different internal expansion RAM capacity. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0AH. Figure 4-1. Format of Internal Expansion RAM Size Switching Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W IXS 0 0 0 0 IXRAM3 IXRAM2 IXRAM1 IXRAM0 FFF4H 0AH W IXRAM3 IXRAM2 IXRAM1 IXRAM0 Internal expansion RAM capacity selection 1 0 1 Other than above 0 1024 bytes Setting prohibited Table 4-1 shows the setting values of IXS that make the memory mapping the same as that of the mask ROM versions. Table 4-1. Internal Expansion RAM Size Switching Register Setting Values Target Mask ROM Versions PD780306, 780306Y IXS Setting Value 0AH PD780308, 780308Y Data Sheet U11776EJ2V1DS 25 PD78P0308, 78P0308Y 5. PROM PROGRAMMING The PD78P0308 and 78P0308Y have an on-chip 60 KB PROM as a program memory. For programming, set the PROM programming mode with the VPP and RESET pins. For the connection of unused pins, refer to PIN CONFIGURATIONS (2) PROM programming mode. Caution Programs must be written in addresses 0000H to EFFFH (the last address EFFFH must be specified). They cannot be written by a PROM programmer that cannot specify the write address. 5.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE, and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM. Table 5-1. Operating Modes of PROM Programming Pin RESET VPP VDD L +12.5 V +6.5 V CE OE PGM D0 to D7 Operating Mode Page data latch H L H Data input Page write H H L High-impedance Byte write L H L Data input Program verify L L H Data output x H H High-impedance x L L Program inhibit Read L L H Data output Output disable +5 V +5 V L H x High-impedance Standby H x x High-impedance x: L or H 26 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y (1) Read mode Read mode is set if CE = L, OE = L is set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, data can be read from any device by controlling the OE pin, if multiple PD78P0308 and 78P0308Ys are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data outputs become high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode. In this mode, 1-page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1 ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed, if CE = L, OE = L are set. If programming is not performed by a one-time program pulse, write and verification operations should be executed X times (X 10) repeatedly. (6) Byte write mode Byte write is executed when a 0.1 ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then, program verification can be performed if OE = L is set. If programming is not performed by a one-time program pulse, write and verification operations should be executed X times (X 10) repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if the write operation was performed correctly after the write. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple PD78P0308 and 78P0308Ys are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device whose PGM pin is driven high. Data Sheet U11776EJ2V1DS 27 PD78P0308, 78P0308Y 5.2 PROM Write Procedure Figure 5-1. Page Program Mode Flow Chart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X=X+1 X = 10 ? 0.1 ms program pulse Verify 4 bytes Yes Fail Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All pass Write end G = Start address N = Program last address 28 Data Sheet U11776EJ2V1DS Defective product PD78P0308, 78P0308Y Figure 5-2. Page Program Mode Timing Page data latch Page program Program verify A2 to A16 A0, A1 Hi-Z D0 to D7 Data input Data output VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Data Sheet U11776EJ2V1DS 29 PD78P0308, 78P0308Y Figure 5-3. Byte Program Mode Flow Chart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 X=X+1 No X = 10 ? 0.1 ms program pulse Yes Address = Address + 1 Fail Verify Pass No Address = N ? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All pass Write end G = Start address N = Program last address 30 Data Sheet U11776EJ2V1DS Defective product PD78P0308, 78P0308Y Figure 5-4. Byte Program Mode Timing Program Program verify A0 to A16 D0 to D7 Hi-Z Data input Data output VPP VPP VDD VDD VDD + 1.5 VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. VDD should be applied before VPP, and cut after VPP. 2. VPP should not exceed +13.5 V, including overshoot. 3. Disconnection during application of +12.5 V to VPP may have an adverse effect on reliability. Data Sheet U11776EJ2V1DS 31 PD78P0308, 78P0308Y 5.3 PROM Read Procedure The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown below. (1) Fix the RESET pin to low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in PIN CONFIGURATIONS (2) PROM programming mode. (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of the data to be read to the A0 to A16 pins. (4) Read mode (5) Output data to the D0 to D7 pins. The timing of steps (2) to (5) above is shown in Figure 5-5. Figure 5-5. PROM Read Timing A0 to A16 Address input CE (input) OE (input) D0 to D7 Hi-Z Data output Hi-Z 6. ONE-TIME PROM VERSION SCREENING The one-time PROM versions cannot be tested completely by NEC Electronics before they are shipped, because of their structure. It is recommended to perform screening to verify PROM after writing the necessary data and performing high-temperature storage under the conditions below. 32 Storage Temperature Storage Time 125C 24 hours Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol Ratings Unit VDD Conditions -0.3 to +7.0 V VPP -0.3 to +13.5 V AVREF -0.3 to VDD + 0.3 V AVSS Input voltage VI1 P00 to P05, P07, P10 to P17, P25 to P27, -0.3 to +0.3 V -0.3 to VDD + 0.3 V P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117, X1, X2, XT2, RESET VI2 A9 PROM programming mode -0.3 to +13.5 V -0.3 to VDD + 0.3 V AVSS - 0.3 to AVREF + 0.3 V Per pin -10 mA Total for P01 to P05, P10 to P17, P25 to P27, -15 mA -15 mA Peak value 30 mA r.m.s. value 15Note mA Peak value 60 mA Output voltage VO Analog input voltage VAN P10 to P17 Output current, high IOH Analog input pin P70 to P72, P110 to P117 Total for P30 to P37, P80 to P87, P90 to P97, P100 to P103 Output current, low IOL Per pin Total for P01 to P05, P10 to P17, P110 to P117 r.m.s. value Total for P30 to P37, Peak value 140 mA P100 to P103 r.m.s. value 100Note mA Total for P25 to P27, P70 to P72, Peak value 50 mA P80 to P87, P90 to P97 r.m.s. value 40 Note 20 mA Note mA Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Note The root mean square (r.m.s.) value should be calculated as follows: [r.m.s. value] = [Peak value] x Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Capacitance (TA = 25C, VDD = VSS = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz Unmeasured pins returned to 0 V. Data Sheet U11776EJ2V1DS MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF 33 PD78P0308, 78P0308Y Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0Note 4 to 5.5 V) Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit 5.0 MHz 4 ms 5 MHz 10 ms Circuit Ceramic VPP X2 resonator X1 Crystal VPP X2 resonator C1 X1 R1 C2 VDD = Oscillation frequency (f R1 C2 Oscillation C1 X2 X1 1.0 voltage range Oscillation After VDD reaches stabilization timeNote 2 oscillation voltage range MIN. Oscillation VDD = Oscillation frequency (fX)Note 1 voltage range Oscillation 4.5 V VDD 5.5 VNote 3 stabilization External clock Note 1 X) timeNote 2 2.0 V V DD < 4.5 V 1 Note 3 X1 input frequency 30 1.0 5.0 MHz 85 500 ns (fX)Note 1 X1 input high-/lowlevel width (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. 3. After VDD reaches oscillation voltage range MIN. 4. However, oscillation start voltage or higher and VDD = 2.0 V or higher (for external clock, VDD = 2.0 V or higher). Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 34 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.0Note 4 to 5.5 V) Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s Circuit Crystal VPP XT1 resonator XT2 R2 C3 C4 External clock Oscillation V DD = Oscillation frequency (fXT)Note 1 voltage range Oscillation 4.5 V VDD 5.5 VNote 3 stabilization timeNote 2 2.0 V V DD < 4.5 VNote 3 XT1 input XT1 XT2 10 32 100 kHz 5 15 s frequency (fXT)Note 1 XT1 input high-/lowlevel width (tXTH, tXTL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. 3. After VDD reaches oscillation voltage range MIN. 4. However, oscillation start voltage or higher and VDD = 2.0 V or higher (for external clock, VDD = 2.0 V or higher). Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS1. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U11776EJ2V1DS 35 PD78P0308, 78P0308Y DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Parameter Input voltage, Symbol VIH1 high Conditions P10 to P17, P30 to P32, P35 to P37, P80 to P87, P90 to P97, P100 to P103 VIH2 P00 to P05, P25 to P27, P33, P34, P70 to P72, P110 to P117, RESET Input voltage, MAX. Unit 2.7 V VDD 5.5 V 0.7VDD MIN. VDD V 2.0 V VDD < 2.7 V 0.8VDD VDD V 2.7 V VDD 5.5 V 0.8VDD VDD V 2.0 V VDD < 2.7 V 0.85VDD VDD V VIH3 X1, X2 2.7 V VDD 5.5 V VDD - 0.5 VDD V 2.0 V VDD < 2.7 V VDD - 0.2 VDD V VIH4 XT1/P07, XT2 4.5 V VDD 5.5 V 0.8VDD VDD V 2.7 V VDD < 4.5 V 0.9VDD VDD V 2.0 V VDD < 2.7 VNote 0.9VDD VDD V 2.7 V VDD 5.5 V 0 0.3VDD V 2.0 V VDD < 2.7 V 0 0.2VDD V 2.7 V VDD 5.5 V 0 0.2VDD V 2.0 V VDD < 2.7 V 0 0.15VDD V 2.7 V VDD 5.5 V 0 0.4 V 2.0 V VDD < 2.7 V 0 0.2 V VIL1 low P10 to P17, P30 to P32, P35 to P37, P80 to P87, P90 to P97, P100 to P103 VIL2 P00 to P05, P25 to P27, P33, P34, P70 to P72, P110 to P117, RESET VIL3 VIL4 X1, X2 XT1/P07, XT2 4.5 V VDD 5.5 V 0 0.2VDD V 2.7 V VDD < 4.5 V 0 0.1VDD V 2.0 V VDD < 2.7 V Note Output voltage, VOH high Output voltage, TYP. VOL1 0 0.1VDD V VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 VDD V IOH = -100 A VDD - 0.5 P100 to P103 VDD = 4.5 to 5.5 V, low 0.6 VDD V 2.0 V 0.4 V 0.2VDD V 0.5 V IOL = 15 mA P01 to P05, P10 to P17, VDD = 4.5 to 5.5 V, P25 to P27, P30 to P37, IOL = 1.6 mA P70 to P72, P80 to P87, P90 to P97, P110 to P117 VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, open-drain, pulled up (R = 1 k) VOL3 Note Remark 36 IOL = 400 A When the XT1/P07 pin is used as P07, input the inverse phase of P07 to the XT2 pin. Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y DC Characteristics (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Parameter Input leakage Symbol ILIH1 Conditions VIN = VDD MIN. TYP. MAX. Unit 3 A X1, X2, XT1/P07, XT2 20 A P00 to P05, P10 to P17, P25 to P27, -3 A P00 to P05, P10 to P17, P25 to P27, current, high P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117, RESET ILIH2 Input leakage ILIL1 VIN = 0 V current, low P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117, RESET -20 A ILOH VOUT = VDD 3 A ILOL VOUT = 0 V -3 A 90 k ILIL2 Output leakage X1, X2, XT1/P07, XT2 current, high Output leakage current, low Software R VIN = 0 V P01 to P05, P10 to P17, pull-up resistor 15 45 P25 to P27, P30 to P37, P70 to P72, P80 to P87, P90 to P97, P100 to P103, P110 to P117 Supply IDD1 currentNote 1 VDD = 5.0 V 10%Note 5 5 15 mA VDD = 3.0 V 10%Note 6 0.7 2.1 mA operating mode VDD = 2.2 V 10%Note 6 0.4 1.2 mA 5.00 MHz crystal oscillation VDD = 5.0 V 10%Note 5 9 27 mA 5.00 MHz crystal oscillation (fXX = 2.5 (fXX = 5.0 IDD2 IDD3 IDD4 IDD5 IDD6 MHz)Note 2 MHz)Note 3 operating mode 5.00 MHz crystal oscillation VDD = 3.0 V 10%Note 6 VDD = 5.0 V 10% 1 3 mA 1.4 4.2 mA (fXX = 2.5 MHz)Note 2 VDD = 3.0 V 10% 500 1500 A HALT mode VDD = 2.2 V 10% 280 840 A 5.00 MHz crystal oscillation VDD = 5.0 V 10% 1.6 4.8 mA (fXX = 5.0 MHz)Note 3 HALT mode VDD = 3.0 V 10% 650 1950 A 32.768 kHz crystal oscillation VDD = 5.0 V 10% 135 270 A operating modeNote 4 VDD = 3.0 V 10% 95 190 A VDD = 2.2 V 10% 70 140 A 32.768 kHz crystal oscillation VDD = 5.0 V 10% 25 55 A HALT modeNote 4 VDD = 3.0 V 10% 5 15 A VDD = 2.2 V 10% 2.5 12.5 A XT1 = VDD VDD = 5.0 V 10% 1 30 A STOP mode VDD = 3.0 V 10% 0.5 10 A When feedback resistor is connected VDD = 2.2 V 10% 0.3 10 A XT1 = VDD VDD = 5.0 V 10% 0.1 30 A STOP mode VDD = 3.0 V 10% 0.05 10 A When feedback resistor is disconnected VDD = 2.2 V 10% 0.05 10 A Notes 1. Current flowing to the VDD pin. Not including the current flowing to the A/D converter, on-chip pull-up resistors, or LCD dividing resistors. 2. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 3. Main system clock fXX = fX operation (when OSMS is set to 01H) 4. When the main system clock is stopped. 5. High-speed mode operation (when processor clock control register (PCC) is set to 00H) 6. Low-speed mode operation (when PCC is set to 04H) Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U11776EJ2V1DS 37 PD78P0308, 78P0308Y LCD Controller/Driver Characteristics (at Normal Operation) (1) Static display mode (TA = -10 to +85C, VDD = 2.0 to 5.5 V) Parameter LCD drive voltage Symbol Conditions VLCD RLCD LCD output voltage VODC IO = 5 A VODS IO = 1 A deviation Note Note 60 VLCD0 = VLCD 100 MAX. Unit VDD V 150 k 0 0.2 V 0 0.2 V 2.0 V VLCD VDD (common) LCD output voltage TYP. 2.0 LCD dividing resistor deviationNote MIN. (segment) The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). (2) 1/3 bias method (TA = -10 to +85C, VDD = 2.5 to 5.5 V) Parameter LCD drive voltage Symbol Conditions VLCD RLCD LCD output voltage VODC IO = 5 A VLCD0 = VLCD VODS IO = 1 A VLCD2 = VLCD x 1/3 deviationNote Note 60 100 MAX. Unit VDD V 150 k 0 0.2 V 0 0.2 V VLCD1 = VLCD x 2/3 (common) LCD output voltage TYP. 2.5 LCD dividing resistor deviationNote MIN. 2.5 V VLCD VDD (segment) The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). (3) 1/2 bias method (TA = -10 to +85C, VDD = 2.7 to 5.5 V) Parameter LCD drive voltage Symbol Conditions VLCD RLCD LCD output voltage VODC IO = 5 A VODS IO = 1 A deviationNote Note 60 VLCD0 = VLCD VLCD2 = VLCD1 Unit VDD V 150 k 0 0.2 V 0 0.2 V 2.7 V VLCD VDD (segment) The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). 38 100 MAX. VLCD1 = VLCD x 1/2 (common) LCD output voltage TYP. 2.7 LCD dividing resistor deviationNote MIN. Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y LCD Controller/Driver Characteristics (at Low-Voltage Operation) (1) Static display mode (TA = -10 to +85C, 2.0 V VDD < 3.4 V) Parameter Symbol Conditions MIN. TYP. MAX. VDD V 100 150 k 0 0.2 V 0 0.2 V LCD drive voltage VLCD 2.0 LCD dividing resistor RLCD 60 LCD output voltage VODC IO = 5 A VLCD0 = VLCD 2.0 V VLCD VDD deviationNote (common) LCD output voltage Unit VODS IO = 1 A deviationNote (segment) Note The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). (2) 1/3 bias method (TA = -10 to +85C, 2.0 V VDD < 3.4 V) Parameter LCD drive voltage Symbol Conditions VLCD RLCD LCD output voltage VODC IO = 5 A VODS IO = 1 A deviationNote Note 60 VLCD0 = VLCD 100 MAX. Unit VDD V 150 k 0 0.2 V 0 0.2 V VLCD1 = VLCD x 2/3 (common) LCD output voltage TYP. 2.0 LCD dividing resistor deviationNote MIN. VLCD2 = VLCD x 1/3 2.0 V VLCD VDD (segment) The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). (3) 1/2 bias method (TA = -10 to +85C, 2.0 V VDD < 3.4 V) Parameter LCD drive voltage Symbol Conditions VLCD RLCD LCD output voltage VODC IO = 5 A 60 VODS IO = 1 A VLCD0 = VLCD VLCD2 = VLCD1 Unit VDD V 150 k 0 0.2 V 0 0.2 V 2.0 V VLCD VDD deviationNote (segment) Note 100 MAX. VLCD1 = VLCD x 1/2 (common) LCD output voltage TYP. 2.0 LCD dividing resistor deviationNote MIN. The voltage deviation is the difference between the output voltage and the corresponding ideal value of the segment or common output (VLCDn; n = 0, 1, 2). Data Sheet U11776EJ2V1DS 39 PD78P0308, 78P0308Y AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 2.0 to 5.5 V) Parameter Cycle time Symbol TCY Conditions Operating on main system clock MHz)Note 1 MAX. Unit 2.7 V VDD 5.5 V MIN. 0.8 TYP. 64 s 2.0 V VDD < 2.7 V 2.0 64 s (Min. instruction (fXX = 2.5 execution time) Operating on main system clock 3.5 V VDD 5.5 V 0.4 32 s (fXX = 5.0 MHz)Note 2 2.7 V VDD < 3.5 V 0.8 32 s 40Note 3 Operating on subsystem clock TI00 input fTI00 tTI00 = tTIH00 + tTIL00 0 122 125 s 1/tTI00 MHz frequency TI00 input high-/ tTIH00, 3.5 V VDD 5.5 V 2/fsam + 0.1Note 4 s low-level width tTIL00 2.7 V VDD < 3.5 V 2/fsam + 0.2Note 4 s 2.0 V VDD < 2.7 V 2/fsam + 0.5Note 4 s 2.7 V VDD 5.5 V 0 100 kHz 2.0 V VDD < 2.7 V 0 50 kHz TI01 input fTI01 frequency TI01 input high-/ tTIH01, 2.7 V VDD 5.5 V 10 s low-level width tTIL01 2.0 V VDD < 2.7 V 20 s TI1, TI2 input fTI1 4.5 V VDD 5.5 V 0 4 MHz 2.0 V VDD < 4.5 V 0 275 kHz TI1, TI2 input high-/ tTIH1, 4.5 V VDD 5.5 V 100 ns low-level width tTIL1 2.0 V VDD < 4.5 V 1.8 s 3.5 V VDD 5.5 V 2/fsam + 0.1Note 4 s 2.7 V VDD < 3.5 V 2/fsam + 0.2Note 4 s 2.0 V VDD < 2.7 V 2/fsam + 0.5Note 4 s 2.7 V VDD 5.5 V 10 s 2.0 V VDD < 2.7 V 20 s 2.7 V VDD 5.5 V 10 s 2.0 V VDD < 2.7 V 20 s frequency Interrupt request tINTH, input high-/low- tINTL INTP0 level width INTP1 to INTP5, P110 to P117 RESET low-level width tRSL Notes 1. Main system clock fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H) 2. Main system clock fXX = fX operation (when OSMS is set to 01H) 3. This is the value when the external clock is used. The value is 114 s (min.) when the crystal resonator is used. 4. In combination with bits 0 (SCS0) and 1 (SCS1) of the sampling clock select register (SCS), selection of fsam is possible between fXX/2N, fXX/32, fXX/64, and fXX/128 (when N = 0 to 4). 40 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y TCY vs. VDD (at main system clock fXX = fX/2 operation) TCY vs. VDD (at main system clock fXX = fX operation) 60 60 10 Cycle time TCY [s] Cycle time TCY [s] 32 Guaranteed operation range 2.0 10 Guaranteed operation range 2.0 1.0 0.8 1.0 0.8 0.4 0.4 0 1 2 2.7 3 4 5 6 0 1 Supply voltage VDD [V] 2 3 3.5 4 5 6 Supply voltage VDD [V] Data Sheet U11776EJ2V1DS 41 PD78P0308, 78P0308Y (2) Serial interface (TA = -40 to +85C, VDD = 2.0 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0...internal clock output) Parameter SCK0 cycle time SCK0 high-/low-level width SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time Symbol tKCY1 Conditions MIN. TYP. MAX. Unit 4.5 V VDD 5.5 V 800 ns 2.7 V VDD < 4.5 V 1600 ns 2.0 V VDD < 2.7 V 3200 ns tKH1, 4.5 V VDD 5.5 V tKCY1/2 - 50 ns tKL1 2.0 V VDD < 4.5 V tKCY1/2 - 100 ns tSIK1 4.5 V VDD 5.5 V 100 ns 2.7 V VDD < 4.5 V 150 ns 2.0 V VDD < 2.7 V 300 ns 400 ns tKSI1 tKSO1 C = 100 pFNote 300 ns MAX. Unit from SCK0 Note C is the load capacitance of SCK0 and SO0 output lines. (ii) 3-wire serial I/O mode (SCK0...external clock input) Parameter SCK0 cycle time SCK0 high-/low-level width SI0 setup time (to SCK0) Symbol tKCY2 Conditions MIN. TYP. 4.5 V VDD 5.5 V 800 ns 2.7 V VDD < 4.5 V 1600 ns 2.0 V VDD < 2.7 V 3200 ns tKH2, 4.5 V VDD 5.5 V 400 ns tKL2 2.7 V VDD < 4.5 V 800 ns 2.0 V VDD < 2.7 V 1600 ns 100 ns tSIK2 SI0 hold time (from SCK0) tKSI2 SO0 output delay time tKSO2 400 C = 100 pFNote ns 300 ns 1000 ns from SCK0 SCK0 rise, fall time tR2, tF2 Note 42 C is the load capacitance of SO0 output line. Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y (iii) SBI mode (SCK0...internal clock output): PD78P0308 only Parameter SCK0 cycle time Symbol tKCY3 Conditions MIN. TYP. MAX. Unit 4.5 V VDD 5.5 V 800 ns 2.0 V VDD < 4.5 V 3200 ns SCK0 high-/low-level tKH3, 4.5 V VDD 5.5 V tKCY3/2 - 50 ns width tKL3 2.0 V VDD < 4.5 V tKCY3/2 - 150 ns SB0, SB1 setup time tSIK3 4.5 V VDD 5.5 V 100 ns 2.0 V VDD < 4.5 V 300 ns tKCY3/2 ns (to SCK0) SB0, SB1 hold time tKSI3 (from SCK0) SB0, SB1 output delay tKSO3 time from SCK0 R = 1 k, 4.5 V VDD 5.5 V 0 250 ns C = 100 pFNote 2.0 V VDD < 4.5 V 0 1000 ns SB0, SB1 from SCK0 tKSB tKCY3 ns SCK0 from SB0, SB1 tSBK tKCY3 ns SB0, SB1 high-level tSBH tKCY3 ns tSBL tKCY3 ns width SB0, SB1 low-level width Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (iv) SBI mode (SCK0...external clock input): PD78P0308 only Parameter Symbol MIN. TYP. MAX. Unit 800 ns 2.0 V VDD < 4.5 V 3200 ns 4.5 V VDD 5.5 V 400 ns tKL4 2.0 V VDD < 4.5 V 1600 ns tSIK4 4.5 V VDD 5.5 V 100 ns tKCY4 SCK0 high-/low-level tKH4, width SB0, SB1 setup time 2.0 V VDD < 4.5 V (to SCK0) SB0, SB1 hold time Conditions 4.5 V VDD 5.5 V SCK0 cycle time tKSI4 300 ns tKCY4/2 ns (from SCK0) SB0, SB1 output delay tKSO4 time from SCK0 SB0, SB1 from SCK0 R = 1 k, C = 100 pFNote 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 0 300 ns 0 1000 ns tKSB tKCY4 ns SCK0 from SB0, SB1 tSBK tKCY4 ns SB0, SB1 high-level tSBH tKCY4 ns tSBL tKCY4 ns width SB0, SB1 low-level width SCK0 rise, fall time tR4, 1000 ns tF4 Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. Data Sheet U11776EJ2V1DS 43 PD78P0308, 78P0308Y (v) 2-wire serial I/O mode (SCK0...internal clock output) Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time Symbol tKCY5 Conditions TYP. MAX. Unit R = 1 k, 2.7 V VDD 5.5 V 1600 ns C = 100 pFNote 2.0 V VDD < 2.7 V 3200 ns tKH5 tKL5 tSIK5 (to SCK0) SB0, SB1 hold time MIN. 2.7 V VDD 5.5 V tKCY5/2 - 160 ns 2.0 V VDD < 2.7 V tKCY5/2 - 190 ns 4.5 V VDD 5.5 V tKCY5/2 - 50 ns 2.0 V VDD < 4.5 V tKCY5/2 - 100 ns 4.5 V VDD 5.5 V 300 ns 2.7 V VDD < 4.5 V 350 ns 2.0 V VDD < 2.7 V 400 ns 600 ns tKSI5 (from SCK0) SB0, SB1 output delay tKSO5 300 ns time from SCK0 Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines. (vi) 2-wire serial I/O mode (SCK0...external clock input) Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time Symbol tKCY6 tKH6 Conditions MIN. TYP. MAX. Unit 2.7 V VDD 5.5 V 1600 ns 2.0 V VDD < 2.7 V 3200 ns 2.7 V VDD 5.5 V 650 ns 2.0 V VDD < 2.7 V 1300 ns 2.7 V VDD 5.5 V 800 ns 2.0 V VDD < 2.7 V 1600 ns tSIK6 100 ns tKSI6 tKCY6/2 ns tKL6 (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay tKSO6 time from SCK0 SCK0 rise, fall time R = 1 k, 4.5 V VDD 5.5 V 0 300 ns C = 100 pFNote 2.0 V VDD < 4.5 V 0 500 ns 1000 ns tR6, tF6 Note 44 R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y (vii) I2C bus mode (SCL...internal clock output): PD78P0308Y only Parameter SCL cycle time Symbol tKCY7 Conditions C = 100 SCL high-level width tKH7 SCL low-level width tKL7 SDA0, SDA1 setup time tSIK7 pFNote (to SCL) SDA0, SDA1 hold time MIN. TYP. MAX. Unit 10 s 2.0 V VDD < 2.7 V 20 s 2.7 V VDD 5.5 V tKCY7 - 160 ns 2.0 V VDD < 2.7 V tKCY7 - 190 ns 4.5 V VDD 5.5 V tKCY7 - 50 ns 2.0 V VDD < 4.5 V tKCY7 - 100 ns 2.7 V VDD 5.5 V 200 ns 2.0 V VDD < 2.7 V 300 ns 0 ns 2.7 V VDD 5.5 V R = 1 k, tKSI7 (from SCL) SDA0, SDA1 output 4.5 V VDD 5.5 V tKSO7 2.0 V VDD < 4.5 V delay time from SCL SDA0, SDA1 from 0 300 ns 0 500 ns tKSB 200 ns SCL from SDA0, SDA1 tSBK 400 ns SDA0, SDA1 high-level tSBH 500 ns SCL or SDA0, SDA1 from SCL width Note R and C are the load resistance and load capacitance of SCL, SDA0, and SDA1 output lines. (viii) I2C bus mode (SCL...external clock input): PD78P0308Y only Parameter SCL cycle time Symbol Conditions MIN. TYP. MAX. Unit tKCY8 1000 ns SCL high-/low-level width tKH8, tKL8 400 ns SDA0, SDA1 setup time tSIK8 200 ns tKSI8 0 ns (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay tKSO8 time from SCL 4.5 V VDD 5.5 V R = 1 k, C = 100 pFNote 2.0 V VDD < 4.5 V 0 300 ns 0 500 ns tKSB 200 ns SCL from SDA0, SDA1 tSBK 400 ns SDA0, SDA1 high-level tSBH 500 ns SDA0, SDA1 from SCL or SDA0, SDA1 from SCL width SCL rise, fall time Note tR8, tF8 1000 ns R and C are the load resistance and load capacitance of SDA0 and SDA1 output lines. Data Sheet U11776EJ2V1DS 45 PD78P0308, 78P0308Y (b) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2...internal clock output) Parameter SCK2 cycle time SCK2 high-/low-level width SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time Symbol Conditions MIN. TYP. MAX. Unit 4.5 V VDD 5.5 V 800 ns 2.7 V VDD < 4.5 V 1600 ns 2.0 V VDD < 2.7 V 3200 ns tKH9, 4.5 V VDD 5.5 V tKCY9/2 - 50 ns tKL9 2.0 V VDD < 4.5 V tKCY9/2 - 100 ns tSIK9 4.5 V VDD 5.5 V 100 ns 2.7 V VDD < 4.5 V 150 ns 2.0 V VDD < 2.7 V 300 ns 400 ns tKCY9 tKSI9 tKSO9 C = 100 pFNote 300 ns MAX. Unit from SCK2 Note C is the load capacitance of SCK2 and SO2 output lines. (ii) 3-wire serial I/O mode (SCK2...external clock input) Parameter SCK2 cycle time SCK2 high-/low-level width Symbol tKCY10 Conditions MIN. TYP. 4.5 V VDD 5.5 V 800 ns 2.7 V VDD < 4.5 V 1600 ns 2.0 V VDD < 2.7 V 3200 ns tKH10, 4.5 V VDD 5.5 V 400 ns tKL10 2.7 V VDD < 4.5 V 800 ns 2.0 V VDD < 2.7 V 1600 ns SI2 setup time (to SCK2) tSIK10 100 ns SI2 hold time (from SCK2) tKSI10 400 ns SO2 output delay time tKSO10 C = 100 pFNote 300 ns 1000 ns from SCK2 SCK2 rise, fall time tR10, tF10 Note 46 C is the load capacitance of SO2 output line. Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y (iii) UART mode (dedicated baud rate generator output) Parameter Symbol Transfer rate MAX. Unit 4.5 V VDD 5.5 V Conditions MIN. TYP. 78125 bps 2.7 V VDD < 4.5 V 39063 bps 2.0 V VDD < 2.7 V 19531 bps MAX. Unit (iv) UART mode (external clock input) Parameter ASCK cycle time Symbol tKCY11 Conditions MIN. TYP. 4.5 V VDD 5.5 V 800 ns 2.7 V VDD < 4.5 V 1600 ns 2.0 V VDD < 2.7 V 3200 ns ASCK high-/low-level tKH11, 4.5 V VDD 5.5 V 400 ns width tKL11 2.7 V VDD < 4.5 V 800 ns 2.0 V VDD < 2.7 V 1600 ns Transfer rate ASCK rise, fall time 4.5 V VDD 5.5 V 39063 bps 2.7 V VDD < 4.5 V 19531 bps 2.0 V VDD < 2.7 V 9766 bps 1000 ns tR11, tF11 Data Sheet U11776EJ2V1DS 47 PD78P0308, 78P0308Y (c) Serial interface channel 3 (i) 3-wire serial I/O mode (SCK3...internal clock output) Parameter SCK3 cycle time Symbol tKCY12 Conditions MIN. TYP. MAX. Unit 4.5 V VDD 5.5 V 800 ns 2.7 V VDD < 4.5 V 1600 ns 2.0 V VDD < 2.7 V 3200 ns SCK3 high-/low-level width tKH12, 4.5 V VDD 5.5 V tKCY12/2 - 50 ns tKL12 2.0 V VDD < 4.5 V tKCY12/2 - 100 ns SI3 setup time (to SCK3) tSIK12 4.5 V VDD 5.5 V 100 ns 2.7 V VDD < 4.5 V 150 ns 2.0 V VDD < 2.7 V 300 ns SI3 hold time (from SCK3) tKSI12 SO3 output delay time tKSO12 400 ns C = 100 pFNote 300 ns MAX. Unit from SCK3 Note C is the load capacitance of SCK3 and SO3 output lines. (ii) 3-wire serial I/O mode (SCK3...external clock input) Parameter SCK3 cycle time SCK3 high-/low-level width SI3 setup time (to SCK3) Symbol Conditions MIN. TYP. 4.5 V VDD 5.5 V 800 ns 2.7 V VDD < 4.5 V 1600 ns 2.0 V VDD < 2.7 V 3200 ns tKH13, 4.5 V VDD 5.5 V 400 ns tKL13 2.7 V VDD < 4.5 V 800 ns 2.0 V VDD < 2.7 V 1600 ns 100 ns tKCY13 tSIK13 SI3 hold time (from SCK3) tKSI13 SO3 output delay time tKSO13 400 C = 100 pFNote ns 300 ns 1000 ns from SCK3 SCK3 rise, fall time tR13, tF13 Note 48 C is the load capacitance of SO3 output line. Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y AC Timing Test Points (Excluding X1, XT1 Inputs) 0.8VDD 0.2VDD 0.8VDD 0.2VDD Test points Clock Timing 1/fX tXL tXH VDD - 0.5 V 0.4 V X1 input 1/fXT tXTL tXTH VIH4 (MIN.) VIL4 (MAX.) XT1 input TI Timing tTIL00, tTIL01 tTIH00, tTIH01 TI00, TI01 1/fTI1 tTIL1 tTIH1 TI1, TI2 Data Sheet U11776EJ2V1DS 49 PD78P0308, 78P0308Y Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm tRn tFn SCK0, SCK2, SCK3 tSIKm SI0, SI2, SI3 tKSIm Input data tKSOm SO0, SO2, SO3 Output data m = 1, 2, 9, 10, 12, 13 n = 2, 10, 13 SBI mode (bus release signal transfer, PD78P0308 only): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBL tSBK tSBH tSIK3, 4 tKSI3, 4 SB0, SB1 tKSO3, 4 SBI mode (command signal transfer, PD78P0308 only): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBK tSIK3, 4 SB0, SB1 tKSO3, 4 50 Data Sheet U11776EJ2V1DS tKSI3, 4 PD78P0308, 78P0308Y 2-wire serial I/O mode: tKCY5, 6 tKL5, 6 tKH5, 6 tR6 tF6 SCK0 tSIK5, 6 tKSI5, 6 tKSO5, 6 SB0, SB1 I2C bus mode (PD78P0308Y only): tF8 tR8 tKCY7, 8 SCL tKH7, 8 tKSI7, 8 tKL7, 8 tKSB tSIK7, 8 tKSO7, 8 tKSB tSBK SDA0, SDA1 tSBH tSBK UART mode: tKCY11 tKH11 tKL11 tR11 tF11 ASCK Data Sheet U11776EJ2V1DS 51 PD78P0308, 78P0308Y A/D Converter Characteristics (TA = -40 to +85C, VDD = 2.2 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions Resolution Overall errorNote 1 MIN. TYP. 8 8 MAX. Unit 8 bit 2.7 V AVREF 5.5 V 0.6 %FSR 2.2 V AVREF < 2.7 V 1.4 %FSR 19.1 200 s 38.2 200 s 2.7 V AVREF 5.5 V Conversion time tCONV Sampling time tSAMP 24/fXX Analog input voltage VIAN AVSS AVREF V Reference voltage AVREF 2.2 VDD V AVREF-AVSS resistance RAIREF When A/D conversion not operating AVREF current AIREF When A/D conversion operatingNote 2 2.5 5.0 mA When A/D conversion not operatingNote 3 0.5 1.5 mA 2.2 V AVREF < 2.7 V 4 s 14 k Notes 1. Quantization error (1/2 LSB) is not included. This is expressed as a percentage (%FSR) to the full-scale value. 2. Indicates current flowing to AVREF pin when the CS bit of the A/D converter mode register (ADM) is 1. 3. Indicates current flowing to AVREF pin when the CS bit of ADM is 0. 52 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Symbol Data retention supply VDDDR Conditions MIN. TYP. 1.6 MAX. Unit 5.5 V 10 A voltage Data retention supply IDDDR current V DDDR = 1.6 V 0.1 Subsystem clock stop and feedback resistor disconnected. Release signal set time Oscillation stabilization tSREL tWAIT wait time s 0 17 Release by RESET 2 /fx s Release by interrupt request Note s Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS), selection of 212/fXX and 214/fXX to 217/fXX is possible. Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Data Sheet U11776EJ2V1DS 53 PD78P0308, 78P0308Y Interrupt Request Input Timing tINTL INTP0 to INTP5 RESET Input Timing tRSL RESET 54 Data Sheet U11776EJ2V1DS tINTH PD78P0308, 78P0308Y PROM Programming Characteristics DC Characteristics (1) PROM write mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Input voltage, high Symbol Conditions VIH Input voltage, low VIL Output voltage, high VOH IOH = -1 mA Output voltage, low VOL IOL = 1.6 mA ILI 0 VIN VDD Input leakage current MIN. TYP. MAX. Unit 0.7VDD VDD V 0 0.3VDD V VDD - 1.0 V -10 0.4 V +10 A VPP supply voltage VPP 12.2 12.5 12.8 V VDD supply voltage VDD 6.25 6.5 6.75 V VPP supply current IPP 50 mA VDD supply current IDD 50 mA MAX. Unit 0.7VDD VDD V 0 0.3VDD PGM = VIL (2) PROM read mode (TA = 25 5C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V) Parameter Input voltage, high Input voltage, low Output voltage, high Symbol Conditions VIH VIL MIN. TYP. V VOH1 IOH = -1 mA VDD - 1.0 V VOH2 IOH = -100 A VDD - 0.5 V VOL IOL = 1.6 mA Input leakage current ILI 0 VIN VDD Output leakage current ILO 0 VOUT VDD, OE = VIH VPP supply voltage VPP VDD - 0.6 VDD supply voltage VDD 4.5 Output voltage, low 0.4 V -10 +10 A -10 +10 A VDD VDD + 0.6 V 5.0 5.5 V VPP supply current IPP VPP = VDD 100 A VDD supply current IDD CE = VIL, VIN = VIH 50 mA Data Sheet U11776EJ2V1DS 55 PD78P0308, 78P0308Y AC Characteristics (1) PROM write mode (a) Page program mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Address setup time (to OE) Symbol Conditions MIN. TYP. MAX. Unit s tAS 2 OE setup time tOES 2 s CE setup time (to OE) tCES 2 s Input data setup time (to OE) tDS 2 s Address hold time (from OE) tAH 2 s tAHL 2 s tAHV 0 s Input data hold time (from OE) tDH 2 s Data output float delay time from OE tDF 0 VPP setup time (to OE) tVPS 1.0 VDD setup time (to OE) tVDS 1.0 250 ms Program pulse width tPW 0.095 0.105 ms Valid data delay time from OE tOE 1 s 250 ns ms tLW 1 s PGM setup time tPGMS 2 s CE hold time tCEH 2 s OE hold time tOEH 2 s OE pulse width during data latching (b) Byte program mode (TA = 25 5C, VDD = 6.5 0.25 V, VPP = 12.5 0.3 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Address setup time (to PGM) tAS 2 s OE setup time tOES 2 s CE setup time (to PGM) tCES 2 s Input data setup time (to PGM) tDS 2 s Address hold time (from OE) tAH 2 s Input data hold time (from PGM) tDH 2 s Data output float delay time from OE tDF 0 VPP setup time (to PGM) tVPS 1.0 ms VDD setup time (to PGM) tVDS 1.0 ms Program pulse width tPW 0.095 Valid data delay time from OE tOE OE hold time tOEH 56 2 Data Sheet U11776EJ2V1DS 250 ns 0.105 ms 1 s s PD78P0308, 78P0308Y (2) PROM read mode (TA = 25 5C, VDD = 5.0 0.5 V, VPP = VDD 0.6 V) Parameter Symbol MAX. Unit Data output delay time from address tACC CE = OE = VIL Conditions MIN. TYP. 800 ns Data output delay time from CE tCE OE = VIL 800 ns Data output delay time from OE tOE CE = VIL 200 ns Data output float delay time from OE tDF CE = VIL 0 60 ns Data hold time from address tOH CE = OE = VIL 0 ns (3) PROM programming mode setting (TA = 25C, VSS = 0 V) Parameter Symbol PROM programming mode setup time tSMA Conditions MIN. 10 Data Sheet U11776EJ2V1DS TYP. MAX. Unit s 57 PD78P0308, 78P0308Y PROM Write Mode Timing (Page Program Mode) Page data latch Page program Program verify A2 to A16 tAS tAHL tAHV tDS tDH tDF A0, A1 D0 to D7 Hi-Z Hi-Z tVPS Data input Hi-Z tPGMS tOE VPP Data output tAH VPP VDD tVDS VDD + 1.5 VDD VDD tCES tOEH VIH CE VIL tCEH tPW VIH PGM VIL tOES tLW VIH OE VIL 58 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y PROM Write Mode Timing (Byte Program Mode) Program Program verify A0 to A16 tAS D0 to D7 tDF Hi-Z Hi-Z Data input tDS Hi-Z Data output tDH tAH VPP VPP VDD tVPS VDD + 1.5 VDD VDD tVDS tOEH VIH CE VIL tCES tPW VIH PGM VIL tOES tOE VIH OE VIL Cautions 1. VDD should be applied before VPP, and cut after VPP. 2. VPP should not exceed +13.5 V, including overshoot. 3. Disconnection during application of 12.5 V to VPP may have an adverse effect on reliability. PROM Read Mode Timing A0 to A16 Valid address VIH CE VIL tCE VIH OE VIL tDFNote 2 tACCNote 1 D0 to D7 Hi-Z tOENote 1 tOH Data output Hi-Z Notes 1. If you want to read within the tACC range, make the OE input delay time from the fall of CE the maximum of tACC - tOE. 2. tDF is the time from when either OE or CE first reaches VIH. Data Sheet U11776EJ2V1DS 59 PD78P0308, 78P0308Y PROM Programming Mode Setting Timing VDD VDD 0 RESET VDD VPP 0 tSMA A0 to A16 60 Valid address Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y 8. PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D Q R 26 25 100 1 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 16.000.20 B 14.000.20 C 14.000.20 D 16.000.20 F 1.00 G 1.00 H 0.22 +0.05 -0.04 I J 0.08 0.50 (T.P.) K 1.000.20 L 0.500.20 M 0.17 +0.03 -0.07 N 0.08 P 1.400.05 Q 0.100.05 R +7 3 -3 S 1.60 MAX. S100GC-50-8EU, 8EA-2 Data Sheet U11776EJ2V1DS 61 PD78P0308, 78P0308Y 100-PIN PLASTIC QFP (14x20) A B 51 50 80 81 detail of lead end S C D Q R 31 30 100 1 F G J H I M P K S N S L M NOTE ITEM Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 23.60.4 B 20.00.2 C 14.00.2 D 17.60.4 F 0.8 G H 0.6 0.300.10 I 0.15 J K L 0.65 (T.P.) 1.80.2 0.80.2 M 0.15+0.10 -0.05 N 0.10 P 2.70.1 Q R S 0.10.1 55 3.0 MAX. P100GF-65-3BA1-4 62 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y 9. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 9-1. Surface Mounting Type Soldering Conditions (1/2) (1) 100-pin plastic QFP (14 x 20) PD78P0308GF-3BA, 78P0308YGF-3BA Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215C, Time: 40 seconds max. VP15-00-3 (at 200C or higher), Count: Three times or less Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) WS60-00-1 - Caution Do not use different soldering methods together (except for partial heating). (2) 100-pin plastic LQFP (fine pitch) (14 x 14) PD78P0308GC-8EU, 78P0308YGC-8EU Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) IR35-107-2 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 10 hours) VP15-107-2 Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note - After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U11776EJ2V1DS 63 PD78P0308, 78P0308Y Table 9-1. Surface Mounting Type Soldering Conditions (2/2) (3) 100-pin plastic QFP (14 x 20) PD78P0308GF-3BA-A, 78P0308YGF-3BA-A Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 20 to 72 hours) Wave soldering For details, contact an NEC Electronics sales representative. - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note IR60-203-3 After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark Products that have the part numbers suffixed by "-A" are lead-free products. (4) 100-pin plastic LQFP (fine pitch) (14 x 14) PD78P0308GC-8EU-A, 78P0308YGC-8EU-A Soldering Method Soldering Conditions Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 7 daysNote (after that, prebake at 125C for 20 to 72 hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) Note IR60-207-3 - After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Remark Products that have the part numbers suffixed by "-A" are lead-free products. 64 Recommended Condition Symbol Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are provided for system development using the PD78P0308 and 78P0308Y. Also refer to (6) Precautions When Using Development Tools. (1) Software Package SP78K0 CD-ROM in which development tools (software) common to 78K/0 Series products are integrated in one package (2) Language Processing Software RA78K0 Assembler package common to 78K/0 Series products CC78K0 C compiler package common to 78K/0 Series products DF780308 Device file for PD780308 and 780308Y Subseries products (part number: SxxxxDF78064) CC78K0-L C compiler library source file common to 78K/0 Series products (3) PROM Write Tools PG-1500 PROM programmer PA-78P0308GC Programmer adapter connected to the PG-1500 PA-78P0308GF PG-1500 controller Control program for the PG-1500 (4) Debugging Tools * When using IE-78K0-NS or IE-78K0-NS-A as in-circuit emulator IE-78K0-NS In-circuit emulator common to 78K/0 Series products IE-78K0-NS-PA Performance board to enhance/expand functions of IE-78K0-NS IE-78K0-NS-A Combination of IE-78K0-NS and IE-78K0-NS-PA IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-70000-98-IF-C Adapter required when using a PC-9800 series (excluding notebook-type PCs) as the host machine (C bus supported) IE-70000-CD-IF-A PC card and interface cable required when using a notebook type PC as the host machine (PCMCIA socket supported) IE-70000-PC-IF-C Adapter required when using an IBM PC/ATTM compatible as the host machine (ISA bus supported) IE-70000-PCI-IF-A Adapter required when using a PC with an on-chip PCI bus as the host machine IE-780308-NS-EM1 Emulation board to emulate PD780308 and 780308Y Subseries products NP-100GC Emulation probe for a 100-pin plastic LQFP (GC-8EU type) NP-H100GC-TQ NP-100GF Emulation probe for a 100-pin plastic QFP (GF-3BA type) NP-100GF-TQ NP-H100GF-TQ TGC-100SDW Conversion adapter to connect the NP-100GC or NP-H100GC-TQ and a target system board made to be mounted on a 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Conversion socket to connect the NP-100GF and a target system board made to be mounted on a 100-pin plastic QFP (GF-3BA type) TGF-100RBP Conversion socket to connect the NP-100GF-TQ or NP-H100GF-TQ and a target system ID78K0-NS Integrated debugger for the IE-78K0-NS and IE-78K0-NS-A SM78K0 System simulator common to 78K/0 Series products DF780308 Device file for PD780308 and 780308Y Subseries products (part number: SxxxxDF78064) board made to be mounted on a 100-pin plastic QFP (GF-3BA type) Data Sheet U11776EJ2V1DS 65 PD78P0308, 78P0308Y * When using IE-78001-R-A as in-circuit emulator IE-78001-R-ANote In-circuit emulator common to 78K/0 Series products IE-70000-98-IF-C Adapter required when using a PC-9800 series (excluding notebook-type PCs) as the host machine (C bus supported) IE-70000-PC-IF-C Adapter required when using an IBM PC/AT compatible as the host machine (ISA bus supported) IE-70000-PCI-IF-A IE-780308-R-EM Note Adapter required when using a PC with an on-chip PCI bus as the host machine Emulation board to emulate PD780308 and 780308Y Subseries products EP-78064GC-R Emulation probe for a 100-pin plastic LQFP (GC-8EU type) EP-78064GF-R Emulation probe for a 100-pin plastic QFP (GF-3BA type) TGC-100SDW Conversion adapter to connect the EP-78064GC-R and a target system board made to be mounted on a 100-pin plastic LQFP (GC-8EU type) EV-9200GF-100 Conversion socket to connect the EP-78064GF-R and a target system board made to be ID78K0 Integrated debugger for the IE-78001-R-A SM78K0 System simulator common to 78K/0 Series products DF780308 Device file for PD780308 and 780308Y Subseries products (part number: SxxxxDF78064) mounted on a 100-pin plastic QFP (GF-3BA type) Note Maintenance product (5) Real-Time OS RX78K0 66 Real-time OS for 78K/0 Series products Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y (6) Precautions When Using Development Tools * The package name of the DF780308 is DF78064. * Use the ID78K0-NS, ID78K0, and SM78K0 in combination with the DF780308. * Use the CC78K0 and RX78K0 in combination with the RA78K0 and DF780308. * The NP-100GC, NP-H100GC-TQ, NP-100GF, NP-100GF-TQ, and NP-H100GF-TQ are products of Naito Densei Machida Mfg. Co., Ltd. (tel: +81-45-475-4191). * The TGC-100SDW and TGF-100RBP are products of TOKYO ELETECH CORPORATION. Contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (tel: +81-3-3820-7112) Osaka Electronics Department (tel: +81-6-6244-6672) * Please refer to Single-Chip Microcontroller Development Tools Selection Guide (U11069E) for information on the third party development tools. * The following table shows the software supported by each host machine and OS. Host machine PC EWS PC-9800 series [Japanese Windows ] HP9000 series 700TM [HP-UXTM] Software IBM PC/AT compatibles [Japanese/English Windows] SPARCstationTM [SunOSTM, SolarisTM] RA78K0 Note CC78K0 Note PG-1500 controller Note ID78K0-NS ID78K0 SM78K0 [OS] TM RX78K0 Note Note DOS-based software Data Sheet U11776EJ2V1DS 67 PD78P0308, 78P0308Y Drawing of Conversion Adapter (TGC-100SDW) Figure A-1. Drawing of TGC-100SDW (for Reference Only) A B X N L M V F E D H I J K X T Protrusion height W C O PQR S U G Y Z e a n m k g d c I b j i f h ITEM INCHES ITEM MILLIMETERS INCHES A B MILLIMETERS 21.55 0.5x24=12 0.848 0.020x0.945=0.472 a b 14.45 1.850.25 0.569 0.0730.010 C 0.5 0.020 c 3.5 0.138 D 0.5x24=12 0.020x0.945=0.472 d 2.0 0.079 E F 15.0 21.55 0.591 0.848 e f 3.9 0.25 0.154 0.010 G 3.55 0.140 g 4.5 0.177 H I 10.9 13.3 0.429 0.524 h i 16.0 1.1250.3 0.630 0.0440.012 J 15.7 0.618 j 0~5 0.000~0.197 K 18.1 0.713 k 5.9 0.232 L M 13.75 0.541 0.5x24=12.0 0.020x0.945=0.472 l m 0.8 2.4 0.031 0.094 N O 1.1250.3 1.1250.2 0.0440.012 n 2.7 P 7.5 0.295 Q R 10.0 11.3 0.394 0.445 S 18.1 0.713 T U 5.0 0.197 5.0 0.197 V 4- 1.3 4- 0.051 W X 1.8 C 2.0 0.071 C 0.079 Y 0.9 0.3 0.035 0.012 Z note: Product of TOKYO ELETECH CORPORATION. 68 0.0440.008 Data Sheet U11776EJ2V1DS 0.106 TGC-100SDW-G1E PD78P0308, 78P0308Y Drawings of Conversion Socket (EV-9200GF-100) and Recommended Footprints Figure A-2. Drawing of EV-9200GF-100 (for Reference Only) A B E M N O L K S J D C R F EV-9200GF-100 Q 1 No.1 pin index P G H I EV-9200GF-100-G0E ITEM MILLIMETERS INCHES A 24.6 0.969 B 21 0.827 C 15 0.591 D 18.6 0.732 E 4-C 2 4-C 0.079 F 0.8 0.031 G 12.0 0.472 H 22.6 0.89 I 25.3 0.996 J 6.0 0.236 K 16.6 0.654 L 19.3 0.76 M 8.2 0.323 N 8.0 0.315 O 2.5 0.098 P 2.0 0.079 Q 0.35 0.014 R 2.3 0.091 S 1.5 0.059 Data Sheet U11776EJ2V1DS 69 PD78P0308, 78P0308Y Figure A-3. Recommended Footprints of EV-9200GF-100 (for Reference Only) G J H D F E K I L C B A EV-9200GF-100-P1E ITEM MILLIMETERS INCHES A 26.3 1.035 B 21.6 0.85 C +0.002 0.650.02 x 29=18.850.05 0.026 +0.001 -0.002 x 1.142=0.742-0.002 D +0.003 0.650.02 x 19=12.350.05 0.026 +0.001 -0.002 x 0.748=0.486 -0.002 E 15.6 0.614 F 20.3 0.799 G 12 0.05 0.472 +0.003 -0.002 H 6 0.05 0.236 +0.003 -0.002 I 0.35 0.02 0.014 +0.001 -0.001 J 2.36 0.03 0.093+0.001 -0.002 K 2.3 0.091 L 1.57 0.03 0.062+0.001 -0.002 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNT MANUAL" website (http://www.necel.com/pkg/en/mount/index.html). 70 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. PD780308, 780308Y Subseries User's Manual U11377E PD780306, 780308 Data Sheet U11105E PD780306Y, 780308Y Data Sheet U12251E PD78P0308, 78P0308Y Data Sheet This document 78K/0 Series Instructions User's Manual U12326E 78K/0 Series Application Note Basic (III) U10182E Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 Assembler Package CC78K0 C Compiler SM78K Series System Simulator Ver.2.30 or Later Document No. Operation U14445E Language U14446E Structured Assembly Language U11789E Operation U14297E Language U14298E Operation (Windows Based) U15373E External Part User Open Interface Specifications U15802E ID78K Series Integrated Debugger Ver.2.30 or Later Operation (Windows Based) U15185E RX78K0 Real-Time OS Fundamentals U11537E Installation U11536E Project Manager Ver.3.12 or Later (Windows Based) U14610E Documents Related to Development Tools (Hardware) (User's Manuals) Document Name Document No. IE-78K0-NS In-Circuit Emulator U13731E IE-78K0-NS-A In-Circuit Emulator U14889E IE-78K0-NS-PA Performance Board To be prepared IE-780308-NS-EM1 Emulation Board U13304E IE-78001-R-A In-Circuit Emulator U14142E IE-780308-R-EM Emulation Board U11362E Documents Related to PROM Programming (User's Manuals) Document Name Document No. PG-1500 PROM Programmer PG-1500 Controller U11940E PC-9800 series (MS-DOSTM) IBM PC series (PC Caution DOSTM) Based Based EEU-1291 U10540E The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. Data Sheet U11776EJ2V1DS 71 PD78P0308, 78P0308Y Other Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 72 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet U11776EJ2V1DS 73 PD78P0308, 78P0308Y Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65030 Hong Kong Tel: 2886-9318 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-265 40 10 * Tyskland Filial NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 74 Data Sheet U11776EJ2V1DS PD78P0308, 78P0308Y FIP and IEBus are trademarks of NEC Electronics Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. Data Sheet U11776EJ2V1DS 75 PD78P0308, 78P0308Y These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of August, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1