SM100PQ-ACTEL - Microsemi - Datasheet.Live

January 2012 I

Accelerator Series FPGAs – ACT 3 Family

Features

• Up to 10,000 Gate Array Equivalent Gates (up to 25,000

equivalent PLD Gates)

• Highly Predictable Perfo rmance with 100% Au tomatic Place-

and-Route

• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)

• Up to 186 MHz On-Chip Performance (–1 Speed Grade)

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock N etworks

• More than 500 Macro Functions

• Replaces up to Twenty 32 Macro-Cell CPLDs

• Replaces up to One Hundred 20-Pin PAL ® Pa ckage s

• Up to 1,153 Dedicated Flip-Flop s

• VQFP, TQFP, BGA, and PQFP Packages

• Nonvolatile, User Programmable

• Fully Tested Prior to Shipment

• 5.0 V and 3.3 V Versions

• Optimized for Logic Synthesis Meth odologies

• Low Power CMOS Technology

Table 1 • ACT 3 Family Product Information

Device A1415 A1425 A1440 A1460 A14100

Capacity

Gate Array Equivalen t Gates 1,500 2,500 4,000 6,000 10,000

PLD Equivalent Gates 3,750 6,250 10,000 15,000 25,000

TTL Equivalent Package (40 gates) 40 60 100 150 250

20-Pin PAL Equivalent Packages (100 gates) 15 25 40 60 100

Logic Modules 200 310 564 848 1,377

S-Module 104 160 288 432 697

C-Module 96 150 276 416 680

Dedicated Flip-Flops1264 360 568 768 1,153

User I/Os (maximum) 80 100 140 168 228

Maximum Performance2 (worst-case commercial, –1 speed grade)

Chip-to-Chip3 (MHz) 80 80 80 78 76

Accumulators (16-bit, MHz) 47 47 47 47 47

Loadable Counter (16-bit, MHz) 82 82 82 82 78

Prescaled Loadable Counters (16-bit, MHz) 186 186 186 150 150

Datapath, Shift Registers (MHz) 186 186 186 150 150

Clock-to-Output (pad-to-pad, ns) 9.0 9.0 9.5 10.0 10.5

Packages4 (by pin count)

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

CQFP

PG1005

PL84

PQ100

–

VQ100

–

PG1335

PL84

PQ100, PQ160

–

VQ100

–

CQ132

PG1755

PL84

PQ160

–

VQ100

TQ176

–

PG207

–

PQ160, PQ208

–

TQ176

BG2255

CQ196

PG257

–

RQ208

–

BG313

CQ256

Notes:

1. One flip-flop per S0Module, two flip-flops per I/O Module.

2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A1410 0A-1.

3. Clock-to-Output (pad-to-pad) + assumed trace d elay + setup time. Refer to the "System Performance Mo del" on page 1-1 and

Table 1-1 on page 1-2.

4. See the "Product Plan" table on page III for package availability.

5. Discontinued device and package combination.

6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product

Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:

PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004

Revision 3

Accelerator Series FPGAs – ACT 3 Family

II Revision 3

Ordering Information

Notes:

1. The –2 and –3 speed gra des have been discontinued.

2. The Ceramic Pin Grid Array packages PG100, PG133, and PG175 have been discontinued in all device densities, speed

grades, and temperature grades.

3. The Plastic Ball Grid Array package BG225 has been discontinued in all device densities (specifically for A1460A), all speed

grades, and all temperature grades.

4. Military Grade devices are no longer available for the A1440A device.

5. For more information about discontinued devices, refer to the Product Discontinuation Notices (PDNs) listed below, av ailable on

the Microsemi SoC Products Group website:

PDN March 2001

PDN 0104

PDN 0203

PDN 0604

PDN 1004

Part Number

Speed Grade

Package Type

Package Lead Count

C = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Application (Temperature Range)

PG = Ceramic Pin Grid Array

PL = Plastic Leaded Chip Carrier

PQ = Plastic Quad Flatpack

RQ = Plastic Power Quad Flatpack

VQ = Very Thin (1.0 mm) Quad Flatpack

TQ = Thin (1.4 mm) Quad Flatpack

CQ = Ceramic Quad Flatpack

BG = Plastic Ball Grid Array

Std = Standard Speed

–1 = Approximately 15% faster than Standard

–2 = Approximately 25% faster than Standard

–3 = Approximately 35% faster than Standard

A1415A = 1,500 Gates

A14V15A = 1,500 Gates (3.3 V)

A1425A = 2,500 Gates

A14V25A = 2,500 Gates (3.3 V)

A1440A = 4,000 Gates

A14V40A = 4,000 Gates (3.3 V)

A1460A = 6,000 Gates

A14V60A = 6,000 Gates (3.3 V)

A14100A = 10,000 Gates

A14V100A = 10,000 Gates (3.3 V)

A14100 1

Die Revision

A = 1.0 mm CMOS Process

ARQ 208GC

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS Compliant Packaging

Accelerator Series FPGAs – ACT 3 Family

Revision 3 III

Product Plan

Device/Package

Speed Grade1Application1

Std. –1 –2 –3 C I M B

A1415A Device

84-Pin Plastic Leaded Chip Carrier (PLCC) ✓✓DD✓✓✓–

100-Pin Plastic Quad Flatpack (PQFP) ✓✓DD✓✓✓–

100-Pin Very Thin Quad Flatpack (VQFP) ✓✓DD✓✓✓–

100-Pin Ceramic Pin Grid Array (CPGA) D D D D D – – –

A14V15A Device

84-Pin Plastic Leaded Chip Carrier (PLCC) ✓–––

✓–––

100-Pin Very Thin Quad Flatpack (VQFP) ✓–––

✓–––

A1425A Device

84-Pin Plastic Leaded Chip Carrier (PLCC) ✓✓DD✓✓

100-Pin Plastic Quad Flatpack (PQFP) ✓✓DD✓✓ ––

100-Pin Very Thin Quad Flatpack (VQFP) ✓✓DD✓✓ ––

132-Pin Ceramic Quad Flatpack (CQFP) ✓✓ ––

✓–✓✓

133-Pin Ceramic Pin Grid Array (CPGA) D D D D D – D D

160-Pin Plastic Quad Flatpack (PQFP) ✓✓DD✓✓ ––

A14V25A Device

84-Pin Plastic Leaded Chip Carrier (PLCC) ✓–––

✓–––

100-Pin Very Thin Quad Flatpack (VQFP) ✓–––

✓–––

160-Pin Plastic Quad Flatpack (PQFP) ✓–––

✓–––

A1440A Device

84-Pin Plastic Leaded Chip Carrier (PLCC) ✓✓DD✓✓ ––

100-Pin Very Thin Quad Flatpack (VQFP) ✓✓DD✓✓ ––

160-Pin Plastic Quad Flatpack (PQFP) ✓✓DD✓✓ ––

175-Pin Ceramic Pin Grid Array (CPGA) D D D D D – – –

176-Pin Thin Quad Flatpack (TQFP) ✓✓DD✓✓––

Notes:

1. Applications:

C = Commercial

I = Industrial

M = Military

2. Commercial only

Availability:

✓ = Available

P = Planned

– = Not planned

D = Discontinued

Speed Grade:

–1 = Approx. 15% faster than Std.

–2 = Approx. 25% faster than Std.

–3 = Approx. 35% faster than Std.

(–2 and –3 speed grades have

been discontinued.)

Accelerator Series FPGAs – ACT 3 Family

IV Revision 3

A14V40A Device

84-Pin Plastic Leaded Chip Carrier (PLCC) ✓–––

✓–––

100-Pin Very Thin Quad Flatpack (VQFP) ✓–––

✓–––

160-Pin Plastic Quad Flatpack (PQFP) ✓–––

✓–––

176-Pin Thin Quad Flatpack (TQFP) ✓–––

✓–––

A1460A Device

160-Pin Plastic Quad Flatpack (PQFP) ✓✓DD✓✓ ––

176-Pin Thin Quad Flatpack (TQFP) ✓✓DD✓✓ ––

196-Pin Ceramic Quad Flatpack (CQFP) ✓✓ ––✓–✓✓

207-Pin Ceramic Pin Grid Array (CPGA) ✓✓DD✓–✓✓

208-Pin Plastic Quad Flatpack (PQFP) ✓✓DD✓✓ ––

225-Pin Plastic Ball Grid Array (BGA) D D D D D –––

A14V60A Device

160-Pin Plastic Quad Flatpack (PQFP) ✓–––✓–––

176-Pin Thin Quad Flatpack (TQFP) ✓–––✓–––

208-Pin Plastic Quad Flatpack (PQFP) ✓–––✓–––

A14100A Device

208-Pin Power Quad Flatpack (RQFP) ✓✓DD✓✓ ––

257-Pin Ceramic Pin Grid Array (CPGA) ✓✓DD✓–✓✓

313-Pin Plastic Ball Grid Array (BGA) ✓✓DD✓–––

256-Pin Ceramic Quad Flatpack (CQFP) ✓✓ ––✓–✓✓

A14V100A Device

208-Pin Power Quad Flatpack (RQFP) ✓–––✓–––

313-Pin Plastic Ball Grid Array (BGA) ✓–––✓–––

Device/Package

Speed Grade1Application1

Std. –1 –2 –3 C I M B

Notes:

1. Applications:

C = Commercial

I = Industrial

M = Military

2. Commercial only

Availability:

✓ = Available

P = Planned

– = Not planned

D = Discontinued

Speed Grade:

–1 = Approx. 15% faster than Std.

–2 = Approx. 25% faster than Std.

–3 = Approx. 35% faster than Std.

(–2 and –3 speed grades have

been discontinued.)

Accelerator Series FPGAs – ACT 3 Family

Revision 3 V

Plastic Device Resources

Hermetic Device Resources

Contact your local Microsemi SoC Products Group (formerly Actel) representative for device availability:

http://www.microsemi.com/soc/contact/default.aspx.

Device

Series Logic

Modules Gates

User I/Os

PL84 PQ100 PQ160 PQ/RQ208 VQ100 TQ176 BG225* BG313

A1415 200 1500 70 80 – – 80 – – –

A1425 310 2500 70 80 100 – 83 – – –

A1440 564 4000 70 – 131 – 83 140 – –

A1460 848 6000 – – 131 167 – 151 168 –

A14100 1377 10000 – – – 175 – – – 228

Note: *Discontinued

Device

Series Logic

Modules Gates

User I/Os

PG100* PG133* PG175* PG207 PG257 CQ132 CQ196 CQ256

A1415 200 1500 80 – – – – – – –

A1425 310 2500 – 100 – – – 100 – –

A1440 564 4000 – – 140 – – – – –

A1460 848 6000 – – – 168 – – 168 –

A14100 1377 10000 – – – – 228 – – 228

Note: *Discontinued

Table of Contents

VI Revision 3

ACT 3 Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Detailed Specifications

Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2

I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11

ACT 3 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42

Package Pin Assignments

PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

PQ208, RQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

CQ132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

CQ196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

BG225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

BG313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22

PG100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

PG133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26

PG175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28

PG207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

PG257 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Safety Critical, Life Support, and High -R eliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Revision 3 1-1

1 – ACT 3 Family Overview

General Description

Microsemi’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity

programmable logic device. ACT 3 FPGAs offer a high performance, PCI compliant programmable

solution capable of 186 MHz on-chip performance and 9.0 nanosecond clock-to-output (–1 speed grade),

with capacities spanning from 1,500 to 10,000 gate array equivalent gates.

The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and

sequential logic modules used in Microsemi’s 3200DX and 1200XL families. In addition, the ACT 3 I/O

modules contain registers which deliver 9.0 nanosecond clock-to-out times (–1 speed grade). The

devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting

very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high

fanout signals such as flip-flop resets and output.

The ACT 3 family is supported by Microsemi’s Designer Series Development System which offers

automatic placement and routing (with automatic or fixed pin assignments), static timing analysis, user

programming, and debug and diagnostic probe capabilities.

System Performance Model

Figure 1- 1 • Predictable Performance (worst-case commercial, –1 speed grade)

Accumulators (16-Bit)

Loadable Counters (16-Bit)

Prescaled Loadable Counters (16-Bit)

Shift Registers

186 MHz

82 MHz

47 MHz

186 MHz

Chip #2 I/O ModuleChip #1 I/O Module

35 pF

I/O CLK I/O CLK

tCKHS tTRACE tINSU

ACT 3 Family Overview

1-2 Revision 3

Table 1-1 • Chip-to-Chip Performance (worst-case commer cial)

Device and Sp eed

Grade tCKHS (ns) tTRACE (ns) tINSU (ns) Tot al (ns) MHz

A1425A -3 7.5 1.0 1.8 10.3 97

A1460A -3 9.0 1.0 1.3 11.3 88

A1425A -2 7.5 1.0 2.0 10.5 95

A1460A -2 9.0 1.0 1.5 11.5 87

A1425A -1 9.0 1.0 2.3 12.3 81

A1460A -1 10.0 1.0 1.8 12.8 78

A1425A STD 10.0 1.0 2.7 13.7 73

A1460A STD 11.5 1.0 2.0 14.5 69

Note: The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN

0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.

Revision 3 2-1

2 – Detailed Specifications

This section of the datasheet is mea nt to familiarize the user with the architecture of the ACT 3 family of

FPGA devices. A generic description of the family will be presented first, followed by a detailed

description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The

on-chip circuitry required to program the devices is not covered.

Topology

The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad

Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is

similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array

itself consists of alternating rows of modules and channels. The logic modules and channels are in the

center of the array; the I/O modules are located along the array periphery. A simplified floor plan is

depicted in Figure 2-1.

Figure 2- 1 • Generalized Floor Plan of ACT 3 Device

IOIO IO IO IOIO

CSCSSIOIOC

BIO IO IO IO IOIO

IOIO BIN S C C SS

IOIO IO CLKM IO

IO IO IO IO

IOIO BIN S C

CSSCSCSSIOIOC

An Array with

rows and

columns

Top I/Os

Bottom I/Os

Left I/Os Right I/Os

Rows

n+1

n–1

•

Channels

n+1

n–1

•

n+2

0 1 2 3 4 5 c–1 c c+1 m m+1m+2 m+3 Columns

Detailed Specifications

2-2 Revision 3

Logic Modules

ACT 3 logic modules are enhanced versions of the 1200XL family logic modules. As in the 1200XL

family, there are two types of modules: C-modules and S-modules (Figure 2-2 and Figure 2-3). The C-

module is functionally equivalent to the 1200XL C-module and implements high fanin combinatorial

macros, such as 5-input AND, 5-input OR, and so on. It is available for use as the CM8 hard macro. The

S-module is designed to implement high-speed sequential functions within a singl e module.

S-modules consist of a full C-module driving a flip-flop, which allows an additional level of logic to be

implemented without additiona l propagation delay. It is available for use as the DF M8A/B and DLM8A/B

hard macros. C-modules and S-modules are arranged in pairs called module-pairs. Module-pairs are

arranged in alternating patterns and make up the bulk of the array. This arrangement allows the

placement software to support two-module macros of four types (CC, CS, SC, and SS). The C-module

implements the following function:

Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0 * D11 EQ 1

where: S0 = A0 * B0 and S1 = A1 + B1

Figure 2- 2 • C-Module Diagram

Figure 2- 3 • S-Module Diagram

D11

D01

D00

D10

A1 B1 A0 B0

YOUT

S1 S0

CLR

CLK

D11

D01

D00

D10

A1 B1 A0 B0

DOUT

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-3

The S-module contains a full implementation of the C-module plus a clearable sequential element that

can either implement a latch or flip-flop function. The S-module can therefore implement any function

implemented by the C-module. This allows complex combinatorial-sequential functions to be

implemented with no delay penalty. The Designer Series Development System will automatically

combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic

module and eliminating a module delay.

The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected

to one of three clock networks: CLKA, CLKB, or HCLK. The C-module and S-module functional

descriptions are shown in Figure 2-2 and Figure 2-3 on page 2-2. The clock selection is determined by a

multiplexer select at the clock input to the S-module.

I/Os

I/O Modules

I/O modules provide an interfa ce between the array and the I/O Pad Drivers. I/O modules are located in

the array and access the routing channels in a similar fashion to logic modules. The I/O module

schematic is shown in Figure 4. The signals Da taIn and DataOut connect to the I/O pad driver.

Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock

(IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data

enable input that can be accessed from the routing channels (ODE and IDE). The asynchronous

preset/clear input is driven by the dedi cated preset/clear network (IOPCL ). Either preset or clear can be

selected individually on an I/O module by I/O module basis.

Figure 2- 4 • Functional Diagram for I/O Module

DDATAOUT

CLR/PRE

DATAIN

IOCLK

IOPCL

CLR/PRE

ODE

MUX

0MUX

MUX0

MUX

S1 S0

Detailed Specifications

2-4 Revision 3

The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into

the array. This allows the outpu t register to be used in high-speed state machine app lications. Side I/O

modules have a dedicated output segment for Y extending into the routing channels above and below

(similar to logic mo dules). Top/Bottom I/O modules have no dedicated output segment. Signals comi ng

into the chip from the top or bottom are routed usin g F-fuses and LVTs (F-fuses and LVTs are explained

in detail in the routing section).

I/O Pad Drivers

All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four

signals: OE (Output Enable), IE (Input Enable ), DataOut, and DataIn. Certain special signals used only

during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN

(global input enable), and SLEW (individual slew sel ection). See Figure 2-5.

Special I/Os

The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during

programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent

special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change

once the device has been programmed. The permanent special I/Os consist of the array clock input

buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input

buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is

determined by the I/O macros selected.

Clock Networks

The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks

and two general purpose routed networks. The high-performance networks function up to 200 MHz,

while the general purpose routed ne tworks function up to 150 MHz.

Figure 2- 5 • Function Diagram for I/O Pad Drive r

PAD

SLEW

DATAOUT

DATAIN

IEN

INEN

OUTEN

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-5

Dedicated Clocks

Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed

performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad

Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the

array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by

special I/Os.

The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock

module (CLKMOD) that selects the source of the clock signal and may be driven as follows (Figure 2-6):

• Externally from the CLKA pad

• Externally from the CLKB pad

• Internally from the CLKINA input

• Internally from the CLKINB input

The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal

clock track are located in each horizontal routing channel. The function of the clock module is determined

by the selection of clock macros from the macro library. The ma cro CLKBUF is used to connect one of

the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally

generated clock signal to a clock network. Since both clock networks are identical, the user does not care

whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like

resets, output enables, or data enables. This saves logic modules a nd results in performance increases

in some cases.

Routing Structure

The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O

modules. These routing tracks are metal interconnects that may either be of continuous length or broken

into segments. Segments can be joined together at the ends using an ti fu ses to in crease their l engths up

to the full length of the track.

Figure 2- 6 • Clock Networks

CLKB

CLKA

FROM

PADS

CLOCK

DRIVERS

CLKMOD

CLKINB

CLKINA

S1 INTERNAL

SIGNAL

CLKO(17)

CLKO(16)

CLKO(15)

CLKO(2)

CLKO(1)

CLOCK TRACKS

Detailed Specifications

2-6 Revision 3

Horizontal Routing

Horizontal channels are located between the rows of modules and are composed of several routing

tracks. The horizontal routing tracks within the channel are divided into one or more segments. The

minimum horizontal segment length is the width of a mo dule-pair, and the maximum horizontal segment

length is the full length of the channel. Any segment that spans more than one-third the row length is

considered a long horizontal segment. A typical channel is shown in Figure 2-7. Undedicated horizontal

routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock

networks and for power and ground tie-off tracks.

Vertical Routing

Other tracks run vertically through the modules. V ertical tracks are of three types: input, output, and long.

Vertical tracks are also di vided into one or more segments. Each segment in an input track is dedicated

to the input of a particular module. Each segment in an output track is dedicated to the output of a

particular module. Long segments are uncommitted and can be assigned during routing. Each output

segment spans four channels (two above and two bel ow), except near the top and bottom of the array

where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks

and segments is shown in Figure 2-8.

Figure 2- 7 • Horizontal Routing Tracks and Segments

Figure 2- 8 • Vertical Routing Tracks and Segments

Module Row

HCLK

CLK0

NVCC

SIGNAL

(LHT)

SIGNAL

NVSS

CLK1

Track

Segment |

Module Row

Vertical Input

Segment

S-Module C-Module

Module Row

Channel

LVTs

S-Module C-Module

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-7

Antifuse Connections

An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in

PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly

testable structures as well as an efficient programming architecture. The structure is highly testable

because there are no preexisting connections; temporary connections can be made using pass

transistors. These temporary connections can isolate individual antifuses to be programmed as well as

isolate individual circuit structures to be tested. This can be done both before and after programming. For

example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the

functionality of all logic modules can be verified.

Four types of antifuse connections are used in the routing structure of the ACT 3 array. (The physical

structure of the antifuse is identical in ea ch case; only the usage differs.)

Table 2-1 shows four types of antifuses.

Examples of all four types of connections are shown in Figure 2-7 on page 2-6 and Figure 2-8 on

page 2-6.

Module Interface

Connections to Logic and I/O modules are mad e through vertical segments that connect to the module

inputs and outputs. These vertical segments lie on vertical tracks that span the entire height of the array.

Module Input Connections

The tracks dedicated to module inputs are segmented by pass transistors in each module row. During

normal user operation, the pass transistors are inactive, w hich isolates the inputs of a module from the

inputs of the module directly above or below it. During certain test modes, the p a ss transistors are active

to verify the continuity of the metal tracks. Vertical input segments span only the channel above or the

channel below. The logic modules are arranged such that half of the inputs are connected to the channel

above and half of the inputs to segments in the channel below, as shown in Figure 2-9.

Table 2-1 • Antifuse Types

Type Description

XF Horizontal-to-vertical connection

HF Horizontal-to-horizontal connection

VF Vertical-to-vertical connection

FF "Fast" vertical connection

Figure 2- 9 • Logic Module Routing Interface

Y+2

Y+1

A1 D10 D11

B1 B0 D01 D00

Y-1

Y-2

LVTs

Y+2

Y+1

Y-1

Y-2

C-Modules

S-Modules

D10 B0 A0 D11 A1 B1 D01

A0 Y

Detailed Specifications

2-8 Revision 3

Module Output Connections

Module outputs have dedicated output segments. Output segments extend vertically two channels above

and two channels below, except at the top or bottom of the array. Output segments twist, as shown in

Figure 10, so that only four vertical tracks are required.

LVT Connections

Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module

pair in the array shares four LVTs th at span the length o f th e column. Any modu le in the column pair can

connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses

connected directly to the driver stage of the module output, bypassing the isolation transistor. FF

antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower

resistance value.

Antifuse Connections

In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed

antifuse (XF-type). One exception is in the case of the clock networks.

Clock Connections

To minimize lo ading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a

few of the C-module and S-module inputs can be connected to the clock networks. To further reduce

loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock

inputs of the S-module.

Programming and Test Circuits

The array of logic and I/O modules is surrounded by test and programming circuits controlled by the

temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family

devices. The ACT 3 family also includes support for two Actionprobe® circuits, allowing complete

observability of any logic or I/O module in the array using the te mporary special I/O pins, PRA and PRB.

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-9

5 V Operating Conditions

Table 2-2 • Absolute Maximum Ratings1, Free Air Temperature Range

Symbol Parameter Limits Units

VCC DC supply voltage –0.5 to +7.0 V

VI Input voltage –0.5 to VCC + 0.5 V

VO Output voltage –0.5 to VCC + 0.5 V

IIO I/O source sink current2±20 mA

TSTG Storage temperature –65 to +150 °C

Notes:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be

operated outside the recommended operating conditions.

2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater

than VCC + 0.5 V for less than GND –0.5 V, the internal protection diodes will forward bias and can draw excessive

current.

Table 2-3 • Recommended Operating Condition s

Parameter Commercial Industrial Military Units

Temperature range* 0 to +70 –40 to +85 –55 to +125 °C

5 V power supply tolerance ±5 ±10 ±10 %VCC

Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military.

Table 2-4 • Electrical Specifications

Symbol Parameter Test Condition

Commercial Industrial Military

UnitsMin. Max. Min. Max. Min. Max.

VOH1,2 High level output IOH = –4 mA (CMOS) – – 3.7 – 3.7 – V

IOH = –6 mA (CMOS) 3.84 V

IOH = –10 mA (TTL)32.40 V

VOL1,2 Low leve l ou tp u t IOL = +6 mA (CMOS) 0.33 0.4 0.4 V

IOL = +12 mA (TTL)30.50

VIH High level input TTL inputs 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V

VIL Low level input TTL inputs –0.3 0.8 –0.3 0.8 –0.3 0.8 V

IIN Input leakage VI = VCC or GND –10 +10 – 10 +10 –10 +10 µA

IOZ 3-state output leakage VO = VCC or GND –10 +10 –10 +10 –10 +10 µA

CIO I/O capacitance3,4 10 10 10 pF

ICC(S) Standby VCC supply current (typica l = 0.7 mA) 2 10 20 mA

ICC(D) Dynamic VCC supply current. See the Power Dissipation section.

Notes:

1. Microsemi devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is

required.

2. Tested one output at a time, VCC = minimum.

3. Not tested; for information only.

4. VOUT = 0 V, f = 1 MHz

5. Typical standby current = 0.7 mA. All out puts unloaded. All inputs = VCC or GND.

Detailed Specifications

2-10 Revision 3

3.3 V Operating Conditions

Table 2-5 • Absolute Maximum Ratings1, Free Air Temperature Range

Symbol Parameter Limits Units

VCC DC supply voltage –0.5 to +7.0 V

VI Input voltage –0.5 to VCC + 0.5 V

VO Output voltage –0.5 to VCC + 0.5 V

IIO I/O source sink current2±20 mA

TSTG Storage temperature –65 to +150 °C

Notes:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be

operated outside the recommended operating conditions.

2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater

than VCC + 0.5 V for less than GND –0.5 V, the internal protection diodes will forward bias and can draw excessive

current.

Table 2-6 • Recommended Operating Condition s

Parameter Commercial Units

Temperature range* 0 to +70 °C

Power supply tolerance 3.0 to 3.6 V

Note: *Ambient temperature (TA) is used for commercial.

Table 2-7 • Electrical Specifications

Parameter

Commercial

UnitsMin. Max.

VOH1IOH = –4 mA 2.15 – V

IOH = –3.2 mA 2.4 V

VOL1IOL = 6 mA 0.4 V

VIL –0.3 0.8 V

VIH 2.0 VCC + 0.3 V

Input transition time tR, tF2VI = VCC or GND –10 +10 µA

CIO I/O Capacitance2,3 10 pF

Standby current, ICC4 (typical = 0.3 mA) 0.75 mA

Leakage current5–10 10 µA

1. Only one output tested at a time. VCC = minimum.

2. Not tested; for information only.

3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f - 1 MHz.

4. Typical standby current = 0.3 mA. All out puts unloaded. All inputs = VCC or GND.

5. VO, VIN = VCC or GND

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-11

Package Thermal Characteristics

The device junction to case thermal characte ristic is θjc, and the j unction to ambient air cha racteristic is

θja. The thermal characteristics for θja are shown with two different air flow rates.

Maximum junction temperature is 150°C.

A sample calculation of the absolute maximum power dissipation allowed for a CPGA 175-pin package at

commercial temperature and still air is as follows:

EQ 2

Table 2-8 • Package Thermal Characteristics

Package Type* Pin Count θjc

θja

Still Air

θja

300 ft./min. Units

Ceramic Pin Grid Array 100 20 35 17 °C/W

133 20 30 15 °C/W

175 20 25 14 °C/W

207 20 22 13 °C/W

257 20 15 8 °C/W

Ceramic Quad Flatpack 132 13 55 30 °C/W

196 13 36 24 °C/W

256 13 30 18 °C/W

Plastic Quad Flatpack 100 13 51 40 °C/W

160 10 33 26 °C/W

208 10 33 26 °C/W

Very Thin Quad Flatpack 100 12 43 35 °C/W

Thin Quad Flatpack 176 11 32 25 °C/W

Power Quad Flatpack 208 0.4 17 13 °C/W

Plastic Leaded Chip Carrier 84 12 37 28 °C/W

Plastic Ball Grid Array 225 10 25 19 °C/W

313 10 23 17 °C/W

Note: Maximum power dissipation in still air:

PQ160 = 2.4 W

PQ208 = 2.4 W

PQ100 = 1.6 W

VQ100 = 1.9 W

TQ176 = 2.5 W

PL84 = 2.2 W

RQ208 = 4.7 W

BG225 = 3.2 W

BG313 = 3.5 W

Max. junction temp. (°C) Max. ambient temp. (°C)–

θja°C/W

--------------------------------------------------------------------------------------------------------------------------------------- 150°C 70°C–

25°C/W

------------------------------------3.2 W==

Detailed Specifications

2-12 Revision 3

Power Dissipation

P = [ICC standby + Iactive] * VCC * IOL * VOL * N + IOH* (VCC – VOH) * M EQ 3

where:

ICC standby is the current flowing when no inputs or outputs are changing

Iactive is the current flowing due to CMOS switching.

IOL and IOH are TTL sink/source current.

VOL and VOH are TTL level output voltages.

N is the number of outputs driving T TL lo ads to VOL.

M equals the number of outputs driving TTL loads to VOH.

An accurate determin ation of N and M is problema tical because their values d epend on the design and

on the system I/O. The power can be divided into two components: static and active.

Static Power Component

Microsemi FPGAs have small static power components that result in lower power dissipation than PALs

or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level

power dissipation can be achieved.

The power due to standby current is typically a sma ll component of the overal l power. Standby power is

calculated in Table 2-9 fo r commercial, worst case conditions.

The static power dissipated by TTL loads depends on the number of o utputs driving hig h or low a nd the

DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will

generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual

dissipation will average somewhere between as I/Os switch states with time.

Active Power Component

Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This

component is frequency dependent, a function of the logic and the exte rnal I/O. Active power dissipation

results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module

inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs.

An additional component of the active power dissipation is the totem-pole current in CMOS transistor

pairs. The net effect can be associated with an equivalent capacitance that can be combined with

frequency and voltage to represent active power dissipation.

Equivalent Capacitance

The power dissipated by a CMOS circuit can be expressed by EQ 4.

Power (µW) = CEQ * VCC2 * F EQ 4

Where:

CEQ is the equivalent capacitance expressed in pF.

VCC is the power supply in volts.

F is the switching frequency in MHz.

Table 2-9 • Standby Power Calculation

ICC VCC Power

2 mA 5.25 V 10.5 mW

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-13

Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for

each circuit component of interest. Measurements have been made over a range of frequencies at a

fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used

over a wide range of operating conditions. Equivalent capacitance values are shown in Figure 2-10.

To calculate the active power dissipated from the complete design , the switching frequency of each part

of the logic must be known. EQ 5 shows a pie ce -wise linear summation over all components.

Power =VCC2 * [(m * CEQM * fm)modules + (n * CEQI * fn) inputs

+ (p * (CEQO+ CL) * fp)outputs

+ 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1

+ 0.5 * (q2 * CEQCR * fq2)routed_Clk2

+ (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk

+ (s2 * CEQCI * fs2)IO_Clk]EQ 5

Where:

m = Number of logic modules switching at fm

n = Number of input buffers switching at fn

p = Number of output buffers switching at fp

q1 = Number of clock loads on the first routed array clock

q2 = Number of clock loads on the second route d array clock

r1 = Fixed capacitance due to first routed array clock

r2 = Fixed capacitance due to second routed array clock

s1 = Fixed number of clock loads on the dedicated array clock

s2 = Fixed number of clock loads on the dedicated I/O clock

CEQM = Equivalent capacitance of logic modules in pF

CEQI = Equivalent capacitance of input buffers in pF

CEQO = Equivalent capacitance of output buffers in pF

CEQCR = Equivalent capacitance of routed array clock in pF

CEQCD = Equivalent capacitance of dedicated array clock in pF

CEQCI = Equivalent capacitance of dedicated I/O clock in pF

CL = Output lead capacitance in pF

fm = Average logic module switching rate in MHz

fn = Average input buffer switching rate in MHz

fp = Average output buffer switching rate in MHz

fq1 = Average first routed array clock rate in MHz

fq2 = Average second routed array clock rate in MHz

fs1 = Average dedicated array clock rate in MHz

fs2 = Average dedicated I/O clock rate in MHz

Table 2-10 • CEQ Values for Microsemi FPGAs

Item CEQ Value

Modules (CEQM) 6.7

Input Buffers (CEQI)7.2

Output Buffers (CEQO) 10.4

Routed Array Clock Buffer Loads (CEQCR) 1.6

Dedicated Clock Buffer Loads (CEQCD) 0.7

I/O Clock Buffer Loads (CEQCI) 0.9

Detailed Specifications

2-14 Revision 3

Table 2-11 • Fixed Capacitance Values for Microsemi FPGAs

Device Type r1, routed_Clk1 r2, routed_Clk2

A1415A 60 60

A14V15A 57 57

A1425A 75 75

A14V25A 72 72

A1440A 105 105

A14V40A 100 100

A1440B 105 105

A1460A 165 165

A14V60A 157 157

A1460B 165 165

A14100A 195 195

A14V100A 185 185

A14100B 195 195

Table 2-12 • Fixed Clock Loads (s1/s2)

Device Type s1, Clock Loads on Dedicated

Array Clock s2, Clock Loads on Dedicated

I/O Clock

A1415A 104 80

A14V15A 104 80

A1425A 160 100

A14V25A 160 100

A1440A 288 140

A14V40A 288 140

A1440B 288 140

A1460A 432 168

A14V60A 432 168

A1460B 432 168

A14100A 697 228

A14V100A 697 228

A14100B 697 228

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-15

Determining Average Switching Frequency

To determi ne the switching frequency for a design, yo u must have a detailed understanding of the data

input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that

they can be generally used to predict the upper limits of power dissipation. These guidelines are as

follows:

Table 2-13 • Guidelines for Predicting Power Dissipation

Data Value

Logic Modules (m) 80% of modules

Inputs switching (n) # inputs/4

Outputs switching (p) # output/4

First routed array clock loads (q1) 40% of sequential modules

Second routed array clock loads (q2) 40% of sequential modules

Load capacitance (CL) 35 pF

Average logic module switching rate (fm) F/10

Average input switching rate (fn) F/5

Average output switching rate (fp) F/10

Average first routed array clock rate (fq1) F/2

Average second routed array clock rate (fq2) F/2

Average dedicated array clock rate (fs1) F

Average dedicated I/O clock rate (fs2)F

Detailed Specifications

2-16 Revision 3

ACT 3 Timing Model

Note: Values shown for A1425A –1 speed grade device.

Figure 2-10 • Timing Model

Output DelaysInternal DelaysInput Delays

tINH = 0.0 ns

tINSU = 2.3 ns

I/O CLOCK

I/O Module

tICKY = 6.0 ns

FIOMAX = 150 MHz

tINY = 3.6 ns tIRD2 = 1.6 ns

Combinatorial

Logic Module

tPD = 2.6 ns

Sequential

Logic Module

I/O Module

tRD1 = 1.1 ns tDHS = 6.4 ns

I/O Module

ARRAY

CLOCK

FHMAX = 150 MHz

Comb.

Logic

Included

in tSUD

DQDQ

tOUTH = 0.9 ns

tOUTSU = 0.9 ns

tDHS = 6.4 ns

tENZHS = 5.1 ns

tRD1 = 1.1 ns

tCO = 2.6 ns

tSUD = 0.7 ns

tHD = 0.0 ns

tRD4 = 2.2 ns

tRD8 = 3.6 ns

Predicted

Routing

Delays

tHCKH = 3.9 ns

tCKHS = 9.0 ns

(pad-pad)

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-17

Figure 2-11 • Output Buffers

Figure 2-12 • AC Test Loads

Figure 2-13 • Input Buffer Delays

To AC test loads (shown below)

PAD

TRIBUFF

In VCC GND

50%

Out

VOL

VOH

1.5 V

tDHS,

50%

1.5 V

tDHS

En VCC GND

50%

Out VOL

1.5 V

tENZHS,

50%

10%

tENHSZ

En VCC GND

50%

Out

GND

VOH

1.5 V

tENZHS,

50%

90%

tENHSZ

VCC

Load 1

(Used to measure propagation delay) Load 2

(Used to measure rising/falling edges)

35 pF

To the output under test VCC GND

35 pF

To the output under test

R to VCC

for tPLZ / tPZL

R to GND for tPHZ / tPZH

R = 1 kΩ

PAD Y

INBUF

In 3V 0V

1.5 V

Out

GND

VCC

50%

INY

1.5 V

50%

INY

Detailed Specifications

2-18 Revision 3

Figure 2-14 • Module Delays

Figure 2-15 • Sequential Module Timing Characteristics

S, A or B

Out

GND

VCC

50%

tPD

Out

GND

VCC

50%

50% 50%

VCC

50% 50%

tPD

Flip-Flops

(Positive edge triggered)

CLK CLR

CLK

CLR

tWCLKA

tWASYN

tHD

tSUD tA

tWCLKA

tCO

tCLR

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-19

Figure 2-16 • I/O Module: Sequential Input Timing Characteristics

Figure 2-17 • I/O Module: Sequential Output Timing Characteristics

(Positive edge triggered)

IOCLK CLR

PRE Y

IOCLK

PRE, CLR

tIOPWH

tIOASPW

tINH

tIDESU

tINSU

tICLRY

tIOP

tIOPWL

tICKY

tIDEH

tCKHS,

IOCLK

PRE, CLR

tIOPWH

tIOASPW

tOUTH

tODESU

tOUTSU

tOCLRY

tIOP

tIOPWL

tOCKY

tCKLS

(Positive edge triggered)

IOCLK CLR

PRE

tODEH

Detailed Specifications

2-20 Revision 3

Tightest Delay Distributions

Propagation delay between logic modules depends on the resistive and capacitive loading of the routing

tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as

the length of routing tracks, the number of interconnect elements, or the number of inputs increases.

From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout

(number of loads) driven by a module. Higher fanout usually require s some paths to have longer le ngths

of routing track. The ACT 3 family delivers the tightest fano ut delay distribution of any FPGA. This tight

distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by

decreasing the number of interconnect eleme nts per path.

Microsemi’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 3

family’s antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200Ω resistance and 6

femtofarad (fF) capacitance per antifuse. The ACT 3 fanout distribution is also tighter than alternative

devices due to the low number of antifuses required per interconnect path. The ACT 3 family’s

proprietary architecture limits the number of antifuses per path to only four, with 90% of interconnects

using only two antifuses.

The ACT 3 family’s tight fanout delay distribution offers an FPGA design environment in which fanout can

be traded for the increased performance of reduced logic level designs. This also simplifies performance

estimates when designing with ACT 3 devices.

Timing Characteristics

Timing characteristics for ACT 3 devices fall into three ca tegories: family dependent, device depe ndent,

and design dependent. The input and output buffer characteristics are common to all ACT 3 family

members. Internal routing delays are device dependent. Design dependency means actual delays are

not determined until after placement and routing of the user’s design is complete. Delay values may then

be determined by using the ALS Timer utility or performing simulation with post-layout delays.

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets, which are used for initial design performance

evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are

determined by net property assignmen t prior to placement and ro uting. Up to 6% of the nets in a design

may be designated as critical, while 90% of the nets in a design are typical.

Long Tracks

Some nets in the design use long tracks. Long tracks are special routing resources that span multiple

rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This

increases capacit ance and resistance, result ng in longer net delays for macros connected to long tracks.

Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute

approximately 4 ns to 14 ns delay. This additional delay is represented statistically in higher fanout

(FO = 8) routing delays in the datasheet specifications section.

Table 2-14 • Logic Module and Rou ting De lay by Fa nout (ns); Worst-Cas e Commercial Condi tions

Speed Grade FO = 1 FO = 2 FO = 3 FO = 4 FO = 8

ACT 3 –3 2.9 3.2 3.4 3.7 4.8

ACT 3 –2 3.3 3.7 3.9 4.2 5.5

ACT 3 –1 3.7 4.2 4.4 4.8 6.2

ACT 3 STD 4.3 4.8 5.1 5.5 7.2

Notes:

1. Obtained by added tRD(x=FO) to tPD from the Logic Module Timing Characteristics Tables found in this

datasheet.

2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 06 04, and

PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-21

Timing Derating

ACT 3 devices are manufactured in a CMOS process. Therefore, device performance varies according

to temperature, voltage, and process va riations. Mi nimum timing parameters reflect maximum opera ting

voltage, minimum operating temperatu re, and best-case processing. Maxi mum timing parameters reflect

minimum operating voltage, maximum operating temperature, and worst-case processing.

Table 2-15 • Timing Derating Factor (Temperature and Voltage)

(Commercial Minimum/Maximum Specification) x Industrial Military

Min. Max. Min. Max.

0.66 1.07 0.63 1.17

Table 2-16 • Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C)

and Voltage (5.0 V)

(Commercial Maximum Specification) x 0.85

Table 2-17 • Temperature a nd Vol ta ge Derating Factors

(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)

–55–400 257085125

4.50 0.72 0.76 0.85 0.90 1.04 1.07 1.117

4.75 0.70 0.73 0.82 0.87 1.00 1.03 1.12

5.00 0.68 0.71 0.79 0.84 0.97 1.00 1.09

5.25 0.66 0.69 0.77 0.82 0.94 0.97 1.06

5.50 0.63 0.66 0.74 0.79 0.90 0.93 1.01

Note: This derating factor applies to all routing and propagation d elays.

Figure 2- 18 • Junction Temperature and Voltage Derating Curves

(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)

Voltage (V)

Derating Factor

0.60

0.70

0.80

0.90

1.00

1.10

1.20

4.50 4.75 5.00 5.25 5.50

Detailed Specifications

2-22 Revision 3

A1415A, A14V15A Timing Characteristics

Table 2-18 • A1415A, A14V15A Worst-Ca se Commercial Conditions, VCC = 4.75 V, TJ = 70°C1

Logic Module Propagation Delays2 –3 Speed3–2 Speed3 –1 Speed Std. Speed 3.3 V Speed1Units

Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns

tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns

tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns

Predicted Routing Delays4

tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns

tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns

tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns

tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns

tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns

Logic Module Sequential Timing

tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns

tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0 .0 ns

tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns

tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns

tWASYN Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns

tWCLKA Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns

tAFlip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns

fMAX Flip-Flop Clock Frequency 250 200 150 125 100 MHz

Notes:

1. VCC = 3.0 V for 3.3 V specifications.

2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.

3. The –2 and –3 speed grades have been discontinued. Please refer to the Product Discontinuation Notices (PDNs) listed

below:

PDN March 2001

PDN 0104

PDN 0203

PDN 0604

PDN 1004

4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case

performance. Post-route timing is based on actual routing delay measurements performed on the device prior to

shipment.

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-23

A1415A, A14V15A Timing Characteristics (continued)

Table 2-19 • A1415A, A14V15A Worst-Ca se Commercial Conditions, VCC = 4.75 V, TJ = 70°C

I/O Module Input Propagation Delays –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed2Units

Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns

tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns

tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns

tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns

tOCLRY Output Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns

Predicted Input Routing Delays2

tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns

tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns

tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns

tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns

tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns

I/O Module Sequential Timing (wrt IOCLK pad)

tINH Input F-F Data Hold 0.0 0.0 0.0 0.0 0.0 ns

tINSU Input F-F Data Setup 2.0 2.3 2.5 3.0 3.0 ns

tIDEH Input Data Enable Hold 0.0 0.0 0.0 0.0 0.0 ns

tIDESU Input Data Enable Setup 5.8 6.5 7.5 8.6 8.6 ns

tOUTH Output F-F Data hold 0.7 0.8 0.9 1.0 1.0 ns

tOUTSU Output F-F Data Setup 0.7 0.8 0.9 1.0 1.0 ns

tODEH Output Data Enable Hold 0.3 0.4 0.4 0.5 0.5 ns

fODESU Output Data Enable Setup 1.3 1.5 1.7 2.0 2.0 ns

Notes:

1. The –2 and –3 speed grades have been discont i nued. Pl ease refer to the Produ ct Disc ont inuati on Notice s (PDNs) listed

below:

PDN March 2001

PDN 0104

PDN 0203

PDN 0604

PDN 1004

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case

performance. Post-route timing is based on actual routing delay measurements performed on the device prior to

shipment.

Detailed Specifications

2-24 Revision 3

A1415A, A14V15A Timing Characteristics (continued)

Table 2-20 • A1415A, A14V15A Worst-Ca se Commercial Conditions, VCC = 4.75 V, TJ = 70°C

I/O Module – TTL Output Timing1–3 Speed2 –2 Speed2–1 Speed Std. Speed 3.3 V Speed1Units

Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

tDHS Data to Pad, High Slew 5.0 5.6 6.4 7.5 9.8 ns

tDLS Data to Pad, Low Slew 8.0 9.0 10.2 12.0 15.6 ns

tENZHS Enable to Pad, Z to H/L, High Slew 4.0 4.5 5.1 6.0 7.8 ns

tENZLS Enable to Pad, Z to H/L, Low Slew 7.4 8.3 9.4 11.0 14.3 ns

tENHSZ Enable to Pad, H/L to Z, High Slew 6.5 7.5 8.5 10.0 13.0 ns

tENLSZ Enable to Pad, H/L to Z, Low Slew 6.5 7.5 8.5 10.0 13.0 ns

tCKHS IOCLK Pad to Pad H/L, High Slew 7.5 7.5 9.0 10.0 13.0 ns

tCKLS IOCLK Pad to Pad H/L, Low Slew 11.3 11.3 13.5 15.0 19.5 ns

dTLHHS Delta Low to High, High Slew 0.02 0.02 0.0 3 0.03 0.04 ns/pF

dTLHLS Delta Low to High, Low Slew 0.05 0.05 0.06 0.07 0.09 ns/pF

dTHLHS Delta High to Low, High Slew 0.04 0 .0 4 0.04 0.05 0.07 ns/pF

dTHLLS Delta High to Low, Low Slew 0.05 0.05 0.0 6 0.07 0.09 ns/pF

I/O Module – CMOS Output Timing1

tDHS Data to Pad, High Slew 6.2 7.0 7.9 9.3 12.1 ns

tDLS Data to Pad, Low Slew 11.7 13.1 14.9 17.5 22.8 ns

tENZHS Enable to Pad, Z to H/L, High Slew 5.2 5.9 6.6 7.8 10.1 ns

tENZLS Enable to Pad, Z to H/L, Low Slew 8.9 10.0 11.3 13.3 17.3 ns

tENHSZ Enable to Pad, H/L to Z, High Slew 6.7 7.5 8.5 10.0 13.0 ns

tENLSZ Enable to Pad, H/L to Z, Low Slew 6.7 7.5 9.0 10.0 13.0 ns

tCKHS IOCLK Pad to Pad H/L, High Slew 8.9 8.9 10.7 11.8 15.3 ns

tCKLS IOCLK Pad to Pad H/L, Low Slew 13.0 13.0 15.6 17.3 22.5 ns

dTLHHS Delta Low to High, High Slew 0.04 0.04 0.0 5 0.06 0.08 ns/pF

dTLHLS Delta Low to High, Low Slew 0.07 0.08 0.09 0.11 0.14 ns/pF

dTHLHS Delta High to Low, High Slew 0.03 0 .0 3 0.03 0.04 0.05 ns/pF

dTHLLS Delta High to Low, Low Slew 0.04 0.04 0.0 4 0.05 0.07 ns/pF

Notes:

1. Delays based on 35 pF loading.

2. The –2 and –3 speed grades have been discont i nued. Pl ease refer to the Produ ct Disc ont inuati on Notice s (PDNs) listed

below:

PDN March 2001

PDN 0104

PDN 0203

PDN 0604

PDN 1004

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-25

A1415A, A14V15A Timing Characteristics (continued)

Table 2-21 • A1415A, A14V15A Worst-Ca se Commercial Conditions, VCC = 4.75 V, TJ = 70°C

Dedicated (hardwired) I/O Clock Network –3 Speed –2 Speed –1 Speed Std. Speed 3.3 V Speed1Units

Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

tIOCKH Input Low to High (pad to I/O module

input) 2.0 2.3 2.6 3.0 3.5 ns

tIOPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns

tIPOWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns

tIOSAPW Minimum Asynchronous Pulse Width 1.9 2.4 3.3 3.8 4.8 ns

tIOCKSW Maximum Skew 0.4 0.4 0.4 0.4 0.4 ns

tIOP Minimum Period 4.0 5.0 6.8 8.0 10.0 ns

fIOMAX Maximum Frequency 250 200 150 125 100 MHz

Dedicated (hardwired) Array Clock

tHCKH Input Low to High (pad to S-module

input) 3.0 3.4 3.9 4.5 5.5 ns

tHCKL Input High to Low (pad to S-module

input) 3.0 3.4 3.9 4.5 5.5 ns

tHPWH Minimum Pulse Width High 1.9 2.4 3.3 3.8 4.8 ns

tHPWL Minimum Pulse Width Low 1.9 2.4 3.3 3.8 4.8 ns

tHCKSW Delta High to Low, Low Slew 0.3 0.3 0.3 0.3 0.3 ns

tHP Minimum Period 4.0 5.0 6.8 8.0 10.0 ns

fHMAX Maximum Frequency 250 200 150 125 100 MHz

Routed Array Clock Netwo rks

tRCKH Input Low to High (FO = 64) 3.7 4.1 4.7 5.5 9.0 ns

tRCKL Input High to Low (FO = 64) 4.0 4.5 5.1 6.0 9.0 ns

tRPWH Min. Pulse Width High (FO = 64) 3.3 3.8 4.2 4.9 6.5 ns

tRPWL Min. Pulse Width Low (FO = 64) 3.3 3.8 4.2 4.9 6.5 ns

tRCKSW Maximum Skew (FO = 128) 0.7 0.8 0.9 1.0 1.0 ns

tRP Minimum Period (FO = 64) 6.8 8.0 8.7 10.0 13.4 ns

fRMAX Maximum Frequency (FO = 64) 150 125 115 100 75 MHz

Clock-to-Clock Skews

tIOHCKSW I/O Clock to H-Clock Skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns

tIORCKSW I/O Clock to R-Clock Skew (FO = 64) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0 0.0 3.0 ns

tHRCKSW H-Clock to R-Clock Skew (FO = 64)

(FO = 50% maximum) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0 0.0

0.0 3.0

3.0 ns

Notes:

1. Delays based on 35 pF loading.

2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at

http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.

Detailed Specifications

2-26 Revision 3

A1425A, A14V25A Timing Characteristics

Table 2-22 • A1425A, A14V25A Worst-Ca se Commercial Conditions, VCC = 4.75 V, TJ = 70°C1

Logic Module Propagation Delays2 –3 Speed3 –2 Speed3 –1 Speed Std. Sp eed 3.3 V Speed1Units

Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

tPD Internal Array Module 2.0 2.3 2.6 3.0 3.9 ns

tCO Sequential Clock to Q 2.0 2.3 2.6 3.0 3.9 ns

tCLR Asynchronous Clear to Q 2.0 2.3 2.6 3.0 3.9 ns

Predicted Routing Delays4

tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns

tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns

tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns

tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns

tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns

Logic Module Sequential Timing

tSUD Flip-Flop Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns

tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 0 .0 ns

tSUD Latch Data Input Setup 0.5 0.6 0.7 0.8 0.8 ns

tHD Latch Data Input Hold 0.0 0.0 0.0 0.0 0.0 ns

tWASYN Asynchronous Pulse Width 1.9 2.4 3.2 3.8 4.8 ns

tWCLKA Flip-Flop Clock Pulse Width 1.9 2.4 3.2 3.8 4.8 ns

tAFlip-Flop Clock Input Period 4.0 5.0 6.8 8.0 10.0 ns

fMAX Flip-Flop Clock Frequency 250 200 150 125 100 MHz

Notes:

1. VCC = 3.0 V for 3.3 V specifications.

2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.

3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at

http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.

4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case

performance. Post-route timing is based on actual routing delay measurements performed on the device prior to

shipment.

Accelerator Series FPGAs – ACT 3 Family

Revision 3 2-27

A1425A, A14V25A Timing Characteristics (continued)

Table 2-23 • A1425A, A14V25A Worst-Ca se Commercial Conditions, VCC = 4.75 V, TJ = 70°C

I/O Module Input Propagation Delays –3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1Units

Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

tINY Input Data Pad to Y 2.8 3.2 3.6 4.2 5.5 ns

tICKY Input Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns

tOCKY Output Reg IOCLK Pad to Y 4.7 5.3 6.0 7.0 9.2 ns

tICLRY Input Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns

tOCLRY Output Asynchronous Clear to Y 4.7 5.3 6.0 7.0 9.2 ns

Predicted Input Routing Delays2

tRD1 FO = 1 Routing Delay 0.9 1.0 1.1 1.3 1.7 ns

tRD2 FO = 2 Routing Delay 1.2 1.4 1.6 1.8 2.4 ns

tRD3 FO = 3 Routing Delay 1.4 1.6 1.8 2.1 2.8 ns

tRD4 FO = 4 Routing Delay 1.7 1.9 2.2 2.5 3.3 ns

tRD8 FO = 8 Routing Delay 2.8 3.2 3.6 4.2 5.5 ns

I/O Module Sequential Timing (wrt IOCLK pad)

tINH Input F-F Data Hold 0.0 0.0 0.0 0.0 0.0 ns

tINSU Input F-F Data Setup 1.8 2.0 2.3 2.7 3.0 ns

tIDEH Input Data Enable Hold 0.0 0.0 0.0 0.0 0.0 ns

tIDESU Input Data Enable Setup 5.8 6.5 7.5 8.6 8.6 ns

tOUTH Output F-F Data hold 0.7 0.8 0.9 1.0 1.0 ns

tOUTSU Output F-F Data Setup 0.7 0.8 0.9 1.0 1.0 ns

tODEH Output Data Enable Hold 0.3 0.4 0.4 0.5 0.5 ns

fODESU Output Data Enable Setup 1.3 1.5 1.7 2.0 2.0 ns

Notes: *

1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at

http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case

performance. Post-route timing is based on actual routing delay measurements performed on the device prior to

shipment.

Detailed Specifications

2-28 Revision 3

A1425A, A14V25A Timing Characteristics (continued)

Table 2-24 • A1425A, A14V25A Worst-Ca se Commercial Conditions, VCC = 4.75 V, TJ = 70°C

I/O Module – TTL Output Timing1–3 Speed2–2 Speed2 –1 Speed Std. Sp ee d 3.3 V Speed1Units