eGaN(R) FET DATASHEET EPC2012C EPC2012C - Enhancement Mode Power Transistor VDS , 200 V RDS (on) , 100 m ID , 5 A D EFFICIENT POWER CONVERSION G Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 60 years. GaN's exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings VALUE UNIT Drain-to-Source Voltage (Continuous) PARAMETER 200 V Continuous (TA = 25C, RJA = 26C/W) 5 Pulsed (25C, TPULSE = 300 s) 22 Gate-to-Source Voltage 6 Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 VDS ID VGS HAL S A V C EPC2012C eGaN(R) FETs are supplied only in passivated die form with solder bars Applications * High Frequency DC-DC Conversion * Class D Audio * Wireless Power Transfer Benefits * Ultra High Efficiency * Ultra Low RDS(on) * Ultra Low QG * Ultra Small Footprint www.epc-co.com/epc/Products/eGaNFETs/EPC2012C.aspx Thermal Characteristics PARAMETER TYP RJC Thermal Resistance, Junction to Case 4.2 RJB Thermal Resistance, Junction to Board 12.5 RJA Thermal Resistance, Junction to Ambient (Note 1) UNIT C/W 85 Note 1: RJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25C unless otherwise stated) TEST CONDITIONS MIN BVDSS Drain-to-Source Voltage PARAMETER VGS = 0 V, ID = 60 A 200 IDSS Drain-Source Leakage VGS = 0 V, VDS = 160 V 10 50 A VGS = 5 V 0.2 1 mA IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage VGS(TH) Gate Threshold Voltage RDS(on) Drain-Source On Resistance VSD Source-Drain Forward Voltage VGS = -4 V TYP MAX UNIT V 10 50 A 1.4 2.5 V VGS = 5 V, ID = 3 A 70 100 m IS = 0.5 A, VGS = 0 V 1.9 VDS = VGS, ID = 1 mA 0.8 V All measurements were done with substrate connected to source. EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1 eGaN(R) FET DATASHEET EPC2012C Dynamic Characteristics (TJ = 25C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX 100 140 0.4 0.6 85 CISS Input Capacitance CRSS Reverse Transfer Capacitance COSS Output Capacitance 64 RG Gate Resistance 0.6 QG Total Gate Charge QGS Gate-to-Source Charge QGD Gate-to-Drain Charge QG(TH) Gate Charge at Threshold QOSS Output Charge QRR Source-Drain Recovery Charge VDS = 100 V, VGS = 0 V VDS = 100 V, VGS = 5 V, ID = 3 A UNIT pF 1 1.3 0.3 VDS = 100 V, ID = 3 A 0.2 0.35 nC 0.2 VDS = 100 V, VGS = 0 V 10 13 0 All measurements were done with substrate connected to source. Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS. Figure 2: Transfer Characteristics Figure 1: Typical Output Characteristics at 25C 15 10 VGS = 5 V VGS = 4 V VGS = 3 V VGS = 2 V 5 0 0 1 2 3 4 VDS - Drain-to-Source Voltage (V) 5 15 10 5 0 0.5 6 Figure 3: RDS(on) vs. VGS for Various Drain Currents 1.5 2 2.5 3 3.5 VGS - Gate-to-Source Voltage (V) 4 4.5 5 250 RDS(on ) - Drain-to-Source Resistance (m) ID = 3 A ID = 6 A ID = 10 A ID = 15 A 200 150 100 50 0 1 Figure 4: RDS(on) vs. VGS for Various Temperatures 250 RDS(om) - Drain-to-Source Resistance (m) 25C 125C VDS = 6 V 20 ID - Drain Current (A) ID - Drain Current (A) 20 2 2.5 3 3.5 4 VGS - Gate-to-Source Voltage (V) 4.5 5 25C 125C 200 ID = 3 A 150 100 50 0 EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | 2 2.5 3 3.5 4 VGS - Gate-to-Source Voltage (V) 4.5 5 | 2 eGaN(R) FET DATASHEET 250 EPC2012C Figure 5a: Capacitance (Linear Scale) 103 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 150 100 50 100 150 10-1 200 VDS - Drain-to-Source Voltage (V) Figure 6: Gate Charge 10 3 2 1 0 3 0.2 0.4 0.6 0.8 QG - Gate Charge (nC) 1 0.5 0 -25 200 Figure 7: Reverse Drain-Source Characteristics 25C 125C 0 0 0.5 1 1.5 2 2.5 3 3.5 VSD - Source-to-Drain Voltage (V ) 4 4.5 5 Figure 9: Normalized Threshold Voltage vs. Temperature 1.3 1.5 150 2 1.4 2 100 VDS - Drain-to-Source Voltage (V) 4 1 ID = 3 A VGS = 5 V 50 6 Figure 8: Normalized On Resistance vs. Temperature 2.5 0 8 ISD - Source-to-Drain Current (A) ID = 3 A VDS = 100 V 4 0 Normalized On-State Resistance - RDS(on) 0 Normalized Threshold Voltage (V) VGS - Gate-to-Source Voltage (V) 5 101 100 50 0 COSS = CGD + CSD CISS = CGD + CGS CRSS = CGD 102 C - Capacitance (pF) C - Capacitance (pF) 200 Figure 5b: Capacitance (Log Scale) ID = 1 mA 1.2 1.1 1 0.9 0.8 0.7 0 25 50 75 100 125 TJ - Junction Temperature (C ) 150 0.6 -25 0 25 50 75 100 125 150 TJ - Junction Temperature (C ) All measurements were done with substrate shortened to source. EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 3 eGaN(R) FET DATASHEET EPC2012C 3 Figure 10: Gate Current 25C 125C IG - Gate Current (mA) 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) Figure 11: Transient Thermal Response Curves Junction-to-Board ZB, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.1 0.1 0.05 PDM t1 0.02 0.01 0.01 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZJB x RJB + TB Single Pulse 0.001 1E-5 1E-4 t2 1E-3 1E-2 1E-1 1E+0 1E+1 tp, Rectangular Pulse Duration, seconds Junction-to-Case ZC, Normalized Thermal Impedance 1 Duty Cycle: 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 PDM t1 0.001 Notes: Duty Factor: D = t1/t2 Peak TJ = PDM x ZJC x RJC + TB Single Pulse 0.0001 1E-6 t2 1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 tp, Rectangular Pulse Duration, seconds EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 4 eGaN(R) FET DATASHEET EPC2012C I D - Drain Current (A) Figure 12: Safe Operating Area 10 Limited by RDS(on) Pulse Widths 100 s 1 ms 10 ms 100 ms 1 0.1 TJ = Max Rated, TC = +25C, Single Pulse 0.1 1 10 100 VDS - Drain-Source Voltage (V) TAPE AND REEL CONFIGURATION 4 mm pitch, 8 mm wide tape on 7" reel 7" reel d e f Loaded Tape Feed Direction g Die orientation dot b 2012 YYYY ZZZZ a c Die is placed into pocket solder bar side down (face side down) EPC2012C (note 1) Dimension (mm) target min max a b c (note 2) d e f (note 2) g 8.00 1.75 3.50 4.00 4.00 2.00 1.5 7.90 1.65 3.45 3.90 3.90 1.95 1.5 8.30 1.85 3.55 4.10 4.10 2.05 1.6 Gate solder bar is under this corner Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS 2012 Die orientation dot Gate Pad solder bar is under this corner YYYY ZZZZ Part Number EPC2012C EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 2012 YYYY ZZZZ | 5 eGaN(R) FET DATASHEET EPC2012C DIE OUTLINE A f x2 d Solder Bar View DIM A B c d e f g c 3 4 B d x2 2 1 g MAX 1681 889 662 245 230 245 600 1711 919 667 250 245 250 600 1741 949 672 255 260 255 600 Pad no. 1 is Gate; Pad no. 2 is Substrate;* Pad no. 3 is Drain; Pad no. 4 is Source *Substrate pin should be connected to Source 100 +/- 20 (685) Side View Seating Plane RECOMMENDED LAND PATTERN Nominal g 815 Max e MICROMETERS MIN 1711 (units in m) 1 4 919 3 409 647 230 x2 The land pattern is solder mask defined. 230 x2 230 2 *Substrate pin should be connected to Source 600 RECOMMENDED STENCIL DRAWING Pad no. 1 is Gate; Pad no. 2 is Substrate;* Pad no. 3 is Drain; Pad no. 4 is Source 600 1711 409 3 4 919 230 x2 0 R6 1 647 Recommended stencil should be 4 mil (100 m) thick, must be laser cut , opening per drawing. The corner has a radius of R60. 230 x2 230 (units in m) Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. 2 600 600 Additional assembly resources available at http://www.epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN(R) is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx EPC - THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | Information subject to change without notice. Revised May, 2019 | 6