eGaN® FET DATASHEET
EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1
EPC2012C
EPC2012C – Enhancement Mode Power Transistor
VDS , 200 V
RDS (on) , 100 mΩ
ID , 5 A
EPC2012C eGaN® FETs are supplied only in
passivated die form with solder bars
Applications
• High Frequency DC-DC Conversion
• Class D Audio
• Wireless Power Transfer
Benets
• Ultra High Eciency
• Ultra Low RDS(on)
• Ultra Low QG
• Ultra Small Footprint
EFFICIENT POWER CONVERSION
HAL
G
D
S
Maximum Ratings
PARAMETER VALUE UNIT
VDS Drain-to-Source Voltage (Continuous) 200 V
ID
Continuous (TA = 25˚C, RθJA = 26°C/W) 5 A
Pulsed (25°C, TPULSE = 300 µs) 22
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -4
TJOperating Temperature -40 to 150 °C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC
Thermal Resistance, Junction to Case
4.2
°C/W RθJB
Thermal Resistance, Junction to Board
12.5
RθJA
Thermal Resistance, Junction to Ambient (Note 1)
85
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
All measurements were done with substrate connected to source.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 60 μA 200 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 160 V 10 50 µA
IGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.2 1 mA
Gate-to-Source Reverse Leakage VGS = -4 V 10 50 µA
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 3 A 70 100 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V
www.epc-co.com/epc/Products/eGaNFETs/EPC2012C.aspx
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally
high electron mobility and low temperature coecient allows very low RDS(on), while its lateral
device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end
result is a device that can handle tasks where very high switching frequency, and low on-time are
benecial as well as those where on-state losses dominate.
eGaN® FET DATASHEET
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EPC2012C
ID
– Drain Current (A)
VDS – Drain-to-Source Voltage (V)
15
20
10
5
00 1 2 3 4 5 6
V
GS
= 5 V
V
GS
= 4 V
V
GS
= 3 V
V
GS
= 2 V
Figure 1: Typical Output Characteristics at 25°C
RDS(om)
– Drain-to-Source Resistance (mΩ)
VGS – Gate-to-Source Voltage (V)
250
200
100
50
150
0
2 2.5 3 3.5 4 4.5 5
ID = 3 A
ID = 6 A
ID = 10 A
ID = 15 A
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID
– Drain Current (A)
VGS – Gate-to-Source Voltage (V)
20
15
10
5
00.5 1 1.5 2 2.5 3 4 4.5 53.5
25˚C
125˚C
VDS = 6 V
Figure 2: Transfer Characteristics
RDS(on)
– Drain-to-Source Resistance (m
Ω)
VGS – Gate-to-Source Voltage (V)
50
150
100
200
250
0
2 2.5 3 3.5 4 4.5 5
ID = 3 A
25˚C
125˚C
Figure 4: RDS(on) vs. VGS for Various Temperatures
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS
Input Capacitance
VDS = 100 V, VGS = 0 V
100 140
pFCRSS
Reverse Transfer Capacitance
0.4 0.6
COSS
Output Capacitance
64 85
RG
Gate Resistance
0.6 Ω
QG
Total Gate Charge
VDS = 100 V, VGS = 5 V, ID = 3 A 1 1.3
nC
QGS
Gate-to-Source Charge
VDS = 100 V, ID = 3 A
0.3
QGD
Gate-to-Drain Charge
0.2 0.35
QG(TH)
Gate Charge at Threshold
0.2
QOSS
Output Charge
VDS = 100 V, VGS = 0 V 10 13
QRR
Source-Drain Recovery Charge
0
All measurements were done with substrate connected to source.
Note 2: COSS(ER) is a xed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS.
Note 3: COSS(TR) is a xed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET
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EPC2012C
All measurements were done with substrate shortened to source.
C – Capacitance (pF)
VDS – Drain-to-Source Voltage (V)
50
100
150
200
250
00 50 100 150 200
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 5a: Capacitance (Linear Scale)
VGS – Gate-to-Source Voltage (V)
QG – Gate Charge (nC)
5
4
3
2
1
00 0.2 0.4 0.6 0.8 1
ID = 3 A
VDS = 100 V
Figure 6: Gate Charge
C – Capacitance (pF)
VDS – Drain-to-Source Voltage (V)
100
101
102
103
10-1
0 50 100 150 200
Figure 5b: Capacitance (Log Scale)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
ISD
– Source-to-Drain Current (A
)
VSD – Source-to-Drain Voltage (V )
2
4
6
8
10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 54.5
25˚C
125˚C
Figure 7: Reverse Drain-Source Characteristics
Normalized On-State Resistance – RDS(on)
TJ – Junction Temperature (˚C )
0
0.5
1
1.5
2
2.5
3
-25 0 25 50 75 100 125 150
ID = 3 A
VGS = 5 V
Figure 8: Normalized On Resistance vs. Temperature
Normalized Threshold Voltage (V)
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
-25 0 25 50 75 100 125 150
ID = 1 mA
Figure 9: Normalized Threshold Voltage vs. Temperature
TJ – Junction Temperature (˚C )
eGaN® FET DATASHEET
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EPC2012C
Figure 11: Transient Thermal Response Curves
Duty Cycle:
0.5
0.1
0.05
0.02
0.01
1
0.1
0.01
0.001
1E-5 1E-4 1E-3 1E-2 1E-1 1E+0 1E+1
tp, Rectangular Pulse Duration, seconds
ZθB
, Normalized Thermal Impedance
Single Pulse
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
Junction-to-Board
tp, Rectangular Pulse Duration, seconds
Duty Cycle:
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
ZθC
, Normalized Thermal Impedance
1
0.1
0.01
0.001
0.0001
1E-5 1E-4 1E-3 1E-2 1E-1 1E+01E-6
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TB
PDM
t1
t2
Junction-to-Case
IG – Gate Current (mA)
VGS – Gate-to-Source Voltage (V)
1.5
1
0.5
3
2
2.5
00 1 2 3 4 5 6
25˚C
125˚C
Figure 10: Gate Current
eGaN® FET DATASHEET
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EPC2012C
2012
YYYY
ZZZZ
Part
Number
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
Lot_Date Code
Marking Line 3
EPC2012C 2012 YYYY ZZZZ
Die orientation dot
Gate Pad solder bar
is under this corner
DIE MARKINGS
Figure 12: Safe Operating Area
0.1
1
10
0.1 1 10 100
ID - Drain Current (A)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
TJ = Max Rated, TC = +25°C, Single Pulse
100 µs
1 ms
Pulse Widths
10 ms
100 ms
YYYY
2012
ZZZZ
TAPE AND REEL CONFIGURATION
4 mm pitch, 8 mm wide tape on 7” reel
7” reel
a
d e f g
c
b
Note 1: MSL 1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
Die
orientation
dot
Gate
solder bar is
under this
corner
Die is placed into pocket
solder bar side down
(face side down)
Loaded Tape Feed Direction
Dimension (mm) target min max
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (note 2) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05
g 1.5 1.5 1.6
EPC2012C (note 1)
eGaN® FET DATASHEET
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EPC2012C
RECOMMENDED
LAND PATTERN
(units in µm)
The land pattern is solder mask dened.
DIE OUTLINE
Solder Bar View
Side View
Information subject to
change without notice.
Revised May, 2019
Ecient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Ecient Power Conversion Corporation.
EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
DIM MICROMETERS
MIN Nominal MAX
A1681 1711 1741
B889 919 949
c662 667 672
d245 250 255
e230 245 260
f245 250 255
g600 600 600
B
c
d
x2
1
3 4
2
d
e g g
f
x2
A
815 Max
100 +/- 20
Seating Plane
(685)
Pad no. 1 is Gate;
Pad no. 2 is Substrate;*
Pad no. 3 is Drain;
Pad no. 4 is Source
*Substrate pin should be connected to Source
Pad no. 1 is Gate;
Pad no. 2 is Substrate;*
Pad no. 3 is Drain;
Pad no. 4 is Source
*Substrate pin should be connected to Source
409
919
647
230
x2
2
3 4
1
230
600 600
230
x2
1711
RECOMMENDED
STENCIL DRAWING
(units in µm) Recommended stencil should be 4 mil (100 μm)
thick, must be laser cut , opening per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 3 solder,
reference 88.5% metals content.
Additional assembly resources available at
http://www.epc-co.com/epc/DesignSupport/
AssemblyBasics.aspx
409
919
647
230
x2
2
3 4
1
230
600 600
230
x2
R60
1711