4 CML Output, Low Jitter Clock Generator with an Integrated 5.4 GHz VCO AD9530 Data Sheet FEATURES GENERAL DESCRIPTION Fully integrated, ultralow noise phase-locked loop (PLL) 4 differential, 2.7 GHz common-mode logic (CML) outputs 2 differential reference inputs with programmable internal termination options <232 fs rms absolute jitter (12 kHz to 20 MHz) with a nonideal reference and 8 kHz loop bandwidth <100 fs rms absolute jitter (12 kHz to 20 MHz) with an 80 kHz loop bandwidth and low jitter input reference clock Supports low loop bandwidths for jitter attenuation Manual switchover Single 2.5 V typical supply voltage 48-lead, 7 mm x 7 mm LFCSP The AD9530 is a fully integrated PLL and distribution supporting, clock cleanup, and frequency translation device for 40 Gbps/ 100 Gbps OTN applications. The internal PLL can lock to one of two reference frequencies to generate four discrete output frequencies up to 2.7 GHz. The AD9530 features an internal 5.11 GHz to 5.4 GHz, ultralow noise voltage controlled oscillator (VCO). All four outputs are individually divided down from the internal VCO using two high speed VCO dividers (the Mx dividers) and four individual 8-bit channel dividers (the Dx dividers). The high speed VCO dividers offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of possible output frequencies. The AD9530 is configurable for loop bandwidths <15 kHz to attenuate reference noise. APPLICATIONS The AD9530 is available in a 48-lead LFCSP and operates from a single 2.5 V typical supply voltage. 40 Gbps/100 Gbps optical transport network (OTN) line side clocking Clocking of high speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) Data communications The AD9530 operates over the extended industrial temperature range of -40C to +85C. FUNCTIONAL BLOCK DIAGRAM AD9530 D1 DIVIDER (1 TO 255) REFA REFA 800MHz MAX REFB R DIVIDER (1 TO 255) M1 DIVIDER /2, /2.5, /3, /3.5 D2 DIVIDER (1 TO 255) M2 DIVIDER /2, /2.5, /3, /3.5 D3 DIVIDER (1 TO 255) PLL REFB D4 DIVIDER (1 TO 255) SERIAL PORT AND CONTROL LOGIC SDIO SDO SCLK CS LD CML 50 SOURCE TERMINATED 2.7GHz MAX OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 14044-001 REF_SEL Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9530 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 27 Applications ....................................................................................... 1 Power Supply Recommendations............................................. 27 General Description ......................................................................... 1 Using the AD9530 Outputs for ADC Clock Applications .... 27 Functional Block Diagram .............................................................. 1 Typical Application Block Diagram ......................................... 28 Revision History ............................................................................... 3 Control Registers ............................................................................ 29 Specifications..................................................................................... 4 Control Register Map Overview .............................................. 29 Supply Voltage and Temperature Range .................................... 4 Control Register Map Descriptions ............................................. 31 Supply Current .............................................................................. 4 SPI Configuration (Register 0x000 to Register 0x001) ......... 31 Power Dissipation ......................................................................... 5 Status (Register 0x002) .............................................................. 32 REFA and REFB Input Characteristics ...................................... 6 Chip Type (Register 0x003) ...................................................... 32 PLL Characteristics ...................................................................... 7 Product ID (Register 0x004 to Register 0x005)...................... 32 PLL Digital Lock Detect .............................................................. 7 Part Version (Register 0x006) ................................................... 33 Clock Outputs (Internal Termination Disabled) ..................... 7 User Scratchpad 1 (Register 0x00A) ........................................ 33 Clock Outputs (Internal Termination Enabled)....................... 8 SPI Version (Register 0x00B) .................................................... 33 Clock Output Absolute Time Jitter (Low Loop Bandwidth) .................................................................................... 9 Vendor ID (Register 0x00C to Register 0x00D)..................... 33 Clock Output Absolute Time Jitter (High Loop Bandwidth) .................................................................................. 10 R Divider (Reference Input Divider) (Register 0x010) ......... 33 RESET and REF_SEL Pins ........................................................ 10 LD Pin .......................................................................................... 10 Serial Control Port ..................................................................... 10 Absolute Maximum Ratings .......................................................... 12 Thermal Resistance .................................................................... 12 ESD Caution ................................................................................ 12 Pin Configuration and Function Descriptions ........................... 13 Typical Performance Characteristics ........................................... 15 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 18 Detailed Functional Block Diagram ........................................ 18 Overview...................................................................................... 18 Configuration of the PLL .......................................................... 18 Reset Modes ................................................................................ 21 Power-Down Modes................................................................... 21 Input/Output Termination Recommendations .......................... 22 Serial Control Port .......................................................................... 23 SPI Serial Port Operation .......................................................... 23 Power Dissipation and Thermal Considerations ....................... 26 Clock Speed and Driver Mode ................................................. 26 Evaluation of Operating Conditions ........................................ 26 Thermally Enhanced Package Mounting Guidelines ............ 26 IO_UPDATE (Register 0x00F) ................................................. 33 R Divider Control (Register 0x011) ......................................... 34 Reference Input A (Register 0x012) ......................................... 34 Reference Input B (Register 0x013) ......................................... 34 OUT1 Divider (Register 0x014) ............................................... 35 OUT1 Driver Control Register (Register 0x015) ................... 35 OUT2 Divider (Register 0x016) ............................................... 35 OUT2 Driver Control (Register 0x017) .................................. 35 OUT3 Divider (Register 0x018) ............................................... 36 OUT3 Driver Control (Register 0x019) .................................. 36 OUT4 Divider (Register 0x01A) .............................................. 36 OUT4 Driver Control (Register 0x01B) .................................. 36 VCO Power (Register 0x01C) ................................................... 37 PLL Lock Detect Control (Register 0x01D) ........................... 37 PLL Lock Detect Readback (Registers 0x01E to 0x01F) ....... 37 M1, M2, M3 Dividers (Register 0x020 to Register 0x022) ... 38 M3 Divider (Register 0x022) .................................................... 39 N Divider (Register 0x023) ....................................................... 39 N Divider Control (Register 0x024) ........................................ 39 Charge Pump (Register 0x025) ................................................ 39 Phase Frequency Dectector (Register 0x026) ......................... 39 Loop Filter (Register 0x027) ..................................................... 40 VCO Frequency (Register 0x028) ............................................ 40 User Scratchpad2 (Register 0x0FE) ......................................... 40 Rev. 0 | Page 2 of 41 Data Sheet AD9530 User Scratchpad3 (Register 0x0FF) ..........................................40 Ordering Guide ........................................................................... 41 Outline Dimensions ........................................................................41 REVISION HISTORY 4/16--Revision 0: Initial Version Rev. 0 | Page 3 of 41 AD9530 Data Sheet SPECIFICATIONS Typical values are given for VDD = 2.5 V 5%, TA = 25C, unless otherwise noted. Minimum and maximum values are given over the full VDD range and TA (-40C to +85C) variations listed in Table 1. SUPPLY VOLTAGE AND TEMPERATURE RANGE SPECIFICATIONS Table 1. Parameter SUPPLY VOLTAGE TEMPERATURE Ambient Temperature Range Junction Temperature 1 1 Symbol VDD Min 2.375 Typ 2.5 Max 2.625 Unit V TA TJ -40 +25 +85 115 C C Test Conditions/Comments 2.5 V 5% The is the maximum junction temperature for which device performance is guaranteed. Note that the Absolute Maximum Ratings section may have a higher maximum junction temperature, but device operation or performance is not guaranteed above the number that appears here. To calculate the junction temperature, see the Power Dissipation and Thermal Considerations section. SUPPLY CURRENT SPECIFICATIONS Table 2. Parameter SUPPLY CURRENT OTHER THAN CLOCK THE DISTRIBUTION CHANNEL Min Typ Max Unit 8.2 18.2 747 10.7 24 860 mA mA mA Typical Operation 1 Reference Input VDD (Pin 3 and Pin 7) PLL VDD (Pin 12) Rotary Travelling Wave Oscillator (RTWO) VDD (Pin 20 to Pin 23) SUPPLY CURRENT FOR AN INDIVIDUAL CLOCK DISTRIBUTION CHANNEL CML Internal Termination Disabled 800 mV 900 mV 1000 mV 1100 mV Internal Termination Enabled 800 mV 900 mV 1000 mV 1100 mV Test Conditions/Comments Current listed in the Typ column is at nominal VDD at 25C; current listed in the Max column is at maximum VDD and worst case temperature fRTWO = 5300.16 MHz; VCO mode = low power; REFA enabled at 110.42 MHz; REFB disabled; R divider = 1; M1 and M3 divider = 3; M2 divider = powered down; phase frequency detector (PFD) = 110.42 MHz; OUT1 CML output at 1766.72 MHz; OUT2, OUT3, and OUT4 outputs and dividers powered down; single-ended output swing level = 800 mV; outputs terminated externally with 50 to VDD Combined current of Pin 3 and Pin 7 Combined current of Pin 20 to Pin 23 Each output channel has a dedicated VDD pin; all current values are listed for a single driver supply pin operating at 1766.72 MHz; output terminated externally, 50 to VDD; these specifications include the current required for the external load resistors 28.8 30.7 32.6 34.5 35.5 37.6 39.8 41.8 mA mA mA mA 47.6 51.5 55.3 59.0 57.2 61.5 65.8 70.1 mA mA mA mA Rev. 0 | Page 4 of 41 Data Sheet AD9530 Parameter CURRENT DELTAS, INDIVIDUAL FUNCTIONS Min Typ Max Unit VCO High Performance Mode Enabled 133.5 160.0 mA REFx/REFx Receiver 1 2.5 3.3 mA Reference Divider -0.55 -0.39 Output Channel 1 mA 28.4 33.3 mA Mx Divider On/Off 33.2 36.2 mA Single Output Plus Associated Channel Divider (OUT1: Pin 31, OUT2: Pin 35, OUT3: Pin 41, OUT4: Pin 45) 28.4 33.4 mA Test Conditions/Comments Current delta when a function is enabled/disabled from Typical Operation 1 Current increase when the VCO mode is changed from low power mode to high performance mode; combined current delta of Pin 20 to Pin 23 Current increase when REFB is enabled with a 110.42 MHz reference input; combined current delta of Pin 3 and Pin 7 Delta from bypassing reference divider to using reference divider = 2; total feedback division doubled to preserve lock; combined current delta of Pin 3 and Pin 7 One output channel enabled by powering up M2 divider = 3; D3 and D4 divider = 1; OUT3 and OUT4 enabled to 800 mV; no internal termination; associated low-dropout regulators (LDOs) enabled; includes the current required by the external termination; both outputs at 1766.72 MHz This is the current consumption delta between an Mx (where x is 0, 1, or 2) divider powered up and powered down; these dividers are a part of the RTWO VDD (Pin 20 to Pin 23) power domain One output driver enabled by powering up the driver and channel divider (does not include power on the extra M2 divider); includes the current required by the external termination; output = 1766.72 MHz Where x is either A or B. POWER DISSIPATION SPECIFICATIONS Table 3. Parameter TOTAL POWER DISSIPATION Power-On Default Power-Down Mode Typical Operation 2 Min Typ Max Unit 2.284 0.338 2.344 2.750 0.480 2.82 W W W 2.536 3.02 W 2.796 3.326 W All Blocks Running 800 mV Output Swing, Without Internal Output Termination 1100 mV Output Swing with Internal Output Termination Rev. 0 | Page 5 of 41 Test Conditions/Comments Does not include power dissipated in external resistors; all CML outputs terminated with 50 to VDD; internal output termination is disabled; output amplitude set to 1.0 V; reference inputs set to ac-coupled mode fRTWO = 5302.5 MHz; VCO mode = high performance; REFA enabled at 101 MHz, ac-coupled; REFB disabled; R divider = 1; M1 divider and M3 divider = 2.5; PFD = 101 MHz; OUT1 and OUT2 CML outputs at 2121 MHz; OUT3 and OUT4 disabled; output swing level = 800 mV; outputs terminated externally to 50 to VDD and internal termination disabled; M2 divider and LDO powered down; D3 and D4 dividers and associated LDOs disabled fRTWO = 5400 MHz; VCO mode = high performance; REFA and REFB enabled at 100 MHz; ac-coupled mode; R divider = 1; M divider = 2; PFD = 100 MHz; four CML outputs at 2700 MHz Single-ended output swing level = 800 mV and internal termination off Single-ended output swing level = 1100 mV and internal termination on AD9530 Data Sheet REFA/REFA AND REFB/REFB INPUT CHARACTERISTICS Table 4. Parameter DC-COUPLED LVDS MODE (REFA, REFA; REFB, REFB) Min Input Frequency 6 Input Sensitivity 494 Common-Mode Input Voltage Differential Input Resistance 0.4 Input Capacitance DC-COUPLED CML MODE (REFA, REFA, REFB, REFB) Input Frequency 6 Input Sensitivity 494 Common-Mode Input Voltage Single-Ended Input Resistance Input Capacitance AC-COUPLED CML MODE (REFA, REFA, REFB, REFB) Max Unit 800 MHz mV p-p 110 1.4 V 3 pF 800 0.4 V pF 800 MHz 55 3 6 Input Sensitivity 494 Input Self Bias Voltage (VTT) (Internally Generated) Differential Input Resistance 0.32 Input Capacitance DC-COUPLED HIGH-Z MODE (REFA, REFA, REFB, REFB) Input Frequency 6 Input Sensitivity 494 Common-Mode Input Voltage Differential Input Resistance 0.4 MHz mV p-p 0.3 Input Frequency Input Capacitance Typ mV p-p 0.355 0.39 V 105 3 pF 800 MHz mV p-p 10.3 1.4 V k 3 pF Rev. 0 | Page 6 of 41 Test Conditions/Comments DC-coupled LVDS mode (REFx_TERM_SEL = 00); includes an internal 100 differential termination; inputs are not self biased in this setting Assumes a minimum of 494 mV p-p differential amplitude as measured with a differential probe at the REFx input pins Peak-to-peak differential voltage swing across the pins to ensure switching between logic levels as measured with a differential probe Allowable common-mode voltage for dc coupling Differential input resistance measured across the REFx and REFx pins Input capacitance measured from each REFx pin to GND DC-coupled (REFx_TERM_SEL = 01); includes an internal termination of 50 from each REFx input to GND; inputs are not self biased in this setting Assumes a minimum of 494 mV p-p differential amplitude as measured with a differential probe at the REFx input pins Peak-to-peak differential voltage swing across pins to ensure switching between logic levels as measured with a differential probe Allowable common-mode voltage for dc coupling Input resistance measured from each REFx pin to GND Input capacitance measured from each REFx pin to GND AC-coupled mode (REFx_TERM_SEL = 10); includes an internal termination of 50 from each REFx input to a nominal dc bias of 0.35 V Assumes a minimum of 494 mV p-p differential amplitude as measured with a differential probe at the REFx input pins Peak-to-peak differential voltage swing across pins to ensure switching between logic levels as measured with a differential probe Self bias voltage of the REFx and REFx inputs in accoupled mode (REFx_TERM_SEL = 10) Differential input resistance measured across the REFx and REFx pins Input capacitance measured from each REFx pin to GND DC-coupled high-Z mode (REFx_TERM_SEL = 11) places the REFx inputs into a high impedance state; inputs are not self biased in this setting Assumes a minimum of 500 mV p-p differential amplitude as measured with a differential probe at the REFx input pins Peak-to-peak differential voltage swing across pins to ensure switching between logic levels as measured with a differential probe Differential input resistance measured across the REFx and REFx pins Input capacitance measured from each REFx pin to GND Data Sheet AD9530 Parameter DUTY CYCLE Min Pulse Width Low High Typ Max Unit 600 600 Test Conditions/Comments Duty cycle bounds are set by pulse width high and pulse width low ps ps PLL CHARACTERISTICS Table 5. Parameter RTWO Frequency Range VCO Gain (KVCO) PHASE FREQUENCY DETECTOR (PFD) PFD Input Frequency CHARGE PUMP (CP) Sink/Source Current (ICP) Min Typ Max Unit 5.4 GHz MHz/V 6 6 800 500 MHz MHz Antibacklash pulse width disabled (Register 0x026, Bit 1 = 0) Antibacklash pulse width enabled (Register 0x026, Bit 1 = 1) 0.05 2.6 mA Register 0x025, Bits[5:0] controls the charge pump current (see Table 56) 3.2 F Maximum value for the C2 capacitor in Figure 16; using a loop filter capacitor value larger than the maximum may affect device functionality sec Minimum wait time implemented before issuing the first RTWO calibration after a POR 5.11 180 LOOP FILTER External Loop Filter Capacitor POWER-ON RESET (POR) TIMER Internal Wait Time 2 Test Conditions/Comments PLL DIGITAL LOCK DETECT SPECIFICATIONS Table 6. Parameter PLL DIGITAL LOCK DETECT WINDOW 1 Lock Threshold 1 Min Typ 0.020 Max Unit 300 ppm Test Conditions/Comments Signal available at the LD pin and in Register 0x01F, Bit 2 Lock threshold is selected by Register 0x01D, Bits[3:1], which is the threshold for transitioning from unlock to lock and vice versa For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the lock detector update interval (see Table 48). CLOCK OUTPUTS (INTERNAL TERMINATION DISABLED) SPECIFICATIONS Table 7. Parameter CML MODE 800 mV Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle Min Typ 5.725 Max Unit MHz ps % % % % mV V Output Differential Voltage, Magnitude 47 48 45 48 600 51 51 50 845 2700 107 53 54 57 53 1090 Common-Mode Output Voltage 1.82 2.075 2.32 78 Test Conditions/Comments All outputs are externally terminated with 50 to VDD Any Mx divider, output divider 1 Mx divider = 2, output divider = 1 Mx divider = 2.5, output divider = 1 Mx divider = 3, output divider = 1 Voltage difference between the output pins; output driver is static; in normal operation, the peak-to-peak amplitude is approximately 2x this value if measured with a differential probe Measured with output driver static Rev. 0 | Page 7 of 41 AD9530 Parameter 900 mV Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle Output Differential Voltage, Magnitude Common-Mode Output Voltage 1000 mV Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle Output Differential Voltage, Magnitude Common-Mode Output Voltage 1100 mV Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle Data Sheet Min Typ 5.725 Max Unit MHz ps % % % % mV 47 48 45 49 675 51 51 51 950 2700 98 53 54 57 53 1340 1.76 2.03 2.29 V MHz ps % % % % mV 77 5.725 47 48 45 49 730 51 51 51 1040 2700 105 53 54 57 52 1340 1.69 1.97 2.25 V MHz ps % % % % mV V 76 Test Conditions/Comments All outputs are externally terminated with 50 to VDD Any Mx divider, output divider 1 Mx divider = 2, output divider = 1 Mx divider = 2.5, output divider = 1 Mx divider = 3, output divider = 1 Voltage difference between the output pins; output driver is static; in normal operation, the peak-to-peak amplitude is approximately 2x this value if measured with a differential probe Measured with output driver static All outputs are externally terminated with 50 to VDD Any Mx divider, output divider 1 Mx divider = 2, output divider = 1 Mx divider = 2.5, output divider = 1 Mx divider = 3, output divider = 1 Voltage difference between the output pins; output driver is static; in normal operation, the peak-to-peak amplitude is approximately 2x this value if measured with a differential probe All outputs are externally terminated with 50 to VDD 5.725 Output Differential Voltage, Magnitude 47 48 45 49 815 51 51 50 1140 2700 104 53 54 57 52 1480 Common-Mode Output Voltage 1.61 1.92 2.22 76 Any Mx divider, output divider 1 Mx divider = 2, output divider = 1 Mx divider = 2.5, output divider = 1 Mx divider = 3, output divider = 1 Voltage difference between the output pins; output driver is static; in normal operation, the peak-to-peak amplitude is approximately 2x this value if measured with a differential probe Measured with output driver static CLOCK OUTPUTS (INTERNAL TERMINATION ENABLED) SPECIFICATIONS Table 8. Parameter CML MODE 800 mV Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle Min Typ 5.725 Max Unit MHz ps % % % % mV V Output Differential Voltage, Magnitude 47 48 43 48 590 52 51 51 830 2700 75 53 56 60 53 1070 Common-Mode Output Voltage 1.9 2.08 2.26 55 Rev. 0 | Page 8 of 41 Test Conditions/Comments All outputs are externally terminated with 50 to VDD Any Mx divider, output divider 1 Mx divider = 2, output divider = 1 Mx divider = 2.5, output divider = 1 Mx divider = 3, output divider = 1 Voltage difference between the output pins; output driver is static; in normal operation, the peak-to-peak amplitude is approximately 2x this value if measured with a differential probe Measured with output driver static Data Sheet AD9530 Parameter 900 mV Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle Min Typ 5.725 Common-Mode Output Voltage 1000 mV Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle 52 51 51 930 1.83 2.03 2.23 V MHz ps % % % % mV 47 47 43 48 735 52 52 51 1025 2700 71 53 56 60 53 1335 1.83 2.03 2.23 V 2700 72 53 56 60 54 1455 MHz ps % % % % mV 2.23 V 53 Common-Mode Output Voltage 1100 mV Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle 5.725 53 Output Differential Voltage, Magnitude Common-Mode Output Voltage INTERNAL OUTPUT TERMINATION RESISTANCE MHz ps % % % % mV 47 48 43 48 660 5.725 Output Differential Voltage, Magnitude Unit 2700 70 53 56 60 53 1200 53 Output Differential Voltage, Magnitude Max 47 47 43 48 810 1.71 52 52 51 1125 1.93 53.7 Test Conditions/Comments All outputs are externally terminated with 50 to VDD Any Mx divider, output divider 1 Mx divider = 2, output divider = 1 Mx divider = 2.5, output divider = 1 Mx divider = 3, output divider = 1 Voltage difference between the output pins; output driver is static; in normal operation, the peak-to-peak amplitude is approximately 2x this value if measured with a differential probe Measured with output driver static All outputs are externally terminated with 50 to VDD Any Mx divider, output divider 1 Mx divider = 2, output divider = 1 Mx divider = 2.5, output divider = 1 Mx divider = 3, output divider = 1 Voltage difference between the output pins; output driver is static; in normal operation, the peak-to-peak amplitude is approximately 2x this value if measured with a differential probe Measured with output driver static All outputs are externally terminated with 50 to VDD Any Mx divider, output divider 1 Mx divider = 2, output divider = 1 Mx divider = 2.5, output divider = 1 Mx divider = 3, output divider = 1 Voltage difference between the output pins; output driver is static; in normal operation, the peak-to-peak amplitude is approximately 2x this value if measured with a differential probe Measured with output driver static Measured with output driver static CLOCK OUTPUT ABSOLUTE TIME JITTER (LOW LOOP BANDWIDTH) SPECIFICATIONS Table 9. Parameter CML OUTPUT ABSOLUTE TIME JITTER fOUT = 2700 MHz fOUT = 2100 MHz fOUT = 2050 MHz fOUT = 1768 MHz fOUT = 1500 MHz fOUT = 100 MHz Min Typ 219 220 214 219 210 232 Max Unit fs rms fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments REFA enabled and ac-coupled; R divider = 1; Mx divider value varies; loop bandwidth = 8 kHz; output divider bypassed unless otherwise noted; single-ended output swing level = 1000 mV; no internal termination; VCO in high power mode, integration bandwidth = 12 kHz to 20 MHz Reference frequency = 100 MHz, Mx divider = 2 Reference frequency = 100 MHz, Mx divider = 2.5 Reference frequency = 102.5 MHz, Mx divider = 2.5 Reference frequency = 104 MHz, Mx divider = 3 Reference frequency = 100 MHz, Mx divider = 3.5 Reference frequency = 100 MHz, Mx divider = 3, output divider (Dx divider) = 17 Rev. 0 | Page 9 of 41 AD9530 Data Sheet CLOCK OUTPUT ABSOLUTE TIME JITTER (HIGH LOOP BANDWIDTH) SPECIFICATIONS Table 10. Parameter CML OUTPUT ABSOLUTE TIME JITTER Min Typ 93 Max Unit fs rms Test Conditions/Comments REFA enabled and ac-coupled; R divider = 1; Mx divider value = 2; loop bandwidth = 80 kHz; output divider bypassed; single-ended output swing level = 1000 mV; no internal termination; VCO in high power mode; reference frequency = 860 MHz; output frequency = 2.58 GHz; integration bandwidth = 12 kHz to 20 MHz; absolute jitter value also depends on the noise of the input clock in the 12 kHz to 80 kHz range RESET AND REF_SEL PINS SPECIFICATIONS Table 11. Parameter INPUT CHARACTERISTICS Voltage Logic 1 Logic 0 Current Logic 1 Logic 0 Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming Min Typ VDD - 0.5 Max Unit VDD 0.5 V V 1 36 3 100 50 A A pF ns ms LD PIN SPECIFICATIONS Table 12. Parameter OUTPUT CHARACTERISTICS Output Voltage High Low Symbol Min Typ VOH VOL VDD - 0.5 Max Unit 0.5 V V Test Conditions/Comments 1 mA output load SERIAL CONTROL PORT SPECIFICATIONS Table 13. Parameter CS (INPUT) Input Voltage Logic 1 Logic 0 Input Current Logic 1 Logic 0 Input Capacitance SCLK (INPUT) Input Voltage Logic 1 Logic 0 Input Current Logic 1 Logic 0 Input Capacitance Symbol Min Typ Max Unit 0.4 V V VDD - 0.4 1 32 3 Test Conditions/Comments CS has an internal 75 k pull-up resistor A A pF SCLK has an internal 75 k pull-down resistor VDD - 0.4 0.4 45 1 3 Rev. 0 | Page 10 of 41 V V A A pF Data Sheet Parameter SDIO (INPUT) Input Voltage Logic 1 Logic 0 Input Current Logic 1 Logic 0 Input Capacitance SDIO, SDO (OUTPUTS) Output Voltage Logic 1 Logic 0 TIMING Clock Rate (SCLK) Pulse Width High Pulse Width Low SDIO to SCLK Setup SCLK to SDIO Hold SCLK to Valid SDIO and SDO CS to SCLK Setup CS to SCLK Hold CS Minimum Pulse Width High AD9530 Symbol Min Typ Max Unit 0.4 V V VDD - 0.4 1 1 3 Test Conditions/Comments A A pF 1 mA load current VDD - 0.2 0.2 V V See Figure 26 through Figure 30 and Table 21 1/tSCLK tHIGH tLOW tDS tDH tDV tS tH tPWH 40 6 6 1.8 0.6 10 0.6 3.5 1.5 Rev. 0 | Page 11 of 41 MHz ns ns ns ns ns ns ns ns AD9530 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 14. Parameter VDD, BP_CAP_1, BP_CAP_2, BP_CAP_3, REFA, REFA, REFB, REFB, SCLK, SDIO, SDO, CS, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, RESET, and REF_SEL to GND Junction Temperature1 Storage Temperature Range Operating Temperature Range Lead Temperature (10 sec) 1 Rating 2.625 V Table 15. Thermal Resistance (Simulated) Package Type 48-Lead LFCSP 150C -65C to +150C -40C to +85C 300C See Table 15 for JA. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Airflow Velocity (m/sec) 0 1.0 2.5 JA1, 2 25.8 22.2 19.7 JC1, 3, 4 2.8 N/A N/A JB1, 4, 5 7.5 N/A N/A JT1, 2, 4 0.20 N/A N/A Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-Std 883, Method 1012.1. 4 N/A means not applicable. 5 Per JEDEC JESD51-8 (still air). 1 2 3 ESD CAUTION Rev. 0 | Page 12 of 41 Unit C/W C/W C/W Data Sheet AD9530 48 47 46 45 44 43 42 41 40 39 38 37 LF_2 LF_3 DNC VDD OUT4 OUT4 GND VDD OUT3 OUT3 GND DNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9530 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 DNC VDD OUT2 OUT2 GND VDD OUT1 OUT1 GND GND BP_CAP_3 BP_CAP_2 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS. 2. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 14044-003 RESET SDO SDIO SCLK CS LD DNC VDD VDD VDD VDD BP_CAP_1 13 14 15 16 17 18 19 20 21 22 23 24 LF_1 1 DNC 2 VDD 3 REFA 4 REFA 5 GND 6 VDD 7 REFB 8 REFB 9 GND 10 REF_SEL 11 VDD 12 Figure 2. Pin Configuration Table 16. Pin Function Descriptions Pin No. 1 Mnemonic LF_1 Type 1 O Description Loop Filter Connection, Negative Output Side of the Active Loop Filter Op Amp. Connect the PLL active loop filter components (R1, C1, and C2) to this pin and LF_2 (Pin 48). Do Not Connect. Do not connect to this pin. 2, 19, 36, 37, 46 3 4 5 DNC N/A VDD REFA REFA P I I 6 7 8 9 GND VDD REFB REFB GND P I I 10 11 GND REF_SEL GND I 12 13 14 15 16 17 18 20 to 23 24 25 26 27 28 VDD RESET SDO SDIO SCLK CS LD VDD P I O I/O I I O P Power Supply for REFA. Reference Clock Input A. This pin, along with REFA, is the first differential reference input for the PLL. Complimentary Reference Clock Input A. This pin, along with REFA, is the first differential reference input for the PLL. Ground for the REFA Power Supply. Connect this pin to ground. Power Supply for REFB. Reference Clock Input B. This pin, along with REFB, is the second differential reference input for the PLL. Complimentary Reference Clock Input B. This pin, along with REFB, is the second differential reference input for the PLL. Ground for the REFB Power Supply. Connect this pin to ground. Reference Input Select. This pin is the digital input to select REFA or REFB as the active reference to the PLL. This pin has an internal 75 k pull-up resistor. Logic high (default) selects REFA. Logic low selects REFB. Power Supply for the Serial Port Interface (SPI) and the PFD. Chip Reset, Active Low. This pin has an internal 75 k pull-up resistor. Serial Control Port Unidirectional Serial Data Output. This pin is high impedance during 3-wire SPI mode. Serial Control Port Bidirectional Serial Data Input/Output. Serial Control Port Clock Signal. This pin has an internal 75 k pull-down resistor. Serial Control Port Chip Select, Active Low. This pin has an internal 75 k pull-up resistor. PLL Lock Detect Output. 2.5 V Power Supply for the RTWO Internal LDO. BP_CAP_1 BP_CAP_2 BP_CAP_3 GND GND O O O GND GND RTWO LDO Op Amp Bypass Capacitor. Connect an external 0.01 F capacitor from this pin to GND. RTWO LDO Bypass Capacitor. Connect an external 1 F capacitor from this pin to GND. RTWO Bias Supply Bypass Capacitor. This pin can be left unconnected (floating). Ground for RTWO Power Supply. Connect this pin to ground. Ground for OUT1 Power Supply. Connect this pin to ground. Rev. 0 | Page 13 of 41 AD9530 Data Sheet Pin No. 29 Mnemonic OUT1 Type 1 O 30 OUT1 O 31 32 33 34 35 38 39 40 41 42 43 44 45 47 48 VDD GND OUT2 OUT2 VDD GND OUT3 OUT3 VDD GND OUT4 OUT4 VDD LF_3 LF_2 P GND O O P GND O O P GND O O P O O EP GND 1 Description CML Complementary Output 1. This pin requires a 50 to VDD termination even if the output is unused. See the CML Output Drivers section for more information. CML Output 1. This pin requires a 50 termination to VDD, even if the output is unused. See the CML Output Drivers section for more information. Power Supply for OUT1. Ground for OUT2 Power Supply. Connect this pin to ground. CML Complementary Output 2. CML Output 2. Power Supply for OUT2. Ground for OUT3 Power Supply. Connect this pin to ground. CML Complementary Output 3. CML Output 3. Power Supply for OUT3. Ground for OUT4 Power Supply. Connect this pin to ground. CML Complementary Output 4. CML Output 4. Power Supply for OUT4. Loop Filter Connection. Connect an external capacitor (CA) between this pin and ground. Loop Filter Connection. This pin is the output side of the active loop filter op amp. Connect the PLL active loop filter components (R1, C1, and C2) to this pin and LF_1 (Pin 1). Exposed Pad. The exposed pad is a ground connection on the chip that must be soldered to the analog ground of the printed circuit board (PCB) to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. O means output, N/A means not applicable, P means power, I means input, GND means ground, and I/O means input/output. Rev. 0 | Page 14 of 41 Data Sheet AD9530 TYPICAL PERFORMANCE CHARACTERISTICS CML = 1.1V CML = 1.0V CML = 0.9V CML = 0.8V 350mV/DIV 2.5ns/DIV A CH1 40.0GS/s IT 1.0ps/pt 14044-007 14044-004 CML = 1.1V CML = 1.0V CML = 0.9V CML = 0.8V -7.0mV 350mV/DIV Figure 3. CML Output Waveform (Differential) at 101 MHz, Internal Termination Disabled 100ps/DIV A CH1 40.0GS/s IT 500fs/pt 42.0mV Figure 6. CML Output Waveform (Differential) at 2650 MHz, Internal Termination Enabled 1.8 1.7 CML = 1.1V CML = 1.0V CML = 0.9V CML = 0.8V 1.6 AMPLITUDE (V) 1.5 1.4 1.3 1.2 1.1 331 OUTPUT FREQUENCY (MHz) Figure 4. CML Output Waveform (Differential) at 101 MHz, Internal Termination Enabled 14044-008 442 530 1060 1325 1768 2120 0.8 -7.0mV 2650 2.5ns/DIV A CH1 40.0GS/s IT 1.0ps/pt 662 14044-005 350mV/DIV 0.9 TERMINATION ON TERMINATION ON TERMINATION ON TERMINATION ON 884 CML = 0.8V, CML = 0.9V, CML = 1.0V, CML = 1.1V, 1.0 Figure 7. Differential Voltage Amplitude vs. Output Frequency, Internal Termination Enabled 1.8 CML = 0.8V, CML = 0.9V, CML = 1.0V, CML = 1.1V, 1.7 CML = 1.1V CML = 1.0V CML = 0.9V CML = 0.8V 1.6 TERMINATION OFF TERMINATION OFF TERMINATION OFF TERMINATION OFF AMPLITUDE (V) 1.5 1.4 1.3 1.2 1.1 14044-006 1.0 331 OUTPUT FREQUENCY (MHz) Figure 5. CML Output Waveform (Differential) at 2650 MHz, Internal Termination Disabled Figure 8. Differential Voltage Amplitude vs. Output Frequency, Internal Termination Disabled Rev. 0 | Page 15 of 41 14044-009 442 530 662 884 1060 1325 1768 0.8 42.0mV 2120 100ps/DIV A CH1 40.0GS/s IT 500fs/pt 2650 350mV/DIV 0.9 AD9530 Data Sheet -20 -50 -60 2 1 -90 3 -100 -110 -120 -130 4 5 NOISE: ANALYSIS RANGE X: START 12kHz STOP 20MHz INTG NOISE: -51.4221dBc/19.69MHz RMS NOISE: 3.79671mRAD 217.536mdeg RMS JITTER: 223.802fsec RESIDUAL FM: 1.57236kHz -140 -150 -160 -170 -180 100 1k 10k -70 -80 -90 1M 10M 100M -180 100 PHASE NOISE (dBc) -50 -60 2 3 -120 -130 4 5 NOISE: ANALYSIS RANGE X: START 12kHz STOP 20MHz INTG NOISE: -54.1475dBc/19.69MHz RMS NOISE: 2.77421mRAD 158.951mdeg RMS JITTER: 210.252fsec RESIDUAL FM: 1.23877kHz -140 -150 -160 -170 -180 100 1k 10k 1M 10M 100M 10M 100M 100Hz, -78.6193dBc/Hz 1kHz, -73.4151dBc/Hz 10kHz, -92.6392dBc/Hz 100kHz, -120.8504dBc/Hz 1MHz, -143.4421dBc/Hz 10MHz, -156.4311dBc/Hz 100MHz, -160.8215dBc/Hz 2 1 -100 -110 3 -120 -130 4 NOISE: ANALYSIS RANGE X: START 12kHz STOP 20MHz INTG NOISE: -57.0182/19.69MHz RMS NOISE: 1.99345mRAD 114.216mdeg RMS JITTER: 211.512fsec RESIDUAL FM: 924.222kHz -180 100 1k 10k 5 7 6 100k 1M 10M 100M FREQUENCY (Hz) Figure 10. Phase Noise, fOUT = 2.1 GHz, Loop Bandwidth = 8 kHz Figure 13. Phase Noise, fOUT = 1.5 GHz, Loop Bandwidth = 8 kHz, High Performance Mode -20 -40 -50 -60 100Hz, -76.5195dBc/Hz 1kHz, -72.1524dBc/Hz 10kHz, -90.4665dBc/Hz 100kHz, -118.45978dBc/Hz 1MHz, -141.0204dBc/Hz 10MHz, -153.8759dBc/Hz 100MHz, -164.4190dBc/Hz -60 -70 2 1 3 -100 -110 4 -180 100 1k 10k 100k 5 6 -80 -100 1 -110 2 -120 3 -130 -140 NOISE: ANALYSIS RANGE X: START 12kHz STOP 20MHz INTG NOISE: -59.5089dBc/19.69MHzMHz RMS NOISE: 1.49648mRAD 85.7421mdeg RMS JITTER: 92.314fsec RESIDUAL FM: 1.58172kHz -160 7 -170 1M 10M 100M FREQUENCY (Hz) 1Hz, -94.3202dBc/Hz 10kHz, -109.4110dBc/Hz 100kHz, -114.0837dBc/Hz 1MHz, -139.4227dBc/Hz 10MHz, -151.9086dBc/Hz 40MHz, -157.7001dBc/Hz -90 -150 -180 14044-012 NOISE: ANALYSIS RANGE X: START 12kHz STOP 20MHz INTG NOISE: -54.8028/19.69MHz RMS NOISE: 2.57262mRAD 174.4mdeg RMS JITTER: 199.729fsec RESIDUAL FM: 1.22141kHz 1: 2: 3: 4: 5: 6: -50 PHASE NOISE (dBc) 1: 2: 3: 4: 5: 6: 7: -30 -40 PHASE NOISE (dBc) -90 -160 -170 6 100k -70 -80 -140 -150 7 FREQUENCY (Hz) -160 -170 1M 1: 2: 3: 4: 5: 6: 7: -30 -40 1 -100 -110 -140 -150 100k 14044-014 100Hz, -77.2438dBc/Hz 1kHz, -72.2169dBc/Hz 10kHz, -89.3822dBc/Hz 100kHz, -118.0579dBc/Hz 1MHz, -140.6235dBc/Hz 10MHz, -153.7840dBc/Hz 100MHz, -158.1045dBc/Hz 14044-011 PHASE NOISE (dBc) -50 -60 -120 -130 10k -20 1: 2: 3: 4: 5: 6: 7: -30 -40 -90 1k 7 6 Figure 12. Phase Noise, fOUT = 1.768 GHz, Loop Bandwidth = 8 kHz -20 -70 -80 5 FREQUENCY (Hz) Figure 9. Phase Noise, fOUT = 2.7 GHz, Loop Bandwidth = 8 kHz -90 4 NOISE: ANALYSIS RANGE X: START 10.006kHz STOP 19.988MHz INTG NOISE: -55.5777dBc/19.69MHz RMS NOISE: 2.35304mRAD 134.819mdeg RMS JITTER: 211.82fsec RESIDUAL FM: 1.03174kHz -140 -150 -160 -170 FREQUENCY (Hz) -70 -80 3 -120 -130 6 100k 2 1 -100 -110 7 100Hz, -77.9943dBc/Hz 1kHz, -72.9378dBc/Hz 10kHz, -90.9651dBc/Hz 100kHz, -119.4690dBc/Hz 1MHz, -141.9879dBc/Hz 10MHz, -155.3944dBc/Hz 100MHz, -161.6441dBc/Hz 1k 10k 10k 100k 4 6 5 1M 10M 100M FREQUENCY (Hz) Figure 11. Phase Noise, fOUT = 2.05 GHz, Loop Bandwidth = 8 kHz Figure 14. Phase Noise, fIN = 860 MHz, fOUT = 2.58 GHz, Loop Bandwidth = 80 kHz, ICP = 2.4 mA, High Performance Mode Rev. 0 | Page 16 of 41 14044-100 -70 -80 1: 2: 3: 4: 5: 6: 7: -30 -40 14044-010 PHASE NOISE (dBc) -50 -60 100Hz, -73.4750dBc/Hz 1kHz, -66.6660dBc/Hz 10kHz, -86.8162dBc/Hz 100kHz, -115.4368dBc/Hz 1MHz, -138.1587dBc/Hz 10MHz, -151.7467dBc/Hz 100MHz, -149.6761dBc/Hz PHASE NOISE (dBc) 1: 2: 3: 4: 5: 6: 7: -30 -40 14044-013 -20 Data Sheet AD9530 TERMINOLOGY Phase Jitter An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time, and this phenomenon is called phase jitter. Although many factors can contribute to phase jitter, one major factor is random noise, which is characterized statistically as being Gaussian (normal) in distribution. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Absolute Phase Noise It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval; it is related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Absolute phase noise is the actual measured noise from the AD9530, and includes the input reference and power supply noise. Additive Phase Noise Additive phase noise is the amount of phase noise that can be attributed to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted, making it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that can be attributed to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is not a part of this jitter number. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. 0 | Page 17 of 41 AD9530 Data Sheet THEORY OF OPERATION DETAILED FUNCTIONAL BLOCK DIAGRAM REF_SEL LF_1 LF_2 LF_3 BP_CAP_1 BP_CAP_2 5.11GHz TO 5.4GHz REFA REFA R DIVIDER (1 TO 255) REFB REFB SDO SCLK CS LOCK DETECTOR OUT1 D2 DIVIDER (1 TO 255) OUT2 D3 DIVIDER (1 TO 255) OUT3 M1 DIVIDER /2, /2.5, /3, /3.5 CHARGE PUMP M2 DIVIDER /2, /2.5, /3, /3.5 VREF CONTROL INTERFACE (SPI) D1 DIVIDER (1 TO 255) N DIVIDER (1 TO 255) M3 DIVIDER /2, /2.5, /3, /3.5 D4 DIVIDER (1 TO 255) OUT1 OUT2 OUT3 OUT4 OUT4 AD9530 14044-022 SDIO PFD BP_CAP_3 LD Figure 15. Detailed Functional Block Diagram OVERVIEW Phase Frequency Detector (PFD) The AD9530 is a fully integrated, integer-N PLL with an ultralow noise, internal 5.11 GHz to 5.4 GHz RTWO capable of generating <232 fs rms, (12 kHz to 20 MHz) jitter clocking signals with a nonideal reference. The AD9530 is tailored for 40 Gbps and 100 Gbps OTN applications with stringent converter and ASIC clocking specifications. The PFD takes inputs from the R divider output and the feedback divider path to produce an output proportional to the phase and frequency difference between them. The PFD includes an adjustable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. The AD9530 includes an on-chip PLL, an internal RTWO, and four output channels with integrated dividers and CML drivers. The PLL contains a partially internal active loop filter, which requires a small number of external components to obtain loop bandwidths lower than 15 kHz for reference phase noise attenuation. The four outputs of the AD9530 feature individual dividers to generate four separate frequencies up to 2.7 GHz. CONFIGURATION OF THE PLL Configuration of the PLL is accomplished by programming the various settings for the R divider, N divider, M3 divider, charge pump current, and a calibration of the RTWO. The combination of these settings and the loop filter determine the PLL loop bandwidth and stability. Successful PLL operation and satisfactory PLL loop performance are highly dependent on proper configuration of the internal PLL settings and loop filter. ADIsimCLKTM is a free program that helps the design and exploration of the capabilities and features of the AD9530, including the design of the PLL loop filter. The maximum allowable input frequency into the PFD is specified in the PFD parameter in Table 5. Charge Pump (CP) The CP is controlled by the PFD. The PFD monitors the phase and frequency relationship between its two inputs and causes the CP to pump up or pump down to charge or discharge, respectively, the integrating node, which is part of the loop filter. The integrated and filtered CP current is transformed into a voltage that drives the tuning node of the RTWO to move the RTWO frequency up or down. The CP current is programmable in 52 steps, where each step corresponds to a current increase of 50 A. Calculate the CP current (ICP) by ICP (A) = 50 x (1 + x) where x is the value written to Register 0x025, Bits[5:0]. Rev. 0 | Page 18 of 41 Data Sheet AD9530 PLL Active Loop Filter The AD9530 active loop filter consists of an internal op amp, internal passive components, and external passive components. Proper loop filter configuration is application dependent. An example of a second-order loop filter is shown in Figure 16. OP AMP BIAS ACTIVE LOOP FILTER WITH DUAL PATH CMAIN VREF VTUNE_MAIN RMAIN VTUNE_TEM P CIN RA_ONCHIP LF_2 LF_1 RTWO C1 LF_3 Use the ADIsimCLK design tool to design and simulate loop filters with varying bandwidths. PLL Reference Inputs The AD9530 features two fully differential PLL reference inputs that are routed through a 2:1 mux to a common R divider. The differential reference input receiver has four internal termination/ biasing options to accommodate many input logic types. A functional diagram of the reference input receiver is shown in Figure 17. Table 18 details the four possible reference input termination and common-mode settings achievable by writing to Register 0x012, Bits[3:2] and Register 0x013, Bits[3:2]. The input frequency specifications for the reference inputs are listed in Table 4. OFF-CHIP COMPONENTS 50 CA_OFFCHIP C2 10k 14044-023 R2 GND VTT BIAS Figure 16. External Second-Order Loop Filer Configuration 10k CIN = 5 pF + 12.5 pF x Register 0x027, Bits[5:2] Note that RMAIN and CMAIN in Figure 16 form a pole at approximately 2 MHz. Table 17 shows the typical loop filter component values and CP settings for an 8 kHz loop bandwidth. The maximum allowable capacitance value for the external loop filter design is shown in Table 5. Exceeding this value may cause various functions of the AD9530 to become unstable. 50 14044-024 C1, C2, CA_OFFCHIP, and R2 are external components required for proper loop filter operation. All internal loop filter components (RMAIN, RA_ONCHIP, CMAIN) are fixed with the exception of CIN, which has available settings of 5 pF to 192.5 pF by programming Register 0x027, Bits[5:2]. This capacitance setting alters the bandwidth of the loop filter op amp. CIN is composed of a fixed 5 pF capacitor and a bank of 15 selectable 12.5 pF capacitors. Calculate the CIN value by Figure 17. Reference Input Receiver Functional Diagram Each REFx/REFx receiver can be disabled by setting the associated reference enable bit to 0. RTWO The internal RTWO tunes from 5.11 GHz to 5.4 GHz and is powered by the VDD supply pins (Pin 20 to Pin 23). The RTWO has two modes: high performance mode and low power mode. These modes are set by Register 0x01C, Bit 0. These modes enable optimization between the phase noise performance and power consumption. See the Power Supply Recommendations section for a recommended power supply configuration for Pin 20 to Pin 23. Table 17. Typical Loop Filter Components and ICP Settings for 8 kHz Loop Bandwidth Reference (MHz) 181.5 R Divider /1 Feedback Divider (N x M3) /30 C1 (nF) 10 C2 (F) 0.47 R2 () 255 CA_OFFCHIP (F) 0.1 ICP (mA) 0.3 Table 18. Possible Reference Input Termination Settings Mode Name DC-Coupled LVDS DC-Coupled, Internally Biased AC-Coupled DC-Coupled High-Z REFx/REFx Input Termination Select Settings 00 01 (default) 10 11 Rev. 0 | Page 19 of 41 On-Chip Termination 100 differential 50 to GND 50 to 0.35 V 10 k to GND Common-Mode Bias High-Z GND 0.35 V GND AD9530 Data Sheet RTWO Calibration The RTWO calibration function selects the appropriate RTWO frequency band for a given configuration. A calibration is performed by toggling Register 0x001, Bit 2 from 0 to 1. The command sequence to issue a VCO calibration is as follows: 1. 2. Write the desired AD9530 configuration, including the divider and output driver settings. Set Register 0x001, Bit 2 = 0 (CALIBRATE VCO bit). Note that this is a self clearing bit. and N dividers have individual resets located at Register 0x022, Bit 0, and Register 0x024, Bit 0, respectively. M1 and M2 Dividers (M1 and M2) The M1 and M2 dividers (Register 0x020, Bits[4:3] and Register 0x021, Bits[4:3], respectively) have fixed divide values of 2, 2.5, 3, and 3.5. The M1 and M2 dividers provide frequency division between the RTWO output and the clock distribution channel dividers (Dx). The M1 and M2 dividers have individual resets located at Register 0x020, Bit 0, and Register 0x021, Bit 0, respectively. A calibration is required after initial power-up, after subsequent resets, and after any changes to the input reference frequency or the divide settings that affect the RTWO operating frequency. A 2 sec wait timer is activated at power-up to gate the first calibration. This wait time is not enforced for subsequent calibrations after power-on. See the CML Output Drivers section for more details. The PLL reference must be active and stable and the PLL must be configured to a valid operational state prior to issuing a calibration. After a calibration, all of the internal dividers are synchronized automatically to ensure proper phase alignment of the PLL and distribution. The AD9530 has four 8-bit channel dividers (Dx) which are identical to the R and N dividers. Dx can be set to any value from 1 to 255. Setting the divide value for D1 through D4 is accomplished by writing Register 0x014, Register 0x016, Register 0x018, and Register 0x01A, respectively. The D1 through D4 reset bits that reset D1 through D4 are located in Bit 0 of Register 0x015, Register 0x017, Register 0x019, and Register 0x01B, respectively. A setting of 0 disables the divider. Reference Switchover Dividers Sync The AD9530 supports two separate differential reference inputs. Manual switchover is performed between these inputs by either writing to Register 0x011, Bit 2 and Bit 1, or by using the REF_SEL pin. Register 0x011, Bit 2 sets whether the REF_SEL pin or the reference select register controls the reference input mux. Default operation ignores the REF_SEL pin setting and uses the value of Register 0x011, Bit 1. Use a sync to phase align all of the AD9530 internal dividers to a common point in time. A global sync of all dividers is performed after a VCO calibration. To perform a VCO calibration, write a 1 to Bit 2 of Register 0x001. A VCO calibration must be performed after power up, as well as any time a different VCO frequency is selected. Dividers (R, Mx, N, and Dx) The AD9530 contains multiple dividers that configure the PLL for a given frequency plan. Each divider has an associated reset bit that is self clearing. Resetting a divider is required every time the divide value of that driver is changed. Issuing a reset of a single divider does not clear the current divide value. Reference Divider (R Divider) The reference inputs are routed through a 2:1 mux into a common 8-bit R divider. R can be set to any value from 1 to 255 (Register 0x010, Bits[7:0]). Setting Register 0x010 = 0x0A is equivalent to an R divider setting of 10. The frequency out of the R divider must not exceed the maximum allowable frequency of the PFD listed in Table 5. The R divider has its own reset located in Register 0x011. This reset bit is self clearing. M3 and N Feedback Dividers The total feedback division from the RTWO to the PFD is the product of the M3 and N dividers. The N divider (Register 0x023, Bits[7:0]) functions identically to the R divider described in the Reference Divider (R Divider) section. The M3 divider (Register 0x022, Bits[3:2]) is limited to fixed divide values of 2, 2.5, 3, and 3.5 and acts as a prescaler to the N divider. The M3 Channel Dividers (Dx) To sync all of the dividers after programming them, without the VCO frequency, write a 1 to Bit 1 of Register 0x001. Lock Detector The AD9530 features a frequency lock detect signal that corresponds to whether the PLL reference and feedback edges are within a certain frequency of one another. The exact frequency lock threshold to indicate a PLL lock is user programmable in Register 0x01D, Bits[3:1]. The three register bits allow the frequency lock threshold to span 20 ppb to 300 ppm. If the frequency error between the reference and feedback edges is lower than the specified lock threshold, the LD pin goes high and the PLL_LOCKED bit = 1. The LD pin and the PLL_LOCKED bit go low when the error between the reference and feedback edges is greater than the frequency lock threshold. The lock detector also outputs an 11-bit word located in Register 0x01E, Bits[7:0] and Register 0x01F, Bits[1:0]. Bit 10 through Bit 0 contain a binary value representative of the measured frequency lock error, and Bit 11 indicates whether the 10-bit value is expressed in ppm (parts per million) or ppb (parts per billion). Note that this 11th bit is found in Register 0x01F, Bit 3. Rev. 0 | Page 20 of 41 Data Sheet AD9530 CML Output Drivers The AD9530 has four CML output drivers that are operable up to 2.7 GHz. Each output driver must be externally terminated as shown in the Input/Output Termination Recommendations section. The output voltage swing, internal termination, and power-down of each CML driver are configurable by writing to the appropriate registers. An initial calibration of the internal termination and voltage swing is performed after a POR event. This calibration requires that OUT1 is terminated, regardless of whether the driver is needed in a specific design. A functional diagram of the output driver is shown in Figure 18. VDD MN3 18mA TO 24mA MN0 The 2 sec wait timer ensures that all internal supplies are stable before allowing the user to issue a VCO calibration. This timer only starts after a POR. The user may program all the necessary registers during this time, including the VCO calibration bit. After the timer times out and a reference input is applied, the calibration issues, allowing the PLL to lock and the outputs to toggle. The maximum internal wait time is shown in Table 5. Hardware Reset via the RESET Pin Soft Reset via the Serial Port 50 MN1 14044-025 MN2 2 sec Wait Timer Driving the RESET pin to a Logic 0 and then back to a Logic 1 restores the chip to the on-chip default register settings. VDD 50 the 2 sec counter finishes, the user can issue a VCO calibration and outputs begin toggling ~500 ns later. 18mA TO 24mA The serial port control register allows a soft reset by setting Register 0x000, Bit 7 and Bit 1. When these bits are set, the chip restores to the on-chip default settings, except for Register 0x000 and Register 0x001. Register 0x000 and Register 0x001 retain the values prior to reset, except for the self clearing bits. However, the self clearing operation does not complete until an additional serial port SCLK cycle occurs; the AD9530 is held in reset until this additional SCLK cycle. Individual Divider Reset via the Serial Port Figure 18. CML Output Simplified Equivalent Circuit The CML differential voltage (VOD) is selectable from 0.8 V to 1.1 V via Bits[5:4] of Register 0x015, Register 0x017, Register 0x019, and Register 0x01B. The AD9530 has optional internal termination for cases where transmission line impedance mismatch between the CML output and the receiver causes increased reflections at high output frequencies. These terminations improve impedance match traces at high frequency at the expense of drawing twice as much current as the default operating condition. For Register 0x015 (for OUT1), Register 0x017 (for OUT2), Register 0x019 (for OUT3), and Register 0x01B (for OUT4), setting the OUTx_TERM_EN (Bit 3) = 1 enables the on-chip termination and is configurable for each driver. Each CML output can be enabled as needed by altering the appropriate OUTx_ENABLE bit. RESET MODES The AD9530 has a POR and several other ways to apply a reset condition to the chip. Power-On Reset (POR) During chip power-up, a POR pulse is issued when VDD reaches ~2 V and restores the chip to the default on-chip setting. At this point, a 2 sec counter is started to allow all the user device settings to load and the RTWO to stabilize. After Every divider in the AD9530 has the ability to reset individually by using the appropriate reset bit. This reset does not clear the value written in the specific divider register but restarts the divider count to 0, which results in a phase adjustment. See the associated divider section or the register map for the location of these bits. POWER-DOWN MODES Sleep Mode via the Serial Port Place the AD9530 in sleep mode by writing Register 0x002, Bits[1:0] = 11. This mode powers down the following blocks: * * * * * * * All OUTx drivers All REFx inputs All Mx dividers RTWO power set to minimum CP current set to minimum PFD Loop filter op amp Individual Clock Input and Output Power-Down Power down any of the reference inputs or clock distribution outputs by individually writing to the appropriate registers. The register map details the individual power-down settings for each input and output. Rev. 0 | Page 21 of 41 AD9530 Data Sheet INPUT/OUTPUT TERMINATION RECOMMENDATIONS Figure 19 through Figure 24 illustrate the recommended input and output connections for connecting the AD9530 to other devices. VDD = 2.5V VDD = 2.5V 50 VDD 0.1F 50 AD9530 CML 0.1F 14044-016 AD9530 100 DIFFERENTIAL 100 (COUPLED) TRANSMISSION LINE 0.1F 14044-019 HSTL 100 DIFFERENTIAL (COUPLED) TRANSMISSION LINE VDD = 2.5V 0.1F VDD = 3.3V VDD = 2.5V 50 100 DIFFERENTIAL 100 (COUPLED) TRANSMISSION LINE 200 200 Figure 23. REFx Input Termination Recommendation for 3.3V LVPECL Drivers VDD VDD = 2.5V VDD VDD 50 AD9530 14044-018 LVDS 100 DIFFERENTIAL 100 (COUPLED) TRANSMISSION LINE AD9530 CML Figure 20. CML DC-Coupled Output Driver (External Termination Required When Using the Internal Termination Option) VDD 0.1F CML Figure 21. REFx Input Termination Recommendation for LVDS Drivers 100 DIFFERENTIAL (COUPLED) TRANSMISSION LINE 50 AD9530 14044-021 AD9530 100 DIFFERENTIAL (COUPLED) TRANSMISSION LINE LVPECL VDD = 2.5V 0.1F VS = VDD 50 14044-017 VDD = 2.5V Figure 22. REFx Input Termination Recommendation for High Speed Transceiver Logic (HSTL) Drivers 14044-020 Figure 19. CML AC-Coupled Output Driver (External Termination Required When Using the Internal Termination Option) Figure 24. REFx Input Termination Recommendation for 2.5V CML Drivers Rev. 0 | Page 22 of 41 Data Sheet AD9530 SERIAL CONTROL PORT The AD9530 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The serial control port allows read/write access to the AD9530 register map. The AD9530 uses the Analog Devices, Inc., unified SPI protocol. The unified SPI protocol guarantees that all new Analog Devices products using the unified protocol have consistent serial port characteristics. The SPI port configuration is programmable via Register 0x0000. This register is a part of the SPI control logic rather than in the register map. The following product specific items are defined in the unified SPI protocol: * * * * Analog Devices unified SPI protocol Revision: 1.0. Chip type: 0x05 (0x05 indicates a clock chip). Product ID: 10011b (in this case) uniquely identifies the device as AD9530. No other Analog Devices clock IC supporting unified SPI has this identifier. Physical layer: 3-wire and 4-wire supported and 2.5 V operation supported. Optional single-byte instruction mode: not supported. Data link: not used. Control: not used. SPI SERIAL PORT OPERATION * * * Pin Descriptions Communication Cycle--Instruction Plus Data The SCLK (serial clock) pin serves as the serial shift clock. This pin is an input. SCLK synchronizes serial control port read and write operations. The rising edge SCLK registers write data bits, and the falling edge registers read data bits. The SCLK pin supports a maximum clock rate of 40 MHz. The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. The 3-wire mode uses the SDIO (serial data input/output) pin for transferring data in both directions. The 4-wire mode uses the SDIO pin for transferring data to the AD9530, and the SDO pin for transferring data from the AD9530. The CS (chip select) pin is an active low control that gates read and write operations. Assertion (active low) of the CS pin initiates a write or read operation to theAD9530 SPI port. Any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented based on the setting of the address ascension bit (Register 0x0000). CS must be deasserted at the end of the last byte transferred, thereby ending the stream mode. This pin is internally connected to a 10 k pullup resistor. When CS is high, the SDIO and SDO pins go into a high impedance state. Implementation Specific Details A detailed description of the unified SPI protocol can be found at www.analog.com/ADISPI, which covers items such as timing, command format, and addressing. The unified SPI protocol consists of a two part communication cycle. The first part is a 16-bit instruction word that is coincident with the first 16 SCLK rising edges and a payload. The instruction word provides the AD9530 serial control port with information regarding the payload. The instruction word includes the R/W bit that indicates the direction of the payload transfer (that is, a read or write operation). The instruction word also indicates the starting register address of the first payload byte. Write If the instruction word indicates a write operation, the payload is written into the serial control port buffer of the AD9530. Data bits are registered on the rising edge of SCLK. Generally, it does not matter what data is written to blank registers; however, it is customary to use 0s. Note that there may be reserved registers with default values not equal to 0x00; however, every effort was made to avoid this. Most of the serial port registers are buffered (see the Buffered/ Active Registers section for details on the difference between buffered and active registers). Therefore, data written into buffered registers does not take effect immediately. An additional operation is needed to transfer buffered serial control port contents to the registers that actually control the device. This transfer is accomplished with an IO_UPDATE operation, which is performed in one of two ways. One method is to write a Logic 1 to Register 0x00F, Bit 0 (this bit is an autoclearing bit). The user can change as many register bits as desired before executing an IO_UPDATE command. The IO_UPDATE operation transfers the buffer register contents to their active register counterparts. Rev. 0 | Page 23 of 41 AD9530 Data Sheet Read SPI MSB/LSB First Transfers If the instruction word indicates a read operation, the next N x 8 SCLK cycles clock out the data starting from the address specified in the instruction word. N is the number of data bytes read. The readback data is driven to the pin on the falling edge and must be latched on the rising edge of SCLK. Blank registers are not skipped over during readback. The AD9530 instruction word and payload can be MSB first or LSB first. The default for the AD9530 is MSB first. The LSB first mode can be set by writing a 1 to Register 0x000, Bit 6 and Bit 1. Immediately after the LSB first bit is set, subsequent serial control port operations are LSB first. A readback operation takes data from either the serial control port buffer registers or the active registers, as determined by Register 0x001, Bit 5. If the address ascension bit (Register 0x000, Bit 5 and Bit 2) = 0, the serial control port register address decrements from the specified starting address toward Address 0x0000. SPI Instruction Word (16 Bits) If the address ascension bit (Register 0x0000, Bit 5 and Bit 2) = 1, the serial control port register address increments from the starting address toward Address 0x0FF. Reserved addresses are not skipped during multibyte input/output operations; therefore, write the default value to a reserved register and 0s to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers. Address Ascension The MSB of the 16-bit instruction word is R/W, which indicates whether the instruction is a read or a write. The next 15 bits are the register address (A14 to A0), which indicates the starting register address of the read/write operation (see Table 20). Note that, because there are no registers that require more than 13 address bits, A14 and A13 are ignored and treated as zeros. Table 19. Streaming Mode (No Addresses Skipped) Address Ascension Increment Decrement Stop Sequence 0x0000 ... 0x1FFF 0x1FFF ... 0x0000 Table 20. Serial Control Port, 16-Bit Instruction Word MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 16-BIT INSTRUCTION HEADER D4 D3 D2 D1 D0 D7 REGISTER (N) DATA D6 D5 D4 D3 D2 D1 D0 DON'T CARE REGISTER (N - 1) DATA 14044-026 SDIO DON'T CARE DON'T CARE Figure 25. Serial Control Port Write--MSB First, Address Decrement, Two Bytes of Data CS SCLK DON'T CARE DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N - 1) DATA REGISTER (N - 2) DATA REGISTER (N - 3) DATA DON'T CARE Figure 26. Serial Control Port Read--MSB First, Address Decrement, Four Bytes of Data tDS tS CS DON'T CARE SDIO DON'T CARE tC tCLK tLOW DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 Figure 27. Timing Diagram for Serial Control Port Write--MSB First Rev. 0 | Page 24 of 41 D2 D1 D0 DON'T CARE 14044-028 SCLK tHIGH tDH 14044-027 SDIO Data Sheet AD9530 CS SCLK DATA BIT N 14044-029 tDV SDIO SDO DATA BIT N - 1 Figure 28. Timing Diagram for Serial Control Port Register Read--MSB First CS SCLK DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 D1 D2 D3 D4 16-BIT INSTRUCTION HEADER D5 D6 REGISTER (N) DATA D7 D0 D1 D2 D3 D4 D5 D6 REGISTER (N + 1) DATA Figure 29. Serial Control Port Write--LSB First, Address Increment, Two Bytes of Data CS tS tC tCLK tHIGH tLOW tDS SCLK SDIO BIT N BIT N + 1 14044-031 tDH Figure 30. Serial Control Port Timing--Write Table 21. Serial Control Port Timing Parameter tDS tDH tCLK tS tC tHIGH tLOW tDV Description Setup time between data and the rising edge of SCLK (see Figure 27 and Figure 30) Hold time between data and the rising edge of SCLK (see Figure 27 and Figure 30) Period of the clock (see Figure 27 and Figure 30) Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle) (see Figure 27 and Figure 30) Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle) (see Figure 27 and Figure 30) Minimum period that SCLK is in a logic high state (see Figure 27 and Figure 30) Minimum period that SCLK is in a logic low state (see Figure 27 and Figure 30) SCLK to valid SDIO (see Figure 28) Rev. 0 | Page 25 of 41 D7 DON'T CARE 14044-030 SDIO DON'T CARE DON'T CARE AD9530 Data Sheet POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9530 is a multifunctional, high speed device that targets a wide variety of clock applications. The numerous innovative features contained in the device each consume incremental power. If all outputs are enabled in the maximum frequency and mode that have the highest power, the safe thermal operating conditions of the device may be exceeded. Careful analysis and consideration of power dissipation and thermal management are critical elements in the successful application of the AD9530. The AD9530 is specified to operate within the industrial temperature range of -40C to +85C. This specification is conditional, such that the absolute maximum junction temperature is not exceeded (as specified in Table 14). At high operating temperatures, extreme care must be taken when operating the device to avoid exceeding the junction temperature and potentially damaging the device. Clock speed directly and linearly influences the total power dissipation of the device and, therefore, the junction temperature. Table 3 lists the currents required by the driver for a single output frequency. If using the current vs. frequency graphs provided in the Typical Performance Characteristics section, subtract the power into the load using the following equation: PLOAD = (Differential Output Voltage Swing2/50 ) EVALUATION OF OPERATING CONDITIONS Many variables contribute to the operating junction temperature within the device, including * * * * CLOCK SPEED AND DRIVER MODE Selected driver mode of operation Output clock speed Supply voltage Ambient temperature The first step in evaluating the operating conditions is to determine the AD9530 maximum power consumption for the user configuration by referring to the values in Table 2. The maximum PD excludes power dissipated in the load resistors of the drivers because such power is external to the device. Use the current dissipation specifications listed in Table 2, as well as the power dissipation numbers in Table 3 to calculate the total power dissipated for the desired configuration. The second step in evaluating the operating conditions is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient. For this example, a thermal impedance of JA = 21.1C/W is used. The combination of these variables determines the junction temperature within the AD9530 for a given set of operating conditions. Example 1 Example 1 is as follows: The AD9530 is specified for an ambient temperature (TA). To ensure that TA is not exceeded, use an airflow source. (1358 mW x 21.1C/W) = 29C With an ambient temperature of 85C, the junction temperature is TJ = 85C + 29C = 114C Use the following equation to determine the junction temperature on the application PCB: This junction temperature is below the maximum allowable temperature. TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured at the top center of the package. JT is the value from Table 14. PD is the power dissipation of the AD9530. Example 2 Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approximation of TJ by the equation This junction temperature is greater than the maximum allowable temperature. The ambient temperature must be lowered by 4C to operate in the condition of Example 2. TJ = TA + (JA x PD) (1630 mW x 21.1C/W) = 34C With an ambient temperature of 85C, the junction temperature is TJ = 85C + 34C = 119C THERMALLY ENHANCED PACKAGE MOUNTING GUIDELINES where TA is the ambient temperature (C). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations. Example 2 is as follows: See the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), for more information about mounting devices with an exposed pad. Rev. 0 | Page 26 of 41 Data Sheet AD9530 APPLICATIONS INFORMATION (RECOMMENDED) OR ADP1741 SNR (dB) BUCK REGULATOR 3.4V 2.5V: VDD RTWO (PINS 20 TO 23) LDO ADM7154 LDO ADP151 LDO 16 90 80 ADP7158 2.5V: VDD DIGITAL (PIN 12) 40 14 200 fs tJ = 400 fs tJ = 1ps tJ = 2ps 12 10 tJ = 10p 8 s 6 30 10 100 1k fA (MHz) USING THE AD9530 OUTPUTS FOR ADC CLOCK APPLICATIONS Figure 32. SNR and ENOB vs. Analog Input Frequency (fA) Any high speed ADC is extremely sensitive to the quality of the sampling clock of the AD9530. An ADC can be thought of as a sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at 14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution, where the step size and quantization error can be ignored, the available SNR can be expressed approximately by tJ = 100 fs tJ = 50 Figure 31. Power Supply Recommendation 1 SNR(dB) 20 log 2f t AJ 70 60 2.5V: VDD OUT AND VDD REF (PIN 3, PIN 7, PIN 31, PIN 35, PIN 41, PIN 45) 18 1 SNR = 20log 2f t A J 100 14044-032 6V INPUT ADP2386 110 ENOB The AD9530 only requires 2.5 V for operation, but proper isolation between power domains is beneficial for performance. Figure 31 shows the recommended Analog Devices power solutions for the best possible performance of the AD9530. These devices are also featured on the evaluation board. Figure 32 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). 14044-033 POWER SUPPLY RECOMMENDATIONS For more information, see the AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter, and the AN-501 Application Note, Aperture Uncertainty and ADC System Performance. Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sampling clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. The differential CML outputs of the AD9530 enable clock solutions that maximize converter SNR performance. Consider the input requirements of the ADC (differential or singleended, logic level termination) when selecting the best clocking/ converter solution. where: fA is the highest analog frequency being digitized. tJ is the rms jitter on the sampling clock. Rev. 0 | Page 27 of 41 AD9530 Data Sheet TYPICAL APPLICATION BLOCK DIAGRAM AD9554 AD9530 (QUAD CHANNEL DPLL) SERDES 10 x 10Gbps 10 x 10Gbps FRAMER/ PHY NPU TRAFFIC MANAGEMENT HIGH SPEED Tx DAC FRAMER/ FEC 25Gbps TO 28Gbps 25Gbps TO 28Gbps 25Gbps TO 28Gbps 25Gbps TO 28Gbps AD9554 SERDES 10 x 10Gbps NPU TRAFFIC MANAGEMENT FRAMER/ FEC HIGH SPEED Tx DAC 25Gbps TO 25Gbps TO 25Gbps TO 25Gbps TO 28Gbps 28Gbps OPTICAL 28Gbps FRONT END 28Gbps FPGA/ASIC 3 x AD9554-1 (QUAD CHANNEL DPLL) FROM NETWORK OPTICAL MODULE TRx MODULES 14044-015 BACKPLANE AD9530 DEMAPPING CONTROL 10 x 10Gbps FRAMER/ PHY TO NETWORK OPTICAL MODULE FPGA/ASIC (QUAD CHANNEL DPLL) OPTICAL FRONT END 10Gbps SERDES Figure 33. Typical Application Block Diagram, 100 Gbps Muxponder with the AD9530 Rev. 0 | Page 28 of 41 Data Sheet AD9530 CONTROL REGISTERS When writing to registers with bits that are marked reserved, take care to always write the default value for the reserved bits. CONTROL REGISTER MAP OVERVIEW Register addresses that are not listed in Table 22 are not used and writing to those registers has no effect. Registers that are marked as reserved must never have their values changed. Unused and reserved registers are in the control register map but are not in the control register description tables. Table 22. Control Register Map Reg. Addr. (Hex) Register Name Bit 7 0x000 SPI_CONFIGA SOFT_RESET 0x001 SPI_CONFIGB 0x002 STATUS 0x003 0x004 0x005 0x006 0x007 0x008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 0x018 0x019 0x01A 0x01B 0x01C CHIP_TYPE PRODUCT_ ID[11:0] PART_VERSION RESERVED RESERVED RESERVED USER_ SCRATCHPAD1 SPI_VERSION VENDOR_ID VENDOR_ID RESERVED IO_UPDATE R_DIVIDER R_DIVIDER_ CTRL REF_A REF_B OUT1_DIVIDER OUT1_DRIVER_ CONTROL OUT2_DIVIDER OUT2_DRIVER_ CONTROL OUT3_DIVIDER OUT3_DRIVER_ CONTROL OUT4_DIVIDER OUT4_DRIVER_ CONTROL VCO_POWER Bit 6 Bit 5 Bit 4 LSB_FIRST ADDRESS_ASCEND RESERVED READ_BUFFER SINGLE_ INSTRUCTION PLL_LOCKED SIGNAL_ FEEDBACK_OK PRESENT RESERVED PRODUCT_ID, Bits[3:0] RESERVED Bit 1 LSB_FIRST (LSB) Bit 0 SOFT_RESET DIVIDER_RESET RESERVED 0x00 RESERVED REFERENCE_ OK SLEEP CHIP_TYPE, Bits[3:0] RESERVED SPI_VERSION, Bits[7:0] VENDOR_ID, Bits[7:0] VENDOR_ID, Bits[15:8] RESERVED RESERVED R_DIVIDER, Bits[7:0] RESERVED RESERVED RESERVED RESERVED REFIN_OVERRIDE_ PIN_SEL RESERVED REFA_TERM_SEL RESERVED REFB_TERM_SEL OUT1_DIVIDER, Bits[7:0] OUT1_AMP_TRIM OUT1_TERM_ OUT1_LDO_EN EN OUT2_DIVIDER, Bits[7:0] OUT2_AMP_TRIM OUT2_TERM_ OUT2_LDO_EN EN OUT3_DIVIDER, Bits[7:0] OUT3_AMP_TRIM OUT3_TERM_ OUT3_LDO_EN EN OUT4_DIVIDER, Bits[7:0] OUT4_AMP_TRIM OUT4_TERM_ OUT4_LDO_EN EN RESERVED 0x021 M2_DIVIDER RESERVED RESERVED RESERVED Varies 0x05 0x3F 0x01 0x14 0x00 0x00 0x00 0x00 IO_UPDATE RESERVED RESERVED 0x023 N_DIVIDER Bit 2 ADDRESS_ ASCEND CALIBRATE VCO PRODUCT_ID, Bits[11:4] PART VERSION RESERVED RESERVED RESERVED USER_SCRATCHPAD1, Bits[7:0] 0x01D PLL_LOCKDET_ CONTROL 0x01E PLL_LOCKDET_ READBACK1 0x01F PLL_LOCKDET_ READBACK2 0x020 M1_DIVIDER 0x022 M3_DIVIDER Bit 3 SDO_ACTIVE Default Value (Hex) 0x00 REFIN_INPUT_ SEL REFA_LDO_EN REFB_LDO_EN REFIN_DIV_ RESET REFA_EN REFB_EN OUT1_EN OUT1_ DIVIDER_RESET 0x00 0x56 0x04 0x00 0x00 0x01 0x06 0x07 0x06 0x01 0x24 0x01 0x24 OUT2_ DIVIDER_RESET 0x01 OUT3_EN 0x24 OUT3_ DIVIDER_RESET 0x01 OUT4_EN 0x24 OUT4_ DIVIDER_RESET 0x01 VCO_LDO_WAIT_ VCO_POWER OVERRIDE PLL_LOCK_DET_ERR_THRESHOLD, Bits[2:0] 0x0C PLL_LOCK_ PLL_LOCK_ DET_START DET_RESET PLL_LOCK_DET_ERROR, Bits[7:0] Varies PLL_LOCK_ PLL_LOCK_ DET_DONE DET_RANGE M1_DIVIDER M2_DIVIDER RESERVED PLL_LOCKED Rev. 0 | Page 29 of 41 PLL_LOCK_DET_ERROR, Bits[9:8] Varies M1_LDO_EN M1_EN M2_LDO_EN M2_EN M3_DIVIDER N_DIVIDER OUT2_EN M3_EN M1_DIVIDER_ RESET M2_DIVIDER_ RESET M3_DIVIDER_ RESET 0x16 0x16 0x02 0x0A AD9530 Reg. Addr. (Hex) Register Name Bit 7 0x024 N_DIVIDER_ CTRL 0x025 CHARGE_PUMP 0x026 PHASE_ FREQUENCY_ DETECTOR 0x027 LOOP_FILTER 0x028 0x0FC 0x0FD 0x0FE VCO_READBACK RESERVED RESERVED USER_ SCRATCHPAD2 0x0FF USER_ SCRATCHPAD3 Data Sheet Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 N_DIVIDER_ RESET PFD_EN_ ANTIBACKLASH PFD_ENABLE RESERVED RESERVED CP_CURRENT RESERVED RESERVED LOOP_FILTER_CAP RESERVED LOOP_FILTER_ BIAS_EN VCO_FREQ_AUTOCAL LOOP_FILTER_ AMP_EN Default Value (Hex) 0x00 0x07 0x01 0x13 RESERVED RESERVED USER_SCRATCHPAD2, Bits[7:0] 0x00 0x00 0x00 0x00 USER_SCRATCHPAD3, Bits[7:0] 0x00 Rev. 0 | Page 30 of 41 Data Sheet AD9530 CONTROL REGISTER MAP DESCRIPTIONS Table 23 through Table 61 provide detailed descriptions for each of the control register functions. The registers are listed by hexadecimal address. Bit fields noted as live indicate that the register write takes effect immediately. Bit fields that are not noted as live only take effect after an IO_UPDATE is issued by writing 0x01 to Register 0x00F. SPI CONFIGURATION (REGISTER 0x000 AND REGISTER 0x001) Table 23. Bit Descriptions for SPI_CONFIGA (Default: 0x00) Bits 7 Bit Name SOFT_RESET 6 LSB_FIRST Settings Description Master SPI reset. Setting this self clearing bit to 1 resets the AD9530. This bit is live. Selects SPI LSB first mode. This bit is live. MSB first SPI access. LSB first SPI access. Selects SPI address ascend mode. This bit is live. SPI streaming mode addresses decrement (default). SPI streaming mode addresses increment. Selects SPI 4-pin mode, which enables the SDO pin. This bit is live. SPI 3-pin mode. The SDIO pin is bidirectional (default). SPI 4-pin mode. The SDI and SDO pins are unidirectional. Selects SPI address ascend mode. This bit is live. SPI streaming mode addresses decrement (default). SPI streaming mode addresses increment. Selects SPI LSB first mode. This bit is live. MSB first SPI access (default). LSB first SPI access. Master SPI reset. Setting this self clearing bit to 1 resets the AD9530. This bit is live. 0 1 5 ADDRESS_ASCEND 0 1 [4:3] SDO_ACTIVE 0 1 2 ADDRESS_ASCEND 0 1 1 LSB_FIRST 0 1 0 SOFT_RESET Reset 0b Access W 0b RW 0b RW 0b RW 0b RW 0b RW 0b W Reset 0b Access RW 0b 0b W RW 00b 0b W W 0b W 0 W Table 24. Bit Descriptions for SPI_CONFIGB (Default: 0x00) Bits 7 6 5 Bit Name SINGLE_INSTRUCTION RESERVED READ_BUFFER Settings 0 1 0 0 1 [4:3] 2 RESERVED CALIBRATE VCO 1 DIVIDER_RESET 0 RESERVED 00 0 Description Single instruction mode. This bit is live. SPI streaming mode (default). SPI single instruction mode. When writing to Register 0x001, this bit must be 0b. For buffered registers, this bit controls whether the value read from the serial port is from the actual (active) registers or the buffered copy. Reads values currently applied to the internal logic of the device (default). Reads buffered values that take effect on the next assertion of IO_UPDATE. When writing to Register 0x001, these bits must be 00b. VCO calibration. Setting this self clearing bit performs a VCO calibration, which must be performed at startup as well as any time the VCO frequency is changed. A VCO calibration also automatically performs a divider reset (Bit 1 in this register). This bit is live. Divider reset. Writing a 1 to this self clearing register stalls the outputs, reset all dividers, and reenable the outputs. A divider reset must be performed any time the divider values are changed. Note that if the divider value change results in a different VCO frequency, the CALIBRATE VCO bit (Bit 2 in this register) must be used instead. This bit is live. When writing to Register 0x001, this bit must be 0b. Rev. 0 | Page 31 of 41 AD9530 Data Sheet STATUS (REGISTER 0x002) Table 25. Bit Descriptions for STATUS (Default: Varies1) Bits 7 Bit Name PLL_LOCKED Settings 0 1 6 SIGNAL_PRESENT 0 1 5 FEEDBACK_OK 0 1 4 REFERENCE_OK 0 [3:2] [1:0] 1 00 RESERVED SLEEP 00 01 10 11 1 Description PLL lock detect status readback PLL unlocked PLL locked Reference signal present Reference input signal not detected Reference input signal detected Feedback signal valid from N divider Feedback signal from N divider not detected Feedback signal from N divider detected Logical AND of reference input signal and feedback signal Either the reference input clock is not detected or the feedback signal is not detected, or neither are detected Reference input signal and feedback signal both detected When writing to Register 0x002, these bits must be 00b Sleep mode Normal operation (default) Undefined Undefined Sleep mode Reset Varies Access R Varies R Varies R Varies R 00b 00b W RW Reset 0x0 0x5 Access R R Reset 0x3 Access R 0xF R Reset 0x01 Access R The default value reads 0xF0 under normal operation if the PLL is locked. CHIP TYPE (REGISTER 0x003) Table 26. Bit Descriptions for CHIP_TYPE (Default: 0x05) Bits [7:4] [3:0] Bit Name RESERVED CHIP_TYPE, Bits[3:0] Settings Description Reserved. The Analog Devices unified SPI protocol reserves this read only register location for identifying the type of device. The default value of 0x05 identifies the AD9530 as a clock IC. PRODUCT ID (REGISTER 0x004 AND REGISTER 0x005) Table 27. Bit Descriptions for PRODUCT_ID[3:0] (Default: 0x3F) Bits [7:4] Bit Name PRODUCT_ID, Bits[3:0] [3:0] RESERVED Settings Description The Analog Devices unified SPI protocol reserves this read only register location as the lower four bits of the clock part serial ID that (along with Register 0x005) uniquely identifies the AD9530 within the Analog Devices clock chip family. No other Analog Devices chip that adheres to the Analog Devices unified SPI has these values for Register 0x003, Register 0x004, and Register 0x005. Reserved. Table 28. Bit Descriptions for PRODUCT_ID[11:4] (Default: 0x01) Bits [7:0] Bit Name PRODUCT_ID, Bits[11:4] Settings Description The Analog Devices unified SPI protocol reserves this read only register location as the upper eight bits of the clock part serial ID that (along with Register 0x004) uniquely identifies the AD9530 within the Analog Devices clock chip family. No other Analog Devices chip that adheres to the Analog Devices unified SPI has these values for Register 0x003, Register 0x004, and Register 0x005. Rev. 0 | Page 32 of 41 Data Sheet AD9530 PART VERSION (REGISTER 0x006) Table 29. Bit Descriptions for PART_VERSION (Default: 0x14) Bits [7:0] Bit Name PART VERSION Settings Description The Analog Devices unified SPI protocol reserves this read only register location for identifying the die revision. Reset 0x00 Access R USER SCRATCH PAD 1 (REGISTER 0x00A) Table 30. Bit Descriptions for USER_SCRATCHPAD1 (Default: 0x00) Bits [7:0] Bit Name USER_SCRATCHPAD1, Bits[7:0] Settings 0x00 to 0xFF Description This register has no effect on device operation. It is available for serial port debugging or register setting revision control. There are two additional user scratch pad registers at Address 0x0FE and Address 0x0FF. Reset 0x00 Access RW SPI VERSION (REGISTER 0x00B) Table 31. Bit Descriptions for SPI_VERSION (Default: 0x00) Bits [7:0] Bit Name SPI_VERSION, Bits[7:0] Settings Description The Analog Devices unified SPI protocol reserves this read only register location for identifying the version of the unified SPI protocol. Reset 0x00 Access R Reset 0x56 Access R Reset 0x04 Access R Reset 0x00 0b Access W W Reset 0x01 Access RW VENDOR ID (REGISTER 0x00C AND REGISTER 0x00D) Table 32. Bit Descriptions for VENDOR ID (Default: 0x56) Bits [7:0] Bit Name VENDOR_ID, Bits[7:0] Settings Description The Analog Devices unified SPI protocol reserves this read only register location for identifying Analog Devices as the chip vendor of this device. All Analog Devices parts adhering to the unified serial port specification have the same value in this register. Table 33. Bit Descriptions for VENDOR_ID (Default: 0x04) Bits [7:0] Bit Name VENDOR_ID, Bits[15:8] Settings Description The Analog Devices unified SPI protocol reserves this read only register location for identifying Analog Devices as the chip vendor of this part. All Analog Devices parts adhering to the unified serial port specification have the same value in this register. IO_UPDATE (REGISTER 0x00F) Table 34. Bit Descriptions for IO_UPDATE (Default: 0x00) Bits [7:1] 0 Bit Name RESERVED IO_UPDATE Settings 0x00 Description When writing to Register 0x00F, these bits must be 0x0. Writing a 1 to this bit transfers the data in the serial input/output buffer registers to the internal control registers of the device. This is a live and autoclearing bit. R DIVIDER--REFERENCE INPUT DIVIDER (REGISTER 0x010) Table 35. Bit Descriptions for R_DIVIDER (Default: 0x01) Bits [7:0] Bit Name R_DIVIDER, Bits[7:0] Settings 0x01 to 0xFF Description PLL reference divider. These bits control the divide ratio of the R divider. Divide ratio goes from /1 (by writing 0x01) to /255 (by writing 0xFF). Rev. 0 | Page 33 of 41 AD9530 Data Sheet R DIVIDER CONTROL (REGISTER 0x011) Table 36. Bit Descriptions for R_DIVIDER_CTRL (Default: 0x06) Bits [7:3] 2 Bit Name RESERVED REFIN_OVERRIDE_PIN_SEL Settings 00000b 0 1 1 REFIN_INPUT_SEL 0 1 0 REFIN_DIV_RESET Description When writing to Register 0x011, these bits must be 00000b. Reference input override pin selection. REFIN_INPUT_SEL bit (in this register) controls reference input selection. REF_SEL pin controls reference input selection. REFA is selected if the REF_SEL pin is high. REFB is selected if the REF_SEL pin is low. Reference input selection. Select REFB input if REFIN_OVERRIDE_PIN_SEL = 0. Select REFA input if REFIN_OVERRIDE_PIN_SEL = 0. Reference input divider reset (autoclearing). Setting this (self clearing) bit resets the R divider. This bit is live, meaning IO_UPDATE is not needed for it to take effect. Default 00000b 1b Access RW RW 1b RW 0b W Default 0x0 01b Access W RW 1b RW 1b RW Default 0x0 01b Access W RW 1b RW 0b RW REFERENCE INPUT A (REGISTER 0x012) Table 37. Bit Descriptions for REF_A (Default: 0x07) Bits [7:4] [3:2] Bit Name RESERVED REFA_TERM_SEL Settings 00 00 01 10 11 1 REFA_LDO_EN 0 1 0 REFA_EN 0 1 Description When writing to Register 0x012, these bits must be 0x0 Reference A input termination select LVDS mode (100 across the inputs) DC-coupled mode (50 to ground) (default) AC-coupled mode (50 to 0.35 V, internal) DC-coupled high-Z mode Reference A enable LDO Disabled Enabled (default) Reference A enable Disabled Enabled (default) REFERENCE INPUT B (REGISTER 0x013) Table 38. Bit Descriptions for REF_B (Default: 0x06) Bits [7:4] [3:2] Bit Name RESERVED REFB_TERM_SEL Settings 00 00 01 10 11 1 REFB_LDO_EN 0 1 0 REFB_EN 0 1 Description When writing to Register 0x013, these bits must be 0x0 Reference B input termination select LVDS mode (100 across the inputs) DC-coupled mode (50 to ground) (default) AC-coupled mode (50 to 0.35 V, internal) DC-coupled high-Z mode Reference B enable LDO Disabled Enabled (default) Reference B enable Disabled (default) Enabled Rev. 0 | Page 34 of 41 Data Sheet AD9530 OUT1 DIVIDER (REGISTER 0x014) Table 39. Bit Descriptions for OUT1_DIVIDER (Default: 0x01) Bits [7:0] Bit Name OUT1_DIVIDER, Bits[7:0] Settings 0x00 to 0xFF Description Output 1 divider. These bits control the divide ratio of the output divider. Divide ratio goes from /1 (by writing 0x01) to /255 (by writing 0xFF). Writing 0x00 disables the divider. Default 0x01 Access RW Default 00b 10b Access W RW 0b RW 1b RW 0b RW 0b W Default 0x01 Access RW Default 00 10b Access W RW 0b RW 1b RW 0b RW OUT1 DRIVER CONTROL REGISTER (REGISTER 0x015) Table 40. Bit Descriptions for OUT1_DRIVER_CONTROL (Default: 0x24) Bits [7:6] [5:4] Bit Name RESERVED OUT1_AMP_TRIM Settings 00 00 01 10 11 3 OUT1_TERM_EN 0 1 2 OUT1_LDO_EN 0 1 1 OUT1_EN 0 1 0 OUT1_DIVIDER_RESET Description When writing to Register 0x015, these bits must be 00b. Output 1 amplitude voltage trim. 0.8 V. 0.9 V. 1.0 V (default). 1.1 V. Output 1 on-chip termination. Disabled (default). Enabled. Output 1 enable LDO. Disabled. Enabled (default). Output 1 enable. Disabled (default). Enabled. Setting this (self clearing) bit resets the Output 1 divider. This bit is live, meaning IO_UPDATE is not needed for it to take effect. OUT2 DIVIDER (REGISTER 0x016) Table 41. Bit Descriptions for OUT2_DIVIDER (Default: 0x01) Bits [7:0] Bit Name OUT2_DIVIDER, Bits[7:0] Settings 0x00 to 0xFF Description Output 2 divider. These bits control the divide ratio of the output divider. Divide ratio goes from /1 (by writing 0x01) to /255 (by writing 0xFF). Writing 0x00 disables the divider. OUT2 DRIVER CONTROL (REGISTER 0x017) Table 42. Bit Descriptions for OUT2_DRIVER_CONTROL (Default: 0x24) Bits [7:6] [5:4] Bit Name RESERVED OUT2_AMP_TRIM Settings 00 00 01 10 11 3 OUT2_TERM_EN 0 1 2 OUT2_LDO_EN 0 1 1 OUT2_EN 0 1 Description When writing to Register 0x017, these bits must be 00b. Output 2 amplitude voltage trim. 0.8 V. 0.9 V. 1.0 V (default). 1.1 V. Output 2 on-chip termination. Disabled (default). Enabled. Output 2 enable LDO. Disabled. Enabled (default). Output 2 enable. Disabled (default). Enabled. Rev. 0 | Page 35 of 41 AD9530 Bits 0 Data Sheet Bit Name OUT2_DIVIDER_RESET Settings Description Setting this (self clearing) bit resets the Output 2 divider. This bit is live, meaning IO_UPDATE is not needed for it to take effect. Default 0b Access W Default 0x01 Access RW Default 00b 10b Access N/A RW 0b RW 1b RW 0b RW 0b W Default 0x01 Access RW Default 00b 10b Access W RW 0b RW OUT3 DIVIDER (REGISTER 0x018) Table 43. Bit Descriptions for OUT3_DIVIDER (Default: 0x01) Bits [7:0] Bit Name OUT3_DIVIDER, Bits[7:0] Settings 0x00 to 0xFF Description Output 3 divider. These bits control the divide ratio of the output divider. Divide ratio goes from /1 (by writing 0x01) to /255 by writing 0xFF. Writing 0x00 disables the divider. OUT3 DRIVER CONTROL (REGISTER 0x019) Table 44. Bit Descriptions for OUT3_DRIVER_CONTROL (Default: 0x24) Bits [7:6] [5:4] Bit Name RESERVED OUT3_AMP_TRIM Settings 00 01 10 11 3 OUT3_TERM_EN 0 1 2 OUT3_LDO_EN 0 1 1 OUT3_EN 0 1 0 OUT3_DIVIDER_RESET Description When writing to Register 0x019, these bits must be 00b. Output 3 amplitude voltage trim. 0.8 V. 0.9 V. 1.0 V (default). 1.1 V. Output 3 on-chip termination. Disabled (default). Enabled. Output 3 enable LDO. Disabled. Enabled (default). Output 3 enable. Disabled (default). Enabled. Setting this (self clearing) bit resets the Output 3 divider. This bit is live, meaning IO_UPDATE is not needed for it to take effect. OUT4 DIVIDER (REGISTER 0x01A) Table 45. Bit Descriptions for OUT4_DIVIDER (Default: 0x01) Bits [7:0] Bit Name OUT4_DIVIDER, Bits[7:0] Settings 0x00 to 0xFF Description Output 4 divider. These bits control the divide ratio of the output divider. Divide ratio goes from /1 (by writing 0x01) to /255 by writing 0xFF. Writing 0x00 disables the divider. OUT4 DRIVER CONTROL (REGISTER 0x01B) Table 46. Bit Descriptions for OUT4_DRIVER_CONTROL (Default: 0x24) Bits [7:6] [5:4] Bit Name RESERVED OUT4_AMP_TRIM Settings 00 00 01 10 11 3 OUT4_TERM_EN 0 1 Description When writing to Register 0x01B, these bits must be 00b. Output 4 amplitude voltage trim. 0.8 V. 0.9 V. 1.0 V (default). 1.1 V. Output 4 on-chip termination. Disabled (default). Enabled. Rev. 0 | Page 36 of 41 Data Sheet Bits 2 Bit Name OUT4_LDO_EN AD9530 Settings 0 1 1 OUT4_EN 0 1 0 OUT4_DIVIDER_RESET Description Output 4 enable LDO. Disabled. Enabled (default). Output 4 enable. Disabled (default). Enabled. Setting this (self clearing) bit resets the Output 4 divider. This bit is live, meaning IO_UPDATE is not needed for it to take effect. Default 1b Access RW 0b RW 0b W VCO POWER (REGISTER 0x01C) Table 47. Bit Descriptions for VCO_POWER (Default: 0x01) Bits [7:2] 1 Bit Name RESERVED VCO_LDO_WAIT_OVERRIDE Settings 000000b Description When writing to Register 0x01C, these bits must be 00b VCO LDO wait state override Wait 2 sec on startup for VCO LDO stability (default) Do not wait for VCO LDO stability VCO power mode Low power mode High power mode (lower jitter) (default) 0 1 0 VCO_POWER 0 1 Default 000000b 0b Access W RW 1b RW Default 000b 0b Access W RW 010b RW 0b RW Default Varies Access R PLL LOCK DETECT CONTROL (REGISTER 0x01D) Table 48. Bit Descriptions for PLL_LOCKDET_CONTROL (Default: 0x0C) Bits [7:5] 4 [3:1] Bit Name RESERVED PLL_LOCK_DET_START Settings 000b 0 1 000b to 111b PLL_LOCK_DET_ERR_ THRESHOLD, Bits[2:0] 000b 001b 010b 011b 100b 101b 110b 111b 0 PLL_LOCK_DET_RESET 0 1 Description When writing to Register 0x01D, these bits must be 000b. PLL lock detect start measurement. This live bit enables the lock detector. PLL lock detector disabled (default). PLL lock detector enabled. PLL lock detect frequency error threshold (ppb is parts per billion and ppm is parts per million).The frequency accuracy of the lock detector is 25% of the lock detect setting. For example, for the 15 ppb setting, the actual accuracy of the lock detector is 11 ppb to 19 ppb. Threshold: 15 ppb. Update interval: 670 ms. Threshold: 60 ppb. Update interval: 170 ms. Threshold: 238 ppb. Update interval: 42 ms (default). Threshold: 954 ppb. Update interval: 10 ms. Threshold: 3.8 ppm. Update interval: 2.6 ms. Threshold: 15 ppm. Update interval: 660 s. Threshold: 61 ppm. Update interval: 160 s. Threshold: 244 ppm. Update interval: 41 s. PLL lock detect disable. PLL lock detector enabled (default). PLL lock detector disabled. PLL LOCK DETECT READBACK (REGISTER 0x01E AND REGISTER 0x01F) Table 49. Bit Descriptions for PLL_LOCKDET_READBACK1 (Read Only; No Default Value) Bits [7:0] Bit Name PLL_LOCK_DET_ERROR, Bits[7:0] Settings Description PLL lock detect error, Bits[7:0]. This read only register, along with Bits[1:0] of Register 0x01F, form a 10-bit number that allows the user to read back the magnitude of the frequency error at the phase frequency detector. Bit 3 in Register 0x01F indicates whether the phase error measurement is in parts per million (ppm) or parts per billion (ppb). Rev. 0 | Page 37 of 41 AD9530 Data Sheet Table 50. Bit Descriptions for PLL_LOCKDET_READBACK2 (Read Only; No Default Value) Bits [7:5] 4 3 Bit Name RESERVED PLL_LOCK_DET_DONE PLL_LOCK_DET_RANGE Settings 000b 0 1 2 PLL_LOCKED 0 1 [1:0] PLL_LOCK_DET_ERROR, Bits[9:8] Description When writing to Register 0x01F, these bits must be 000b. PLL lock detect measurement done. PLL lock detect error range. The read back error is expressed in ppb (parts per billion). The read back error is expressed in ppm (parts per million). PLL lock detect status readback. PLL unlocked. PLL locked. PLL lock detect error, Bits[9:8]. These read only register bits, along with Bits[7:0] Register 0x01E, form a 10-bit number that allows the user to read back the magnitude of the frequency error at the phase frequency detector. Bit 3 in Register 0x01F indicates whether the phase error measurement is in parts per million (ppm) or parts per billion (ppb). Default 000b Varies Varies Access R R R Varies R Varies R Default 000b 10b Access W RW 1b RW 1b RW 0b W Default 000b 10b Access W RW 1b RW 1b RW 0b W M1, M2, M3 DIVIDERS (REGISTER 0x020 AND REGISTER 0x022) Table 51. Bit Descriptions for M1_DIVIDER (Default 0x16) Bits [7:5] [4:3] Bit Name RESERVED M1_DIVIDER Settings 000b 00 01 10 11 2 M1_LDO_EN 0 1 1 M1_EN 0 1 0 M1_DIVIDER_RESET Description When writing to Register 0x020, these bits must be 000b. These bits control the divide ratio for the M1 divider that feeds the D1 and D2 dividers. Divide by 2. Divide by 2.5. Divide by 3 (default). Divide by 3.5. M1 divider enable LDO. Disabled. Enabled (default). M1 divider enable. Disabled. Enabled (default). Setting this (self clearing) bit resets the M1 divider. This bit is live, meaning IO_UPDATE is not needed for it to take effect. Table 52. Bit Descriptions for M2_DIVIDER (Default: 0x16) Bits [7:5] [4:3] Bit Name RESERVED M2_DIVIDER Settings 000b 00 01 10 11 2 M2_LDO_EN 0 1 1 M2_EN 0 1 0 M2_DIVIDER_RESET Description When writing to Register 0x021, these bits must be 000b. These bits control the divide ratio for the M2 divider that feeds the D3 and D4 dividers. Divide by 2. Divide by 2.5. Divide by 3 (default). Divide by 3.5 M2 divider enable LDO. Disabled. Enabled (default). M2 divider enable. Disabled. Enabled. Setting this (self clearing) bit resets the M2 divider. This bit is live, meaning IO_UPDATE is not needed for it to take effect. Rev. 0 | Page 38 of 41 Data Sheet AD9530 M3 DIVIDER (REGISTER 0x022) Table 53. Bit Descriptions for M3_DIVIDER (Default: 0x02) Bits [7:4] [3:2] Bit Name RESERVED M3_DIVIDER Settings 0x0 00 01 10 11 1 M3_EN 0 1 0 M3_DIVIDER_RESET Description When writing to Register 0x01F, these bits must be 0x0. These bits control the divide ratio for the M3 divider. Divide by 2 (default). Divide by 2.5. Divide by 3. Divide by 3.5. M3 divider enable. Disabled. Enabled (default). Setting this (self clearing) bit resets the M3 divider. This bit is live, meaning IO_UPDATE is not needed for it to take effect. Default 0x0 00b Access W RW 1b RW 0b W Default 0x0A Access RW Default 0000000b 0b Access W W Default 00b 0x07 Access W RW Default 000000b 0b Access W RW N DIVIDER (REGISTER 0x023) Table 54. Bit Descriptions for N_DIVIDER (Default: 0x0A) Bits [7:0] Bit Name N_DIVIDER Settings 0x01 to 0xFF Description PLL feedback divider. These bits control the divide ratio of the PLL feedback divider. The divide ratio ranges from /1 (by writing 0x01) to /255 by writing 0xFF. Writing 0x00 disables the divider. N DIVIDER CONTROL (REGISTER 0x024) Table 55. Bit Descriptions for N_DIVIDER_CTRL (Default:0x00) Bits [7:1] 0 Bit Name RESERVED N_DIVIDER_RESET Settings 0000000b Description When writing to Register 0x024, these bits must be 0x00. Setting this (self clearing) bit resets the N divider (also called the feedback divider). This bit is live, meaning IO_UPDATE is not needed for it to take effect. CHARGE PUMP (REGISTER 0x025) Table 56. Bit Descriptions for CHARGE_PUMP (Default: 0x07) Bits [7:6] [5:0] Bit Name RESERVED CP_CURRENT Settings 00b 000000b 000001b ... 000111b ... 110010b 110011 Description When writing to Register 0x025, these bits must be 0x0. Charge pump current. Charge pump current, ICP, is equal to: (1 + CP_CURRENT) x 50 A. The allowable range is 50 A to 2.6 mA. Higher register settings result in ICP = 2.6 mA. 50 A. 100 A. 400 A (default). 2.55 mA. 2.6 mA (maximum). PHASE FREQUENCY DECTECTOR (REGISTER 0x026) Table 57. Bit Descriptions for PHASE_FREQUENCY_DETECTOR (Default: 0x01) Bits [7:2] 1 Bit Name RESERVED PFD_EN_ANTIBACKLASH Settings 000000b 0 1 Description When writing to Register 0x026, these bits must be 0x00. PFD antibacklash enable. Normal antibacklash pulse width (default). Elongated antibacklash pulse width. Rev. 0 | Page 39 of 41 AD9530 Bits 0 Bit Name PFD_ENABLE Data Sheet Settings 0 1 Description PFD enable. This bit enables the phase frequency detector. Disabled. Enabled (default). Default 1b Access RW LOOP FILTER (REGISTER 0x027) Table 58. Bit Descriptions for LOOP_FILTER (Default: 0x13) Bits [7:6] [5:2] Bit Name RESERVED LOOP_FILTER_CAP Settings 00b 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 LOOP_FILTER_BIAS_EN 0 1 0 LOOP_FILTER_AMP_EN 0 1 Description When writing to Register 0x027, these bits must be 00b Loop filter capacitance select (CIN in Figure 16) 5 pF 17.5 pF 30 pF 42.5 pF 55 pF (default) 67.5 pF 80 pF 92.5 pF 105 pF 117.5 pF 130 pF 142.5 pF 155 pF 167.5 pF 180 pF 192.5 pF Loop filter enable bias Disabled Enabled (default) Loop filter enable amplifier Disabled Enabled (default) Default 00b 0x4 Access W RW 1b RW 1b RW Default 000b Varies Access R R Reset 0x00 Access RW Reset 0x00 Access RW VCO FREQUENCY (REGISTER 0x028) Table 59. Bit Descriptions for VCO_READBACK (Default: 0x00) Bits [7:5] [4:0] Bit Name RESERVED VCO_FREQ_AUTOCAL Settings Description Reserved Read only VCO autocalibrated frequency band. This is a diagnostic bit and the user normally does not need to access this register. USER SCRATCH PAD 2 (REGISTER 0x0FE) Table 60. Bit Descriptions for USER_SCRATCHPAD2 (Default: 0x00) Bits [7:0] Bit Name USER_SCRATCHPAD2, Bits[7:0] Settings 0x00 to 0xFF Description This register has no effect on device operation. It is available for serial port debugging or register setting revision control. There are two additional user scratch pad registers at Address 0x00A and Address 0x0FF. USER SCRATCH PAD 3 (REGISTER 0x0FF) Table 61. Bit Descriptions for USER_SCRATCHPAD3 (Default: 0x00) Bits [7:0] Bit Name USER_SCRATCHPAD3, Bits[7:0] Settings 0x00 to 0xFF Description This register has no effect on device operation. It is available for serial port debugging or register setting revision control. There are two additional user scratch pad registers at Address 0x00A and Address 0x0FE. Rev. 0 | Page 40 of 41 Data Sheet AD9530 OUTLINE DIMENSIONS 0.30 0.25 0.20 37 36 48 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 5.60 SQ 5.50 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE *5.70 EXPOSED PAD 24 PIN 1 INDICATOR 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 10-24-2013-D PIN 1 INDICATOR 7.10 7.00 SQ 6.90 Figure 34. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body and 0.75 mm Package Height (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9530BCPZ AD9530BCPZ-REEL7 AD9530/PCBZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. (c)2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14044-0-4/16(0) Rev. 0 | Page 41 of 41 Package Option CP-48-13 CP-48-13