AD7441BRTZ-R2 - Analog Devices, Inc.

Pseudo Differential Input, 1 MSPS,

10-/12-Bit ADCs in an 8-Lead SOT-23

AD7441/AD7451

Rev. D

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FEATURES

Fast throughput rate: 1 MSPS

Specified for VDD of 2.7 V to 5.25 V

Low power at maximum throughput rate:

4 mW maximum at 1 MSPS with VDD = 3 V

9.25 mW maximum at 1 MSPS with VDD = 5 V

Pseudo differential analog input

Wide input bandwidth:

70 dB SINAD at 100 kHz input frequency

Flexible power/serial clock speed management

No pipeline delays

High speed serial interface:

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

Power-down mode: 1 μA maximum

8-lead SOT-23 and MSOP packages

APPLICATIONS

Transducer interface

Battery-powered systems

Data acquisition systems

Portable instrumentation

FUNCTIONAL BLOCK DIAGRAM

REF

T/H

CONTROL LOGIC

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

GND

SCLK

SDATA

AD7441/AD7451

IN+

IN–

03153-001

Figure 1.

GENERAL DESCRIPTION

The AD7441/AD74511 are, respectively, 10-/12-bit high speed,

low power, single-supply, successive approximation (SAR),

analog-to-digital converters (ADCs) that feature a pseudo

differential analog input. These parts operate from a single

2.7 V to 5.25 V power supply and achieve very low power

dissipation at high throughput rates of up to 1 MSPS.

The AD7441/AD7451 contain a low noise, wide bandwidth,

differential track-and-hold (T/H) amplifier that handles input

frequencies up to 3.5 MHz. The reference voltage for these

devices is applied externally to the VREF pin and can range from

100 mV to VDD, depending on the power supply and what suits

the application.

The conversion process and data acquisition are controlled

using CS and the serial clock, allowing the device to interface

with microprocessors or DSPs. The input signals are sampled

on the falling edge of CS when the conversion is initiated.

The SAR architecture of these parts ensures that there are no

pipeline delays.

1 Protected by U.S. Patent Number 6,681,332.

PRODUCT HIGHLIGHTS

1. Operation with 2.7 V to 5.25 V Power Supplies.

2. High Throughput with Low Power Consumption.

With a 3 V supply, the AD7441/AD7451 offer 4 mW maxi-

mum power consumption for a 1 MSPS throughput rate.

3. Pseudo Differential Analog Input.

4. Flexible Power/Serial Clock Speed Management.

The conversion rate is determined by the serial clock,

allowing the power to be reduced as the conversion time

is reduced through the serial clock speed increase. These

parts also feature a shutdown mode to maximize power

efficiency at lower throughput rates.

5. Variable Voltage Reference Input.

6. No Pipeline Delays.

7. Accurate Control of Sampling Instant via CS Input and

Once-Off Conversion Control.

8. ENOB > 10 Bits Typically with 500 mV Reference.

AD7441/AD7451

Rev. D | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 7

Timing Diagrams .......................................................................... 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

Circuit Information .................................................................... 13

Converter Operation .................................................................. 13

ADC Transfer Function ............................................................. 13

Typical Connection Diagram ................................................... 14

Analog Input ............................................................................... 14

Analog Input Structure .............................................................. 14

Digital Inputs .............................................................................. 15

Reference ..................................................................................... 15

Serial Interface ............................................................................ 16

Modes of Operation ....................................................................... 18

Normal Mode .............................................................................. 18

Power-Down Mode .................................................................... 18

Power vs. Throughput Rate ....................................................... 20

Microprocessor and DSP Interfacing ...................................... 20

Grounding and Layout Hints .................................................... 22

Evaluating Performance ............................................................ 22

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 24

REVISION HISTORY

3/10—Rev. C to Rev. D

Changes to IDD Normal Mode (Operational) Parameter .................. 6

Updated Outline Dimensions ............................................................ 23

Changes to Ordering Guide ............................................................... 24

3/07—Rev. B to Rev. C

Changes to Table 5 ................................................................................. 9

Updated Layout .................................................................................... 12

Changes to Terminology Section....................................................... 12

Updated Outline Dimensions ............................................................ 23

Changes to Ordering Guide ............................................................... 24

2/05—Rev. A to Rev. B

Changes to Ordering Guide ............................................................... 24

2/04—Rev. 0 to Rev. A

Updated Format ..................................................................... Universal

Changes to General Description ....................................................... 1

Changes to Table 1 Footnotes ............................................................ 4

Changes to Table 2 Footnotes ............................................................ 6

Changes to Table 3 Footnotes ............................................................ 7

Changes to Table 5 .............................................................................. 9

Updated Figures 7, 8, and 9 .............................................................. 13

Changes to Figure 23 ......................................................................... 16

Changes to Reference Section .......................................................... 17

9/03—Revision 0: Initial Version

AD7441/AD7451

Rev. D | Page 3 of 24

SPECIFICATIONS

VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Temperature ranges for A, B

versions: −40°C to +85°C.

Table 1. AD7451

Parameter Test Conditions/Comments A Version B Version Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-Noise Ratio (SNR)1 VDD = 2.7 V to 5.25 V 70 70 dB min

Signal-to-(Noise + Distortion) (SINAD)1 VDD = 2.7 V to 3.6 V 69 69 dB min

DD = 4.75 V to 5.25 V 70 70 dB min

Total Harmonic Distortion (THD)1 V

DD = 2.7 V to 3.6 V; −78 dB typ −73 −73 dB max

DD = 4.75 V to 5.25 V; −80 dB typ −75 −75 dB max

Peak Harmonic or Spurious Noise1 V

DD = 2.7 V to 3.6 V; −80 dB typ −73 −73 dB max

DD = 4.75 V to 5.25 V; −82 dB typ −75 −75 dB max

Intermodulation Distortion (IMD)1 fa = 90 kHz; fb = 110 kHz

Second-Order Terms −80 −80 dB typ

Third-Order Terms −80 −80 dB typ

Aperture Delay1 5 5 ns typ

Aperture Jitter1 50 50 ps typ

Full-Power Bandwidth1, 2 @ −3 dB 20 20 MHz typ

@ −0.1 dB 2.5 2.5 MHz typ

DC ACCURACY

Resolution 12 12 Bits

Integral Nonlinearity (INL)1 ±1.5 ±1 LSB max

Differential Nonlinearity (DNL)1 Guaranteed no missed codes to 12 bits ±0.95 ±0.95 LSB max

Offset Error1 ±3.5 ±3.5 LSB max

Gain Error1 ±3 ±3 LSB max

ANALOG INPUT

Full-Scale Input Span VIN+ − VIN– VREF V

REF V

Absolute Input Voltage

VIN+ VREF VREF V

VIN–3 VDD = 2.7 V to 3.6 V −0.1 to +0.4 −0.1 to +0.4 V

DD = 4.75 V to 5.25 V −0.1 to +1.5 −0.1 to +1.5 V

DC Leakage Current ±1 ±1 μA max

Input Capacitance When in track-and-hold 30/10 30/10 pF typ

REFERENCE INPUT

VREF Input Voltage4 ±1% tolerance for specified performance 2.5 2.5 V

DC Leakage Current ±1 ±1 μA max

VREF Input Capacitance When in track-and-hold 10/30 10/30 pF typ

LOGIC INPUTS

Input High Voltage, VINH 2.4 2.4 V min

Input Low Voltage, VINL 0.8 0.8 V max

Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 ±1 μA max

Input Capacitance, CIN5 10 10 pF max

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA 2.8 2.8 V min

DD = 2.7 V to 3.6 V; ISOURCE = 200 μA 2.4 2.4 V min

Output Low Voltage, VOL ISINK = 200 μA 0.4 0.4 V max

Floating-State Leakage Current ±1 ±1 μA max

Floating-State Output Capacitance5 10 10 pF max

Output Coding Straight

(natural) binary

Straight

(natural) binary

AD7441/AD7451

Rev. D | Page 4 of 24

Parameter Test Conditions/Comments A Version B Version Unit

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 16 SCLK cycles

Track-and-Hold Acquisition Time1 Sine wave input 250 250 ns max

Full-scale step input 290 290 ns max

Throughput Rate 1 1 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 2.7/5.25 V min/max

IDD6, 7

Normal Mode (Static) SCLK on or off 0.5 0.5 mA typ

Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 1.95 mA max

DD = 2.7 V to 3.6 V 1.45 1.45 mA max

Full Power-Down Mode SCLK on or off 1 1 μA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V; 1.55 mW typical for 100 ksps6 9.25 9.25 mW max

DD = 3 V; 0.6 mW typical for 100 ksps6 4 4 mW max

Full Power-Down VDD = 5 V; SCLK on or off 5 5 μW max

DD = 3 V; SCLK on or off 3 3 μW max

1 See Terminology section.

2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.

3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+.

4 The AD7451 is functional with a reference input in the range of 100 mV to VDD.

5 Guaranteed by characterization.

6 See the Power vs. Throughput Rate section.

7 Measured with a full-scale dc input.

AD7441/AD7451

Rev. D | Page 5 of 24

VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Temperature range for

B version: −40°C to +85°C.

Table 2. AD7441

Parameter Test Conditions/Comments B Version Unit

DYNAMIC PERFORMANCE fIN = 100 kHz

Signal-to-(Noise + Distortion) (SINAD)1 61 dB min

Total Harmonic Distortion (THD)1 2.7 V to 3.6 V; −77 dB typical −72 dB max

4.75 V to 5.25 V; −79 dB typical −73 dB max

Peak Harmonic or Spurious Noise1 2.7 V to 3.6 V; −80 dB typical −72 dB max

4.75 V to 5.25 V; −82 dB typical −74 dB max

Intermodulation Distortion (IMD)1 fa = 90 kHz, fb = 110 kHz

Second-Order Terms −80 dB typ

Third-Order Terms −80 dB typ

Aperture Delay1 5 ns typ

Aperture Jitter1 50 ps typ

Full-Power Bandwidth1, 2 @ −3 dB 20 MHz typ

@ −0.1 dB 2.5 MHz typ

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity (INL)1 ±0.5 LSB max

Differential Nonlinearity (DNL)1 Guaranteed no missed codes to 10 bits ±0.5 LSB max

Offset Error1 ±1 LSB max

Gain Error1 ±1 LSB max

ANALOG INPUT

Full-Scale Input Span VIN+ − VIN– VREF V

Absolute Input Voltage

VIN+ VREF V

VIN–3 VDD = 2.7 V to 3.6 V −0.1 to +0.4 V

DD = 4.75 V to 5.25 V −0.1 to +1.5 V

DC Leakage Current ±1 μA max

Input Capacitance When in track-and-hold 30/10 pF typ

REFERENCE INPUT

VREF Input Voltage4 ±1% tolerance for specified performance 2.5 V

DC Leakage Current ±1 μA max

VREF Input Capacitance When in track-and-hold 10/30 pF typ

LOGIC INPUTS

Input High Voltage, VINH 2.4 V min

Input Low Voltage, VINL 0.8 V max

Input Current, IIN Typically 10 nA, VIN = 0 V or VDD ±1 μA max

Input Capacitance, CIN5 10 pF max

LOGIC OUTPUTS

Output High Voltage, VOH VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA 2.8 V min

DD = 2.7 V to 3.6 V; ISOURCE = 200 μA 2.4 V min

Output Low Voltage, VOL ISINK = 200 μA 0.4 V max

Floating-State Leakage Current ±1 μA max

Floating-State Output Capacitance5 10 pF max

Output Coding Straight (natural) binary

AD7441/AD7451

Rev. D | Page 6 of 24

Parameter Test Conditions/Comments B Version Unit

CONVERSION RATE

Conversion Time 888 ns with an 18 MHz SCLK 16 SCLK cycles

Track-and-Hold Acquisition Time1 Sine wave input 250 ns max

Step input 290 ns max

Throughput Rate 1 MSPS max

POWER REQUIREMENTS

VDD 2.7/5.25 V min/max

IDD6, 7

Normal Mode (Static) SCLK on or off 0.5 mA typ

Normal Mode (Operational) VDD = 4.75 V to 5.25 V 1.95 mA max

DD = 2.7 V to 3.6 V 1.45 mA max

Full Power-Down Mode SCLK on or off 1 μA max

Power Dissipation

Normal Mode (Operational) VDD = 5 V; 1.55 mW typ for 100 ksps6 9.25 mW max

DD = 3 V; 0.6 mW typ for 100 ksps6 4 mW max

Full Power-Down VDD = 5 V; SCLK on or off 5 μW max

DD = 3 V; SCLK on or off 3 μW max

1 See the Terminology section.

2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.

3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+.

4 The AD7441 is functional with a reference input in the range 100 mV to VDD.

5 Guaranteed by characterization.

6 See the Power vs. Throughput Rate section.

7 Measured with a full-scale dc input.

AD7441/AD7451

Rev. D | Page 7 of 24

TIMING SPECIFICATIONS1

VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter Limit at TMIN, TMAX Unit Description

fSCLK2 10 kHz min

18 MHz max

tCONVERT 16 × tSCLK tSCLK = 1/fSCLK

888 ns max

tQUIET 60 ns min Minimum quiet time between end of a serial read and next falling edge of CS

t1 10 ns min Minimum CS pulse width

t2 10 ns min CS falling edge to SCLK falling edge setup time

t33 20 ns max Delay from CS falling edge until SDATA three-state disabled

t4 40 ns max Data access time after SCLK falling edge

t5 0.4 tSCLK ns min SCLK high pulse width

t6 0.4 tSCLK ns min SCLK low pulse width

t7 10 ns min SCLK edge to data valid hold time

t84 10 ns min SCLK falling edge to SDATA, three-state enabled

35 ns max SCLK falling edge to SDATA, three-state enabled

tPOWER-UP5 1 μs max Power-up time from full power-down

1 Guaranteed by characterization. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3,

and the Serial Interface section.

2 Mark/space ratio for the SCLK input is 40/60 to 60/40.

3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and the time required for an output to

cross 0.4 V or 2.0 V for VDD = 3 V.

4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time (t8) quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

5 See the Power-Up Time section.

TIMING DIAGRAMS

QUIET

CONVERT

SCLK

SDATA

4 LEADING ZEROS THREE-STATE

12345 13141516

0 0 0 0 DB11 DB10 DB2 DB1 DB0

03153-002

Figure 2. AD7451 Serial Interface Timing Diagram

QUIET

CONVERT

SCLK

SDAT

4 LEADING ZEROS 2 TRAILING ZEROS THREE-STATE

12345 13141516

0 0 0 0 DB9 DB8 DB0 0 0

03153-003

Figure 3. AD7441 Serial Interface Timing Diagram

AD7441/AD7451

Rev. D | Page 8 of 24

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V

VIN+ to GND −0.3 V to VDD + 0.3 V

VIN– to GND −0.3 V to VDD + 0.3 V

Digital Input Voltage to GND −0.3 V to +7 V

Digital Output Voltage to GND −0.3 V to VDD + 0.3 V

VREF to GND −0.3 V to VDD + 0.3 V

Input Current to any Pin Except Supplies1 ±10 mA

Operating Temperature Range

Commercial (A, B Version)

−40°C to +85°C

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

θJA Thermal Impedance 205.9°C/W (MSOP)

211.5°C/W (SOT-23)

θJC Thermal Impedance 43.74°C/W (MSOP)

91.99°C/W (SOT-23)

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

ESD 1 kV

1 Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

1.6mA I

200µA I

1.6V

TO OUTPUT

PIN C

25pF

03153-004

Figure 4. Load Circuit for Digital Output Timing Specifications

ESD CAUTION

AD7441/AD7451

Rev. D | Page 9 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SCLK

SDATA

REF 1

IN+ 2

IN– 3

GND

AD7441/

AD7451

TOP VIEW

(Not to Scale)

3153-006

Figure 5. 8-Lead MSOP Pin Configuration

VREF

VIN+

VIN–

GND

VDD 1

SCLK 2

SDATA 3

CS 4

AD7441/

AD7451

TOP VIEW

(Not to Scale)

3153-005

Figure 6. 8-Lead SOT-23 Pin Configuration

Table 5. Pin Function Descriptions

Pin. No.

Mnemonic Description

MSOP SOT-23

1 8 VREF Reference Input for the AD7441/AD7451. An external reference in the range of 100 mV to VDD must be

applied to this input. The specified reference input is 2.5 V. This pin is decoupled to GND with a capacitor

of at least 0.1 μF.

2 7 VIN+ Noninverting Analog Input.

3 6 VIN– Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc

offset to provide a pseudo ground.

4 5 GND Analog Ground. Ground reference point for all circuitry on the AD7441/AD7451. All analog input signals

and any external reference signal are referred to this GND voltage.

5 4 CS Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on

the AD7441/AD7451 and framing the serial data transfer.

6 3 SDATA Serial Data, Logic Output. The conversion result from the AD7441/AD7451 is provided on this output as

a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of

the AD7451 consists of four leading zeros followed by the 12 bits of conversion data that are provided

MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the 10 bits of con-

version data, followed by two trailing zeros. In both cases, the output coding is straight (natural) binary.

7 2 SCLK Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input

is also used as the clock source for the conversion process.

8 1 VDD Power Supply Input. VDD is 2.7 V to 5.25 V. This supply is decoupled to GND with a 0.1 μF capacitor and a

10 μF tantalum capacitor.

AD7441/AD7451

Rev. D | Page 10 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, fS = 1 MSPS, fSCLK = 18 MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V, unless otherwise noted.

10 100 1000

FREQUENCY (kHz)

SINAD (dB)

= 5.25V

= 4.75V

= 3.6V

= 2.7V

03153-007

Figure 7. SINAD vs. Analog Input Frequency for the AD7451 for

Various Supply Voltages

–120

–80

–100

–60

–40

–20

0 100 200 300 400 500 600 700 800 900 1000

SUPPLY RIPPLE FREQUENCY (kHz)

PSRR (dB)

100mV p-p SINE WAVE ON V

NO DECOUPLING ON V

= 3V

= 5V

03153-008

Figure 8. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

FREQUENCY (kHz)

SNR (dB)

0 100 200

–100

–140

500

–20

–120

–40

–60

–80

8192 POINT FFT

SAMPLE

= 1MSPS

= 100kSPS

SINAD = 71dB

THD = –82dB

SFDR = –83dB

300 400

03153-009

Figure 9. AD7451 Dynamic Performance for VDD = 5 V

DNL ERROR (LSB)

CODE

0.4

0 1024 2048 3072

0.2

–0.2

–0.4

–1.0

4096

0.6

0.8

1.0

–0.6

–0.8

03153-010

Figure 10. Typical DNL for the AD7451 for VDD = 5 V

INL ERROR (LSB)

CODE

0.4

0 1024 2048 3072

0.2

–0.2

–0.4

–1.0

4096

0.6

0.8

1.0

–0.6

–0.8

03153-011

Figure 11. Typical INL for the AD7451 for VDD = 5 V

COUNTS

CODES

2046 2047 2048 2049 2050 2051

27 CODES 24 CODES

1000

2000

3000

4000

5000

6000

7000

8000

9000

10000

9949

CODES

03153-012

Figure 12. Histogram of 10,000 Conversions of a DC Input for the AD7451

AD7441/AD7451

Rev. D | Page 11 of 24

CHANGE IN DNL (LSB)

–1.0

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

01234

4.0

VREF (V)

POSITIVE DNL

NEGATIVE DNL

03153-013

Figure 13. Change in DNL vs. VREF for VDD = 5 V

CHANGE IN INL (LSB)

–2

–1

01234

VREF (V)

POSITIVE DNL

NEGATIVE DNL

03153-014

Figure 14. Change in INL vs. VREF for VDD = 5 V

EFFECTIVE NUMBER OF BITS

012345

VREF (V)

VDD = 3V

VDD = 5V

03153-015

Figure 15. ENOB vs. VREF for VDD = 5 V and 3 V

SNR (dB)

0 100 200 300 400 500

–20

–40

–60

–80

–100

–120

–140

VREF (V)

8192 POINT FFT

fSAMPLE = 1MSPS

fIN = 100kSPS

SINAD = 61.7dB

THD = –81.7dB

SFDR = –82dB

03153-016

Figure 16. AD7441 Dynamic Performance

DNL ERROR (LSB)

0 256 512 768 1024

0.5

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

CODE

3153-017

Figure 17. Typical DNL for the AD7441

INL ERROR (LSB)

0 256 512 768 1024

0.5

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

CODE

3153-018

Figure 18. Typical INL for the AD7441

AD7441/AD7451

Rev. D | Page 12 of 24

TERMINOLOGY

Signal-to-(Noise + Distortion) Ratio (SINAD)

This is the measured ratio of SINAD at the output of the ADC.

The signal is the rms amplitude of the fundamental. Noise is

the sum of all nonfundamental signals up to half the sampling

frequency (fS/2), excluding dc. The ratio is dependent on the

number of quantization levels in the digitization process: the more

levels, the smaller the quantization noise. The theoretical SINAD

ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Therefore, for 12-bit converters, the SINAD is 74 dB; for 10-bit

converters, the SINAD is 62 dB.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the

fundamental. In the AD7441/AD7451, THD is

()

65432 V

VVVVV

THD 22222

log20dB ++++

where:

V1 is the rms amplitude of the fundamental.

V2, V3, V4, V5, and V6 are the rms amplitudes of the second to

the sixth harmonics.

Peak Harmonic or Spurious Noise

Peak harmonic (spurious noise) is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to fS/2, excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is

a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, an active device with nonlinearities creates distortion products

at sum and difference frequencies of mfa ± nfb where m, n = 0,

1, 2, 3, and so on. Intermodulation distortion terms are those in

which neither m nor n are equal to zero. For example, the second-

order terms include (fa + fb) and (fa − fb), while the third-order

terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

The AD7441/AD7451 are tested using the CCIF standard where

two input frequencies near the top end of the input bandwidth

are used. In this case, the second-order terms are usually dis-

tanced in frequency from the original sine waves while the

third-order terms are usually at a frequency close to the input

frequencies. As a result, the second- and third-order terms

are specified separately. The calculation of the intermodulation

distortion is as per the THD specification where it is the ratio of

the rms sum of the individual distortion products to the rms

amplitude of the sum of the fundamentals expressed in decibels.

Aperture Delay

This is the amount of time from the leading edge of the

sampling clock until the ADC actually takes the sample.

Aperture Jitter

This is the sample-to-sample variation in the effective point in

time at which the actual sample is taken.

Full Power Bandwidth

The full power bandwidth of an ADC is that input frequency

at which the amplitude of the reconstructed fundamental is

reduced by 0.1 dB or 3 dB for a full-scale input.

Integral Nonlinearity (INL)

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function.

Differential Nonlinearity (DNL)

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (000…000 to

000…001) from the ideal (that is, AGND + 1 LSB).

Gain Error

This is the deviation of the last code transition (111…110 to

111…111) from the ideal (that is, VREF − 1 LSB) after the offset

error has been adjusted out.

Track-and-Hold Acquisition Time

The track-and-hold acquisition time is the minimum time

required for the track-and-hold amplifier to remain in track

mode for its output to reach and settle to within 0.5 LSB of the

applied input signal.

Power Supply Rejection Ratio (PSRR)

The power supply rejection ratio is defined as the ratio of the

power in the ADC output at full-scale frequency (f) to the

power of a 100 mV p-p sine wave applied to the ADC VDD

supply of Frequency fS. The frequency of this input varies from

1 kHz to 1 MHz.

PSRR (dB) = 10log(Pf/Pfs)

where:

Pf is the power at Frequency f in the ADC output.

Pfs is the power at Frequency fs in the ADC output.

AD7441/AD7451

Rev. D | Page 13 of 24

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7441/AD7451 are 10-/12-bit, high speed, low power,

single-supply, successive approximation, analog-to-digital con-

verters (ADCs) with a pseudo differential analog input. These

parts operate with a single 2.7 V to 5.25 V power supply and are

capable of throughput rates up to 1 MSPS when supplied with

an 18 MHz SCLK. The AD7441/AD7451 require an external

reference to be applied to the VREF pin.

The AD7441/AD7451 have a SAR ADC, an on-chip differential

track-and-hold amplifier, and a serial interface housed in either

an 8-lead SOT-23 or an MSOP package. The serial clock input

accesses data from the part and provides the clock source for

the SAR ADC. The AD7441/AD7451 feature a power-down

option for reduced power consumption between conversions.

The power-down feature is implemented across the standard

serial interface, as described in the Modes of Operation section.

CONVERTER OPERATION

The AD7441/AD7451 are SAR ADCs based around two

capacitive DACs. Figure 19 and Figure 20 show simplified

schematics of the ADC in the acquisition and conversion phase,

respectively. The ADC is comprised of control logic, an SAR,

and two capacitive DACs. In Figure 19 (acquisition phase), SW3

is closed, SW1 and SW2 are in Position A, the comparator is

held in a balanced condition, and the sampling capacitor arrays

acquire the differential signal on the input.

IN+

IN–

SW1

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

REF

SW2

03153-019

Figure 19. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 20), SW3 opens

and SW1 and SW2 move to Position B, causing the comparator

to become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and the charge redistribu-

tion DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is rebal-

anced, the conversion is complete. The control logic generates

the ADC output code. The output impedances of the sources

driving the VIN+ and VIN– pins must be matched; otherwise the

two inputs have different settling times, resulting in errors.

IN+

IN–

SW1

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

REF

SW2

03153-020

Figure 20. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7441/AD7451 is straight (natural)

binary. The designed code transitions occur at successive LSB

values (1 LSB, 2 LSB, and so on). The LSB size of the AD7451

is VREF/4096, and the LSB size of the AD7441 is VREF/1024. The

ideal transfer characteristic of the AD7441/AD7451 is shown in

Figure 21.

000...000

ADC CODE

ANALOG INPUT

111...111

000...001

111...000

011...111

111...110

000...010

1LSB =

REF

4096 (AD7451)

1LSB = VREF/1024 (AD7441)

VREF – 1LSB1LSB

03153-021

Figure 21. AD7441/AD7451 Ideal Transfer Characteristic

AD7441/AD7451

Rev. D | Page 14 of 24

TYPICAL CONNECTION DIAGRAM

Figure 22 shows a typical connection diagram for the device.

In this setup, the GND pin is connected to the analog ground

plane of the system. The VREF pin is connected to the AD780,

a 2.5 V decoupled reference source. The signal source is connected

to the VIN+ analog input via a unity gain buffer. A dc voltage is

connected to the VIN– pin to provide a pseudo ground for the

VIN+ input. The VDD pin is decoupled to AGND with a 10 μF

tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.

The reference pin is decoupled to AGND with a capacitor of at

least 0.1 μF. The conversion result is output in a 16-bit word

with four leading zeros followed by the MSB of the 12-bit or

10-bit result. The 10-bit result of the AD7441 is followed by two

trailing zeros.

AD7441/

AD7451

0.1µF

10µF

REF

DC INPUT

VOLTAGE

IN+

SCLK

2.7V TO 5.25

SUPPLY

SERIAL

INTERFACE

µC/µP

SDATA

GND

IN–

2.5V

AD780

REF

p-p

03153-022

Figure 22. Typical Connection Diagram

ANALOG INPUT

The AD7441/AD7451 have a pseudo differential analog input.

The VIN+ input is coupled to the signal source and must have an

amplitude of VREF p-p to make use of the full dynamic range of

the part. A dc input is applied to the VIN–. The voltage applied to

this input provides an offset from ground or a pseudo ground

for the VIN+ input. Pseudo differential inputs separate the analog

input signal ground from the ADC ground, allowing dc common-

mode voltages to be cancelled.

Because the ADC operates from a single supply, it is necessary

to level shift ground-based bipolar signals to comply with the

input requirements. An op amp (for example, the AD8021) can

be configured to rescale and level shift a ground-based (bipolar)

signal so that it is compatible with the input range of the AD7441/

AD7451 (see Figure 23).

When a conversion takes place, the pseudo ground corresponds

to 0, and the maximum analog input corresponds to 4096 for

the AD7451 and 1024 for the AD7441.

2.5

1.25V

+1.25V

–1.25V

0.1µF

AD7441/

AD7451

IN+

IN–

REF

EXTERNAL

REF

(2.5V)

3153-023

Figure 23. Op Amp Configuration to Level Shift a Bipolar Input Signal

ANALOG INPUT STRUCTURE

Figure 24 shows the equivalent circuit of the analog input

structure of the AD7441/AD7451. The four diodes provide

ESD protection for the analog inputs. Care must be taken to

ensure that the analog input signals never exceed the supply

rails by more than 300 mV. This causes these diodes to become

forward-biased and start conducting into the substrate. These

diodes can conduct up to 10 mA without causing irreversible

damage to the part. The C1 capacitors (see Figure 24) are

typically 4 pF and can be attributed primarily to pin capaci-

tance. The resistors are lumped components made up of

the on resistance of the switches. The value of these resistors

is typically about 100 Ω. The C2 capacitors are the ADC

sampling capacitors and have a capacitance of 16 pF typically.

For ac applications, removing high frequency components from

the analog input signal through the use of an RC low-pass filter

on the relevant analog input pins is recommended. In applica-

tions where harmonic distortion and the signal-to-noise ratio

are critical, it is recommended that the analog input be driven

from a low impedance source. Large source impedances

significantly affect the ac performance of the ADC, which can

necessitate the use of an input buffer amplifier. The choice of

the amplifier is a function of the particular application.

VDD

VIN+

VIN–

03153-024

Figure 24. Equivalent Analog Input Circuit;

Conversion Phase—Switches Open;

Track Phase—Switches Closed

AD7441/AD7451

Rev. D | Page 15 of 24

When no amplifier is used to drive the analog input, it is

recommended that the source impedance be limited to low

values. The maximum source impedance depends on the

amount of total harmonic distortion that can be tolerated.

The THD increases as the source impedance increases and

performance degrades.

Figure 25 shows a graph of THD vs. analog input signal

frequency for different source impedances.

–100

–90

–80

–70

–60

–50

–40

–30

–10

–20

10k 100k 1M

INPUT FREQUENCY (Hz)

THD (dB)

200Ω

100Ω

62Ω10Ω

TA = 25°C

VDD = 5V

03153-025

Figure 25. THD vs. Analog Input Frequency for Various Source Impedances

Figure 26 shows a graph of THD vs. analog input frequency for

various supply voltages while sampling at 1 MSPS with an SCLK

of 18 MHz. In this case, the source impedance is 10 Ω.

–

–90

–85

–80

–75

–70

–65

–60

–55

10 100 1000

INPUT FREQUENCY (kHz)

THD (dB)

TA = 25°C

VDD = 2.7V

VDD = 3.6V

VDD = 4.75V

VDD = 5.25V

03153-026

Figure 26. THD vs. Analog Input Frequency for Various Supply Voltages

DIGITAL INPUTS

The digital inputs applied to the AD7441/AD7451 are not limited

by the maximum ratings that limit the analog inputs. Instead,

the digital inputs applied, that is, CS and SCLK, can go to 7 V

and are not restricted by the VDD + 0.3 V limits as on the analog

input. The main advantage of the inputs not being restricted to

the VDD + 0.3 V limit is that power supply sequencing issues are

avoided. If CS or SCLK are applied before VDD, there is no risk

of latch-up as there would be on the analog inputs if a signal

greater than 0.3 V were applied prior to VDD.

REFERENCE

An external source is required to supply the reference to the

AD7441/AD7451. This reference input can range from 100 mV

to VDD. The specified reference is 2.5 V for the power supply

range 2.7 V to 5.25 V. The reference input chosen for an appli-

cation must never be greater than the power supply. Errors in

the reference source result in gain errors in the AD7441/AD7451

transfer function and add to the specified full-scale errors of the

part. A capacitor of at least 0.1 μF must be placed on the VREF

pin. Suitable reference sources for the AD7441/AD7451 include

the AD780 and the ADR421. Figure 27 shows a typical connec-

tion diagram for the VREF pin.

AD780

GND

TEMP

OPSEL

TRIM

OUT

AD7441/

AD7451*

REF

2.5V

NC = NO CONNECT

10nF 0.1µF 0.1µF

0.1µF

*ADDITIONAL PINS OMITTED FOR CLARITY.

3153-027

Figure 27. Typical VREF Connection Diagram for VDD = 5 V

AD7441/AD7451

Rev. D | Page 16 of 24

SERIAL INTERFACE

Figure 2 and Figure 3 show detailed timing diagrams for the

serial interface of the AD7451 and the AD7441, respectively.

The serial clock provides the conversion clock and also controls

the transfer of data from the device during conversion.

CS initiates the conversion process and frames the data transfer.

The falling edge of CS puts the track-and-hold into hold mode

and takes the bus out of three-state. The analog input is sampled

and the conversion initiated at this point. The conversion requires

16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track-and-hold

goes back into track mode on the next SCLK rising edge, as

shown at Point B in Figure 2 and Figure 3. On the 16th SCLK

falling edge, the SDATA line goes back into three-state.

If the rising edge of CS occurs before 16 SCLKs have elapsed,

the conversion is terminated and the SDATA line goes back into

three-state.

The conversion result from the AD7441/AD7451 is provided on

the SDATA output as a serial data stream. The bits are clocked

out on the falling edge of the SCLK input. The data stream of

the AD7451 consists of four leading zeros followed by 12 bits

of conversion data, provided MSB first. The data stream of the

AD7441 consists of four leading zeros, followed by the 10 bits

of conversion data, followed by two trailing zeros, which is also

provided MSB first. In both cases, the output coding is straight

(natural) binary.

Sixteen serial clock cycles are required to perform a conversion

and to access data from the AD7441/AD7451. CS going low

provides the first leading zero to be read in by the DSP or the

microcontroller. The remaining data is then clocked out on the

subsequent SCLK falling edges, beginning with the second leading

zero. Thus, the first falling clock edge on the serial clock pro-

vides the second leading zero. The final bit in the data transfer

is valid on the 16th falling edge, having been clocked out on the

previous (15th) falling edge. Once the conversion is complete

and the data has been accessed after the 16 clock cycles, it is

important to ensure that, before the next conversion is initiated,

enough time is left to meet the acquisition and quiet-time speci-

fications (see the and

sections). To achieve 1 MSPS with an 18 MHz clock, an 18-clock

burst performs the conversion and leaves enough time before the

next conversion for the acquisition and quiet time.

Timing Example 1 Timing Example 2

In applications with slower SCLKs, it is possible to read in data

on each SCLK rising edge; that is, the first rising edge of SCLK

after the CS falling edge has the leading zero provided, and the

15th SCLK edge has DB0 provided.

AD7441/AD7451

Rev. D | Page 17 of 24

Timing Example 2

Timing Example 1

Having fSCLK = 5 MHz and a throughput rate of 315 kSPS gives a

cycle time of

Having fSCLK = 18 MHz and a throughput rate of 1 MSPS gives a

cycle time of

1/Throughput = 1/315,000 = 3.174 μs

1/Throughput = 1/1,000,000 = 1 μs

A cycle consists of

t2 + 12.5 (1/fSCLK) + tACQUISITION = 3.174 μs

t2 + 12.5 (1/fSCLK) + tACQUISITION = 1 μs

Therefore, if t2 is 10 ns, then

Therefore, if t2 = 10 ns, then

10 ns + 12.5 (1/5 MHz) + tACQUISITION = 3.174 μs

tACQUISITION = 664 ns

10 ns + 12.5 (1/18 MHz) + tACQUISITION = 1 μs

tACQUISITION = 296 ns

This 664 ns satisfies the requirement of 290 ns for tACQUISITION.

This 296 ns satisfies the requirement of 290 ns for tACQUISITION.

From Figure 28, tACQUISITION comprises

2.5 (1/fSCLK) + t8 = tQUIET

where t8 = 35 ns. This allows a value of 129 ns for tQUIET,

satisfying the minimum requirement of 60 ns.

where t8 = 35 ns. This allows a value of 122 ns for tQUIET,

satisfying the minimum requirement of 60 ns.

As in this example and with other slower clock values, the signal

can already be acquired before the conversion is complete, but it

is still necessary to leave 60 ns minimum tQUIET between conver-

sions. In Example 2, the signal is fully acquired at approximately

Point C in Figure 28.

tCONVERT

SCLK 12345 13141516

12.5(1/

fSCLK

)

tACQUISITION

1/THROUGHPUT

tQUIET

10ns

B C

03153-028

Figure 28. Serial Interface Timing Example

AD7441/AD7451

Rev. D | Page 18 of 24

MODES OF OPERATION

The operating mode of the AD7441/AD7451 is selected by

controlling the logic state of the CS signal during a conversion.

There are two operating modes: normal mode and power-down

mode. The point at which CS is pulled high after the conversion

is initiated determines whether the part enters power-down mode.

Similarly, if already in power-down, CS controls whether the

device returns to normal operation or remains in power-down.

These modes provide flexible power management options that

can optimize the power dissipation/throughput rate ratio for

differing application requirements.

NORMAL MODE

This mode is intended for fastest throughput rate performance.

The user does not have to worry about any power-up times with

the AD7441/AD7451 remaining fully powered up all the time.

Figure 29 shows the general diagram of the operation of the

AD7441/AD7451 in this mode. The conversion is initiated

on the falling edge of CS (see the section). To

ensure that the part remains fully powered up,

Serial Interface

CS must remain

low until at least 10 SCLK falling edges elapse after the falling

edge of CS.

If CS is brought high any time after the 10th SCLK falling edge,

but before the 16th SCLK falling edge, the part remains pow-

ered up, however the conversion is terminated and SDATA goes

back into three-state. Sixteen serial clock cycles are required to

complete the conversion and access the complete conversion

result. CS can idle high until the next conversion or can idle

low until sometime prior to the next conversion. Once a data

transfer is complete—that is, when SDATA has returned to

three-state—another conversion can be initiated after the

quiet time, tQUIET, elapses again bringing CS low.

110

SCLK

DATA

4 LEADING ZEROS + CONVERSION RESULT

3153-029

Figure 29. Normal Mode Operation

POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required; either the ADC is powered

down between each conversion or a series of conversions can

be performed at a high throughput rate and the ADC is then

powered down for a relatively long duration between these

bursts of conversions. When the AD7441/AD7451 are in

power-down mode, all analog circuitry is powered down.

For the AD7441/AD7451 to enter power-down mode, the

conversion process must be interrupted by bringing CS high

anywhere after the second falling edge of SCLK and before

the 10th falling edge of SCLK, as shown in . Figure 30

Once CS has been brought high in this window of SCLKs, the

part enters power-down, the conversion that was initiated by

the falling edge of CS is terminated, and SDATA goes back into

three-state. The time from the rising edge of CS to SDATA

three-state enabled is never greater than t8 (see the

section). If

Timing

Specifications CS is brought high before the second

SCLK falling edge, the part remains in normal mode and does

not power down. This avoids accidental power-down due to

glitches on the CS line.

To exit power-down mode and power up the AD7441/AD7451

again, a dummy conversion is performed. On the falling edge

of CS, the device begins to power up and continues to do so

as long as CS is held low until after the falling edge of the 10th

SCLK. The device is fully powered up after 1 μs has elapsed and,

as shown in , valid data results from the next

conversion.

Figure 31

110

SCLK

SDATA THREE-STATE

3153-030

Figure 30. Entering Power-Down Mode

AD7441/AD7451

Rev. D | Page 19 of 24

SCLK

SDATA

110 16 1 10 16

THIS PART IS FULLY POWERED

UP WITH V

FULLY ACQUIRED

PART BEGINS

TO POWER UP

INVALID DATA VALID DATA

tPOWER-UP

03153-031

Figure 31. Exiting Power-Down Mode

If CS is brought high before the 10th falling edge of SCLK, the

AD7441/AD7451 again go back into power-down. This avoids

accidental power-up due to glitches on the CS line or an inad-

vertent burst of eight SCLK cycles while CS is low. So although

the device may begin to power up on the falling edge of CS, it

again powers down on the rising edge of CS as long as it occurs

before the 10th SCLK falling edge.

Power-Up Time

The power-up time of the AD7441/AD7451 is typically 1 μs,

which means that with any frequency of SCLK up to 18 MHz,

one dummy cycle is always sufficient to allow the device to

power up. Once the dummy cycle is complete, the ADC is fully

powered up and the input signal is acquired properly. The quiet

time, tQUIET, must still be allowed—from the point at which the

bus goes back into three-state after the dummy conversion to

the next falling edge of CS.

When running at the maximum throughput rate of 1 MSPS,

the AD7441/AD7451 power up and acquire a signal within

±0.5 LSB in one dummy cycle, that is, 1 μs. When powering up

from the power-down mode with a dummy cycle, as in Figure 31,

the track-and-hold, which was in hold mode while the part was

powered down, returns to track mode after the first SCLK edge

the part receives after the falling edge of CS. This is shown as

Point A in . Figure 31

Although at any SCLK frequency one dummy cycle is sufficient

to power up the device and acquire VIN, it does not necessarily

mean that a full dummy cycle of 16 SCLKs must always elapse

to power up the device and acquire VIN fully; 1 μs is sufficient to

power up the device and acquire the input signal.

For example, when a 5 MHz SCLK frequency is applied to the

ADC, the cycle time is 3.2 μs (that is, 1/(5 MHz) × 16). In one

dummy cycle, 3.2 μs, the part is powered up, and VIN is acquired

fully. However, after 1 μs with a five MHz SCLK, only five SCLK

cycles elapse. At this stage, the ADC is fully powered up and the

signal acquired. Therefore, in this case, the CS can be brought

high after the 10th SCLK falling edge and brought low again

after a time, tQUIET, to initiate the conversion.

When power supplies are first applied to the AD7441/AD7451,

the ADC can power up either in power-down mode or normal

mode. For this reason, it is best to allow a dummy cycle to elapse

to ensure that the part is fully powered up before attempting a

valid conversion. Likewise, if the user wants the part to power

up in power-down mode, then the dummy cycle can be used to

ensure the device is in power-down mode by executing a cycle

such as that shown in Figure 30. Once supplies are applied to

the AD7441/AD7451, the power-up time is the same as that

when powering up from power-down mode. It takes approxi-

mately 1 μs to power up fully in normal mode. It is not necessary

to wait 1 μs before executing a dummy cycle to ensure the

desired mode of operation. Instead, the dummy cycle can

occur directly after power is supplied to the ADC. If the first

valid conversion is then performed directly after the dummy

conversion, care must be taken to ensure that adequate

acquisition time has been allowed.

As mentioned earlier, when powering up from the power-down

mode, the part returns to track mode upon the first SCLK edge

applied after the falling edge of CS. However, when the ADC

powers up initially after supplies are applied, the track-and-

hold is already in track mode. This means (assuming one has

the facility to monitor the ADC supply current) that if the ADC

powers up in the desired mode of operation, a dummy cycle is

not required to change mode. Thus, a dummy cycle is also not

required to place the track-and-hold into track.

AD7441/AD7451

Rev. D | Page 20 of 24

POWER VS. THROUGHPUT RATE

By using the power-down mode on the device when not con-

verting, the average power consumption of the ADC decreases

at lower throughput rates. Figure 32 shows how, as the through-

put rate is reduced, the device remains in its power-down state

longer and the average power consumption reduces accordingly.

For example, if the AD7441/AD7451 are operated in continuous

sampling mode with a throughput rate of 100 kSPS and an SCLK

of 18 MHz, and the device is placed in the power-down mode

between conversions, then the power consumption during

normal operation equals 9.25 mW maximum (for VDD = 5 V).

If the power-up time is one dummy cycle (1 μs) and the remain-

ing conversion time is another cycle (1 μs), then the AD7441/

AD7451 can be said to dissipate 9.25 mW for 2 μs during each

conversion cycle. (This power consumption figure assumes a

very short time to enter power-down mode. This power figure

increases as the burst of clocks used to enter power-down mode

is increased). The AD7441/AD7451 consume just 5 μW for the

remaining 8 μs.

Calculate the power numbers in Figure 32 as follows:

If the throughput rate = 100 kSPS, then the cycle time = 10 μs,

and the average power dissipated during each cycle is

(2/10) × 9.25 mW = 1.85 mW

For the same scenario, if VDD = 3 V, the power dissipation

during normal operation is 4 mW maximum.

The AD7441/AD7451 can now be said to dissipate 4 mW for

2 μs during each conversion cycle.

The average power dissipated during each cycle with a

throughput rate of 100 kSPS is, therefore,

(2/10) × 4 mW = 0.8 mW

THROUGHPUT (kSPS)

100

0350

POWER (mW)

0.01 50 100 150 200 250 300

0.1

10 VDD = 5V

VDD = 3V

03153-032

Figure 32. Power vs. Throughput Rate for Power-Down Mode

For optimum power performance in throughput rates above

320 kSPS, it is recommended that the serial clock frequency be

reduced.

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7441/AD7451 allows the part to

be connected directly to a range of different microprocessors.

This section explains how to interface the AD7441/AD7451

with some of the more common microcontroller and DSP serial

interface protocols.

AD7441/AD7451 to ADSP-21xx

The ADSP-21xx family of DSPs is interfaced directly to the

AD7441/AD7451 without any glue logic required. The SPORT

control register is set up as follows:

TFSW = RFSW = 1 Alternate framing

INVRFS = INVTFS = 1 Active low frame signal

DTYPE = 00 Right justify data

SLEN = 1111 16-bit data-words

ISCLK = 1 Internal serial clock

TFSR = RFSR = 1 Frame every word

IRFS = 0

ITFS = 1

To implement power-down mode, SLEN is set to 1001 to issue

an 8-bit SCLK burst.

The connection diagram is shown in Figure 33. ADSP-21xx has

the TFS and RFS of the SPORT tied together, with TFS set as an

output and RFS set as an input. The DSP operates in alternate

framing mode, and the SPORT control register is set up as

described. The frame synchronization signal generated on the

TFS is tied to CS, and, as with all signal processing applications,

equidistant sampling is necessary. However, in this example,

the timer interrupt is used to control the sampling rate of the

ADC, and, under certain conditions, equidistant sampling

cannot be achieved.

AD7441/

AD7451*

ADSP-21xx*

SCLK

RFS

TFS

SCLK

SDATA

*ADDITIONAL PINS REMOVED FOR CLARITY.

3153-033

Figure 33. Interfacing to the ADSP-21xx

AD7441/AD7451

Rev. D | Page 21 of 24

AD7441/AD7451 to DSP56xxx

The timer registers, for example, are loaded with a value that

provides an interrupt at the required sample interval. When an

interrupt is received, a value is transmitted with TFS/DT (ADC

control word). The TFS is used to control the RFS and, there-

fore, the reading of data. The frequency of the serial clock is set

in the SCLKDIV register. When the instruction to transmit with

TFS is given, that is, AX0 = TX0, the state of the SCLK is checked.

The DSP waits until the SCLK has gone high, low, and high

before starting transmission. If the timer and SCLK values are

chosen such that the instruction to transmit occurs on or near

the rising edge of SCLK, then the data can either be transmitted

or wait until the next clock edge.

The connection diagram in Figure 35 shows how the AD7441/

AD7451 can be connected to the SSI (synchronous serial interface)

of the DSP56xxx family of DSPs from Motorola. The SSI is

operated in synchronous mode (SYN bit in CRB = 1) with

internally generated 1-bit clock period frame sync for both Tx

and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB). Set the word

length to 16 by setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. To

implement the power-down mode on the AD7441/AD7451, the

word length can be changed to eight bits by setting B it WL1 = 0

and Bit WL0 = 0 in CRA. Note that for signal processing applica-

tions, the frame synchronization signal from the DSP56xxx must

provide equidistant sampling.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value of 3,

an SCLK of 2 MHz is obtained and eight master clock periods

elapse for every one SCLK period. If the timer registers are

loaded with the value 803, 100.5 SCLKs occur between inter-

rupts and subsequently between transmit instructions. This

situation results in nonequidistant sampling, because the

transmit instruction occurs on an SCLK edge. If the number

of SCLKs between interrupts is a whole integer figure of N,

equidistant sampling is implemented by the DSP.

AD7441/

AD7451*

DSP56xxx*

SCLK

SRD

SR2

SCLK

SDATA

*ADDITIONAL PINS REMOVED FOR CLARITY.

03153-035

Figure 35. Interfacing to the DSP56xxx

AD7441/AD7451 to TMS320C5x/C54x

The serial interface on the TMS320C5x/C54x uses a continuous

serial clock and frame synchronization signals to synchronize

the data transfer operations with peripheral devices such as the

AD7441/AD7451. The CS input allows easy interfacing between

the TMS320C5x/C54x and the AD7441/AD7451 without any

glue logic required. The serial port of the TMS320C5x/C54x is

set up to operate in burst mode with internal CLKx (Tx serial

clock) and FSx (Tx frame sync). The serial port control register

(SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1,

and TXM = 1. The format bit, FO, can be set to 1 to set the word

length to eight bits in order to implement the power-down

mode on the AD7441/AD7451. The connection diagram is

shown in . Note that for signal processing applications,

the frame synchronization signal from the TMS320C5x/ C54x

must provide equidistant sampling.

Figure 34

AD7441/

AD7451*

TMS320C5x/

C54x*

CLKx

FSx

FSR

SCLK

SDATA

CLKR

*ADDITIONAL PINS REMOVED FOR CLARITY.

03153-034

Figure 34. Interfacing to the TMS320C5x/C54x

AD7441/AD7451

Rev. D | Page 22 of 24

GROUNDING AND LAYOUT HINTS

The printed circuit board that houses the AD7441/AD7451

must be designed so that the analog and digital sections are

separated and confined to certain areas of the board. This

facilitates the use of ground planes that can be easily separated.

A minimum etch technique is generally best for ground planes,

as it gives the best shielding. Digital and analog ground planes

must be joined in only one place: a star ground point estab-

lished as close to the GND pin on the AD7441/AD7451 as

possible.

Avoid running digital lines under the device, as this couples

noise onto the die. The analog ground plane must be allowed to

run under the AD7441/AD7451 to avoid noise coupling. The

power supply lines to the AD7441/AD7451 must use as large

a trace as possible to provide low impedance paths and reduce

the effects of glitches on the power supply line.

Fast switching signals like clocks must be shielded with digital

grounds to avoid radiating noise to other sections of the board,

and clock signals must never run near the analog inputs. Avoid

crossover of digital and analog signals. Traces on opposite sides

of the board must run at right angles to each other. This reduces

the effects of feedthrough on the board. A microstrip technique is

by far the best but is not always possible with a double-sided board.

In this technique, the component side of the board is dedicated

to ground planes while signals are placed on the solder side.

Good decoupling is also important. All analog supplies must

be decoupled with 10 μF tantalum capacitors in parallel with

0.1 μF capacitors to GND. To achieve the best from these

decoupling components, they must be placed as close as

possible to the device.

EVALUATING PERFORMANCE

The evaluation board package includes a fully assembled and

tested evaluation board, documentation, and software for con-

trolling the board from a PC via the evaluation board controller.

The evaluation board controller can be used in conjunction with

the AD7441 and the AD7451 evaluation boards, as well as with

many other Analog Devices, Inc. evaluation boards ending with

the CB designator, to demonstrate and evaluate the ac and dc

performance of the AD7441 and the AD7451.

The software allows the user to perform ac (fast Fourier transform)

and dc (histogram of codes) tests on the AD7441/AD7451. See

the AD7441/AD7451 application note that accompanies the

evaluation kit for more information.

AD7441/AD7451

Rev. D | Page 23 of 24

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-178-BA

121608-A

8°

4°

0°

SEATING

PLANE

1.95

BSC

0.65 BSC

0.60

BSC

1234

3.00

2.90

2.80

3.00

2.80

2.60

1.70

1.60

1.50

1.30

1.15

0.90

.15 MAX

.05 MIN

1.45 MAX

0.95 MIN

0.22 MAX

0.08 MIN

0.38 MAX

0.22 MIN

0.60

0.45

0.30

PIN 1

INDICATOR

Figure 36. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-187-AA

100709-B

6°

0°

0.80

0.55

0.40

0.65 BSC

0.40

0.25

1.10 MAX

3.20

3.00

2.80

COPLANARITY

0.10

0.23

0.09

3.20

3.00

2.80

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

Figure 37. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

AD7441/AD7451

Rev. D | Page 24 of 24

ORDERING GUIDE

Model1 Temperature Range Linearity Error (LSB)2 Package Description Package Option Branding

AD7451ARTZ-REEL7 −40°C to +85°C ± 1.5 8-Lead SOT-23 RJ-8 C3T

AD7451ARMZ −40°C to +85°C ± 1.5 8-Lead MSOP RM-8 C3T

AD7451BRMZ −40°C to +85°C ± 1 8-Lead MSOP RM-8 C3U

AD7441BRTZ-R2 −40°C to +85°C ± 0.5 8-Lead SOT-23 RJ-8 C4M

AD7441BRTZ-REEL7 −40°C to +85°C ± 0.5 8-Lead SOT-23 RJ-8 C4M

AD7441BRMZ −40°C to +85°C ± 0.5 8-Lead MSOP RM-8 C4M

EVAL-AD7451CBZ3 Evaluation Board

EVAL-CONTROL BRD24 Controller Board

1 Z = RoHS Compliant Part.

2 Linearity error here refers to integral nonlinearity error.

3 This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.

4 The evaluation board controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

To order a complete evaluation kit, you must order the ADC evaluation board (EVAL-AD7451CB or EVAL-AD7441CB), the EVAL-CONTROL BRD2, and a 12 V ac

transformer. See the AD7451/AD7441 application note that accompanies the evaluation kit for more information.

registered trademarks are the property of their respective owners.

D03153-0-3/10(D)