XCR3032XL-7CSG48C - Xilinx, Inc.

DS012 (v2.5) May 26, 2009 www.xilinx.com 1

Product Specification

countries. All other trademarks are the property of their respective owners.

Features

• Fast Zero Power (FZP) design technique provides

ultra-low power and very high speed

- Typical Standby Current of 17 to 18 μA at 25°C

• Innovative CoolRunner™ XPLA3 architecture

combines high speed with extreme flexibility

• Based on industry's first TotalCMOS PLD — both

CMOS design and process technologies

• Advanced 0.35μ five layer metal EEPROM process

- 1,000 erase/program cycles guaranteed

- 20 years data retention guaranteed

• 3V, In-System Programmable (ISP) using JTAG IEEE

1149.1 interface

- Full Boundary-Scan Test (IEEE 1149.1)

- Fast programming times

• Support for complex asynchronous clocking

- 16 product term clocks and four local control term

clocks per function block

- Four global clocks and one universal control term

clock per device

• Excellent pin retention during design changes

• Available in commercial grade and extended voltage

(2.7V to 3.6V) industrial grade

• 5V tolerant I/O pins

• Input register setup time of 2.5 ns

• Single pass logic expandable to 48 product terms

• High-speed pin-to-pin delays of 5.0 ns

• Slew rate control per output

• 100% routable

• Security bit prevents unauthorized access

• Supports hot-plugging capability

• Design entry/verification using Xilinx or industry

standard CAE tools

• Innovative Control Term structure provides:

- Asynchronous macrocell clocking

- Asynchronous macrocell register preset/reset

- Clock enable control per macrocell

• Four output enable controls per function block

• Foldback NAND for synthesis optimization

• Universal 3-state which facilitates "bed of nails" testing

• Available in Chip-scale BGA, Fineline BGA, and QFP

packages. Pb-free available for most package types.

See Xilinx Packaging for more information.

CoolRunner XPLA3 CPLD

DS012 (v2.5) May 26, 2009 014

Product Specification

Table 1: CoolRunner XPLA3 Device Family

XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL

Macrocells 32 64 128 256 384 512

Usable Gates 750 1,500 3,000 6,000 9,000 12,000

Registers 32 64 128 256 384 512

TPD (ns) 4.55.55.57.07.07.0

TSU (ns) 3.0 3.5 3.5 4.3 4.3 3.8

TCO (ns) 3.5 4 4 4.5 4.5 5.0

Fsystem (MHz) 213 192 175 154 135 135

ICCSB (μA) 17 17 17 18 18 18

Table 2: CoolRunner XPLA3 Packages and User I/O Pins

XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL

44-pin VQFP 36 36 - - - -

48-pin 0.8mm CSP 36 40 - - - -

56-pin 0.5mm CSP - 48 - - - -

100-pin VQFP - 68 84 - - -

144-pin 0.8mm CSP - - 108 - - -

144-pin TQFP - - 108 120 118(1) -

208-pin PQFP - - - 164 172 180

256-pin Fineline BGA - - - 164 212 212

280-pin 0.8mm CSP - - - 164 - -

324-pin Fineline BGA - - - - 220 260

1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the CoolRunner XPLA3 family in the TQ144 package.

2. Most packages are available in Pb-Free option. See individual data sheets for more details.

3. The 44-pin PLCC package is discontinued per XCN07022.

CoolRunner XPLA3 CPLD

2www.xilinx.com DS012 (v2.5) May 26, 2009

Product Specification

Family Overview

The CoolRunner XPLA3 (eXtended Programmable Logic

Array) family of CPLDs is targeted for low power systems

that include portable, handheld, and power sensitive appli-

cations. Each member of the CoolRunner XPLA3 family

includes Fast Zero Power (FZP) design technology that

combines low power and high speed. With this design tech-

nique, the CoolRunner XPLA3 family offers true pin-to-pin

speeds of 5.0 ns, while simultaneously delivering power

that is less than 56 μW at standby without the need for

"turbo bits" or other power down schemes. By replacing

conventional sense amplifier methods for implementing

product terms (a technique that has been used in PLDs

since the bipolar era) with a cascaded chain of pure CMOS

gates, the dynamic power is also substantially lower than

any other CPLD. CoolRunner devices are the only TotalC-

MOS PLDs, as they use both a CMOS process technology

and the patented full CMOS FZP design technique. The

FZP design technique combines fast nonvolatile memory

cells with ultra-low power SRAM shadow memory to deliver

the industry’s lowest power 3.3V CPLD family.

The CoolRunner XPLA3 family employs a full PLA structure

for logic allocation within a function block. The PLA provides

maximum flexibility and logic density, with superior pin lock-

ing capability, while maintaining deterministic timing.

CoolRunner XPLA3 CPLDs are supported by

Xilinx® WebPACK™ software and industry standard CAE

tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys,

Viewlogic, and Synplicity), using HDL editors with ABEL,

VHDL, and Verilog, and/or schematic capture design entry.

Design verification uses industry standard simulators for

functional and timing simulation. Development is supported

on multiple personal computer (PC), Sun, and HP plat-

forms.

The CoolRunner XPLA3 family features also include the

industry-standard, IEEE 1149.1, JTAG interface through

which boundary-scan testing, In-System Programming

(ISP), and reprogramming of the device can occur. The

CoolRunner XPLA3 CPLD is electrically reprogrammable

using industry standard device programmers.

CoolRunner XPLA3 Architecture

Figure 1 shows a high-level block diagram of a 128 macro-

cell device implementing the CoolRunner XPLA3 architec-

ture. The CoolRunner XPLA3 architecture consists of

function blocks that are interconnected by a Zero-power

Interconnect Array (ZIA). The ZIA is a virtual crosspoint

switch. Each function block has 40 inputs from the ZIA and

contains 16 macrocells.

From this point of view, this architecture looks like many

other CPLD architectures. What makes the CoolRunner

XPLA3 family unique is logic allocation inside each function

block, and the design technique used to implement product

terms.

Function Block Architecture

Figure 3 illustrates the function block architecture. Each

function block contains a PLA array that generates control

terms, clock terms, and logic cells. A PLA differs from a PAL

in that the PLA has a fully programmable AND array fol-

lowed by a fully programmable OR array. A PAL array has a

fixed OR array, limiting flexibility. Refer to Figure 2 for an

example of a PAL and a PLA array. The PLA array receives

its inputs directly from the ZIA. There are 40 pairs of true

and complement inputs from the ZIA that feed the 48 prod-

uct terms in the array. Within the 48 P-terms there are eight

local control terms (LCT[0:7]) available as control signals to

each macrocell for use as asynchronous clocks, resets, pre-

sets and output enables. If not needed as control terms,

these P-Terms can join the other 40 P-Terms as additional

logic resources.

In each function block there are eight foldback NAND prod-

uct terms that can be used to synthesize increased logic

density in support of wider logic equations. This feature can

be disabled in software by the user. As with unused control

P-Terms, unused foldback NAND P-Terms can be used as

additional logic resources.

Sixteen high-speed P-Terms are available at each macro-

cell for speed critical logic. If wider than a single P-Term

logic is required at a macrocell, 47 additional P-Terms can

be summed in prior to the VFM (Variable Function Multi-

plexer). The VFM increases logic optimization by imple-

menting some two input logic functions before entering the

macrocell (see Figure 4).

Each macrocell can support combinatorial or registered

logic. The macrocell register accommodates asynchronous

presets and resets, and "power on" initial state. A hardware

clock enable is also provided for either D or T type registers,

and the register clock input is used as a latch enable when

the macrocell register is configured as a latch function.

CoolRunner XPLA3 CPLD

DS012 (v2.5) May 26, 2009 www.xilinx.com 3

Product Specification

Figure 1: Xilinx XPLA3 CPLD Architecture

Figure 2: PLA and PAL Array Example

FUNCTION

BLOCK

FUNCTION

BLOCK

I/O 40

MC1

MC2

MC16

I/O

MC1

MC2

MC16

FUNCTION

BLOCK

FUNCTION

BLOCK

I/O 40

MC1

MC2

MC16

I/O

MC1

MC2

MC16

FUNCTION

BLOCK

FUNCTION

BLOCK

I/O 40

MC1

MC2

MC16

I/O

MC1

MC2

MC16

FUNCTION

BLOCK

FUNCTION

BLOCK

I/O 40

MC1

MC2

MC16

I/O

MC1

MC2

MC16

DS012_01_112000

ZIA

Inputs

DS012_08_020601

PLA Array

PAL Array

Outputs

CoolRunner XPLA3 CPLD

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Product Specification

Macrocell Architecture

Figure 5 shows the architecture of the macrocell used in the

CoolRunner XPLA3 CPLD. Any macrocell can be reset or

preset on power-up. Each macrocell register can be config-

ured as a D-, T-, or Latch-type flip-flop, or bypassed if the

macrocell is required as a combinatorial logic function.

Each of these flip-flops can be clocked from any one of eight

sources or their complements. There are two global syn-

chronous clocks that are selected from the four external

clock pins. There is one universal clock signal. The clock

input signals CT[4:7] (Local Control Terms) can be individu-

ally configured as either a PRODUCT term or SUM term

equation created from the 40 signals available inside the

function block.

There are two muxed paths to the ZIA. One mux selects

from either the output of the VFM or the output of the regis-

ter. The other mux selects from the output of the register or

from the I/O pad of the macrocell. When the I/O pin is used

as an output, the output buffer is enabled, and the macrocell

feedback path can be used to feed back the logic imple-

mented in the macrocell. When an I/O pin is used as an

input, the output buffer is 3-stated and the input signal is fed

into the ZIA via the I/O feedback path. The logic imple-

Figure 3: Xilinx CoolRunner XPLA3 Function Block Architecture

Figure 4: Variable Function Multiplexer

Foldback NAND

(PT[8:15])

(PT[0:47])

(PT0)

(PT7)

(PT[32:47])

(PT16)

(PT[0:47])

(PT31)

To Local Control Term (LCT0)

To Universal Control Term (UCT) Mux

To Local Control Term (LCT7)

P-term Clocks

Product

Term

Array

40 x 48

ZIA

VFM

Macrocell 1

DQI/O1

ZIA

I/O16

VFM

Macrocell 16

DS012_02_101200

From PLA OR Term

To Combinatorial Path

and Register Input

From P-term

DS012_03_121699

CoolRunner XPLA3 CPLD

DS012 (v2.5) May 26, 2009 www.xilinx.com 5

Product Specification

mented in the buried macrocell can be fed back to the ZIA

via the macrocell feedback path.

If a macrocell pin is configured as a registered input, there is

a direct path to the register to provide a fast input setup

time. If the macrocell is configured as a latch, the register

clock input functions as the latch enable, with the latch

transparent when this signal is High. The hardwired clock

enable is non-functional when the macrocell is configured

as a latch.

I/O Cell

The OE (Output Enable) multiplexer has eight possible

modes (Figure 6). When the I/O Cell is configured as an

input (or 3-stated output), a half latch feature exists. This

half latch pulls the input High (through a weak pull-up) if the

input should float and cross the threshold. This protects the

input from staying in the linear region and causing an

increased amount of power consumption. This same weak

pull-up can be enabled in software such that it is always on

when the I/O Cell is configured as an input. This weak pull

up is automatically turned on when a pin is unused by the

design.

The I/O Cell is 5V tolerant when the device is powered.

Each output has independent slew rate control (fast or slow)

which assists in reducing EMI emissions.

See individual device data sheets for 3.3V PCI electrical

specification compatibility.

Note that an I/O macrocell used as buried logic that does

not have the I/O pin used for input is considered to be

unused, and the weak pull-up resistors will be turned on. It

is recommended that any unused I/O pins on the CoolRun-

ner XPLA3 family of CPLDs be left unconnected. Dedicated

input pins (CLKx/INx) do not have on-chip weak pull-up

resistors; therefore unused dedicated input pins must have

external termination. As with all CMOS devices, do not

allow inputs to float.

Figure 5: XPLA3 Macrocell Architecture

Global CLK

Universal CLK

P-term CLK

CT [4:7]

ds012_05_122299

Universal PST

CT [0:5]

Universal RST

CT [0:5]

To ZIA

To I/O

PAD

Note: Global CLK signals come from pins.

To ZIA

VFM

RST

PST

D/T/L

CLKEn

CT4

P-term

PLA OR Term

From PT Array

Figure 6: I/O Cell

GND (Weak P.U.)

VCC

Universal OE

GND

OE [2:0]

To Macrocell / ZIA

From Macrocell I/O Pin

Slew

Control

Decode

I/O Pin

State

3-State

Function CT0

Function CT1

Function CT2

Function CT6

Universal OE

Enable

Weak P.U.

ds012_06_121699

Weak Pull-up

OE = 7

VCC

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Product Specification

Power-Up Characteristics

During power-up, the CoolRunner XPLA3 device I/Os may

be undefined until VCC rises above 1.0V. This time period is

called the Subthreshold State, as transistors have not yet

fully been turned on. When VCC rises above 1.0V, the

device I/Os enter the Quiescent State, and I/Os are dis-

abled with weak pull-ups as shown in Ta b l e 3 . When VCC

reaches the threshold of the User Operation State (approx-

imately 2.1V), user registers are initialized (typically within

200 μs) after which I/Os assume the behavior determined

by the user pattern, as shown in Figure 7.

If the device is in the erased state (before any user pattern

is programmed), the device outputs remain disabled with

weak pull-ups. The JTAG pins are enabled to allow the

device to be programmed at any time. All devices are

shipped in the erased state from the factory.

If the device is programmed, the device inputs and outputs

take on their configured states for normal operation.

Security

Designs can be secured during programming to prevent

pattern theft via readback. This security setting does not

protect readback of the Usercode/signature space, which is

often used for storing application serial numbers or revision

codes. The only way to clear the security setting is to com-

pletely erase the entire device.

Timing Model

The CoolRunner XPLA3 architecture follows a timing model

that allows deterministic timing in design and redesign. The

basic timing model is shown in Figure 8. There is a fast path

(TLOGI1) into the macrocell which is used if there is a single

product term. The TLOGI2 path is used for multiple product

term timing. For optimization of logic, the CoolRunner

XPLA3 CPLD architecture includes a Foldback NAND path

(TLOGI3). There is a fast input path to each macrocell if used

as an Input Register (TFIN). The CoolRunner XPLA3 archi-

tecture also includes universal control terms (TUDA) that can

be used for synchronization of the macrocell registers in dif-

ferent function blocks. There is slew rate control and output

enable control on a per macrocell basis.

Figure 7: Device Behavior During Power Up

VCC

Power

3.8 V

(Typ)

Power

Quiescent

State

Quiescent

State

User Operation State

Initialization of User Registers

DS012_12_082707

2.1V

1.6V

(Typ)

Subthreshold

State

1.0V

Tabl e 3 : I/O Power-Up Characteristics

Device Circuitry Subthreshold State Quiescent State Erased Device Operation Valid User Operation

Device I/Os Undetermined Disabled with Weak

Pull-up

Disabled with Weak

Pull-up As Configured

Device

Inputs/Clocks Undetermined High-Z High-Z High-Z

JTAG Controller Undetermined Disabled with Weak

Pull-up Enabled As Configured

CoolRunner XPLA3 CPLD

DS012 (v2.5) May 26, 2009 www.xilinx.com 7

Product Specification

JTAG Testing Capability

JTAG is the commonly used acronym for the Boundary

Scan Test (BST) feature defined for integrated circuits by

IEEE Standard 1149.1. This standard defines input/output

pins, logic control functions, and commands that facilitate

both board and device level testing without the use of spe-

cialized test equipment. CoolRunner XPLA3 devices use

the JTAG Interface for In-System Programming/Reprogram-

ming. The JTAG command set is implemented as described

in Ta b l e 4 .

As implemented in CoolRunner XPLA3 CPLDs, the JTAG

Port includes four of the five pins (refer to Ta b l e 5 ) described

in the JTAG specification: TCK, TMS, TDI, and TDO. The

fifth signal defined by the JTAG specification is TRST (Test

Reset). TRST is considered an optional signal, since it is

not actually required to perform BST or ISP. The CoolRun-

ner XPLA3 CPLD saves an I/O pin for general purpose use

by not implementing the optional TRST signal in the JTAG

interface. Instead, the CoolRunner XPLA3 CPLD supports

the test reset functionality through the use of its power-up

reset circuit.

Port Enable Pin

The Port Enable pin is used to reclaim TMS, TDO, TDI, and

TCK for JTAG ISP programming if the user has defined

these pins as general purpose I/O during device program-

ming. For ease of use, CoolRunner XPLA3 devices are

shipped with the JTAG port pins enabled. The Port Enable

pin must be a low logic level during the power-up sequence

for the device to operate properly.

During device programming, the JTAG ISP pins can be left

as is or reconfigured as user specific I/O pins. If the JTAG

ISP pins have been used for I/O pins, simply applying a high

logic level to the Port Enable pin converts the JTAG ISP pins

back to their respective programming function and the

device can be reprogrammed via ISP. After completing the

desired JTAG ISP programming function, simply return Port

Enable to Ground to re-establish the JTAG ISP pins to their

respective I/O function. Reconfiguring the JTAG port pins as

I/Os makes these pins non-JTAG ISP functional until

reclaimed by port enable.

If the JTAG pins are not required as I/O, port enable should

be permanently tied to GND. Pins associated with the JTAG

port have internal weak pull ups enabled to terminate the

pins. However, in noisy environments, external 10K pull ups

are recommended.

The CoolRunner XPLA3 family allows the macrocells asso-

ciated with these pins to be used as buried logic when the

JTAG/ISP function is enabled.

Figure 8: XPLA3 Timing Model

TIN

TOUT

TEN

TSLEW

TLOGI1,2

TPTCK

DLT Q

S/R

TLOGI3

TFIN

TGCK TUDA

DS017_02_031802

CoolRunner XPLA3 CPLD

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Product Specification

3V, In-System Programming (ISP)

CoolRunner XPLA3 CPLDs allow for 3V, in-system pro-

gramming/reprogramming of its EEPROM cells via a JTAG

interface. An on-chip charge pump eliminates the need for

externally provided super-voltages. This allows program-

ming on the circuit board using only the 3V supply required

by the device for normal operation. The ISP commands

implemented in CoolRunner XPLA3 CPLDs are specified in

Table 6.

Tabl e 4 : XPLA3 Low-level JTAG Boundary-scan Commands

Instruction

(Instruction

Code)

Sample/Preload

(00010)

Boundary-scan

The mandatory Sample/Preload instruction allows a snapshot of the normal operation of the

component to be taken and examined. It also allows data values to be loaded into the latched parallel

outputs of the Boundary-scan Shift Register prior to selection of the other boundary-scan test

instructions.

Extest

(00000)

Boundary-scan

The mandatory Extest instruction allows testing of off-chip circuitry and board level interconnections.

Data is typically loaded onto the latched parallel outputs of Boundary-scan Shift Register using the

Sample/Preload instruction prior to selection of the Extest instruction.

Bypass

(11111)

Bypass Register

Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass

synchronously through the selected device to adjacent devices during normal device operation. The

Bypass instruction can be entered by holding TDI at a constant High value and completing an

Instruction-scan cycle.

Idcode

(00001)

Boundary-scan

Selects the Idcode register and places it between TDI and TDO, allowing the Idcode to be serially

shifted out of TDO. The Idcode instruction permits blind interrogation of the components assembled

onto a printed circuit board. Thus, in circumstances where the component population can vary, it is

possible to determine what components exist in a product.

High-Z

(00101)

Bypass Register

The High-Z instruction places the component in a state which all of its system logic outputs are placed

in an inactive drive state (e.g., high impedance). In this state, an in-circuit test system can drive

signals onto the connections normally driven by a component output without incurring the risk of

damage to the component. The High-Z instruction also forces the Bypass Register between TDI and

TDO.

Intest

(00011)

Boundary-scan

The Intest instruction selects the boundary scan register prior to applying tests to the logic core of the

device. This permits testing of on-chip system logic while the component is already on the board.

Tabl e 5 : JTAG Pin Description

Pin Name Description

TCK Test Clock Input Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,

respectively.

TMS Test Mode Select Serial input pin selects the JTAG instruction mode. TMS should be driven High during

user mode operation.

TDI Test Data Input Serial input pin for instructions and test data. Data is shifted in on the rising edge of

TCK.

TDO Test Data Output Serial output pin for instructions and test data. Data is shifted out on the falling edge

of TCK. The signal is 3-stated if data is not being shifted out of the device.

CoolRunner XPLA3 CPLD

DS012 (v2.5) May 26, 2009 www.xilinx.com 9

Product Specification

JTAG and ISP Interfacing

A number of industry-established methods exist for

JTAG/ISP interfacing with CPLDs and other integrated cir-

cuits. The CoolRunner XPLA3 family supports the following

methods:

• Xilinx HW 130

• PC Parallel Port

• Workstation or PC Serial Port

• Embedded Processor

• Automated Test Equipment

• Third Party Programmers

• Xilinx ISP Programming Tools

Tabl e 6 : Low-level ISP Commands

Instruction

(Register Used)

Instruction

Code Description

Enable

(ISP Shift Register)

01001 Enables the Erase, Program, and Verify commands. Using the Enable instruction

before the Erase, Program, and Verify instructions allows the user to specify the

outputs of the device using the JTAG Boundary-Scan Sample/Preload command.

Erase

(ISP Shift Register)

01010 Erases the entire EEPROM array. User can define the outputs during this

operation by using the JTAG Sample/Preload command.

Program

(ISP Shift Register)

01011 Programs the data in the ISP Shift Register into the addressed EEPROM row. The

outputs can be defined by using the JTAG Sample/Preload command.

Disable

(ISP Shift Register)

10000 Allows the user to leave ISP mode. It selects the ISP register to be directly

connected between TDO and TDI.

Verify

(ISP Shift Register)

01100 Transfers the data from the addressed row to the ISP Shift Register. The data can

then be shifted out and compared with the JEDEC file. The user can define the

outputs during this operation.

CoolRunner XPLA3 CPLD

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Product Specification

Absolute Maximum Ratings

Tabl e 7 : Programming Specifications

Symbol Parameter Min. Max. Unit

DC Parameters

VCCP VCC supply program/verify 3.0 3.6 V

ICCP ICC limit program/verify(1) -30mA

VIH Input voltage (High) 2.0 - V

VIL Input voltage (Low) - 0.8 V

VOL Output voltage (Low) - 0.4 V

VOH Output voltage (High) 2.4 - V

AC Parameters

FMAX TCK maximum frequency - 10 MHz

PWE Pulse width erase 100 - ms

PWP Pulse width program 10 - ms

PWV Pulse width verify 10 - μs

TINIT Initialization time(1) -200μs

TMS_SU TMS setup time before TCK ↑10 - ns

TDI_SU TDI setup time before TCK ↑10 - ns

TMS_H TMS hold time after TCK ↑20 - ns

TDI_H TDI hold time after TCK ↑20 - ns

TDO_CO TDO valid after TCK ↓-30ns

Notes:

1. Family specification. See individual device data sheets for specific device measurements.

Symbol Parameter(1) Min. Max. Unit

VCC Supply voltage(2) relative to GND –0.5 4.0 V

VIInput voltage(3) relative to GND –0.5 5.5(4) V

IOUT Output current, per pin –100 100 mA

TJMaximum junction temperature –40 150 °C

TSTR Storage temperature –65 150 °C

Notes:

1. Stresses above those listed might cause malfunction or permanent damage to the device. This is a stress rating only. Functional

operation at these or any other condition above those indicated in the operational and programming specification is not implied.

2. The chip supply voltage must rise monotonically.

3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins can undershoot to –2.0V or overshoot to 7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing

current being limited to 200 mA.

4. External I/O voltage must not exceed VCC by 4.0V.

CoolRunner XPLA3 CPLD

DS012 (v2.5) May 26, 2009 www.xilinx.com 11

Product Specification

Recommended Operation Conditions

Quality and Reliability Characteristics

Additional Information

CoolRunner XPLA3 CPLD Data Sheets and Application

Notes

Device Packages

Device Package User Guide

Symbol Parameter Test Conditions Min. Max. Unit

VCC Supply voltage Commercial TA = 0°C to 70°C 3.0 3.6 V

Industrial TA = –40°C to +85°C 2.7 3.6 V

VIL Low-level input voltage 0 0.8 V

VIH High-level input voltage 2.0 5.5 V

VOOutput voltage 0 VCC V

TRInput rise time - 20 ns

TFInput fall time - 20 ns

Symbol Parameter Min Max Units

TDR Data retention 20 - Years

NPE Program/erase cycles (Endurance) MOSIV devices 1,000 - Cycles

NPE Program/erase cycles (Endurance) UMC devices 10,000 - Cycles

VESD Electrostatic Discharge (ESD) 2,000 - Volts

CoolRunner XPLA3 CPLD

12 www.xilinx.com DS012 (v2.5) May 26, 2009

Product Specification

Revision History

The following table shows the revision history for this document.

Notice of Disclaimer

THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND

CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED

WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE

SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE

PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES

THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO

APPLICABLE LAWS AND REGULATIONS.

Date Version Revision

02/20/00 1.0 Initial Xilinx release.

03/06/00 1.1 Minor updates.

11/30/00 1.2 Updated Macrocell numbering, I/O pins, and available packages.

02/09/01 1.3 Updated specification.

04/11/01 1.4 Under Features, changed Global 3-state to Universal 3-state. Added XCR3512XL device;

changed TSU numbers, added 324-pin Fineline BGA package, Programming Specs:

changed TINIT from 50 min. to 50 max., Quality & Rel. specs: added NPE for UMC

devices—10,000 cycles.

01/07/02 1.5 Table 7: Added Note 1, changed TINIT from 50 to 200 (max). Changed ICCP from 20 to 30

(max); updated Device Family Ta b le 1 usable gate counts. Updated Device Family Ta bl e 2

package types, updated I/O cell section. Absolute Maximum Ratings table: Changed max

supply voltage relative to GND to 4.0V to match XC9500XL and UMC standard specs.

01/06/03 1.6 Added TPTCK parameter to timing model. Changed FSYSTEM for all devices in Tab l e 1 .

Changed from Advance Information to Preliminary. Added Note 1 to Figure 2 regarding

XCR3384XL TQ144 JTAG pins.

06/23/03 1.7 Added Power-Up Characteristics.

02/13/04 1.8 Added Maximum Soldering temperature (TSOL) specification. Added links.

09/29/04 1.9 Added text on shadow memory to first paragraph, page 2.

01/10/05 2.0 Changed Function Block input references to 40.

04/08/05 2.1 Add ICCSB Typical Specification

03/31/06 2.2 Added Warranty Disclaimer.

08/31/07 2.3 Added description of subthreshold power-up characteristics, page 6. Changes to Figure 7

and Table 3 on page 6 to describe subthreshold behavior. Add security description, page 6.

09/08/08 2.4 Removed PC44 and PCG44 packages. See Product Discontinuation Notice xcn07022.pdf.

05/26/09 2.5 Added note 3 to Ta b l e 2 .