DS1744/DS1744P Y2KC Nonvolatile Timekeeping www.dalsemi.com FEATURES PIN ASSIGNMENT Integrated NV SRAM, real time clock, crystal, power-fail control circuit and lithium energy source Clock registers are accessed identical to the static RAM. These registers are resident in the eight top RAM locations. Century byte register; ie., Y2K compliant Totally nonvolatile with over 10 years of operation in the absence of power BCD coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 Battery voltage level indicator flag Power-fail write protection allows for 10% V CC power supply tolerance Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time DIP Module only - Standard JEDEC Byte-wide 32k x 8 static RAM pinout PowerCap Module Board only - Surface mountable package for direct connection to PowerCap containing battery and crystal - Replaceable battery (PowerCap) - Power-On Reset Output - Pin for pin compatible with other densities of DS174XP Timekeeping RAM 1 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 28-PIN ENCAPSULATED PACKAGE (700 MIL EXTENDED) NC NC NC RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X1 GND VBAT X2 NC NC A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 34-PIN POWERCAP MODULE BOARD (USES DS9034PCX POWERCAP) of 18 111999 DS1744/DS1744P PIN DESCRIPTION A0-A14 CE OE WE V CC GND DQ0-DQ7 NC RST X1, X2 V BAT - - - - - - - - - Address Input Chip Enable Output Enable Write Enable Power Supply Input Ground Data Input/Output No Connection Power-on Reset Output(Power- Cap Module board only) - Crystal Connection - Battery Connection ORDERING INFORMATION DS1744P-XXX (5 Volt) -70 70 ns access -100 100 ns access blank 28-pin DIP Module P 34-pin PowerCap Module board* DS1744WP-XXX (3.3 Volt) -120 120 ns access -150 150 ns access blank 28-pin DIP Module P 34-pin PowerCap Module board* *DS9034PCX (PowerCap) Required: (must be ordered separately) DESCRIPTION The DS1744 is a full function, year 2000 compliant (Y2KC), real-time clock/calendar (RTC) and 32K x 8 non-volatile static RAM. User access to all registers within the DS1744 is accomplished with a bytewide interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24 hour BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1744 also contains its own power-fail circuitry which deselects the device when the V CC supply is in an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. 2 of 18 DS1744/DS1744P DS1746 BLOCK DIAGRAM Figure 1 PACKAGES The DS1744 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the Power-Cap to be mounted on top of the DS1744P after the completion of the surface mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. CLOCK OPERATIONS-READING THE CLOCK While the double buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1744 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a one is written into the read bit, bit 6 of the century register, see Table 2. As long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1744 registers are updated simultaneously after the internal clock register updating process has been reenabled. Updating is within a second after the read bit is written to zero. 3 of 18 DS1744/DS1744P DS1744TRUTH TABLE Table 1 VCC VCC>VPF VSO<VCC<VPF VCC<VSO CE OE WE MODE DQ POWER VIH VIL VIL VIL X X X X VIL VIH X X X VIL VIH VIH X X DESELECT WRITE READ READ DESELECT DESELECT HIGH-Z DATA IN DATA OUT HIGH-Z HIGH-Z HIGH-Z STANDBY ACTIVE ACTIVE ACTIVE CMOS STANDBY DATA RETENTION MODE SETTING THE CLOCK As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the read bit, halts updates to the DS1744 registers. The user can then load them with the correct day, date and time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual clock counters and allows normal operation to resume. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see Table 2. Setting it to a one stops the oscillator. FREQUENCY TEST BIT As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic "1" and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable). CLOCK ACCURACY (DIP MODULE) The DS1744 is guaranteed to keep time accuracy to within 1 minute per month at 25C. The clock is calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements. The DS1744 does not require additional calibration and temperature deviations will have a negligible effect in most applications. For this reason, methods of field clock calibration are not available and not necessary. CLOCK ACCURACY (POWERCAP MODULE) The DS1744P and DS9034PCX are each individually tested for accuracy. Once mounted together, the module is guaranteed to keep time accuracy to within 1.53 minutes per month (35 ppm) at 25C. 4 of 18 DS1744/DS1744P DS1744 REGISTER MAP Table 2 ADDRESS B7 7FFFF 7FFFE X 7FFFD X 7FFFC BF 7FFFB X 7FFFA X 7FFF9 OSC 7FFF8 W OSC = STOP BIT W = WRITE BIT B6 X X FT X R DATA B5 B4 B3 B2 B1 10 YEAR YEAR X 10 MO MONTH 10 DATE DATE X X X DAY 10 HOUR HOUR 10 MINUTES MINUTES 10 SECONDS SECONDS 10 CENTURY CENTURY R = READ BIT X = SEE NOTE BELOW B0 FUNCTION/RANGE YEAR 00-99 MONTH 01-12 DATE 01-31 DAY 01-07 HOUR 00-23 MINUTES 00-59 SECONDS 00-59 CENTURY 00-39 FT = FREQUENCY TEST BF = BATTERY FLAG NOTE: All indicated "X" bits are not dedicated to any particular function and can be used as normal RAM bits. RETRIEVING DATA FROM RAM OR CLOCK The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and states are not met, valid data will be available at the latter of chip enable access (tCEA ) or at output enable access time (tOEA ). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA , the data lines are driven to an intermediate state until tAA . If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH ) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1744 is in the write mode whenever WE, and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid t DS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. 5 of 18 DS1744/DS1744P DATA RETENTION MODE The 5 volt device is fully accessible and data can be written or read only when VCC is greater than VPF . However, when VCC is below the power fail point, VPF , (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. At this time the power fail reset output signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when VCC is greater than VPF . When VCC falls below the power fail point, VPF , access to the device is inhibited. At this time the power fail reset output signal (RST) is driven active and will remain active until VCC returns to nominal levels. If VPF is less than VBAT , the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF . If VPF is greater than VBAT , the device power is switched from VCC to the backup supply (VBAT ) when VCC drops below VBAT . RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and requires a pull up. Except for the RST, all control, data, and address signals must be powered down when VCC is powered down. BATTERY LONGEVITY The DS1744 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1744 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of VCC power. Each DS1744 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF , the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1744 will be much longer than 10 years since no lithium battery energy is consumed when VCC is present. BATTERY MONITOR The DS1744 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not writable and should always be a one when read. If a zero is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable. 6 of 18 DS1744/DS1744P ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +6.0V 0C to 70C -20C to +70C 260C for 10 seconds (See Note 7) * This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Logic 1 Voltage All Inputs VCC = 5V10% VCC = 3.3V10% Logic 0 Voltage All Inputs VCC = 5V10% VCC = 3.3V10% SYMBOL MIN VIH TYP MAX UNITS NOTES 2.2 VCC+0.3V V 1 VIH 2.0 VCC+0.3V V 1 VIL -0.3 0.8 V 1 VIL -0.3 0.6 V 1 DC ELECTRICAL CHARACTERISTICS =10%) PARAMETER Active Supply Current TTL Standby Current (CE = VIH) CMOS Standby Current (CE VCC-0.2V) Input Leakage Current (any input) Output Leakage Current (any output) Output Logic 1 Voltage (IOUT = -1.0 mA) Output Logic 0 Voltage (IOUT = +2.1 mA) Write Protection Voltage Battery Switch Over Voltage (0C to 70C) SYMBOL Icc MIN (0C to 70C; V CC = 5.0V TYP X MAX 75 UNITS mA NOTES 2,3 Icc1 X 6 mA 2,3 Icc2 X 4 mA 2,3 IIL -1 +1 A IOL -1 +1 A VOH 2.4 1 VOL VPF VSO 0.4 4.25 7 of 18 4.37 VBAT 4.50 1 V 1 1,4 DS1744/DS1744P DC ELECTRICAL CHARACTERISTICS PARAMETER Active Supply Current TTL Standby Current (CE = VIH) CMOS Standby Current (CE VCC-0.2V) Input Leakage Current (any input) Output Leakage Current (any output) Output Logic 1 Voltage (IOUT = -1.0 mA) Output Logic 0 Voltage (IOUT = +2.1 mA) Write Protection Voltage Battery Switch Over Voltage SYMBOL Icc (0C to 70C; V CC = 3.3V 10%) MIN TYP X MAX 30 UNITS mA NOTES 2,3 Icc1 X 2 mA 2,3 Icc2 X 2 mA 2,3 IIL -1 +1 A IOL -1 +1 A VOH 2.4 1 VOL 0.4 VPF 4.25 4.37 VBAT or VPF VSO READ CYCLE, AC CHARACTERISTICS PARAMETER SYMBOL 1 2.97 V 1 V 1,4 (0C to 70C; V CC = 5.0V 10%) 70 ns access MIN MAX 70 100 ns access MIN MAX 100 UNITS Read Cycle Time tRC Address Access Time tAA CE to DQ Low-Z tCEL CE Access Time tCEA 70 100 ns CE Data Off Time tCEZ 25 35 ns OE to DQ Low-Z tOEL OE Access Time tOEA 35 55 ns OE Data Off Time tOEZ 25 35 ns Output Hold from Address tOH 70 5 8 of 18 100 5 5 5 ns ns 5 5 ns ns ns NOTES DS1744/DS1744P READ CYCLE, AC CHARACTERISTICS PARAMETER Read Cycle Time Address Access Time CE to DQ Low-Z CE Access Time CE Data Off Time OE to DQ Low-Z OE Access Time OE Data Off Time Output Hold from Address SYMBOL tRC (0C to 70C; V CC = 3.3V 10%) 120 ns access MIN MAX 70 70 tAA tCEL 150 ns access MIN MAX 100 5 100 5 UNITS ns ns ns tCEA 70 100 ns tCEZ 25 35 ns tOEL 5 5 ns tOEA 35 55 ns tOEZ 25 35 ns tOH 5 READ CYCLE TIMING DIAGRAM 9 of 18 5 ns NOTES DS1744/DS1744P WRITE CYCLE, AC CHARACTERISTICS PARAMETER Write Cycle Time Address Setup Time SYMBOL tWC (0C to 70C; V CC = 5.0V 10%) 70 ns access MIN MAX 70 100 ns access MIN MAX 100 UNITS ns NOTES tAS 0 0 ns WE Pulse Width tWEW 50 70 ns CE Pulse Width tCEW 60 75 ns Data Setup Time tDS 30 40 ns Data Hold Time tDH1 0 0 ns 8 Data Hold Time tDH2 X X ns 9 Address Hold Time tAH1 5 5 ns 8 Address Hold Time tAH2 X X ns 9 WE Data Off Time tWEZ Write Recovery Time tWR 25 5 WRITE CYCLE, AC CHARACTERISTICS PARAMETER Write Cycle Time Address Setup Time SYMBOL tWC 35 5 ns ns (0C to 70C; V CC = 3.3V 10%) 120 ns access MIN MAX 120 150 ns access MIN MAX 150 UNITS ns NOTES tAS 0 0 ns WE Pulse Width tWEW 100 130 ns CE Pulse Width tCEW 110 140 ns CE and CE2 Pulse Width tCEW 110 140 ns Data Setup Time tDS 80 90 ns Data Hold Time tDH1 0 0 ns 8 Data Hold Time tDH2 X X ns 9 Address Hold Time tAH1 0 0 ns 8 Address Hold Time tAH2 X X ns 9 WE Data Off Time tWEZ Write Recovery Time tWR 40 10 10 of 18 50 10 ns ns DS1744/DS1744P WRITE CYCLE TIMING DIAGRAM, WRITE ENABLE CONTROLLED WRITE CYCLE TIMING DIAGRAM, CHIP ENABLE CONTROLLED 11 of 18 DS1744/DS1744P (0C to 70C; V CC = 5.0V =10%) POWER-UP/DOWN AC CHARACTERISTICS PARAMETER CE or WE at VH Before Power-down VCC Fall Time: VPF(MAX) to VPF(Min) VCC Fall Time: VPF(MIN) to VSO VCC Rise Time: VPF(MIN) to VPF(MAX) Power-up Recover Time Expected Data Retention Time (Oscillator ON) SYMBOL tPD MIN 0 tF 300 s tFB tR 10 0 s s tREC tDR TYP 35 10 POWER-UP/POWER-DOWN TIMING 5 VOLT DEVICE 12 of 18 MAX UNITS s ms years NOTES 5,6 DS1744/DS1744P POWER-UP/DOWN CHARACTERISTICS PARAMETER CE or WE at VH, Before Power-down VCC Fall Time: VPF(MAX) to VPF(Min) VCC Rise Time: VPF(MIN) to VPF(MAX) (0C to 70C; V CC = 3.3V 10%) SYMBOL tPD MIN 0 tF 300 s tR 0 s VPF to RST High tREC Expected Data Retention Time (Oscillator ON) tDR TYP MAX 35 10 UNITS s NOTES ms years 5,6 POWER-UP/DOWN WAVEFORM TIMING 3.3 VOLT DEVICE CAPACITANCE PARAMETER Capacitance on all input pins Capacitance on all output pins (t A = 25C) SYMBOL CIN CO MIN 13 of 18 TYP MAX 7 10 UNITS pF pF NOTES DS1744/DS1744P AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0 Volts Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ns NOTES: 1. Voltages are referenced to ground. 2. Typical values are at 25C and nominal supplies. 3. Outputs are open. 4. Battery switch over occurs at the lower of either the battery terminal voltage or VPF . 5. Data retention time is at 25C. 6. Each DS1744 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined for DIP modules and assembled PowerCap modules as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 7. Real-Time Clock Modules (DIP) can be successfully processed through conventional wave- soldering tecniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85C. Post solder cleaning with water washing techniques is acceptable, provided that ultra-sonic vibration is not used. In addition, for the PowerCap: a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up ("live - bug"). b. Hand Soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. 8. tAH1 , tDH1 are measured from WE going high. 9. tAH2 , tDH2 are measured from CE going high. 14 of 18 DS1744/DS1744P DS1744 28-PIN PACKAGE PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 28-PIN MIN MAX 1.470 1.490 37.34 37.85 0.675 0.740 17.75 18.80 0.335 0.355 8.51 9.02 0.075 0.105 1.91 2.67 0.015 0.030 0.38 0.76 0.140 0.180 3.56 4.57 0.090 0.110 2.29 2.79 0.590 0.630 14.99 16.00 0.010 0.018 0.25 0.45 0.015 0.025 0.43 0.58 15 of 18 DS1744/DS1744P DS1746P PKG DIM A B C D E F G MIN 0.920 0.980 0.052 0.048 0.015 0.025 INCHES NOM 0.925 0.985 0.055 0.050 0.020 0.027 MAX 0.930 0.990 0.080 0.058 0.052 0.025 0.030 NOTE: Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up ("live - bug"). Hand Soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. 16 of 18 DS1744/DS1744P DS1744P WITH DS9034PCX ATTACHED PKG DIM A B C D E F G MIN 0.920 0.955 0.240 0.052 0.048 0.015 0.020 INCHES NOM 0.925 0.960 0.245 0.055 0.050 0.020 0.025 MAX 0.930 0.965 0.250 0.058 0.052 0.025 0.030 COMPONENTS AND PLACEMENT MAY VARY FROM EACH DEVICE 17 of 18 DS1744/DS1744P RECOMMENDED POWERCAP MODULE LAND PATTERN PKG DIM A B C D E 18 of 18 INCHES MIN NOM 1.050 0.826 0.050 0.030 0.112 MAX -