DS1744/DS1744P
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DS1744 REGISTER MAP Table 2 DATA
ADDRESS B7 B6 B5 B4 B3 B2 B1 B0FUNCTION/RANGE
7FFFF 10 YEAR YEAR YEAR 00-99
7FFFE X X X 10 MO MONTH MONTH 01-12
7FFFD X X 10 DATE DATE DATE 01-31
7FFFC BF FT X X X DAY DAY 01-07
7FFFB X X 10 HOUR HOUR HOUR 00-23
7FFFA X 10 MINUTES MINUTES MINUTES 00-59
7FFF9 OSC 10 SECONDS SECONDS SECONDS 00-59
7FFF8 W R 10 CENTURY CENTURY CENTURY 00-39
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING D ATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable ) is high, and CE
(chip enable) is low. The device architect ure allows ripple-throu gh access to any of the addr ess locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip enable access (tCEA ) or at output enable
access time (tOEA ). The state of the data input/output pins (DQ) is controlled b y CE and OE. If the outputs
are activated before tAA , the data lines are driven to an intermediate state until tAA . If the address inputs
are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH )
but will then go indeterminate until the next address access.
WRITING DAT A TO RAM OR CLOCK
The DS1744 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid t DS prior to the end of write and remain valid for tDH afterward. In a
typical application, the OE si gnal will be high during a write cycle. Howev er, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the outputs tWEZ after WE goes active.