DS1744W-150 - Maxim Integrated Products, Inc.

1 of 18 111999

FEATURES

 Integrated NV SRAM, real time clock,

crystal, power-fail control circuit and lithium

energy source

 Clock registers are accessed identical to the

static RAM. These registers are resident in the

eight top RAM locations.

 Century byte register; ie., Y2K compliant

 Totally nonvolatile with over 10 years of

operation in the absence of power

 BCD coded century, year, month, date, day,

hours, minutes, and seconds with automatic

leap year compensation valid up to the year

2100

 Battery voltage level indicator flag

 Power-fail write protection allows for ±10%

V CC power supply tolerance

 Lithium energy source is electrically

disconnected to retain freshness until power is

applied for the first time

 DIP Module only

- Standard JEDEC Byte-wide 32k x 8

static RAM pinout

 PowerCap Module Board only

- Surface mountable package for direct

connection to PowerCap containing

battery and crystal

- Replaceable battery (PowerCap)

- Power-On Reset Output

- Pin for pin compatible with other densities

of DS174XP Timekeeping RAM

PIN ASSIGNMENT

DS1744/DS1744P

Y2KC Nonvolatile Timekeeping

www.dalsemi.com

NC 2

RST

VCC

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

34 NC

X1 GND VBAT X2

34-PIN P OWERCAP MODULE BOARD

(USES DS9034PCX POWERCAP)

VCC

DQ7

DQ6

DQ5

DQ4

DQ3

A14

A12

DQ0

DQ1

DQ2

GND

28-PIN ENCAPSULATED PACKAGE

(

700 MIL EXTENDED

)

DS1744/DS1744P

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PIN DESCRIPTION

A0–A14 – Address Input

CE – Chip Enable

OE – Output Enable

WE – Write Enable

V CC – Power Supply Input

GND – Ground

DQ0–DQ7 – Data Input/Output

NC – No Connection

RST – Power–on Reset Output(Power–

Cap Module board only)

X1, X2 – Crystal Connection

V BAT – Battery Connection

ORDERING INFORMATION

DS1744P–XXX (5 Volt)

-70 70 ns access

-100 100 ns access

blank 28-pin DIP Module

P 34-pin PowerCap Module board*

DS1744WP-XXX (3.3 Volt)

-120 120 ns access

-150 150 ns access

blank 28-pin DIP Module

P 34-pin PowerCap Module

board*

*DS9034PCX (PowerCap) Required:

(must be ordered separately)

DESCRIPTION

The DS1744 is a full function, year 2000 compliant (Y2KC), real–time clo ck/calendar (RTC) and 32K x

8 non–volatile static RAM. User access to all registers within the DS1744 is accomplished with a

bytewide interface as shown in Figure 1. The Real Time Clock (RTC ) information and cont rol bits reside

in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, da y, hours,

minutes, and seconds data in 24 hour BCD format. Corrections for the date of each month and leap year

are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data

that can occur during clock update cycles. The double buffered system also prevents time loss as the

timekeeping countdown continues unabated by access to time register data. Th e DS1744 also contains its

own power–fail circuitry which deselects the device when the V CC supply is in an out of tolerance

condition. This feature prevents loss of data from unpredictable s ystem operation brought on by low VCC

as errant access and update cycles are avoided.

DS1744/DS1744P

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DS1746 BLOCK DIAGRAM Figure 1

PACKAGES

The DS1744 is available in two packages (28–pin DIP and 34–pin PowerCap module). The 28–pin DIP

style module integrates the crystal, lithium energy source, and silicon all in one package. The 34–pin

PowerCap Module Board is designed with contacts for conne ction to a separa te PowerC ap (DS9034PCX)

that contains the crystal and battery. This design allows the Power-Cap to be mounted on top of the

DS1744P after the completion of the surface mount process. Mounting the PowerCap after the surface

mount process prevents damage to the crystal and battery due to the hi gh tempe ratures requir ed for solde r

reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap

are ordered separately and shipped in separate containers. The part number for the PowerCap is

DS9034PCX.

CLOCK OPERATIONS-READING THE CLOCK

While the double buffered register structure reduc es the chance o f readin g incorrect data, internal updates

to the DS1744 clock registers should be halted before clock data is read to prevent reading of data in

transition. However, halting the internal clock register updating process does not affect clock accuracy.

Updating is halted when a one is written into the read bit, bit 6 of the century register, see Table 2. As

long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the

count, that is day, date, and time that was current at the moment the halt command was issued. However,

the internal clock registers of the doubl e buffered system continue to update so that the clock accuracy is

not affected by the access of data. All of the DS1744 registers are updated simultaneously after the

internal clock register updating process has been reenabled. Updating is within a second after the read

bit is written to zero.

DS1744/DS1744P

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DS1744TRUTH TABLE Table 1

VCC CE OE WE MODE DQ POWER

VIH X X DESELECT HIGH-Z STANDBY

VIL XV

IL WRITE DATA IN ACTIVE

VIL VIL VIH READ DATA OUT ACTIVE

VCC>VPF

VIL VIH VIH READ HIGH-Z ACTIVE

VSO<VCC<VPF X X X DESELECT HIGH-Z CMOS STANDBY

VCC<VSO X X X DESELECT HIGH-Z DATA RETENTION

MODE

SETTING THE CLOCK

As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the

read bit, halts updates to the DS1744 registers. The user can then load them with the co rrect day, date and

time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual

clock counters and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at an y time. To increase the shelf life, the oscillator can be turn ed off

to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see

Table 2. Setting it to a one stops the oscillator.

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to

logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the

seconds register is being read, the DQ0 line will toggle at the 512 Hz fr equency as lon g as conditions for

access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and

stable).

CLOCK ACCURACY (DIP M ODULE)

The DS1744 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The clock is

calibrated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements.

The DS1744 does not require additional calibration and temperature deviations will have a negligible

effect in most applications. For this reason, methods of field clock calibration are not available and not

necessary.

CLOCK ACCUR ACY (POWERCAP MODULE)

The DS1744P and DS9034PCX are each individually tested for accuracy. Once mounted together, the

module is guaranteed to keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C.

DS1744/DS1744P

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DS1744 REGISTER MAP Table 2 DATA

ADDRESS B7 B6 B5 B4 B3 B2 B1 B0FUNCTION/RANGE

7FFFF 10 YEAR YEAR YEAR 00-99

7FFFE X X X 10 MO MONTH MONTH 01-12

7FFFD X X 10 DATE DATE DATE 01-31

7FFFC BF FT X X X DAY DAY 01-07

7FFFB X X 10 HOUR HOUR HOUR 00-23

7FFFA X 10 MINUTES MINUTES MINUTES 00-59

7FFF9 OSC 10 SECONDS SECONDS SECONDS 00-59

7FFF8 W R 10 CENTURY CENTURY CENTURY 00-39

OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST

W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING D ATA FROM RAM OR CLOCK

The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable ) is high, and CE

(chip enable) is low. The device architect ure allows ripple-throu gh access to any of the addr ess locations

in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is

stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and

states are not met, valid data will be available at the latter of chip enable access (tCEA ) or at output enable

access time (tOEA ). The state of the data input/output pins (DQ) is controlled b y CE and OE. If the outputs

are activated before tAA , the data lines are driven to an intermediate state until tAA . If the address inputs

are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH )

but will then go indeterminate until the next address access.

WRITING DAT A TO RAM OR CLOCK

The DS1744 is in the write mode whenever WE, and CE are in their active state. The start of a write is

referenced to the latter occurring transition of WE or CE. The addresses must be held valid throughout

the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or

write cycle. Data in must be valid t DS prior to the end of write and remain valid for tDH afterward. In a

typical application, the OE si gnal will be high during a write cycle. Howev er, OE can be active provided

that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the

data bus can become active with read data defined by the address inputs. A low transition on WE will

then disable the outputs tWEZ after WE goes active.

DS1744/DS1744P

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DATA RETENTION MODE

The 5 volt device is fully accessible and data can be written or read only when VCC is greater than VPF .

However, when VCC is below the power fail point, VPF , (point at which write protection occurs) the

internal clock registers and SRAM are blocked from any access. At this time the power fail reset output

signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls

below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the

backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to

nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when VCC is

greater t han VPF . When VCC falls below the po wer fail point, VPF , access to the device is inhibited. At this

time the power fail reset output signal (RST) is driven active and will remain active until VCC returns to

nominal levels. If VPF is less than VBAT , the device power is switched from VCC to the backup supply (VBAT)

when VCC drops below VPF . If VPF is greater than VBAT , the device power is switched from VCC to the

backup supply (VBAT ) when VCC drops below VBAT . RTC operation and SRAM data are maintained

from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and

requires a pull up. Ex cept for the RST, all control, data, and address si gnals must be powered down when

VCC is powered down.

BATTERY LONGEVITY

The DS1744 has a lithium power source that is designed to provide energy for clock activity, and clock

and RAM data retention when the VCC suppl y is not present. The capability of this internal power supply

is sufficient to power the DS1744 continuously for the life of the equipment in which it is installed. For

specification purposes, the life ex pectan cy is 10 years at 25°C with the internal clock os cillator running in

the absence of VCC power. Each DS1744 is shipped from Dallas Semiconductor with its lithium energy

source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than

VPF , the lithium energy source is enabled for battery backup operation. Actual life expectancy of the

DS1744 will be much longer than 10 years since no lithium battery energy is consumed when VCC is

present.

BATTERY MONITOR

The DS1744 constantly monitors the battery voltage o f the internal batter y. The Battery Flag bit (bit 7) of

the day register is used to indicate the voltage level range of the battery. This bit is not writable and

should always be a one when read. If a zero is ever present, an exhausted lithium energy source is

indicated and both the contents of the RTC and RAM are questionable.

DS1744/DS1744P

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ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.3V to +6.0V

Operating Temperature 0°C to 70°C

Storage Temperat ure –20°C to +70°C

Soldering Temperature 260°C for 10 seconds (See Note 7)

* This is a stress rating only and functional operation of the device at these or an y other condition above

those indicated in the operation sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATI NG CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

VIH 2.2 VCC+0.3V V 1

Logic 1 Voltage All Inputs

VCC = 5V±10%

VCC = 3.3V±10% VIH 2.0 VCC+0.3V V 1

VIL -0.3 0.8 V 1

Logic 0 Voltage All Inputs

VCC = 5V±10%

VCC = 3.3V±10% VIL -0.3 0.6 V 1

DC ELECTRICAL CHARACTERISTI CS (0°C to 70°C; V CC = 5.0V

±=10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Active Supply Current Icc X 75 mA 2,3

TTL Standby Current

(CE = VIH)Icc1X 6 mA 2,3

CMOS Standby Current

(CE ≥VCC-0.2V) Icc2X 4 mA 2,3

Input Leakage Current (an y input) IIL -1 +1 µA

Output Leakage Current

(any output) IOL -1 +1 µA

Output Logic 1 Voltage

(IOUT = -1.0 mA) VOH 2.4 1

Output Logic 0 Voltage

(IOUT = +2.1 mA) VOL 0.4 1

Write Protection Voltage VPF 4.25 4.37 4.50 V 1

Battery Switch Over Voltage VSO VBAT 1,4

DS1744/DS1744P

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DC ELECTRICAL CHARACTERISTI CS (0°C to 70°C; V CC = 3.3V ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Active Supply Current Icc X 30 mA 2,3

TTL Standby Current

(CE = VIH)Icc1X 2 mA 2,3

CMOS Standby Current

(CE ≥VCC-0.2V) Icc2X 2 mA 2,3

Input Leakage Current (an y input) IIL -1 +1 µA

Output Leakage Current

(any output) IOL -1 +1 µA

Output Logic 1 Voltage

(IOUT = -1.0 mA) VOH 2.4 1

Output Logic 0 Voltage

(IOUT = +2.1 mA) VOL 0.4 1

Write Protection Voltage VPF 4.25 4.37 2.97 V 1

Battery Switch Over Voltage VSO VBAT or

VPF V 1,4

READ CYCLE, AC CHARACTER ISTICS (0°C to 70°C; V CC = 5.0V ± 10%)

70 ns access 100 ns access

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Read Cycle Time tRC 70 100 ns

Address Access Time tAA 70 100 ns

CE to DQ Low-Z tCEL 55ns

CE Access Time tCEA 70 100 ns

CE Data Off Time tCEZ 25 35 ns

OE to DQ Low-Z tOEL 55ns

OE Access Time tOEA 35 55 ns

OE Data Off Time tOEZ 25 35 ns

Output Hold from Address tOH 55ns

DS1744/DS1744P

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READ CYCLE, AC CHARACTER ISTICS (0°C to 70°C; V CC = 3.3V ± 10%)

120 ns access 150 ns access

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Read Cycle Time tRC 70 100 ns

Address Access Time tAA 70 100 ns

CE to DQ Low-Z tCEL 55ns

CE Access Time tCEA 70 100 ns

CE Data Off Time tCEZ 25 35 ns

OE to DQ Low-Z tOEL 55ns

OE Access Time tOEA 35 55 ns

OE Data Off Time tOEZ 25 35 ns

Output Hold from Address tOH 55ns

READ CYCLE TIMING DIAGRAM

DS1744/DS1744P

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WRITE CYCLE, AC CHARACTERISTI CS (0°C to 70°C; V CC = 5.0V ± 10%)

70 ns access 100 ns access

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Write Cycle Time tWC 70 100 ns

Address Setup Time tAS 00 ns

WE Pulse Width tWEW 50 70 ns

CE Pulse Width tCEW 60 75 ns

Data Setup Time tDS 30 40 ns

Data Hold Time tDH1 0 0 ns 8

Data Hold Time tDH2 X X ns 9

Address Hold Time tAH1 5 5 ns 8

Address Hold Time tAH2 X X ns 9

WE Data Off Time tWEZ 25 35 ns

Write Recovery Time tWR 55 ns

WRITE CYCLE, AC CHARACTERISTI CS (0°C to 70°C; V CC = 3.3V ± 10%)

120 ns access 150 ns access

PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Write Cycle Time tWC 120 150 ns

Address Setup Time tAS 00 ns

WE Pulse Width tWEW 100 130 ns

CE Pulse Width tCEW 110 140 ns

CE and CE2 Pulse Width tCEW 110 140 ns

Data Setup Time tDS 80 90 ns

Data Hold Time tDH1 0 0 ns 8

Data Hold Time tDH2 X X ns 9

Address Hold Time tAH1 0 0 ns 8

Address Hold Time tAH2 X X ns 9

WE Data Off Time tWEZ 40 50 ns

Write Recovery Time tWR 10 10 ns

DS1744/DS1744P

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WRITE CYCLE TIMI NG DIAG RAM, WRITE ENABLE CONTROLLED

WRITE CYCLE TIMING DIAGR AM, CHI P ENABLE CONTROLLED

DS1744/DS1744P

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POWER–UP/DOWN AC CHARACTERISTICS (0°C to 70°C; V CC = 5.0V ±=10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE or WE at VH

Before Power-down tPD 0µs

VCC Fall Time: VPF(MAX) to

VPF(Min) tF300 µs

VCC Fall Time: VPF(MIN) to VSO tFB 10 µs

VCC Rise Time: VPF(MIN) to

VPF(MAX) tR0µs

Power-up Recover Time tREC 35 ms

Expected Data Retention Time

(Oscillator ON) tDR 10 years 5,6

POWER–UP/POWER–DOWN TIMING 5 VOLT DEVICE

DS1744/DS1744P

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POWER–UP/DOWN CHARACTERISTICS (0°C to 70°C; V CC = 3. 3V ±10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

CE or WE at VH, Before

Power-down tPD 0µs

VCC Fall Time: VPF(MAX) to

VPF(Min) tF300 µs

VCC Rise Time: VPF(MIN) to

VPF(MAX) tR0µs

VPF to RST High tREC 35 ms

Expected Data Retention Time

(Oscillator ON) tDR 10 years 5,6

POWER–UP/DOWN WAVEFORM TIMING 3. 3 VOLT DEVICE

CAPACITANCE (t A = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Capacitance on all input pins CIN 7pF

Capacitance on all output pins CO10 pF

DS1744/DS1744P

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AC TEST CONDITIONS

Output Load: 100 pF + 1TTL Gate

Input Pulse Levels: 0.0 to 3.0 Volts

Timing Measurement Reference Levels:

Input: 1.5V

Output: 1.5V

Input Pulse Rise and Fall Times: 5 ns

NOTES:

1. Voltages are referenced to ground.

2. Typical values are at 25°C and nominal supplies.

3. Outputs are open.

4. Battery switch over occurs at the lower of either the battery terminal voltage or VPF .

5. Data retention time is at 25°C.

6. Each DS1744 has a built–in switch that disconnects the lithium source until VCC is first applied by

the user. The expected tDR is defined for DIP modules and assembled PowerCap modules as a

cumulative time in the absence of VCC starting from the time power is first applied by the user.

7. Real–Time Clock Modules (DIP) can be successfully processed through conventional wave–

soldering tecniques as long as temperatures as long as temperature exposure to the lithium energy

source contained within does not exceed +85°C. Post solder cleaning with water washing

techniques is acceptable, provided that ultra-sonic vibration is not used.

In addition, for the PowerCap:

a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through

solder reflow oriented with the label side up (“live – bug”).

b. Hand Soldering and touch–up: Do not touch or appl y the soldering iron to leads for more than 3

(three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder.

To remove the part, apply flux, heat the lead frame pad until the solder reflows and use a

solder wick to remove solder.

8. tAH1 , tDH1 are measured from WE going high.

9. tAH2 , tDH2 are measured from CE going high.

DS1744/DS1744P

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DS1744 28–PIN PACKAGE

PKG 28-PIN

DIM MIN MAX

A IN.

MM 1.470

37.34 1.490

37.85

B IN.

MM 0.675

17.75 0.740

18.80

C IN.

MM 0.335

8.51 0.355

9.02

D IN.

MM 0.075

1.91 0.105

2.67

E IN.

MM 0.015

0.38 0.030

0.76

F IN.

MM 0.140

3.56 0.180

4.57

G IN.

MM 0.090

2.29 0.110

2.79

H IN.

MM 0.590

14.99 0.630

16.00

J IN.

MM 0.010

0.25 0.018

0.45

K IN.

MM 0.015

0.43 0.025

0.58

DS1744/DS1744P

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DS1746P

PKG INCHES

DIM MIN NOM MAX

A 0.920 0.925 0.930

B 0.980 0.985 0.990

C - - 0.080

D 0.052 0.055 0.058

E 0.048 0.050 0.052

F 0.015 0.020 0.025

G 0.025 0.027 0.030

NOTE:

Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder

reflow oriented with the label side up (“live – bug”).

Hand Soldering and touch–up: Do not touch or apply the soldering iron to leads for more than 3 (three)

seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part,

apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.

DS1744/DS1744P

17 of 18

DS1744P WITH DS9034PCX ATTACHED

PKG INCHES

DIM MIN NOM MAX

A 0.920 0.925 0.930

B 0.955 0.960 0.965

C 0.240 0.245 0.250

D 0.052 0.055 0.058

E 0.048 0.050 0.052

F 0.015 0.020 0.025

G 0.020 0.025 0.030

COMPONENTS AND PLACEMENT MAY

VARY FROM EACH DEVICE

DS1744/DS1744P

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RECOMME NDED POWERC AP MODULE L AND PATTERN

INCHESPKG

DIM MIN NOM MAX

A - 1.050 -

B - 0.826 -

C - 0.050 -

D - 0.030 -

E - 0.112 -