Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
HM5425161B Series
HM5425801B Series
HM5425401B Series
256M SSTL_2 interface DDR SDRAM
143 MHz/133 MHz/125 MHz/100 MHz
4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/
16-Mword × 4-bit × 4-bank
ADE-203-1077 (Z)
Preliminary
Rev. 0.0
Jun. 28, 1999
Description
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM
devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high
speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
Features
• JEDEC standard compatible devices
• 2.5 V power supply
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143 MHz/133 Mhz/125 MHz/100 MHz
• Data inputs, outputs, and DM are synchronized with DQS
• 4 banks can operate simultaneously and independently
• Burst read/write operation
• Programmable burst length: 2/4/8
Burst read stop capability
• Programmable burst sequence
Sequential
Interleave
HM5425161B, HM5425801B, HM5425401B Series
2
• Start addressing capability
Even and Odd
• Programmable CAS latency: 2/2.5
• 8192 refresh cycles: 7.8 µs (8192 row/64 ms)
• 2 variations of refresh
Auto refresh
Self refresh
Ordering Information
Type No. Frequency Package
HM5425161BTT-75A
HM5425161BTT-75B
HM5425161BTT-10
143 MHz/133 MHz
133 MHz/100 MHz
125 MHz/100 MHz
400-mill 66-pin plastic TSOP II (TTP-66D)
HM5425801BTT-75A
HM5425801BTT-75B
HM5425801BTT-10
143 MHz/133 MHz
133 MHz/100 MHz
125 MHz/100 MHz
HM5425401BTT-75A
HM5425401BTT-75B
HM5425401BTT-10
143 MHz/133 MHz
133 MHz/100 MHz
125 MHz/100 MHz
HM5425161B, HM5425801B, HM5425401B Series
3
Pin Arrangement (HM5425161B)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
NC
VCCQ
DQSL
NC
VCC
NC
DML
WE
CAS
RAS
CS
NC
A14
A13
A10/AP
A0
A1
A2
A3
VCC
VSS
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
DQ8
NC
VSSQ
DQSU
NC
VREF
VSS
DMU
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
66-pin TSOP
(Top view)
HM5425161B, HM5425801B, HM5425401B Series
4
Pin Description
Pin name Function
A0 to A14 Address input
Row address A0 to A12
Column address A0 to A8
Bank select address A13 (BA1)/A14 (BA0)
DQ0 to DQ15 Data-input/output
DQSU Upper input and output data strobe
DQSL Lower input and output data strobe
CS Chip select
RAS Row address strobe command
CAS Column address strobe command
WE Write enable
DMU Upper byte input mask
DML Lower byte input mask
CLK Clock input
CLK Differential clock input
CKE Clock enable
VREF Input reference voltage
VCC Power for internal circuit
VSS Ground for internal circuit
VCCQ Power for DQ circuit
VSSQ Ground for DQ circuit
NC No connection
HM5425161B, HM5425801B, HM5425401B Series
5
Pin Arrangement (HM5425801B)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VCC
DQ0
VCCQ
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
NC
VCCQ
NC
NC
VCC
NC
NC
WE
CAS
RAS
CS
NC
A14
A13
A10/AP
A0
A1
A2
A3
VCC
VSS
DQ7
VSSQ
NC
DQ6
VCCQ
NC
DQ5
VSSQ
NC
DQ4
VCCQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
66-pin TSOP
(Top view)
HM5425161B, HM5425801B, HM5425401B Series
6
Pin Description
Pin name Function
A0 to A14 Address input
Row address A0 to A12
Column address A0 to A9
Bank select address A13 (BA1)/A14 (BA0)
DQ0 to DQ7 Data-input/output
DQS Input and output data strobe
CS Chip select
RAS Row address strobe command
CAS Column address strobe command
WE Write enable
DM Input mask
CLK Clock input
CLK Differential clock input
CKE Clock enable
VREF Input reference voltage
VCC Power for internal circuit
VSS Ground for internal circuit
VCCQ Power for DQ circuit
VSSQ Ground for DQ circuit
NC No connection
HM5425161B, HM5425801B, HM5425401B Series
7
Pin Arrangement (HM5425401B)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VCC
NC
VCCQ
NC
DQ0
VSSQ
NC
NC
VCCQ
NC
DQ1
VSSQ
NC
NC
VCCQ
NC
NC
VCC
NC
NC
WE
CAS
RAS
CS
NC
A14
A13
A10/AP
A0
A1
A2
A3
VCC
VSS
NC
VSSQ
NC
DQ3
VCCQ
NC
NC
VSSQ
NC
DQ2
VCCQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
66-pin TSOP
(Top view)
HM5425161B, HM5425801B, HM5425401B Series
8
Pin Description
Pin name Function
A0 to A14 Address input
Row address A0 to A12
Column address A0 to A9, A11
Bank select address A13 (BA1)/A14 (BA0)
DQ0 to DQ3 Data-input/output
DQS Output data strobe
CS Chip select
RAS Row address strobe command
CAS Column address strobe command
WE Write enable
DM Input mask
CLK Clock input
CLK Differential clock input
CKE Clock enable
VREF Input reference voltage
VCC Power for internal circuit
VSS Ground for internal circuit
VCCQ Power for DQ circuit
VSSQ Ground for DQ circuit
NC No connection
HM5425161B, HM5425801B, HM5425401B Series
9
Block Diagram
Column address
counter
Column address
buffer Row address
buffer Bank
select
Refresh
counter
Address register
Address (A0 to A14)
AY0 to AY11 AX0 to AX12 AX13, AX14
A0 to A14
DQ*2
Input
buffer
Output
buffer DQS
buffer
Row
decoder
Sense amplifier & I/O bus
Column decoder
Bank 0
*1*1*1*1
Notes: 1. 8192 row × 512 column × 16 bit: HM5425161B
8192 row × 1024 column × 8 bit: HM5425801B
8192 row × 2048 column × 4 bit: HM5425401B
2. DQ0 to DQ15: HM5425161B
DQ0 to DQ7: HM5425801B
DQ0 to DQ3: HM5425401B
Row
decoder
Sense amplifier & I/O bus
Column decoder
Bank 1
Row
decoder
Sense amplifier & I/O bus
Column decoder
Bank 2
Row
decoder
CLK
CKE
DM,
DMU/DML
DLL
DQS,
DQSU/DQSL
CLK
RAS
CAS
WE
CS
Sense amplifier & I/O bus
Column decoder
Bank 3
Control logic & timing generator
Mode register
HM5425161B, HM5425801B, HM5425401B Series
10
Pin Functions (1)
CLK, CLK (input pin): The CLK and the CLK are the master clock inputs. All inputs except DMs, DQSs
and DQs are referred to the cross point of the CLK rising edge and the VREF level. When a read operation,
DQSs and DQs are referred to the cross point of the CLK and the CLK. When a write operation, DMs and
DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to
the cross point of the CLK and the CLK.
CS (input pin): When CS is Low, commands and data can be input. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS, and WE (input pins): These pins define operating commands (read, write, etc.) depending on
the combinations of their voltage levels. See "Command operation".
A0 to A1 2 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross
point of the CLK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to
AY8; the HM5425161B, AY0 to AY9; the HM54 25801B, AY0 to AY9, AY11; the HM5425401B) is loaded
via the A0 to the A9 at the cross point of the CLK rising edge and the VREF level in a read or a write command
cycle. This column address becomes the starting address of a burst operation.
A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a
write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If
A10 = Low when a precharge command is issued, only the bank that is selected by A1 3 (BA1)/A14 (BA0) is
precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 =
Low, auto-precharge function is disabled.
A13 (BA1)/A14 (BA0) (input pin): A13 (BA1)/A14 (BA0) are bank select signals. The memory array is
divided into bank 0, bank 1, bank 2 and bank 3. If A1 3 = Low and A14 = Low, bank 0 is selected. If A1 3 =
High and A14 = Low, bank 1 is selected. If A1 3 = Low and A14 = High, bank 2 is selected. If A13 = High
and A14 = High, bank 3 is selected.
CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh
commands are entered when the CKE is driven Low and exited when it resumes to High.
The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least, that is, if CKE changes at the cross point of
the CLK rising edge and the VREF level with proper setup time tIS, by the next CLK rising edge CKE level
must be kept with proper hold time tIH.
HM5425161B, HM5425801B, HM5425401B Series
11
Pin Functions (2)
DM, DMU/DML (input pins): DM (the HM5425801B and the HM5425401B), DMU/DML (the
HM5425161B) are the reference signals of the data input mask function. DMs are sampled at the cross point
of DQS and VREF. DMU/DML provide the byte mask function. When DMU/DML = High, the data input at
the same timing are masked while the internal burst counter will be count up. DML controls the lower byte
(DQ0 to DQ7) and DMU controls the upper byte (DQ8 to DQ15) of write data.
DQ0 to DQ15 (input and output pins): Data are input to and output from these pins (the DQ0 to the DQ15;
the HM5425161B, the DQ0 to the DQ7; the HM5425801B, the DQ0 to the DQ3; the HM5425401B).
DQS, DQSU/DQSL (input and output pin): DQS (the HM5425801B and the HM5425401B),
DQSU/DQSL (the HM5425161B) provide the read data strobes (as output) and the write data strobes (as
input). DQSL is the lower byte (DQ0 to DQ7) data strobe signal, DQSU is the upper byte (DQ8 to DQ15)
data strobe signal.
VCC and VCCQ (power supply pins): 2.5 V is applied. (VCC is for the internal circuit and VCCQ is for the
output buffer.)
VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the
output buffer.)
HM5425161B, HM5425801B, HM5425401B Series
12
Command Operation
Command Truth Table
The HM5425161B, the HM5425801B and HM5425401B recognize the following commands specified by the
CS, RAS, CAS, WE and address pins. All other combinations than those in the table below are illegal.
CKE
Command Symbol n – 1 n CS RAS CAS WE BA1 BA0 AP Address
Ignore command DESL H ×H×××××××
No operation NOP H ×LHHH××××
Burst stop in read command BST H ×LHHL××××
Column address and read command READ H ×LHLHVVLV
Read with auto-precharge READA H ×LHLHVVHV
Column address and write command WRIT H ×LHLLVVLV
Write with auto-precharge WRITA H ×LHLLVVHV
Row address strobe and bank active ACTV H ×LLHHVVVV
Precharge select bank PRE H ×LLHLVVL×
Precharge all bank PALL H ×LLHL××H×
Refresh REF H H L L L H ××××
SELF H L L L L H ××××
Mode register set MRS H ×LLLLLLLV
EMRS H ×LLLLLHLV
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input
2. The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least.
Ignore command [DESL]: When CS is High at the cross point of the CLK rising edge and the VREF level,
every input are neglected and internal status is held.
No operation [NOP]: As long as this command is input at the cross point of the CLK rising edge and the
VREF level, address and data input are neglected and internal status is held.
Burst stop in read operation [BST]: This command stops a burst read operation, which is not applicable for
a burst write operation.
Column address strobe and read command [READ]: This command starts a read operation. The start
address of the burst read is determined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9;
the HM5425801B, AY0 to AY9, AY11; the HM5425401B) and the bank select address (B A). After the
completion of the read operation, the output buffer becomes High-Z.
HM5425161B, HM5425801B, HM5425401B Series
13
Read with auto-precharge [READA]: This command starts a read operation. After completion of the read
operation, precharge is automatically executed.
Column address strobe and write command [WRIT]: This command starts a write operation. The start
address of the burst write is determined by the column address (AY0 to AY8; the HM5425161B, AY0 to
AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B) and the bank select address (BA).
Write with auto-precharge [WRITA]: This command starts a write operation. After completion of the
write operation, precharge is automatically executed.
Row address strobe and bank activate [ACTV]: This command activates the bank selected by A13/A14
(BA) and determines a row address (AX0 to AX1 2). When A1 3 = A14 = Low, bank 0 is activated. When
A13 = High and A14 = Low, bank 1 is activated. When A13 = Low and A14 = High, bank 2 is activated.
When A13 = A14 = High, bank 3 is activated.
Precharge selected bank [PRE]: This command starts a pre-charge operation for the bank selected by
A13/A14.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts a refresh operation. There are two types of refresh operation,
one is auto-refresh, and another is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]: The DDR SDRAM has the two mode
registers, the mode register and the extended mode register, to defines how it works. The both mode registers
are set through the address pins (the A0 to the A14) in the mode register set cycle. For details, refer to "Mode
register and extended mode register set".
HM5425161B, HM5425801B, HM5425401B Series
14
CKE Truth Table
CKE
Current state Command n – 1 n CS RAS CAS WE Address Notes
Idle Auto-refresh command (REF) H H L L L H ×2
Idle Self-refresh entry (SELF) H L L L L H ×2
Idle Power down entry (PDEN) H L L H H H ×
HLH××××
Self refresh Self refresh exit (SELFX) L H L H H H ×
LHH××××
Power down Power down exit (PDEX) L H L H H H ×
LHH××××
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL.
2. All the banks must be in IDLE before executing this command.
3. The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least.
Auto-refresh command [REF]: This command executes auto-refresh. The banks and the ROW addresses
to be refreshed are internally determined by the internal refresh contoroller. The average refresh cycle is 7.8
µs. The output buffer becomes High-Z after auto-refresh start. Precharge has been completed automatically
after the auto-refresh. The ACTV or MRS command can be issued tRFC after the last auto-refresh command.
Self-refresh entry [SELF]: This command starts self-refresh. The self-refresh operation continues as long
as CKE is held Low. During the self-refresh operation, all ROW addresses are repeated refreshing by the
internal refresh contoroller. A self-refresh is terminated by a self-refresh exit command.
Power down mode entry [PDEN]: tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR
SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by
deactivating the input initial circuit. Power down mode continues while CKE is held Low. No internal
refresh operation occurs during the power down mode. [PDEN] do not disable DLL.
Self-refresh exit [SELFX]: This command is executed to exit from self-refresh mode. 10 cycles (= tSNR)
after [SELFX], non-read commands can be executed. For read operation, wait for 200 cycles (= tSRD) after
[SELFX] to adjust Dout timing by DLL. After the exit, within 7.8 µs input auto-refresh command.
Power down exit [PDEX]: The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the
cycle when [PDEX] is issued.
HM5425161B, HM5425801B, HM5425401B Series
15
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of
the DDR SDRAM.
Function Truth Table (1)
Current state CS RAS CAS WE Address Command Operation Next state
Precharging*2H×××× DESL NOP ldle
LHHH×NOP NOP ldle
LHHL×BST ILLEGAL*12 —
L H L H BA, CA, A10 READ/READA ILLEGAL*12 —
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*12 —
L L H H BA, RA ACTV ILLEGAL*12 —
L L H L BA, A10 PRE, PALL NOP ldle
LLL×× ILLEGAL —
Idle*3H×××× DESL NOP ldle
LHHH×NOP NOP ldle
LHHL×BST ILLEGAL*12 —
L H L H BA, CA, A10 READ/READA ILLEGAL*12 —
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*12 —
L L H H BA, RA ACTV ILLEGAL*12 Activating
L L H L BA, A10 PRE, PALL NOP ldle
LLLH×REF, SELF Refresh/
Selfrefresh*13 ldle/
Selfrefresh
L L L L MODE MRS Mode register set*13 ldle
Refresh
(auto-refresh)*4H×××× DESL NOP ldle
LHHH×NOP NOP ldle
HHHL ×BST ILLEGAL —
LHL×× ILLEGAL —
LL××× ILLEGAL —
HM5425161B, HM5425801B, HM5425401B Series
16
Function Truth Table (2)
Current state CS RAS CAS WE Address Command Operation Next state
Activating*5H×××× DESL NOP Active
LHHH×NOP NOP Active
LHHL×BST ILLEGAL*12 —
L H L H BA, CA, A10 READ/READA ILLEGAL*12 —
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*12 —
L L H H BA, RA ACTV ILLEGAL*12 —
L L H L BA, A10 PRE, PALL ILLEGAL*12 —
LLL×× ILLEGAL —
Active*6H×××× DESL NOP Active
LHHH×NOP NOP Active
LHHL×BST ILLEGAL Active
L H L H BA, CA, A10 READ/READA Starting read
operation Read/READ
A
L H L L BA, CA, A10 WRIT/WRITA Starting write
operation Write
recovering/
precharging
L L H H BA, RA ACTV ILLEGAL*12 —
L L H L BA, A10 PRE, PALL Pre-charge Idle
LLL×× ILLEGAL —
Read*7H×××× DESL NOP Active
LHHH×NOP NOP Active
LHHL×BST BST Active
LHLHBA, CA, A10 READ/READA Interrupting burst
read operation to
start new read
Active
LHLLBA, CA, A10 WRIT/WRITA ILLEGAL*14 —
L L H H BA, RA ACTV ILLEGAL*12 —
L L H L BA, A10 PRE, PALL Interrupting burst
read operation to
start pre-charge
Precharging
LLL××ILLEGAL —
HM5425161B, HM5425801B, HM5425401B Series
17
Function Truth Table (3)
Current state CS RAS CAS WE Address Command Operation Next state
Read with auto-
pre-charge*8H×××× DESL NOP Precharging
LHHH×NOP NOP Precharging
LHHL×BST ILLEGAL —
L H L H BA, CA, A10 READ/READA ILLEGAL —
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL —
L L H H BA, RA ACTV ILLEGAL*12 —
L L H L BA, A10 PRE, PALL ILLEGAL*12 —
LLL×× ILLEGAL —
Write*9H×××× DESL NOP Write
recovering
LHHH×NOP NOP Write
recovering
LHHL×BST ILLEGAL —
L H L H BA, CA, A10 READ/READA Interrupting burst
write operation to
start read operation.
Read/ReadA
L H L L BA, CA, A10 WRIT/WRITA Interrupting burst
write operation to
start new write
operation.
Write/WriteA
L L H H BA, RA ACTV ILLEGAL*12 —
L L H L BA, A10 PRE, PALL Interrupting write
operation to start
pre-charge.
Idle
LLL×× ILLEGAL —
Write
recovering*10 H×××× DESL NOP Active
LHHH×NOP NOP Active
LHHL×BST ILLEGAL —
L H L H BA, CA, A10 READ/READA Starting read
operation. Read/ReadA
L H L L BA, CA, A10 WRIT/WRITA Starting new write
operation. Write/WriteA
L L H H BA, RA ACTV ILLEGAL*12 —
L L H L BA, A10 PRE/PALL ILLEGAL*12 —
LLL×× ILLEGAL —
HM5425161B, HM5425801B, HM5425401B Series
18
Function Truth Table (4)
Current state CS RAS CAS WE Address Command Operation Next state
Write with auto-
pre-charge*11 H×××× DESL NOP Precharging
LHHH×NOP NOP Precharging
LHHL×BST ILLEGAL —
L H L H BA, CA, A10 READ/READA ILLEGAL —
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL —
L L H H BA, RA ACTV ILLEGAL*12 —
L L H L BA, A10 PRE, PALL ILLEGAL*12 —
LLL×× ILLEGAL —
Notes: 1. H: VIH. L: VIL. ×: VIH or VIL.
2. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.
3. The DDR SDRAM reachs "IDLE" state tRP after precharge command is issued.
4. The DDR SDRAM is in "Refresh" state for tRC after auto-refresh command is issued.
5. The DDR SDRAM is in "Activating" state for tRCD after ACTV command is issued.
6. The DDR SDRAM is in "Active" state after "Activating" is completed.
7. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are
turned off.
8. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has
been output and DQ output circuits are turned off.
9. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
10.The DDR SDRAM is in "Write recovering" for tWR after the last data are input.
11.The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input.
12.This command may be issued for other banks, depending on the state of the banks.
13.All banks must be in "IDLE".
14.Before executing a write command to stop the preceding burst read operation, BST command must
be issued.
HM5425161B, HM5425801B, HM5425401B Series
19
Simplified State Diagram
PRECHARGE
ROW
ACTIVE
IDLE
IDLE
POWER
DOWN
AUTO
REFRESH
SELF
REFRESH
MODE
REGISTER
SET
ACTIVE
POWER
DOWN
POWER
ON
WRITEA READA
SR ENTRY
SR EXIT
MRS REFRESH
CKE
CKE_
CKE
CKE_ ACTIVE
WRITE READ
WRITE
WITH AP READ
WITH AP
POWER
APPLIED PRECHARGE
AP
READ WRITE
WRITE
WITH
AP
READ
WITH
READ
WITH AP WRITE
WITH AP
PRECHARGE
PRECHARGE PRECHARGE
*1
READ
Read
WRITE
Write
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically
and enter the IDLE state.
HM5425161B, HM5425801B, HM5425401B Series
20
Operation of the DDR SDRAM
Power-up Sequence
The following sequence is recommended for Power-up.
(1) Apply power and attempt to maintain CKE at an LVCMOS low state (all other inputs may be undefined).
Apply VCC before or at the same time as VCCQ.
Apply VCCQ before or at the same time as VTT and VREF.
(2) Start clock and maintain stable condition for a minimum of 200 µs.
(3) After the minimum 200 µs of stable power and clock (CLK, CLK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200
cycles of clock input is required to lock the DLL after every DLL reset).
(7) Issue precharge all command for the device.*1
(8) Issue 2 or more auto-refresh commands.*1
(9) Issue a mode register set command to initialize device operation.
Note: 1. Sequence of (7) and (8) may be reversed.
Power-up Sequence after CKE Goes High
Command EMRS
PALL MRS REF
2 cycles (min) 2 cycles (min)
200 cycles (min)
2 cycles (min)2 cycles (min) tRP tRC tRC
PALL MRSREF REF Any
command
DLL enable DLL reset
HM5425161B, HM5425801B, HM5425401B Series
21
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A14 pins by the mode register set command [MRS] or
the extended mode register set command [EMRS]. The mode register and the extended mode register are set
by inputting signal via the A0 to the A14 during mode register set cycles. A14 (BA0) and A13 (BA1)
determine which one of the mode register or the extended mode register are set. Prior to a read or a write
operation, the mode register must be set.
Remind that no other parameters are shown in the table bellow are allowed to input to the registers.
Mode Register Set [MRS] (A14 = 0, A13 = 0)
A2 A1 A0 Burst Length
001 2
010 4
011 8
BT=0 BT=1
2
4
8
A3
0 Sequential
1 Interleave
Burst Type
A6 A5 A4 CAS Latency
010 2
2.5
110
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0000 0DR LMODE BT BL
A8
0No
1 Yes
DLL Reset
A11 A10
A12
A13
(BA1)
0
A14
(BA0)
0
MRS
Extended Mode Register Set [EMRS] (A14 = 1, A13 = 0)
A0
0 DLL Enable
1 DLL Disable
DLL Control
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
000 0 0000 0 0 0 DLL0
A11 A10A12
A13
(BA1)
0
A14
(BA0)
1
EMRS
HM5425161B, HM5425801B, HM5425401B Series
22
Burst Operation
The burst type (BT) and the first three bits of the column address determines the order of a data out.
A2 A1 A0 Addressing(decimal)
000
001
010
011
111
InterleaveSequence
100
110
101
Starting Ad.
0, 1, 2, 3, 4, 5, 6, 7,
1, 2, 3, 4, 5, 6, 7,
2, 3, 4, 5, 6, 7,
3, 4, 5, 6, 7,
4, 5, 6, 7,
5, 6, 7,
6, 7,
7,
0,
0, 1,
0, 1, 2,
0, 1, 2, 3,
0, 1, 2, 3, 4,
0, 1, 2, 3, 4, 5,
0, 1, 2, 3, 4, 5, 6,
0, 1, 2, 3, 4, 5, 6, 7,
1, 0, 3, 2, 5, 4, 7,
2, 3, 0, 1, 6, 7,
3, 2, 1, 0, 7,
4, 5, 6, 7,
5, 4, 7,
6, 7,
7,
6,
4, 5,
6, 5, 4,
0, 1, 2, 3,
6, 1, 0, 3, 2,
4, 5, 2, 3, 0, 1,
6, 5, 4, 3, 2, 1, 0,
Burst length = 8
A1 A0 Addressing(decimal)
00
01
10
11
InterleaveSequence
Starting Ad.
0, 1, 2, 3,
1, 2, 3, 0,
2, 3, 0, 1,
3, 0, 1, 2,
0, 1, 2, 3,
1, 0, 3, 2,
2, 3, 0, 1,
3, 2, 1, 0,
Burst length = 4
A0 Addressing(decimal)
0
1
InterleaveSequence
Starting Ad.
0, 1,
1, 0, 0, 1,
1, 0,
Burst length = 2
HM5425161B, HM5425801B, HM5425401B Series
23
Read/Write Operations
Bank active: A read or a write operation begins with the bank active command [ACTV]. The bank active
command determines a bank address (AX14, AX13) and a row address (AX0 to AX12). For the bank and the
row, a read or a write command can be issued tRCD after the ACTV is issued.
Read operation: The burst length (BL), the CAS latency (CL) and the burst type (BT) of the mode register
are referred when a read command is issued. The burst length (BL) determines the length of a sequential
output data by the read command which can be set to 2, 4, or 8. The starting address of the burst read is
defined by the column address (AY0 to AY8; the HM5425161B , AY0 to AY9; the HM5425801B, AY0 to
AY9, AY11; the HM5425401B), the bank select address (AX14, AX13) which are loaded via the A0 to A14
pins in the cycle when the read command is issued. The data output timing are characterized by CL (2 or 2.5)
and tAC. The read burst start CL • tCK + tAC (ns) after the clock rising edge where the read command are
latched. The DDR SDRAM output the data strobe through DQS or DQSU/DQSL simultaneously with data.
tRPRE prior to the first rising edge of the data strobe, the DQS or the DQSU/DQSL are driven Low from VTT
level. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both
the rising and falling edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst
read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z.
This low period of DQS is referred as read postamble.
Read Operation (Burst Length)
D0 D1
D0 D1 D2 D3
D0 D1 D2 D3 D4 D5 D6 D7
CLK
CLK
Address
DQS*
Dout
BL = 2
BL = 4
BL = 8
Command
CAS latency = 2
BL: Burst length
t1t0 t2 t3 t4 t5 t6 t7 t8
tRCD
tRPRE
DQS*:DQS,DUSU/DQSL
tRPST
ACTVNOP NOP NOPREAD
!"
Row Column
HM5425161B, HM5425801B, HM5425401B Series
24
Read Operation (CAS Latency)
CLK
CLK
DQS VTT
VTT
VTT
VTT
DQ
DQS
DQ
CL = 2
CL = 2.5
Command
t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
D0 D1 D2 D3
D0 D1 D2 D3
tRPST
tRPRE
tRPRE tRPST
tAC,tDQSCK
tAC,tDQSCK
Read NOP
HM5425161B, HM5425801B, HM5425401B Series
25
Write operation : The burst length (BL) and the burst type (BT) of the mode register are referred when a
write command is issued. The burst length (BL) determines the length of a sequential data input by the write
command which can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The
starting address of the burst read is defined by the column address (AY0 to AY8; the HM5425161B , AY0 to
AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B), the bank select address (AX14, AX13)
which are loaded via the A0 to A14 pins in the cycle when the write command is issued. DQS, DQSU/DQSL
should be input as the strobe for the input-data and DM, DMU/DML as well during burst operation. tWPREH
prior to the first rising edge of the DQS, the DQSU/DQSL should be set to Low and tWPST after the last falling
edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble.
The last low period of DQS is referred as wrtie postamble.
Write Operation
in1
in0 in1 in2 in3
in0 in1 in2 in3 in4 in5 in6 in7
CLK
CLK
Address
DQS*
Din
BL = 2
BL = 4
BL = 8
Command
BL: Burst length
t1t0 t2 t3 t3.5 t4 t5 t6 t7 t8
tRCD
tWPST
DQS*:DQS,DQSU/DQSL
in0
ACTVNOP NOP NOPWRITE
tWPREH
tWPRES
#
!"#
Row Column
HM5425161B, HM5425801B, HM5425401B Series
26
Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during
a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles
after a BST command issued, the DQ pins become High-Z. The BST command is not supported for the burst
write operation. Note that bank address is not referred when this command is executed.
Burst Stop during a Read Operation
CLK
CLK
DQS
DQ
DQS
DQ
CL = 2
CL = 2.5
Command
t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
D0 D1
D0 D1
CL: CAS latency
Read BST NOP
2 cycles
tBSTZ
tBSTZ 2.5 cycles
HM5425161B, HM5425801B, HM5425401B Series
27
Auto Precharge
Read with auto-precharge: The precharge is automatically performed after completing a read operation.
The precharge starts t RPD (BL/2) cycle after READA command input. tRCD for READA should be determined
so that tRC (ACTV to ACTV) spec. is obeyed when READA is issued successively after a bank active
command, that is tRCD (READA) ≥ tRC (min.)-tRP (min.)-tRPD. A column command to the other active bank can
be issued the next cycle after the last data output. Read with auto -precharge command does not limit row
commands execution for other bank.
D0 D1 D2 D3
CLK
CLK
DQ
Command
tRAS (min) tRP (min)
tRCD (min)
ACTV
Note: Internal auto-precharge starts at the timing indicated by " ".
NOP
2 cycles (= BL/2)
READAACTV
DQS,
DQSU/DQSL
tAC,tDQSCK
tRPD
HM5425161B, HM5425801B, HM5425401B Series
28
Write with auto-precharge: The precharge is automatically performed after completing a burst write
operation. The precharge operation is started t WPD (= BL/ 2 + 3) cycles after WRITA command issued. t RCD
for WRITA should be determined so that tRC (ACTV to ACTV) spec. is obeyed when WRITA is issued
successively after a bank active command, that is tRCD (WRITA) ≥ tRC(min.)-tRP(min.)-tWPD. A column
command to the other active command can be issued the next cycle after the internal precharge command
issued. Write with auto-precharge command does not limit row commands execution for other bank.
Burst Write (Burst Length = 4)
D1 D2 D3 D4
CLK
CLK
DQ
Command
DM,
DMU/DML
tRAS (min)
tRCD (min)
#
tRP
DQS,
DQSU/DQSL
ACTV WRITA ACTV
BL/2 + 3 cycles
tWPD
Note: Internal auto-precharge starts at the timing indicated by " ". Burst length = 4
NOPNOP
HM5425161B, HM5425801B, HM5425401B Series
29
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the
consecutive read command
Bank
address Row
address State Operation
1. Same Same ACTIVE The consecutive read can be performed after an interval of no less
than 1 cycle to interrupt the preceding read operation.
2. Same Different — Precharge the bank to interrupt the preceding read operation. tRP after
the precharge command, issue the ACTV command. tRCD after the
ACTV command, the consecutive read command can be issued. See
‘A read command to the consecutive precharge interval’ section.
3. Different Any ACTIVE The consecutive read can be performed after an interval of no less
than 1 cycle to interrupt the preceding read operation.
IDLE Precharge the bank without interrupting the preceding read operation.
tRP after the precharge command, issue the ACTV command. tRCD after
the ACTV command, the consecutive read command can be issued.
READ to READ Command Interval (same ROW address in the same bank)
"#
A0 A1 B0 B1 B2 B3
CLK
CLK
Address
BA
Dout
DQS,
DQSU/DQSL
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
Bank0
Active
Column = A
Dout Column = B
Dout
"#
CAS latency = 2
Burst length = 4
Bank0
NOP
ACTV NOP READ
Row Column A
READ
Column B
Column = A
Read Column = B
Read
HM5425161B, HM5425801B, HM5425401B Series
30
READ to READ Command Interval (different bank)

!
A0 A1 B0 B1 B2 B3
CLK
CLK
Address
BA
Dout
DQS,
DQSU/DQSL
Command
t1t0 t2 t3 t4 t5 t6 t7 t8 t9
Bank0
Active Bank3
Active Bank0
Read Bank3
Read
Bank0
Dout

CAS latency = 2
Burst length = 4
NOP
ACTV NOP NOP
Row0
ACTV READ
Row1 Column A
READ
Column B
Column = A
Read Column = B
Read Bank3
Dout
HM5425161B, HM5425801B, HM5425401B Series
31
A Write command to the consecutive Write command Interval:
Destination row of the
consecutive write command
Bank
address Row
address State Operation
1. Same Same ACTIVE The consecutive write can be performed after an interval of no less
than 1 cycle to interrupt the preceding write operation.
2. Same Different — Precharge the bank to interrupt the preceding write operation. tRP after
the precharge command, issue the ACTV command. tRCD after the
ACTV command, the consecutive write command can be issued. See
‘A write command to the consecutive precharge interval’ section.
3. Different Any ACTIVE The consecutive write can be performed after an interval of no less
than 1 cycle to interrupt the preceding write operation.
IDLE Precharge the bank without interrupting the preceding write operation.
tRP after the precharge command, issue the ACTV command. tRCD after
the ACTV command, the consecutive write command can be issued.
WRITE to WRITE Command Interval (same ROW address in the same bank)
"#
!
A0 A1 B0 B1 B2 B3
CLK
CLK
Address
BA
Din
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
Bank0
Active
#
!
Burst length = 4
Bank0
NOP
DQS,
DQSU/DQSL
ACTV NOP WRIT
Row Column A
WRIT
Column B
Column = A
Write Column = B
Write
HM5425161B, HM5425801B, HM5425401B Series
32
WRITE to WRITE Command Interval (different bank)
!"#
A0 A1 B0 B1 B2 B3
CLK
CLK
Address
BA
Din
Command
t1t0 t2 t3 t4 t5 t6 t7 t8 t9
Bank0
Active Bank3
Active
Bank0
Write Bank3
Write

Burst length = 4
Bank0, 3
NOP
DQS,
DQSU/DQSL
ACTV NOP ACTV WRIT
Row0 Row1 Column A
WRIT
Column B
HM5425161B, HM5425801B, HM5425401B Series
33
A Read command to the consecutive Write command interval with the BST command
Destination row of the
consecutive write command
Bank
address Row
address State Operation
1. Same Same ACTIVE Issue the BST command. tBSTW (≥ t BSTZ) after the BST command, the
consecutive write command can be issued.
2. Same Different — Precharge the bank to interrupt the preceding read operation. tRP after
the precharge command, issue the ACTV command. tRCD after the
ACTV command, the consecutive write command can be issued. See
‘A read command to the consecutive precharge interval’ section.
3. Different Any ACTIVE Issue the BST command. t BSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
IDLE Precharge the bank independently of the preceding read operation.
tRP after the precharge command, issue the ACTV command. tRCD after
the ACTV command, the consecutive write command can be issued.
READ to WRITE Command Interval
Q0 Q1 D0 D1 D2 D3
CLK
CLK
DM,
DMU/DML
DQ
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
!"#
Burst Length = 4
CAS Latency= 2
DQS,
DQSU/DQSL
OUTPUT INPUT
tBSTW (≥ tBSTZ)
High-Z
READ WRIT
BST NOP NOP
tBSTZ (= CL)
HM5425161B, HM5425801B, HM5425401B Series
34
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the
consecutive read command
Bank
address Row
address State Operation
1. Same Same ACTIVE To complete the burst operation, the consecutive read command
should be performed tWRD (= BL/ 2 + 2) after the write command.
2. Same Different — Precharge the bank tWRD after the preceding write command. tRP after
the precharge command, issue the ACTV command. tRCD after the
ACTV command, the consecutive read command can be issued. See
‘A read command to the consecutive precharge interval’ section.
3. Different Any ACTIVE To complete a burst operation, the consecutive read command should
be performed tWRD (= BL/ 2 + 2) after the write command.
IDLE Precharge the bank independently of the preceding write operation.
tRP after the precharge command, issue the ACTV command. tRCD after
the ACTV command, the consecutive read command can be issued.
WRITE to READ Command Interval
D0 D1 D2 D3 Q2
Q0 Q1
CLK
CLK
DM,
DMU/DML
DQ
Command
t1t0 t2 t3 t4 t5 t6
!"
,
!
BL = 4
CL = 2
tWRD (min)
DQS,
DQSU/DQSL
INPUT OUTPUT
BL/2 + 2 cycle
WRIT NOP NOPREAD
HM5425161B, HM5425801B, HM5425401B Series
35
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the
consecutive read command
Bank
address Row
address State Operation
1. Same Same ACTIVE DM, DMU/DML must be input 1 cycle prior to the read command input
to prevent from being written invalid data. In case, the read command
is input in the next cycle of the write command, DM, DMU/DML is not
necessary.
2. Same Different — —*1
3. Different Any ACTIVE DM, DMU/DML must be input 1 cycle prior to the read command input
to prevent from being written invalid data. In case, the read command
is input in the next cycle of the write command, DM, DMU/DML is not
necessary.
IDLE —*1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the
write operation in this case.
WRITE to READ Command Interval (Samebank, same ROW address)
[WRITE to READ delay = 1 clock cycle]
D0 D1 D2 Q0 Q1 Q2 Q3
CLK
CLK
DM,
DMU/DML
DQ
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
,
!"#
BL = 4
CL= 2
DQS,
DQSU/DQSL
CL=2
Data masked by read command
1 cycle
READ NOPWRIT
High-Z
High-Z
HM5425161B, HM5425801B, HM5425401B Series
36
[WRITE to READ delay = 2 clock cycle]
D0 D1 D2 D3 Q0 Q1 Q2 Q3
CLK
CLK
DM,
DMU/DML
DQ
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
BL = 4
CL= 2
DQS,
DQSU/DQSL
CL=2
Data masked by read command
Data masked by DM
,
,
 !"
2 cycle
READ NOPNOPWRIT
High-Z
High-Z
[WRITE to READ delay = 3 clock cycle]
D0 D1 D2 D3 Q0 Q1 Q2 Q3
CLK
CLK
DM,
DMU/DML
DQ
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
BL = 4
CL= 2
DQS,
DQSU/DQSL
CL=2
Data masked by DM
!"
,
!"
3 cycle
READWRIT NOP NOP
HM5425161B, HM5425801B, HM5425401B Series
37
A Read command to the consecutive Precharge command interval (same bank):
To output all data: To complete a burst read opeartion and get a burst length of data, the consecutive
precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued.
READ to PRECHARGE Command Interval (same bank): To output all data
CAS Latency = 2, Burst Length = 4
A0 A1 A2 A3
CLK
CLK
Dout
DQS,
DQSU/DQSL
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
tRPD = BL/2
READ NOPNOP NOP
PRE/
PALL
CAS Latency = 2.5, Burst Length = 4
A0 A1 A2 A3
CLK
CLK
Dout
DQS,
DQSU/DQSL
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
tRPD = BL/2
READ NOP NOP NOP
PRE/
PALL
HM5425161B, HM5425801B, HM5425401B Series
38
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-
Z tHZP (= CL) after the precharge command.
CAS Latency = 2, Burst Length = 2, 4, 8
A0 A1
CLK
CLK
Dout
DQS,
DQSU/DQSL
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
PRE/PALL
tHZP = CL + 1
READ
NOP NOP
High-Z
High-Z
CAS Latency = 2.5, Burst Length = 2, 4, 8
A0 A1
CLK
CLK
Dout
DQS,
DQSU/DQSL
Command
t1t0 t2 t3 t4 t5 t6 t7 t8
High-Z
High-Z
tHZP = CL + 1
CL = 2.5
READ
NOP NOP
PRE/PALL
HM5425161B, HM5425801B, HM5425401B Series
39
A Write command to the consecutive Precharge command interval (same bank): The minimum interval
tWPD ((BL/ 2 + 3) cycles) is necessary between the write command and the precharge command.
WRITE to PRECHARGE Command Interval (same bank)
Burst Length = 4
A0 A1 A2 A3
CLK
CLK
Din
DM,
DMU/DML
DQS,
DQSU/DQSL
Command
t1t0 t2 t3 t4 t5 t6 t7
Last data input
tWPD
!"
,
WRIT NOP NOP
tWR
BL/2 +3 cycles
PRE/PALL
HM5425161B, HM5425801B, HM5425401B Series
40
Bank active command interval:
Destination row of the
consecutive ACTV command
Bank
address Row
address State Operation
1. Same Any ACTIVE Two successive ACTV commands can be issued at tRC interval. In
between two successive ACTV operations, precharge command
should be executed.
2. Different Any ACTIVE Prechage the bank. tRP after the precharge command, the consecutive
ACTV command can be issued.
IDLE tRRD after an ACTV command, the next ACTV command can be issued.
Bank Active to Bank Active
CLK
CLK
Command
BA
tRC
Address
,

ACTV
tRRD
Bank0
Active Bank3
Active Bank0
Precharge Bank0
Active

!"#
PRE
ACTV
ROW: 0
NOP NOPNOPACTV
,
ACTV
ROW: 1ROW: 0
Mode register set to Bank-active command interval: The interval between setting the mode register and
executing a bank-active command must be no less than tMRD.
CLK
CLK
Command
Address
NOP NOPMRS ACTV
tMRD
Mode Register Set Bank3
Active
"
CODE BS and ROW
HM5425161B, HM5425801B, HM5425401B Series
41
DMU/DML Control (HM5425161B)
DMU can mask upper byte of input data. DML can mask lower byte of input data. By setting DMU/DML to
Low, data can be written. When DMU/DML is set to High, the corresponding data is not written, and the
previous data is held. The latency between DMU/DML input and enabling/disabling mask function is 0.
DM Control (HM5425801B/HM5425401B)
DM can mask input data. By setting DM to Low, data can be written. When DM is set to High, the
corresponding data is not written, and the previous data is held. The latency between DM input and
enabling/disabling mask function is 0.
Mask Mask
DQS,
DQSU/DQSL
DQ
DM,
DMU/DML
t1 t2 t3 t4 t5 t6
Write mask latency = 0
HM5425161B, HM5425801B, HM5425401B Series
42
Absolute Maximum Ratings
Parameter Symbol Value Unit Note
Voltage on any pin relative to Vss VT–1.0 to +4.6 V 1
Supply voltage relative to VSS VCC, VCCQ –1.0 to +4.6 V 1
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Note: 1. Refer to VSS.
DC Operating Conditions (Ta = 0 to +70˚C)
Parameter Symbol Min Typ Max Unit Notes
Supply voltage VCC, VCCQ 2.3 2.5 2.7 V 1, 2
VSS, VSSQ 000V
Input reference voltage VREF 1.15 1.25 1.35 V 1
Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V 1
DC Input high voltage VIH VREF + 0.18 — VCCQ + 0.3 V 1, 3
DC Input low voltage VIL –0.3 — VREF – 0.18 V 1, 4
DC Input signal voltage VIN (dc) –0.3 — VCCQ + 0.3 V 5
DC differential input voltage VSWING (dc) 0.36 — VCCQ + 0.6 V 6
Notes: 1. All parameters are referred to VSS, when measured.
2. VCCQ must be lower than or equal to VCC.
3. VIH is allowed to exceed VCC up to 4.6 V for the period shorter than or equal to 5 ns.
4. VIL is allowed to outreach below VSS down to –1.0 V for the period shorter than or equal to 5 ns.
5. VIN (dc) specifies the allowable dc execution of each differential input.
6. VSWING (dc) specifies the input differential voltage required for switching.
HM5425161B, HM5425801B, HM5425401B Series
43
DC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 2.5 V ± 0.2 V, VSS
, VSSQ = 0 V)
(HM5425161B)
HM5425161B
-75A -75B -10
Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes
Operating current
(ACTV-PRE) ICC0 — TBD — TBD — TBD mA CKE ≥ VIH, tRC = min 1, 2, 5
Operating current
(ACTV-READ-PRE) ICC1 — TBD — TBD — TBD mA CKE ≥ VIH, BL = 2,
CL = 2.5, tRC = min 1, 2, 5
Idle power down
standby current ICC2P — TBD — TBD — TBD mA CKE ≤ VIL 4
Idle standby current ICC2N — TBD — TBD — TBD mA CKE ≥ VIH, CS ≥ VIH 4
Active power down
standby current ICC3P — TBD — TBD — TBD mA CKE ≤ VIL 3
Active standby current ICC3N — TBD — TBD — TBD mA CKE ≥ VIH,
tRAS = max 3
Operating current
(Burst read operation) ICC4R — TBD — TBD — TBD mA CKE ≥ VIH, BL = 2,
CL = 2.5 1, 2, 5,
6
Operating current
(Burst write operation) ICC4W — TBD — TBD — TBD mA CKE ≥ VIH, BL = 2,
CL = 2.5 1, 2, 5,
6
Auto refresh current ICC5 — TBD — TBD — TBD mA tRFC = min,
Input ≤ VIL or ≥ VIH
Self refresh current ICC6 — 2 — 2 — 2 mA Input ≥ VCC – 0.2 V
Input ≤ 0.2 V
Input leakage current ILI –10 10 –10 10 –10 10 µAV
CC ≥ Vin ≥ VSS
Output leakage current ILO –10 10 –10 10 –10 10 µAV
CC ≥ Vout ≥ VSS
Output high voltage VOH VTT +
0.76 —V
TT +
0.76 —V
TT +
0.76 —VI
OH (max) = –15.2
mA
Output low voltage VOL —V
TT –
0.76 —V
TT –
0.76 —V
TT –
0.76 VI
OL (min) = 15.2 mA
Notes. 1. These ICC data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. Data/Data mask transition twice per one cycle.
7. The ICC data on this table are measured with regard to tCK = min in general.
HM5425161B, HM5425801B, HM5425401B Series
44
DC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 2.5 V ± 0.2 V, VSS, VSSQ = 0 V)
(HM5425801B/HM5425401B)
HM5425801B/HM5425401B
-75A -75B -10
Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes
Operating current
(ACTV-PRE) ICC0 — TBD — TBD — TBD mA CKE ≥ VIH, tRC = min 1, 2, 5
Operating current
(ACTV-READ-PRE) ICC1 — TBD — TBD — TBD mA CKE ≥ VIH, BL = 2,
CL = 2.5, tRC = min 1, 2, 5
Idle power down
standby current ICC2P — TBD — TBD — TBD mA CKE ≤ VIL 4
Idle standby current ICC2N — TBD — TBD — TBD mA CKE ≥ VIH, CS ≥ VIH 4
Active power down
standby current ICC3P — TBD — TBD — TBD mA CKE ≤ VIL 3
Active standby current ICC3N — TBD — TBD — TBD mA CKE ≥ VIH,
tRAS = max 3
Operating current
(Burst read operation) ICC4R — TBD — TBD — TBD mA CKE ≥ VIH, BL = 2,
CL = 2.5 1, 2, 5,
6
Operating current
(Burst write operation) ICC4W — TBD — TBD — TBD mA CKE ≥ VIH, BL = 2,
CL = 2.5 1, 2, 5,
6
Auto Refresh current ICC5 — TBD — TBD — TBD mA tRFC = min,
Input ≤ VIL or ≥ VIH
Self refresh current ICC6 — 2 — 2 — 2 mA Input ≥ VCC – 0.2 V
Input ≤ 0.2 V
Input leakage current ILI –10 10 –10 10 –10 10 µAV
CC ≥ Vin ≥ VSS
Output leakage current ILO –10 10 –10 10 –10 10 µAV
CC ≥ Vout ≥ VSS
Output high voltage VOH VTT +
0.76 —V
TT +
0.76 —V
TT +
0.76 —VI
OH (max) = –15.2
mA
Output low voltage VOL —V
TT –
0.76 —V
TT –
0.76 —V
TT –
0.76 VI
OL (min) = 15.2 mA
Notes: 1. These ICC data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. Data/Data mask transition twice per one clock cycle.
7. The ICC data on this table are measured with regard to tCK = min in general.
HM5425161B, HM5425801B, HM5425401B Series
45
Capacitance (Ta = 25°C, VCC, VCCQ = 2.5 V ± 0.2 V)
Parameter Symbol Min Max Unit Notes
Input capacitance (Address) CI1 2.5 3.5 pF 1
Input capacitance (Command) CI2 2.5 3.5 pF 1
Data and DOS input/output capacitance (I/O) CO4 5.5 pF 1, 2
Notes: 1. These parameters are measured on conditions: f = 100 MHz, Vout = VCCQ/2, ∆Vout = 0.2 V.
2. Dout circuits are disabled.
HM5425161B, HM5425801B, HM5425401B Series
46
AC Characteristics (Ta = 0 to +70˚C, VCC, VCCQ = 2.5 V ± 0.2 V, VSS, VSSQ = 0 V)
HM5425161B/HM542581B/HM5425401B
-75A -75B -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Clock cycle time
(CAS latency = 2) tCK 7.5 15 10 15 10 15 ns 10
(CAS latency = 2.5) tCK 7 15 7.5 15 8 15 ns
Input clock high level time tCH 0.45 — 0.45 — 0.45 — tCK
Input clock low level time tCL 0.45 — 0.45 — 0.45 — tCK
CLK to DQS skew tDQSCK –0.7 0.7 –0.7 0.7 –0.8 0.8 ns 2
DATA to CLK skew tAC –0.7 0.7 –0.7 0.7 –0.8 0.8 ns 2
Dout to DQS skew tDQSQ –0.5 0.5 –0.5 0.5 –0.6 0.6 ns 3
Dout/DQS valid window t DV 0.35 — 0.35 — 0.35 — tCK 4
DQS valid window tDQSV 0.35 — 0.35 — 0.35 — tCK 4
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK
DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
Dout-High impedance delay
from CLK/CLK tHZ –0.7 0.7 –0.7 0.7 –0.8 0.8 ns 5
Dout-Low impedance delay
from CLK/CLK tLZ –0.7 0.7 –0.7 0.7 –0.8 0.8 ns 6
DQ and DM input pulse
width tDIPW 1.7 — 1.7 — 2 — ns 7
Data and data mask to data
strobe setup time tDS 0.5 — 0.5 — 0.6 — ns 8
Data and data mask to data
strobe hold time tDH 0.5 — 0.5 — 0.6 — ns 8
Clock to DQS write
preamble setup time tWPRES 0—0—0—ns
Clock to DQS write
preamble hold time tWPREH 0.25 — 0.25 — 0.25 — tCK
DQS last edge to High-Z
time (DQS write postamble) tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 9
Clock to the DQS first rising
edge for write delay tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
HM5425161B, HM5425801B, HM5425401B Series
47
HM5425161B/HM5425801B/HM5425401B
-75A -75B -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
DQS falling edge to CLK
setup time tDSS 0.2 — 0.2 — 0.2 — tCK
DQS falling edge hold time
to CLK tDSH 0.2 — 0.2 — 0.2 — tCK
DQS high pulse width
(DQS write) tDQSH 0.35 — 0.35 — 0.35 — tCK
DQS low pulse width
(DQS write) tDQSL 0.35 — 0.35 — 0.35 — tCK
Input command and
address setup time tIS 1.1 — 1.1 — 1.2 — ns 8
Input command and
address hold time tIH 1.1 — 1.1 — 1.2 — ns 8
Active command period tRC 65 — 65 — 70 — ns
Auto refresh to active/Auto
refresh command cycle tRFC 75 — 75 — 80 — ns
Active to Precharge
command period tRAS 45 120000 45 120000 50 120000 ns
Active to column command
period tRCD 20 — 20 — 20 — ns
Last data in to precharge tWR 15 — 15 — 15 — ns
Precharge to active
command period tRP 20 — 20 — 20 — ns
Active to active command
period tRRD 15 — 15 — 15 — ns
Average periodic refresh
interval tREF — 7.8 — 7.8 — 7.8 µs
HM5425161B, HM5425801B, HM5425401B Series
48
Notes. 1. On all AC measurements, we assume the test conditions shown in the next page. For timing
parameter definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CLK and CLK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or
DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as Dout transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CLK and CLK. This parameter is not referred to a specific Dout
voltage level, but specify when the device output stops driving.
6. tLZ is defined as Dout transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific Dout voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or
DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A
specific reference voltage to judge this transition is not given.
10.tCK max is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is
not assured.
11.VCC is assumed to be 2.5 V ± 0.2 V. VCC power supply variation per cycle expected to be less than
0.4 V/400 cycle.
HM5425161B, HM5425801B, HM5425401B Series
49
Test Conditions
Parameter Symbol Min Typ Max Unit
Input reference voltage VREF 1.15 1.25 1.35 V
Termination voltage VTT VREF − 0.04 VREF VREF + 0.04 V
AC input high voltage VIH (ac) VREF + 0.35 — — V
AC input low voltage VIL (ac) — — VREF − 0.35 V
AC differential input high voltage VSWING (ac) 0.7 — VCCQ + 0.6 V
AC differential cross point voltage VX (ac) VREF − 0.2 VREF VREF + 0.2 V
Input signal slew rate SLEW — 1 — V/ns
VTT
VREF
CLK
CLK
VREF
VSS
SLEW = (VIH (ac) – VIL (ac))/∆t
Measurement point
VIH
VIL
VCC
VCC
VSS
DQ
RT = 25 Ω
RS = 25 ΩCL = 30 pF
VX
∆t
tCL
tCK
tCH
VSWING
HM5425161B, HM5425801B, HM5425401B Series
50
Timing Parameter Measured in Clock Cycle
Number of clock cycle
Parameter Symbol Min Max
Write to pre-charge command delay (same bank) tWPD 3 + BL/2
Read to pre-charge command delay (same bank) tRPD BL/2
Write to read command delay (to input all data) tWRD 2 + BL/2
Burst stop command to write command delay
(CAS latency = 2) tBSTW 2
(CAS latency = 2.5) tBSTW 3
Burst stop command to DQ High-Z
(CAS latency = 2) tBSTZ 2
(CAS latency = 2.5) tBSTZ 2.5
Read command to write command delay (to output all data)
(CAS latency = 2) tRWD 2 + BL/2
(CAS latency = 2.5) tRWD 3 + BL/2
Pre-charge command to High-Z
(CAS latency = 2) tHZP 2
(CAS latency = 2.5) tHZP 2.5
Write command to data in latency tWCD 1
Write recovery tWR 2
DM to data in latency tDMD 0
Register set command to active or register set command tMRD 2
Self refresh exit to non-read command tSNR 10
Self refresh exit to read command tSRD 200
Power down entry tPDEN 1
Power down exit to command input tPDEX 1
CKE minimum pulse width tCKEPW 1
HM5425161B, HM5425801B, HM5425401B Series
51
Timing Waveforms
Command and Addresses Input Timing Definition
CLK
CLK
VREF
Command
(RAS, CAS,
WE, CS)
Address
tIS
tIS
tIH
tIH
,
!"
,
!
VREF
Read Timing Definition
CLK
CLK
DQS
High-Z
(V
TT
)V
TT
V
TT
DQ
(Dout)
t
LZ
t
RPRE
t
DQSCK
t
AC
t
DV
t
HZ
t
CK
t
CH/
t
CL
t
CL/
t
CH
Notes: 1. Specific voltage for transition from/to High-Z is not given.
2. The transition to High-Z is defined to occur when output stop driving.
3. The transition from High-Z is defined to occur when output begins driving.
*1
*1
t
DQSV
t
RPST
t
DQSV
HM5425161B, HM5425801B, HM5425401B Series
52
Write Timing Definition
CLK
CLK
DQS
DM
V
REF
V
REF
V
REF
DQ
(Din)
t
DS
t
DH
t
DQSS
t
WPREH
t
WPRES
t
DS
t
DH
t
DIPW
t
DIPW
t
DIPW
t
CK
t
DSH
t
DSS
t
DQSL
t
DQSH
t
WPST
!"#
"#
,
,
#
HM5425161B, HM5425801B, HM5425401B Series
53
Read Cycle
Bank 0
Active Bank 0
Read Bank 0
Precharge
5<=
'(/67=>?
9:
,
08?
,45;<
'/
/7>?
(0
"#)*2
CAS latency = 2
Burst length = 4
Bank0 Access
= VIH or VIL
,
Bank 0
Active Bank 0
Read Bank 0
Precharge
(018
%&,-.45
'
+,34:;
#$
$%,-4
&'./56=
:
)189
,
8
!(
#*+23
#
./67=>
)0129
29:
tIS tIH
tCH
tCK
tCL
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS
tRPRE tRPST
tDQSVtDQSV
tDV tDV
tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
RAS
A10
Address
High-Z
High-Z
CS
CKE
CLK
CLK
CAS
WE
BA
DQS,
DQSU/DQSL
DQ (output)
DM,
DMU/DML
VIH
tRCD tRAS tRP
tRC
$%+,34:;BCJKL
,
,
HM5425161B, HM5425801B, HM5425401B Series
54
Write Cycle
Bank 0
Active
,
8?
*239:
$%,-34;<
7?
-56<=
")*129
%
,-345<
%&-
'
0189
CAS latency = 2
Burst length = 4
Bank0 Access
= VIH or VIL
Bank 0
Active Bank 0
Write Bank 0
Precharge
&-.6
#$*+123:
,
89
"#*
>?
!"()01
3;<
"
#$*+,3
3:;<
078?
./67>
6=>
,&'.
!(
#$+,23:;
&'./
/7?
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
VIH
tRCD tRAS
tRC
tRP
tDQSS
tDQSL
tDQSL tWPST
tWR
CS
CLK
CLK
CKE
RAS
CAS
WE
BA
A10
Address
DQ (input)
DM,
DMU/DML
DQS,
DQSU/DQSL
(input)
tCK
tCH tCL
tDS
tDS
tDS
tDH
tDH
tDH
HM5425161B, HM5425801B, HM5425401B Series
55
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
CLK
CKE
CS
RAS
CAS
WE
BA
Address
DM,
DMU/DML
DQ (output)
8@AIJ
,
@I
<EFMN
;<DELM
6?@H
089
&'
$%-6
56>G
%-.67?G
2;<CDKL
%
b
valid code
code
tRP
Precharge
If needed Mode
register
set
Bank 3
Active Bank 3
Read
,
@HI
/78@AI
'(0
'(01
/08
&/
EFNO
FO
./67@
&
R: b C: b
VIH
Bank 3
Precharge
tMRD
High-Z
High-Z
%&
CAS latency = 2
Burst length = 4
= VIH or VIL

DQS,
DQSU/DQSL
!"
&'
*
./67?@HP
HM5425161B, HM5425801B, HM5425401B Series
56
Read/Write Cycle
%-.6?G
%.67?H
.67?@H
78?@HI
P
OP
"
R:a C:a C:bR:b C:b''
"
,
FOP
&'/08
%&.
&'./
%&./
%.
$%-.6>G
b’’
Bank 0
Active Bank 3
Active
Bank 0
Read Bank 3
Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CKE
RAS
CS
DQS,
DQSU/DQSL
CAS
WE
Address
CLK
BA
DQ (output)
DQ (input)
CLK
Bank 3
Write
tWRD
High-Z
VIH
tRWD
b
Read cycle
CAS latency = 2
Burst lenght = 4
=VIH or VIL
DM,
DMU/DML
K
!")*23:;CL
a
HM5425161B, HM5425801B, HM5425401B Series
57
Auto Refresh Cycle
$%-.
CKL
,
,
,
)*23
,
)*12:;BCK
,
,
./7@
,
,
CLM
LM
:CKL
$%
!")*123:;C
BCKL
Precharge
If needed Auto
Refresh Bank 0
Active Bank 0
Read
CLK
CLK
CKE
CS
CAS
WE
BA
Address
DM,
DMU/DML
DQ (output)
DQ (input)
RAS
/78@A
6>?GOP
,
,
,
!"#
,
,
CAS latency = 2
Burst length = 4
= VIH or VIL
VIH
tRP
A10=1 R: b C: b
b
High-Z tRC
DQS
DQSU/DQSL
HM5425161B, HM5425801B, HM5425401B Series
58
Self Refresh Cycle
&'./67?@HP
,
,
Self
refresh
entry
Self refresh
exit
High-Z
$,-5>
M
#$,45<=EFMN
%.
$
&'
&
,
,
,
'(/08
,
$,45=>EFMN
P
,
()0189B
$%
DLM
,#
CLK
CKE
CS
RAS
CAS
WE
BA
Address
DM,
DMU/DML
DQ (output)
DQ (input)
CLK
Precharge
If needed Bank 0
Active Bank 0
Read
tRP tSNR
'(0
EFNO
,
H
A10=1 R: b
,5=>F
/0
C: b
DQS
DQSU/DQSL
CAS latency = 2.5
Burst length = 4
= VIH or VIL
$
tIS tIH
tCKEPW
CKE = low
HM5425161B, HM5425801B, HM5425401B Series
59
Power Down Mode
#+,45<=EFMN
P
$%.
%&./
,
-.67?GHP
,
,
,
,
!"
$-.6>FGOP
,
,
$,-5=>EFNO
$
IJ
,
'(0
'(0
,
8@AHI
"#+
"#+
.7?@H
,
.78?@HIP
,
.78?@HIP
'
'
&/8
&'./78
&'./78
,
,
#
'/089A
,
High-Z
A10=1 R: cR: b
CLK
CKE
CS
RAS
CAS
WE
BA
Address
DM,
DMU/DML
DQ (output)
DQ (input)
QS,
QSU/QSL
CLK
Precharge
If needed Power down
entry Power
down
exit
Bank 0
Active Bank 0
Read
tPDEX
CAS latency = 2.5
Burst lenght = 4
=VIH or VIL
tPDEN
CKE = low
,
,
,
,
,
tRP
tIS tIH
tCKEPW
HM5425161B, HM5425801B, HM5425401B Series
60
Package Dimensions
HM5425161BTT/HM5425801BTT/HM5425401BTT Series (TTP-66D)
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
TTP-66D
—
—
0.53 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.13 M
0.10
0.65
66 34
133
22.22
22.72 Max
1.20 Max
10.16
0.13 ± 0.05
11.76 ± 0.20 0° – 5°
0.91 Max
*0.145 ± 0.05
0.22 ± 0.05
*0.24 ± 0.07
0.125 ± 0.04
0.50 ± 0.10
0.68
0.80
Preliminary
HM5425161B, HM5425801B, HM5425401B Series
61
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
URL NorthAmerica : http:semiconductor.hitachi.com/
Europe : http://www.hitachi-eu.com/hel/ecg
Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan : http://www.hitachi.co.jp/Sicd/indx.htm
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
For further information write to:
HM5425161B, HM5425801B, HM5425401B Series
62
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Jun. 28, 1999 Initial issue