HM5425161B Series HM5425801B Series HM5425401B Series 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword x 16-bit x 4-bank/8-Mword x 8-bit x 4-bank/ 16-Mword x 4-bit x 4-bank ADE-203-1077 (Z) Preliminary Rev. 0.0 Jun. 28, 1999 Description The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip Delay Locked Loop (DLL) can be set enable or disable. Features * * * * * * * * JEDEC standard compatible devices 2.5 V power supply SSTL-2 interface for all inputs and outputs Clock frequency: 143 MHz/133 Mhz/125 MHz/100 MHz Data inputs, outputs, and DM are synchronized with DQS 4 banks can operate simultaneously and independently Burst read/write operation Programmable burst length: 2/4/8 Burst read stop capability * Programmable burst sequence Sequential Interleave Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications. HM5425161B, HM5425801B, HM5425401B Series * Start addressing capability Even and Odd * Programmable CAS latency: 2/2.5 * 8192 refresh cycles: 7.8 s (8192 row/64 ms) * 2 variations of refresh Auto refresh Self refresh Ordering Information Type No. Frequency Package HM5425161BTT-75A HM5425161BTT-75B HM5425161BTT-10 143 MHz/133 MHz 133 MHz/100 MHz 125 MHz/100 MHz 400-mill 66-pin plastic TSOP II (TTP-66D) HM5425801BTT-75A HM5425801BTT-75B HM5425801BTT-10 143 MHz/133 MHz 133 MHz/100 MHz 125 MHz/100 MHz HM5425401BTT-75A HM5425401BTT-75B HM5425401BTT-10 143 MHz/133 MHz 133 MHz/100 MHz 125 MHz/100 MHz 2 HM5425161B, HM5425801B, HM5425401B Series Pin Arrangement (HM5425161B) 66-pin TSOP VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 NC VCCQ DQSL NC VCC NC DML WE CAS RAS CS NC A14 A13 A10/AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 NC VSSQ DQSU NC VREF VSS DMU CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS (Top view) 3 HM5425161B, HM5425801B, HM5425401B Series Pin Description Pin name Function A0 to A14 Address input Row address A0 to A12 Column address A0 to A8 Bank select address A13 (BA1)/A14 (BA0) DQ0 to DQ15 Data-input/output DQSU Upper input and output data strobe DQSL Lower input and output data strobe CS Chip select RAS Row address strobe command CAS Column address strobe command WE Write enable DMU Upper byte input mask DML Lower byte input mask CLK Clock input CLK Differential clock input CKE Clock enable VREF Input reference voltage VCC Power for internal circuit VSS Ground for internal circuit VCCQ Power for DQ circuit VSSQ Ground for DQ circuit NC No connection 4 HM5425161B, HM5425801B, HM5425401B Series Pin Arrangement (HM5425801B) 66-pin TSOP VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC NC VCCQ NC NC VCC NC NC WE CAS RAS CS NC A14 A13 A10/AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC NC VSSQ DQS NC VREF VSS DM CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS (Top view) 5 HM5425161B, HM5425801B, HM5425401B Series Pin Description Pin name Function A0 to A14 Address input Row address A0 to A12 Column address A0 to A9 Bank select address A13 (BA1)/A14 (BA0) DQ0 to DQ7 Data-input/output DQS Input and output data strobe CS Chip select RAS Row address strobe command CAS Column address strobe command WE Write enable DM Input mask CLK Clock input CLK Differential clock input CKE Clock enable VREF Input reference voltage VCC Power for internal circuit VSS Ground for internal circuit VCCQ Power for DQ circuit VSSQ Ground for DQ circuit NC No connection 6 HM5425161B, HM5425801B, HM5425401B Series Pin Arrangement (HM5425401B) 66-pin TSOP VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC NC VCCQ NC NC VCC NC NC WE CAS RAS CS NC A14 A13 A10/AP A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC NC VSSQ DQS NC VREF VSS DM CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS (Top view) 7 HM5425161B, HM5425801B, HM5425401B Series Pin Description Pin name Function A0 to A14 Address input Row address A0 to A12 Column address A0 to A9, A11 Bank select address A13 (BA1)/A14 (BA0) DQ0 to DQ3 Data-input/output DQS Output data strobe CS Chip select RAS Row address strobe command CAS Column address strobe command WE Write enable DM Input mask CLK Clock input CLK Differential clock input CKE Clock enable VREF Input reference voltage VCC Power for internal circuit VSS Ground for internal circuit VCCQ Power for DQ circuit VSSQ Ground for DQ circuit NC No connection 8 HM5425161B, HM5425801B, HM5425401B Series Block Diagram Address (A0 to A14) Address register AY0 to AY11 Column address buffer AX0 to AX12 AX13, AX14 Bank select Refresh counter Row address buffer A0 to A14 Column address counter *1 Bank 1 *1 Bank 2 *1 Row decoder Column decoder Sense amplifier & I/O bus Bank 0 Row decoder Column decoder Sense amplifier & I/O bus Row decoder Column decoder Sense amplifier & I/O bus Column decoder Sense amplifier & I/O bus Row decoder Bank 3 *1 Control logic & timing generator Mode register CLK CLK CKE CS RAS CAS WE DM, DMU/DML Input buffer DQS, DQSU/DQSL Output buffer DQS buffer DLL DQ*2 Notes: 1. 8192 row x 512 column x 16 bit: HM5425161B 8192 row x 1024 column x 8 bit: HM5425801B 8192 row x 2048 column x 4 bit: HM5425401B 2. DQ0 to DQ15: HM5425161B DQ0 to DQ7: HM5425801B DQ0 to DQ3: HM5425401B 9 HM5425161B, HM5425801B, HM5425401B Series Pin Functions (1) CLK, CLK (input pin): The CLK and the CLK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CLK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CLK and the CLK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CLK and the CLK. CS (input pin): When CS is Low, commands and data can be input. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CLK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B) is loaded via the A0 to the A9 at the cross point of the CLK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by A13 (BA1)/A14 (BA0) is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. A13 (BA1)/A14 (BA0) (input pin): A13 (BA1)/A14 (BA0) are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If A13 = Low and A14 = Low, bank 0 is selected. If A13 = High and A14 = Low, bank 1 is selected. If A13 = Low and A14 = High, bank 2 is selected. If A13 = High and A14 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least, that is, if CKE changes at the cross point of the CLK rising edge and the VREF level with proper setup time tIS, by the next CLK rising edge CKE level must be kept with proper hold time tIH. 10 HM5425161B, HM5425801B, HM5425401B Series Pin Functions (2) DM, DMU/DML (input pins): DM (the HM5425801B and the HM5425401B), DMU/DML (the HM5425161B) are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and VREF. DMU/DML provide the byte mask function. When DMU/DML = High, the data input at the same timing are masked while the internal burst counter will be count up. DML controls the lower byte (DQ0 to DQ7) and DMU controls the upper byte (DQ8 to DQ15) of write data. DQ0 to DQ15 (input and output pins): Data are input to and output from these pins (the DQ0 to the DQ15; the HM5425161B, the DQ0 to the DQ7; the HM5425801B, the DQ0 to the DQ3; the HM5425401B). DQS, DQSU/DQSL (input and output pin): DQS (the HM5425801B and the HM5425401B ), DQSU/DQSL (the HM5425161B) provide the read data strobes (as output) and the write data strobes (as input). DQSL is the lower byte (DQ0 to DQ7) data strobe signal, DQSU is the upper byte (DQ8 to DQ15) data strobe signal. VCC and V CCQ (power supply pins): 2.5 V is applied. (VCC is for the internal circuit and V CCQ is for the output buffer.) VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) 11 HM5425161B, HM5425801B, HM5425401B Series Command Operation Command Truth Table The HM5425161B, the HM54 25801B and HM5425401B recognize the following commands specified by the CS, RAS, CAS, WE and address pins. All other combinations than those in the table below are illegal. CKE CS RAS CAS WE BA1 BA0 AP Address x H x x x x x x x H x L H H H x x x x BST H x L H H L x x x x Column address and read command READ H x L H L H V V L V Read with auto-precharge READA H x L H L H V V H V Column address and write command WRIT H x L H L L V V L V Write with auto-precharge WRITA H x L H L L V V H V Row address strobe and bank active ACTV H x L L H H V V V V Precharge select bank PRE H x L L H L V V L x Precharge all bank PALL H x L L H L x x H x Refresh REF H H L L L H x x x x SELF H L L L L H x x x x MRS H x L L L L L L L V EMRS H x L L L L L H L V Command Symbol n-1 n Ignore command DESL H No operation NOP Burst stop in read command Mode register set Notes: 1. H: VIH. L: V IL. x: V IH or VIL. V: Valid address input 2. The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least. Ignore command [DESL]: When CS is High at the cross point of the CLK rising edge and the VREF level, every input are neglected and internal status is held. No operation [NOP]: As long as this command is input at the cross point of the CLK rising edge and the VREF level, address and data input are neglected and internal status is held. Burst stop in read operation [BST]: This command stops a burst read operation, which is not applicable for a burst write operation. Column address strobe and read command [READ]: This command starts a read operation. The start address of the burst read is determined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B) and the bank select address (BA). After the completion of the read operation, the output buffer becomes High-Z. 12 HM5425161B, HM5425801B, HM5425401B Series Read with auto-precharge [READA]: This command starts a read operation. After completion of the read operation, precharge is automatically executed. Column address strobe and write command [WRIT]: This command starts a write operation. The start address of the burst write is determined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B) and the bank select address (BA). Write with auto-precharge [WRITA]: This command starts a write operation. After completion of the write operation, precharge is automatically executed. Row address strobe and bank activate [ACTV]: This command activates the bank selected by A13/A14 (BA) and determines a row address (AX0 to AX12). When A13 = A14 = Low, bank 0 is activated. When A13 = High and A14 = Low, bank 1 is activated. When A13 = Low and A14 = High, bank 2 is activated. When A13 = A14 = High, bank 3 is activated. Precharge selected bank [PRE]: This command starts a pre-charge operation for the bank selected by A13/A14. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another is self-refresh. For details, refer to the CKE truth table section. Mode register set/Extended mode register set [MRS/EMRS]: The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins (the A0 to the A14) in the mode register set cycle. For details, refer to "Mode register and extended mode register set". 13 HM5425161B, HM5425801B, HM5425401B Series CKE Truth Table CKE Current state Command n-1 n CS RAS CAS WE Address Notes Idle Auto-refresh command (REF) H H L L L H x 2 Idle Self-refresh entry (SELF) H L L L L H x 2 Idle Power down entry (PDEN) H L L H H H x H L H x x x x L H L H H H x L H H x x x x L H L H H H x L H H x x x x Self refresh Power down Self refresh exit (SELFX) Power down exit (PDEX) Notes: 1. H: V IH. L: VIL. x: VIH or VIL. 2. All the banks must be in IDLE before executing this command. 3. The CKE level must be kept for 1 CLK cycle (= tCKEPW) at least. Auto-refresh command [REF]: This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh contoroller. The average refresh cycle is 7.8 s. The output buffer becomes High-Z after auto-refresh start. Precharge has been completed automatically after the auto-refresh. The ACTV or MRS command can be issued tRFC after the last auto-refresh command. Self-refresh entry [SELF]: This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the self-refresh operation, all ROW addresses are repeated refreshing by the internal refresh contoroller. A self-refresh is terminated by a self-refresh exit command. Power down mode entry [PDEN]: tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not disable DLL. Self-refresh exit [SELFX]: This command is executed to exit from self-refresh mode. 10 cycles (= tSNR ) after [SELFX], non-read commands can be executed. For read operation, wait for 200 cycles (= tSRD) after [SELFX] to adjust Dout timing by DLL. After the exit, within 7.8 s input auto-refresh command. Power down exit [PDEX]: The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. 14 HM5425161B, HM5425801B, HM5425401B Series Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM. Function Truth Table (1) Current state 2 Precharging* CS RAS CAS WE Address Command Operation Next state H x x x x DESL NOP ldle L H H H x NOP NOP L x L L L 3 Idle* H H H L L H L BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA -- 12 -- 12 -- 12 ILLEGAL* ILLEGAL* ILLEGAL* L L H H BA, RA ACTV ILLEGAL* -- L L H L BA, A10 PRE, PALL NOP ldle L L L x x ILLEGAL -- H x x x x DESL NOP ldle L H H H x NOP NOP L x L L L Refresh (auto-refresh)*4 H ldle 12 H H H H L L H L BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA ldle 12 -- 12 -- 12 -- 12 ILLEGAL* ILLEGAL* ILLEGAL* L L H H BA, RA ACTV ILLEGAL* Activating L L H L BA, A10 PRE, PALL NOP ldle L L L H x REF, SELF Refresh/ Selfrefresh*13 ldle/ Selfrefresh L L L L MODE MRS Mode register set*13 ldle H x x x x DESL NOP ldle L H H H x NOP NOP ldle H H H L x BST ILLEGAL -- L H L x x ILLEGAL -- L L x x x ILLEGAL -- 15 HM5425161B, HM5425801B, HM5425401B Series Function Truth Table (2) Current state Activating* 5 CS RAS CAS WE Address Command Operation Next state H x x x x DESL NOP Active L H H H x NOP NOP L x L L L L Active* 7 Read* 16 6 H H H L H L L H H L H BST BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA BA, RA ACTV PRE, PALL Active 12 -- 12 -- 12 -- 12 -- 12 ILLEGAL* -- ILLEGAL -- ILLEGAL* ILLEGAL* ILLEGAL* ILLEGAL* L L H L BA, A10 L L L x x H x x x x DESL NOP Active L H H H x NOP NOP Active L H H L x BST ILLEGAL Active L H L H BA, CA, A10 READ/READA Starting read operation Read/READ A L H L L BA, CA, A10 WRIT/WRITA Starting write operation Write recovering/ precharging L L H H BA, RA ACTV ILLEGAL*12 -- L L H L BA, A10 PRE, PALL Pre-charge Idle L L L x x ILLEGAL -- H x x x x DESL NOP Active L H H H x NOP NOP Active L H H L x BST BST Active L H L H BA, CA, A10 READ/READA Active L H L L BA, CA, A10 WRIT/WRITA Interrupting burst read operation to start new read ILLEGAL*14 12 -- L L H H BA, RA ACTV ILLEGAL* -- L L H L BA, A10 PRE, PALL Interrupting burst read operation to start pre-charge Precharging L L L x x ILLEGAL -- HM5425161B, HM5425801B, HM5425401B Series Function Truth Table (3) RAS CAS WE Address Command Operation Next state Read with auto- H pre-charge*8 x x x x DESL NOP Precharging L H H H x NOP NOP Precharging L H H L x BST ILLEGAL -- L H L H BA, CA, A10 READ/READA ILLEGAL -- L H L L BA, CA, A10 WRIT/WRITA ILLEGAL Current state CS L 9 Write* Write recovering* 10 L H H BA, RA ACTV PRE, PALL -- 12 -- 12 ILLEGAL* -- ILLEGAL -- ILLEGAL* L L H L BA, A10 L L L x x H x x x x DESL NOP Write recovering L H H H x NOP NOP Write recovering L H H L x BST ILLEGAL -- L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 WRIT/WRITA L L H H BA, RA ACTV L L H L BA, A10 PRE, PALL L L L x x H x x x x L H H H L H H L H L L Interrupting burst Read/ReadA write operation to start read operation. Write/WriteA Interrupting burst write operation to start new write operation. ILLEGAL*12 -- Interrupting write operation to start pre-charge. Idle ILLEGAL -- DESL NOP Active x NOP NOP Active L x BST ILLEGAL -- L H BA, CA, A10 READ/READA Starting read operation. Read/ReadA H L L BA, CA, A10 WRIT/WRITA Write/WriteA L H H BA, RA Starting new write operation. ILLEGAL*12 L L H L BA, A10 L L L x x ACTV PRE/PALL 12 -- ILLEGAL* -- ILLEGAL -- 17 HM5425161B, HM5425801B, HM5425401B Series Function Truth Table (4) RAS CAS WE Address Command Operation Next state Write with auto- H pre-charge*11 x x x x DESL NOP Precharging L H H H x NOP NOP Precharging L H H L x BST ILLEGAL -- L H L H BA, CA, A10 READ/READA ILLEGAL -- L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL Current state CS L L H H BA, RA L L H L BA, A10 L L L x x ACTV PRE, PALL -- 12 -- 12 ILLEGAL* -- ILLEGAL -- ILLEGAL* H: VIH. L: V IL. x: VIH or VIL. The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. The DDR SDRAM reachs "IDLE" state tRP after precharge command is issued. The DDR SDRAM is in "Refresh" state for tRC after auto-refresh command is issued. The DDR SDRAM is in "Activating" state for tRCD after ACTV command is issued. The DDR SDRAM is in "Active" state after "Activating" is completed. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 8. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been output and DQ output circuits are turned off. 9. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input. 10. The DDR SDRAM is in "Write recovering" for tWR after the last data are input. 11. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input. 12. This command may be issued for other banks, depending on the state of the banks. 13. All banks must be in "IDLE". 14. Before executing a write command to stop the preceding burst read operation, BST command must be issued. Notes: 1. 2. 3. 4. 5. 6. 7. 18 HM5425161B, HM5425801B, HM5425401B Series Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MRS MODE REGISTER SET REFRESH IDLE *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE ACTIVE POWER DOWN CKE_ CKE ROW ACTIVE WRITE Write WRITE READ WRITE WITH AP READ WRITE READ WITH AP WRITE WITH AP READ WITH AP WRITE WITH AP Read READ READ WITH AP PRECHARGE WRITEA READA PRECHARGE POWER APPLIED POWER ON PRECHARGE PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 19 HM5425161B, HM5425801B, HM5425401B Series Operation of the DDR SDRAM Power-up Sequence The following sequence is recommended for Power-up. (1) Apply power and attempt to maintain CKE at an LVCMOS low state (all other inputs may be undefined). Apply VCC before or at the same time as VCCQ. Apply VCCQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200 s. (3) After the minimum 200 s of stable power and clock (CLK, CLK), apply NOP and take CKE high. (4) Issue precharge all command for the device. (5) Issue EMRS to enable DLL. (6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of clock input is required to lock the DLL after every DLL reset). (7) Issue precharge all command for the device.*1 (8) Issue 2 or more auto-refresh commands.*1 (9) Issue a mode register set command to initialize device operation. Note: 1. Sequence of (7) and (8) may be reversed. Power-up Sequence after CKE Goes High Command PALL EMRS 2 cycles (min) MRS 2 cycles (min) DLL enable PALL 2 cycles (min) REF REF tRP DLL reset 200 cycles (min) 20 REF tRC MRS tRC Any command 2 cycles (min) HM5425161B, HM5425801B, HM5425401B Series Mode Register and Extended Mode Register Set There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A14 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A14 during mode register set cycles. A14 (BA0) and A13 (BA1) determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Remind that no other parameters are shown in the table bellow are allowed to input to the registers. Mode Register Set [MRS] (A14 = 0, A13 = 0) A14 A13 A12 (BA0) (BA1) 0 0 A11 A10 A9 0 0 0 0 A8 A7 DR 0 A6 A5 A4 LMODE A3 A2 A1 BT A0 BL MRS A8 DLL Reset A6 A5 A4 CAS Latency 2 0 1 0 0 No 1 1 Yes 1 2.5 0 A3 Burst Type 0 Sequential 1 Interleave A2 A1 A0 Burst Length BT=0 BT=1 2 2 0 0 1 0 1 0 4 4 0 1 1 8 8 Extended Mode Register Set [EMRS] (A14 = 1, A13 = 0) A14 A13 A12 A11 A10 A9 (BA0) (BA1) 1 0 0 0 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 DLL EMRS A0 DLL Control 0 DLL Enable 1 DLL Disable 21 HM5425161B, HM5425801B, HM5425401B Series Burst Operation The burst type (BT) and the first three bits of the column address determines the order of a data out. Burst length = 2 Burst length = 4 Starting Ad. Addressing(decimal) A0 Sequence Interleave Starting Ad. Addressing(decimal) A1 A0 Sequence Interleave 0 0, 1, 0, 1, 0 0 0, 1, 2, 3, 0, 1, 2, 3, 1 1, 0, 1, 0, 0 1 1, 2, 3, 0, 1, 0, 3, 2, 1 0 2, 3, 0, 1, 2, 3, 0, 1, 1 1 3, 0, 1, 2, 3, 2, 1, 0, Burst length = 8 Addressing(decimal) Starting Ad. 22 A2 A1 A0 Sequence Interleave 0 0 0 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0 0 1 1, 2, 3, 4, 5, 6, 7, 0, 1, 0, 3, 2, 5, 4, 7, 6, 0 1 0 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 6, 7, 4, 5, 0 1 1 3, 4, 5, 6, 7, 0, 1, 2, 3, 2, 1, 0, 7, 6, 5, 4, 1 0 0 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 1 0 1 5, 6, 7, 0, 1, 2, 3, 4, 5, 4, 7, 6, 1, 0, 3, 2, 1 1 0 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 2, 3, 0, 1, 1 1 1 7, 0, 1, 2, 3, 4, 5, 6, 7, 6, 5, 4, 3, 2, 1, 0, HM5425161B, HM5425801B, HM5425401B Series Read/Write Operations Bank active: A read or a write operation begins with the bank active command [ACTV]. The bank active command determines a bank address (AX14, AX13) and a row address (AX0 to AX12). For the bank and the row, a read or a write command can be issued t RCD after the ACTV is issued. Read operation: The burst length (BL), the CAS latency (CL) and the burst type (BT) of the mode register are referred when a read command is issued. The burst length (BL) determines the length of a sequential output data by the read command which can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B), the bank select address (AX14, AX13) which are loaded via the A0 to A14 pins in the cycle when the read command is issued. The data output timing are characterized by CL (2 or 2.5) and tAC . The read burst start CL * tCK + tAC (ns) after the clock rising edge where the read command are latched. The DDR SDRAM output the data strobe through DQS or DQSU/DQSL simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS or the DQSU/DQSL are driven Low from VTT level. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is referred as read postamble. Read Operation (Burst Length) t0 CLK CLK t1 t2 t3 t4 t5 t6 t7 t8 tRCD Command Address NOP ACTV Row NOP READ NOP Column tRPRE BL = 2 BL = 4 D1 tRPST D0 D1 D2 D3 !" DQS* Dout D0 BL = 8 DQS*:DQS,DUSU/DQSL D0 D1 D2 D3 D4 D5 D6 D7 CAS latency = 2 BL: Burst length 23 HM5425161B, HM5425801B, HM5425401B Series Read Operation (CAS Latency) t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 CLK CLK Command Read NOP tRPRE tRPST VTT DQS CL = 2 tAC,tDQSCK D0 DQ D1 D2 VTT D3 tRPRE tRPST DQS CL = 2.5 tAC,tDQSCK DQ 24 D0 D1 D2 D3 VTT VTT # HM5425161B, HM5425801B, HM5425401B Series Write operation: The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command which can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to AY9, AY11; the HM5425401B), the bank select address (AX14, AX13) which are loaded via the A0 to A14 pins in the cycle when the write command is issued. DQS, DQSU/DQSL should be input as the strobe for the input-data and DM, DMU/DML as well during burst operation. tWPREH prior to the first rising edge of the DQS, the DQSU/DQSL should be set to Low and tWPST after the last falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as wrtie postamble. Write Operation t0 t1 t2 t3 t3.5 t4 t5 t6 t7 t8 !"# CLK CLK tRCD Command Address NOP ACTV Row NOP WRITE NOP Column tWPREH tWPRES BL = 2 in0 in1 tWPST DQS* Din BL = 4 BL = 8 DQS*:DQS,DQSU/DQSL in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in6 in7 BL: Burst length 25 HM5425161B, HM5425801B, HM5425401B Series Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. Burst Stop during a Read Operation t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 CLK CLK Command Read BST NOP tBSTZ 2 cycles DQS CL = 2 DQ D0 D1 tBSTZ 2.5 cycles DQS CL = 2.5 DQ D0 D1 CL: CAS latency 26 HM5425161B, HM5425801B, HM5425401B Series Auto Precharge Read with auto-precharge: The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRCD for READA should be determined so that tRC (ACTV to ACTV) spec. is obeyed when READA is issued successively after a bank active command, that is tRCD (READA) tRC (min.)-tRP (min.)-tRPD . A column command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge command does not limit row commands execution for other bank. CLK CLK tRAS (min) tRCD (min) Command ACTV tRP (min) tRPD 2 cycles (= BL/2) READA NOP ACTV DQS, DQSU/DQSL DQ tAC,tDQSCK Note: Internal auto-precharge starts at the timing indicated by " D0 D1 D2 D3 ". 27 # HM5425161B, HM5425801B, HM5425401B Series Write with auto-precharge: The precharge is automatically performed after completing a burst write operation. The precharge operation is started tWPD (= BL/ 2 + 3) cycles after WRITA command issued. t RCD for WRITA should be determined so that tRC (ACTV to ACTV) spec. is obeyed when WRITA is issued successively after a bank active command, that is tRCD (WRITA) tRC(min.)-tRP(min.)-tWPD . A column command to the other active command can be issued the next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row commands execution for other bank. Burst Write (Burst Length = 4) CLK CLK tRAS (min) tRP tRCD (min) Command ACTV NOP WRITA NOP ACTV tWPD BL/2 + 3 cycles DM, DMU/DML DQS, DQSU/DQSL DQ D1 D2 Note: Internal auto-precharge starts at the timing indicated by " 28 D3 ". D4 Burst length = 4 HM5425161B, HM5425801B, HM5425401B Series Command Intervals A Read command to the consecutive Read command Interval Destination row of the consecutive read command Bank address Row address State Operation 1. Same Same ACTIVE The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. 2. Same Different -- Precharge the bank to interrupt the preceding read operation. t RP after the precharge command, issue the ACTV command. t RCD after the ACTV command, the consecutive read command can be issued. See `A read command to the consecutive precharge interval' section. 3. Different Any ACTIVE The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. IDLE Precharge the bank without interrupting the preceding read operation. t RP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive read command can be issued. READ to READ Command Interval (same ROW address in the same bank) t0 t1 t2 t3 ACTV NOP READ READ t4 t5 t6 t7 t8 CLK CLK Command Address Row NOP Column A Column B BA Dout A0 Column = A Read Column = B Read A1 Column = A Dout B0 B1 B2 B3 Column = B Dout DQS, DQSU/DQSL Bank0 Active CAS latency = 2 Burst length = 4 Bank0 29 ! HM5425161B, HM5425801B, HM5425401B Series READ to READ Command Interval (different bank) t0 t1 t2 t3 t4 t5 Command ACTV NOP ACTV NOP READ READ Address Row0 t6 t7 t8 t9 CLK CLK Row1 NOP Column A Column B BA Dout A0 Column = A Column = B Read Read A1 Bank0 Dout B0 B1 B2 B3 Bank3 Dout DQS, DQSU/DQSL Bank0 Active 30 Bank3 Active Bank0 Read Bank3 Read CAS latency = 2 Burst length = 4 ! HM5425161B, HM5425801B, HM5425401B Series A Write command to the consecutive Write command Interval: Destination row of the consecutive write command Bank address Row address State Operation 1. Same Same ACTIVE The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. 2. Same Different -- Precharge the bank to interrupt the preceding write operation. t RP after the precharge command, issue the ACTV command. t RCD after the ACTV command, the consecutive write command can be issued. See `A write command to the consecutive precharge interval' section. 3. Different Any ACTIVE The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. IDLE Precharge the bank without interrupting the preceding write operation. t RP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive write command can be issued. WRITE to WRITE Command Interval (same ROW address in the same bank) t0 t1 t2 t3 ACTV NOP WRIT WRIT t4 t5 t6 t7 t8 CLK CLK Command Address Row NOP Column A Column B BA Din A0 A1 Column = A Write B0 B1 B2 B3 Column = B Write DQS, DQSU/DQSL Bank0 Active Burst length = 4 Bank0 31 !"# HM5425161B, HM5425801B, HM5425401B Series WRITE to WRITE Command Interval (different bank) t0 t1 t2 t3 t4 Command ACTV NOP ACTV WRIT WRIT Address Row0 t5 t6 t7 t8 t9 CLK CLK Row1 NOP Column A Column B BA Din A0 A1 Bank0 Write B0 B1 B2 B3 Bank3 Write DQS, DQSU/DQSL Bank0 Active 32 Bank3 Active Burst length = 4 Bank0, 3 HM5425161B, HM5425801B, HM5425401B Series A Read command to the consecutive Write command interval with the BST command Destination row of the consecutive write command Bank address 1. Same 2. Same 3. Different Row address State Operation Same ACTIVE Issue the BST command. t BSTW ( t BSTZ) after the BST command, the consecutive write command can be issued. Different -- Precharge the bank to interrupt the preceding read operation. t RP after the precharge command, issue the ACTV command. t RCD after the ACTV command, the consecutive write command can be issued. See `A read command to the consecutive precharge interval' section. Any ACTIVE Issue the BST command. t BSTW ( tBSTZ) after the BST command, the consecutive write command can be issued. IDLE Precharge the bank independently of the preceding read operation. t RP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive write command can be issued. READ to WRITE Command Interval CLK CLK Command t0 t1 t2 t3 READ BST NOP WRIT t4 t5 t6 t7 t8 NOP tBSTW ( tBSTZ) DM, DMU/DML tBSTZ (= CL) DQ Q0 Q1 D0 D1 D2 D3 High-Z DQS, DQSU/DQSL OUTPUT INPUT Burst Length = 4 CAS Latency= 2 33 , ! HM5425161B, HM5425801B, HM5425401B Series A Write command to the consecutive Read command interval: To complete the burst operation Destination row of the consecutive read command Bank address Row address State Operation 1. Same Same ACTIVE To complete the burst operation, the consecutive read command should be performed t WRD (= BL/ 2 + 2) after the write command. 2. Same Different -- Precharge the bank t WRD after the preceding write command. tRP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive read command can be issued. See `A read command to the consecutive precharge interval' section. 3. Different Any ACTIVE To complete a burst operation, the consecutive read command should be performed t WRD (= BL/ 2 + 2) after the write command. IDLE Precharge the bank independently of the preceding write operation. t RP after the precharge command, issue the ACTV command. tRCD after the ACTV command, the consecutive read command can be issued. WRITE to READ Command Interval t0 t1 t2 CLK CLK Command WRIT NOP t3 t4 READ t5 t6 NOP tWRD (min) BL/2 + 2 cycle DM, DMU/DML DQ D0 D1 D2 DQS, DQSU/DQSL INPUT D3 Q0 Q1 Q2 OUTPUT BL = 4 CL = 2 34 , HM5425161B, HM5425801B, HM5425401B Series A Write command to the consecutive Read command interval: To interrupt the write operation Destination row of the consecutive read command Bank address 1. Same 2. Same 3. Different Note: Row address State Operation Same ACTIVE DM, DMU/DML must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM, DMU/DML is not necessary. Different -- --* 1 Any ACTIVE DM, DMU/DML must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM, DMU/DML is not necessary. IDLE --* 1 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case. WRITE to READ Command Interval (Samebank, same ROW address) [WRITE to READ delay = 1 clock cycle] CLK CLK Command t0 t1 WRIT READ 1 cycle DM, DMU/DML DQ D0 t2 t3 t4 t5 t6 t7 t8 NOP CL=2 D1 D2 Q0 Q1 Q2 Q3 High-Z High-Z DQS, DQSU/DQSL Data masked by read command BL = 4 CL= 2 35 " ! , , , HM5425161B, HM5425801B, HM5425401B Series [WRITE to READ delay = 2 clock cycle] t0 t1 t2 WRIT NOP READ t3 t4 t5 t6 t7 t8 CLK CLK Command 2 cycle NOP CL=2 DM, DMU/DML DQ D0 D1 D2 Q0 D3 Q1 Q2 High-Z Q3 High-Z DQS, DQSU/DQSL Data masked by DM BL = 4 CL= 2 Data masked by read command [WRITE to READ delay = 3 clock cycle] t0 t1 t2 t3 t4 t5 t6 t7 t8 CLK CLK Command WRIT NOP READ 3 cycle NOP CL=2 DM, DMU/DML DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3 DQS, DQSU/DQSL Data masked by DM 36 BL = 4 CL= 2 HM5425161B, HM5425801B, HM5425401B Series A Read command to the consecutive Precharge command interval (same bank): To output all data: To complete a burst read opeartion and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 2, Burst Length = 4 t0 t1 t2 t3 t4 READ NOP PRE/ PALL t5 t6 t7 t8 t7 t8 CLK CLK Command NOP Dout A0 NOP A1 A2 A3 DQS, DQSU/DQSL tRPD = BL/2 CAS Latency = 2.5, Burst Length = 4 t0 t1 t2 t3 READ NOP PRE/ PALL t4 t5 t6 CLK CLK Command NOP Dout NOP A0 A1 A2 A3 DQS, DQSU/DQSL tRPD = BL/2 37 HM5425161B, HM5425801B, HM5425401B Series READ to PRECHARGE Command Interval (same bank): To stop output data A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become HighZ tHZP (= CL) after the precharge command. CAS Latency = 2, Burst Length = 2, 4, 8 t0 t1 t2 t3 t4 READ PRE/PALL t5 t6 t7 t8 CLK CLK Command NOP NOP High-Z Dout A0 A1 DQS, DQSU/DQSL High-Z tHZP = CL + 1 CAS Latency = 2.5, Burst Length = 2, 4, 8 t0 t1 t2 t3 t4 t5 t6 t7 t8 CLK CLK Command NOP NOP READ PRE/PALL CL = 2.5 Dout DQS, DQSU/DQSL A1 High-Z tHZP = CL + 1 38 High-Z A0 !" , HM5425161B, HM5425801B, HM5425401B Series A Write command to the consecutive Precharge command interval (same bank): The minimum interval tWPD ((BL/ 2 + 3) cycles) is necessary between the write command and the precharge command. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 t0 t1 t2 t3 t4 t5 t6 t7 CLK CLK Command WRIT NOP PRE/PALL NOP tWPD BL/2 +3 cycles tWR DM, DMU/DML DQS, DQSU/DQSL Din A0 A1 A2 A3 Last data input 39 ,, HM5425161B, HM5425801B, HM5425401B Series Bank active command interval: Destination row of the consecutive ACTV command Bank address Row address State Operation 1. Same Any ACTIVE Two successive ACTV commands can be issued at t RC interval. In between two successive ACTV operations, precharge command should be executed. 2. Different Any ACTIVE Prechage the bank. t RP after the precharge command, the consecutive ACTV command can be issued. IDLE t RRD after an ACTV command, the next ACTV command can be issued. Bank Active to Bank Active !"# CLK CLK Command Address ACTV ACTV ACTV ROW: 0 ROW: 1 NOP PRE NOP ACTV NOP ROW: 0 BA Bank0 Active tRRD Bank3 Active Bank0 Precharge Bank0 Active tRC Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tMRD . CLK CLK Command Address MRS NOP CODE BS and ROW Mode Register Set tMRD 40 ACTV Bank3 Active NOP HM5425161B, HM5425801B, HM5425401B Series DMU/DML Control (HM5425161B) DMU can mask upper byte of input data. DML can mask lower byte of input data. By setting DMU/DML to Low, data can be written. When DMU/DML is set to High, the corresponding data is not written, and the previous data is held. The latency between DMU/DML input and enabling/disabling mask function is 0. DM Control (HM5425801B/HM5425401B) DM can mask input data. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0. t1 t2 t3 t4 t5 t6 DQS, DQSU/DQSL DQ Mask Mask DM, DMU/DML Write mask latency = 0 41 HM5425161B, HM5425801B, HM5425401B Series Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to V ss VT -1.0 to +4.6 V 1 Supply voltage relative to VSS VCC, VCCQ -1.0 to +4.6 V 1 Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Note: 1. Refer to VSS . DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VCC, VCCQ 2.3 2.5 2.7 V 1, 2 VSS , VSSQ 0 0 0 V Input reference voltage VREF 1.15 1.25 1.35 V 1 Termination voltage VTT VREF - 0.04 VREF VREF + 0.04 V 1 DC Input high voltage VIH VREF + 0.18 -- VCCQ + 0.3 V 1, 3 DC Input low voltage VIL -0.3 -- VREF - 0.18 V 1, 4 DC Input signal voltage VIN (dc) -0.3 -- VCCQ + 0.3 V 5 DC differential input voltage VSWING (dc) 0.36 -- VCCQ + 0.6 V 6 Notes: 1. 2. 3. 4. 5. 6. 42 All parameters are referred to VSS , when measured. VCCQ must be lower than or equal to VCC. VIH is allowed to exceed VCC up to 4.6 V for the period shorter than or equal to 5 ns. VIL is allowed to outreach below VSS down to -1.0 V for the period shorter than or equal to 5 ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching. HM5425161B, HM5425801B, HM5425401B Series DC Characteristics (Ta = 0 to +70C, VCC , VCCQ = 2.5 V 0.2 V, VS S, VSSQ = 0 V) (HM5425161B) HM5425161B -75A -75B -10 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Operating current (ACTV-PRE) I CC0 -- TBD -- TBD -- TBD mA CKE VIH, t RC = min 1, 2, 5 Operating current (ACTV-READ-PRE) I CC1 -- TBD -- TBD -- TBD mA CKE VIH, BL = 2, CL = 2.5, tRC = min 1, 2, 5 Idle power down standby current I CC2P -- TBD -- TBD -- TBD mA CKE V IL 4 Idle standby current I CC2N -- TBD -- TBD -- TBD mA CKE VIH, CS VIH 4 Active power down standby current I CC3P -- TBD -- TBD -- TBD mA CKE V IL 3 Active standby current I CC3N -- TBD -- TBD -- TBD mA CKE VIH, t RAS = max 3 Operating current I CC4R (Burst read operation) -- TBD -- TBD -- TBD mA CKE VIH, BL = 2, CL = 2.5 1, 2, 5, 6 Operating current I CC4W (Burst write operation) -- TBD -- TBD -- TBD mA CKE VIH, BL = 2, CL = 2.5 1, 2, 5, 6 Auto refresh current I CC5 -- TBD -- TBD -- TBD mA t RFC = min, Input VIL or VIH Self refresh current I CC6 -- 2 -- 2 -- 2 mA Input VCC - 0.2 V Input 0.2 V Input leakage current I LI -10 10 -10 10 -10 10 A VCC Vin V SS Output leakage current I LO -10 10 -10 10 -10 10 A VCC Vout VSS Output high voltage VOH VTT + -- 0.76 V I OH (max) = -15.2 mA Output low voltage VOL -- Notes. 1. 2. 3. 4. 5. 6. 7. VTT + -- 0.76 VTT - -- 0.76 VTT + -- 0.76 VTT - -- 0.76 VTT - V 0.76 Notes I OL (min) = 15.2 mA These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The I CC data on this table are measured with regard to t CK = min in general. 43 HM5425161B, HM5425801B, HM5425401B Series DC Characteristics (Ta = 0 to +70C, VCC , VCCQ = 2.5 V 0.2 V, VSS, VSSQ = 0 V) (HM5425801B/HM5425401B) HM5425801B/HM5425401B -75A -75B -10 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Operating current (ACTV-PRE) I CC0 -- TBD -- TBD -- TBD mA CKE VIH, t RC = min 1, 2, 5 Operating current (ACTV-READ-PRE) I CC1 -- TBD -- TBD -- TBD mA CKE VIH, BL = 2, CL = 2.5, tRC = min 1, 2, 5 Idle power down standby current I CC2P -- TBD -- TBD -- TBD mA CKE V IL 4 Idle standby current I CC2N -- TBD -- TBD -- TBD mA CKE VIH, CS VIH 4 Active power down standby current I CC3P -- TBD -- TBD -- TBD mA CKE V IL 3 Active standby current I CC3N -- TBD -- TBD -- TBD mA CKE VIH, t RAS = max 3 Operating current I CC4R (Burst read operation) -- TBD -- TBD -- TBD mA CKE VIH, BL = 2, CL = 2.5 1, 2, 5, 6 Operating current I CC4W (Burst write operation) -- TBD -- TBD -- TBD mA CKE VIH, BL = 2, CL = 2.5 1, 2, 5, 6 Auto Refresh current I CC5 -- TBD -- TBD -- TBD mA t RFC = min, Input VIL or VIH Self refresh current I CC6 -- 2 -- 2 -- 2 mA Input VCC - 0.2 V Input 0.2 V Input leakage current I LI -10 10 -10 10 -10 10 A VCC Vin V SS Output leakage current I LO -10 10 -10 10 -10 10 A VCC Vout VSS Output high voltage VOH VTT + -- 0.76 V I OH (max) = -15.2 mA Output low voltage VOL -- Notes: 1. 2. 3. 4. 5. 6. 7. 44 VTT + -- 0.76 VTT - -- 0.76 VTT + -- 0.76 VTT - -- 0.76 VTT - V 0.76 I OL (min) = 15.2 mA These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one clock cycle. Data/Data mask transition twice per one clock cycle. The I CC data on this table are measured with regard to tCK = min in general. Notes HM5425161B, HM5425801B, HM5425401B Series Capacitance (Ta = 25C, VCC, VCCQ = 2.5 V 0.2 V) Parameter Symbol Min Max Unit Notes Input capacitance (Address) CI1 2.5 3.5 pF 1 Input capacitance (Command) CI2 2.5 3.5 pF 1 4 5.5 pF 1, 2 Data and DOS input/output capacitance (I/O) CO Notes: 1. These parameters are measured on conditions: f = 100 MHz, Vout = VCCQ/2, Vout = 0.2 V. 2. Dout circuits are disabled. 45 HM5425161B, HM5425801B, HM5425401B Series AC Characteristics (Ta = 0 to +70C, VCC, VCCQ = 2.5 V 0.2 V, VSS, VSSQ = 0 V) HM5425161B/HM542581B/HM5425401B -75A -75B -10 Parameter Symbol Min Max Min Max Min Max Unit Notes Clock cycle time (CAS latency = 2) t CK 7.5 15 10 15 10 15 ns t CK 7 15 7.5 15 8 15 ns Input clock high level time t CH 0.45 -- 0.45 -- 0.45 -- t CK Input clock low level time t CL 0.45 -- 0.45 -- 0.45 -- t CK CLK to DQS skew t DQSCK -0.7 0.7 -0.7 0.7 -0.8 0.8 ns 2 DATA to CLK skew t AC -0.7 0.7 -0.7 0.7 -0.8 0.8 ns 2 Dout to DQS skew t DQSQ -0.5 0.5 -0.5 0.5 -0.6 0.6 ns 3 Dout/DQS valid window t DV 0.35 -- 0.35 -- 0.35 -- t CK 4 DQS valid window t DQSV 0.35 -- 0.35 -- 0.35 -- t CK 4 DQS read preamble t RPRE 0.9 1.1 0.9 1.1 0.9 1.1 t CK DQS read postamble t RPST 0.4 0.6 0.4 0.6 0.4 0.6 t CK Dout-High impedance delay t HZ from CLK/CLK -0.7 0.7 -0.7 0.7 -0.8 0.8 ns 5 Dout-Low impedance delay t LZ from CLK/CLK -0.7 0.7 -0.7 0.7 -0.8 0.8 ns 6 DQ and DM input pulse width 1.7 -- 1.7 -- 2 -- ns 7 Data and data mask to data t DS strobe setup time 0.5 -- 0.5 -- 0.6 -- ns 8 Data and data mask to data t DH strobe hold time 0.5 -- 0.5 -- 0.6 -- ns 8 Clock to DQS write preamble setup time t WPRES 0 -- 0 -- 0 -- ns Clock to DQS write preamble hold time t WPREH 0.25 -- 0.25 -- 0.25 -- t CK DQS last edge to High-Z t WPST time (DQS write postamble) 0.4 0.6 0.4 0.6 0.4 0.6 t CK Clock to the DQS first rising t DQSS edge for write delay 0.75 1.25 0.75 1.25 0.75 1.25 t CK (CAS latency = 2.5) 46 t DIPW 10 9 HM5425161B, HM5425801B, HM5425401B Series HM5425161B/HM5425801B/HM5425401B -75A -75B -10 Parameter Symbol Min Max Min Max Min Max Unit Notes DQS falling edge to CLK setup time t DSS 0.2 -- 0.2 -- 0.2 -- t CK DQS falling edge hold time t DSH to CLK 0.2 -- 0.2 -- 0.2 -- t CK DQS high pulse width (DQS write) t DQSH 0.35 -- 0.35 -- 0.35 -- t CK DQS low pulse width (DQS write) t DQSL 0.35 -- 0.35 -- 0.35 -- t CK Input command and address setup time t IS 1.1 -- 1.1 -- 1.2 -- ns 8 Input command and address hold time t IH 1.1 -- 1.1 -- 1.2 -- ns 8 Active command period t RC 65 -- 65 -- 70 -- ns Auto refresh to active/Auto t RFC refresh command cycle 75 -- 75 -- 80 -- ns Active to Precharge command period t RAS 45 120000 45 120000 50 120000 ns Active to column command t RCD period 20 -- 20 -- 20 -- ns Last data in to precharge t WR 15 -- 15 -- 15 -- ns Precharge to active command period t RP 20 -- 20 -- 20 -- ns Active to active command period t RRD 15 -- 15 -- 15 -- ns Average periodic refresh interval t REF -- 7.8 -- 7.8 -- 7.8 s 47 HM5425161B, HM5425801B, HM5425401B Series Notes. 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see `Timing Waveforms' section. 2. This parameter defines the signal transition delay from the cross point of CLK and CLK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing V TT. 5. t HZ is defined as Dout transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CLK and CLK. This parameter is not referred to a specific Dout voltage level, but specify when the device output stops driving. 6. t LZ is defined as Dout transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific Dout voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. t CK max is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. VCC is assumed to be 2.5 V 0.2 V. VCC power supply variation per cycle expected to be less than 0.4 V/400 cycle. 48 HM5425161B, HM5425801B, HM5425401B Series Test Conditions Parameter Symbol Min Typ Max Unit Input reference voltage VREF 1.15 1.25 1.35 V Termination voltage VTT VREF - 0.04 VREF VREF + 0.04 V AC input high voltage VIH (ac) VREF + 0.35 -- -- V AC input low voltage VIL (ac) -- -- VREF - 0.35 V AC differential input high voltage VSWING (ac) 0.7 -- VCCQ + 0.6 V AC differential cross point voltage VX (ac) VREF - 0.2 VREF VREF + 0.2 V Input signal slew rate SLEW -- 1 -- V/ns tCK VCC CLK V SWING VX CLK tCL tCH VREF VSS VCC VIH VIL VREF VSS t SLEW = (VIH (ac) - VIL (ac))/t VTT Measurement point RT = 25 DQ RS = 25 CL = 30 pF 49 HM5425161B, HM5425801B, HM5425401B Series Timing Parameter Measured in Clock Cycle Number of clock cycle Parameter Symbol Min Write to pre-charge command delay (same bank) t WPD 3 + BL/2 Read to pre-charge command delay (same bank) t RPD BL/2 Write to read command delay (to input all data) t WRD 2 + BL/2 Burst stop command to write command delay (CAS latency = 2) t BSTW 2 t BSTW 3 t BSTZ 2 t BSTZ 2.5 (CAS latency = 2.5) Burst stop command to DQ High-Z (CAS latency = 2) (CAS latency = 2.5) Read command to write command delay (to output all data) t RWD (CAS latency = 2) (CAS latency = 2.5) Max 2 + BL/2 t RWD 3 + BL/2 t HZP 2 t HZP 2.5 Write command to data in latency t WCD 1 Write recovery t WR 2 DM to data in latency t DMD 0 Register set command to active or register set command t MRD 2 Self refresh exit to non-read command t SNR 10 Self refresh exit to read command t SRD 200 Power down entry t PDEN 1 Power down exit to command input t PDEX 1 CKE minimum pulse width t CKEPW Pre-charge command to High-Z (CAS latency = 2) (CAS latency = 2.5) 50 1 !" , HM5425161B, HM5425801B, HM5425401B Series Timing Waveforms Command and Addresses Input Timing Definition CLK CLK tIS Command (RAS, CAS, WE, CS) tIH VREF tIS tIH VREF Address Read Timing Definition tCK CLK CLK DQS tRPRE High-Z (VTT) tDQSCK tDQSV tDQSV tCL/tCH tRPST *1 VTT *1 DQ (Dout) tCH/tCL tLZ tAC tDV tHZ VTT Notes: 1. Specific voltage for transition from/to High-Z is not given. 2. The transition to High-Z is defined to occur when output stop driving. 3. The transition from High-Z is defined to occur when output begins driving. 51 ,!"#"#, HM5425161B, HM5425801B, HM5425401B Series Write Timing Definition tCK CLK CLK tDQSS tDSS tDSH VREF DQS tDQSL tWPRES tWPREH tDQSH tWPST DQ (Din) VREF tDS tDH tDIPW VREF DM tDS 52 tDH tDIPW tDIPW HM5425161B, HM5425801B, HM5425401B Series , ' ? > = 7 6 / < ; 5 4 , : " . & % $ 3 + * # 9 2 1 0 ) '/.67=>?$%+,34:;BCJKL,)189(0:,( !, Read Cycle tCK tCH tCL CLK CLK tRC VIH CKE tRAS tRCD tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH CS RAS CAS WE BA A10 tIS tIH Address DM, DMU/DML DQS, DQSU/DQSL High-Z DQ (output) High-Z tRPRE tDQSVtDQSV tDV Bank 0 Active Bank 0 Read tRPST tDV Bank 0 Precharge CAS latency = 2 Burst length = 4 Bank0 Access = VIH or VIL 53 &'./7?,!( 80 "#$*+3)1 29%-4;<: , #$*+123:089./67>&-%,45<?;= , HM5425161B, HM5425801B, HM5425401B Series Write Cycle tCK tCH tCL CLK CLK tRC VIH CKE tRAS tRCD tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH CS RAS CAS WE BA A10 tIS tIH Address tDQSS DQS, DQSU/DQSL (input) tDQSL tWPST tDQSL tDH tDS tDS DM, DMU/DML tDS tDH DQ (input) tWR tDH Bank 0 Active 54 Bank 0 Write Bank 0 Precharge CAS latency = 2 Burst length = 4 Bank0 Access = VIH or VIL HM5425161B, HM5425801B, HM5425401B Series Mode Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GP>5*!"@HI./67 & %8A'(01-?9$J FOEN2;<CDKLM./67?@H&' CLK CLK CKE VIH CS RAS CAS WE BA Address code R: b code valid C: b DM, DMU/DML DQS, DQSU/DQSL High-Z High-Z b DQ (output) tRP Precharge If needed tMRD Mode register set Bank 3 Active Bank 3 Read Bank 3 Precharge CAS latency = 2 Burst length = 4 = VIH or VIL 55 , HM5425161B, HM5425801B, HM5425401B Series " >GFOP!")*23:;CL &'/08%. $-67?H@I K Read/Write Cycle 0 CLK CLK CKE 1 2 3 4 C:a R:b 5 6 7 8 9 10 11 12 13 14 15 VIH CS RAS CAS WE BA Address R:a C:b'' C:b DM, DMU/DML DQS, DQSU/DQSL a DQ (output) DQ (input) b tRWD Bank 0 Active 56 b'' High-Z Bank 0 Bank 3 Read Active tWRD Bank 3 Write Bank 3 Read Read cycle CAS latency = 2 Burst lenght = 4 =VIH or VIL *GOP>!"1:;CCL23))*2BK/78@A. $%- % $ ? 6 :BCLKM !"# HM5425161B, HM5425801B, HM5425401B Series ,, , ,,,,, , Auto Refresh Cycle CLK CLK CKE VIH CS RAS CAS WE BA Address R: b A10=1 DM, DMU/DML DQS DQSU/DQSL DQ (output) DQ (input) C: b b High-Z tRP Precharge If needed tRC Auto Refresh Bank 0 Active Bank 0 Read CAS latency = 2 Burst length = 4 = VIH or VIL 57 PPO,45=>EFMNDLM#4<=EFN5>,'(0&'.67?@ H)189B/$%.,-$ ' & $ , /0 HM5425161B, HM5425801B, HM5425401B Series Self Refresh Cycle CLK CLK tIS tIH CKE , ,, ,,, CKE = low tCKEPW CS RAS CAS WE BA Address R: b A10=1 C: b DM, DMU/DML DQS DQSU/DQSL DQ (output) High-Z DQ (input) Precharge If needed 58 tSNR tRP Self refresh entry Self refresh exit Bank 0 Active Bank 0 Read CAS latency = 2.5 Burst length = 4 = VIH or VIL HM5425161B, HM5425801B, HM5425401B Series Power Down Mode # ! + " PG#+,45<=EFMN>O.78?@HIAJ'/09&( $-6% CLK CLK tIS , , , , , ,,,, ,, tIH CKE = low CKE tCKEPW CS RAS CAS WE BA Address A10=1 R: b R: c DM, DMU/DML QS, QSU/QSL DQ (output) High-Z DQ (input) tRP Precharge If needed tPDEN Power down entry tPDEX Power Bank 0 Bank 0 down Active Read exit CAS latency = 2.5 Burst lenght = 4 =VIH or VIL 59 HM5425161B, HM5425801B, HM5425401B Series Package Dimensions HM5425161BTT/HM5425801BTT/HM5425401BTT Series (TTP-66D) Preliminary Unit: mm 22.22 22.72 Max 34 10.16 66 1 0.65 *0.24 0.07 0.22 0.05 33 0.13 M 0.80 11.76 0.20 0.91 Max *Dimension including the plating thickness Base material dimension 60 0.50 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-66D -- -- 0.53 g 0.68 0.13 0.05 0.10 *0.145 0.05 0.125 0.04 1.20 Max 0 - 5 HM5425161B, HM5425801B, HM5425401B Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 61 HM5425161B, HM5425801B, HM5425401B Series Revision Record Rev. Date 0.0 62 Contents of Modification Jun. 28, 1999 Initial issue Drawn by Approved by