ASIX ELECTRONICS CORPORATION Frist Released Date: Dec/20/2001
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
AX88172 L
USB to Fast Ethernet/HomePNA Controller
USB to Fast Ethernet/HomePNA Controller
Document No.: AX172-4/ V1.4 / DEC, 20/02
Features
• Single chip USB to 10/100Mbps Fast Ethernet and
1/10Mbps HomePNA and HomePlug Network
Controller
• Compliant with USB specification 1.0 and 1.1 and
2.0
• Full/High Speed USB Device with bus power
capability
• Support 4 endpoints on USB
• IEEE 802.3u 100BASE-T, TX, and T4 Compatible
• Embedded 7K*16 bit SRAM, 256*16 bit SRAM
and 8 FIFOs
• Support both full-duplex or half-duplex operation
on Fast Ethernet
• Provides a MII port for both Ethernet and
HomePNA/ HomePlug PHY interface
• Supports suspended mode and remote wakeup
(link_up or magic packet or external pin)
• Optional PHY power down m ode for power saving
• Support (94c56/93c66) 256/512 bytes serial
EEPROM (used for saving USB Descriptors)
• Support automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM on power-on initialization
• External PHY loop-back diagnostic capability
• Small form factor with 80-pin LQFP package
• Single 12MHz clock input, pure 3.3V operation
*IEEE is a registered trademark of the Institute of Electrical and
Electronic Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88172 USB to Fast Ethernet/HomePNA/HomePlug Controller is a high performance and highly integrated
Controller with embedded 7K*16 bit SRAM. The AX88172 contains a USB interface to host CPU and compliant with
USB Standard V1.0, V1.1 and V2.0. The AX88172 could be used for both 10M/100Mbps Fast Ethernet function based on
IEEE802.3 / IEEE802.3u LAN standard and 1M/10M HomePNA standard. The AX88172 supports media-independent
interface (MII) to simplify the design on implementing Fast Ethernet and HomePNA functions.
System Block Diagram
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No
liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
AX88172
10/100 Mbps Ethernet
PHY/TxRx
MAGNETIC
RJ45
USB I/F
EEPROM
1/10 Mbps
Home LAN PHY
MAGNETIC
RJ11
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CONTENTS
1.0 INTRODUCTION....................................................................................................................... 4
1.1 GENERAL DESCRIPTION:............................................................................................................. 4
1.2 AX88172 BLOCK DIAGRAM:...................................................................................................... 4
1.3 AX88172 PIN CONNECTION DIAGRAM....................................................................................... 5
2.0 SIGNAL DESCRIPTION........................................................................................................... 6
3.0 EEPROM MEMORY MAPPING............................................................................................ 9
4.0 USB COMMANDS ................................................................................................................... 11
4.1 USB STANDARD COMMANDS.................................................................................................... 11
4.2 USB VENDOR COMMANDS....................................................................................................... 12
5.0 USB CONFIGURATION STRUCTURE .............................................................................. 14
5.1 USB CONFIGURATION.............................................................................................................. 14
5.2 USB INTERFACE....................................................................................................................... 14
5.3 USB ENDPOINTS. ..................................................................................................................... 14
6.0 ELECTRICAL SPECIFICATION AND TIMINGS............................................................ 15
6.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................... 15
6.2 GENERAL OPERATION CONDITIONS.......................................................................................... 15
6.3 DC CHARACTERISTICS ............................................................................................................. 15
6.4 A.C. TIMING CHARACTERISTICS............................................................................................... 16
6.4.1 12M_XIN........................................................................................................................... 16
6.4.2 Reset Timing...................................................................................................................... 16
6.4.3 MII Timing......................................................................................................................... 17
6.4.4 STATION MANAGEMENT TIMING................................................................................. 18
6.4.5 SERIAL EEPROM TIMING .............................................................................................. 19
7.0 PACKAGE INFORMATION.................................................................................................. 20
APPENDIX A: SYSTEM APPLICATIONS................................................................................ 21
A.1 USB TO FAST ETHERNET CONVERTER .................................................................................... 21
A.2 USB TO FAST ETHERNET AND/OR HOMELAN COMBO SOLUTION........................................... 21
DEMONSTRATION CIRCUIT A: AX88172 (ED2 VERSION) + ETHERNET PHY(8201L)
........................................................................................................................................................... 22
DEMONSTRATION CIRCUIT B: AX88172 (ED3 VERSION) + ETHERNET PHY
(8201LBL)........................................................................................................................................ 24
REMARK:....................................................................................................................................... 26
REVISIONS HISTORY................................................................................................................. 27
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FIGURES
FIG – 1 AX88172 BLOCK DIAGRAM ...................................................................................................................................4
FIG – 2 AX88172 PIN CONNECTION DIAGRAM...................................................................................................................5
TABLES
TAB - 1 PIN SIGNALS ..........................................................................................................................................................8
TAB - 2 EEPROM MEMORY MAPPING ..............................................................................................................................9
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1.0 Introduction
1.1 General Description:
The AX88172 USB to Fast Ethernet Cont roller is a hi gh performance and highly integrated USB bus Ethernet Controlle r
with embedded 7K*16 bit SRAM. The AX88172 supported Full/High Speed USB Device with bus power capability. The
AX88172 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3/ IEEE802.3u LAN standard.
The AX88172 supports media-independent interface (MII) to simplify the design on implementing Fast Ethernet and
HomePNA functions.
AX88172 uses 80-pin LQFP low profile package, 12MHz operat ion for USB and 25MHz operat ion for Ethernet, C MOS
process with pure 3.3V operation.
1.2 AX88172 Block Diagram:
Fig – 1 AX88172 Block Diagram
MAC
Core
Memory Arbiter
USB to
Ethernet
Bridge
USB Core and Interface
STA
SEEPROM
Loader I/F
DM/DP
MII /IF
MDC
MDIO
EECS
EECK
EEDI
EEDO
7K* 16
SRAM
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1.3 AX88172 Pin Connection Diagram
The AX88172 is housed in the 80-pin plastic light quad flat pack.
Fig – 2 AX88172 Pin Connection Diagram
AVDD
AVSS
AVSS
AVSS
DP
AVSS
DM
AVDD
EXTWAKEUPN
N
C
N
C
VDD
MDC
MDIO
N
C
VDD
TXD0
TXD1
TXD2
TXD3
TXEN
VDD
RXCLK
RXD0
RXD1
RXD2
RXD3
VDD
RXER
RXDV
TEST1
GPIO2
PHYRSTN
N
C
NC
LED
VDD
NC
NC
VSS
EECS
EEC
K
EEDI
EEDO
VSS
NC
NC
ANA_XIQ
VDD
CLKI
TESTMODE
RESET/RESET
VSS
VDD
PVDD
PVSS
VC
XOUT12M
XIN12M
80
79
78
77
76
75
74
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
73
72
71
70
69
68
67
66
65
ASIX
AX88172
17
18
19
20
37
38
39
40
44
43
42
41
64
63
62
61
R1
EPTEST
N
C
N
C
N
C
VSS
VSS
VDD
TEST0
GPIO0
GPIO1
VDD
RST_TYPE
NC
NC
NC
CRS
TXCLK
VBUS
COL
PHYRSTP
ED3
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2.0 Signal Description
The following terms describe the AX88172 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I Input PU Internal Pull Up (100K)
O Output PD Internal Pull Down (100K)
I/O Input/Output P Power Pin
OD Open Drain
SIGNAL TYPE PIN NO. DESCRIPTION
R1 I 1 Constant-votage pin
A 6.2K± 1% resistors is connected to AVSS. Be sure t o make the line
between R1 and each resistor as short as possible.
AVDD P 2 Power supply pin for analog circuits +3.3V DC
AVSS P 3 Power supply pin for analog circuits Ground
AVSS P 4 Power supply pin for analog circuits Ground
DP B 5 USB data line Data+
AVSS P 6 Power supply pin for analog circuits Ground
DM B 7 USB data line Data-
AVSS P 8 Power supply pin for analog circuits Ground
AVDD P 9 Power supply pin for analog circuits +3.3V DC
/EXTWAKEUP I/PU 10 Remote-wakeup trigger from external pin. It active low
and should be keep low over 2 clocks (12MHz)
NC B 11 For testin g
NC B 12 For testing
VDD P 13 Power Supply for logic circuits: +3.3V DC.
MDC O 14 Station Managem ent Data Clock: The ti ming reference for MDIO. All
data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
MDIO I/O/PU 15 Station Management Data Input/Output: Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII specification.
NC O 16 For testing
NC O 17 For testing
NC O 18 For testing
NC O 19 For testing
VSS P 20 Power Supply: +0V DC or Ground Power.
VDD P 21 Power Supply for logic circuits: +3.3V DC.
COL I 22 Collision: this signal is dr iven by PHY when collision is d etected.
NC 23 No connection
TX_CLK I 24 Transmit Clock: TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
CRS I 25 Carrier Sense: Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
TXD[3:0] O 29, 28, 27,
26 Transmit Data: TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
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TX_EN O 30 Transmit Enable: TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_E
N
indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
VDD P 31 Power Supply for logic circuits: +3.3V DC.
RX_CLK I 32 Receive Clock: RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV, RXD[3:0] and
RX_ER signals from the PHY to the MII port o f the MAC.
RXD[3:0]
I 36, 35, 34,
33 Receive Data: RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
VDD P 37 Power Supply for logic circuits: +3.3V DC.
RX_ER I 38 Receive Error: RX_ER is driven by PHY and synchronous to
RX_CLK, is assert ed for one or m ore RX_C LK periods to indi cate t o
the port that an error has detected.
RX_DV I 39 Receive Data Valid: RX_DV is driven by the PHY synchronously
with respect t o RX_CLK. Asserted high when valid data is present on
RXD [3:0].
VSS P 40 Power Supply: +0V DC or Ground Power.
VDD P 41 Power Supply for logic circuits: +3.3V DC.
TEST0 I/PU 42 Test Pin: This pin for test purpose only.
Pull up the pin or keep no connection for normal operation.
TEST1 I/PU 43 Test Pin: This pin for test purpose only.
Pull up the pin or keep no connection for normal operation.
GPIO[2:0] I/O/PU 46, 45, 44 General Purpose Input/ Output Pins.
/PHYRST O 47 Output for reset PHY active low
PHYRST O 48 Output for reset PHY active high
VSS P 49 Power Supply: +0V DC or Ground Power.
NC I/PD 50 For testing
NC I/PD 51 For testing
LED O 52 LED indicator: When link FS, drives logic high always. When link
HS, the pin drives logic low. and it will drives high/low a period when
line has activity (data transfer).
VDD P 53 Power Supply for logic circuits: +3.3V DC.
NC I/PD 54 For testing
NC ID 55 For testing
EECS O 56 EEPROM Chip Select: EEPROM ch ip select signal.
EECK O 57 EEPROM Clock: Signal connected to EEPROM clock pin.
EEDI O 58 EEPROM Data In: Signal connected to EEPROM data input pin.
EEDO I/PD 59 EEPROM Data Out: Signal connected to EEPROM data output pin.
VSS P 60 Power Supply: +0V DC or Ground Power.
VDD P 61 Power Supply for logic circuits: +3.3V DC.
RST_TYPE I/PU 62 This pin define the assert level of Reset (pin 72)
When =’1’ or NC, reset signal is active High
When =’0’, reset signal is active Low
NC I/PD 63, 64, 65,
66, 67 For testing
ANA_XIQ I 68 Sets the IQ mode
This pin is used during testing. It must be set to low in IQ
measurement mode.
0: IQ mode
1: Normal operation mode
VDD P 69 Power Supply for logic circuits: +3.3V DC.
CLKI I/PD 70 External 60MHz input
TESTMODE I/PD 71 For testing (TESTMODE)
0: Normal operation mode
1: External clock Synchronization mode
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RESET/RESET I 72 Reset/Reset
Reset is active high/low depend on RST_TYPE (pin 62) definition.
When assert, place AX88172 into reset mode immediately. Reset
complete loads the EEPROM data.
VSS P 73 Power Supply: +0V DC or Ground Power.
VDD P 74 Power Supply for logic circuits: +3.3V DC.
PVDD P 75 Power supply pin for PLL and oscillator circuits +3.3V DC
PVSS P 76 Power supply pin for PLL and oscillator circuits +0V DC or Ground
Powe
VC I 77 Monitor pin for two PLL charge pumps
Connect to GND on PCB when actually using
PTEST I 78 Charge pump monitor ON/OFF:
Connect to GND on PCB when actually using
XIN12M I 79 12M crystal oscillator input
XOUT12M O 80 12M crystal oscillator output
Tab - 1 PIN signals
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3.0 EEPROM Memory Mapping
EEPROM
OFFSET HIGH BYTE LOW BYTE
00H RESERVED WORD COUNT FOR PRELOAD
01H *FLAG
02H HIGH-SPEED LENGTH OF DEVICE
DESCRIPTOR (BYTE) HIGH-SPEED EEPROM OFFSET OF DEVICE
DESCRIPTOR
03H HIGH-SPEED LENGTH OF CONFIGURATION
DESCRIPTOR (BYTE) HIGH-SPEED EEPROM OFFSET OF
CONFIGURATION DESCRIPTOR
04H NODE ID 1 NODE ID 0
05H NODE ID 3 NODE ID 2
06H NODE ID 5 NODE ID 4
07H LANGUAGE ID HIGH BYTE LANGUAGE ID LOW BYTE
08H LENGTH OF STRING INDEX 1 EEPROM OFFSET OF STRING INDEX 1
09H LENGTH OF STRING INDEX 2 EEPROM OFFSET OF STRING INDEX 2
0AH LENGTH OF STRING INDEX 3 EEPROM OFFSET OF STRING INDEX 3
0BH LENGTH OF STRING INDEX 4 EEPROM OFFSET OF STRING INDEX 4
0CH LENGTH OF STRING INDEX 5 EEPROM OFFSET OF STRING INDEX 5
0DH LENGTH OF STRING INDEX 6 EEPROM OFFSET OF STRING INDEX 6
0EH LENGTH OF STRING INDEX 7 EEPROM OFFSET OF STRING INDEX 7
0FH RESERVED RESERVED
10H MAX PACKETSIZE HIGH BYTE MAX PACKET LOW BYTE
11H **(PHY TYPE[7:5]) (SECONDARY PHY
ID[4:0]) **(PHY TYPE[7:5])(FIRST PHY ID[4:0] )
12H PAUSE PACKET HIGH W A TER LEVEL PAUSE PACKET LOW WATER LEVEL
13H FULL-SPEED LENGTH OF DEVICE
DESCRIPTOR (BYTE) FULL-SPEED EEPROM OFFSET OF DEVICE
DESCRIPTOR
14H FULL-SPEED LENGTH OF CONFIGURATION
DESCRIPTOR (BYTE) FULL-SPEED EEPROM OFFSET OF
CONFIGURATION DESCRIPTOR
15H-1FH RESERVED RESERVED
Tab - 2 EEPROM Memory Mapping
Note:
*FLAG:
Bit0 Self Powered (for USB GetStatus) 1: self power ; 0 : bus power
Bit 1 Reserved
Bit 2 RemoteWakeUP support
Bit 3 1
Bit 4 –5 Reserved
Bit 6 RX drop CRC Enable
Bit 7 TX append CRC enab le
Bit 8 Capture Effective Mode
Bit 9 – F Reserved
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** PHY TYPE[7:5]
3’b000 = 10/100 Ethernet PHY or 1M HOME PHY (Link report as normal case)
3’b100 = special case 1 (Link report always active)
3’b101 = reserved
3’b111 = No supported PHY
FOR EXAMPLE: EEPROM OFFSET 11 HIGH BYTE IS “E0” MEAN IS NO SUPPORTED
SECONDARY PHY.
***Unicode MAC Address:
If the MAC’s NODE ID is 01,23,45,67,89,ABh respect to NODE ID 0, NODE ID 1, … NODE ID5
Then the unicode will be 30-31,32-33,34-35,36-37,38-39,41-42h respects to BYTE 1 OF UNICODE MAC
ADDRESS- BYTE 2 OF UNICODE MAC ADDRESS, …-BYTE 12 OF UNICODE MAC ADDRESS.
Isolate 2 PHY step procedure by hardware when every hardware reset
1. write 0 PHY_ID isolate and power down
2. write PRIMARILY PHY ID isolate and power down
3. write SECONDARY PHY ID isolate and power down
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4.0 USB Commands
There are three command groups for Endpoint 0 in AX88172:
The USB standard commands
USB Communication Class commands
USB vendor commands.
4.1 USB standard commands
The Language ID is 0x0904 for English
PPLL means buffer length
CC means configuration number
I I means Interface number
SETUP COMMAND DATA IN/OUT DESCRIPTION
80 06 00 01 00 00 LL PP Data PPLL bytes Get Device Descriptor
80 06 00 02 00 00 LL PP Data PPLL bytes Get Configuration Descriptor
80 06 00 03 00 00 LL PP Data 2 bytes Get Supported Language ID
80 06 01 03 09 04 LL PP Data PPLL bytes Get Manufacture String
80 06 02 03 09 04 LL PP Data PPLL bytes Get Product String
80 06 03 03 09 04 LL PP Data PPLL bytes Get Serial Number String
80 06 04 03 09 04 LL PP Data PPLL bytes Get Configuration String
80 06 05 03 09 04 LL PP Data PPLL bytes Get Interface 0 String
80 06 06 03 09 04 LL PP Data PPLL bytes Get Interface 1/0 String
80 06 07 03 09 04 LL PP Data PPLL bytes Get Interface 1/1 Stirng
80 06 08 03 09 04 LL PP Data 12 bytes Get Ethernet Address String
80 08 00 00 00 00 01 00 Data 1 bytes Get Configuration
00 09 CC 00 00 00 00 00 No Data Set Configuration
81 0A 00 00 I I 00 01 00 Data 1 byte Get Interface
01 0B AS 00 00 00 00 00 No Data Set Interface
Tab - 3 USB stabdard commands
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4.2 USB Vendor Commands
SETUP COMMAND DATA IN/OUT DESCRIPTION
C0 02 XX YY 0M 00 02 00 Data 2 bytes Read Rx/Tx SRAM
M = 0 : Rx, M=1 : Tx
40 03 XX YY PP QQ 00 00 No Data Write Rx SRAM
40 04 XX YY PP QQ 00 00 No Data Write Tx SRAM
40 06 00 00 00 00 00 00 No Data Software MII Operation
C0 07 PI 00 RG 00 02 00 Data 2 Bytes Read MII Register
40 08 PI 00 RG 00 02 00 Data 2 Bytes Write MII Register
C0 09 00 00 00 00 01 00 Data 1 Bytes Read MII Operation Mode
40 0A 00 00 00 00 00 00 No Data Hardware MII Operation
C0 0B DR 00 00 00 02 00 Data 2 Bytes Read SROM
40 0C DR 00 MM SS 00 00 No Data Write SROM
40 0D 00 00 00 00 00 00 No Data Write SROM Enable
40 0E 00 00 00 00 00 00 No Data Write SROM Disable
C0 0F 00 00 00 00 02 00 Data 2 Bytes Read Rx Control Register
40 10 RR 00 00 00 00 00 No Data Write Rx Control Register
C0 11 00 00 00 00 03 00 Data 3 Bytes Read IPG/IPG1/IPG2 Register
40 12 II 00 00 00 00 00 No Data Write IPG Register
40 13 II 00 00 00 00 00 No Data Write IPG1 Register
40 14 II 00 00 00 00 00 No Data Write IPG2 Register
C0 15 00 00 00 00 08 00 Data 8 Bytes Read Multi-Filter Array
40 16 00 0 0 00 00 08 0 0 Data 8 Bytes Write Multi-Filter Array
C0 17 00 00 00 00 06 00 Data 6 Bytes Read Node ID
C0 19 00 00 00 00 02 00 Data 2 Bytes (*) Read Ethernet/HomePNA PhyID
C0 1A 00 00 00 00 01 00 Data 1 Byte Read Medium Status (**)
40 1B MM 00 00 00 00 00 No Data Write Medium Mode (**)
C0 1C 00 00 00 00 01 00 Data 1 Byte Get Monitor Mode Status (***)
40 1D MM 00 00 00 00 00 No Data Set Monitor Mode On/Off (***)
C0 1E 00 00 00 00 01 00 Data 1 Byte Read GPIOs (****)
40 1F MM 00 00 00 00 00 No Data Write GPIOs (****)
* Note1: read 1st byte is Secondary PHY ID; 2nd byte is Primarily PHY ID
** Read / Write Medium status
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Read X X X Flow_Control_En TxAbortAllow Full_Duplex
Write X X X Flow_Control_En X TxAbortAllow Full_Duplex X
*** Read / Write Monitor Mode
Bit7-5 Bit4 Bit3 Bit2 Bit1 Bit0
Read 3’b101 HS/FS X Magic_Packet_En Link_UP_Wake Monitor_Mode
Write X X X Magic_Packet_En Link_UP_Wake Monitor_Mode
**** Read / Write GPIO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Read GPI2 GPO2EN GPI1 GPO1EN GPI0 GPO0EN
Write GPO2 GPO2EN GPO1 GPO1EN GPO0 GPO0EN
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Interrupt endpoint frame format
Byte Number
Byte 0 A1 Fixed value 00
Byte 1 00 Fixed value 00
Byte 2 NN Bit_1: SECONDARY PHY Link state (active high),
Bit_0: PRIMARILY PHY LINK STATE
Byte 3 00 Fixed value 00
Byte 4 00 Fixed value 00
Byte 5 80 90h
Byte 6 00 Fixed value 00
Byte 7 00 Fixed value
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5.0 USB Configuration Structure
5.1 USB Configuration.
The AX88172 supports 1 Configuration only.
5.2 USB Interface.
The AX88172 supports 2 interfaces, the interface 0 is Data Interface and interface 1 is for Communication Interface.
5.3 USB Endpoints.
The AX88172 supports 4 endpoints.
Endpoint 0 Control endpoint, it is for configuring device.
Endpoint 1 (optional) Interrupt endpoint, it is for reporting status
Endpoint 2 Bulk Out endpoint, it is for Transmitting Ethernet Packet.
Endpoint 3 Bulk In endpoint, it is for Receiving Ethernet Packet.
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6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description SYM Min Max Units
Operating Temperature Ta 0 +85 °C
Storage Temperature Ts -65 +150 °C
Supply Voltage Vdd -0.3 +3.6 V
Input Voltage Vin -0.3 Vdd+0.3 V
Output Voltage Vout -0.3 Vdd+0.3 V
Lead Temperature (soldering 10 seconds maximum) Tl -55 +240 °C
Note: Stress above those li ste d under Absolute M aximum Rati ngs m ay cause permanent damage to t he device. Exposure
to Absolute Maximum Ratings conditions for extended period , adversely affect device life and reliability.
6.2 General Operation Conditions
Description SYM Min Tpy Max Units
Operating Temperature Ta 0 25 +70 °C
Supply Voltage Vdd +3.0 +3.30 +3.6 V
6.3 DC Characteristics
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 70°C)
Description SYM Min Tpy Max Units
Low Input Voltage Vil - 0.3*Vdd V
High Input Voltage Vih 0.7*Vdd - V
Low Output Voltage Vol - 0.4 V
High Output Voltage Voh 2.4 - V
Input Leakage Current Iil -1 +1 uA
Output Leakage Current Iol -10 +10 uA
Input Pull-up / down resistance Ri 75 K ohm
Description SYM Min Tpy Max Units
Power Consumption (3.3V) SPt3v 150 mA
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6.4 A.C. Timing Characteristics
6.4.1 12M_XIN (CL=16pF, +/-50ppm)
12M_XIN
Tr Tf Tlow
Symbol Description Min Typ. Max Units
Tcyc CYCLE TIME 83.33 ns
Thigh CLK HIGH TIME 34.71 41.66 49.99 ns
Tlow CLK LOW TIME 34.71 41.66 49.99 ns
Tr/Tf CLK SLEW RATE 1 - 4 ns
6.4.2 Reset Timing
12M_XIN
RESET/RESET
Symbol Description Min Typ. Max Units
Trst Reset pulse width (6ms ~10ms) 100 - - 12M
_XIN
Tcyc
Thigh
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6.4.3 MII Timing
Ttclk Ttch Ttcl
TXCLK(in)
Ttv Tth
TXD<3:0>(out)
TXEN(out)
Trclk Trch Trcl
RXCLK(in)
Trs Trh
RXD<3:0>(in)
RXDV(in)
Trs1
RXER(in)
CRS(in)
Symbol Description Min Typ. Max Units
Ttclk Cycle time(100Mbps) - 40 - ns
Ttclk Cycle time(10Mbps) - 400 - ns
Ttch high time(100Mbps) 14 - 26 ns
Ttch high time(10Mbps) 140 - 260 ns
Trch low time(100Mbps) 14 - 26 ns
Trch low time(10Mbps) 140 - 260 ns
Ttv Clock to data valid 3 - 10 ns
Tth Data output hold time 3 - 10 ns
Trclk Cycle time(100Mbps) - 40 - ns
Trclk Cycle time(10Mbps) - 400 - ns
Trch high time(100Mbps) 14 - 26 ns
Trch high time(10Mbps) 140 - 260 ns
Trcl low time(100Mbps) 14 - 26 ns
Trcl low time(10Mbps) 140 - 260 ns
Trs data setup time 6 - - ns
Trh data hold time 6 - - ns
Trs1 RXER data setup time 6 - - ns
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6.4.4 STATION MANAGEMENT TIMING
MDC
MDIO
(output)
MDIO
(input)
Symbol Description Min Typ. Max Units
Tclk MDC Clock Cycle Time 375 KHz
Tch MDC Clock High Time 1328 ns
Tcl MDC Clock Low Time 1328 ns
Tod Clock Falling Edge to Output Valid Delay 0 2 ns
Ts Data In Setup Time 10 ns
Th Data In Hold Time 100 ns
To
d
Tclk
Ts Th
Tch Tcl
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6.4.5 SERIAL EEPROM TIMING
EECK
EEDI
(output)
EECS
EEDO
(input)
Symbol Description Min Typ. Max Units
Tclk EECK Clock Cycle Time 187.5 KHz
Tch EECK Clock High Time 2666 ns
Tcl EECK Clock Low Time 2666 ns
Tdv EEDI Data Valid Output to EECK High Time 2666 ns
Tod EECK High to EEDI Data Output Delay Time 2666 ns
Tscs EECS Valid to EECK High Time 2666 ns
Thcs EECK Low to EECS Invalid Time 0 ns
Tlcs Minimum EECS Low Time 23904 ns
Ts Data Input Setup Time 10 ns
Th Data Input Hold Time 100 ns
Tch
Tclk
Tcl
VALID VALID
Tdv Tod
Tscs Thcs Tlcs
Th
DATA VALID
Ts
ASIX ELECTRONICS CORPORATION
20
AX88172 PRELIMINARY
7.0 Package Information
be
D
Hd
E
He
pin 1
A2 A1
L
L1
θ
A
MILIMETER SYMBOL
MIN. NOM MAX
A1 0.05 0.1 0.15
A2 1.3 1.40 1.5
A 1.70
b 0.175 0.18 0.28
D 11.9 12.00 12.1
E 11.9 12.00 12.1
e 0.5
Hd 13.6 14.00 14.4
He 13.6 14.00 14.4
L 0.3 0.50 0.7
L1 1.00
θ 0° 10°
ASIX ELECTRONICS CORPORATION
21
AX88172 PRELIMINARY
Appendix A: System Applications
Some typical applications for AX88170 are illustrated bellow.
A.1 USB to Fast Ethernet Converter
A.2 USB to Fast Ethernet and/or HomeLAN Combo solution
AX88172
10/100 PHY/TxRx
MAGNETIC
RJ45
USB I/F
EEPROM
AX88172
10/100 Mbps
Ethernet PHY/TxRx
MAGNETIC
RJ45
USB I/F
EEPROM
1/10 Mbps
Home LAN PHY
MAGNETIC
RJ11
AX88172 USB to Fast Ethernet/HomePNA Controller
ASIX ELECTRONICS CORPORATION
22
Demonstration Circuit A: AX88172 (ED2 version) + Ethernet PHY(8201L)
AX88172
2.1
AX88172 DEMO Board
B
12Friday, May 31, 2002
Title
Size Document Number Rev
Date: Sheet of
VDD3
VDD3L
VDD3L
VDD3
VDD5
VDD3L
GND
RXDV
VDD3L
RXER
RXD2
RXD3
TXD3
RXD0
VDD3L
RXD1
RX_CLK
TXEN
TXD1
CRS
TXD2
TXD0
TX_CLK
VDD3L
RST
VDD3L
VDD3L
MDIO
VDD3L
MDC
VDD3L
COL
TX_CLK
MDIO
RX_CLK
TXEN
TXD0
RXER
TXD2
MDC
COL
RXD0
VDD3
GND
RXD1
RXD3
RXD2
RXDV
TXD3
TXD1
/PHY_RST
CRS
DPLUS
EEDO
EECS
EEDI
EECK
VDD3L
GND
GND
DMINUS
GND
/PHY_RST
EEDO
EEDI
EECK
EECS VDD3
LED
VDD3L
VDD3
RST
VDD3L
DMINUS
DPLUS
VDD5
60MHz
60MHz
AVDD
AVSS
VDD3
PVSS
VDD3
PVDD
VDD3
PVDD
VDD3 GND
PVSS GND
GND
AVSS
AVDD
AVSS
AVDD
AVSS
GND
GND GND
AVSS
C37
0.1u
C34
0.1u
C32
0.1u
C31
0.1u
J1
DC POWER JACK
1
2
3
+
C20
47u/16V
L5 F.BEAD.
+
C35
22u
C19
0.01u
D2 DIODE
C2
0.1u
L1 F.BEAD.
U5
AMS1117
32
1
VIN VOUT
ADJ/GND
+
C16
10u/16V
C17
0.1u
C12
0.1u
L2 F.BEAD.
U3
XC74UL14
1
3 4
5
2NC
GND Y
VCC
A
C24
0.1u
C3
0.1u
C27
0.1u
L3 F.BEAD.
U2
93C56
1
2
3
4 5
6
7
8
CS
SK
DI
DO GND
NC
NC
VCC
C25
0.1u C33
0.01u
S1
SW PUSHBUTTON
C29
0.1u
C26
0.1u
C22
0.1u
+
C18
47u/16V
C21
0.1u
C23
0.1u
R9
0
C9 0.1u
R6
6.2K 1%
C4
0.1u
R1
1K
D1
LED
C6
0.1u
U4
60MHz
8 4
5
VCC GND
OUT
C15
0.1u
C14
0.1u
R8 33
+
C30
22u
C36
0.01u
C11 0.1u
L6 F.BEAD.
C10
0.1u
C28
0.1u
R2
0
R7
15K
L8 F.BEAD.
C5
0.01u
C1
1000P
AX88172
U1
AX88172
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
601
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VDD
RST_TYPE
NC
NC
NC
NC
NC
ANA_XIQ
VDD
CLKI
TESTMODE
RESET
VSS
VDD
PVDD
PVSS
VC
PTEST
XIN12M
XOUT12M
VDD
TEST0
TEST1
GPIO0
GPIO1
GPIO2
PHYRSTN
PHYRSTP
VSS
NC
ATPGEN
LED
VDD
SPEEDUP
NC
EECS
EECK
EEDI
EEDO
VSSR1
AVDD
AVSS
AVSS
DP
AVSS
DM
AVSS
AVDD
EXTWAKEUPN
NC
NC
VDD
MDC
MDIO
NC
NC
NC
NC
VSS
VDD
COL
NC
TXCLK
CRS
TXD0
TXD1
TXD2
TXD3
TXEN
VDD
RXCLK
RXD0
RXD1
RXD2
RXD3
VDD
RXER
RXDV
VSS
41
23
J2
USB-CON
4
1
3
2
GND
VDD5
D+
D-
SS
L4 F.BEAD.
C13
0.47uF
R3
10K
L7 F.BEAD.
C8
24P
Y1
12.000MHz
C7
24P
R5
220
R4
1M
RX_CLK
RXD0
RXD2
TXEN
TXD0
/PHY_RST
GND
TXD1
RXD1
TX_CLK
MDIO
VDD3
CRS
TXD3
COL
RXDV
TXD2
RXER
MDC
RXD3
USB Port Link/Act LED
OPTION
U3 : TOREX / XC74UL14AAMR
OPTION
1 / NC : PIN72 RESET ACTIVE HIGH.
DC 5.0V POWER
1206 & DIP 1206 & DIP
1206 & DIP
1206 & DIP
0 : PIN72 RESET ACTIVE LOW.
RESET ACTIVE LOW : USED "R8" ONLY.
RESET ACTIVE HIGH : USED "U2" ONLY.
OPTION
1206 & DIP 1206 & DIP
AVSS and PVSS :
Single-point ground
OPTION
OPTION
(Next version chip)
AX88172 USB to Fast Ethernet/HomePNA Controller
ASIX ELECTRONICS CORPORATION
23
RTL8201-TS6121A
2.1
AX88172 DEMO Board
B
22Friday, May 31, 2002
Title
Size Document Number Rev
Date: Sheet of
VDD3
VDD3
VDD3
TX+
TX-
RX-
RX+
LED3
LED2
LED0
LED1
X1 X2
AVDD0
AVDD1
AVDD2
GND
GND
GND
X1
X2
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN
RXDV
RXD0
RXD1
RXD2
RXD3
COL
CRS
RXER
AVDD2
DVDD0
AVDD1
AVDD0
VDD3
/PHY_RST
LED0
LED1
LED3
LED2
LED4
LED4
DVDD0
VDD3
VDD3
VDD3
VDD3
RXC
TXC
MDC
GND
R23
75
U7
TS6121A
1
2
3
6
7
8 9
10
11
14
15
16
1
2
3
6
7
89
10
11
14
15
16
C42
0.01u
L10 F.BEAD.
L12 F.BEAD.
C50
0.1u
R35 510
R38 510
R41 510
R16 2K 1%
R19 1K
R20 1K
R40 4.7K
R36 4.7K
R34 4.7K
D4
LED
D3
LED
R33 510
R31 510
R26 1K
R25 1K
R27 1K
R29 1K
R28 1K
R32 4.7K
R30 4.7K
R15
2K
R10 1.5K
R14 20
R13 20
+
C49
10uF/16V
L9 F.BEAD.
C44
0.1u
C45
0.1u
C43
0.1u
RTL 8201
U6
RTL8201
25
26
27
6
5
4
3
2
7
22
21
32
36
48
29
35
45
20
19
18
16
1
23
24
46
47
9
10
12
13
15
8
14
11
17
30
31
28
33
34
43
40
39
38
37
41
44
42
MDC
MDIO
RTT3/VCTRL
TXD0
TXD1
TXD2
TXD3
TXEN
TXC
RXDV
RXD0
AVDD0
AVDD1
AVDD2
AGND
AGND
AGND
RXD1
RXD2
RXD3
RXC
COL
CRS
RXER
X1
X2
LED0/PHYA0
LED1/PHYA1
LED2/PHYA2
LED3/PHYA3
LED3/PHYA4
DVDD0
DVDD1
DGND
DGND
TPRX-
TPRX+
RTSET
TPTX-
TPTX+
ISOLATE
REPT
SPEED
DUPLEX
ANE
LDPS
MII/SNIB
RESETB
R37 1M
R39 0Y2 CRYSTAL 25.000 MHz
C52
20P
R12
49.9
C51
20P
C46
0.1u
R24
75
C38
0.01u
C47
0.1u
J3
RJ45
2
1
3
6
4
5
7
8
SS
L11 F.BEAD.
R22
75
R21
75
C39
0.01u
D7
LED
C41
0.01u/2KV
C48
0.1u
C40
0.01u
D5
LED
R18
49.9
D6
LED
R17
49.9
R11
49.9
VDD3
COL
TXD1
RXD0
RXER
RXD2
TX_CLK
MDIO
TXEN
RXDV
RXD3
TXD0
RXD1
MDC
CRS
TXD3
TXD2
RX_CLK
GND
/PHY_RST
Set PHY ADDRESS TO 00011
COLL
Link LED
Link 10-Active
Link 100-Active
FULL LED
U6 : BOTHHAND / TS6121A
U5 REALTEK RTL8201
( CONNECT TO CHASIS GND )
1206 & DIP
AX88172 USB to Fast Ethernet/HomePNA Controller
ASIX ELECTRONICS CORPORATION
24
Demonstration Circuit B: AX88172 (ED3 version) + Ethernet PHY (8201LBL)
AX88172
2.2
AX88172 DEMO Board ED3
B
12Friday, October 04, 2002
Title
Size Document Number Rev
Date: Sheet of
VDD3
VDD3L
VDD3L
VDD3 VDD3L
VDD5
GND
RXDV
VDD3L
RXER
RXD2
RXD3
TXD3
RXD0
VDD3L
RXD1
RX_CLK
TXEN
TXD1
CRS
TXD2
TXD0
TX_CLK
VDD3L
RST
VDD3L
MDIO
VDD3L
MDC
VDD3L
COL
TX_CLK
MDIO
RX_CLK
TXEN
TXD0
RXER
TXD2
MDC
COL
RXD0
VDD3
GND
RXD1
RXD3
RXD2
RXDV
TXD3
TXD1
/PHY_RST
CRS
DPLUS
EEDO
EECS
EEDI
EECK
VDD3L
GND
GND
DMINUS
GND
/PHY_RST
EEDO
EEDI
EECK
EECS VDD3
LED
VDD3L
RST
AVDD PVDD
PVDD
GND
GND
GND
AVDD
AVDD
VDD5
DPLUS
DMINUS
GND
PVSS
AVSS
VDD3L
AVSS
PVSS
VDD3 VDD3
GND GND AVSS
VDD3
AVSS
AVSS
C30
0.1u
C31
0.1u C33
0.1u C36
0.1u
+
C19
47u/16V
+
C34
22u
C18
0.01u
L1 F.BEAD.
C16
0.1u
+
C15
10u/16V
U4
AMS1117
32
1
VIN VOUT
ADJ/GND
C11
0.1u
C2
0.1u
C23
0.1u
C26
0.1u
L2 F.BEAD.
C24
0.1u
U1
93C56
1
2
3
4 5
6
7
8
CS
SK
DI
DO GND
NC
NC
VCC
C32
0.01u
C28
0.1u
C25
0.1u
+
C17
47u/16V
C21
0.1u
C22
0.1u
C20
0.1u
R11
0
C8 0.1u
C3
0.1u
R8
6.2K 1%
C5
0.1u
D1
LED
R1
1K
+
C29
22u
C35
0.01u
C10 0.1u
L4 F.BEAD.
C27
0.1u
C9
0.1u
R2
0
L6 F.BEAD.
R9
15K
C1
1000P
C4
0.01u
41
23
J1
USB-CON
4
1
3
2
GND
VDD5
D+
D-
SS
AX88172
U2
AX88172
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
601
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VDD
RST_TYPE
NC
NC
NC
NC
NC
ANA_XIQ
VDD
CLKI
TESTMODE
RESET
VSS
VDD
PVDD
PVSS
VC
PTEST
XIN12M
XOUT12M
VDD
TEST0
TEST1
GPIO0
GPIO1
GPIO2
PHYRSTN
PHYRSTP
VSS
NC
ATPGEN
LED
VDD
SPEEDUP
NC
EECS
EECK
EEDI
EEDO
VSSR1
AVDD
AVSS
AVSS
DP
AVSS
DM
AVSS
AVDD
EXTWAKEUPN
NC
NC
VDD
MDC
MDIO
NC
NC
NC
NC
VSS
VDD
COL
NC
TXCLK
CRS
TXD0
TXD1
TXD2
TXD3
TXEN
VDD
RXCLK
RXD0
RXD1
RXD2
RXD3
VDD
RXER
RXDV
VSS
L5 F.BEAD.
R3
10K
C14
0.47uF
C7
24P
Y1
12.000MHz
C6
24P R6
1M
R7
220
RX_CLK
RXD0
RXD2
TXEN
TXD0
/PHY_RST
GND
TXD1
RXD1
TX_CLK
MDIO
VDD3
CRS
TXD3
COL
RXDV
TXD2
RXER
MDC
RXD3
USB Port Link/Act LED
1206 & DIP 1206 & DIP
1206 & DIP
1206 & DIP 1206 & DIP
AVSS and PVSS :
Single-point
ground
AX88172 USB to Fast Ethernet/HomePNA Controller
ASIX ELECTRONICS CORPORATION
25
RTL8201BL MII1.0 2.2
RTL8201BL application circuit - interface with MAC(MII)
B
22Friday, December 20, 2002
Title
Size Document Number Rev
Date: Sheet of
VDD3
VDD3
VDD3
VDD3
GND
CH_GND
GND
GND
GND GND
GND
GND GND
GND
LED2
LED0
LED3
LED4
LED1
X1 X2
VDD3
GND
GND
GND
VDD3
VDD3
LED4/PHYAD4
LED1/PHYAD1
GND
AVDD3
VDD3
GND
GND
LED3/PHYAD3
PHY_RST
AVDD3
DVDD25
LED0/PHYAD0
AVDD25
LED2/PHYAD2
DVDD25
X1
X2
TXD0
TXD1
TXD2
TXD3
TXEN
COL
RXER
TXC
MDC
MDIO
RXC
RXDV
RXD3
RXD2
RXD1
RXD0
CRS
C42
0.01U/3KV
R14
50
R23
75
C38
0.1U
R21
75
R20
5.6K (1%)
U5
RTL8201BL LQFP48
25
26
6
5
4
3
2
7
22
21
20
19
18
16
1
23
46
47
9
10
12
13
15
8
14
11
17
32
36
48
29
35
45
24
27
34
33
31
30
28
43
40
42
39
38
37
41
44
MDC
MDIO
TXD0
TXD1
TXD2
TXD3
TXEN
TXC
RXDV
RXD0
RXD1
RXD2
RXD3
RXC
COL
CRS
X1
X2
LED0/PHYAD0
LED1/PHYAD1
LED2/PHYAD2
LED3/PHYAD3
LED4/PHYAD4
DVDD25
DVDD33
DGND
DGND
AVDD25
AVDD33
DVDD33
AGND
AGND
AGND
RXER/FXEN
NC
TPTX+
TPTX-
TPRX+
TPRX-
RTSET
ISOLATE
RPTR
RESETB
SPEED
DUPLEX
ANE
LDPS
MII/SNIB/RTT3
C48
0.1U
L8
BEAD
C49
0.1U
C45
22U C46
0.1U C47
0.1U
L7
BEAD
R19
50
C41
0.1U
R18
50
R39 510
R43 510
R41 510
R42 4.7K
R40 4.7K
R38 4.7K
D2
LED
D3
LED
R34 510
R37 510
R36 4.7K
R32 4.7K
R12 1.5K
R17
2K
R15 20
R16 20
R26
5.1K
R25
5.1K
C50
0.1U
Y2 CRYSTAL 25.000 MHz
R35 0
R33 1M
C43
20P C44
20P
D6
LED
D4
LED
D5
LED
R30
5.1K
R29
5.1K
R28
5.1K
R27
5.1K R31
5.1K
U6
PE68515
1
2
3
15
14
16
7
5
6
11
12
10
RD+
RD-
CT
TD-
CT
TD+
RX+
CT
RX-
TX-
CMT
TX+
R13
50
C37
0.1U
C39
0.1U
C40
0.1U
R22
75
U7
RJ8-45
1
2
3
4
5
6
7
8 9
TX+
TX-
RX+
N/C
N/C
RX-
N/C
N/C GND
R24
75
AVDD25
AVDD25
COL
TXD1
RXER
MDIO
TXEN
TXD0
MDC
CRS
TXD3
TXD2
RX_CLK
TX_CLK RXDV
RXD0
RXD1
RXD3
RXD2
for EMI supression
(CONNECT TO CHASSIS GND)
RTL8201BL has built in 3.3V to 2.5V regulator, and
pin 8(AVDD25) sources out 2.5V. A 22uF capacitir
and a 0.1uF capacitor are recommended between
AVDD25 and GND. Place C14, C15, L4 close to AVDD25
and place C11 close to DVDD25.
U1/pin14 U1/pin48
Place L2, C17, C18, C19 as close to each power pin
as possible.
Hardwire Configuration network:
1. This configuration shows
Enable: Auto negotiation, Full duplex, 100Mbps,
Link Down Power Saving, MII interface
Disable: Isolate, Repeater mode
2. These senven configuration pins could be connected to VDD
or GND directly.
Link 100-Active
FULL LED
COLL
Set PHY ADDRESS TO 00011
Link 10-Active
Link LED
RTL8201BL
R18 value need fine tune,
the range may from 2K to
5.6K
26
AX88172 PRELIMINARY
Remark:
The schematic change between ED2 and ED3 are shown following:
1. 60MHZ oscillator is no longer needed
2. AX88172 Pin 23 need coonect to VBUS in ED3
3. Pin 70 (CLKI) changes from 60MHz OSC to NC,
4. Pin 71 (test mode) from VDD3L to NC.
27
AX88172 PRELIMINARY
Revisions history
Revision Date Comment
V. 1.0 12/25/01 Initial Release
V.1.1 12/28/01 Pin 62 change from “SROM size to NC”
R1 change from 6K +/-1% to 6.2K+/-1%
Power on reset specific 6ms ~10ms
“Primary”PHY ID change to “First” PHY ID in
EEPROM memory mapping
V.1.2 2002/2/25 Pin 62 change from “NC” to “RST_TYPE”
Pin 72 change from “RESET” to”RESET/RESET”
On page 12 modify following:
USB vendor command modify from “disable H/W
MII operation” to “Software MII operation”
USB vendor command modify from “Enable H/W MII
operation” to “Hardware MII operation”
Read/write Mointor mode at read bit 7-5 change
from 100 to 101”
Add /Reset timing
Reference design schematic updated
BOM update
V.1.3 2002/5/7 Chip ED2 new schematic with external 60 MHZ
Add RTl 8201 BL version schematic
Remove BOM
V.1.4 2002/12/20
dd ED3 reference design with RTL 8201BL version
PHY and remark the difference
Add 12M osc spec
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