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© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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Doc. No. 1078, Rev. H
CAT28F001
1 Megabit CMOS Boot Block Flash Memory
FEATURES
■Fast Read Access Time: 90/120 ns
■On-Chip Address and Data Latches
■Blocked Architecture
— One 8 KB Boot Block w/ Lock Out
• Top or Bottom Locations
— Two 4 KB Parameter Blocks
— One 112 KB Main Block
■Low Power CMOS Operation
■12.0V ± 5% Programming and Erase Voltage
■Automated Program & Erase Algorithms
■High Speed Programming
■Commercial, Industrial and Automotive
Temperature Ranges
■Deep Powerdown Mode
— 0.05 µA ICC Typical
— 0.8 µA IPP Typical
■Hardware Data Protection
■Electronic Signature
■100,000 Program/Erase Cycles and 10 Year
Data Retention
■JEDEC Standard Pinouts:
— 32 pin DIP
— 32 pin PLCC
— 32 pin TSOP
■Reset/Deep Power Down Mode
■"Green" Package Options Available
I/O0–I/O7
I/O BUFFERS
CE, OE LOGIC SENSE
AMP
DATA
LATCH
ERASE VOLTAGE
SWITCH
COMMAND
REGISTER
CE
OE
WE
VOLTAGE VERIFY
SWITCH
ADDRESS LATCH
Y-DECODER
X-DECODER
Y-GATING
8K-BYTE BOOT BLOCK
4K-BYTE PARAMETER BLOCK
4K-BYTE PARAMETER BLOCK
112K-BYTE MAIN BLOCK
A0–A16
WRITE STATE
MACHINE
ADDRESS
COUNTER
STATUS
REGISTER
COMPARATOR
PROGRAM VOLTAGE
SWITCH
RP
BLOCK DIAGRAM
DESCRIPTION
The CAT28F001 is a high speed 128K X 8 bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F001 has a blocked architecture with one 8
KB Boot Block, two 4 KB Parameter Blocks and one 112
KB Main Block. The Boot Block section can be at the top
or bottom of the memory map and includes a reprogram-
ming write lock out feature to guarantee data integrity. It
is designed to contain secure code which will bring up
the system minimally and download code to other loca-
tions of CAT28F001.
The CAT28F001 is designed with a signature mode
which allows the user to identify the IC manufacturer and
device type. The CAT28F001 is also designed with on-
Chip Address Latches, Data Latches, Programming and
Erase Algorithms.
The CAT28F001 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, PLCC or TSOP packages.
Licensed Intel
second source
CAT28F001
2
Doc. No. 1078, Rev. H
PIN CONFIGURATION
DIP Package (P, L)
TSOP Package (Standard Pinout) (T, H)
PIN FUNCTIONS
Pin Name Type Function
A0–A16 Input Address Inputs for
memory addressing
I/O0–I/O7I/O Data Input/Output
CE Input Chip Enable
OE Input Output Enable
WE Input Write Enable
VCC Voltage Supply
VSS Ground
VPP Program/Erase
Voltage Supply
RP Input Power Down
28F001 F02
PLCC Package (N, G)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
A4
A5
A6
A7
A12
A15
A16
VPP
VCC
WE
RP
A14
A13
A8
A9
A11
I/O0
I/O1
I/O2
VSS
I/O6
I/O5
I/O4
I/O3
13
14
15
16
20
19
18
17
9
10
11
12
24
23
22
21
A3
A2
A1
A0
OE
A10
CE
I/O7
A7
A6
A5
A4
5
6
7
8
1
2
3
4
VPP
A16
A15
A12
A13
A8
A9
A11
28
27
26
25
32
31
30
29
VCC
WE
RP
A14
A7
A6
A5
A4
5
6
7
8
A3
A2
A1
A0
9
10
11
12
I/O013
A14
A13
A8
A9
29
28
27
26
A11
OE
A10
CE
25
24
23
22
I/O7
21
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
14 15 16 17 18 19 20
4321323130
A12
A15
A16
VPP
VCC
WE
RP
CAT28F001
3Doc. No. 1078, Rev. H
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
(Except A9, RP, OE, VCC and VPP)
Voltage on Pin A9, RP AND OE with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Test Method
NEND(3) Endurance 100K Cycles/Byte MIL-STD-883, Test Method 1033
TDR(3) Data Retention 10 Years MIL-STD-883, Test Method 1008
VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(3)(4) Latch-Up 100 mA JEDEC Standard 17
CAPACITANCE TA = 25°C, f = 1.0 MHz
Limits
Symbol Test Min Max. Units Conditions
CIN(3) Input Pin Capacitance 8 pF VIN = 0V
COUT(3) Output Pin Capacitance 12 pF VOUT = 0V
CVPP(3) VPP Supply Capacitance 25 pF VPP = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
CAT28F001
4
Doc. No. 1078, Rev. H
D.C. OPERATING CHARACTERISTICS
VCC = +5V ±10%, unless otherwise specified
Limits
Symbol Parameter Min. Max. Unit Test Conditions
ILI Input Leakage Current ±1.0 µAV
IN = VCC or VSS
VCC = 5.5V
ILO Output Leakage Current ±10 µAV
OUT = VCC or VSS,
VCC = 5.5V
ISB1 VCC Standby Current CMOS 100 µA CE = VCC ±0.2V = RP
VCC = 5.5V
ISB2 VCC Standby Current TTL 1.5 mA CE = RP = VIH, VCC = 5.5V
IPPD VPP Deep Powerdown Current 1.0 µA RP = GND±0.2V
ICC1 VCC Active Read Current 30 mA VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 8 MHz
ICC2(1) VCC Programming Current 20 mA VCC = 5.5V,
Programming in Progress
ICC3(1) VCC Erase Current 20 mA VCC = 5.5V,
Erase in Progress
IPPS VPP Standby Current ±10 µAV
PP < VCC
200 µAV
PP > VCC
IPP1 VPP Read Current 200 µAV
PP = VPPH
IPP2(1) VPP Programming Current 30 mA VPP = VPPH,
Programming in Progress
IPP3(1) VPP Erase Current 30 mA VPP = VPPH,
Erase in Progress
VIL Input Low Level –0.5 0.8 V
VOL Output Low Level 0.45 V IOL = 5.8mA, VCC = 4.5V
VIH Input High Level 2.0 VCC+0.5 V
VOH Output High Level 2.4 V IOH = 2.5mA, VCC = 4.5V
VID A9 Signature Voltage 11.5 13.0 V A9 = VID
IID A9 Signature Current 500 µAA
9 = VID
ICCD VCC Deep Powerdown Current 1.0 µA RP = GND±0.2V
ICCES VCC Erase Suspend Current 10 mA Erase Suspended CE = VIH
IPPES VPP Erase Suspend Current 300 µA Erase Suspended
VPP=VPPH
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
CAT28F001
5Doc. No. 1078, Rev. H
SUPPLY CHARACTERISTICS
Limits
Symbol Parameter Min Max. Unit
VLKO VCC Erase/Write Lock Voltage 2.5 V
VCC VCC Supply Voltage 4.5 5.5 V
VPPL VPP During Read Operations 0 6.5 V
VPPH VPP During Erase/Program 11.4 12.6 V
VHH RP, OE Unlock Voltage 11.4 12.6 V
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For High Speed Input Pulse Levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For High Speed Input and Output Timing Reference = 1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For load and reference points, see Fig. 1
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 100 pF
OUT
CL INCLUDES JIG CAPACITANCE
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.8 V
VCC - 0.3V
0.0 V
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
Testing Load Circuit (example)
1.3V
DEVICE
UNDER
TEST
1N914
3.3K
CL = 30 pF
OUT
CL INCLUDES JIG CAPACITANCE
INPUT PULSE LEVELS REFERENCE POINTS
3.0 V
0.0 V
1.5 V
Figure 2. Highspeed A.C. Testing Input/Output
Waveform(3)(4)(5)
Testing Load Circuit (example)
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CAT28F001
6
Doc. No. 1078, Rev. H
A.C. CHARACTERISTICS, Program/Erase Operation
VCC = +5V ±10%
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
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CAT28F001
7Doc. No. 1078, Rev. H
ERASE AND PROGRAMMING PERFORMANCE
FUNCTION TABLE(1)
Pins
Mode RPRP
RPRP
RP CECE
CECE
CE OEOE
OEOE
OE WEWE
WEWE
WE VPP I/O Notes
Read VIH VIL VIL VIH XD
OUT
Output Disable VIH VIL VIH VIH X High-Z
Standby VIH VIH X X X High-Z
Signature (MFG) VIH VIL VIL VIH X 31H A0 = VIL, A9 = 12V
Signature (Device) VIH VIL VIL VIH X 94H-28F001T A0 = VIH, A9 = 12V
95H-28F001B
Write Cycle VIH VIL VIH VIL XD
IN During Write Cycle
Deep Power Down VIL XXXXHIGH-Z
WRITE COMMAND TABLE
Commands are written into the command register in one or two write cycles. Write cycles also internally latch
addresses and data required for programming and erase operations.
First Bus Cycle Second Bus Cycle
Mode Operation Address DIN Operation Address DIN DOUT
Read Array/Reset Write X FFH
Program Setup/ Write AIN 40H Write AIN DIN
Program 10H
Read Status Reg. Write X 70H Read X St. Reg. Data
Clear Status Reg. Write X 50H
Erase Setup/Erase Write Block ad 20H Write Block ad D0H
Confirm
Erase Suspend/ Write X B0H Write X D0H
Erase Resume
Read Sig (Mfg) Write X 90H Read 0000H 31H
Read Sig (Dev) Write X 90H Read 0001H 94H-28F001T
95H-28F001B
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH)
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CAT28F001
8
Doc. No. 1078, Rev. H
READ OPERATIONS
Read Mode
The CAT28F001 memory can be read from any of its
Blocks (Boot Block, Main Block or Parameter Block),
Status Register and Signature Information by sending
the Read Command Mode to the Command Register.
CAT28F001 automatically resets to Read Array mode
upon initial device power up or after exit from deep
power down. A Read operation is performed with both
CE and OE low and with RP and OE high. Vpp can be
either high or low. The data retrieved from the I/O pins
reflects the contents of the memory location correspond-
ing to the state of the 17 address pins. The respective
timing waveforms for the read operation are shown in
Figure 3. Refer to the AC Read characteristics for
specific timing parameters.
Signature Mode
The signature mode allows the user to identify the IC
manufacturer and the type of the device while the device
resides in the target system. This mode can be activated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).
The conventional method is entered as a regular read
mode by driving the CE and OE low (with WE high), and
applying the required high voltage on address pin A9
while the other address line are held at VIL.
A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O7 to I/O0:
Catalyst Code = 0011 0001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O7 to I/O0:
CAT28F001T = 1001 0100 (94H)
CAT28F001B = 1001 0101 (95H)
Standby Mode
With CE at a logic-high level, the CAT28F001 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power con-
sumption. The outputs are placed in a high-impendance
state independent of the OE status.
Deep Power-Down
When RP is at logic-low level, the CAT28F001 is placed
in a Deep Power-Down mode where all the device
circuitry are disabled, thereby reducing the power con-
sumption to 0.25µW.
Figure 3. A.C. Timing for Read Operation
ADDRESSES
CE (E)
OE (G)
WE (W)
DATA (I/O) HIGH-Z
POWER UP STANDBY DEVICE AND
ADDRESS SELECTION
OUPUTS
ENABLED
DATA VALID STANDBY
ADDRESS STABLE
OUTPUT VALID
tAVQV (tACC)
tELQX (tLZ)
tGLQX (tOLZ)
tGLQV (tOE)
tELQV (tCE)
tOH
tGHQZ (tDF)
tEHQZ
tAVAV (tRC)
POWER DOWN
HIGH-Z
tPHQV (tPWH)
RP (P)
CAT28F001
9Doc. No. 1078, Rev. H
WRITE OPERATIONS
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Array
The device can be put into a Read Array Mode by
initiating a write cycle with FFH on the data bus. The
device is also in a standard Read Array Mode after the
initial device power up and when comes out of the Deep
Power-Down mode.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register. A read cycle
from address 0000H with CE and OE low (and WE high)
will output the device signature.
Catalyst Code = Catalyst Code = 0011 0001 (31H)
A Read cycle from address 0001H retrieves the
binary code for the device on outputs I/O7 to I/O0:
CAT28F001T = 1001 0100 (94H)
CAT28F001B = 1001 0101 (95H)
To terminate the operations, it is necessary to write
another valid command into the register.
STATUS REGISTER
The 28F001 contains an 8-bit Status Register. The
Status Register is polled to check for write or erase
completion or any related errors. The Status Register
may be read at any time by issuing a Read Status
Register (70H) command. All subsequent read opera-
tions output data from the Status Register, until another
valid command is issued. The contents of the Status
Register are latched on the falling edge of OE or CE ,
whichever occurs last in the read cycle. OE or CE must
be toggled to VIH before further reads to update the
status register latch.
The Erase Status (SR.5) and Program Status (SR.4) are
set to 1 by the WSM and can only be reset issuing Clear
Status Register (50H) These two bits can be polled for
failures, thus allowing more flexibility to the designer
when using the CAT28F001. Also, VPP Status (SR.3)
when set to 1 must be reset by system software before
any further byte programs or block erases are attempted.
ERASE SETUP/ERASE CONFIRM
Erase is executed one block at a time, initiated by a two
cycle command sequence. The two cycle command
sequence provides added security against accidental
block erasure. During the first write cycle, a Command
20H (Erase Setup) is first written to the Command
Register, followed by the Command D0H (Erase Con-
firm). These commands require both appropriate com-
mand data and an address within Block to be erased.
Also, Block erasure can only occur when VPP= VPPH.
Block preconditioning, erase and verify are all handled
internally by the Write State Machine, invisible to the
system. After receiving the two command erase se-
quence the CAT28F001 automatically outputs Status
Register data when read (Fig.5). The CPU can detect
the completion of the erase event by checking if the
SR.7 of the Status Register is set.
SR.5 will indicate whether the erase was successful. If
an erase error is detected, the Status Register should be
cleared. The device will be in the Status Register Read
Mode until another command is issued.
ERASE SUSPEND/ERASE RESUME
The Erase Suspend Command allows erase sequence
interruption in order to read data from another block of
memory. Once the erase sequence is started, writing
the Erase Suspend command (B0H) to the Command
Register requests that the WSM suspend the erase
sequence at a predetermined point in the erase algo-
rithm. The CAT28F001 continues to output Status Reg-
ister data when read, after the Erase Suspend command
is written to it. Polling the WSM Status and Erase
Suspend Status bits will determine when the erase
operation has been suspended (both will be set to “1s”).
The device may now be given a Read ARRAY Com-
mand, which allows any locations 'not within the block
being erased' to be read. Also, you can either perform
a Read Status Register or resume the Erase Operation
by sending Erase Resume (D0H), at which time the
WSM will continue with the erase sequence. The Erase
Suspend Status and WSM Status bits of the Status
Register will be cleared.
PROGRAM SETUP/PROGRAM COMMANDS
Programming is executed by a two-write sequence. The
program Setup command (40H) is written to the Com-
mand Register, followed by a second write specifying
the address and data (latched on the rising edge of WE)
to be programmed. The WSM then takes over, control-
ling the program and verify algorithms internally. After
the two-command program sequence is written to it, the
CAT28F001 automatically outputs Status Register data
when read (see figure 4; Byte Program Flowchart). The
CPU can detect the completion of the program event by
analyzing the WSM Status bit of the Status Register.
Only the Read Status Register Command is valid while
programming is active.
CAT28F001
10
Doc. No. 1078, Rev. H
When the Status Register indicates that programming is
complete, the Program Status bit should be checked. If
program error is detected, the Status Register should be
cleared. The internal WSM verify only detects errors for
“1s” that do not successfully program to “0s”. The
Command Register remains in Read Status Register
mode until further commands are issued to it.
If erase/byte program is attempted while VPP = VPPL, the
Status bit (SR.5/SR.4) will be set to “1”. Erase/Program
attempts while VPPL < V
PP < V
PPH produce spurious
results and should not be attempted.
EMBEDDED ALGORITHMS
The CAT28F001 integrates the Quick Pulse program-
ming algorithm on-chip, using the Command Register,
Status Register and Write State Machine (WSM). On-
chip integration dramatically simplifies system software
and provides processor-like interface timings to the
Command and Status Registers. WSM operation, inter-
nal program verify, and VPP high voltage presence are
monitored and reported via appropriate Status Register
bits. Figure 4 shows a system software flowchart for
device programming.
As above, the Quick Erase algorithm is now imple-
mented internally, including all preconditioning of block
data. WSM operation, erase verify and VPP high voltage
presence are monitored and reported through the Status
Register. Additionally, if a command other than Erase
Confirm is written to the device after Erase Setup has
been written, both the Erase Status and Program Status
bits will be set to “1”. When issuing the Erase Setup and
Erase Confirm commands, they should be written to an
address within the address range of the block to be
erased. Figure 5 shows a system software flowchart for
block erase.
The entire sequence is performed with VPP at VPPH.
Abort occurs when RP transitions to VIL, or VPP drops to
VPPL. Although the WSM is halted, byte data is partially
programmed or Block data is partially erased at the
location where it was aborted. Block erasure or a repeat
of byte programming will initialize this data to a known
value.
BOOT BLOCK PROGRAM AND ERASE
The boot block is intended to contain secure code which
will minimally bring up a system and control program-
ming and erase of other blocks of the device, if needed.
Therefore, additional “lockout” protection is provided to
guarantee data integrity. Boot block program and erase
operations are enabled through high voltage VHH on
either RP or OE, and the normal program and erase
command sequences are used. Reference the AC
Waveforms for Program/Erase.
If boot block program or erase is attempted while RP is
at VIH, either the Program Status or Erase Status bit will
be set to “1”, reflective of the operation being attempted
and indicating boot block lock. Program/erase attempts
while VIH < RP < VHH produce spurious results and
should not be attempted.
NOTES:
The Write State Machine Status Bit must first be checked to
determine program or erase completion, before the
Program or Erase Status bits are checked for success.
If the Program AND Erase Status bits are set to “1s” during an
erase attempt, an improper command sequence was
entered. Attempt the operation again.
If VPP low status is detected, the Status Register must be
cleared before another program or erase operation is
attempted.
The VPP Status bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
the VPP level only after the program or erase command
sequences have been entered and informs the system if
VPP has not been switched on. The VPP Status bit is not
guaranteed to report accurate feedback between VPPL and
VPPH.
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
0 = Erase in Progress/Completed
SR.5 = ERASE STATUS
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = PROGRAM STATUS
1 = Error in Byte Program
0 = Successful Byte Program
SR.3 = VPP STATUS
1 = VPP Low Detect; Operation Abort
0 = VPP Okay
SR.2 -SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked
out when polling the Status Register.
WSMS ESS ES PS VPPS R R R
76543210
CAT28F001
11 Doc. No. 1078, Rev. H
Bus
Operation Command Comments
Write Program Data = 40H
Setup Address = Bytes to be Programmed
Write Program Data to be programmed
Address = Byte to be Programmed
Read Status Register Data.
Toggle OE or CE to update
Status Register
Check SR.7
Standby 1 = Ready, 0 = Busy
Repeat for subsequent bytes.
Full Status check can be done after each byte or after a sequence
of bytes.
Write FFH after the last byte programming operation to reset the
device to Read Array Mode.
Bus
Operation Command Comments
Standby Check SR.3
1 = VPP Low Detect
Standby Check SR.3
1 = Byte Program Error
SR.3 MUST be cleared, if set during a program attempt, before
further attempts are allowed by the Write State Machine.
SR.3 is only cleared by the Clear Status Register Command, in
case where multiple bytes are programmed before full status is
checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
START
WRITE 40H,
BYTE ADDRESS
READ STATUS
REGISTER
SR.7 = 1?
FULL STATUS
CHECK IF DESIRED
BYTE PROGRAM
COMPLETED
STATUS REGISTER DATA
READ (SEE ABOVE)
SR.3 = 0?
SR.4 = 0?
BYTE PROGRAM
SUCCESSFUL
NO
NO
WRITE BYTE
ADDRESS/DATA
FULL STATUS CHECK PROCEDURE
NO
V
PP
RANGE
ERROR
BYTE PROGRAM
ERROR
YES
YES
YES
Figure 4 Byte Programming Flowchart
IN-SYSTEM OPERATION
For on-board programming, the RP pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase confirms commands, RP must
transition to VHH. Hold RP at this high voltage throughout
the program or erase interval (until after Status Register
confirm of successful completion). At this time, it can
return to VIH or VIL.
CAT28F001
12
Doc. No. 1078, Rev. H
Bus
Operation Command Comments
Write Erase Data = 20H
Setup Address = Within Block to be erased
Write Erase Data - D0H
Address = Within Block to be erased
Read Status Register Data.
Toggle OE or CE to update
Status Register
Standby Check SR.7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Full Status check can be done after each block or after a sequence
of blocks.
Write FFH after the last block erase operation to reset the device to
Read Array Mode.
Bus
Operation Command Comments
Standby Check SR.3
1 = VPP Low Detect
Standby Check SR.4
Both 1 = Command Sequence Error
Standby Check SR.5
1 = Block Erase Error
SR.3 MUST be cleared, if set during a erase attempt, before further
attempts are allowed by the Write State Machine.
SR.3 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erased before full status is
checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Figure 5 Block Erase Flowchart
START
WRITE 20H,
BLOCK ADDRESS
READ STATUS
REGISTER
SR.7 = 1?
FULL STATUS
CHECK IF DESIRED
BLOCK ERASE
COMPLETED
STATUS REGISTER DATA
READ (SEE ABOVE)
SR.3 = 0?
SR.5 = 0?
BLOCK ERASE
SUCCESSFUL
NO
NO
WRITE D0H
BLOCK ADDRESS
FULL STATUS CHECK PROCEDURE
NO
V
PP
RANGE
ERROR
BLOCK ERASE
ERROR
SR.4,5 = 1? YES COMMAND SEQUENCE
ERROR
SUSPEND
ERASE?
NO
ERASE SUSPEND
LOOP
YES
YES
NO
YES
CAT28F001
13 Doc. No. 1078, Rev. H
Bus
Operation Command Comments
Write Erase Data = B0H
Suspend
Standby/ Read Status Register
Ready Check SR.7
1 = Ready, 0 = Busy
Toggle OE or CE to Update
Status Register
Standby Check SR.6
1 = Suspended
Write Read Array Data = FFH
Read Read array data from block other
than that being erased.
Write Erase Resume Data = D0H
START
WRITE B0H
READ STATUS
REGISTER
SR.7 = 1?
SR.6 = 1?
CONTINUE
ERASE
NO
DONE
READING?
WRITE FFH
WRITE D0H
NO
ERASE HAS
COMPLETED
YES
YES
NO
YES
Figure 6 Block Erase Suspend/Resume Flowchart
CAT28F001
14
Doc. No. 1078, Rev. H
POWER UP/DOWN PROTECTION
The CAT28F001 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F001 is reset to the Read Mode on
power up.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between VCC and VSS and VPP and VSS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Figure 7. A.C. Timing for Program/Erase Operation
ADDRESSES (A)
CE (E)
OE (G)
WE (W)
DATA (I/O)
RP (P)
VPP (V)
VIL
VIH
VPPL
VPPH
VIL
VIH
6.5V
VHH
VIL
VIH
VIL
VIH
VIL
VIH
tELWL tWHEH
tAVAV
AIN AIN
tAVWH tWHAX
tWHGL
tWHWL
tPHWL
tDVWH
tWLWH
tWHDX
tPHHWH tQVPH
tVPWH tQVVL
DIN DIN VALID
SRD DIN
HIGH Z
VIH
VIH
VCC POWER-UP
& STANDBY
WRITE PROGRAM OR
ERASE SETUP COMMAND
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
WRITE READ ARRAY
COMMAND
WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
VIL
VIL
tWHQV 1, 2, 3, 4
CAT28F001
15 Doc. No. 1078, Rev. H
ALTERNATE CE-CONTROLLED WRITES
VCC = +5V ±10%, unless otherwise specified
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
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CAT28F001
16
Doc. No. 1078, Rev. H
Figure 8. Alternate Boot Block Access Method Using OE
Figure 9. Alternate AC Waveform for Write Operations
WRITE PROGRAM OR
ERASE SETUP COMMAND
WRITE
VALID ADDRESS AND DATA (PROGRAM)
OR ERASE CONFIRM COMMAND AUTOMATED PROGRAM
OR ERASE DELAY READ STATUS
REGISTER DATA
VHH
VIH
VIL
VIH
VIL
VIH
VIL
DIN DIN
tGHHWL tWHGH
VALID
SR DATA
OE
WE
DATA
ADDRESSES
CE (E)
OE (a)
WE (W)
DATA I/O
RP (P)
VPP (V)
VIL
VIH
VPPL
VPPH
VIL
VIH
6.5V
VHH
VIL
VIH
VIL
VIH
VIL
VIH
tWLEL tEHWH
tAVAV
AIN AIN
tAVEH tEHAX
tEHGL
tEHEL
tPHEL
tDVEH
tELEH
tEHDX
tPHHEH tQVPH
tVPEH tQVVL
DIN DIN VALID
SRD DIN
HIGH Z
VIH
VIH
VCC POWER-UP
& STANDBY
WRITE PROGRAM OR
ERASE SETUP COMMAND
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
WRITE READ ARRAY
COMMAND
WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
VIL
VIL
tEHQV 1, 2, 3, 4
CAT28F001
17 Doc. No. 1078, Rev. H
ORDERING INFORMATION
Note:
(1) The device used in the above example is a CAT28F001PI-90BT (PDIP, Industrial Temperature, 90ns access time, Bottom Boot Block,
Tape & Reel)
Prefix Device # Suffix
28F001 PI
Product
Number Temperature Range
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Tape & Reel
Package
N: PLCC
P: PDIP
T: TSOP(8mmx20mm)
G: PLCC (Lead free, Halogen free)
L: PDIP (Lead free, Halogen free)
H: TSOP (Lead free, Halogen free)
Speed
90: 90 ns
12: 120 ns
-90CAT B
Boot Block
B: Bottom
T: Top
* -40˚ to +125˚C is available upon request
Optional
Company ID
BT
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Publication #: 1078
Revison: H
Issue date: 09/21/04
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
REVISION HISTORY
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