ee March 1998 FAIRCHILD ee SEMICONDUCTOR 100304 Low Power Quint AND/NAND Gate General Description @ 2000V ESD protection @ Pin/uncti ible with 100104 The 100304 is monolithic quint AND/NAND gate. The Func- in/function compatible wit tion output is the wire-NOR of all five AND gate outputs. All . Voltage compensated operating range = 4.2V to -5.7V inputs have 50 kQ pull-down resistors. @ Available to industrial grade temperature range @ Available to MIL-STD-883 Features mw Low Power Operation Ordering Code: Logic Symbol FE Dia Oa Oza Oa Dip Op Dap Op Dic Oc Doe Oc Dia Og Deg Og Die Oc D2e Oo DS010681-1 Logic Equation F = (Dra * Daa) + (Dip * Dag) + Dic + Dag) + (Dra * Daa) + (Dre * Daz). Pin Names Description DnaDPne Data Inputs F Function Output O,-O, Data Outputs 0,-O, Complementary Data Outputs 1998 Fairchild Semiconductor Corporation DS010581 www fairchildsemi.com 3185 GNVN/GNV IUINH 18M0d MO] POE00!Connection Diagrams 24-Pin DIP ar 0.41 24 F-Dp, 0,42 23Dy, Oy-q3 22-Diy Oy-44 21 Dog F5 20 D2, Veo 8 19F-Di, Veca 7 18 F- Vee 0.48 17 Da, 0-49 16 Fy, Op-410 15 Do, Ott 14D, , 04-412 13-0, DS010881-2 28-Pin PCC Dog Dia %Vees % Op fy fo] (2) ] Ty Dos Vee Vers Dre Doe Dog Dig Di_DaeVeES% I Og DSO 1058 1-4 24-Pin Quad Cerpak Dod Poe Die Ver Pap Pip Lt tt td 24 23 22 21 20 19 Dig! 18 F=Do, Die-2 17D, Dog 3 16-0, 0,44 15F-0, e158 14-0, Oy46 13,0, 7 8 9 10 11 12 ITUriutd 9g F Yee Yoca % % DS010681-3 www fairchildsemi.comAbsolute Maximum Ratings (note 1) Recommended Operating Above which the useful life may be impaired Conditions Storage Temperature (Tera) -65C to +150C Case Temperature (T) Maximum Junction Temperature (T,) Commercial 0C to 485C Ceramic +175C Industrial -40C to +85C Plastic +1506 Milt 56C to +125C Vee Pin Potential to Ground Pin -7.0V to +0.5V ary ~ o+ Input Voltage (DS) Vee to +0.8V Nolet hbwokan nee ti th lues b ond whe he ote 1: solute Maximum ratings are those values beyond wnicl je de- Output Current (DC Output HIGH) -50 mA vice may be damaged or have its useful life impaired. Functional operation ESD (Note 2) 22000V under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics Vee = -4.2V to -5.7V, Voc = Veca = GND, Te = 0C to +85C (Note 3) Symbol Parameter Min Typ Max Units Conditions Vou Output HIGH Voltage -1025 -955 -870 mV Vin =Vin (Max) Loading with Voi Output LOW Voltage -1830 -1705 -1620 mV or Vit (min) 50Q to -2.0V Vouc Output HIGH Voltage -1035 mV Vin = Vincminy Loading with Vote Output LOW Voltage -1610 mV or Vit (Max) 50Q to -2.0V Vin Input HIGH Voltage -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 HA Vin = Vic aminy liq Input High Current Doa-D2e 250 HA Vin = Vin(Max) DiaDie 350 lee Power Supply Current -69 -43 -30 mA Inputs open Note 3: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. DIP AC Electrical Characteristics Ver = -4.2V to -5.7V, Voo = Veca = GND Symbol Parameter To = 0'C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay 0.40 1.75 0.40 1.65 0.40 1.75 ns teHL Dna-Dne to O, 3 teLy Propagation Delay 1.00 2.60 1.00 2.60 1.15 3.20 ns Figures 1, 2 teu Data to F toy Transition Time 0.35 1.20 0.35 1.20 0.35 1.20 ns true 20% to 80%, 80% to 20% 3 www fairchildsemi.comPCC and Cerpak AC Electrical Characteristics Vee = 4.2V to -5.7V, Voo = Veca = GND Symbol Parameter Te = 0C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay 0.40 1.55 0.40 1.45 0.40 1.55 ns teu Dna-Dne to O, ) teLy Propagation Delay 1.00 2.40 1.00 2.40 1.15 3.00 ns Figures 1, 2 tpHL Data to F tty Transition Time 0.35 1.10 0.35 1.15 0.35 1.10 ns true 20% to 80%, 80% to 20% Industrial Version PCC DC Electrical Characteristics Vee = -4.2V to -5.7V, Veco = Veca = GND, To = -40C to +85C (Note 4) Symbol Parameter To = -40C To = OC to +85C Units Conditions Min Max Min Max Vou Output HIGH Voltage -1085 -870 -1025 -870 mV Vin =Vin (Max) Loading with VoL Output LOW Voltage -1830 8 -1575 -1830 -1620 or Vit (min) 50Q to -2.0V Vouc Output HIGH Voltage -1095 -1035 mV Vin = Vinqminy Loading with Voto Output LOW Voltage -1565 -1610 or Vit (max) 50Q to -2.0V Vin Input HIGH Voltage -1170 -870 -1165 -870 mV Guaranteed HIGH Signal for All Inputs Vit Input LOW Voltage -1830 -1480 -1830 -1475 mV Guaranteed LOW Signal for All Inputs lit Input LOW Current 0.50 0.50 HA Vin = Vic amin) liq Input HIGH Current DzaDoe 250 250 HA Vin = Vin (max) DiaDie 350 350 lee Power Supply Current -69 -30 -69 -30 mA Inputs Open PCC AC Electrical Characteristics Vee = 4.2V to -5.7V, Voo = Voca = GND Note 4: The specified limits represent the "worst case value for the parameter. Since these values normally occur at the temperature extremes, additional noise im- munity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under worst case conditions. Symbol Parameter Te = 40C To = +25C To = +85C Units Conditions Min Max Min Max Min Max teLy Propagation Delay 0.35 1.55 0.40 1.45 0.40 1.55 ns teHL Dna-Dne to O, 5 teLy Propagation Delay 1.00 2.40 1.00 2.40 1.15 3.00 ns . Figures 1, 2 teu Data to F troy Transition Time 0.35 1.10 0.35 1.15 0.35 1.10 ns trot 20% to 80%, 80% to 20% www fairchildsemi.comMilitary Version DC Electrical Characteristics Ver = -4.2V to -5.7V, Vog = Voca = GND, Ty = -55C to +125C Symbol Parameter Min Max | Units Te Conditions Notes Vou Output HIGH Voltage |-1025 | -870 mV 0C to +125C -1085 | -870 mV -55C Vin = Vin (Max) Loading with (Notes 5, 6, 7) VoL Output LOW Voltage |-1830 |}-1620 | mV 0C to or Vi (Min) 500 to -2.0V +125C -1830 |-1555 | mV -55C Vouc Output HIGH Voltage |-1035 mV 0C to +125C -1085 mV -55C Vin = Vin (Min) Loading with (Notes 5, 6, 7) Vote Output LOW Voltage -1610 | mV 0C to or Vi_ (Max) 50Q to -2.0V +125C -1555 | mV -55C Vin Input HIGH Voltage -1165 | -870 mV -55C Guaranteed HIGH Signal (Notes 5, 6, 7, 8) +125C | for All Inputs Vit Input LOW Voltage -1830 |-1475 | mV -55C to | Guaranteed LOW Signal (Notes 5, 6, 7, 8) +125C | for All Inputs lit Input LOW Current 0.50 HA -58C to | Vee = -4.2V (Notes 5, 6, 7) +125C | Vin = Vit (Min) Input High Current DaagDoe 250 HA 0C to Dia-Die 350 +125C | Vee = -8.7V (Notes 5, 6, 7) iy Vin = Vin (Max) DaaDoe 350 HA -55C Dia-Dyo 500 lee Power Supply Current | -75 -25 mA -58C to Inputs Open (Notes 5, 6, 7) +125C Note 5: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55'C), then testing immediately without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 6: Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups, 1, 2 3, 7, and 8. Note 7: Sample tested (Method 5005, Table |) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8. Note 8: Guaranteed by applying specified input condition and testing VoH/VoL. www fairchildsemi.comAC Electrical Characteristics Vee = -4.2V to -5.7V, Veo = Veca = GND Symbol Parameter To = -55C To = +25C Te = +125C | Units | Conditions Notes Min Max Min Max Min Max teLy Propagation Delay 0.30 1.90 0.40 1.80 0.30 2.30 ns teu Dna-Dne to 0, O (Notes 9, 10, 11) teLy Propagation Delay 0.80 2.90 0.90 2.80 0.90 3.40 ns Figures 1, 2 tpHL Data to F tty Transition Time 0.20 1.80 0.30 1.60 0.20 2.00 ns (Note 12) tru 20% to 80%, 80% to 20% Notes: Test Circuitry Note 9: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately after power-up. This provides cold start specs which can be considered a worst case condition at cold temperatures. Note 10: Screen tested 100% on each device at +25C temperature only, Subgroup AQ. Note 11: Sample tested (Method 5005, Table |) on each mfg. lot at +25C, Subgroup AQ, and at +125C and -55C temperatures, Subgroups A10 and A11. Note 12: Not tested at +25C, +125C, and -55C temperature (design characterization data). Voc. Veca = +2V, Veg = -2.5V L1 and L2 = equal length 50Q impedance lines Ry = 50Q terminator internal to scope Decoupling 0.1 pF from GND to Voc and Vee All unused outputs are loaded with 500 to GND C, = Fixture and stray capacitance < 3 pF L1 Oo SCOPE y 7 CHAN A CC 0.1 F L2 PULSE ON ROR On SCOPE GENERATOR i TEST Le CHAN 8 I L gs, 0.1,.F = vee T ~ DS010581-5 FIGURE 1. AC Test Circuit www fairchildsemi.comSwitching Waveforms 0.7 + 0.1 ns [orem ns +1.05 V +0.31 V OUTPUT tpLH >| tpt 80% 50% COMPLEMENT 20% trun >| [trv DS010681-6 FIGURE 2. Propagation Delay and Transition Times Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100304 D C QB Device Type (Basic) a | tL Special Variation QB = Military grade device with environmental and burn-in processing Package Code D = Ceramic DIP F = Quad Cerpak Temperature Range Q = Plastic Leaded Chip Carrier (PCC) C = Commercial (0C to + 85C) P = Plastic DIP | = Industrial ( 40C to + 85C) (PCC only) M = Military (55C to + 125C) DS010681-7 7 www fairchildsemi.comPhysical DimensiONS inches (millimeters) unless otherwise noted 24-Pin Plastic Dual-In-Line Package (P) Package Number N24E 1.215 - (30.86) ~ 9.025 MAX 0.030 0.055 (0.64) 24 13 6 nad a a 0.390 (9.91) MAX ! LPT BA ht Gel hel RA GT GA bal bel fl 2 >| Pe fesrston 0.005 GLASS 0.050 0.060 er 0.400 0.430 0.180 _ \~_ _ | j< ___ (0.13) SEALANT (1.27 - 1.52) mp 0.015 ~ 0.055 1, (10.16 10.92) (4.57) MIN TYP (0.38 1.40) Y MAX T 1 \ = 0.225 | le (5.72) ' MAX TYP eT. t i ' 90 100 | 0.008 -0.012 TYP (0.20 0.30) 0.125 TYP 0.055 0.090-0.110 | 0.015 0.021 (3.18) 0.435 0.535 (1.40) (2.29 2.79) (0.38 -0.53) MIN (11.05-13.59) MAX TYP TYP TYP TYP BOTH ENDS JME (REV J) 24-Pin Ceramic Dual-In-Line Package (D) Package Number J24E 1.194-1.214 [30.33-30.84] 0.202 24 [5.13] 13 eee ee eel pg 0-035-0.045 f [0.89-1.14] oD 0.337-0.347 [8.56-8.81] u LICICICOI LCI Ooo u 1 12 PIN NO. 1 IDENT 0.125 [3.18] 0.125-0.135 5 0.060 0.039 [3.18-3.43] TYP >| ja AX | ee 0.390-0.410 [1.52] [0.99] 0.065 [9.91-10.41] [1.65] 0.145-0.200 | t } 90-100 [3.68-5.08] | _ I 86-g4 0.380 9.020 ny} L_0.125-0.140 5, 4 Leb [9.65] "IN os [3.18-3.56] | | | |. 0.047-0.057 +0.040 0.050 yp | P11.19-1.45] ne 0.428 9015 [1.27] [10 37 11-22] 0.015+0.021 0,090-0.110 0.009-0.015 Oo" 0.38] [0.38-0.53] TYP [2.29-2.79] TYP [0.23-0.38] N24E (REY A) www fairchildsemi.comPhysical DimMeNnSiONS inches (millimeters) unless otherwise noted (Continued) +0,006 0.450 -0.000 +0.15 [11.43] -0.00 PIN #1 IDENT 4 1 26 0.02940.003 450 x 0-045 Typ [0.4340.10] S [0.7440.08] 1 _| _ [] 25 L] C] L] a L] [Jig 12) 9.050 | 2 TYP [1.27] | 9.300 typ _ [7.62] 0.165-0.180 [4.19-4.57] 0.490+0.005 TYP [12.4540.13] 0.41040.020 yyp [10.4140.51] an SEATING PLANE >| J 0-920 Win Tye [0.51] 0.10540.015 yyp [2.6740.38] [0.004 [0.10] V2BA (REV K} 28-Pin Plastic Leaded Chip Carrier (Q) Package Number V28A 1.14 [1.14] 9.01740.004 yp www fairchildsemi.com100304 Low Power Quint AND/NAND Gate Physical DimensiON$ inches (millimeters) unless otherwise noted (Continued) 0.360 0.370 MIN 0.360 0.007 <p259 YP > TYP mI 9250 TYP | o.ooa TYP (MOLDED BODY) PIN NO. 1 ar 24 19 4 18,0 0 TT 1 o TT 1 aq TY + | ao J dd a __ 13 a 7 12 0.018 | 0.075 MAX 0.050 o.oig YP 8 PLES < 9.035 0.050 +.0.005 >| - 0.085 max TYP ; lg 0.400 MAX TYP GLASS 24-Pin Quad Cerpak (F) Package Number W24B LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- 2. tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. wag (REV Dj A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 8 141-35-0 English Tel: +44 (0) 1 793-85-68-56 Italy Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Corporation Americas Customer Response Center Tal: 1-888-522-5372 www fairchildsemi.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, & Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.