Switching Characteristics
VCC ea
5.0V, TAea
25§C (See Section 1 for waveforms and load configurations)
CLe15 PF
Symbol Parameter RLe500XUnits
Min Max
tPLH Propagation Delay 75 ns
tPHL Anto a–g 50
tPLH Propagation Delay 90 ns
tPHL LE to a–g 70
Functional Description
The ’70 has active LOW outputs capable of sinking in ex-
cess of 25 mA which allows it to drive a wide variety of
7-segment incandescent displays directly. It may also be
used to drive common anode LED displays, multiplexed or
directly with the aid of suitable current limiting resistors. This
device accepts a 4-bit binary code and produces output
drive to the appropriate segments of the 7-segment display.
It has a hexadecimal decode format which produces numer-
ic codes ‘’0’’ through ‘‘9’’ and alpha codes ‘‘A’’ through ‘‘F’’
using upper and lower case fonts.
Latches on the four data inputs are controlled by an active
LOW latch enable LE. When the LE is LOW, the state of the
outputs is determined by the input data. When the LE goes
HIGH, the last data present at the inputs is stored in the
latches and the outputs remain stable. The LE pulse width
necessary to accept and store data is typically 30 ns which
allows data to be strobed into the ’70 at normal TTL speeds.
This feature means that data can be routed directly from
high speed counters and frequency dividers into the display
without slowing down the system clock or providing interme-
diate data storage.
The latch/decoder combination is a simple system which
drives incandescent displays with multiplexed data inputs
from MOS time clocks, DVMs, calculator chips, etc. Data
inputs are multiplexed while the displays are in static mode.
This lowers component and insertion costs since several
circuitsÐseven diodes per display, strobe drivers, a sepa-
rate display voltage source, and clock failure detect cir-
cuitsÐtraditionally found in incandescent multiplexed dis-
play systems are eliminated. It also allows low strobing rates
to be used without display flicker.
Another ’70 feature is the reduced loading on the data in-
puts when the Latch Enable is HIGH (only 10 mA typ). This
allows many ’70s to be driven from a MOS device in multi-
plex mode without the need for drivers on the data lines.
The ’70 also provides automatic blanking of the leading
and/or trailing-edge zeroes in a multidigit decimal number,
resulting in an easily readable decimal display conforming to
normal writing practice. In an 8-digit mixed integer fraction
decimal representation, using the automatic blanking capa-
bility, 0060.0300 would be displayed as 60.03. Leading-
edge zero suppression is obtained by connecting the Ripple
Blanking Output (RBO) of a decoder to the Ripple Blanking
Input (RBI of the next lower stage device. The most signifi-
cant decoder stage should have the RBI input grounded;
and since suppression of the least significant integer zero in
a number is not usually desired, the RBI input of this decod-
er stage should be left open. A similar procedure for the
fractional part of a display will provide automatic suppres-
sion of trailing-edge zeroes. The RBO terminal of the decod-
er can be OR-tied with a modulating signal via an isolating
buffer to achieve pulse duration intensity modulation. A suit-
able signal can be generated for this purpose by forming a
variable frequency multivibrator with a cross coupled pair of
TTL or DTL gates.
Logic Symbol
TL/F/9797–2
VCC ePin 16
GND ePin 8
3