Data Sheet Rev.1.3 23.11.2010 1GB DDR2 - SDRAM SO-DIMM Features: 200 Pin SO-DIMM SEN01G64D1BH1MT-25R 1GB PC2-6400 in FBGA Technology RoHS compliant Options: Data Rate / Latency DDR2 800 MT/s CL6 DDR2 667 MT/s CL5 DDR2 533 MT/s CL4 Module Density 1GB with 8 dies and 1 rank Standard Grade (TA) (TC) Grade E (TA) (TC) Grade W (TA) (TC) Marking -25 -30 -37 0C to 70C 0C to 85C 0C to 85C 0C to 95C -40C to 85C -40C to 95C * The refresh rate has to be doubled when 85C>TC>95C Environmental Requirements: Operating temperature (ambient) standard Grade 0C to 70C Grade E 0C to 85C Grade W -40C to 85C Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55C to 100C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50C 200-pin 64-bit Small Outline, Dual-In-Line Double Data Rate Synchronous DRAM Module Module organization: single rank 128M x 64 VDD = 1.8V 0.1V, VDDQ 1.8V 0.1V 1.8V I/O ( SSTL_18 compatible) Auto Refresh (CBR) and Self Refresh 8k Refresh every 64ms Serial Presence Detect with EEPROM Gold-contact pad This module is fully pin and functional compatible to the JEDEC PC2-6400 spec. and JEDEC- Standard MO-224. (see www.jedec.org) The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR2 - SDRAM component MICRON MT47H128M8CF-25 DIE-Revision H 128Mx8 DDR2 SDRAM in FBGA-60 package Four bit prefetch architecture DLL to align DQ and DQS transitions with CK Eight internal device banks for concurrent operation Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency - 1 tCK Programmable burst length: 4 or 8 Adjustable data-output drive strength On-die termination (ODT) Figure: mechanical dimensions 1 1 if no tolerances specified 0.15mm Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 1 of 14 Data Sheet Rev.1.3 23.11.2010 This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Dual-In-line Memory Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve highspeed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving "power-down" mode. All inputs and all full drive-strength outputs are SSTL_18 compatible. The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial 2 EEPROM using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the SO-DIMM manufacturer (swissbit) to identify the module type, the module's organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR2 SDRAMs used Row Addr. Device Bank Select Column Addr. Refresh Module Bank Select 128M x 64bit 8 x 128M x 8bit (1024Mbit) 14 BA0, BA1,BA2 10 8k S0# Module Dimensions in mm 67.60 (long) x 30 (high) x 3.80 [max] (thickness) Timing Parameters Part Number Module Density Transfer Rate Clock Cycle/Data bit rate Latency SEN01G64D1BH1MT-25[E/W]R SEN01G64D1BH1MT-30[E/W]R SEN01G64D1BH1MT-37[E/W]R 1024 MB 1024 MB 1024 MB 6.4 GB/s 5.3 GB/s 4.26 GB/s 2.5ns/800MT/s 3.0ns/667MT/s 3.75ns/533MT/s 6-6-6 5-5-5 4-4-4 Pin Name A0-9, A11 - A13 Address Inputs A10/AP Address Input / Autoprecharge Bit BA0 - BA2 Bank Address Inputs DQ0 - DQ63 Data Input / Output DM0-DM7 Input Data Mask DQS0 - DQS7 Data Strobe, positive line DQS0# - DQS7# Data Strobe, negative line (only used when differential data strobe mode is enabled) RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable CKE0 Clock Enable CK0 - CK1 Clock Inputs, positive line Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 2 of 14 Data Sheet Rev.1.3 CK0# - CK1# Clock Inputs, negative line S0# Chip Select VDD Supply Voltage (1.8V 0.1V) VREF Input / Output Reference VSS Ground VDDSPD Serial EEPROM Positive Power Supply SCL Serial Clock for Presence Detect SDA Serial Data Out for Presence Detect SA0 - SA1 Presence Detect Address Inputs ODT0 On-Die Termination NC No Connection 23.11.2010 Pin Configuration PIN # Front Side PIN # Back Side PIN # Front Side PIN # Back Side 1 VREF 2 VSS 101 A1 102 A0 3 VSS 4 DQ4 103 VDD 104 VDD 5 DQ0 6 DQ5 105 A10/AP 106 BA1 7 DQ1 8 VSS 107 BA0 108 RAS# 9 VSS 10 DM0 109 WE# 110 S0# 11 DQS0# 12 VSS 111 VDD 112 VDD 13 DQS0 14 DQ6 113 CAS# 114 ODT0 15 VSS 16 DQ7 115 NC (S1#) 116 A13 17 DQ2 18 VSS 117 VDD 118 VDD 19 DQ3 20 DQ12 119 NC (ODT1) 120 NC (S3) 21 VSS 22 DQ13 121 VSS 122 VSS 23 DQ8 24 VSS 123 DQ32 124 DQ36 25 DQ9 26 DM1 125 DQ33 126 DQ37 27 VSS 28 VSS 127 VSS 128 VSS 29 DQS1# 30 CK0 129 DQS4# 130 DM4 31 DQS1 32 CK0# 131 DQS4 132 VSS 33 VSS 34 VSS 133 VSS 134 DQ38 35 DQ10 36 DQ14 135 DQ34 136 DQ39 37 DQ11 38 DQ15 137 DQ35 138 VSS 39 VSS 40 VSS 139 VSS 140 DQ44 41 VSS 42 VSS 141 DQ40 142 DQ45 43 DQ16 44 DQ20 143 DQ41 144 VSS 45 DQ17 46 DQ21 145 VSS 146 DQS5# 47 VSS 48 VSS 147 DM5 148 DQS5 49 DQS2# 50 NC (EVENT#) 149 VSS 150 VSS 51 DQS2 52 DM2 151 DQ42 152 DQ46 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 3 of 14 Data Sheet PIN # Front Side PIN # Back Side PIN # Rev.1.3 Front Side PIN # 23.11.2010 Back Side 53 VSS 54 VSS 153 DQ43 154 DQ47 55 DQ18 56 DQ22 155 VSS 156 VSS 57 DQ19 58 DQ23 157 DQ48 158 DQ52 59 VSS 60 VSS 159 DQ49 160 DQ53 61 DQ24 62 DQ28 161 VSS 162 VSS 63 DQ25 64 DQ29 163 NC (TEST) 164 CK1 65 VSS 66 VSS 165 VSS 166 CK1# 67 DM3 68 DQS3# 167 DQS6# 168 VSS 69 NC (RESET#) 70 DQS3 169 DQS6 170 DM6 71 VSS 72 VSS 171 VSS 172 VSS 73 DQ26 74 DQ30 173 DQ50 174 DQ54 75 DQ27 76 DQ31 175 DQ51 176 DQ55 77 VSS 78 VSS 177 VSS 178 VSS 79 CKE0 80 NC (CKE1) 179 DQ56 180 DQ60 81 VDD 82 VDD 181 DQ57 182 DQ61 83 NC (S2#) 84 NC (A15) 183 VSS 184 VSS 85 BA2 86 NC (A14) 185 DM7 186 DQS7# 87 VDD 88 VDD 187 VSS 188 DQS7 89 A12 90 A11 189 DQ58 190 VSS 91 A9 92 A7 191 DQ59 192 DQ62 93 A8 94 A6 193 VSS 194 DQ63 95 VDD 96 VDD 195 SDA 196 VSS 97 A5 98 A4 197 SCL 198 SA0 99 A3 100 A2 199 VDDSPD 200 SA1 (Sig): Signal in brackets may be routed to the socket connector, but is not used on the module Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 4 of 14 Data Sheet Rev.1.3 23.11.2010 FUNCTIONAL BLOCK DIAGRAMM 1GB DDR2 SDRAM SODIMM, 1 RANK AND 8 COMPONENTS CKE0 ODT0 S0 CS ODT CKE DQS0 DQS DQS DM DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS ODT CKE DQS4 DQS DQS DM DQS4 DM4 D0 I/O 0 I/O 1 I/O 2 DQ32 DQ33 DQ34 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS ODT CKE DQS1 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DQS DM I/O 0 I/O 1 CS ODT CKE DQS5 DQS5 DM5 D1 DQS DQS DM I/O 0 I/O 1 I/O 2 DQ40 DQ41 DQ42 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ43 DQ44 DQ45 DQ46 DQ47 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS ODT CKE DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DQS DM I/O 0 I/O 1 DQS6 DM6 DQS DQS DM I/O 0 I/O 1 I/O 2 DQ48 DQ49 DQ50 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS ODT CKE DQS3 DQS DQS DM DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA2 A0-A13 RAS CAS WE Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen DQS DQS DM DQS7 DM7 I/O 0 I/O 1 I/O 2 DQ56 DQ57 DQ58 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 BA0-BA2: SDRAM D0-D7 A0-A13: SDRAM D0-D7 RAS: SDRAM D0-D7 CAS: SDRAM D0-D7 WE: SDRAM D0-D7 D6 CS ODT CKE DQS7 D3 D5 CS ODT CKE DQS6 D2 D4 I/O 0 I/O 1 VDDSPD Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 D7 I/O 0 I/O 1 SPD VREF D0-D7 VDD D0-D7 VSS D0-D7/SPD www.swissbit.com eMail: info@swissbit.com Page 5 of 14 Data Sheet Rev.1.3 23.11.2010 MAXIMUM ELECTRICAL DC CHARACTERISTICS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage Voltage on any pin relative to VSS INPUT LEAKAGE CURRENT SYMBOL VDD VDDQ VDDL Vin, Vout Any input 0V VIN VDD, VREF pin 0V VIN 0.95V (All other pins not under test = 0V) MIN -1.0 -0.5 -0.5 -0.5 MAX 2.3 2.3 2.3 2.3 II UNITS V V V V A Command/Address -40 40 IOZ -20 -5 -5 20 5 5 A IVREF -16 16 A NOM 1.8 1.8 1.8 0.50 x VDDQ VREF MAX 1.9 1.9 1.9 0.51x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.125 UNITS V V V V V V V MIN VREF + 0.25 - MAX VREF - 0.25 UNITS V V RAS#, CAS#, WE#, S#, CKE CK, CK# DM OUTPUT LEAKAGE CURRENT (DQ's and ODT are disabled; 0V VOUT VDDQ) DQ, DQS, DQS# VREF LEAKAGE CURRENT ; VREF is on a valid level DC OPERATING CONDITIONS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VDD VDDQ VDDL VREF VTT VIH (DC) VIL (DC) MIN 1.7 1.7 1.7 0.49 x VDDQ VREF - 0.04 VREF + 0.125 -0.3 AC INPUT OPERATING CONDITIONS PARAMETER/ CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH (AC) VIL (AC) CAPACITANCE At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 6 of 14 Data Sheet Rev.1.3 23.11.2010 IDD Specifications and Conditions (0C TCASE + 85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V) Parameter & Test Condition OPERATING CURRENT *) : One device bank Active-Precharge; tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH between valid commands; DQ inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT *) : One device bank; Active-Read-Precharge; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address inputs changing once every two clock cycles; Data Pattern is same as IDD4W PRECHARGE POWER-DOWN CURRENT: All device banks idle; Power-down mode; tCK = tCK (IDD); CKE is LOW; All Control and Address bus inputs are not changing; DQ's are floating at VREF PRECHARGE QUIET STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All Control and Address bus inputs are not changing; DQ's are floating at VREF PRECHARGE STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Fast PDN Exit ACTIVE POWER-DOWN MR[12] = 0 CURRENT: All device banks open; tCK = tCK (IDD); Slow PDN Exit CKE is LOW; All Control and MR[12] = 1 Address bus inputs are not changing; DQ's are floating at VREF ACTIVE STANDBY CURRENT: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Symbol max. 6400-666 5300-555 4200-444 Unit IDD0 720 680 560 mA IDD1 880 800 760 mA IDD2P 56 56 56 mA IDD2Q 400 320 320 mA IDD2N 400 320 320 mA IDD3P 320 240 240 mA 80 80 80 mA 480 440 360 mA IDD3N Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 7 of 14 Data Sheet Parameter & Test Condition OPERATING READ CURRENT: All device banks open, Continuous burst reads; One module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle SELF REFRESH CURRENT: CK and CK# at 0V; CKE 0.2V; All other Control and Address bus inputs are floating at VREF; DQ's are floating at VREF OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle Symbol Rev.1.3 max. 6400-666 5300-555 4200-444 23.11.2010 Unit IDD4R 1280 1080 1000 mA IDD4W 1280 1080 1000 mA IDD5 1880 1720 1680 mA IDD6 56 56 56 mA IDD7 2680 2240 2160 mA TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 6400-666 5300-555 CL (IDD) tRCD (IDD) tRC (IDD) tRRD (IDD) tCK (IDD) tRAS MIN (IDD) tRAS MAX (IDD) tRP (IDD) tRFC (IDD) 6 15 60 7.5 2.5 45 70'000 15 127.5 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen 5 15 60 7.5 3.0 45 70'000 15 127.5 4200-444 Unit 4 15 60 7.5 3.75 45 70'000 15 127.5 tCK ns ns ns ns ns ns ns ns Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 8 of 14 Data Sheet Rev.1.3 23.11.2010 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0C TCASE + 85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V) AC CHARACTERISTICS PARAMETER Clock cycle time CL = 6 CL = 5 CL = 4 CL = 3 CK high-level width CK low-level width Half clock period SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP 6400-666 MIN MAX 2.5 8.0 3.08.03.75 8.0 0.48 0.52 0.48 0.52 min (tCH, tCL) -0.40 +0.40 5300-555 MIN MAX + 3.0 8.0 3.75 8.0 5.0 8.0 0.45 0.55 0.45 0.55 min (tCH, tCL) -0.45 +0.45 4200-444 MIN MAX 3.75 8.0 5.0 8.0 0.45 0.55 0.45 0.55 min (tCH, tCL) -0.50 +0.50 +0.45 +0.50 (= tAC max) (= tAC max) Unit ns ns ns ns tCK tCK ps Access window (output) of DQS from CK/CK# Data-out high-impedance window from CK/CK# tAC Data-out low-impedance window from CK/CK# tLZ DQ and DM input setup time relative to DQS tDS 0.05 0.10 0.10 ns DQ and DM input hold time relative to DQS DQ and DM input pulse width ( for each input ) Data hold skew factor DQ-DQS hold, DQS to first DQ to go non-valid, per access Data valid output window tDH 0.125 0.30 0.35 ns tDIPW 0.35 0.35 0.35 tCK tQHS tQH tHP - tQHS tHP - tQHS tHP - tQHS tDVW tQH tDQSQ tQH tDQSQ tQH tDQSQ ns DQS input high pulse width DQS input low pulse width DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time DQS -DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble DQS write preamble setup time DQS write postamble Positive DQS latching edge to associated clock edge Write command to first DQS latching transition Address and control input pulse width ( for each input ) Address and control input setup time tDQSH tDQSL tDSS 0.35 0.35 0.2 0.35 0.35 0.2 0.35 0.35 0.2 tCK tCK tCK tDSH 0.2 0.2 0.2 tCK Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen tHZ tAC max tAC min tAC max +0.45 -0.50 +0.50 (= tAC max) (= tAC min) (= tAC max) 0.34 0.3 0.2 tDQSQ tRPRE tRPST tWPRE tWPRES tWPST tDQSS 0.9 0.4 0.35 0 0.4 1.1 0.6 - 0.25 + 0.25 WL+ tDQSS tIPW WLtDQSS 0.6 tISa 0.175 - -0.45 (= tAC min) 0.6 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 0.4 0.24 0.9 0.4 0.35 0 0.4 - 0.25 WLtDQSS 0.6 0.4 1.1 0.6 0.6 + 0.25 WL+ tDQSS 0.9 0.4 0.25 0 0.4 - 0.25 WLtDQSS 0.6 ns ns ns ns ns 0.30 ns 1.1 0.6 tCK tCK tCK ns tCK tCK 0.6 + 0.25 WL+ tDQSS 0.5 www.swissbit.com eMail: info@swissbit.com tCK tCK ns Page 9 of 14 Data Sheet Rev.1.3 23.11.2010 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0C TCASE + 85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V) AC CHARACTERISTICS PARAMETER Address and control input hold time CAS# to CAS# command delay ACTIVE to ACTIVE (same bank) command period ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK, CK# uncertainty REFRESH to ACTIVE or REFRESH to REFRESH command interval Average periodic refresh interval (0C<= TCASE <= 85 C) (85C<= TCASE <= 95 C) Exit SELF REFRESH to nonREAD command Exit SELF REFRESH to READ command Exit SELF REFRESH timing reference ODT turn-on delay ODT turn-on 6400-666 SYMBOL Min Max 0.25 tIH 5300-555 MIN MAX 0.4 4200-444 MIN MAX 0.5 Unit ns tCCD tRC 2 60 2 60 2 60 tCK ns tRRD 7.5 7.5 7.5 ns tRCD 15 15 15 ns tFAW tRAS 37.5 45 tRTP 7.5 7.5 7.5 ns tWR tDAL 15 tWR + tRP 15 tWR + tRP 15 tWR + tRP ns ns tWTR 7.5 7.5 7.5 ns tRP tRPA 15 tRP + tCK 15 tRP + tCK 15 tRP + tCK ns ns tMRD 2 2 2 tCK tDELAY tIS + tCK + tIH tIS + tCK + tIH tIS + tCK + tIH tCK 127.5 tRFC 70,000 70,000 tREFI 7.8 tREFI (IT) tRFC(min) tXSNR 3.9 + 10 37.5 45 127.5 70,000 70,000 37.5 45 127.5 70,000 70,000 ns 7.8 s 3.9 s ns 7.8 3.9 tRFC(min) + 10 tRFC(min) + 10 ns ns tXSRD 200 200 200 tCK tISXR tIS tIS tIS ps tAOND tAON 2 2 2 2 2 2 tAC(min) tAC(max) + 1,000 tAC(min) tAC(max) + 1,000 tAC(min) tAC(max) + 1,000 ODT turn-off delay ODT turn-off tAOFD tAOF 2.5 2.5 2.5 2.5 2.5 2.5 tAC(min) tAC(min) tAONPD tAC(min) + 2,000 ODT turn-off (power-down mode) tAOFPD tAC(min) + 2,000 tAC(max) + 600 2 x tCK + tAC(max) + 1,000 2.5 x tCK + tAC(max) + 1,000 tAC(min) ODT turn-on (power-down mode) tAC(max) + 600 2 x tCK + tAC(max) + 1,000 2.5 x tCK + tAC(max) + 1,000 tAC(max) + 600 2 x tCK + tAC(max) + 1,000 2.5 x tCK + tAC(max) + 1,000 ODT to power-down entry latency tANPD 3 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 tAC(min) + 2,000 tAC(min) + 2,000 3 tAC(min) + 2,000 tAC(min) + 2,000 3 www.swissbit.com eMail: info@swissbit.com tCK ps tCK ps ps ps tCK Page 10 of 14 Data Sheet Rev.1.3 23.11.2010 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0C TCASE + 85C; VDDQ = +1.8V 0.1V, VDD = +1.8V 0.1V) AC CHARACTERISTICS PARAMETER ODT power-down exit latency ODT enable from MRS command Exit active power-down to READ command, MR [bit 12 = 0] Exit active power-down to READ command, MR [bit 12 = 1] Exit precharge power-down to any non-READ command CKE minimum high/low time Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen SYMBOL tAXPD 6400-666 Min Max 8 5300-555 MIN MAX 8 4200-444 MIN MAX 8 Unit tCK tMOD 12 12 12 ns tXARD 2 2 2 tCK tXARDS 8 - AL 7 - AL 6 - AL tCK tXP 2 2 2 tCK tCKE 3 3 3 tCK Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 11 of 14 Data Sheet Rev.1.3 23.11.2010 SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION 6400-666 5300-555 0 NUMBER OF SPD BYTES USED 0x80 1 TOTAL NUMBER OF BYTES IN SPD DEVICE 0x08 2 3 0x08 0x0E 5 FUNDAMENTAL MEMORY TYPE NUMBER OF ROW ADDRESSES ON ASSEMBLY NUMBER OF COLUMN ADDRESSES ON ASSEMBLY DIMM HIGHT AND MODULE RANKS 6 7 MODULE DATA WIDTH MODULE DATA WIDTH (continued) 0x40 0x00 8 MODULE VOLTAGE INTERFACE LEVELS (VDDQ) SDRAM CYCLE TIME, (tCK ) [max CL] CL = 6 (6400), CL = 5 (5300), CL = 4 (4200) 0x05 4 9 0x0A 0x60 0x25 0x30 0x3D 0x40 0x45 0x50 10 SDRAM ACCESS FROM CLOCK, (tAC) [max CL] CL = 6 (6400), CL = 5 (5300), CL = 4 (4200) 11 12 MODULE CONFIGURATION TYPE REFRESH RATE / TYPE 0x00 0x82 13 14 SDRAM DEVICE WIDTH (PRIMARY SDRAM) ERROR- CHECKING SDRAM DATA WIDTH 0x08 0x00 16 MINIMUM CLOCK DELAY, BACK-TO-BACK RANDOM COLUMN ACCESS BURST LENGTHS SUPPORTED 17 18 NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED 19 20 MODULE THICKNESS DDR2 DIMM TYPE 0x01 0x04 21 SDRAM MODULE ATTRIBUTES 0x00 22 SDRAM DEVICE ATTRIBUTES: Weak Driver and 50 ODT 23 SDRAM CYCLE TIME, (tCK) [max CL - 1] CL = 5 (6400), CL = 4 (5300), CL = 3 (4200) 15 24 25 SDRAM ACCESS FROM CK, (tAC) [max CL - 1] CL = 5 (6400), CL = 4 (5300), CL = 3 (4200) SDRAM CYCLE TIME, (tCK) [max CL - 2] CL = 4 (6400), CL = 3 (5300) 0x00 0x0C 0x08 0x38 0x70 0x03 0x30 0x3D 0x50 0x40 0x45 0x50 0x3D 0x50 0x00 0x40 0x45 0x00 SDRAM ACCESS FROM CK, (tAC) [max CL - 2] CL = 4 (6400), CL = 3 (5300) 27 28 MINIMUM ROW PRECHARGE TIME, (tRP) MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD) 0x3C 0x1E 29 30 MINIMUM RAS# TO CAS# DELAY, (tRCD) MINIMUM RAS# PULSE WIDTH, (tRAS) 0x3C 0x2D 31 MODULE BANK DENSITY 0x01 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 0x18 0x01 26 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen 4200-444 www.swissbit.com eMail: info@swissbit.com Page 12 of 14 Data Sheet Rev.1.3 23.11.2010 SERIAL PRESENCE-DTECT MATRIX (continued) BYTE 6400-666 5300-555 4200-444 32 ADDRESS AND COMMAND SETUP TIME, (tISb) 0x17 0x20 0x25 33 ADDRESS AND COMMAND HOLD TIME, (tIHb) 0x25 0x27 34 DATA / DATA MASK INPUT SETUP TIME, (tDSb) 0x05 35 DATA / DATA MASK INPUT HOLD TIME, (tDHb) 0x12 36 WRITE RECOVERY TIME, (tWR) 0x3C 37 38 WRITE to READ Command Delay, (tWTR) READ to PRECHARGE Command Delay, (tRTP) 0x1E 0x1E 39 Mem Analysis Probe 0x00 40 Extension for Bytes 41 and 42 0x06 41 MIN ACTIVE AUTO REFRESH TIME, (tRC) MINIMUM AUTO REFRESH TO ACTIVE / AUTO REFRESH COMMAND PERIOD, (tRFC) SDRAM DEVICE MAX CYCLE TIME, (tCKMAX) SDRAM DEVICE MAX DQS-DQ SKEW TIME, (tDQSQ) SDRAM DEVICE MAX READ DATA HOLD SKEW FACTOR, (tQHS) PLL Relock Time 0x3C 42 43 44 45 46 47-61 DESCRIPTION SPD REVISION 63 CHECKSUM FOR BYTES 0-62 64-66 67 0x17 0x22 0x7F 0x80 0x14 0x18 0x1E 0x1E 0x22 0x28 0x00 Optional Features, not supported 62 0x37 0x10 0x00 0x13 0xCA 0xEF MANUFACTURERS JEDEC ID CODE 0x7F MANUFACTURERS JEDEC ID CODE (continued) 0xDA 68-71 72 RESERVED MANUFACTURING LOCATION 73-90 MODULE PART NUMBER (ASCII) 0x9A 0x00 0x01 (Switzerland) | 0x02 (Germany) | 0x03 (USA) "SEN01G64D1BH1MT-xx" 91 PCB IDENTIFICATION CODE x 92 IDENTIFICATION CODE (continued) x 93 YEAR OF MANUFACTURE IN BCD x 94 WEEK OF MANUFACTURE IN BCD x 95-98 MODULE SERIAL NUMBER 99-127 MANUFACTURER-SPECIFIC DATA (RSVD) x 0x00 128-255 Open for customer use 0xff Part Number Code S E N 01G 64 D1 B H 1 MT 1 2 3 4 5 6 7 8 9 10 - 25 * R 11 12 13 *RoHs compl. DDR2-800MT/s Swissbit AG SDRAM DDR2 200 Pin Unbuffered 1.8V Depth (1GB) Width PCB-Type (8231a) Chip Vendor (MICRON) 1 Module Rank Chip Rev. H Chip organisation x8 * optional / additional information Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 13 of 14 Data Sheet Rev.1.3 23.11.2010 Locations Swissbit AG Industriestrasse 4 - 8 CH - 9552 Bronschhofen Switzerland Phone: +41 (0)71 913 03 03 Fax: +41 (0)71 913 03 15 _____________________________ Swissbit Germany GmbH Wolfener Strasse 36 D - 12681 Berlin Germany Phone: +49 (0)30 93 69 54 - 0 Fax: +49 (0)30 93 69 54 - 55 _____________________________ Swissbit NA, Inc. 14 Willett Avenue, Suite 301A Port Chester, NY 10573 USA Phone: +1 914 935 1400 Fax: +1 914 935 9865 _____________________________ Swissbit NA, Inc. 3913 Todd Lane, Suite - 307 Austin, TX 78744 USA Phone: +1 512 302 9001 Fax: +1 512 302 4808 _____________________________ Swissbit Japan, Inc. 3F Core Koenji, 2-1-24 Koenji-Kita, Suginami-Ku, Tokyo 166-0002 Japan Phone: +81 3 5356 3511 Fax: +81 3 5356 3512 Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 14 of 14 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Swissbit: SEN01G64D1BH1MT-25WR