SEN01G64D1BH1MT-25WR - Swissbit

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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Figure: mechanical dimensions1

1GB DDR2 – SDRAM SO-DIMM

200 Pin SO-DIMM

SEN01G64D1BH1MT-25R

1GB PC2-6400 in FBGA Technology

RoHS compliant

* The refresh rate has to be doubled when 85°C>TC>95°C

Environmental Requirements:

 Operating temperature (ambient)

standard Grade 0°C to 70°C

Grade E 0°C to 85°C

Grade W -40°C to 85°C

 Operating Humidity

10% to 90% relative humidity, noncondensing

 Operating Pressure

105 to 69 kPa (up to 10000 ft.)

 Storage Temperature

-55°C to 100°C

 Storage Humidity

5% to 95% relative humidity, noncondensing

 Storage Pressure

1682 PSI (up to 5000 ft.) at 50°C

Options:

 Data Rate / Latency Marking

DDR2 800 MT/s CL6 -25

DDR2 667 MT/s CL5 -30

DDR2 533 MT/s CL4 -37

 Module Density

1GB with 8 dies and 1 rank

 Standard Grade (TA) 0°C to 70°C

(TC) 0°C to 85°C

Grade E (TA) 0°C to 85°C

(TC) 0°C to 95°C

Grade W (TA) -40°C to 85°C

(TC) -40°C to 95°C

Features:

 200-pin 64-bit Small Outline, Dual-In-Line Double

Data Rate Synchronous DRAM Module

 Module organization: single rank 128M x 64

 VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V

 1.8V I/O ( SSTL_18 compatible)

 Auto Refresh (CBR) and Self Refresh 8k Refresh

every 64ms

 Serial Presence Detect with EEPROM

 Gold-contact pad

 This module is fully pin and functional compatible to

the JEDEC PC2-6400 spec. and JEDEC- Standard

MO-224. (see www.jedec.org)

 The pcb and all components are manufactured

according to the RoHS compliance specification

[EU Directive 2002/95/EC Restriction of Hazardous

Substances (RoHS)]

 DDR2 - SDRAM component MICRON

MT47H128M8CF-25 DIE-Revision H

 128Mx8 DDR2 SDRAM in FBGA-60 package

 Four bit prefetch architecture

 DLL to align DQ and DQS transitions with CK

 Eight internal device banks for concurrent operation

 Programmable CAS latency (CL)

 Posted CAS additive latency (AL)

 WRITE latency = READ latency – 1 tCK

 Programmable burst length: 4 or 8

 Adjustable data-output drive strength

 On-die termination (ODT)

1if no tolerances specified ± 0.15mm

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Dual-In-line Memory

Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally

configured octal-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve high-

speed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE

accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a

programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An

auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst

access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is

providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All

inputs and all full drive-strength outputs are SSTL_18 compatible.

The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial

EEPROM using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes

are utilized by the SO-DIMM manufacturer (swissbit) to identify the module type, the module’s organization and

several timing parameters. The second 128 bytes are available to the end user.

Module Configuration

Organization

DDR2 SDRAMs used

Row

Addr.

Device Bank

Select

Column

Addr.

Refresh

Module

Bank Select

128M x 64bit

8 x 128M x 8bit (1024Mbit)

14

BA0, BA1,BA2

10

8k

S0#

Module Dimensions

in mm

67.60 (long) x 30 (high) x 3.80 [max] (thickness)

Timing Parameters

Part Number

Module Density

Transfer Rate

Clock Cycle/Data bit rate

Latency

SEN01G64D1BH1MT-25[E/W]R

1024 MB

6.4 GB/s

2.5ns/800MT/s

6-6-6

SEN01G64D1BH1MT-30[E/W]R

1024 MB

5.3 GB/s

3.0ns/667MT/s

5-5-5

SEN01G64D1BH1MT-37[E/W]R

1024 MB

4.26 GB/s

3.75ns/533MT/s

4-4-4

Pin Name

A0-9, A11 – A13

Address Inputs

A10/AP

Address Input / Autoprecharge Bit

BA0 – BA2

Bank Address Inputs

DQ0 – DQ63

Data Input / Output

DM0-DM7

Input Data Mask

DQS0 - DQS7

Data Strobe, positive line

DQS0# - DQS7#

Data Strobe, negative line (only used when differential data strobe mode is enabled)

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

CKE0

Clock Enable

CK0 – CK1

Clock Inputs, positive line

Figure 1: Mechanical Dimensions

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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CK0# - CK1#

Clock Inputs, negative line

S0#

Chip Select

VDD

Supply Voltage (1.8V± 0.1V)

VREF

Input / Output Reference

VSS

Ground

VDDSPD

Serial EEPROM Positive Power Supply

SCL

Serial Clock for Presence Detect

SDA

Serial Data Out for Presence Detect

SA0 – SA1

Presence Detect Address Inputs

ODT0

On-Die Termination

NC

No Connection

Pin Configuration

PIN #

Front Side

PIN #

Back Side

PIN #

Front Side

PIN #

Back Side

1

VREF

2

VSS

101

A1

102

A0

3

VSS

4

DQ4

103

VDD

104

VDD

5

DQ0

6

DQ5

105

A10/AP

106

BA1

7

DQ1

8

VSS

107

BA0

108

RAS#

9

VSS

10

DM0

109

WE#

110

S0#

11

DQS0#

12

VSS

111

VDD

112

VDD

13

DQS0

14

DQ6

113

CAS#

114

ODT0

15

VSS

16

DQ7

115

NC (S1#)

116

A13

17

DQ2

18

VSS

117

VDD

118

VDD

19

DQ3

20

DQ12

119

NC (ODT1)

120

NC (S3)

21

VSS

22

DQ13

121

VSS

122

VSS

23

DQ8

24

VSS

123

DQ32

124

DQ36

25

DQ9

26

DM1

125

DQ33

126

DQ37

27

VSS

28

VSS

127

VSS

128

VSS

29

DQS1#

30

CK0

129

DQS4#

130

DM4

31

DQS1

32

CK0#

131

DQS4

132

VSS

33

VSS

34

VSS

133

VSS

134

DQ38

35

DQ10

36

DQ14

135

DQ34

136

DQ39

37

DQ11

38

DQ15

137

DQ35

138

VSS

39

VSS

40

VSS

139

VSS

140

DQ44

41

VSS

42

VSS

141

DQ40

142

DQ45

43

DQ16

44

DQ20

143

DQ41

144

VSS

45

DQ17

46

DQ21

145

VSS

146

DQS5#

47

VSS

48

VSS

147

DM5

148

DQS5

49

DQS2#

50

NC (EVENT#)

149

VSS

150

VSS

51

DQS2

52

DM2

151

DQ42

152

DQ46

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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PIN #

Front Side

PIN #

Back Side

PIN #

Front Side

PIN #

Back Side

53

VSS

54

VSS

153

DQ43

154

DQ47

55

DQ18

56

DQ22

155

VSS

156

VSS

57

DQ19

58

DQ23

157

DQ48

158

DQ52

59

VSS

60

VSS

159

DQ49

160

DQ53

61

DQ24

62

DQ28

161

VSS

162

VSS

63

DQ25

64

DQ29

163

NC (TEST)

164

CK1

65

VSS

66

VSS

165

VSS

166

CK1#

67

DM3

68

DQS3#

167

DQS6#

168

VSS

69

NC (RESET#)

70

DQS3

169

DQS6

170

DM6

71

VSS

72

VSS

171

VSS

172

VSS

73

DQ26

74

DQ30

173

DQ50

174

DQ54

75

DQ27

76

DQ31

175

DQ51

176

DQ55

77

VSS

78

VSS

177

VSS

178

VSS

79

CKE0

80

NC (CKE1)

179

DQ56

180

DQ60

81

VDD

82

VDD

181

DQ57

182

DQ61

83

NC (S2#)

84

NC (A15)

183

VSS

184

VSS

85

BA2

86

NC (A14)

185

DM7

186

DQS7#

87

VDD

88

VDD

187

VSS

188

DQS7

89

A12

90

A11

189

DQ58

190

VSS

91

A9

92

A7

191

DQ59

192

DQ62

93

A8

94

A6

193

VSS

194

DQ63

95

VDD

96

VDD

195

SDA

196

VSS

97

A5

98

A4

197

SCL

198

SA0

99

A3

100

A2

199

VDDSPD

200

SA1

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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FUNCTIONAL BLOCK DIAGRAMM 1GB DDR2 SDRAM SODIMM,

1 RANK AND 8 COMPONENTS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

D0

DQS

CS

DQ0

DQ1

DQ2

DQ3

DQ5

DQ4

DQ6

DQ7

S0

ODT0

DQS0

DM0

DQS0

CKE0

ODT CKE

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

D4

DQS

CS

DQ32

DQ33

DQ34

DQ35

DQ37

DQ36

DQ38

DQ39

DQS4

DM4

DQS4

ODT CKE

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

D1

DQS

CS

DQ8

DQ9

DQ10

DQ11

DQ13

DQ12

DQ14

DQ15

DQS1

DM1

ODT CKE

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

D5

DQS

CS

DQ40

DQ41

DQ42

DQ43

DQ45

DQ44

DQ46

DQ47

DQS5

DM5

DQS5

ODT CKE

DQS1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

D2

DQS

CS

DQ16

DQ17

DQ18

DQ19

DQ21

DQ20

DQ22

DQ23

DQS2

DM2

ODT CKE

DQS2

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

D3

DQS

CS

DQ24

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

DQS3

DM3

ODT CKE

DQS3

BA0-BA2: SDRAM D0-D7

A0-A13: SDRAM D0-D7

RAS: SDRAM D0-D7

CAS: SDRAM D0-D7

WE: SDRAM D0-D7

BA0-BA2

A0-A13

RAS

CAS

WE

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

D6

DQS

CS

DQ48

DQ49

DQ50

DQ51

DQ53

DQ52

DQ54

DQ55

ODT CKE

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM

DQS

D7

DQS

CS

DQ56

DQ57

DQ58

DQ59

DQ61

DQ60

DQ62

DQ63

ODT CKE

DQS6

DM6

DQS6

DQS7

DM7

DQS7

VDDSPD SPD

VREF D0-D7

VDD D0-D7

D0-D7/SPD

VSS

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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MAXIMUM ELECTRICAL DC CHARACTERISTICS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Supply Voltage

VDD

-1.0

2.3

V

I/O Supply Voltage

VDDQ

-0.5

2.3

V

VDDL Supply Voltage

VDDL

-0.5

2.3

V

Voltage on any pin relative to VSS

Vin, Vout

-0.5

2.3

V

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V

(All other pins not under test = 0V)

II

µA

Command/Address

RAS#, CAS#, WE#, S#, CKE

-40

40

CK, CK#

-20

20

DM

-5

5

OUTPUT LEAKAGE CURRENT

(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

-5

5

µA

DQ, DQS, DQS#

VREF LEAKAGE CURRENT ; VREF is on a valid level

IVREF

-16

16

µA

DC OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

NOM

MAX

UNITS

Supply Voltage

VDD

1.7

1.8

1.9

V

I/O Supply Voltage

VDDQ

1.7

1.8

1.9

V

VDDL Supply Voltage

VDDL

1.7

1.8

1.9

V

I/O Reference Voltage

VREF

0.49 x VDDQ

0.50 x VDDQ

0.51x VDDQ

V

I/O Termination Voltage (system)

VTT

VREF – 0.04

VREF

VREF + 0.04

V

Input High (Logic 1) Voltage

VIH (DC)

VREF + 0.125

VDDQ + 0.3

V

Input Low (Logic 0) Voltage

VIL (DC)

-0.3

VREF – 0.125

V

AC INPUT OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Input High (Logic 1) Voltage

VIH (AC)

VREF + 0.25

-

V

Input Low (Logic 0) Voltage

VIL (AC)

-

VREF - 0.25

V

CAPACITANCE

At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values.

When inductance and delay parameters associated with trace lengths are used in simulations, they are

significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then

render a considerably more accurate result. JEDEC modules are now designed by using simulations to close

timing budgets.

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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IDD Specifications and Conditions

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)

Parameter

& Test Condition

Symbol

max.

Unit

6400-666

5300-555

4200-444

OPERATING CURRENT *) :

One device bank Active-Precharge;

tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is

HIGH between valid commands;

DQ inputs changing once per clock cycle; Address

and control inputs changing once every two clock

cycles

IDD0

720

680

560

mA

OPERATING CURRENT *) :

One device bank; Active-Read-Precharge;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address inputs

changing once every two clock cycles; Data

Pattern is same as IDD4W

IDD1

880

800

760

mA

PRECHARGE POWER-DOWN CURRENT:

All device banks idle; Power-down mode;

tCK = tCK (IDD); CKE is LOW; All Control and

Address bus inputs are not changing; DQ’s are

floating at VREF

IDD2P

56

mA

PRECHARGE QUIET STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All Control and Address bus inputs are not

changing; DQ’s are floating at VREF

IDD2Q

400

320

mA

PRECHARGE STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All other Control and Address bus inputs are

changing once every two clock cycles; DQ inputs

changing once per clock cycle

IDD2N

400

320

mA

ACTIVE POWER-DOWN

CURRENT:

All device banks open; tCK = tCK (IDD);

CKE is LOW; All Control and

Address bus inputs are not

changing; DQ’s are floating at VREF

Fast PDN Exit

MR[12] = 0

IDD3P

320

240

mA

Slow PDN Exit

MR[12] = 1

80

mA

ACTIVE STANDBY CURRENT:

All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid

commands;

All other Control and Address bus inputs are

changing once every two clock cycles; DQ inputs

changing once per clock cycle

IDD3N

480

440

360

mA

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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Parameter

& Test Condition

Symbol

max.

Unit

6400-666

5300-555

4200-444

OPERATING READ CURRENT:

All device banks open, Continuous burst reads;

One module rank active; IOUT = 0mA; BL = 4, CL =

CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX

(IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are

changing once every two clock cycles; DQ inputs

changing once per clock cycle

IDD4R

1280

1080

1000

mA

OPERATING WRITE CURRENT:

All device banks open, Continuous burst writes;

One module rank active; BL = 4, CL = CL (IDD), AL

= 0;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are changing once

every two clock cycles; DQ inputs changing once

per clock cycle

IDD4W

1280

1080

1000

mA

BURST REFRESH CURRENT:

tCK = tCK (IDD); refresh command at every tRFC (IDD)

interval, CKE is HIGH, CS# is HIGH between valid

commands; All other Control and Address bus

inputs are changing once every two clock cycles;

DQ inputs changing once per clock cycle

IDD5

1880

1720

1680

mA

SELF REFRESH CURRENT:

CK and CK# at 0V; CKE ≤ 0.2V; All other Control

and Address bus inputs are floating at VREF; DQ’s

are floating at VREF

IDD6

56

mA

OPERATING CURRENT*) :

Four device bank interleaving READs, IOUT = 0mA; BL

= 4, CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK

= tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD =

tRCD (IDD);

CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are not changing

during DESELECT; DQ inputs changing once per

clock cycle

IDD7

2680

2240

2160

mA

TIMING VALUES USED FOR IDD MEASUREMENT

IDD MEASUREMENT CONDITIONS

SYMBOL

6400-666

5300-555

4200-444

Unit

CL (IDD)

6

5

4

tCK

tRCD (IDD)

15

ns

tRC (IDD)

60

ns

tRRD (IDD)

7.5

ns

tCK (IDD)

2.5

3.0

3.75

ns

tRAS MIN (IDD)

45

ns

tRAS MAX (IDD)

70’000

ns

tRP (IDD)

15

ns

tRFC (IDD)

127.5

ns

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)

AC CHARACTERISTICS

6400-666

5300-555

4200-444

Unit

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

Clock cycle time

CL = 6

tCK (6)

2.5

8.0

-

+

-

ns

CL = 5

tCK (5)

3.0-

8.0-

3.0

8.0

-

ns

CL = 4

tCK (4)

3.75

8.0

3.75

8.0

3.75

8.0

ns

CL = 3

tCK (3)

-

5.0

8.0

5.0

8.0

ns

CK high-level width

tCH

0.48

0.52

0.45

0.55

0.45

0.55

tCK

CK low-level width

tCL

0.48

0.52

0.45

0.55

0.45

0.55

tCK

Half clock period

tHP

min

(tCH, tCL)

min

(tCH, tCL)

min

(tCH, tCL)

ps

Access window (output) of DQS

from CK/CK#

tAC

-0.40

+0.40

-0.45

+0.45

-0.50

+0.50

ns

Data-out high-impedance

window from CK/CK#

tHZ

tAC max

+0.45

(= tAC

max)

+0.50

(= tAC

max)

ns

Data-out low-impedance

window from CK/CK#

tLZ

tAC min

tAC max

-0.45

(= tAC min)

+0.45

(= tAC

max)

-0.50

(= tAC min)

+0.50

(= tAC

max)

ns

DQ and DM input setup time

relative to DQS

tDS

0.05

0.10

ns

DQ and DM input hold time

relative to DQS

tDH

0.125

0.30

0.35

ns

DQ and DM input pulse width

( for each input )

tDIPW

0.35

tCK

Data hold skew factor

tQHS

0.3

0.34

0.4

ns

DQ-DQS hold, DQS to first DQ

to go non-valid, per access

tQH

tHP - tQHS

ns

Data valid output window

tDVW

tQH -

tDQSQ

tQH -

tDQSQ

tQH -

tDQSQ

ns

DQS input high pulse width

tDQSH

0.35

tCK

DQS input low pulse width

tDQSL

0.35

tCK

DQS falling edge to CK rising

- setup time

tDSS

0.2

tCK

DQS falling edge from CK rising

- hold time

tDSH

0.2

tCK

DQS –DQ skew, DQS to last

DQ valid, per group, per access

tDQSQ

0.2

0.24

0.30

ns

DQS read preamble

tRPRE

0.9

1.1

0.9

1.1

0.9

1.1

tCK

DQS read postamble

tRPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

DQS write preamble

tWPRE

0.35

0.25

tCK

DQS write preamble setup time

tWPRES

0

ns

DQS write postamble

tWPST

0.4

0.6

0.4

0.6

0.4

0.6

tCK

Positive DQS latching edge to

associated clock edge

tDQSS

- 0.25

+ 0.25

- 0.25

+ 0.25

- 0.25

+ 0.25

tCK

Write command to first DQS

latching transition

-

WL-

tDQSS

WL+

tDQSS

WL-

tDQSS

WL+

tDQSS

WL-

tDQSS

WL+

tDQSS

tCK

Address and control input pulse

width ( for each input )

tIPW

0.6

tCK

Address and control input setup

time

tISa

0.175

0.4

0.5

ns

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

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DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)

AC CHARACTERISTICS

6400-666

5300-555

4200-444

Unit

PARAMETER

SYMBOL

Min

Max

MIN

MAX

MIN

MAX

Address and control input hold

time

tIH

0.25

0.4

0.5

ns

CAS# to CAS# command delay

tCCD

2

tCK

ACTIVE to ACTIVE (same

bank) command period

tRC

60

ns

ACTIVE bank a to ACTIVE

bank b command

tRRD

7.5

ns

ACTIVE to READ or WRITE

delay

tRCD

15

ns

Four bank Activate period

tFAW

37.5

ns

ACTIVE to PRECHARGE

command

tRAS

45

70,000

45

70,000

45

70,000

ns

Internal READ to precharge

command delay

tRTP

7.5

ns

Write recovery time

tWR

15

ns

Auto precharge write recovery +

precharge time

tDAL

tWR + tRP

ns

Internal WRITE to READ

command delay

tWTR

7.5

ns

PRECHARGE command period

tRP

15

ns

PRECHARGE ALL command

period

tRPA

tRP + tCK

ns

LOAD MODE command cycle

time

tMRD

2

tCK

CKE low to CK, CK#

uncertainty

tDELAY

tIS + tCK + tIH

tCK

REFRESH to ACTIVE or

REFRESH to REFRESH

command interval

tRFC

127.5

70,000

127.5

70,000

127.5

70,000

ns

Average periodic refresh

interval

(0°C<= TCASE <= 85 °C)

tREFI

7.8

µs

(85°C<= TCASE <= 95 °C)

tREFI (IT)

3.9

µs

Exit SELF REFRESH to non-

READ command

tXSNR

tRFC(min)

+ 10

tRFC(min)

+ 10

tRFC(min)

+ 10

ns

Exit SELF REFRESH to READ

command

tXSRD

200

tCK

Exit SELF REFRESH timing

reference

tISXR

tIS

ps

ODT turn-on delay

tAOND

2

tCK

ODT turn-on

tAON

tAC(min)

tAC(max)

+ 1,000

tAC(min)

tAC(max)

+ 1,000

tAC(min)

tAC(max)

+ 1,000

ps

ODT turn-off delay

tAOFD

2.5

tCK

ODT turn-off

tAOF

tAC(min)

tAC(max)

+ 600

tAC(min)

tAC(max)

+ 600

tAC(min)

tAC(max)

+ 600

ps

ODT turn-on (power-down

mode)

tAONPD

tAC(min)

+ 2,000

2 x tCK +

tAC(max)

+ 1,000

tAC(min)

+ 2,000

2 x tCK +

tAC(max)

+ 1,000

tAC(min)

+ 2,000

2 x tCK +

tAC(max)

+ 1,000

ps

ODT turn-off (power-down

mode)

tAOFPD

tAC(min)

+ 2,000

2.5 x tCK

+

tAC(max)

+ 1,000

tAC(min)

+ 2,000

2.5 x tCK

+

tAC(max)

+ 1,000

tAC(min)

+ 2,000

2.5 x tCK

+

tAC(max)

+ 1,000

ps

ODT to power-down entry

latency

tANPD

3

tCK

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 11

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)

AC CHARACTERISTICS

6400-666

5300-555

4200-444

Unit

PARAMETER

SYMBOL

Min

Max

MIN

MAX

MIN

MAX

ODT power-down exit

latency

tAXPD

8

tCK

ODT enable from MRS

command

tMOD

12

ns

Exit active power-down to

READ command, MR [bit 12

= 0]

tXARD

2

tCK

Exit active power-down to

READ command, MR [bit 12

= 1]

tXARDS

8 – AL

7 – AL

6 – AL

tCK

Exit precharge power-down

to any non-READ command

tXP

2

tCK

CKE minimum high/low time

tCKE

3

tCK

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 12

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SERIAL PRESENCE-DETECT MATRIX

BYTE

DESCRIPTION

6400-666

5300-555

4200-444

0

NUMBER OF SPD BYTES USED

0x80

1

TOTAL NUMBER OF BYTES IN SPD DEVICE

0x08

2

FUNDAMENTAL MEMORY TYPE

0x08

3

NUMBER OF ROW ADDRESSES ON ASSEMBLY

0x0E

4

NUMBER OF COLUMN ADDRESSES ON

ASSEMBLY

0x0A

5

DIMM HIGHT AND MODULE RANKS

0x60

6

MODULE DATA WIDTH

0x40

7

MODULE DATA WIDTH (continued)

0x00

8

MODULE VOLTAGE INTERFACE LEVELS (VDDQ)

0x05

9

SDRAM CYCLE TIME, (tCK ) [max CL]

CL = 6 (6400), CL = 5 (5300), CL = 4 (4200)

0x25

0x30

0x3D

10

SDRAM ACCESS FROM CLOCK, (tAC) [max CL]

CL = 6 (6400), CL = 5 (5300), CL = 4 (4200)

0x40

0x45

0x50

11

MODULE CONFIGURATION TYPE

0x00

12

REFRESH RATE / TYPE

0x82

13

SDRAM DEVICE WIDTH (PRIMARY SDRAM)

0x08

14

ERROR- CHECKING SDRAM DATA WIDTH

0x00

15

MINIMUM CLOCK DELAY, BACK-TO-BACK

RANDOM COLUMN ACCESS

0x00

16

BURST LENGTHS SUPPORTED

0x0C

17

NUMBER OF BANKS ON SDRAM DEVICE

0x08

18

CAS LATENCIES SUPPORTED

0x70

0x38

0x18

19

MODULE THICKNESS

0x01

20

DDR2 DIMM TYPE

0x04

21

SDRAM MODULE ATTRIBUTES

0x00

22

SDRAM DEVICE ATTRIBUTES: Weak Driver and

50 ODT

0x03

0x01

23

SDRAM CYCLE TIME, (tCK) [max CL – 1]

CL = 5 (6400), CL = 4 (5300), CL = 3 (4200)

0x30

0x3D

0x50

24

SDRAM ACCESS FROM CK, (tAC) [max CL – 1]

CL = 5 (6400), CL = 4 (5300), CL = 3 (4200)

0x40

0x45

0x50

25

SDRAM CYCLE TIME, (tCK) [max CL – 2]

CL = 4 (6400), CL = 3 (5300)

0x3D

0x50

0x00

26

SDRAM ACCESS FROM CK, (tAC) [max CL – 2]

CL = 4 (6400), CL = 3 (5300)

0x40

0x45

0x00

27

MINIMUM ROW PRECHARGE TIME, (tRP)

0x3C

28

MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD)

0x1E

29

MINIMUM RAS# TO CAS# DELAY, (tRCD)

0x3C

30

MINIMUM RAS# PULSE WIDTH, (tRAS)

0x2D

31

MODULE BANK DENSITY

0x01

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 13

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SERIAL PRESENCE-DTECT MATRIX (continued)

BYTE

DESCRIPTION

6400-666

5300-555

4200-444

32

ADDRESS AND COMMAND SETUP TIME, (tISb)

0x17

0x20

0x25

33

ADDRESS AND COMMAND HOLD TIME, (tIHb)

0x25

0x27

0x37

34

DATA / DATA MASK INPUT SETUP TIME, (tDSb)

0x05

0x10

35

DATA / DATA MASK INPUT HOLD TIME, (tDHb)

0x12

0x17

0x22

36

WRITE RECOVERY TIME, (tWR)

0x3C

37

WRITE to READ Command Delay, (tWTR)

0x1E

38

READ to PRECHARGE Command Delay, (tRTP)

0x1E

39

Mem Analysis Probe

0x00

40

Extension for Bytes 41 and 42

0x06

41

MIN ACTIVE AUTO REFRESH TIME, (tRC)

0x3C

42

MINIMUM AUTO REFRESH TO ACTIVE /

AUTO REFRESH COMMAND PERIOD, (tRFC)

0x7F

43

SDRAM DEVICE MAX CYCLE TIME, (tCKMAX)

0x80

44

SDRAM DEVICE MAX DQS-DQ SKEW TIME,

(tDQSQ)

0x14

0x18

0x1E

45

SDRAM DEVICE MAX READ DATA HOLD SKEW

FACTOR, (tQHS)

0x1E

0x22

0x28

46

PLL Relock Time

0x00

47-61

Optional Features, not supported

0x00

62

SPD REVISION

0x13

63

CHECKSUM FOR BYTES 0-62

0xCA

0xEF

0x9A

64-66

MANUFACTURER`S JEDEC ID CODE

0x7F

67

MANUFACTURER`S JEDEC ID CODE (continued)

0xDA

68-71

RESERVED

0x00

72

MANUFACTURING LOCATION

0x01 (Switzerland) | 0x02 (Germany) | 0x03 (USA)

73-90

MODULE PART NUMBER (ASCII)

“SEN01G64D1BH1MT-xx”

91

PCB IDENTIFICATION CODE

x

92

IDENTIFICATION CODE (continued)

x

93

YEAR OF MANUFACTURE IN BCD

x

94

WEEK OF MANUFACTURE IN BCD

x

95-98

MODULE SERIAL NUMBER

x

99-127

MANUFACTURER-SPECIFIC DATA (RSVD)

0x00

128-255

Open for customer use

0xff

Part Number Code

S

E

N

01G

64

D1

B

H

1

MT

-

25

*

R

1

2

3

4

5

6

7

8

9

10

11

12

13

*RoHs compl.

Swissbit AG

DDR2-800MT/s

SDRAM DDR2

200 Pin Unbuffered 1.8V

Chip Vendor (MICRON)

Depth (1GB)

1 Module Rank

Width

Chip Rev. H

PCB-Type (8231a)

Chip organisation x8

* optional / additional information

Data Sheet Rev.1.3 23.11.2010

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 14

CH-9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 14

Locations

Swissbit AG

Industriestrasse 4 – 8

CH – 9552 Bronschhofen

Switzerland

Phone: +41 (0)71 913 03 03

Fax: +41 (0)71 913 03 15

_____________________________

Swissbit Germany GmbH

Wolfener Strasse 36

D – 12681 Berlin

Germany

Phone: +49 (0)30 93 69 54 – 0

Fax: +49 (0)30 93 69 54 – 55

_____________________________

Swissbit NA, Inc.

14 Willett Avenue, Suite 301A

Port Chester, NY 10573

USA

Phone: +1 914 935 1400

Fax: +1 914 935 9865

_____________________________

Swissbit NA, Inc.

3913 Todd Lane, Suite – 307

Austin, TX 78744

USA

Phone: +1 512 302 9001

Fax: +1 512 302 4808

_____________________________

Swissbit Japan, Inc.

3F Core Koenji,

2-1-24 Koenji-Kita, Suginami-Ku,

Tokyo 166-0002

Japan

Phone: +81 3 5356 3511

Fax: +81 3 5356 3512

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Swissbit:

SEN01G64D1BH1MT-25WR