VESD15A1-HD1
www.vishay.com Vishay Semiconductors
Rev. 1.5, 16-May-17 1Document Number: 82724
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
ESD Protection Diode in LLP1006-2L
MARKING (example only)
Bar = cathode marking
X = date code
Y = type code (see table below)
DESIGN SUPPORT TOOLS click logo to get started
FEATURES
Ultra compact LLP1006-2L package
Low package height < 0.4 mm
1-line ESD protection
Low leakage current < 0.01 μA
Low load capacitance CD = 45 pF
(VR = 0 V; f = 1 MHz)
ESD immunity acc. IEC 61000-4-2
± 30 kV contact discharge
± 30 kV air discharge
High surge current acc. IEC 61000-4-5 IPP > 6 A
Soldering can be checked by standard vision inspection.
No X-ray necessary
Pin plating NiPdAu (e4) no whisker growth
e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
PATENT(S): www.vishay.com/patents
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
PATENT(S): www.vishay.com/patents
This Vishay product is protected by one or more United States and international patents.
20856
21
20855
21121
XY
Available
Models
ORDERING INFORMATION
DEVICE NAME ORDERING CODE TAPED UNITS PER REEL
(8 mm TAPE on 7" REEL) MINIMUM ORDER QUANTITY
VESD15A1-HD1 VESD15A1-HD1-G4-08 8000 8000
PACKAGE DATA
DEVICE NAME PACKAGE
NAME
TYPE
CODE WEIGHT MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL
SOLDERING
CONDITIONS
VESD15A1-HD1 LLP1006-2L W 0.72 mg UL 94 V-0 MSL level 1
(according J-STD-020)
Peak temperature
max. 260 °C
ABSOLUTE MAXIMUM RATINGS RATINGS VESD15A1-HD1
PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT
Peak pulse current Acc. IEC 61000-4-5; tP = 8/20 μs; single shot IPPM 6A
Peak pulse power Acc. IEC 61000-4-5; tP = 8/20 μs; single shot PPP 150 W
ESD immunity Contact discharge acc. IEC 61000-4-2; 10 pulses VESD
± 30 kV
Air discharge acc. IEC 61000-4-2; 10 pulses ± 30 kV
Operating temperature Junction temperature TJ-40 to +125 °C
Storage temperature Tstg -55 to +150 °C
VESD15A1-HD1
www.vishay.com Vishay Semiconductors
Rev. 1.5, 16-May-17 2Document Number: 82724
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
BiAs-MODE (bidirectional asymmetrical protection mode)
With the VESD15A1-HD1 one signal- or data-lines (L1) can be protected against voltage transients. With pin 1 connected to
ground and pin 2 connected to a signal- or data-line which has to be protected. As long as the voltage level on the data- or
signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the protection diode
between data line and ground offers a high isolation to the ground line. The protection device behaves like an open switch.
As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode
becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The
clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance
(resistance and inductance) of the protection device.
Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of
the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level.
Due to the different clamping levels in forward and reverse direction the VESD15A1-HD1 clamping behavior is bidirectional and
asymmetrical (BiAs).
ELECTRICAL CHARACTERISTICS VESD15A1-HD1
(Tamb = 25 °C, unless otherwise specified)
PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT
Protection paths Number of line which can be protected Nchannel - - 1 lines
Reverse stand-off voltage Max. reverse working voltage VRWM --15V
Reverse voltage At IR = 0.1 μA VR15 - - V
Reverse current At VR = 15 V IR- < 0.01 0.1 μA
Reverse breakdown voltage At IR = 1 mA VBR 15.5 16 17 V
Reverse clamping voltage At IPP = 1 A VC-1820V
At IPP = IPPM = 6 A VC-2427V
Forward clamping voltage
At IPP = 0.2 A VF- 0.85 1.2 V
At IPP = 1 A VF-1.11.3V
At IPP = IPPM = 6 A VF-2.02.5V
Capacitance At VR = 0 V; f = 1 MHz CD-4550pF
At VR = 7.5 V; f = 1 MHz CD-18-pF
Clamping voltage
Transmission line pulse (TLP), tp = 100 ns
ITLP = 8 A VC-TLP -19- V
Transmission line pulse (TLP), tp = 100 ns
ITLP = 16 A VC-TLP - 20.5 - V
Dynamic resistance Transmission line pulse (TLP), tp = 100 ns RDYN -0.27- Ω
L1
20925
2
1
Ground
BiAs
VESD15A1-HD1
www.vishay.com Vishay Semiconductors
Rev. 1.5, 16-May-17 3Document Number: 82724
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 Ω/150 pF)
Fig. 2 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
Fig. 5 - Typical Reverse Voltage VR vs.
Reverse Current IR
Fig. 6 - Typical Clamping Voltage vs.
Peak Pulse Current IPP
10
100
1000
10000
0
20
40
60
80
100
120
-10 0 10 20 30 40 50 60 70 80 90 100
Axis Title
1st line
2nd line
2nd line
IESD (%)
t (ns)
2nd line
Rise time = 0.7 ns to 1 ns
53
27
20557
10
100
1000
10000
0
20
40
60
80
100
010203040
Axis Title
1st line
2nd line
2nd line
IPPM (%)
t (µs)
2nd line
20 µs to 50 %
8 µs to 100 %
20548
f = 1 MHz
0
10
20
30
40
45
50
35
25
15
5
0 5 10 15
VR (V)
CD (pF)
0.001
0.01
0.1
1
10
100
0.5 0.6 0.7 0.8 1.0
VF (V)
IF (mA)
1000
0.9
0
2
4
6
8
10
12
14
18
0.01 0.1 1 10 100 1000 10 000
IR (µA)
VR (V)
16
0
5
10
15
20
25
01234 567 8
Reverse
Forward
IPP (A)
V
F
/V
C
(V)
Measured acc. IEC 61000-4-5
(8/20 µs - wave form)
VC
30
VESD15A1-HD1
www.vishay.com Vishay Semiconductors
Rev. 1.5, 16-May-17 4Document Number: 82724
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Clamping Performance at +8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 8 - Typical Clamping Performance at -8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 9 - Typical Peak Clamping Voltage vs. TLP current
(TLP = transmission line pulse; tp = 100 ns)
-20
-10
0
10
20
30
40
50
60
70
- 10 0 10 20 30 40 50 60 70 80 90
Acc. IEC 61000-4-2
+8 kV
contact discharge
t (ns)
VC-ESD (V)
-50
-40
-30
-10
0
10
-10 0 102030405060708090
t (ns)
VC-ESD (V)
-20
Acc. IEC 61000-4-2
-8 kV
contact discharge
VESD15A1-HD1
www.vishay.com Vishay Semiconductors
Rev. 1.5, 16-May-17 5Document Number: 82724
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PACKAGE DIMENSIONS in millimeters (inches): LLP1006-2L
0.3 [0.012]
0.2 [0.008]
0.45 [0.018]
0.35 [0.014]
0.65 [0.026]
0.55 [0.022]
1.05 [0.041]
0.95 [0.037]
Foot print recommendation:
1 [0.039]
Solder
resist mask
Solder pad
Document no.: S8-V-3906.04-005 (4)
Rev. 7 - Date: 11.May 2016
20812
0.05 [0.002] 0.5 [0.020]
0.55 [0.022]
0.45 [0.018]
0.4 [0.016]
0.33 [0.013]
0.6 [0.024]
0.5 [0.020]
0.25 [0.010]
0.15 [0.006]
0.05 [0.002]
0 [0.000]
0.2 [0.008]
0.125 [0.005] ref.
Orientation identication
0.25 [0.010]
Pad Design Patented:
US 9.018.537 B2)
P
(
LLP1006-2X
Top view Pad layout - view from top
seen at bottom side
Unreeling direction
Orientation
identication
S8-V-3906.04-017 (4)
02.05.2017
22965
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 08-Feb-17 1Document Number: 91000
Disclaimer
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