MB39C006A
1 ch DC/DC Converter IC with PFM/PWM
Synchronous Rectification Datasheet
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-09201 Rev . *A Revised November 1 1, 2016
The MB39C006A is a current mode type 1-channel DC/DC converter IC built-in switching FET, synchronous rectification, and down
conversion support. The device is integrated with a switching FET, oscillator, error amplifier, PFM/PWM control circuit, reference
voltage source, and POWERGOOD circuit.
External inductor and decoupling capacitor are needed only for the external component.
MB39C006A is small, achieve a highly effective DC/DC converter in the full load range, this is suitable as the built-in power supply
for handheld equipment such as mobile phone/PDA, DVDs, and HDDs.
Features
■High efficiency : 96 (Max)
■Low current consumption : 30 A (at PFM)
■Output current (DC/DC) : 800 mA (Max)
■Input voltage range : 2.5 V to 5.5 V
■Operating frequency : 2.0/3.2 MHz (Typ)
■Built-in PWM operation fixe d function
■No flyback diode needed
■Low dropout operation : For 100 on duty
■Built-in high-precision reference voltage generator : 1.20 V 2
■Consumption current in shutdown mode : 1 A or less
■Built-in switching FET : P-ch MOS 0.3 (Typ) N-ch MOS 0.2 (Typ)
■High speed for input and load transient response in the current mode
■Over temperature protection
■Packaged in a compact pa ckage : SON10
Applications
■Flash ROMs
■MP3 players
■Electronic dictionary devices
■Surveillance cameras
■Portable GPS navigators
■Mobile phones etc.
Document Number: 002-09201 Rev. *A Page 2 of 45
MB39C006A
Contents
Features.........................................................................................................................................................1
Applications ..................................................................................................................................................1
1. Pin Assignment.........................................................................................................................................3
2. Pin Descriptions .......................................................................................................................................3
3. I/O Pin Equivalent Circuit Diagram .........................................................................................................4
4. Block Diagram...........................................................................................................................................5
5. Function of Each Block............................................................................................................................7
6. Absolute Maximum Ratings.....................................................................................................................9
7. Recommended Operating Conditions ..................................................................................................10
8. Electrical Characteristics.......................................................................................................................11
9. Test Circuit for Measuring Typical Operating Characteristics...........................................................13
10. Application Notes .................................................................................................................................14
10.1 Selection of components.................................................................................................................14
10.2 Output voltage setting.....................................................................................................................15
10.3 About conversion efficiency............................................................................................................15
10.4 Power dissipation and heat considerations.....................................................................................16
10.5 Transient response.........................................................................................................................16
10.6 Board layout, design example.........................................................................................................17
11. Example of Standard Operation Characteristics...............................................................................18
12. Application Circuit Examples..............................................................................................................33
13. Usage Precautions ...............................................................................................................................35
14. Ordering Information............................................................................................................................35
15. RoHS Compliance Information of Lead (Pb) Free Version ...............................................................35
16. Labeling Sample (Lead Free Version).................................................................................................36
17. Marking Format.....................................................................................................................................36
18. Recommended Mounting Conditions of MB39C006APN..................................................................37
18.1 Cypress Recommended Mounting Conditions................................................................................37
18.2 Parameters for Each Mounting Method..........................................................................................37
19. Evaluation Board Specification...........................................................................................................38
20. EV Board Ordering Information...........................................................................................................42
21. Package Dimension..............................................................................................................................43
Document History.......................................................................................................................................44
Sales, Solutions, and Legal Information ..................................................................................................45
Document Number: 002-09201 Rev. *A Page 3 of 45
MB39C006A
1. Pin Assignment
2. Pin Descriptions
Pin No Pin name I/O Description
1 LX O Inductor connection output pin. High impedance during shut down.
2GND
Ground pin.
3 CTL I Control input pin. (L : Shut down / H : Normal operation)
4 VREF O Reference voltage output pin.
5 POWERGOOD O POWERGOOD circuit output pin. Internally connected to an N-ch MOS open drain
circuit.
6FSELI
Frequency switch pin.
(L (open) : 2.0 MHz, H : 3.2 MHz)
7 VREFIN I Error amplifier (Error Amp) non-inverted input pin.
8MODEI
Operation mode switch pin.
(L : PFM/PWM mode, OPEN : PWM mode)
9 OUT I Output voltage feedback pin.
10 VDD Power supply pin.
(Top View)
(LCC-10P-M04)
POWERGOODVREFCTLGNDLX
VDD OUT MODE VREFIN FSEL
12345
109876
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MB39C006A
3. I/O Pin Equivalent Circuit Diagram
∗
∗
GND
VDD
GND
VDD
LX VREF
POWER
GOOD
∗
GND
FSEL
∗
GND
VDD
∗
GND
VDD
CTL
GND
VDD
∗
∗
VREFIN OUT
∗
∗
∗
MODE
*
GND
VDD
*
* : ESD Protection devi ce
Document Number: 002-09201 Rev. *A Page 5 of 45
MB39C006A
4. Block Diagram
VDD
×3Error Amp
IOUT
Comparator
1.20 V VREF PFM/PWM
Logic
Control
ON/OFF
CTL
OUT
POWERGOOD POWER-
GOOD
VREF
VREFIN
DAC
MODE
FSEL GND
LX VOUT
VDD
VIN
10
3
9
5
4
7
8
−
+
6 2
1
Mode
Control
Lo : PFM/PWM
OPEN : PWM
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MB39C006A
■Current mode
❐Original voltage mode type:
Stabilize the output voltage by comparing two items below and on-duty control.
• Voltage (VC) obtained through negative feedback of the output voltag e by Error Amp
• Reference triangular wave (VTRI)
❐Current mode type:
Instead of the triangular wave (VTRI), the voltage (VIDET) obtained through I-V conversion of the sum of currents that flow in the
oscillator (rectangular wave generation circuit) and SW FET is used.
Stabilize the output voltage by comparing two items below and on-duty control.
• Voltage (VC) obtained through negative feedback of the output voltag e by Error Amp
• Voltage (VIDET) obtained through I-V conversion of the sum of current that flow in th e oscillator (rectangular wave generation
circuit) and SW FET
V
IN
ton
toff
V
TRI
Vc
Vc
V
TRI
V
IN
toff
Vc
Vc
V
IDET
S
R
ton
SR-FF
V
IDET
Q
Voltage mode type model Current mode type model
Oscillator
Note : The above models illustrate the general operation and an actual operation will be preferred in the IC.
Document Number: 002-09201 Rev. *A Page 7 of 45
MB39C006A
5. Function of Each Block
■PFM/PWM Logic control circuit
In normal operation, frequency (2.0 MHz/3.2 MHz) which is set by the built-in oscillator (square wave oscillation circuit) controls the
built-in P-ch MOS FET and N-ch MOS FET for the synchronous rectification operation. In the light load mode, the intermittent (PFM)
operation is executed.
This circuit protects against pass-through current caused by synchronous rectifica ti on and against reverse current caused in a non-
successive operation mode.
■IOUT comparator circuit
This circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch MOS FET.
By comparing VIDET obtained through I-V conversion of peak current IPK of ILX with the Error Amp output, the built-in P-ch MOS FET is
turned off via the PFM/PWM Logic Control circuit.
■Error Amp phase compensation circuit
This circuit compares the output voltage to reference voltages such as VREF. The MB39C006A has a built-in phase compensation
circuit that is designed to optimize the operation of the MB39C 006A. This needs neither to be considered nor addition of a phase
compensation circuit and an external phase compensation device.
■VREF circuit
A high accuracy reference voltage is generated with BGR (bandgap reference) circuit. The output voltage is 1.20 V (Typ).
■POWERGOOD circuit
The POWERGOOD circuit monito rs the voltage at the OUT pin. The POWERGOOD pin is open drain output. Use the pin with pull-
up using the external resistor in the normal operation.
When the CTL is at the H level, the POWERGOOD pin becomes the H level. However, if the output voltage drops because of over
current and etc, the POWERGOOD pin becomes the L level.
Timing chart example : (POWERGOOD pin pulled up to VIN)
VUVLO : UVLO threshold voltage
tDLYPG : POWERGOOD delay time
(pull up to VIN)
Document Number: 002-09201 Rev. *A Page 8 of 45
MB39C006A
■Protection circuit
The MB39C006A has a built-in over-temp erature protection circuit.
The over-temperature protection circuit turns off both N-ch and P-ch switching FETs when the junction temperature reaches +135 C.
When the junction temperature drops to + 110 C, the switching FET returns to the normal operation.
Since the PFM/PWM control circuit of the MB39C006A is in the control method in current mode, the current peak value is also
monitored and controlled as required.
■Function Table
* : Don't care
MODE Input Output
Switching
frequency CTL MODE FSEL OUTPUT pin
voltage VREF POWERGOOD
Shutdown
mode L * * Output stop Output
stop Function stop
PFM/PWM
mode 2.0 MHz H L L VOUT voltage
output 1.2 V Operation
PWM fixed
mode 2.0 MHz H OPEN L VOUT voltage
output 1.2 V Operation
PFM/PWM
mode 3.2 MHz H L H VOUT voltage
output 1.2 V Operation
PWM fixed
mode 3.2 MHz H OPEN H VOUT voltage
output 1.2 V Operation
Document Number: 002-09201 Rev. *A Page 9 of 45
MB39C006A
6. Absolute Maximum Ratings
*1 : See “Example of Standard Operation Characteristics Power dissipation vs. Operating ambient temperature” for the package
power dissipation of Ta from + 25 C to + 85 C.
*2 : When mounted on a four- layer epoxy board of 11.7 cm 8.4 cm
*3 : IC is mounted on a four-layer epoxy board, which has thermal via, and the IC's thermal pad is connected to the epoxy board
(Thermal via is 4 holes).
*4 : IC is mounted on a four-layer epoxy board, which has no thermal via, and the IC's thermal pad is connected to the epoxy board.
Notes:
■The use of negative voltages below 0.3 V to the GND pin may create parasitic transistors on LSI lines, which can cause abnormal
operation.
■This device can be damaged if the LX pin is short-circuited to VDD pin or GND pin.
■Take measures not to keep the FSEL pin falling below the GND pin potential of the MB39C006A as much as possible. In addition
to erroneous operation, the IC may latch up and destroy itself if 110 mA or more current flows from this pin.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Condition Rating Unit
Min Max
Power supply voltage VDD VDD pin 0.3 6.0 V
Signal input voltage VISIG
OUT pin 0.3 VDD 0.3
VCTL, MODE, FSEL pins 0.3 VDD 0.3
VREFIN pin 0.3 VDD 0.3
POWERGOOD pull-up voltage VIPG POWERGOOD pin 0.3 6.0 V
LX voltage VLX LX pin 0.3 VDD 0.3 V
LX peak current IPK The upper limit value of ILX 1.8 A
Power dissipation PD
Ta 25 C2632*1, *2, *3mW
980*1, *2, *4
Ta 85 C1053*1, *2, *3mW
392*1, *2, *4
Operating ambient temperature Ta 40 85 C
Storage temperatur e TSTG 55 125 C
Document Number: 002-09201 Rev. *A Page 10 of 45
MB39C006A
7. Recommended Operating Conditions
Note : The output current from this device has a situation to decrease if the power supp ly voltage (VIN) and the DC/DC
converter output voltage (VOUT) differ only by a small amount. This is a result of slope compensation and will not damage this
device.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating condi tions, or combina tions not repr esented on th e
data sheet. Users considering application outside the listed conditions are advised to contact their
represen ta tive s be fo re ha n d.
Parameter Symbol Condition Value Unit
Min Typ Max
Power supply voltage VDD 2.5 3.7 5.5 V
VREFIN voltage VREFIN 0.15 1.20 V
CTL voltage VCTL 05.0 V
LX current ILX 800 mA
POWERGOOD current IPG 1mA
VREF output current IROUT 2.5 V VDD 3.0 V 0.5 mA
3.0 V VDD 5.5 V  1
Inductor value L fOSC1 2.0 MHz (FSEL L) 2.2 H
fOSC2 3.2 MHz (FSEL H) 1.5
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MB39C006A
8. Electrical Characteristics
(Ta 25 C, VDD 3.7 V, VOUT setting value 2.5 V, MODE 0 V)
* : This value isn't be specified. This should be used as a reference to support de signing the circuits.
Parameter Symbol Pin
No. Condition Value Unit
Min Typ Max
DC/DC
converter
block
Input current
IREFINM
7
VREFIN 0.833 V 100 0 100 nA
IREFINLVREFIN 0.15 V 100 0 100 nA
IREFINHVREFIN 1.20 V 100 0 100 nA
Output voltage VOUT
9
VREFIN 0.833 V,
OUT 100 mA 2.45 2.50 2.55 V
Input stability LINE 2.5 V VDD 5.5 V *110 mV
Load stability LOAD 100 mA OUT
800 mA 10 mV
Out pin input
impedance ROUT OUT 2.0 V 0.6 1.0 1.5 M
LX peak current IPK
1
Output shorted to GND 0.9 1.2 1.7 A
PFM/PWM switch
current IMSW FSEL 0 V, L 2.2 H30 mA
Oscillation
frequency fOSC1 FSEL 0 V 1.6 2.0 2.4 MHz
fOSC2 FSEL 3.7 V 2.56 3.20 3.84 MHz
Rise delay time tPG 3, 9 C1 4.7 F, OUT 0 A,
VOUT 90% 45 80 s
SW NMOS FET
OFF voltage VNOFF
1
20* mV
SW PMOS FET ON
resistance RONP LX 100 mA 0.30 0.47
SW NMOS FET
ON resistance RONN LX 100 mA 0.20 0.36
LX leak current ILEAKM0 LX VDD*21.0 8.0 A
ILEAKHVDD 5.5 V, 0 LX VDD*22.0 16.0 A
Protection
circuit block
Over temperature
protection
(Junction Temp.)
TOTPH

120* 135* 155* C
TOTPL 95* 110* 130* C
UVLO threshold
voltage VTHH
10 2.07 2.20 2.33 V
VTHL 1.92 2.05 2.18 V
UVLO hysteresis
width VHYS 0.08 0.15 0.25 V
Document Number: 002-09201 Rev. *A Page 12 of 45
MB39C006A
(Ta 25 C, VDD 3.7 V, VOUT settin g va lue 2.5 V, MODE 0 V)
*1 : The minimum value of VDD is the 2. 5 V or V OUT setting value 0.6 V, whichever is higher.
*2 : The leak at the LX pin includes the current of the internal circuit.
*3 : Detected with respect to the output voltag e setting value of VREFIN
*4 : Current consumption based on 100 ON-duty (High side FET in full ON state). The SW FET gate drive current is not included
because the device is in full ON state (no switchin g operation). Also the load current is not incl uded.
Parameter Symbol Pin
No. Condition Value Unit
Min Typ Max
POWER-
GOOD block
POWERGOOD
threshold vo ltag e VTHPG
5
*3 VREFIN
3
0.93
VREFIN
3
0.97
VREFIN
3
0.99 V
POWERGOOD
delay time tDLYPG1 FSEL 0 V 250 s
tDLYPG2 FSEL 3.7 V 170 s
POWERGOOD
output voltage VOL POWERGOOD = 250 A0.1 V
POWERGOOD
output current IOH POWERGOOD 5.5 V 1.0 A
Control
block
CTL threshold volt-
age VTHHCT
3
0.55 0.95 1.45 V
VTHLCT 0.40 0.80 1.30 V
CTL pin
input curren t IICTL CTL 3.7 V 1.0 A
MODE threshold
voltage VTHMMD
8
OPEN setting 1.5 V
VTHLMD 0.4 V
MODE pin input
current ILMD MODE 0 V 0.8 0.4 A
FSEL threshold
voltage VTHHFS 62.96 V
VTHLFS 0.74 V
Reference
voltage
block
VREF voltage VREF 4
VREF 2.7 A,
OUT 100 mA 1.176 1.200 1.224 V
VREF load
stability LOADREF VREF 1.0 mA 20 mV
General
Shut down
power supply
current
IVDD1
10
CTL 0 V,
All circuits in OFF state 1.0 A
IVDD1H CTL 0 V, VDD 5.5 V 1.0 A
Power supply
current at
DC/DC operation
(PFM mode)
IVDD2 CTL 3.7 V,
MODE 0 V,
OUT 0 A 30 48 A
Power supply
current at
DC/DC operation
(PWM fixed mode)
IVDD2
CTL 3.7 V,
MODE OPEN,
OUT 0 A,
FSEL 0 V
4.8 8.0 mA
Power-on
invalid current IVDD CTL 3.7 V,
VOUT 90*4800 1500 A
Document Number: 002-09201 Rev. *A Page 13 of 45
MB39C006A
9. Test Circuit for Measuring Typical Operating Characteristics
Note : These components are recommended based on the operating tests authorized.
TDK : TDK Corporation
SSM : SUSUMU Co., Ltd
KOA : KOA Corporation
Component Specification Vendor Part Number Remark
R1 1 MKOA RK73G1JTTD D 1 M
R3-1
R3-2 7.5 k
120 kSSM
SSM RR0816-752-D
RR0816-124-D At VOUT 2.5 V setting
R4 300 kSSM RR0816-304-D
R5 1 MKOA RK73G1JTTD D 1 M
C1 4.7 F TDK C2012JB1A475K
C2 4.7 F TDK C2012JB1A475K
C6 0.1 F TDK C1608JB1H104K For adjusting slow start
time
L1 2.2 H TDK VLF4012AT-2R2M 2.0 MHz operation
1.5 H TDK VLF4012AT-1R5M 3.2 MHz operation
VIN
VOUT
L1
1.5 µH/2.2 µH
C1
4.7 µF IOU
T
C2
4.7 µF
SW CTL
MODE
VREF
VREFIN GND
OUT
LX
VDD
GND
R5
1 MΩ
V
DD
V
DD
MB39C006A
POWER-
GOOD
FSEL
R1
1 MΩ
R4
300 kΩ
R3-1
7.5 kΩ
R3-2
120 kΩ
SW
SW
C6
0.1 µF
103
8
4
6
7
1
9
5
2
VOUT VREFIN 2.97
Document Number: 002-09201 Rev. *A Page 14 of 45
MB39C006A
10. Application Notes
10.1 Selection of components
■Selection of an external inductor
Basically it dose not need to design inductor. The MB39C006A is designed to operate efficiently with a 2.2 H (2.0 MHz operation)
or 1.5 H (3.2 MHz operation) external inductor.
The inductor should be rated for a saturation current higher than the LX peak current value during normal operating conditions, and
should have a minimal DC resistance. (100 m or less is recommended.)
The LX peak current value IPK is obtained by the followi ng formula.
L : External inductor value
IOUT : Load current
VIN : Power supply voltage
VOUT : Output setting voltage
D : ON- duty to be switched( VOUT/VIN)
fosc : Switching frequency (2.0 MHz or 3.2 MHz)
ex) At VIN 3.7 V, VOUT 2.5 V, IOUT 0.8 A, L 2.2 H, fosc 2.0 MHz
The maximum peak current value IPK;
■I/O capacitor selection
❐Select a low equivalent series resistance (ESR) for the VDD input capacitor to suppress dissipation from ripple currents.
❐Also select a low equivalent series resistance (ESR) for the output capacitor. The variation in the inductor current causes ripple
currents on the output capacitor which, in turn, causes ripple voltages an output equal to the amount of variation multiplied by the
ESR value. The output capacitor value has a significant impact on the operating stability of the device when used as a DC/DC
converter. Therefore, Cypress generally recommends a 4.7 F capacitor , or a larger capacitor value can be used if ripple voltages
are not suitable. If the VIN/VOUT voltage difference is within 0.6 V, the use of a 10 F output ca pacitor value is recommended.
❐Types of capacitors
Ceramic capacitors are effective for reducing the ESR and afford smaller DC/DC converter circuit. However, power supply functions
as a heat generator, therefore avoid to use capacitor with the F-temperature rating
( 80% to 20%) . Cypress recommends capacitors with the B-temperature rating ( 10 to 20).
Normal electrolytic capacitors are not recommended due to th eir high ESR.
Tantalum capacitor will reduce ESR, however , it is dangerous to use because it turns into short mode when damaged. If you insist
on using a tantalum capacitor, Cypress recommends the type with an internal fuse.
IPK IOUT VIN VOUT D 1 IOUT (VIN VOUT) VOUT
Lfosc2 2 L fosc VIN
IPK IOUT (VIN VOUT) VOUT 0.8 A (3.7 V 2.5 V) 2.5 V := 0.89 A
2 L fosc VIN 2 2.2 H 2 MHz 3.7 V
Document Number: 002-09201 Rev. *A Page 15 of 45
MB39C006A
10.2 Output voltage setting
The output voltag e VOUT of the MB39C006A is defined by the voltage input to VREFIN. Supply the voltage for inputting to VREFIN
from an external power supply, or set the VREF output by dividing it with resistors.
The output voltage when the VREFIN voltage is set by dividing the VREF voltage with resistors is shown in the following formula .
Note : See “ Application Circuit Examples” for an example of this circuit.
Although the output voltage is define d according to the dividing ratio of resistance, select the resistance va lue so that the current
flowing through the resistance does not exceed the VREF current rating (1 mA) .
10.3 About conversion efficiency
The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit.
The total loss (PLOSS) of the DC/DC converter is roughly divided as follows :
PLOSS PCONT PSW PC
PCONT : Control system circuit loss (The power to operate the MB39C006A, including the gate driving power for internal SW FET s)
PSW : Switching loss (The loss caused during the switch of the IC's internal SW FETs)
PC : Continuity loss (The loss caused when currents flow through the IC's internal SW FETs and external circuits)
The IC's control circuit loss (PCONT) is extremely small, several tens of mW* with no load.
As the IC contains FET s which can switch faster with less power, the continuity loss (PC) is more predominant as the loss during heavy-
load operation than the control circuit loss (PCONT) and switching loss (PSW) .
* : The loss in the successive operation mode. This IC suppresses the loss in order to execute the PFM operation in the low load
mode (less than 100 A in no load mode). Mode is changed by the current peak value IPK which flows into switching FET. The
threshold value is about 30 mA.
Furthermore, the continuity loss (PC) is divided roughly into the loss by internal SW FET ON-resistance and by external inductor series
resistance.
PC IOUT2 (RDC D RONP (1 D) RONN)
VOUT 2.97 VREFIN, VREFIN R4 VREF
R3 R4
(VREF 1.20 V)
R4
R3
VREF
VREFIN
VREF
VREFIN
MB39C006A
4
7
Document Number: 002-09201 Rev. *A Page 16 of 45
MB39C006A
D : Switching ON-duty cycle ( VOUT / VIN)
RONP : Internal P-ch SW FET ON resistance
RONN : Internal N-ch SW FET ON resistance
RDC : External inductor series resistance
IOUT : Load current
The above formula indicates that it is important to reduce RDC as much as possible to improve efficiency by selecting components.
10.4 Power dissipation and heat considerations
The IC is so efficient that no consideration is required in most of the cases. However, if the IC is used at a low power supply voltage,
heavy load, high output voltage, or high temperature, it requires further consideration for higher efficiency.
The internal loss (P) is roughly obtained from the following formula :
P IOUT2 (D RONP (1 D) RONN)
D : Switching ON-duty cycle ( VOUT / VIN)
RONP : Internal P-ch SW FET ON resistance
RONN : Internal N-ch SW FET ON resistance
IOUT : Output current
The loss expressed by the above formula is mainly continuity loss. The internal loss includes the switching loss and the control circuit
loss as well but they are so small compared to the continuity loss they can be ignored.
In the MB39C00 6A with RONP greater than RONN, the larger the on-duty cycle, the greater the loss.
When assuming VIN 3.7 V, Ta 70 C for example, RONP 0.42 and RONN 0.36 according to the graph “MOS FET ON
resistance vs. Operating ambient temperature”. The IC's internal loss P is 144 mW at VOUT 2.5 V and IOUT 0.6 A. According to the
graph “Power dissipation vs. Operating ambient temperature”, the power dissipation at an operating ambient temperature Ta of 70
C is 539 mW and the internal loss is smaller than the power dissipation.
10.5 Transient response
Normally, IOUT is suddenly changed while VIN and VOUT are maintained constant, responsiveness including the response time and
overshoot/undershoot voltage is checked. As the MB39C006A has built-in Error Amp with an optimized design, it shows good transient
response characteristics. However, if ring ing upon sudden change of the load is high due to the operating conditions, add capacitor
C6 (e.g. 0.1 F). (Since this capacitor C6 chan ges the start time, check the start waveform as well.) This action is not required for
DAC input.
R4 C6
R3
VREF
VREFIN
VREF
VREFIN
MB39C006A
4
7
Document Number: 002-09201 Rev. *A Page 17 of 45
MB39C006A
10.6 Board layout, design example
The board layout needs to be designed to ensure the stable operation of the MB39C006A.
Follow the procedure belo w for designing the layout.
❐Arrange the input capacitor (Cin) as close as possible to both the VDD and GND pins. Make a through hole (TH) near the pins of
this capacitor if the board has planes for power and GND.
❐Large AC currents flow between the MB39C006A and the input capacitor (Cin), output capacitor (CO), and external inductor (L).
Group these components as close as possible to the MB39C006A to reduce the overall loop area occupie d by this group. Also
try to mount these components on the same surface and arrange wiring without through hole wiring. Use thick, short, and straight
routes to wire the net (The layout by planes is recommended.).
❐The feedback wiring to the OUT should be wired from the voltage output pin closest to the output capacitor (CO). The OUT pin is
extremely sensitive and should thus be kept wired awa y from the LX pin of the MB39C006A as far as possible.
❐If applying voltage to the VREFIN pin through dividing resistors, arrange the resistors so that the wiring can be kept as short as
possible. Also arrange them so that the GND pin of the VREFIN resistor is close to the IC's GND pi n. Further, provide a GND
exclusively for the control line so that the resistor can be connected via a path that does not carry current. If installing a bypass
capacitor for the VREFIN, put it close to the VREFIN pin.
❐T ry to make a GND plane on the surface to which the MB39C006A will be mounted. For efficient heat dissipation when using the
SON 10 package, Cypress recommends providing a thermal via in the footprint of the thermal pad.
■Layout Example of IC SW components
■Notes for Circuit Design
The switching operation of the MB39C006A works by monitoring and controlling the peak current which, incidentally, serves as form
of short-circuit protection. However, do not leave the output short-circuited for long periods of time. If the output is short-circuited where
VIN < 2.9 V, the current limit value (peak current to the indu ctor) tends to rise. Leaving in the short-circuit state, the temperatur e of
the MB39C006A will continue rising and activate the thermal protection.
Once the thermal protection stops the output, the temperature of the IC will go down and operation will resume, after which the output
will repeat the starting and stopping.
Although this effect will not destroy the IC, the thermal exposure to the IC over prolonged hours may affect the peripherals surrounding
it.
Co Cin
Vo L
GND 1 Pin VIN
Feedback line
Document Number: 002-09201 Rev. *A Page 18 of 45
MB39C006A
11. Example of Standard Operation Characteristics
(Shown below is an example of characteristics for connection acco rding to Test Circuit for Measuring Typi cal Operating
Characteristics.)
50
60
70
80
90
100
V
IN
= 3.0 V
V
IN
= 4.2 V
Ta = +25°C
V
OUT
= 2.5 V
FSEL = L
MODE = L
V
IN
= 3.7 V
V
IN
= 5.0 V
110100
1000
50
60
70
80
90
100
VIN = 3.0 V
VIN = 4.2 V
Ta = +25°C
VOUT = 1.2 V
FSEL = L
MODE = L
VIN = 3.7 V
VIN = 5.0V
110 100 1000
50
60
70
80
90
100
VIN = 3.0 V
VIN = 4.2 V
Ta = +25°C
VOUT = 1.8 V
FSEL = L
MODE = L
VIN = 3.7 V
VIN = 5.0 V
110 100 1000
0
10
20
30
40
50
60
70
80
90
100
VIN = 4.2 V
Ta = +25°C
VOUT = 3.3 V
FSEL = L
MODE = L
VIN = 3.7 V
VIN = 5.0 V
110 100 1000
Load curren t IOUT (m A)
Conversion efficiency ()
Load current IOUT (mA)
Conversion eff icie nc y ()
Load current IOUT (mA)
Conversion efficiency ()
Load current IOUT (mA)
Conversion efficiency ()
Conversion efficiency vs. Load current
(2.0 MHz:PFM/PWM mode) Conversion efficiency vs. Load current
(2.0 MHz:PFM/PWM mode)
Conversion efficiency vs. Load current
(2.0 MHz:PFM/PWM mode) Conversion efficiency vs. Load current
(2.0 MHz:PFM/PWM mode)
Document Number: 002-09201 Rev. *A Page 19 of 45
MB39C006A
0
10
20
30
40
50
60
70
80
90
100
VIN = 3.0 V
VIN = 4.2 V
VIN = 3.7 V
VIN = 5.0 V
Ta = +25°C
VOUT = 2.5 V
FSEL = L
MODE = OPEN
110100
1000
0
10
20
30
40
50
60
70
80
90
100
VIN = 3.0 V
VIN = 4.2 V
VIN = 3.7 V
VIN = 5.0V
Ta = +25°C
VOUT = 1.2 V
FSEL = L
MODE = OPEN
110100
1000
0
10
20
30
40
50
60
70
80
90
100
V
IN
= 3.0 V
V
IN
= 4.2 V
V
IN
= 3.7 V
V
IN
= 5.0 V
Ta = +25°C
V
OUT
= 1.8 V
FSEL = L
MODE = OPEN
110 100 1000
0
10
20
30
40
50
60
70
80
90
100
VIN = 4.2 V
VIN = 3.7 V
VIN = 5.0 V
Ta = +25°C
VOUT = 3.3 V
FSEL = L
MODE = OPEN
110 100 1000
Load current IOUT (mA)
Conversion efficiency ()
Load curren t IOUT (mA)
Conversion ef ficienc y ()
Load curren t IOUT (m A)
Conversion efficiency ()
Load current IOUT (mA)
Conversion efficiency ()
Conversion efficiency vs. Load current
(2.0 MHz:PWM fixed mode) Conversion efficiency vs. Load current
(2.0 MHz:PWM fixe d mo d e)
Conversion efficiency vs. Load current
(2.0 MHz:PWM fixed mode) Conversion efficiency vs. Load current
(2.0 MHz:PWM fixed mode)
Document Number: 002-09201 Rev. *A Page 20 of 45
MB39C006A
50
60
70
80
90
100
VIN = 3.0 V
VIN = 4.2 V
VIN = 3.7 V
VIN = 5.0 V
Ta = +25°C
VOUT = 2.5 V
FSEL = H
MODE = L
110 100 1000
50
60
70
80
90
100
VIN = 3.0 V
VIN = 4.2 V
VIN = 3.7 V
VIN = 5.0 V
Ta = +25°C
VOUT = 1.2 V
FSEL = H
MODE = L
110 100 1000
50
60
70
80
90
100
VIN = 3.0 V
VIN = 4.2 V
VIN = 3.7 V
VIN = 5.0 V
Ta = +25°C
VOUT = 1.8 V
FSEL = H
MODE = L
110 100 1000
0
10
20
30
40
50
60
70
80
90
100
V
IN
= 4.2 V
V
IN
= 3.7 V
V
IN
= 5.0 V
Ta = +25°C
V
OUT
= 3.3 V
FSEL = H
MODE = L
110 100 1000
Load current IOUT (mA)
Conversion efficiency ()
Load current IOUT (mA)
Conversion efficiency ()
Load current IOUT (mA)
Conversion efficiency ()
Load current IOUT (mA)
Conversion efficiency ()
Conversion efficiency vs. Load current
(3.2 MHz: PFM/PWM mode) Conversion efficiency vs. Load current
(3.2 MHz: PFM/PWM mode)
Conversion efficiency vs. Load current
(3.2 MHz:PFM/PWM mode) Conversion efficiency vs. Load current
(3.2 MHz:PFM/PW M mo d e)
Document Number: 002-09201 Rev. *A Page 21 of 45
MB39C006A
0
10
20
30
40
50
60
70
80
90
100
V
IN
= 3.0 V
V
IN
= 4.2 V
V
IN
= 3.7 V
V
IN
= 5.0 V
Ta = +25°C
V
OUT
= 2.5 V
FSEL = H
MODE = OPEN
110100
1000
0
10
20
30
40
50
60
70
80
90
100
V
IN
= 3.0 V
V
IN
= 4.2 V
V
IN
= 3.7 V
V
IN
= 5.0 V
Ta = +25°C
V
OUT
= 1.2 V
FSEL = H
MODE = OPEN
110100
1000
0
10
20
30
40
50
60
70
80
90
100
VIN = 3.0 V
VIN = 4.2 V
VIN = 3.7 V
VIN = 5.0 V
Ta = +25°C
VOUT = 1.8 V
FSEL = H
MODE = OPEN
110100
1000
0
10
20
30
40
50
60
70
80
90
100
VIN = 4.2 V
VIN = 3.7 V
VIN = 5.0 V
Ta = +25°C
VOUT = 3.3 V
FSEL = H
MODE = OPEN
110100
1000
Load current IOUT (mA)
Conversion efficiency ()
Load curren t IOUT (mA)
Conversion eff icie nc y ()
Load current IOUT (mA)
Conversion efficiency ()
Load current IOUT (mA)
Conversion efficiency ()
Conversion efficiency vs. Load current
(3.2 MHz:PWM fixed mode) Conversion efficiency vs. Load current
(3.2 MHz:PWM fixe d mo d e)
Conversion efficiency vs. Load current
(3.2 MHz:PWM fixed mode) Conversion efficiency vs. Load current
(3.2 MHz:PWM fixed mode)
Document Number: 002-09201 Rev. *A Page 22 of 45
MB39C006A
2.40
2.0 4.03.0 5.0 6.0
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
OUT = -100 mA
OUT = 0 A
Ta = +25°C
VOUT = 2.5 V
FSEL = L
MODE = L
2.0 4.03.0 5.0 6.0
2.40
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
OUT = -100 mA
OUT = 0 A
Ta = +25°C
VOUT = 2.5 V
FSEL = H
MODE = L
2.0 4.03.0 5.0 6.0
2.40
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
OUT = -100 mA
OUT = 0 A
Ta = +25°C
VOUT = 2.5 V
FSEL = L
MODE = OPEN
2.0 4.03.0 5.0 6.0
2.40
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
OUT = -100 mA
OUT = 0 A
Ta = +25°C
VOUT = 2.5 V
FSEL = H
MODE = OPEN
Input voltage VIN (V)
Output voltage VOUT (V)
Input voltage VIN (V)
Output voltage VOUT (V)
Input voltage VIN (V)
Output voltage VOUT (V)
Input voltage VIN (V)
Output voltage VOUT (V)
Output voltage vs. Input voltage
(2.0 MHz: PFM/PWM mode) Output voltage vs. Input voltage
(3.2 MHz: PFM/PWM mode)
Output voltage vs. Input voltage
(2.0 MHz: PWM fixed mode) Output voltage vs. Input voltage
(3.2 MHz: PWM fixed mode)
Document Number: 002-09201 Rev. *A Page 23 of 45
MB39C006A
2.40
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
0200
400 600 800
Ta = +25°C
VIN = 3.7 V
VOUT = 2.5 V
FSEL = L 0 200 400 600 800
2.40
2.42
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.58
2.60
Ta = +25°C
VIN = 3.7 V
VOUT = 2.5 V
FSEL = H
-50 0 +50 +100
1.10
1.12
1.14
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
V
IN
= 3.7 V
V
OUT
= 2.5 V
OUT = 0 A
FSEL = L
MODE = L
2.0 3.0 4.0 5.0 6.0
1.10
1.12
1.14
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
Ta = +25°C
VOUT = 2.5 V
FSEL = L
MODE = L
OUT = -100 mA
OUT = 0 A
Load current IOUT (mA)
Output voltage VOUT (V)
Load current IOUT (mA)
Output voltage VOUT (V)
Input voltage VIN (V)
Reference voltage VREF (V)
Operating ambient temperature Ta ( C)
Reference vo ltag e VREF (V)
Output voltage vs. Load current
(2.0 MHz) Output voltage vs. Load current
(3.2 MHz)
Reference voltage vs. Input voltage
(2.0 MHz: PFM/PWM mode)
Reference voltage vs.
Operating ambient temperature
(2.0 MHz: PFM/PWM mode)
PFM/PWM mode
PWM fixed mode
PFM/PWM mode
PWM fixed mode
Document Number: 002-09201 Rev. *A Page 24 of 45
MB39C006A
0
5
10
15
20
25
30
35
40
45
50
Ta = +25°C
V
OUT
= 2.5 V
MODE = L
2.0 3.0 4.0 5.0 6.0
2.0 3.0 4.0 5.0 6.0
0
1
2
3
4
5
6
7
8
9
10
Ta = +25°C
VOUT = 2.5 V
MODE = OPEN
-50 0 +50 +100
0
5
10
15
20
25
30
35
40
45
50
VIN = 3.7 V
VOUT = 2.5 V
MODE = L
-50 0 +50 +100
0
1
2
3
4
5
6
7
8
9
10
VIN = 3.7 V
VOUT = 2.5 V
MODE = OPEN
Input current vs. Input voltage
(PFM/PWM mode)
Input curr ent IIN (mA)
Input current vs.
Operating ambient temperature
(PWM fixed mode)
Input current IIN (mA)
Input current vs.
Operating ambient temperature
(PFM/PWM mode)
Input current IIN (mA)
Input current vs. Input voltage
(PWM fixed mode)
Input current IIN (m A)
Input voltage VIN (V)
Operating am b ient temperat ur e T a ( C) Operating ambient temperature Ta ( C)
Input voltage VIN (V)
Document Number: 002-09201 Rev. *A Page 25 of 45
MB39C006A
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
Ta = +25°C
V
OUT
= 1.8 V
OUT = -200 mA
FSEL = L
2.0 3.0 4.0 5.0 6.0
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Ta = +25°C
V
OUT
= 1.8 V
OUT = -200 mA
FSEL = H
2.0 3.0 4.0 5.0 6.0
-50
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
V
IN
= 3.7 V
V
OUT
= 2.5 V
OUT = -200 mA
FSEL = L
0+50 +100
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V
IN
= 3.7 V
V
OUT
= 2.5 V
OUT = -200 mA
FSEL = H
-50 0+50 +100
Input voltage VIN (V)
Oscillation frequency fOSC1 (MHz)
Input voltage VIN (V)
Oscillation frequency fOSC2 (MHz)
Operating ambient temperature Ta ( C)
Oscillation frequency fOSC1 (MHz)
Operating ambient temperature Ta ( C)
Oscillation frequency fOSC2 (MHz)
Oscillation frequency vs. Input voltage
(2.0 MHz) Oscillation frequency vs. Input voltage
(3.2 MHz)
Oscillation frequency vs.
Operating ambient temperature
(2.0 MHz)
Oscillation frequency vs.
Operating am b ient temperat ur e
(3.2 MHz)
Document Number: 002-09201 Rev. *A Page 26 of 45
MB39C006A
0.0
0.1
0.2
0.3
0.4
0.5
0.6
P-ch
N-ch
Ta = +25°C
2.0 3.0 4.0 5.0 6.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
VIN = 5.5 V
VIN = 3.7 V
−
50
0
+50 +100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
V
IN
= 3.7 V
V
IN
= 5.5 V
−
50
0
+50 +100
Input voltage VIN (V)
MOS FET ON resistance RON ()
Operating ambient temperature Ta ( C)
P-ch MOS FET ON resistance RONP ()
Operating ambient temperature Ta ( C)
N-ch MOS FET ON resistance RONN ()
MOS FET
ON resistance vs. Input voltage P-ch MOS FET
ON resistance vs. Operating ambient temperature
N-ch MOS FET
ON resistance vs. Operating ambient temperature
Document Number: 002-09201 Rev. *A Page 27 of 45
MB39C006A
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Ta = +25°C
V
OUT
= 2.5 V
V
THHCT
V
THLCT
2.0 3.0 4.0 5.0 6.0
0
500
1000
1500
2000
2500
3000
2632
85
1053
−
50
0
+50 +100
0
500
1000
1500
2000
2500
3000
980
85
392
−
50
0
+50 +100
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Ta = +25°C
VOUT = 2.5 V
VTHLMD
VTHMMD
2.0 3.0 4.0 5.0 6.0
Input voltage VIN (V)
MODE VTH (V)
Input voltage VIN (V)
CTL VTH (V)
MODE VTH vs. Input voltage CTL VTH vs. Input voltage
Operating ambient temperature Ta ( C) Operating ambient temperature Ta ( C)
Power dissipation PD (mW)
Power dissipation vs.
Operating ambient temperature
(with thermal via)
Power dissipation vs.
Operating ambient temperature
(without thermal via)
Power dissipation PD (mW)
VTHHCT: circuit OFF ON
VTHLCT: circuit ON OFF
Document Number: 002-09201 Rev. *A Page 28 of 45
MB39C006A
■Switching waveforms
V
LX
: 2.0 V/div
V
OUT
:
20 mV/div (AC)
I
LX
: 500 mA/div
V
IN
= 3.7 V, I
OUT
= −20 mA, V
OUT
= 2.5 V, MODE = L, Ta = +25
°C
1 μs/div
1
2
4
VIN = 3.7 V, IOUT = −800 mA, VOUT = 2.5 V, MODE = L, Ta = +25
°C
ILX : 500 mA/div
VLX : 2.0 V/div
VOUT:
20 mV/div (AC)
1 μs/div
1
2
4
PFM/PWM operation
PWM operation
Document Number: 002-09201 Rev. *A Page 29 of 45
MB39C006A
■Output waveforms at sudden load changes (0 A↔ 800 mA)
■Output waveforms at sudden load changes ( 20 mA↔ 800 mA)
■Output waveforms at sudden load changes ( 100 mA 800 mA)
V
LX
: 2.0 V/div
V
OUT
:
200 mV/div
I
OUT
: 1 A/div
V
IN
= 3.7 V, V
OUT
= 2.5 V, MODE = L, Ta = +25
°C
−800 mA
0 A
100 μs/div
1
2
4
1
2
4
V
LX
: 2.0 V/div
V
OUT
:
200 mV/div
I
OUT
: 1 A/div
V
IN
= 3.7 V, V
OUT
= 2.5 V, MODE = L, Ta = +25
°C
−800 mA
− 20 mA
100 μs/div
2
4
V
LX
: 2.0 V/div
V
OUT
:
200 mV/div
I
OUT
: 1 A/div
V
IN
= 3.7 V, V
OUT
= 2.5 V, MODE = L, Ta = +25
°C
−800 mA
− 100 mA
100 μs/div
1
Document Number: 002-09201 Rev. *A Page 30 of 45
MB39C006A
■CTL start-up waveform
V
LX
: 5 V/div
CTL : 5 V/div
I
LX
:1 A/div
10 μs/div
V
OUT
: 1 V/div
V
IN
= 3.7 V, I
OUT
= 0 A, V
OUT
= 2.5 V, MODE = L, Ta = +25
°C
2
4
1
3
V
LX
: 5 V/div
CTL : 5 V/div
I
LX
:1 A/div
10 μs/div
V
OUT
: 1 V/div
V
IN
= 3.7 V, I
OUT
= −800 mA, (3.125 Ω) V
OUT
= 2.5 V,
MODE = L, Ta = +25
°C
2
4
1
3
V
LX
: 5 V/div
CTL : 5 V/div
I
LX
:1 A/div
10 ms/div
V
OUT
: 1 V/div
V
IN
= 3.7 V, I
OUT
= 0 A, V
OUT
= 2.5 V, MODE = L, Ta = +25
°C
2
4
1
3
V
LX
: 5 V/div
CTL : 5 V/div
I
LX
:1 A/div
10 ms/div
V
OUT
: 1 V/div
V
IN
= 3.7 V, I
OUT
= −800 mA, (3.125 Ω) V
OUT
= 2.5 V,
MODE = L, Ta = +25
°C
2
4
1
3
(No load, No VREFIN capacitor) (Maximum load, No VREFIN capacitor)
(No load, VREFIN capacitor 0.1 F) (Maximum load, VREFIN capa citor 0.1 F)
Document Number: 002-09201 Rev. *A Page 31 of 45
MB39C006A
■CTL stop waveform (No load, VREFIN capacitor 0.1 F)
■Current limitation waveform
VLX : 5 V/div
CTL : 5 V/div
ILX :1 A/div
10 μs/div
VOUT : 1 V/div
VIN = 3.7 V, IOUT = −800 mA, (3.125 Ω) VOUT = 2.5 V,
MODE = L, Ta = +25
°C
2
4
1
3
V
OUT
: 1 V/div
2.5 V
1.5 V
10 μs/div
l
LX
: 1 A/div
1.2 A
V
IN
= 3.7 V, I
OUT
= −600 mA (4.2 Ω) I
OUT
= −1.2 A (2.1 Ω) V
OUT
= 2.5 V, MODE = L,Ta = +25 °C
600 mA
1
2
4
V
POWERGOOD
: 1 V/div
Normal operat ion Current limitation
operation Normal operation
Document Number: 002-09201 Rev. *A Page 32 of 45
MB39C006A
■Waveform of dynamic output voltage transition (VO1 1.8 V 2.5 V)
VIN = 3.7 V, IO1 = −800 mA, −576 mA (3.125 Ω), MODE = L, Ta = +25 °C, VREFIN
1
VOUT : 200 mV/div
VVRFFIN : 200 mV/div
610 mV
840 mV
3
1.8 V
10 μs/div
2.5 V
No, VREFIN Capacitor
Document Number: 002-09201 Rev. *A Page 33 of 45
MB39C006A
12. Application Circuit Examples
■Application Circuit Example 1
❐An external voltage is input to the reference voltage external input (VREFIN) , and the VOUT voltage is set to 2.97 times as much
as the VOUT setting gain.
V
OUT
= 2.97 × V
REFIN
V
IN
CPU V
OUT
APLI
C2
C1
L1
R5
DAC
4.7 μF
4.7 μF
2.2 μH
1 MΩ
VDD
CTL
FSEL
VREF
VREFIN
GND
LX
OUT
POWER-
GOOD
MODE
L (OPEN) = 2.0 MHz
H = 3.2 MHz
10
3
5
9
1
6
4
7
2
8
L=PFM/PWM mode
OPEN=PWM fixed mode
Document Number: 002-09201 Rev. *A Page 34 of 45
MB39C006A
■Application Circuit Example 2
❐The voltage of VREF pin is input to the reference voltage external input (VREFIN) by the dividing resistors. The VOUT voltage is
set to 2.5 V.
■Application Circuit Example Comp onents List
TDK : TDK Corporation
FDK : FDK Corporation
KOA : KOA Corporation
Component Item Part Number Specification Package Vendor
L1 Inductor VLF4012AT-2R2M 2.2 H, RDC = 76 mSMD TDK
MIPW3226D2R2M 2.2 H, RDC = 100 mSMD FDK
C1 Ceramic
capacitor C2012JB1A475K 4.7 F (10 V) 2012 TDK
C2 Ceramic
capacitor C2012JB1A475K 4.7 F (10 V) 2012 TDK
R3 Resistor RK73G1JTTD D 7.5 k
RK73G1JTTD D 120 k7.5 k
120 k1608
1608 KOA
R4 Resistor RK73G1JTTD D 300 k300 k1608 KOA
R5 Resistor RK73G1JTTD D 1 M 0.51608 KOA
VOUT = 2.97 × VREFIN
VOUT = 2.97 ×
(VREF = 1.20 V)
VREFIN = R4
R3 + R4
R4
300 kΩ
VDD
CTL
FSEL
VREF
VREFIN GND
LX
OUT
POWER-
GOOD
MODE
10
3
5
9
1
6
4
7
2
L
(OPEN) = 2.0 MHz
R3 127.5 kΩ
H
= 3.2 MHz
VOUT
APLI
C1
L1 4.7 μF
2.2 μH
R3(120 kΩ + 7.5 kΩ)
CPU R5
1 MΩ
VIN
C2
4.7 μF
× VREF
× 1.20 V = 2.5
V
300 kΩ
127.5 kΩ + 300 kΩ
8
L=PFM/PWM mode
OPEN=PWM fixed mode
Document Number: 002-09201 Rev. *A Page 35 of 45
MB39C006A
13. Usage Precautions
1. Do not configure the IC over the maximum ratings
lf the lC is used over the maximum ratings, the LSl may be permanently damaged.
It is preferable for the device to normally operate within the recommended usage conditions. Usage outside of these conditions can
adversely affect reliability of the LSI.
2. Use the devices within recommended operating conditions
The recommended operating conditions are the conditions under which the LSl is guaranteed to operate.
The electrical ratings are guaranteed when the device is used within the recommended operating conditions and under the conditions
stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common impedance
4. Take appropriate static electricity measures.
■Containers for semiconductor materials should have anti-static protection or be made of conductive material.
■After mounting, printed circuit boards should be stored and shipped in cond uctive bags or containers.
■Work platforms, tools, and instruments should be properly grounded.
■Working personnel should be grounded with resistance of 250 k to 1 M between body and ground.
5. Do not apply negative voltages.
The use of negative voltages be low 0.3 V may create parasitic transistors on LSI lines, which can cause abnormal operation.
14. Ordering Information
15. RoHS Compliance Information of Lead (Pb) Free Version
The LSI products of Cypress with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium,
mercury, hexavalent chromium, polybrominated biphenyls (PBB), and polybrominated diphenylethers (PBDE).
A product whose part number has trailing characters “E1” is RoHS compliant.
Part number Package Remarks
MB39C006APN 10-pin plastic SON
(LCC-10P-M04)
Document Number: 002-09201 Rev. *A Page 36 of 45
MB39C006A
16. Labeling Sample (Lead Free Version)
17. Marking Format
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
The part number of a lead-free product has
the trailing characters “E1”.
Lead-free mark
JEITA logo JEDEC logo
“ASSEMBLED IN CHINA” is printed on the label
of a produc t assembled in China.
INDEX
Lead-free version
Document Number: 002-09201 Rev. *A Page 37 of 45
MB39C006A
18. Recommended Mounting Conditions of MB39C006APN
18.1 Cypress Recommended Mounting Conditions
18.2 Parameters for Each Mounting Method
18.2.1 IR (infrared reflow)
Item Condition
Mounting Method IR (infrared reflow), warm air reflow
Mounting times 2 times
Storage period Before opening Please use it within two years after
manufacture.
From opening to the 2nd
reflow
Storage conditi ons 5 C to 30 C, 70%RH or less (the lowest possible humidity)
260°C
(e)
(d')
(d)
255°C
170 °C
190 °C
RT (b)
(a)
(c)
~
H rank : 260 C Max
Note: Temperatu r e: the top of the package body
(a) Temperature Increase gradient : Average 1 C/s to 4 C/s
(b) Preliminary heating : Temperature 170 C to 190 C, 60s to 180s
(c) Temperature Increase gradient : Average 1 C/s to 4 C/s
(d) Actual heating : Temperature 260 C Max; 255 C or more, 10s or les s
(d’) : Temperature 230 C up 40s or le ss
or
Temperatu re 225 C up 60s or less
or
Temperatu re 220 C up 80s or less
(e) Cooling : Natural cooling or forced cooling
Document Number: 002-09201 Rev. *A Page 38 of 45
MB39C006A
19. Evaluation Board Specification
The MB39C006A Evaluation Board provides the proper environment for evaluating the efficiency and other characteristics of the
MB39C006A.
■Terminal information
■Startup terminal information
Symbol Functions
VIN
Power supply terminal.
In standard condition 3.1 V to 5.5 V*.
* When the VIN/VOUT diffe rence is to be held within 0.6 V or less, such as for devices with
a standard output voltage (VOUT 2.5 V) a nd VIN < 3.1 V, Cypress recommends to
change the output capacity (C1) to 10 F.
VOUT Output terminal.
VCTL Power supply terminal for setting the CTL terminal.
Use this terminal by connecting with VIN (When SW is mounted).
CTL Direct supply terminal of CTL.
CTL 0 V to 0.80 V (Typ) : Shutdown
CTL 0.95 V (Typ) to VIN : Normal operation
MODE Direct supply terminal of MODE.
MODE 0 V to 0.4 V (Max) : PFM/PWM mode
MODE OPEN (Remove R6) : PWM mode
VREF Reference voltage output terminal.
VREF 1.20 V (Typ)
VREFIN External reference voltage input terminal.
When an external reference voltage is supplied, connect to this terminal.
FSEL
Operating frequency range setting terminal.
FSEL 0 V : 2.0 MHz operation
FSEL VIN : 3.2 MHz operation*
* Cypress recommends to change the inductor to 1.5 H.
POWERGOOD POWERGOOD output terminal.
“High” level output when OUT voltage reaches 97% or more of output setting voltage .
PGND Ground terminal.
Connect power supply GND to the PGND terminal next to the VOUT terminal.
AGND Ground terminal.
Terminal name Condition Functions
CTL L : Open
H : Connect to VIN
ON/OFF switch for the IC.
L : Shutdown
H : Normal operation
FSEL L : Open
H : Connect to VIN
Setting switch of FSEL terminal.
L : 2.0 MHz operation
H : 3.2 MHz operation
Document Number: 002-09201 Rev. *A Page 39 of 45
MB39C006A
■Jumper information
■Setup and checkup
1. Setup
a. Connect the CTL terminal to the VIN terminal.
b. Connect the power supply terminal to the VIN terminal, and the power supply GND terminal to the PGND terminal. (Example of
setting power supply voltage : 3.7 V)
2. Checkup
Supply power to VIN. The IC is operating normally if VOUT 2.5 V (Typ).
■Component layout on the evaluation board (Top View)
JP Functions
JP1 Normally used shorted (0 )
JP2 Not mounted
VIN
PGND
VOUT
POWER_GOOD VREF VREFIN
AGND
CTL
FSEL
FSEL
CTL
SW1
VCTL
MODE
JP2
JP1
C2
C3
C1 R1
M1
L1
R8
R4
R3-2
R3-1
R6
OFF
12
MB39C006AEVB-06 Rev.2.0
Document Number: 002-09201 Rev. *A Page 40 of 45
MB39C006A
■Evaluation board layout (Top View)
Top Side (Layer1) Inner Side (Layer2)
Inner Side(Layer 3) Bottom Side(Layer 4)
Document Number: 002-09201 Rev. *A Page 41 of 45
MB39C006A
■Connection diagram
JP2
JP1
IIN
VIN
VOUT
L1
2.2 µH
R4
300 kΩ
R3-1
7.5 kΩ
C1
4.7 µF
C6
0.1 µF
VCTL
CTL
VREF
VREFIN
IOUT
MB39C006A
AGND
PGND
C2
4.7 µF
MODE
SW1-1
R5
1MΩ
R3-2
120 kΩ
8
3
4
7
2
5
9
1
10
CTL
MODE
VREF
VREFIN GND
OUT
POWER-
GOOD
LX
VDD
R1
1MΩ
6FSEL
SW1-2
FSEL
POWER-
GOOD
R6
* Not mounted
Document Number: 002-09201 Rev. *A Page 42 of 45
MB39C006A
■Component list
Note : These comp onents are recommended based on the operating tests authorized .
TDK : TDK Corporation
KOA : KOA Corporation
SSM : SUSUMU Co., Ltd
20. EV Board Ordering Information
Component Part Name Model Number Specification Package Vendor Remark
M1 IC MB39C006APN SON10 Cypress
L1 Inductor VLF4012AT-2R2M 2.2 H,
RDC=76 mSMD TDK
C1 Ceramic capacitor C2012JB1A475K 4.7 F (10 V) 2012 TDK
C2 Ceramic capacitor C2012JB1A475K 4.7 F (10 V) 2012 TDK
C6 Ceramic capacitor C1608JB1H104K 0.1 F (50 V) 1608 TDK
R1 Resister RK73G1JTTD D
1 M1 M 0.5% 1608 KOA
R3-1 Resister RR0816P-752-D 7.5 k 0.5% 1608 SSM
R3-2 Resister RR0816P-124-D 120 k 0.5% 1608 SSM
R4 Resister RR0816P-304-D 300 k 0.5% 1608 SSM
R5 Resister RK73G1JTTD D
1 M1 M 0.5% 1608 KOA
R6 Resister RK73Z1J 0 , 1A 1608 KOA
SW1 DIP switch 
Not
mounted
JP1 Jumper RK73Z1J 0 , 1A 1608 KOA
JP2 Jumper 
Not
mounted
EV Board Part No. EV Board Version No. Remarks
MB39C006AEVB-06 MB39C006AEVB-06 Rev.2.0 SON10
Document Number: 002-09201 Rev. *A Page 43 of 45
MB39C006A
21. Package Dimension
10-pin plastic SON Lead pitch 0.50 mm
Package width ×
package length 3.00 mm × 3.00 mm
Sealing method Plastic mold
Mounting height 0.75 mm MAX
Weight 0.018 g
10-pin plastic SON
(LCC-10P-M04)
(LCC-10P-M04)
C
2008 FUJITSU MICROELECTRONICS LIMITED C10004S-c-1-2
INDEX AREA
(.118±.004)
3.00±0.10
(.067±.004)
3.00±0.10
(.118±.004)
1.70±0.10
2.40±0.10
(.094±.004)
0.50(.020)
TYP
1PIN CORNER
(C0.30(C.012))
MAX
0.75(.030)
0.15(.006)
(.016±.004)
0.40±0.10
(.010±.001)
0.25±0.03
1 5
10 6
0.05(.002)
(.000 )
0.00
–0.00
+0.05
–.000
+.002
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Document Number: 002-09201 Rev. *A Page 44 of 45
MB39C006A
Document History
Spansion Publication Number: DS04-27245 -2E
Document Title: MB39C006A, 1 ch DC/DC Converter IC with PFM/PWM Synchronous Rectification Datasheet
Document Number: 002-09201
Revision ECN Orig. of
Change Submission
Date Description of Change
** - TAOA 11/21/2008 Migrated to Cypress and assigned document number 002-09201.
No change to document contents or format.
*A 5518137 TAOA 11/11/2016 Updated to Cypress template
Document Number: 002-09201 Rev. *A Revised November 11, 2016 Page 45 of 45
MB39C006A
© Cypress Semiconductor Corporation, 2008-2016. This document is the property of Cypr ess Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including an y so ftw ar e or fi rmw ar e incl u ded o r r efe r ence d i n thi s docu m ent ("Software"), is owned b y C yp re ss u nd er th e i nte lle ctua l p ro pe rt y law s and treaties of the Uni te d States and other countrie s
worldwide. Cypre ss re serv es all r ights u nd er such laws an d tr ea ties and does not, except as specifically stated in this paragraph, grant any licen se un de r i ts pa ten t s, co pyri ght s, tr ade m ar ks, or oth er
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distrib ute the So ftware in binar y code form externall y to end u sers
(either directl y or ind irectl y throu gh resel lers and distri buto rs ), solely for use on Cypr ess har dware pr oduct un it s, and (2) u nder th ose clai m s o f C yp re ss's p ate nts that are infringed by the Sof tw ar e (a s
provided by Cypre ss, unmodified) to m ake, use, distribute, an d import the Softw are solely for use with Cypress hardwa re products. Any other u se, repr oduction, modification, t ranslation, or compilation
of the Software is proh ibi ted.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WA RRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability ar ising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, i s provided only for reference purposes. It is
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered tr ademarks of Cypress in
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