Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 1 of 12
Key Feature s
- 10MHz Se rial Inter face
- Individu al LED Seg ment Control
- Decode/No-Decode Digit Selection
- 20µA Lo w-Power Shut down (Data Retained )
- Extremely low Ope rating Curr ent 0.5mA in open loo p
- Digital and Analog Bright ness Control
- Display Blanked on Power-Up
- Drive Common-C athode LED Display
- Software Reset1
- Optional Ex ternal clock
- 24-Pin DIP and SO Packages
- Fully compatible to MAX7219
General Des cription
The AS1100 is an LED driver for 7 segment numeric
displays of up to 8 digits. The AS1100 can be programmed
via a conventional 4 wire serial interface. It includes a BCD
code-B decoder, a multiplex scan circuitry, segment and
display d rivers and a 64 Bit memory. The memo ry is used to
store the LED setti ngs, so that continuous reprogramming is
not necessary.
1 Software Reset and external clock are not supported by
MAX7219
Every individual segment can be addressed and updated
separately. Only one external resistor is required to set the
current through the LED display. Brightness can be
controlled either in an analog or digital way. The user can
choose the internal code-B decoder to display numeric
digits or to address each segment directly. The AS1100
features an extremely low shutdown current of only 20µA.
and an operational current of less than 500µA. The number
of visible digits can be programmed as well. The AS1100
can be reset by soft ware and an external clock can be used.
Several t est modes s upport easy debugging.
The AS1100 is fully compatible to the MAX 7219. AS1100 is
offered i n a 24 pins PDIP and SOI C package.
Applications
- Bar-Grap h Displays
- Industri al Cont rollers
- Panel Meters
- LED Matrix Displays
- White Goods
Serially In terfaced, 8-Digit LED Driver
AS1100 DATA SH EET
8-Digit µP Display
8 Segments
8 Digits
9.53k
+5V
MOSI
µP I/O
SCK
LOAD
CLK
GND GND
DIG0-DIG7
SEG A-G
SEP DP
VDD
4
9
1
12
1
18
19
ISET
DIN
Pin Confi
g
uration Typical Application Circuit
AS1100
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIP/SO 24
DIN
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
GND
GND
LOAD
DOUT
VDD
ISET
CLK
SEG A
SEG B
SEG C
SEG D
SEG E
SEG F
SEG G
SEG D P
TOP
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 2 of 12
Absolu te Maximum Ratings
Voltage (with r espect to G ND)
VDD -0.3V to 6 V
DIN, CLK, LOAD -0.3V to 6V
All Other Pins -0.3V to (VDD + 0.3V)
Current
DIG0–DIG 7 Sink Curre nt 500mA
SEGA–G, DP Sou rce Current 100mA
Continuous Power Dissipation (TA = +85°C)
Narrow Plastic DIP (derate 13.3mW/°C above
+70°C 1066mW
Wide SO ( derate 11.8 mW/°C above +7 0°C) 941mW
Operating Temperatur e Ranges (TMIN to TMAX)
AS1100xL 0°C to +70°C
AS1100xE -40°C to +85°C
Storage Temperature Ran ge -65°C to +150°C
Package b ody tempe rature 2+240°C
Electrical Ch aracteristics
(VDD = 5V, RSET = 9 .53kΩ±1%, TA = TMIN to TMAX, unless otherwise noted.)
Parameter Symbol Conditions Min Typ Max Units
Operatin g Supply Volta ge VDD 4.0 5.0 5.5 V
Shutdo wn Supply Cu rrent IDDSD All di gital inputs at VDD or G ND, TA =
+25°C 20 50 µA
RSET = open ci rcuit 500 µA
Operatin g Supply Cu rrent IDD All segm ents and dec imal point on , ISEG = -
40mA 330 mA
Display Scan Rate fOSC 8 digits s canned 500 800 1300 Hz
Digit Drive Sink Current IDIGIT VOUT = 0.65V 320 mA
Segment Drive Sourc e Current ISEG TA = +25°C, VOUT = (VDD -1V) -30 -40 -45 mA
Segment Drive Curr ent
Matching ∆ISEG 3.0 %
Digit Drive Sourc e Current IDIGIT Digit o ff, VDIGIT = (VDD -0.3 V) -2 mA
Segment D rive Sink Cur rent ISEG Segment of f, VSEG = 0 .3V 5 mA
Logic Inputs
2 The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020B “Moisture/Reflow Sensitivity
Classification for non-hermetic Solid State Surface Mount Devices”.
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 3 of 12
Parameter Symbol Conditions Min Typ Max Units
Input Current DIN, CLK, LOAD IIH, IIL VIN = 0V or V DD -1 1 µA
Logic High Input Voltage VIH 3.5 V
Logic Low Input Volt age VIL 0.8 V
Output High Voltage VOH DOUT, ISOURCE = -1mA VDD - 1 V
Output Low Voltage VOL DOUT, ISINK = 1.6mA 0.4 V
Hysteresis Voltage VIDIN, CLK, LOAD 1 V
Timing Characteristics
CLK Clock Peri od tCP 100 ns
CLK Pulse Width High tCH 50 ns
CLK Pulse Width Low tCL 50 ns
CLK Rise to LOAD Rise Hold
Time tCSH 0ns
DIN Setup T ime tDS 25 ns
DIN Hold Time tDH 0ns
Output Dat a Propagati on Delay tDO CLOAD = 50 pF 25 ns
LOAD Risi ng Edge to Next
Clock Rising Edge tLDCK 50 ns
Minimu m LOAD Pulse High tCSW 50 ns
Data-to-Segment Delay tDSPD 2.25 ms
Pin Descripti on
Pin Name Function
1 DIN Data inp ut. Data is programme d into the 16Bit shift register on the risin g CLK edge
2, 3, 5–8, 10,
11 DIG 0–DIG 7 8 digit driver lines that sink t he current from the com mon cathod e of the dis play.
In shutd own mode the AS 1100 switc hes the outp uts to VDD
4, 9 GND both GND pi ns must b e connected
12 LOAD Strobe i nput. With t he rising ed ge of the LOA D signal t he 16 bit of serial dat a is latche d into
the register.
13 CLK Clock i nput. The i nterface is capable t o support clock freq uencies up t o 10MHz. T he serial
data is c locked int o the internal shift re gister with the risin g edge of th e CLK signal. On the
DOUT pin the data is applied with the falling edge of CLK.
14–17, 20–23 SEG A–G,
DP Seven segment driver lines including the decimal point. When a segment is turned off the
output is c onnected t o GND.
18 ISET The cu rrent into I SET determi nes the p eak current through th e segments and therefo re the
brightness.
19 VDD Positive Supply Voltage (+5V)
24 DOUT Serial data output for cascading drivers. The output is valid after 16.5 clock cycles. The
output is never set t o high imped ance.
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 4 of 12
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X Address MSB D ata LSB
Tabl e 1: S erial data fo rmat (16 b its)
Detailed Description
Serial-Addressing Modes
Programming of the AS1100 is done via the 4 wire serial
interface. A programming sequence consists of 16-bit
packages. The data is shifted into the internal 16 Bit
register with the rising edge of the CLK signal. With the
rising edge of the LOAD signal the data is latched into a
digital or control register depending on the address. The
LOAD signal must go to high after the 16th rising clock
edge. The LOAD signal can also come later but just before
the next rising edge of CLK, otherwise data would be lost.
The content of the internal shift register is applied 16.5
clock cycles later to the DOUT pin. The data is clocked out
at the falling edge of CLK. The Bits of the 16Bit-
programming package are described in table 1. The first 4
Bits D15-D12 are ”don’t care, D11-D8 contain the address
and D7-D0 contain the data. The first bit is D15, the most
signific ant bit (MSB) . The exact ti ming is given in figur e 1.
Digit and Control Registers
The AS1100 incorporates 15 registers, which are listed in
Table 2. The digit and control registers are selected via the
4Bit address word. The 8 digit registers are realized with a
64bit memory. Each digit can be controlled directly without
rewriting the whole contents. The control registers consist
of decode mode, display intensity, number of scanned
digits, shutdown, display test and reset/external clock
register.
Shutdown Mode
The AS1100 features a shutdown mode, where it consumes
only 20µA current. The shutdown mode is entered via a
write to register 0Ch. Then all segment current sources are
pulled to ground and all digit drivers are connected to VDD,
so that nothing is displayed. All internal digit registers keep
the programmed values. The shutdown mode can either be
used for power saving or for generating a flashing display
by repeatedly entering and leaving the shutdown mode. The
AS1100 needs typically 250µs to exit the shutdown mode.
During shutdown the AS1100 is fully programmable. Only
the display test function overrides the shutdo wn mode.
Initial Powe r-Up
After powering up the system all register are reset, so that
the display is blank. The AS1100 starts the shutdown mode.
All registers should be programmed for normal operation.
The default settings enable only scan of one digit, the
internal decoder is disabled, data register and intensity
regist er are set t o the minim um value.
Figure 1: Timing diagram
LOAD
CLK
DIN
DOUT
tDS
tDH
tCL tCH
D15 D14 D1 D0
tDO
tCP
tCS tLDCK
tCSW
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 5 of 12
Decode-Mode Register
In the AS1100 a BCD decoder is included. Every digit can
be selected via register 09h to be decoded. The BCD code
consists of the numbers 0-9, E,H, L,P and -. In register 09h
a logic high enables the decoder for the appropriate digit. In
case that the decoder is bypassed (logic low) the data Bits
D7-D0 correspond to the segment lines of the AS1100. In
table 4 some possible settings for register 09h are shown.
Bit D7, which corresponds to the decimal point, is not
affected by the settings of the decoder. Logic high means
that the decimal point is displayed. In table 5 the font of the
Code B decoder is shown. In table 6 the correspondence of
the register to the appropriate segments of a 7 segment
display is shown (s ee figure 2)
Intensity Control and Interdigit Blanking
Brightness of the display can be con trolled in an analog way
by changing the external resistor (RSET). The current, which
flows between VDD and ISET, defines the current that flows
through the LEDs. The LED current is 100 times the ISET
current. The minimum value of RSET should be 9.53kΩ,
which corresponds to 40mA segment current. The
brightness of the display can also be controlled digitally via
register 0Ah. The brightness can be programmed in 16
steps and is shown in table 7. An internal pulse width
modulato r controls the intens ity of the display.
Scan-Limi t Register
The scan limit register 0Bh selects the number of digits
displayed. When all 8 digits are displayed the update
frequency is typically 800Hz. If the number of digits
displayed is reduced, the update frequency is reduced as
well. The frequency can be calculated using 8fOSC/N,
where N is the number of digits. Since the number of
displayed digits influences the brightness, the resistor RSET
should be adjusted accordingly. Table 9 shows the
maximum allowed current, when fewer than 4 digits are
used. To avoid differences in brightness the scan limit
register should not be used to blank portions of the display
(leadi ng zeros) .
Address
Register D15–D12 D11 D10 D9 D8 Hex
Code
No-Op X 0 0 0 0 0xX0
Digit 0 X 0 0 0 1 0xX1
Digit 1 X 0 0 1 0 0xX2
Digit 2 X 0 0 1 1 0xX3
Digit 3 X 0 1 0 0 0xX4
Digit 4 X 0 1 0 1 0xX5
Digit 5 X 0 1 1 0 0xX6
Digit 6 X 0 1 1 1 0xX7
Digit 7 X 1 0 0 0 0xX8
Decode
Mode X 1 0010xX9
Intensity X 1 0 1 0 0xXA
Scan Limit X 1 0 1 1 0xXB
Shutdown X 1 1 0 0 0xXC
Not used X 1 1 0 1 0xXD
Reset a nd
ext. Cloc k X11100xXE
Display
Test X11110xXF
Tabl e 2: Register addre ss map
Register Data
Mode Address Code
(Hex) D7 D6 D5 D4 D3 D2 D1 D0
Shutdown
Mode 0xXC XXXXXXX0
Normal
Operation 0xXC XXXXXXX1
Tabl e 3: S hutdo wn reg ister form at (addr ess ( hex) = 0xXC)
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 6 of 12
Register Data
Decode Mode D7 D6 D5 D4 D3 D2 D1 D0 Hex Cod e
No decode for digits 7–0 00000000 0x00
Code B dec ode for di git 0
No decode for digits 7–1 00000001 0x01
Code B decode for digits
3–0
No decode for digits 7–4 00001111 0x0F
Code B decode for digits
7–0 11111111 0xFF
Tabl e 4: D ecode- mod e reg ister exampl es (a ddres s (he x) = 0xX9)
Register Data On Segments = 17-Segment
Character D7* D6–D4 D3 D2 D1 D0 DP* A B C D E F G
0 X 0000 1111110
1 X 0001 0110000
2 X 0010 1101101
3 X 0011 1111001
4 X 0100 0110011
5 X 0101 1011011
6 X 0110 1011111
7 X 0111 1110000
8 X 1000 1111111
9 X 1001 1111011
— X 1010 0000001
E X 1011 1001111
H X 1100 0110111
L X 1101 0001110
P X 1110 1100111
blank X 1111 0000000
Table 5: Cod e B font
*The dec imal poi nt is s et by bit D7 = 1
Register Data
D7 D6 D5 D4 D3 D2 D1 D0
Corresponding
Segment Line DP A B C D E F G
Table 6: No-decode mode data bits and corr esponding segment lines
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 7 of 12
Duty C ycle D7 D6 D5 D4 D3 D2 D1 D0 Hex Cod e
1/32 (min on) XXXX 00 00 0xX0
3/32 XXXX0001 0xX1
5/32 XXXX0010 0xX2
7/32 XXXX0011 0xX3
9/32 XXXX0100 0xX4
11/32 XXXX0101 0xX5
13/32 XXXX0110 0xX6
15/32 XXXX0111 0xX7
17/32 XXXX1000 0xX8
19/32 XXXX1001 0xX9
21/32 XXXX1010 0xXA
23/32 XXXX1011 0xXB
25/32 XXXX1100 0xXC
27/32 XXXX1101 0xXD
29/32 XXXX1110 0xXE
31/32 (max on)XXXX 1 111 0xXF
Tabl e 7: In tensit y reg ister f ormat (addr ess (h ex) = 0xXA)
Register Data
Scan Limit D7 D6 D5 D4 D3 D2 D1 D0 Hex Co de
Display di git 0 only X X X X X 0 0 0 0xX0
Display digits 0 & 1 X X X X X 0 0 1 0xX1
Display di gits 0 1 2 X X X X X 0 1 0 0xX 2
Display di gits 0 1 2 3 X X X X X 0 1 1 0xX3
Display di gits 0 1 2 3 4 X X X X X 1 0 0 0xX4
Display di gits 0 1 2 3 4 5 X X X X X 1 0 1 0x X5
Display di gits 0 1 2 3 4 5
6XXXXX110 0xX6
Display di gits 0 1 2 3 4 5
6 7 XXXXX111 0xX7
Tabl e 8: Sc an-lim it reg ister format (addr ess ( hex) = 0xXB)
Figure 2: Standard 7-segment LED
DP
A
F
E
D
B
C
G
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 8 of 12
Display T est Regis ter
With the display test register 0Fh all LED can be tested. In
the test mode all LEDs are switched on at maximum
brightness (duty cycle 31/32). All programming of digit and
control registers is maintained. The format of the register is
given in table 10.
Number of
Digits
Displayed
Maximum
Segment Current
(mA)
110
220
330
Tabl e 9: Maxim um segme nt current for 1-, 2-, or 3-d igit displa ys
Register Data
Mode D7 D6 D5 D4 D3 D2 D1 D0
Normal OperationXXXXXXX 0
Display Test
Mode XXXXXXX1
Table 10: Display-test register format (address (hex) = 0xXF)
Note : The AS1100 remains in display-test mode until the
display-test register is reconfigured for normal operation.
No-Op Register (Ca scading o f As1100)
The no-operation register 00h is used when AS1100s are
cascaded in order to support more than 8 digit displays. The
cascading must be done in a way that all DOUT are
connected to DIN of the following AS1100. The LOAD and
CLK signals are connected to all devices. For a write
operation for example to the fifth device the command must
be followed by four no-operation commands. When the
LOAD signal finally goes to high all shift registers are
latched. The first four devices have got no-operation
commands and only the fifth device sees the intended
command and updates i ts registe r.
Reset an d external Clock Regi ster3
This re gister is a ddressed vi a the se rial interfac e. It allo ws
to switc h the device to extern al clock mod e (If D0= 1 the
CLK pin of the serial int erface operates as syste m clock
input.) and to apply an external reset (D 1). This bri ngs all
regist ers (excep t reg. E) to default sta te. For sta ndard
operati on the regis ter contents should b e "00h".
3 This register is not used by MAX7219, since it does not support
software reset and external clocks
Register Data
Mode Address
code (hex) D7 D6 D5 D4 D3 D2 D1 D0
Normal O peration,
internal c lock 0xXE XXXXXX00
Normal O peration,
external c lock 0xXE XXXXXX01
Reset state,
internal c lock 0xXE XXXXXX10
Reset state,
external c lock 0xXE XXXXXX11
Table 11: Reset and external Clock register (address (hex) = 0xXE)
Applications Information
Supply Bypassing and Wiring
In order to achieve optimal performance the AS1100 shall
be placed very close to the LED display to minimize effects
of electromagnetic interference and wiring inductance.
Furthermore it is recommended to connect a 10µF
electrolytic and a 0.1µF ceramic capacitor between VDD
and GND to avoid power supply ripple. Also, both GNDs
must be c onnected t o ground.
Selecting RSET Resistor and Using External Drivers
The current through the segments is controlled via the
external resistor RSET. Segment current is about 100 times
the current in ISET. The right values for ISET are given in
table 12. The maximum current the AS1100 can drive is
40mA. If higher currents are needed, external drivers must
be used. In that case it is no longer necessary that the
AS1100 drives high currents. A recommended value for
RSET is 47kΩ. In cases that the AS1100 only drives few
digits table 9 specifies t he maximum currents and RSET must
be set accordingly. Refer to absolute maximum ratings to
calculate acceptable limits for ambient temperature,
segment c urrent, an d the LED for ward-volta ge drop.
VLED (V)
ISEG (m A) 1.5 2.0 2.5 3.0 3.5
40 12.2 11.8 11.0 10.6 9.69
30 17.8 17.1 15.8 15.0 14.0
20 29.8 28.0 25.9 24.5 22.6
10 66.7 63.7 59.3 55.4 51.2
Tabl e 12: RSET vs. seg ment current and LE D for ward volt age
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 9 of 12
8x8 LED Dot Matrix Driver
The example in Figure 3 uses the AS1100 to drive an 8x8 LED dot matrix. The LED columns have common cathode
and are connected to the DIG0-7 outputs. The rows are connected to the segment drivers. Each of the 64 LEDs can
be addressed separately. The columns are selected via the digits as shown in Table 2. The decode mode register
(0xX9) has to be programmed to ‘00000000’ as stated in Table 4. The single LEDs in a column can be addressed as
stated in Table 6, where D0 corresponds to segment G and d/ to segment DP. For a multiple digit dot matrix several
AS1100 have to be cascaded.
Cascadin g Drivers
The AS110 0 can be cas caded as well. The DOUT pin must be connect ed to the DIN pin o f the followi ng AS1100.
Package Therm al Resistance (θ
θθ
θJA)
24 Narrow DIP +75°C/W
24 Wide SO +85°C/W
Maximum J unction T emperature (T J) = +150°C
Maximum A mbient Te mperature (T A) = +85°C
Table 13: Package thermal resistance data
Figure 3: Application example as LED dot matrix driver
µP
DIG 7
8x8 LED Dot
Mti
9.53k
VBAT
LOA
CLK
GND GND
DIG 0-SEG A-G
SEP DP
VDD
4
9
1
12
1
18
19
ISET
DIN
DIG 0
SEG B
SEG A
SEG DP
SEG E
SEG D
SEG C
SEG F
SEG G
8x8 LED Dot
Mti
9.53k
VBAT
LOA
CLK
GND GND
DIG 0-SEG A-G
SEP DP
VDD
4
9
1
12
1
18
19
ISET
DIN
DIG 0
SEG B
SEG A
SEG DP
SEG E
SEG D
SEG C
SEG F
SEG G
DIG 7
DOUT
24
Diode Arrangement
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 10 of 12
Computing Power Dissipation
The uppe r limit fo r power diss ipation (P D) for the AS1100 is d etermined fr om the follo wing equa tion:
PD = (V DD x 0.5mA ) + (VDD - VLED)(DUTY x ISEG x N)
where: VDD = supply voltage
DUTY = duty cycle set by intensity register
N = numbe r of segme nts drive n (worst cas e is 8)
VLED = LED fo rward volt age
ISEG = se gment current s et by RSET
Dissipati on Example :
ISEG = 40mA, N = 8, DUTY = 31/32, VLED = 1.8V at 40mA, VDD = 5 .25V
PD = 5.25V (0.5mA) + (5 .25V - 1.8V )(31/32 x 40mA x 8) = 1 .07W
Thus, f or a PDIP pack age θJA = +75°C /W (from Tabl e 13), th e maximum all owed ambien t temperatu re TA is given by:
TJ,MAX = TA + PD x θJA = 150°C = TA + 1.07W x 75° C/W.
where TA = +69.7°C.
The TA li mit for SO Packages in t he dissipati on exampl e above is +5 9.0°C.
Package Info rmation
Inches Millimeters
Dim Min Max Min Max
A 0.093 0.104 2.35 2.65
A1 0.004 0.012 0.10 0.30
B 0.014 0.019 0.35 0.49
C 0.009 0.013 0.23 0.32
D 0.598 0.614 15.20 15.60
e 0.050 1.27
E 0.291 0.299 7.40 7.60
H 0.394 0.419 10.00 10.65
L 0.016 0.050 0.40 1.27
Figure 4: SOIC-24 package dimensions
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 11 of 12
Inches Millimeters
Dim Min Max Min Max
A --- 0.180 --- 4.572
A1 0.015 --- 0.380 ---
A2 0.125 .0175 3.180 4.450
A3 0.055 0.080 1.400 2.030
B 0.015 0.022 0.381 0.560
B1 0.045 0.065 1.140 1.650
C 0.008 0.014 0.200 0.355
D 1.140 1.265 28.96 32.13
D1 0.005 0.080 0.130 2.030
E 0.300 0.325 7.620 8.260
E1 0.240 0.310 6.100 7.870
e 0.100 BSC 2.54 BSC.
eA 0.300 BSC 7.62 BSC.
eB 0.400 BSC 10.2 BSC.
L 0.115 0.150 2.921 3.810
Figure 5: PDIP-24 package dimensions
Figure 6: Segment driver capability
00.5 11.5 22.5 33.5 44.5
0
5
10
15
20
25
30
35
40
45
50 Segment Driver Capability, VDD = 5V, Logic Level = High
Vol t age below VDD at out put i n V
Segment Current in m A
Lower Limit
Upper Lim i t
Data Sheet AS1100
Revision 1.32, Oct. 2004 Page 12 of 12
Ordering Information
Part Temp Range Pin
Package Delivery
Form
AS1100PL 0°C to +70°C 24 Narrow
Plastic DIP Tubes
AS1100WL 0°C to + 70°C 24 Wide SO T ubes
AS1100PE -40°C to +85°C 24 Narrow
Plastic DIP Tubes
AS1100WE -40°C to +85°C 24 Wide SO T ubes
AS1100WL-T 0°C to +70°C 24 Wi de SO T&R
AS1100WE-T -40°C to + 85°C 24 Wi de SO T&R
For Pb-f ree packa ge use suffi x ‘-Z‘
Contact
austriamicrosystems AG
A 8141 Sc hloss Premst ätten, Austri a
T. +43 (0) 3136 500 0
F. +43 (0) 3136 525 01
info@austriamicrosystems.com
Copyright
Copyrigh t © 2004 austriamic rosystems. T rademarks
regist ered ®. All rights res erved. T he material herein m ay
not be re produced, adapted, m erged, transl ated, stor ed, or
used with out the p rior writ ten consent of the copy right
owner. To the best of its knowledge, austriamicrosystems
asserts th at the info rmation co ntained in t his public ation is
accurate and correct.
Austriamicrosystems reserves the right to change the circuitry and
specifications without notice at any time.
Figure 7: Segment Current versa RSET
10
1
10
2
0
5
10
15
20
25
30
35
40
45
50 S egment Current = f(R
SET
)
R
SET
in kOhm
I
SEGMENT
in mA
