SEEQ 28C64 Technology, Incorporated TI / } ler E: 2 July 1991 Features @ Military, Extended and Commercial Temperature @ Power Up/Down Protection Circuitry Range M 200 ns Maximum Access Time -55C to +125C Operation (Military) 40C to +85C Operation (Extended) @ JEDEC Approved Byte Wide Pinout 0C to +70C Operation (Commercial) MIL 883 Class B Complaint @ CMOS Technology MIL SMD 5962 Complaint lm Low Power 50 mA Active * 200 yA Standby Description @ Page Write Mode SEEQ's 28C64 is a CMOS 5V only, 8K x 8 Electrically + 64 Byte Page Erasable Programmable Read Only Memory (EEPROM). It 160 us Average Byte Write Time is manufactured using SEEQ's advanced 1.25 micron Byte Write Mode M Write Cycle Completion indication DATAPolling Pin Configuation @ On-Chip Timer DUAL-IN-LINE LEADLESS CHIP CARRIER + Automatic Erase Before Write TOP VIEW TOP VIEW EB High Endurance * 10,000 Cycles/Byte Minimum 10 Year Data Retention Block Diagram Row ADORESS DECODER Row A 12 ADORESS LATCHES COLUMN ADDRESS os teenies Note: The PLCC has the same pin configuration as the LCC except pins 1 and 17 are don't connects. LATCH ENABLE EDGE Pin Names 64 BYTE PAGE GUFFER cE | DETECTION wee}| 2. ASA, ADDRESSESCOLUMN A,-A,, | ADDRESSESROW CE CHIP ENABLE OE _VO BUFFER __ DATA POLLING OE OUTPUT ENABLE WE WRITE ENABLE v0, DATA INPUT (WRITEVDATA s OUTPUT (READ) NC NO CONNECTION Q Cell is a trademark of SEEQ Technology, Inc. SEEQ Technelegy, ncorperated 1-33 MD400106/ACMOS Process and is available in most Thru Hole and Surface Mount Package options as listed under Ordering Information. The 28C64 is ideal for applications which require low power consumption, non-volatility and in sys- tem reprogrammability. The endurance, the number of times a byte can be written, is specified at 10,000 cycles per byte and, is typically 1,000,000 cycles per byte. The extraordinary high endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and its innovative Q Cell design. System reliability, in all appli- cations, is higher because of the low failure rate of the Q Cell. The 28C64 has aninternal timer which automatically times out the write time. The on-chip timer, along with input latches free the microprocessor for other tasks while the partis busy writing. The 28C64s write cycle time is 10 ms. Anautomatic erase is performed before a write. The DATA polling feature of the 28C64 can be used to determine the end of a write cycle. Once the write cycle has been completed, datacan be readin a maximum of 200 ns. Data retention is specified for 10 years. Device Operation Operational Modes There are five operational modes (see Table1 )and, except for the chip erase mode, only TTL inputs are required. A Write can only be initiated under the conditions shown. Any other conditions for CE, OE, and WE will inhibit writing and the /O lines will either be in a high impedance state or have data, depending on the state of aforementioned three input lines. Mode Selection Mode CE | OF | WE vo Read Viv Vie Via Dour Standby Vig xX X High Z Write Vi Via Vi Diy Write X Vi X High Z/D,,, Inhibit X X Vin | High Z/D,,, Chip Erase | V,, Va Vi xX X: Any TTL level V,,: High Voltage Reads A read is accomplished by presenting the address of the desired byte to the address inputs. Once the address is stable, CE is brought to a TTL low in order to enable the chip. The WE pin must be at a TTL high during the entire 28C64 read cycle. The output drivers are made active by bringing Output Enable (OE) to a TTL low. During read, the address, CE ,OE, and /O latches are transparent. Writes To write into a particular location, the address must be valid and a TTL low applied to the Write Enable (WE) pin of a selected (CE low) device. This combined with Output Enable (OE) being high, initiates a write cycle. During a write cycle, all inputs except data are latched on the falling edge of WE or CE, whichever occurred last. Write enable needs to be at a TTL low only for the specified typ time. Data is latched on the rising edge of WE or CEwhichever occurred first. An automatic erase is performed before data is written. Write Cycle Control Pins For system design simplification, the 28C64 is designed such that either the CE or WE pin can be used to initiate a write cycle. The device uses the latest high-to-low transi- tion of either CE or WE signal to latch addresses and the earliest low-to-high transition to latch the data. Address and OE setup and hold are with respect to the later of CE or WE: data setup and hold is with respect to the earlier of WE or CE. To simplify the following discussion, the WE pin is used as the write cycle control pin throughout the rest of this data sheet. Timing diagrams of both write cycles are included in the AC Characteristics. Write Mode One to 64 bytes of data can be randomly loaded into the page. The partlatches row addresses, A6-A12, during the first byte write. These addresses are latched on the falling edge of the WE signal and are ignored after that until the end of the write cycle. This will eliminate any false write into another page if different row addresses are applied and the page boundary is crossed. The column addresses, AO-A5, which are used to select different locations of the page, are latched every time a new write is initiated, These addresses and the OE state (high) are latched on the falling edge of WE signal. For proper write initiation and latching, the WE pin has to stay low for a minimum of typ, ns. Data is latched on the rising edge of WE, allowing easy microprocessor interface. Upon a low to high WE transition, the 28C64 latches data and starts the internal page load timer, The timer is reset on the falling edge of the WE signal if another write is initiated before the timer has timed out. The timer stays SEE Technology. incorperatnd MD400106/Areset while the WE pin is kept low. If no additional write cycles have been initiated within t,,, after the last WE low to high transition, the part terminates the page load cycle and starts the internal write. During this time which takes a maximum of 10 ms, the device ignores any additional write attempts. The part can be read to determine the end of write cycle (DATA polling). Extended Page Load In order to take advantage of the page mode's faster average byte write time, data must be loaded at the page load cycle time (t,,,). Since some applications may not be able to sustain transfers at this minimum rate, the 28C64 permits an extended page load cycle. To do this, the write cycle must be stretched by maintaining WE low, assuming a write enable-controlled cycle, and leaving all other control inputs (CE, OE) in the proper page load cycle state. Since the page load timer is reset on the falling edge of WE, keeping this signal low will not start the page load timer. When WE returns high, the input data is latched and the page load cycle timer begins. In CE controlled write the sameistrue, with CE holding the timer reset instead oMWE. DATA Polling The 28C64 has a maximum write cycle time of 10 ms. Typically though, a write will be completed in less than the specified maximum cycle time. DATA polling is a method of minimizing write times by determining the actual end- point of a write cycle. if aread is performed to any address while the 28C64 is still writing, the device will present the ones-complement of the last byte written. When the 28C64 28C64 has completed its write cycle, a read from the last address written will result in validdata. Thus, softwarecan simply read from the part until the last data byte written is read correctly. A DATA polling read can occur immediately after a byte is loadedinto a page, prior to the initation of the internal write cycle. DATA polling attempted during the middle of a page load cycle will present a ones complement of the most recent data byte loaded into the page. Timing fora DATA polling read is the same as a normal read. Chip Erase Certain applications may require all bytes to be erased si- multaneously. This feature, which requires high voltage, is optional and timing specifications are available from SEEQ. Power Up/Down Considerations There is internal circuitry to minimize a false write during power up or power down. This circuitry prevents writing under any one of the following conditions. 1. Veo is less than VV. __ 2. A high to low Write Enable (WE) transition has not occurred when the V,.. supply is between V,,V and Vg with CE low and OE high. Writing will also be inhibited when WE, CE, or OE are in TTL logical states other than that specified for a write inthe Mode Selection table. SEEQ Technetegy, Incerperated 1-35 MD400106/AAbsolute Maximum Stress Ratings* Temperature SHOLAGO oo ceesscsscecsssscsstersssstssesetassasese Under Bias Military/Extended Temperature ..~65C to +135C Commercial Temperature -10C to +80C -65C fo +150C D.C. Voltage applied to all Inputs or Outputs with respect to ground +6.0Vto-05V Undershoot pulse of less than 10 ns (measured at 50% point) applied to all inputs or outputs with respect to ground Recommended Operating Conditions 28C64 Overshoot pulse of less than 10 ns (measured at 50% point )applied to all inputs or outputs With reSPeCt tO QFOUNG ...escereseesecssserssssssesssseses "COMMENT: Stresses beyond those listed under Abso- lute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional op- eration of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. MD400106/A 28C64-200 28C64-250 28C64-300 28C64-350 Temperature Commercial 0C to +70 0C to +70 0C to +70 0C to +70 Range Extended 40C to +85C | -40C to +85C | -40C to +85C | ~40C to +85C Military 55C to +125C | -55C to +125C | -55C to +125C | -55C to +125C Voc Supply Voltage 5V+10% 5V410% 5V+10% 5V110% Endurance and Data Retention Symbol Parameter Value Units Condition N Minimum Endurance 10,000 Cycles/Byte MIL-STD 883 Test Method 1033 Tor Data Retention >10 Years MIL-STD 883 Test Method 1008 SEEQ Techn elegy, incerpersiad 1-3628C64 DC Characteristics (Over operating temperature and V,,, range, unless otherwise specified) Limits Symbol Parameter Min. Max. Units Test Condition lee Active V.,. Current Mil. /Extended 60 mA CE = OE =V, : All /O Open; Other Inputs = V,, Max; Max read or write cycle time Commercial 50 mA CE = OE =V,: All VO Open; Other Inputs = V,, Max; Max read or write cycle time leas Standby V,,. Current 2 mA CE = V,,, OE = V,,; All /O Open; (TTL Inputs) Other Inputs = Any TTL Level lene Standby V,, Current (CMOS Inputs) Mil./Extended 250 HA CE = V,, -0.3 Other Inputs = V,, to V,, All /O Open Commercial 200 pA CE = V,, -0.3 Other Inputs = V,, to V,, All VO Open 1!) Input Leakage Current 1 HA Vin = Veg Max. lor Output Leakage Current 10 pA Vour = Veco Max. Vi Input Low Voltage -0.3 0.8 Vv Vin Input High Voltage 2.0~ 6 V Vor Output Low Voltage 0.45 Vv I = 2.1 mA Vou Output High Voltage 2.4 v log = 400 LA Vow Write inhibit Voltage 3.8 V Notes: 1. Characterized. Not tested. 2. Inputs only. Does not include VO. SEEQ Technology, incorporated 1-37 MD400106/A SEE 28C64 Capacitance!" T, = 25C, f = 1 MHz A.C. Test Conditions Symbol | Parameter Max Conditions Output Load: 1 TTL gate and C, = 100 pF C Input G it 6 oF V.= OV Input Rise and Fall Times: < 10 ns IN npmapact ance P w= 0 Input Pulse Levels: 0.45 V to 2.4 V Cour Data (I/O) Capacitance | 12pF | V,.= OV Timing Measurement Reference Level: Inputs 0.8 V and 2 V Outputs 0.8 V and 2 V AC Characteristics Read Operation (Over operating temperature and Veg Range, unless otherwise specified) Limits 28C64-200 | 28C64-250 | 28C64-300 | 28C64-350 Test Symbol | Parameter Min. | Max. | Min. | Max. | Min. | Max.| Min.| Max. | Units | Conditions tec Read Cycle Time 200 250 300 350 ns {CE = OE =V, toe Chip Enable Access Time 200 250 300 350 | ns |OE=V, tea Address Access Time 200 250 300 350 | ns |CE=OE=V, toe Output Enable Access Time 80 90 90 90 {| ns |CE=V, tor Output or Chip Enable Highto | 0 | 60 | oO | 60 | 0 | 80 | 0 | 80 | ns [CE=V, output not being driven ton Output Hold from Address 0 ) ) 0 ns |CE=OE=V, Change, Chip Enable, or Output Enable, whichever oceurs first Read/Data Polling Cycle Time tre ADDRESSES ADDRESSES Ay NEXT ADDRESS DAT. DATA VALID DATA VALID NOTES: 1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance. Technotegy, incorporated 1-38 MD400106/A28C64 AC Characteristics Write Operation (Over the operating temperature and V,,. range, unless otherwise specified) Limits 28C64-200 | 28C64-250 | 28C64-300 | 28C64-350 Symbol | Parameter Min. | Max. | Min. | Max. | Min. | Max. [| Min. | Max. Units twe Write Cycle Time 10 10 10 10 ms tys Address Set-up Time 10 10 10 10 ns tan Address Hold Time (see note 1) 150 150 150 150 ns tog Write Set-up Time 0 0 0 0 ns ton Write Hold Time 0 0 0 0 ns tow CE Pulse Width (note 2) 150 150 150 150 ns toes GE High Set-up Time 10 10 10 10 ns toen OE High Hold Time 10 10 10 10 ns twe WE Pulse Width (note 2) 150 150 150 150 ns tos Data Set-up Time 50 50 50 50 ns ton Data Hold Time 0 0 0 0 ns tec Byte Load Timer Cycle (Page Mode Only see note 3) Military/Extended 0.2 | 200 | 0.2 | 200 | 0.2 | 200 | 0.2 | 200 ys Commercial 0.2 | 300 |] 0.2 | 300 | 0.2 | 300 | 0.2 | 300 ys tp Last Byte Loaded 200 200 200 200 ns to DATA Polling . Write Timing WE CONTROLLED WRITE CYCLE CE CONTROLLED WRITE CYCLE DATA DATA BYTE WRITE -}4 POLLING =| BYTE WAITE rs J. ~ OE ~ toen VLE LLLD ADDRESSES Pe tan to YS we : tes +--t we ti p- / ce om + ip fos] ot DATA "HGH Ze DATAIN DATA f$p DATA DATAIN NOTES: 1 Address hold time is with respect to the falling edge of the control signal WE or CE. 2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle. 3. ty, min. is the minimum time before the next byte can be loaded. t,,, max. is the minimum time the byte load timer waits before initiating internal write cycle. SEEQ Technology, Incorporated 1-39 MD400106/APage Write Timing ae 28C64 PAGE LOAD | DATA POLLING ee a 4 ADDRESSES VALID al mK KOLB OK y ta Petar a | rs 7 \ \ lf \_ Sf ~ wer Le tes cH i Par twe }eteic>| be $$ tic We RA ST NY Nr | f* too tos} ee HIGHZ DATA S, DATA ~~ DATA <8 <F EE ey Ordering Information D M 28C64-200 B PACKAGE TEMPERATURE DEVICE ACCESS TIME SCREENING TYPE RANGE OPTION D = CERAMIC DIP M =-55C to + 125C 8K x 8 EEPROM 200 = 200 ns MIL 883 L=Lcc (MILITARY) 250 = 250 ns CLASS B F = FLATPACK 300 = 300 ns SCREENED N= PLCC E =-40C to +85C 350 = 350 ns P = PLASTIC DIP (EXTENDED) $=SOIC T = PIN GRID ARRAY Q = 0C to 70C UX = UNENCAPSULATED DIE (COMMERCIAL) SEEQ Technology, Incorporated 1 - 40 MD400106/A