Datasheet
BMM150 Geomagnetic Sensor
BST-BMM150-DS001-01 | Revision 1.0 | April 2013 Bosch Sensortec
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Note: Specifications within this document are subject to change without notice.
4.3 Sensor output data
4.3.1 Magnetic field data
The representation of magnetic field data is different between X/Y-axis and Z-axis. The width of
X- and Y-axis magnetic field data is 13 bits each and stored in two’s complement.
DATAX_LSB (0x42) contains 5-bit LSB part [4:0] of the 13 bit output data of the X-channel.
DATAX_MSB (0x43) contains 8-bit MSB part [12:5] of the 13 bit output data of the X-channel.
DATAY_LSB (0x44) contains 5-bit LSB part [4:0] of the 13 bit output data of the Y-channel.
DATAY_MSB (0x45) contains 8-bit MSB part [12:5] of the 13 bit output data of the Y-channel.
The width of the Z-axis magnetic field data is 15 bit word stored in two’s complement.
DATAZ_LSB (0x46) contains 7-bit LSB part [6:0] of the 15 bit output data of the Z-channel.
DATAZ_MSB (0x47) contains 8-bit MSB part [14:7] of the 15 bit output data of the Z-channel.
For all axes, temperature compensation on the host is used to get ideally matching sensitivity
over the full temperature range. The temperature compensation is based on a resistance
measurement of the hall sensor plate. The resistance value is represented by a 14 bit unsigned
output word.
RHALL_LSB (0x48) contains 6-bit LSB part [5:0] of the 14 bit output data of the RHALL-
channel.
RHALL_MSB (0x49) contains 8-bit MSB part [13:6] of the 14 bit output data of the RHALL-
channel.
All signed register values are in two´s complement representation. Bits which are marked
“reserved” can have different values or can in some cases not be read at all (read will return
0x00 in I²C mode and high-Z in SPI mode).
Data register readout and shadowing is implemented as follows:
After all enabled axes have been measured; complete data packages consisting of DATAX,
DATAY, DATAZ and RHALL are updated at once in the data registers. This way, it is prevented
that a following axis is updated while the first axis is still being read (axis mix-up) or that MSB
part of an axis is updated while LSB part is being read.
While reading from any data register, data register update is blocked. Instead, incoming new
data is written into shadow registers which will be written to data registers after the previous
read sequence is completed (i.e. upon stop condition in I²C mode, or CSB going high in SPI
mode, respectively). Hence, it is recommended to read out at all data at once (0x42 to 0x49 or
0x4A if status bits are also required) with a burst read.
Single bytes or axes can be read out, while in this case it is not assured that adjacent registers
are not updated during readout sequence.
The “Data ready status” bit (register 0x48 bit0) is set “1” when the data registers have been
updated but the data was not yet read out over digital interface. Data ready is cleared (set “0”)
directly after completed read out of any of the data registers and subsequent stop condition
(I²C) or lifting of CSB (SPI).
In addition, when enabled the “Data overrun” bit (register 0x4A bit7) turns “1” whenever data
registers are updated internally, but the old data was not yet read out over digital interface (i.e.
data ready bit was still high). The “Data overrun” bit is cleared when the interrupt status register
0x4A is read out. This function needs to be enabled separately by setting the “Data overrun En”
bit (register 0x4D bit7)).