TSC80C31/80C51 CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller Description The TSC80C31/80C51 is high performance SCMOS versions of the 8051 NMOS single chip 8 bit C. The fully static design of the TSC80C31/80C51 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TSC80C31/80C51 retains all the features of the 8051 : 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ; two 16 bit timers ; a 5-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits. TSC80C31/80C51-L16 : Low power version Vcc : 2.7-5.5 V Freq : 0-16 MHz TSC80C31/80C51-L20 : Low power version Vcc : 2.7-5.5 V Freq : 0-20 MHz TSC80C31/80C51-12 : 0 to 12 MHz TSC80C31/80C51-20 : 0 to 20 MHz TSC80C31/80C51-25 : 0 to 25 MHz In addition, the TSC80C31/80C51 has two software-selectable modes of reduced activity for further reduction in power consumption. In the Idle Mode the CPU is frozen while the RAM, the timers, the serial port, and the interrupt system continue to function. In the Power Down Mode the RAM is saved and all other functions are inoperative. The TSC80C31/80C51 is manufactured using SCMOS process which allows them to run from 0 up to 44 MHz with VCC = 5 V. The TSC80C31/80C51 is also available at 20 MHz with 2.7 V < Vcc < 5.5 V. TSC80C31/80C51-30 : 0 to 30 MHz TSC80C31/80C51-36 : 0 to 36 MHz TSC80C31/80C51-40 : 0 to 40 MHz TSC80C31/80C51-44 : 0 to 44 MHz* * Commercial and Industrial temperature range only. For other speed and range please consult your sale office. Features Power control modes 128 bytes of RAM 4 K bytes of ROM (TSC80C31/80C51) 32 programmable I/O lines Two 16 bit timer/counter 64 K program memory space 64 K data memory space Fully static design 0.8 m CMOS process Boolean processor 5 interrupt sources Programmable serial port Temperature range : commercial, industrial, automotive and military Optional Secret ROM : Encryption Secret TAG : Identification number MATRA MHS Rev. E (14 Jan.97) 1 TSC80C31/80C51 Interface Figure 1. Block Diagram 2 MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 DIL40 P0.3/A3 P0.2/A2 P0.1/A1 P0.0/A0 VCC NC P1.0 P1.1 P1.2 P1.3 P1.4 Figure 2. Pin Configuration P1.5 P0.4/A4 P1.6 P0.5/A5 P1.7 P0.6/A6 RST P0.7/A7 EA RxD/P3.0 PLCC44 NC NC ALE TxD/P3.1 P15 P04 /A4 P16 P05 /A5 P17 P06 /A6 RST P07 /A7 RxD/P30 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P03/A3 P02/A2 P01/A1 VCC P00/A0 P10 NC P11 P12 P13 P14 NC P2.5/A13 VSS T1/P3.5 XTAL1 P2.6/A14 XTAL2 P2.7/A15 T0/P3.4 RD/P3.7 PSEN INT1/P3.3 WR/P3.6 INT0/P3.2 EA PQFP44 NC NC ALE TxD/P31 P24 /A12 P23 /A11 P22 /A10 P21 /A9 P20 /A8 NC V SS P25 /A13 XTAL1 P26 /A14 T1/P35 XTAL2 P27 /A15 T0/P34 RD/P37 PSEN INT1/P33 WR/P36 INT0/P32 Diagrams are for reference only. Packages sizes are not to scale. MATRA MHS Rev. E (14 Jan.97) 3 TSC80C31/80C51 Pin Description VSS Circuit ground potential. VCC Supply voltage during normal, Idle, and Power Down operation. Port 0 Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1's. Port 0 also outputs the code bytes during program verification in the TSC80C31/80C51. External pullups are required during program verification. Port 0 can sink eight LS TTL inputs. It also receives the high-order address bits and control signals during program verification in the TSC80C31/80C51. Port 2 can sink or source three LS TTL inputs. It can drive CMOS inputs without external pullups. Port 3 Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the pullups. It also serves the functions of various special features of the TEMIC C51 Family, as listed below. Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 1 Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups. Port 1 also receives the low-order address byte during program verification. In the TSC80C31/80C51, Port 1 can sink or source three LS TTL inputs. It can drive CMOS inputs without external pullups. Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) TD (Timer 0 external input) T1 (Timer 1 external input) WR (external Data Memory write strobe) RD (external Data Memory read strobe) Port 3 can sink or source three LS TTL inputs. It can drive CMOS inputs without external pullups. RST A high level on this for two machine cycles while the oscillator is running resets the device. An internal pull-down resistor permits Power-On reset using only a capacitor connected to VCC. As soon as the Reset is applied (Vin), PORT 1, 2 and 3 are tied to one. This operation is achieved asynchronously even if the oscillator does not start-up. Port 2 Port 2 is an 8 bit bi-directional I/O port with internal pullups. Port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (ILL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16 bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1's. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. 4 ALE Address Latch Enable output for latching the low byte of the address during accesses to external memory. ALE is activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data memory access at which time one ALE pulse is skipped. ALE can sink/source 8 LS TTL inputs. It can drive CMOS inputs without an external pullup. If desired, ALE operation can be disabled by setting bit 0 of SFR location AFh (MSCON). With the bit set, ALE is active only during MOVX instruction and external fetches. Otherwise the pin is pulled low. MSCON SFR is set to XXXXXXX0 by reset. MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 PSEN XTAL1 Program Store Enable output is the read strobe to external Program Memory. PSEN is activated twice each machine cycle during fetches from external Program Memory. (However, when executing out of external Program Memory, two activations of PSEN are skipped during each access to external Data Memory). PSEN is not activated during fetches from internal Program Memory. PSEN can sink or source 8 LS TTL inputs. It can drive CMOS inputs without an external pullup. Input to the inverting amplifier that forms the oscillator. Receives the external oscillator signal when an external oscillator is used. XTAL2 Output of the inverting amplifier that forms the oscillator. This pin should be floated when an external oscillator is used. EA When EA is held high, the CPU executes out of internal Program Memory (unless the Program Counter exceeds 3 FFFH). When EA is held low, the CPU executes only out of external Program Memory. EA must not be floated. Idle And Power Down Operation Figure 3. shows the internal Idle and Power Down clock configuration. As illustrated, Power Down operation stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to function, while the clock to the CPU is gated off. These special modes are activated by software via the Special Function Register, PCON. Its hardware address is 87H. PCON is not bit addressable. PCON : Power Control Register (MSB) SMOD (LSB) - - - GF1 GF0 PD IDL Symbol Position Name and Function SMOD PCON.7 - - - GF1 GF0 PD PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 IDL PCON.0 Double Baud rate bit. When set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. (Reserved) (Reserved) (Reserved) General-purpose flag bit. General-purpose flag bit. Power Down bit. Setting this bit activates power down operation. Idle mode bit. Setting this bit activates idle mode operation. Figure 3. Idle and Power Down Hardware. If 1's are written to PD and IDL at the same time. PD takes, precedence. The reset value of PCON is (000X0000). Idle Mode The instruction that sets PCON.0 is the last instruction executed before the Idle mode is activated. Once in the Idle mode the CPU status is preserved in its entirety : the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM and all other registers maintain their data during idle. Table 1 describes the status of the external pins during Idle mode. MATRA MHS Rev. E (14 Jan.97) There are three ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction to be executed will be the one following the instruction that wrote 1 to PCON.0. 5 TSC80C31/80C51 The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. The second way of terminating the Idle mode is with a hardware reset. Since the oscillator is still running, the hardware reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation. Power Down Mode The instruction that sets PCON.1 is the last executed prior to entering power down. Once in power down, the oscillator is stopped. The contents of the onchip RAM and the Special Function Register is saved during power down mode. The hardware reset initiates the Special Fucntion Register. In the Power Down mode, VCC may be lowered to mi-nimize circuit power consumption. Care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which freezes the oscillator. Reset should not be released until the oscillator has restarted and stabilized. A hardware reset is the only way of exiting the power down mode. Table 1 describes the status of the external pins while in the power down mode. It should be noted that if the power down mode is activated while in external program memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the data is a 1, the port pin is held high during the power down mode by the strong pullup, T1, shown in Figure 4. Table 1. Status of the external pins during idle and power down modes. MODE PROGRAM MEMORY ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Port Data Port Data Port Data Port Data Idle External 1 1 Floating Port Data Address Port Data Power Down Internal 0 0 Port Data Port Data Port Data Port Data Power Down External 0 0 Floating Port Data Port Data Port Data Stop Clock Mode Due to static design, the TSC80C31/80C51 clock speed can be reduced until 0 MHz without any data loss in memory or registers. This mode allows step by step utilization, and permits to reduce system power consumption by bringing the clock frequency down to any value. At 0 MHz, the power consumption is the same as in the Power Down Mode. Figure 4. I/O Buffers in the TSC80C31/80C51 (Ports 1, 2, 3). I/O Ports The I/O buffers for Ports 1, 2 and 3 are implemented as shown in Figure 4. 6 MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 When the port latch contains a 0, all pFETS in Figure 4. are off while the nFET is turned on. When the port latch makes a 0-to-1 transition, the nFET turns off. The strong pFET, T1, turns on for two oscillator periods, pulling the output high very rapidly. As the output line is drawn high, pFET T3 turns on through the inverter to supply the IOH source current. This inverter and T form a latch which holds the 1 and is supported by T2. When Port 2 is used as an address port, for access to external program of data memory, any address bit that contains a 1 will have his strong pullup turned on for the entire duration of the external memory access. When an I/O pin son Ports 1, 2, or 3 is used as an input, the user should be aware that the external circuit must sink current during the logical 1-to-0 transition. The maximum sink current is specified as ITL under the D.C. Specifications. When the input goes below approximately 2 V, T3 turns off to save ICC current. Note, when returning to a logical 1, T2 is the only internal pullup that is on. This will result in a slow rise time if the user's circuit does not force the input line high. Oscillator Characteristics XTAL1 and XTAL2 are the input and output respectively, of an inverting amplifier which is configured for use as an on-chip oscillator, as shown in Figure 5. Either a quartz crystal or ceramic resonator may be used. Figure 5. Crystal Oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected as shown in Figure 6. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the Data Sheet must be observed. Figure 6. External Drive Configuration. TSC80C51 with Secret ROM TEMIC offers TSC80C31/80C51 with the encrypted secret ROM option to secure the ROM code contained in the TSC80C31/80C51 microcontrollers. The clear reading of the program contained in the ROM is made impossible due to an encryption through several random keys implemented during the manufacturing process. The keys used to do such encryption are selected randomwise and are definitely different from one microcontroller to another. - Everytime a byte is addressed during a verify of the ROM content, a byte of the encryption array is selected. - MOVC instructions executed from external program memory are disabled when fetching code bytes from internal memory. - EA is sampled and latched on reset, thus all state modification are disabled. For further information please refer to the application note (ANM053) available upon request. This encryption is activated during the following phases : MATRA MHS Rev. E (14 Jan.97) 7 TSC80C31/80C51 TSC80C31/80C51 with Secret TAG TEMIC offers special 64-bit identifier called "SECRET TAG" on the microcontroller chip. The Secret Tag option is available on both ROMless and masked microcontrollers. The Secret Tag feature allows serialization of each microcontroller for identification of a specific equipment. A unique number per device is implemented in the chip during manufacturing process. The serial number is a 64-bit binary value which is contained and addressable in the Special Function Registers (SFR) area. 8 This Secret Tag option can be read-out by a software routine and thus enables the user to do an individual identity check per device. This routine is implemented inside the microcontroller ROM memory in case of masked version which can be kept secret (and then the value of the Secret Tag also) by using a ROM Encryption. For further information, please refer to the application note (ANM031) available upon request. MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 Electrical Characteristics * Notice Absolute Maximum Ratings* Ambiant Temperature Under Bias : C = commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I = industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65C to + 150C Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to + 7 V Voltage on Any Pin to VSS . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W** ** This value is based on the maximum allowable die temperature and the thermal resistance of the package Stresses at or above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Parameters TA = 0C to 70C ; VSS = 0 V ; VCC = 5 V 10 % ; F = 0 to 44 MHz TA = -40C + 85C ; VSS = 0 V ; VCC = 5 V 10 % ; F = 0 to 44 MHz Symbol Parameter Min Typ (3) Max Unit - 0.5 0.2 Vcc - 0.1 V 0.2 Vcc + 0.9 Vcc + 0.5 V 0.7 Vcc Test Conditions VIL Input Low Voltage VIH Input High Voltage (Except XTAL and RST) VIH1 Input High Voltage (for XTAL and RST) Vcc + 0.5 V VOL Output Low Voltage (Port 1, 2 and 3) (4) 0.3 0.45 1.0 V V V IOL = 100 A IOL = 1.6 mA (2) IOL = 3.5 mA VOL1 Output Low Voltage (Port 0, ALE, PSEN) (4) 0.3 0.45 1.0 V V V IOL = 200 A IOL = 3.2 mA (2) IOL = 7.0 mA VOH Output High Voltage Port 1, 2, 3 Vcc - 0.3 V IOH = - 10 A Vcc - 0.7 V IOH = - 30 A Vcc - 1.5 V IOH = - 60 A VCC = 5 V 10 % Vcc - 0.3 V IOH = - 200 A Vcc - 0.7 V IOH = - 3.2 mA Vcc - 1.5 V IOH = - 7.0 mA VCC = 5 V 10 % VOH1 Output High Voltage (Port 0, ALE, PSEN) IIL Logical 0 Input Current (Ports 1, 2 and 3) - 50 A Vin = 0.45 V ILI Input leakage Current 10 A 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) - 650 A Vin = 2.0 V IPD Power Down Current Vcc = 2.0 V to 5.5 V (1) RRST RST Pulldown Resistor CIO Capacitance of I/O Buffer ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq 12 MHz Icc op max = 0.9 Freq (MHz) + 5 Icc idle max = 0.3 Freq (MHz) + 1.7 Freq 20 MHz Icc op typ = 0.7 Freq (MHz) Freq 20 MHz Icc op typ = 0.5 Freq (MHz) + 4 Freq 20 MHz Icc idle typ = 0.16 Freq (MHz) + 0.4 Freq 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2 MATRA MHS Rev. E (14 Jan.97) 50 5 30 A 90 200 K 10 pF 1.8 1 9 3.5 mA mA mA mA mA mA mA mA mA mA fc = 1 MHz, Ta = 25_C Vcc = 5.5 V 0.7 0.5 4.2 1.4 9 TSC80C31/80C51 Absolute Maximum Ratings* ** This value is based on the maximum allowable die temperature and the thermal resistance of the package Ambient Temperature Under Bias : A = Automotive . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65C to + 150C Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to + 7 V Voltage on Any Pin to VSS . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W** * Notice Stresses above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Parameters TA = -40C + 125C ; VSS = 0 V ; VCC = 5 V 10 % ; F = 0 to 40 MHz Symbol Parameter Min Typ (3) Max Unit - 0.5 0.2 Vcc - 0.1 V 0.2 Vcc + 0.9 Vcc + 0.5 V 0.7 Vcc Vcc + 0.5 V Test Conditions VIL Input Low Voltage VIH Input High Voltage (Except XTAL and RST) VIH1 Input High Voltage (for XTAL and RST) VOL Output Low Voltage (Port 1, 2 and 3) (4) 0.3 0.45 1.0 V V V IOL = 100 A IOL = 1.6 mA (2) IOL = 3.5 mA VOL1 Output Low Voltage (Port 0, ALE, PSEN) (4) 0.3 0.45 1.0 V V V IOL = 200 A IOL = 3.2 mA (2) IOL = 7.0 mA VOH Output High Voltage Port 1, 2 and 3 Vcc - 0.3 V IOH = - 10 A Vcc - 0.7 V IOH = - 30 A Vcc - 1.5 V IOH = - 60 A VCC = 5 V 10 % Vcc - 0.3 V IOH = - 200 A Vcc - 0.7 V IOH = - 3.2 mA Vcc - 1.5 V IOH = - 7.0 mA VCC = 5 V 10 % VOH1 IIL Logical 0 Input Current (Ports 1, 2 and 3) - 75 A Vin = 0.45 V ILI Input leakage Current 10 A 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) - 750 A Vin = 2.0 V IPD Power Down Current 5 75 A Vcc = 2.0 V to 5.5 V (1) 90 200 K 10 pF 1.8 1 9 3.5 mA mA mA mA mA mA mA mA mA mA RRST 10 Output High Voltage (Port 0, ALE, PSEN) RST Pulldown Resistor CIO Capacitance of I/O Buffer ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq 12 MHz Icc op max = 0.9 Freq (MHz) + 5 Icc idle max = 0.3 Freq (MHz) + 1.7 Freq 20 MHz Icc op typ = 0.7 Freq (MHz) Freq 20 MHz Icc op typ = 0.5 Freq (MHz) + 4 Freq 20 MHz Icc idle typ = 0.16 Freq (MHz) + 0.4 Freq 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2 50 fc = 1 MHz, Ta = 25_C Vcc = 5.5 V 0.7 0.5 4.2 1.4 MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 Absolute Maximum Ratings* ** This value is based on the maximum allowable die temperature and the thermal resistance of the package Ambient Temperature Under Bias : M = Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65C to + 150C Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to + 7 V Voltage on Any Pin to VSS . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W** * Notice Stresses at or above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Parameters TA = -55C + 125C ; Vss = 0 V ; Vcc = 5 V 10 % ; F = 0 to 40 MHz Symbol Parameter Min Typ (3) Max Unit - 0.5 0.2 Vcc - 0.1 V 0.2 Vcc + 0.9 Vcc + 0.5 V 0.7 Vcc Vcc + 0.5 V Test Conditions VIL Input Low Voltage VIH Input High Voltage (Except XTAL and RST) VIH1 Input High Voltage (for XTAL and RST) VOL Output Low Voltage (Port 1, 2 and 3) (4) 0.45 V IOL = 1.6 mA (2) VOL1 Output Low Voltage (Port 0, ALE, PSEN) (4) 0.45 V IOL = 3.2 mA (2) VOH Output High Voltage (Port 1, 2 and 3) 2.4 V IOH = - 60 A Vcc = 5 V 10 % 0.75 Vcc V IOH = - 25 A 0.9 Vcc V IOH = - 10 A 2.4 V IOH = - 400 A Vcc = 5 V 10 % 0.75 Vcc V IOH = - 150 A 0.9 Vcc V IOH = - 40 A - 75 A Vin = 0.45 V VOH1 Output High Voltage (Port 0 in External Bus Mode, ALE, PEN) IIL Logical 0 Input Current (Ports 1, 2 and 3) ILI Input leakage Current +/- 10 A 0.45 < Vin < Vcc ITL Logical 1 to 0 Transition Current (Ports 1, 2 and 3) - 750 A Vin = 2.0 V IPD Power Down Current 5 75 A Vcc = 2.0 V to 5.5 V (1) 90 200 K 10 pF 1.8 1 9 3.5 mA mA mA mA mA mA mA mA mA mA RRST RST Pulldown Resistor CIO Capacitance of I/O Buffer ICC Power Supply Current Freq = 1 MHz Icc op Icc idle Freq = 6 MHz Icc op Icc idle Freq 12 MHz Icc op max = 0.9 Freq (MHz) + 5 Icc idle max = 0.3 Freq (MHz) + 1.7 Freq 20 MHz Icc op typ = 0.7 Freq (MHz) Freq 20 MHz Icc op typ = 0.5 Freq (MHz) + 4 Freq 20 MHz Icc idle typ = 0.16 Freq (MHz) + 0.4 Freq 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2 MATRA MHS Rev. E (14 Jan.97) 50 fc = 1 MHz, Ta = 25_C Vcc = 5.5 V 0.7 0.5 4.2 1.4 11 TSC80C31/80C51 * Notice Absolute Maximum Ratings* Ambient Temperature Under Bias : C = Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I = Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65C to + 150C Voltage on VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to + 7 V Voltage on Any Pin to VSS . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W** ** This value is based on the maximum allowable die temperature and the thermal resistance of the package Stresses at or above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. DC Characteristics : Low Power Version TA = 0C to 70C ; Vcc = 2.7 V to 5.5 V ; Vss = 0 V ; F = 0 to 20 MHz TA = -40C to 85C ; Vcc = 2.7 V to 5.5 V ; F = 0 to 20 MHz Symbol Parameter Min Typ (3) Max Unit - 0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V Test Conditions VIL Input Low Voltage VIH Input High Voltage (Except XTAL and RST) VIH2 Input High Voltage to RST for Reset 0.7 VCC VCC + 0.5 V VIH1 Input High Voltage to XTAL1 0.7 VCC VCC + 0.5 V VPD Power Down Voltage to Vcc in PD Mode 2.0 5.5 V VOL Output Low Voltage (Ports 1, 2, 3) (4) 0.45 V IOL = 0.8 mA (2) VOL1 Output Low Voltage Port 0, ALE, PSEN (4) 0.45 V IOL = 1.6 mA (2) VOH Output High Voltage (Port 1, 2 and 3) 0.9 Vcc V IOH = - 10 A VOH1 Output High Voltage (Port 0 in External Bus Mode), ALE, PSEN 0.9 Vcc V IOH = - 40 A IIL Logical 0 Input Current Ports 1, 2, 3 - 50 A Vin = 0.45 V ILI Input Leakage Current 10 A 0.45 < Vin < VCC ITL Logical 1 to 0 Transition Current (Ports 1, 2, 3) - 650 A Vin = 2.0 V IPD Power Down Current 5 30 A VCC = 2.0 V to 5.5 V (1) 90 200 k 10 pF RRST CIO RST Pulldown Resistor 50 Capacitance of I/O Buffer fc = 1 MHz, TA = 25_C Icc (mA) Operating (1) 2.7 V Frequency/Vcc 3V 3.3 V 2.7 V 3V 3.3 V Max Typ Max Typ Max Typ Max Typ Max Typ Max Typ 1 MHz 0.8 0.37 1 0.42 1.1 0.46 0.4 0.22 0.5 0.24 0.6 0.27 6 MHz 4 2.2 5 2.5 6 2.7 1.5 1.2 1.7 1.4 2 1.6 12 MHz 8 4 10 4.7 12 5.3 2.5 1.7 3 2.2 3.5 2.6 16 MHz 10 5 12 5.8 14 6.6 3 1.9 3.8 2.5 4.5 3 Freq > 12MHz (Vcc = 5.5 V) 12 Idle (1) Icc op max (mA) = 0.9 x Freq (MHz) + 5 Icc Idle max (mA) = 0.3 x Freq (MHz) + 1.7 MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 Idle ICC is measured with all output pins disconnected ; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V ; XTAL2 N.C ; Port 0 = VCC ; EA = RST = VSS. Figure 7. ICC Test Condition, Idle Mode. Power Down ICC is measured with all output pins disconnected ; EA = PORT 0 = VCC ; XTAL2 N.C. ; RST = VSS. Note 2 : Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operations. In the worst cases (capacitive loading 100 pF), the noise pulse on the ALE line may exceed 0.45 V with maxi VOL peak 0.6 V. A Schmitt Trigger use is not necessary. All other pins are disconnected. Figure 8. ICC Test Condition, Active Mode. Note 3 : Typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5V. Note 4 : Under steady state (non-transient)) conditions, IOL must be externally limited as follows : Maximum IOL per port pin : 10 mA Maximum IOL per 8-bit port : Port 0 : 26 mA Ports 1, 2 and 3 : 15 mA Maximum total IOL for all output pins : 71 mA All other pins are disconnected. Figure 9. ICC Test Condition, Power Down Mode. If IOL exceed the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. All other pins are disconnected. Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns. MATRA MHS Rev. E (14 Jan.97) 13 TSC80C31/80C51 Explanation of the AC Symbol Each timing symbol has 5 characters. The first character is always a "T" (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A : Address. C : Clock. D : Input data. H : Logic level HIGH I : Instruction (program memory contents). L : Logic level LOW, or ALE. P : PSEN. Example : TAVLL = Time for Address Valid to ALE low. TLLPL = Time for ALE low to PSEN low. Q : Output data. R : READ signal. T : Time. V : Valid. W : WRITE signal. X : No longer a valid logic level. Z : Float. AC Parameters TA= 0 to + 70C ; Vss= 0 V ; Vcc= 5 V 10 % ; F= 0 to 44 MHz TA= 0 to +70C ; Vss= 0 V ; 2.7 V <Vcc < 5.5 V ; F= 0 to 16 MHz TA=-40 to +85C; Vss= 0 V; 2.7 V<Vcc <5.5 V ; F= 0 to 16 MHz TA= -55 + 125C; Vss= 0 V; Vcc= 5 V 10 % ; F= 0 to 40 MHz (Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF) External Program Memory Characteristics (values in ns) 16 MHz SYMBOL PARAMETER 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 44 MHz min max min max min max min max min max min max min max TLHLL ALE Pulse Width 110 90 70 60 50 40 30 TAVLL Address valid to ALE 40 30 20 15 10 9 7 TLLAX Address Hold After ALE 35 35 35 35 35 30 20 TLLIV ALE to valid instr in 185 170 130 100 80 70 65 TLLPL ALE to PSEN 45 40 30 25 20 15 12 TPLPH PSEN pulse Width 165 130 100 80 75 65 54 TPLIV PSEN to valid instr in TPXIX Input instr Hold After PSEN 125 0 110 0 50 85 0 35 0 Input instr Float After PSEN PSEN to Address Valid TAVIV Address to Valid instr in 230 210 170 130 90 80 70 TPLAZ PSEN low to Address Float 10 10 8 6 5 5 5 40 30 45 0 TPXIZ 50 35 50 0 TPXAV 55 45 65 0 35 25 30 20 25 10 15 External Program Memory Read Cycle TAVIV 14 MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 External Data Memory Characteristics (values in ns) 16 MHz SYMBOL PARAMETER 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 44 MHz min max min max min max min max min max min max min max TRLRH RD pulse Width 340 270 210 180 120 100 80 TWLWH WR pulse Width 340 270 210 180 120 100 80 85 TLLAX Address Hold After ALE TRLDV RD to Valid data in 85 TRHDX Data hold after RD TRHDZ Data float after RD 90 90 80 70 50 45 35 240 0 70 210 0 55 175 0 35 135 0 30 110 0 25 90 0 70 0 TLLDV ALE to Valid Data In 435 370 350 235 170 150 130 TAVDV Address to Valid Data IN 480 400 300 260 190 180 170 TLLWL ALE to WR or RD 150 250 135 170 120 130 90 115 70 100 60 95 50 TAVWL Address to WR or RD 180 180 140 115 75 65 55 TQVWX Data valid to WR transition 35 35 30 20 15 10 6 TQVWH Data Setup to WR transition 380 325 250 215 170 160 140 TWHQX Data Hold after WR 40 35 30 20 15 10 6 TRLAZ RD low to Address Float TWHLH RD or WR high to ALE high 0 35 90 0 35 60 0 25 45 0 20 40 0 20 40 0 15 35 85 0 13 33 External Data Memory Write Cycle TAVWL TQVWX External Data Memory Read Cycle MATRA MHS Rev. E (14 Jan.97) 15 TSC80C31/80C51 Serial Port Timing - Shift Register Mode (values in ns) 16 MHz SYMBOL PARAMETER 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 44 MHz min max min max min max min max min max min max min max TXLXL Serial Port Clock Cycle Time 750 600 480 400 330 250 227 TQVXH Output Data Setup to Clock Rising Edge 563 480 380 300 220 170 140 TXHQX Output Data Hold after Clock Rising Edge 90 90 65 50 45 35 25 TXHDX Input Data Hold after Clock Rising Edge 0 0 0 0 0 0 0 TXHDV Clock Rising Edge to Input Data Valid 563 450 350 300 250 200 160 Shift Register Timing Waveforms 16 MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 External Clock Drive Characteristics (XTAL1) SYMBOL PARAMETER FCLCL Oscillator Frequency TCLCL Oscillator period TCHCX MIN MAX UNIT 44 MHz 22.7 ns High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns External Clock Drive Waveforms AC Testing Input/Output Waveforms AC inputs during testing are driven at Vcc - 0.5 for a logic "1" and 0.45 V for a logic "0". Timing measurements are made at VIH min for a logic "1" and VIL max for a logic "0". Float Waveforms For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. Iol/IoH 20 mA. MATRA MHS Rev. E (14 Jan.97) 17 TSC80C31/80C51 Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA = 25C fully loaded) RD and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 18 MATRA MHS Rev. E (14 Jan.97) TSC80C31/80C51 Ordering Information TSC 80C51 XXX Part Number 80C31: External ROM 80C51: 4Kx8 Mask ROM 80C51C: Secret ROM version 80C51T: Secret Tag version -20 C -12: 12 MHz version -16: 16 MHz version -20: 20 MHz version -25: 25 MHz version -30: 30 MHz version -36: 36 MHz version -40: 40 MHz version -44: 44 MHz version -L16: Low Power (VCC: 2.7-5.5V, Freq.: 0-16 MHz) -L20: Low Power (VCC: 2.7-5.5V, Freq.: 0-20 MHz) B Packaging A: PDIL 40 B: PLCC 44 C: PQFP 44 (fp 13.9mm) D: PQFP 44 (fp 12.3mm) E: VQFP 44 (1.4mm) F: TQFP 44 (1mm) G: CDIL 40 (.6) H: LCC 44 I: CQPJ 44 Blank: Standard /883: MIL 883 Compliant P883: MIL 883 Compliant with PIND test. Die form: W: Wafer X: Dice Form Y: Wafer on Ring Customer ROM Code (Not used for external ROM Device) TEMIC Semiconductor Microcontroller Product Line R Temperature Range C : Commercial 0 to 70C I : Industrial -40 to 85C A : Automotive -40 to 125C M : Military -55 to 125C Conditioning R : Tape & Reel D : Dry Pack B : Tape & Reel and Dry Pack Examples : Mask ROM version XXX, PDIL 40, 20 MHz version, Commercial Temperature Range . TSC80C31/80C51XXX-20CA (1) Ceramic of multi-layer packages: contact TEMIC Sales office Product Marking : For PDIL 40, PLCC 44 & QFP 44 Packages TEMIC Customer P/N Temic P/N Intel 80, 82 YYWW Lot Number MATRA MHS Rev. E (14 Jan.97) 19