=1 attice ispLSI 1016 : = : : : Corporation tor In-System Programmable High Density PLD [Features Functional Block Diagram * HIGH-DENSITY PROGRAMMABLE LOGIC High-Speed Global Interconnect 2000 PLD Gates 32 I/O Pins, Four Dedicated Inputs 96 Registers Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic Security Cell Prevents Unauthorized Copying + HIGH PERFORMANCE E2CMOS TECHNOLOGY fmax = 110 MHz Maximum Operating Frequency fmax = 60 MHz for Industrial and Military/883 Devices tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile E2CMOS Technology 100% Tested OO ~ O oO =slelslelelelele 1] PM ]} BB wtput Routing Pool Output Routing Poo! outing Pool (GRP) ee) Ege] Lege) Ectqee] EA * IN-SSYSTEM PROGRAMMABLE CLK FE= In-System Programmable (ISP) 5-Volt Only _ Increased Manufacturing Yields, Reduced Time Market, and Improved Product Quality Bae Reprogram Soldered Devices for Faster D IBILITY OF FIELD PROGRAMMABL, YS igpE Si.016 is a High-Density Programmable Logic Complete Programmable Devic: ne Logic and Structured Desig? Three Dedicated Clock Input Synchronous and Asy Flexible Pin Placeme dicated Input pins, three Dedicated Clock Input d a Global Routing Pool (GRP). The GRP pro- es complete interconnectivity between all of these ements. The ispLSI 1016 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1016 device is the ading CAE Vendor Tools Generic Logic Block (GLB). The GLBs are labeled AO, A1 ig Timing Analyzer, Explore .. B7 (see figure 1). There are a total of 16 GLBs in the ispLSI 1016 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. Allofthe GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. March 1999 Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com 1016 08 {Lattice gueut= Semiconductor sauuee Corporation Specifications ispLS!I 1016 Functional Block Diagram Figure 1. ispLSI 1016 Functional Block Diagram Generic Logic Blocks (GLBs) e-------------)|-----, IN3 MODE/IN 2 vO 31 v0 30 vo | V0 29 vor 0 28 yo2 _ vos a V0 27 | oO 0 26 WO4 a | = or 8 0 25 VO5 o a ||3 V0 24 vO6 3S i Global om | |a a}} 9 | Routin //s 3 ! 9 = VO7 a o Pool a a VO 23 sl] s aa V0.8 al| (GRP) cc V0 22 ]| 3 a vo 24 vos c 5 vO 20 vO 10 3 ' vot | | V0 19 oO 1 10 18 vO 12 vO17 1013 ' V0 16 VO 14 ' VO 15 ' SDV/INO cLKo SDO/IN 1 coo Clock PGKI _, Megablock Distribution Network 1OCLKO IOCLK 1 The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered in- put, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signallevels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The ispLSI 1016 device contains two of these Megablocks. Yo + | YuRESET SCLK/Y2 *Note: Y1 and RESET are multiplexed on the same pin 0139B(ta)-isp.eps The GRP has as its inputs the outputs from allofthe GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1016 device are selected using the Clock Distribution Network. Three dedicated clock pins (YO, Y1 and Y2) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (BO on the ispLSI 1016 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.Lattice Specifications ispLSI 1016 sauuee Corporation Absolute Maximum Ratings 1 Supply Voltage Voge veccceccccceessseeeesseesteeeees -0.5 to +7.0V Input Voltage Applied ............ ee -2.5 tO Voc +1.0V Off-State Output Voltage Applied ..... -2.5 t0 Voc +1.0V Storage Temperature ..............::ceeeeee -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (Ty) with Power Applied ... 150C 1. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions SYMBOL PARAMETER MIN. MAX. UNITS Commercial Ta= 0C to +70C 4.75 5.25 Vcc Supply Voltage Industrial Ta = -40C to +85C 45 5.5 V Military/883 TT, = -55C to +125C 4.5 5.5 VIL Input Low Voltage 0 0.8 V VIH Input High Voltage 2.0 Vcc + 1 V Table 2- OOOSAisp w/mil.eps Capacitance (T,=25C, f=1.0 MHz) SYMBOL | PARAMETER MAXIMUM! UNITS TEST CONDITIONS C, ; ; Commercial/Industrial 8 pf Vec=5.0V, Vy=2.0V Dedicated Input Capacitance Military 10 pf Vec=5.0V, Viy=2.0V C, 1/0 and Clock Capacitance 10 pf Vec=5.0V, Vig, Vy=2.0V 1. Guaranteed but not 100% tested. Table 2 0006 Data Retention Specifications PARAMETER MINIMUM MAXIMUM UNITS Data Retention 20 _ Years Erase/Reprogram Cycles 10000 _ Cycles Table 2- 0008BLattice Specifications ispLS!I 1016 tuum Corporation Switching Test Conditions Figure 2. Test Load Input Pulse Levels GND to 3.0V Input Rise and Fall Time <3ns 10% to 90% + 5V Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V RY Output Load See figure 2 Device Test Output 3-state levels are measured 0.5V from steady-state I F Point active level. Ro T c* Table 2- 0003 Output Load Conditions (see figure 2) *oL includes Test Fixture and Probe Capacitance. Test Condition R1 R2 CL A 4700 3902 35pF B Active High 0 39002 35pF Active Low 470Q 39002 35pF Active High to Z oo 39002 5pF Cc at V,,,- 0.5V Active Low to Z 470Q 39002 5pF at V,, + 0.5V Table 2- 0004A DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL PARAMETER CONDITION min. | Typ3 | MAX.| UNITS VOL | Output Low Voltage lo. =8 MA - - 0.4 Vv VOH_ | Output High Voltage low =-4 MA 2.4 - - V IIL Input or /O Low Leakage Current | OV < Vin $ Vit (MAX.) - - -10 uA HH Input or I/O High Leakage Current | 3.5V < Vin < Voc - - 10 WA liL-isp isp Input Low Leakage Current OV < Vin < Vit (MAX.) - = -150 uA IiL-PU | I/O Active Pull-Up Current OV < Vins Vi - - -150 WA lost | Output Short Circuit Current Voo = SV, Vour = 0.5V - - -200 mA Icc2:4 | Operating Power Supply Current | Vi = 0-5V, V,,= 3.0V | Commercial = 100 | 150 mA frocete = 1 MHz Industrial/Military - 100 170 mA 1. One output at a time for a maximum duration of one second. V,, = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. . Measured using four 16-bit counters. . Typical values are at V.,. = 5V and T, = 25C. . Maximum |, varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec- tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I WP cc" Table 2-0007A-16 w/milLattice uuu Semiconductor sauuee Corporation Specifications ispLSI 1016 External Timing Parameters Over Recommended Operating Conditions PARAMETER|TEST|#| DESCRIPTION! 110 80 _tunrs . MIN. |MAX.] MIN. |MAX, tpd1 A |1 | Data Propagation Delay, 4PT bypass, ORP bypass - 10 - 12 ns tpd2 A_ | 2 | Data Propagation Delay, Worst Case Path ns fmax (Int.) A |3 | Clock Frequency with Internal Feedback? MHz fmax (Ext.) |4 | Clock Frequency with External Feedback (5a) MHz fmax (Tog.) - |5 | Clock Frequency, Max Toggle* MHz tsu1 |6] GLB Reg. Setup Time before Clock, 4PT bypass ns teo1 A |7 | GLB Reg. Clock to Output Delay, ORP bypass ns thi |8 | GLB Reg. Hold Time after Clock, 4 PT bypass ns tsu2 |9]|GLB Reg. Setup Time before Clock ns tco2 |10} GLB Reg. Clock to Output Delay ns the |11} GLB Reg. Hold Time after Clock ns tr A {12} Ext. Reset Pin to Output Delay ns trw1 |13] Ext. Reset Pulse Duration ns ten B |14] Input to Output Enable ns tis C |15] Input to Output Disable ns twh |16] Ext. Sync. Clock Pulse Duration, High 4 - 4 - ns tw 17] Ext. Syne. Clock Pulse Duration, Low 4 - 4 - ns tsu5 |18] I/O Reg. Setup Time before Ext. Sync. Clock (Y1, Y2) 2 - 2 - ns ths 19] I/O Reg. Hold Time after Ext. Sync. Clock (Y1, Y2) 55] - |65] - ns anWwn . Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and YO clock. . Refer to Timing Model in this data sheet for further details. . Standard 16-Bit loadable counter using GRP feedback. . fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. . Reference Switching Test Conditions Section. Table 2-0030-16/110,90CLattice Specifications ispLS!I 1016 sauuee Corporation External Timing Parameters Over Recommended Operating Conditions TEST 5) 42 1 -80 -60 PARAMETER COND # | DESCRIPTION UNITS . MIN. |MAX.] MIN. |MAX. tod1 A | 1 | Data Propagation Delay, 4PT bypass, ORP bypass - 15 - 20 ns tpd2 A_ | 2 | Data Propagation Delay, Worst Case Path ns fmax (Int.) A | 3 | Clock Frequency with Internal Feedback? MHz fmax (Ext.) | 4 | Clock Frequency with External Feedback (5am) MHz fmax (Tog.) |5 | Clock Frequency, Max Toggle* MHz tsu1 |6 | GLB Reg. Setup Time before Clock, 4PT bypass ns tco1 A |7 | GLB Reg. Clock to Output Delay, ORP bypass ns thi |8 | GLB Reg. Hold Time after Clock, 4 PT bypass ns tsu2 |9 | GLB Reg. Setup Time before Clock ns tco2 |10} GLB Reg. Clock to Output Delay ns the |11}) GLB Reg. Hold Time after Clock ns tr A |12]| Ext. Reset Pin to Output Delay ns trv |13] Ext. Reset Pulse Duration ns ten B |14] Input to Output Enable ns tis C |15] Input to Output Disable ns twh |16} Ext. Syne. Clock Pulse Duration, High ns tw |17} Ext. Syne. Clock Pulse Duration, Low ns tsu5 |18] /O Reg. Setup Time before Ext. Syne. Clock (Y1, Y2) ns ths |19} I/O Reg. Hold Time after Ext. Syne. Clock (Y1, Y2) 65) - [85] - ns Table 2-0030-16/80,60C 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and YO clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit loadable counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions Section.Lattice Specifications ispLSI 1016 sauuee Corporation Internal Timing Parameters' 5 -110 -90 PARAMETER| # DESCRIPTION UNITS MIN. |MAX.| MIN. |MAX. Inputs tiobp 20 | I/O Register Bypass - |}ogs] - | 1.0] ns tiolat 21 | I/O Latch Delay - | 1.7] - |20] ns tiosu 22 | I/O Register Setup Time before Clock 4.1 - 745] - ns tioh 23 | I/O Register Hold Time after Clock 18) - [2.0 ns tioco 24 | I/O Register Clock to Out Delay - 1.7 ns tior 25 | I/O Register Reset to Out Delay - 2.1 ns tdin 26 | Dedicated Input Delay ns GRP tgrp1 27 | GRP Delay, 1 GLB Load ns tgrp4 28 | GRP Delay, 4 GLB Loads ns tgrps 29 | GRP Delay, 8 GLB Loads ns tgrp12 30 | GRP Delay, 12 GLB Loads ns tgrp16 31 | GRP Delay, 16 GLB Loads ns GLB t4ptbp 33 | 4 Product Term Bypass Path Delay ns tptxor 34 | 1 Product Term/XOR Path Delay ns t20ptxor 35 | 20 Product Term/XOR Path Delay ns txoradj 36 | XOR Adjacent Path Delay? ns tgbp 37 | GLB Register Bypass Delay ns tgsu 38 | GLB Register Setup Time before Clock ns tgh 39 | GLB Register Hold Time after Clock ns tgco 40 | GLB Register Clock to Output Delay ns tgr 41 | GLB Register Reset to Output Delay ns tptre 42 | GLB Product Term Reset to Register Delay . 10.0] ns tptoe 43 | GLB Product Term Output Enable to I/O Cell Delay ns totck 44 | GLB Product Term Clock Delay ns ORP torp 45 | ORP Delay - | 20] - | 25] ns torpbp 46 | ORP Bypass Delay - |04]7 - |05]7 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Hard Macros.Lattice Specifications ispLS!I 1016 sauuee Corporation Internal Timing Parameters 2 -110 -90 PARAMETER| # DESCRIPTION UNITS MIN. |MAX.| MIN. |MAX. Outputs tob 47 | Output Buffer Delay | 21 ns toen 48 | I/O Cell OE to Output Enabled ns todis 49 | I/O Cell OE to Output Disabled ns Clocks tgyo 50 | Clock Delay, YO to Global GLB Clock Line (Ref. clock) ns tgy1/2 51 | Clock Delay, Y1 or Y2 to Global GLB Clock Line ns tgcp 52 | Clock Delay, Clock GLB to Global GLB Clock Line ns tioy1/2 53 | Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line ns tiocp 54 | Clock Delay, Clock GLB to I/O Cell Global Clock Line ns Global Reset tgr | 55 | Global Reset to GLB and I/O Registers ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.Lattice Specifications ispLSI 1016 sauuee Corporation Internal Timing Parameters' 2 -80 -60 PARAMETER]! # DESCRIPTION UNITS MIN. |MAX.| MIN. |MAX. Inputs tiobp 20 | I/O Register Bypass - |20] - | 27] ns tiolat 21 | V/O Latch Delay - 130] - | 40] ns tiosu 22 | I/O Register Setup Time before Clock 7.3 - ns tioh 23 | I/O Register Hold Time after Clock 1.3 - ns tioco 24 | I/O Register Clock to Out Delay - 4.0 ns tior 25 | I/O Register Reset to Out Delay - 3.3 ns tdin 26 | Dedicated Input Delay - | 537 ns GRP tgrp1 27 | GRP Delay, 1 GLB Load | 207 ns tgrp4 28 | GRP Delay, 4 GLB Loads - 2.7 ns tgrps 29 | GRP Delay, 8 GLB Loads - | 40] ns tgrp12 30 | GRP Delay, 12 GLB Loads | 5.0 ns tgrp16 31 | GRP Delay, 16 GLB Loads - 6.0 ns GLB t4ptbp 33 | 4 Product Term Bypass Path Delay - 8.6 ns ti ptxor 34 | 1 Product Term/XOR Path Delay - | 93 ns t20ptxor 35 | 20 Product Term/XOR Path Delay | 10.67 ns txoradj 36 | XOR Adjacent Path Delay? - |12.7] ns tgbp 37 | GLB Register Bypass Delay - 1.3 ns tgsu 38 | GLB Register Setup Time before Clock 1.3 - ns tgh 39 | GLB Register Hold Time after Clock 6.0 - ns tgco 40 | GLB Register Clock to Output Delay - 2.7 ns tgr 41 | GLB Register Reset to Output Delay - 3.3 ns tptre 42 | GLB Product Term Reset to Register Delay 10.0] - | 13.3] ns tptoe 43 | GLB Product Term Output Enable to I/O Cell Delay 907 - | 12.0] ns tptck 44 | GLB Product Term Clock Delay 35 | 75746] 9.9 ns ORP torp 45 | ORP Delay - |25] - | 33] ns torpbp 46 | ORP Bypass Delay - 05, - 0.7 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Hard Macros.Lattice Specifications ispLS!I 1016 sauuee Corporation Internal Timing Parameters' 2 -80 -60 PARAMETER| # DESCRIPTION UNITS MIN. |MAX.| MIN. |MAX. Outputs tob 47 | Output Buffer Delay ns toen 48 | I/O Cell OE to Output Enabled ns todis 49 | I/O Cell OE to Output Disabled ns Clocks tgyo 50 | Clock Delay, YO to Global GLB Clock Line (Ref. clock) ns tgy1/2 51 | Clock Delay, Y1 or Y2 to Global GLB Clock Line ns tgcp 52 | Clock Delay, Clock GLB to Global GLB Clock Line ns tioy1/2 53 | Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line ns tiocp 54 | Clock Delay, Clock GLB to I/O Cell Global Clock Line ns Global Reset tgr | 55 | Global Reset to GLB and I/O Registers ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 10Lattice uuu Semiconductor sauuee Corporation Specifications ispLSI 1016 ispLSI 1016 Timing Model VO Cell GRP GLB ORP VO Cell ee ot Ma Ne Feedback | Ded. In We (10 Pin> VO Reg Bypass | GRP 4 | 4 PT Bypass | GLB Reg Bypass | ORP Bypass | ap #20 i #28 iJ #33 _ #37 _ #46 _ (Input) | (Output) Input || GRP 20 PT GLB Reg ORP #48, 49 D Register Q Loading XOR Delays Delay Delay RST Delay D Q #55 #21 -25 #27, 29, #34, 35, 36 #45 N 30, 31, 32 RST A =| | 39 A m| Glock [LI Control RE Distribution PTs OE 1,2 #51,52, #42, 43, CK 53, 54 44 #50 > | Yo > Derivations of tsu, th and tco from the Product Term Clock! tsu 5.5 ns tco Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#20 + #28 + #35) + (#38) - (#20 + #28 + #44) (1.0 + 1.0 + 8.0) + (1.0) - (1.0+ 1.0+ 3.5) Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#20 + #28 + #44) + (#39) - (#20 + #28 + #35) (1.0+ 1.0 + 7.5) + (3.5) - (1.0+ 1.0 + 8.0) Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (#20 + #28 + #44) + (#40) + (#45 + #47) 16.0 ns = (1.0+ 1.0 +7.5) + (1.5) + (2.5 + 2.5) Derivations of tsu, th and tco from the Clock GLB" 3.5 ns = tco 16.5 ns Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgyo(min) + tgco + tgcp(min)) (#20 + #28 + #35) + (#38) - (#50 + #40 + #52) (1.0+ 1.0 + 8.0) + (1.0) - (3.54+ 1.54 1.0) Clock (max) + Reg h - Logic (tgyo(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#50 + #40 + #52) + (#39) - (#20 + #28 + #35) (3.5 + 1.5 + 5.0) + (3.5) - (1.0 + 1.0 + 8.0) Clock (max) + Reg co + Output (tgyo(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#50 + #40 + #52) + (#40) + (#45 + #47) (3.5 + 1.54 5.0) + (1.5) + (2.5 + 2.5) 1. Calculations are based upon timing specifications for the ispLSI 1016-90. 14Lattice Specifications ispLSI 1016 gueut= Semiconductor sauuee Corporation Maximum GRP Delay vs GLB Loads ispLSI 1016-60 ispLSI 1016-80 0 | l l 4 8 12 16 GLB Loads So Oo fF} OT DD GRP Delay (ns) 0126A-80-16-isp.eps Power Consumption Power consumption in the ispLSI 1016 device depends ure 3 shows the relationship between power and operat- on two primary factors: the speed at which the device is ing speed. operating, and the number of Product Terms used. Fig- Figure 3. Typical Device Power Consumption vs fmax 150 ispLSI 1016 Icc 0 10 20 30 40 50 60 70 80 90 100 110 fmax (MHz) Notes: Configuration of Four 16-bit Counters Typical Current at 5V, 25BC Icc can be estimated for the ispLS! 1016 using the following equation: Icc = 31 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.009) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICc should be verified. 12Lattice Specifications ispLSI 1016 sauuee Corporation Pin Description PLCC TQFP JLCC NAME _|PIN NUMBERS| PIN NUMBERS | PIN NUMBERS DESCRIPTION VO0-V03 15, 16, 17, 18,]/9, 10, 11, 12,] 15, 16, 17, 18,| Input/Output Pins - These are the general purpose I/O VO4-VO7 | 19, 20, 21, 22,|13, 14, 15, 16,| 19, 20, 21, 22,] Pins used by the logic array. VO8-VO11 | 25, 26, 27, 28,)19, 20, 21, 22,| 25, 26, 27, 28, VO 12-015] 29, 30, 31, 32,} 23, 24, 25, 26,| 29, 30, 31, 32, VO 16-1019 | 37, 38, 39, 40,}31, 32, 33, 34,| 37, 38, 39, 40, VO 20 - 1/0 23 | 41, 42, 43, 44,/35, 36, 37, 38,] 41, 42, 43, 44, VO 24-V/O27|3, 4, 5, 6, |41, 42, 43, 44,/3, 4, 5, 6, VO 28-VO31|7, 8 9, 10/1, 2, 3, 4 |7, 8 9, 10 IN3 2 4o 2 Dedicated input pins to the device. ispEN 13 7 13 Input Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. SDI/IN 07 14 8 14 Input This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. MODE/IN 21 36 30 36 Input This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. SDO/IN 11 24 18 24 Input/Output This pin performs two functions. Itis a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. SCLK/Y2' 33 27 33 Input This pin performs _two_ functions. It is a dedicated clock input when ispEN is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or |/Ocellon the device. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. YO 11 5 11 Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Y1/RESET 35 29 35 This pin performs two functions: Dedicated clock input. This clock inputis brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. GND 1, 23 17, 39 1, 23 Ground (GND) Vcc 12, 34 6, 28 12, 34 Veg 1. Pins have dual function capability. Table 2- 00020-16isp 13Lattice == Semiconductor aa Corporation Specifications ispLS!I 1016 Pin Configuration ispLSI 1016 44-Pin PLCC Pinout Diagram 44 43 42 41 40 vo 28 17 3917 1/0 18 vo 29 [8 3810 1/0 17 vo 30 9 370 1/0 16 vO 31 []10 36 [1] IN 2/MODE1 yo (11 . 35(1] Y1/RESET vec [12 ispLSI 1016 341 vec ispEN [13 Top View 3310] Y2/SCLK1 Ispivino [14 3211] 0 15 voo [15 311 10 14 vo1 (16 301 1/0 13 vo2 (17 291] 1/0 12 18 19 20 21 22 23 24 25 26 27 28 OOOO OLIOCICo nowyrnwn onananradnnoonrn 2 or PQLOkQkBEZLLQoo oO = 3 a a 1. Pins have dual function capability. 0123A-isp1016 ispLSI 1016 44-Pin TQFP Pinout Diagram ~ oOo WW + On +r OD NAN NW o aNN AN AN ge@92292g,222990 OOO Oooo 44 43 42 41 40 39 38 37 36 35 34 vo 28 [1 330 lo 18 vo 29 [2 3200 0 17 vo 30 []3 3117 Vo 16 vo31 [4 30/1] IN2/MODE1 yo 5 . 29|7] Y1/RESET vee He ispLSI 1016 >8H] vec ispEN [7 Top View 2717] Y2/SCLK1 1 spvino [8 261] VO 15 voog 25(] vo 14 vo 1[]10 24[] 0 13 voz (11 2317 Vo 12 12 13 14 15 16 17 18 19 20 21 22 OOODOOWOWOOC owyrwnoonanranosensdonr 2 er QLLLkHRBZLLoo oO = 3 a a 1. Pins have dual function capability. 0851 -16/TQFP 14tuum Corporation Lattice Specifications ispLSI 1016 Pin Configuration ispLSI 1016 44-Pin JLCC Pinout Diagram vO 28077 VO 29718 VO 30E 79 VO 31 C_jio YOO Ti) , vecE12} IspLSI 1016/883 ispEN [113 Top View 1 spvino [14 vVOOC 15 VO1T 16 vo2C 17 1. Pins have dual function capability. VO 18 VO 17 VO 16 IN 2/MODE1 Y1/RESET vec Y2/SCLK1 VO 15 VO 14 VO 13 VO 12 0123-16-ispJLCC. 15Lattice Specifications ispLS!I 1016 sauuee Corporation Part Number Description ispLSI 1016 XXX X XXX X Device Family Grade ispLSI Blank = Commercial . | = Industrial Device Number /883 = 883 Military Process Speed Package 110 = 110 MHz fmax J=PLcc 90 = 90 MHz fmax T44 = TQFP 80 = 80 MHz fmax H=JLcc 60 = 60 MHz fmax Power L=Low 0212-80B-isp1016 Ordering Information COMMERCIAL Family fmax (MHz) | tpd (ns) Ordering Number Package 110 10 ispLSI 1016-110LJ 44-Pin PLCC 90 12 ispLSI 1016-90LJ 44-Pin PLCC 90 12 ispLSI 1016-90LT44 44-Pin TQFP ispLSI 80 15 ispLSI 1016-80LJ 44-Pin PLCC 80 15 ispLSI 1016-80LT44 44-Pin TQFP 60 20 ispLSI 1016-60LJ 44-Pin PLCC 60 20 ispLSI 1016-60LT44 44-Pin TQFP INDUSTRIAL Family fmax (MHz) | tpd (ns) Ordering Number Package 60 20 ispLSI 1016-60LuI 44-Pin PLCC ispLSI 60 20 ispLSI 1016-60LT441 44-Pin TQFP MILITARY/883 Family fmax (MHz) | tpd (ns) Ordering Number SMD # Package ispLSI 60 20 ispLSI 1016-60LH/883 5962-9476201MXC | 44-Pin JLCC Note: Lattice Semiconductor recognizes the trend in military device procurement towards Table 2-0041-16-isp1016 using SMD compliant devices, as such, ordering by this number is recommended.