IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET IDT54/74FCT273T/AT/CT FEATURES: DESCRIPTION: - - - - The FCT273T is an octal D flip-flop built using an advanced dual metal CMOS technology. The FCT273T has eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. - - - - - Std., A, and C speed grades Low input and output leakage 1 A (max.) CMOS power levels True TTL input and output compatibility * VOH = 3.3V (typ.) * VOL = 0.3V (typ.) High drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: * Industrial: SOIC, SSOP, QSOP * Military: CERDIP, LCC, CERPACK The register is fully edge-triggered. The state of each D input, one setup time before the low-to-high clock transition, is transferred to the corresponding flip-flop's O output. All outputs will be forced low independently of Clock or Data inputs by a low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CP Q D Q D CP CP RD Q D CP RD Q D CP RD Q D CP Q D CP RD RD Q D CP RD Q D CP RD RD MR O0 O1 O2 O3 MILITARY AND INDUSTRIAL TEMPERATURE RANGES O4 O5 O6 O7 MAY 2001 1 c 2001 Integrated Device Technology, Inc. DSC-2568/- IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES D0 3 18 D7 D1 4 17 D6 16 D20-1 SO20-2 SO20-7 SO20-8 E20-1 D1 4 O1 5 O6 O2 6 15 O5 D2 D3 O1 5 O2 6 D2 7 14 D5 D3 8 13 D4 O3 9 12 O4 10 11 CP GND 20 19 1 D7 17 D6 16 O6 7 15 O5 8 14 D5 L20-2 O3 9 10 11 12 13 LCC TOP VIEW PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS(1) Rating Terminal Voltage with Respect to GND 2 18 CERDIP/ SOIC/ SSOP/ QSOP/ CERPACK TOP VIEW Symbol VTERM(2) 3 O7 O7 D4 19 V CC 2 O4 O0 INDEX MR V CC CP 20 O0 1 GND MR D0 PIN CONFIGURATION Unit V Pin Names DN -0.5 to VCC+0.5 V MR Master Reset (Active LOW) C CP Clock Pulse Input (Active Rising Edge) mA ON Data Outputs Max. -0.5 to +7 VTERM(3) Terminal Voltage with Respect to GND TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120 Description Data Inputs 8T-link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. FUNCTION TABLE(1) Operating Mode MR Inputs CP DN Outputs ON Reset (Clear) L X X L 2. Inputs and Vcc terminals only. Load "1" H h H 3. Outputs and I/O terminals only. Load "0" H I L NOTE: 1. H = HIGH voltage level steady state h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level steady state I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition X = Don't Care = LOW-to-HIGH Clock Transition CAPACITANCE (TA = +25OC, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 6 Max. 10 COUT Output Capacitance VOUT = 0V 8 12 Unit pF pF 8T-link NOTE: 1. This parameter is measured at characterization but not tested. 2 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10% Symbol VIH Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level VIL Input LOW Level Guaranteed Logic LOW Level IIH Input HIGH Current(4) VCC = Max. IIL Input LOW Current(4) VCC = Max. II Input HIGH Current(4) VCC = Max., VI = VCC (Max.) VIK Clamp Diode Voltage VCC = Min., IN = -18mA -- -0.7 -1.2 V IOS Short Circuit Current VCC = Max.(3), VO = GND -60 -120 -225 mA VOH Output HIGH Voltage VCC = Min. VIN = VIH or VIL 2.4 3.3 -- V 2 3 -- -- 0.3 0.5 V -- 200 -- mV -- 0.01 1 mA VOL Output LOW Voltage VH Input Hysteresis ICC Quiescent Power Supply Current Min. 2 Typ.(2) -- Max. -- Unit V -- -- 0.8 V VI = 2.7V -- -- 1 A VI = 0.5V -- -- 1 A -- -- 1 A IOH = -6mA MIL IOH = -8mA IND IOH = -12mA MIL IOH = -15mA IND IOL = 32mA MIL IOL = 48mA IND VCC = Min. VIN = VIH or VIL -- VCC = Max. VIN = GND or VCC NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test parameter for this parameter is 5A at TA = -55C. 3 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) IC Total Power Supply Current(6) ICC Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open MR = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle MR = VCC One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle MR = VCC Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle Min. Typ.(2) Max. Unit -- 0.5 2 mA VIN = VCC VIN = GND -- 0.15 0.25 mA/ MHz VIN = VCC VIN = GND -- 1.5 3.5 mA VIN = 3.4V VIN = GND -- 2 5.5 VIN = VCC VIN = GND -- 3.8 7.3(5) VIN = 3.4V VIN = GND -- 6 16.3(5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 4 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL IDT74FCT273T Symbol tPLH tPHL Parameter Propagation Delay CP to ON Condition(1) CL = 50pF RL = 500 Min. (2) IDT74FCT273AT IDT74FCT273CT Max. Min. (2) Max. Min. (2) Max. Unit 2 13 2 7.2 2 5.8 ns 2 7.2 2 6.1 ns tPHL Propagation Delay MR to ON 2 13 tSU Set-up Time HIGH or LOW DN to CP 3 -- 2 -- 2 -- ns tH Hold Time HIGH or LOW DN to CP 2 -- 1.5 -- 1.5 -- ns tW CP Pulse Width HIGH or LOW 7 -- 6 -- 6 -- ns tW MR Pulse Width LOW 7 -- 6 -- 6 -- ns tREM Recovery Time MR to CP 4 -- 2 -- 2 -- ns SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY IDT74FCT273T Symbol tPLH tPHL Parameter Propagation Delay CP to ON Condition(1) CL = 50pF RL = 500 Min. (2) IDT74FCT273AT IDT74FCT273CT Max. Min. (2) Max. Min. (2) Max. Unit 2 15 2 8.3 2 6.5 ns 2 15 2 8.3 2 6.8 ns 3.5 -- 2 -- 2 -- ns tPHL Propagation Delay MR to ON tSU Set-up Time HIGH or LOW DN to CP tH Hold Time HIGH or LOW DN to CP 2 -- 1.5 -- 1.5 -- ns tW CP Pulse Width HIGH or LOW 7 -- 6 -- 6 -- ns tW MR Pulse Width LOW 7 -- 6 -- 6 -- ns tREM Recovery Time MR to CP 5 -- 2.5 -- 2.5 -- ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 5 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC Test 7.0V Switch Open Drain 500 Disable Low V OUT V IN Pulse Generator Enable Low All Other Tests D.U.T. 50pF R Closed T C Open 8-link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500 L O ctal lin k PULSE WIDTH SET-UP, HOLD, AND RELEASE TIMES 3V 1.5V 0V 3V 1.5V 0V DATA INPUT tH t SU TIM ING INPUT ASYNCHRONOUS C ONTROL PRES ET CLEAR ETC. SYNCHRO NOUS CONTRO L PRES ET CLEAR CLOCK ENABLE ETC. t REM t SU LO W -HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW -HIGH PULSE 1.5V 3V 1.5V 0V tH O ctal lin k O ctal lin k PROPAGATION DELAY ENABLE AND DISABLE TIMES ENAB LE SAM E PHASE INPUT TRANSITION t PLH t PH L OUTPUT t PLH OPPOSITE P HASE INPUT TRANSITION t PH L 3V 1.5V 0V DISA BLE 3V CO NTROL INPUT 1.5V t PZL V OH 1.5V V OL OUTPUT NO RM A LLY LO W 3V 1.5V 0V SW ITCH CLOSE D O ctal lin k SW ITCH OPEN 3.5V 3.5V 1.5V 0.3V t PZH OUTPUT NO RM A LLY HIGH 0V t PLZ V OL t PHZ 0.3V V OH 1.5V 0V 0V O ctal lin k NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns 6 IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX Temp. Range FCT XXXX XX X Device Type Package Process Blank B Industrial MIL-STD-883, Class B SO PY Q Industrial Options Small Outline IC (SO20-2) Shink Small Outline Package (SO20-7) Quarter-size Small Outline Package (SO20-8) D E L Military Options CERDIP (D20-1) CERPACK (E20-1) Leadless Chip Carrier (L20-1) 273T 273AT 273CT Octal D Flip-Flop with Master Reset 54 74 - 55C to +125C - 40C to +85C CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 7