1
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES
MAY 2001
2001 Integrated Device Technology, Inc. DSC-2568/-c
IDT54/74FCT273T/AT/CT
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
DESCRIPTION:
The FCT273T is an octal D flip-flop built using an advanced dual metal
CMOS technology. The FCT273T has eight edge-triggered D-type flip-
flops with individual D inputs and O outputs. The common buffered Clock
(CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one set-
up time before the low-to-high clock transition, is transferred to the corre-
sponding flip-flop’s O output.
All outputs will be forced low independently of Clock or Data inputs by
a low voltage level on the MR input. The device is useful for applications
where the true output only is required and the Clock and Master Reset are
common to all storage elements.
FUNCTIONAL BLOCK DIAGRAM
D
CP
Q
RD
D0
O0
D
CP
Q
RD
D1
O1
D
CP
Q
RD
D2
O2
D
CP
Q
RD
D3
O3
D
CP
Q
RD
D4
O4
D
CP
Q
RD
D5
O5
D
CP
Q
RD
D6
O6
D
CP
Q
RD
D7
O7
CP
MR
FEATURES:
− Std., A, and C speed grades
− Low input and output leakage ≤1µA (max.)
− CMOS power levels
− True TTL input and output compatibility
• VOH = 3.3V (typ.)
• VOL = 0.3V (typ.)
− High drive outputs (-15mA IOH, 48mA IOL)
− Meets or exceeds JEDEC standard 18 specifications
− Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
− Power off disable outputs permit “live insertion”
− Available in the following packages:
• Industrial: SOIC, SSOP, QSOP
• Military: CERDIP, LCC, CER PACK
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MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
PIN CONFIGURATION
CERDIP/ SOIC/ SSOP/ QSOP/ CERPACK
TOP VIEW
2
3
1
16
15
14
11
19
18
20
17
13
12
5
6
7
4
D20-1
SO20-2
SO20-7
SO20-8
E20-1
8
9
10
D1
O0
D0
VCC
O1
D3
O2
D2
O3
GND
O7
O6
D7
D6
O5
O4
D5
D4
CP
MR
1
23
4
5
7
9
6
8
10 11 12 13
14
15
16
17
18
1920
L20-2 O6
D7
D6
O5
D5
D
0
O
0
O
3
GND
CP
O
4
D
4
MR
V
CC
O
7
INDEX
D1
O1
D3
O2
D2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Max. Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
8T-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other c onditions abov e those indic ated in t he operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability. No
terminal voltage may exceed Vcc by +0.5V unl es s otherwis e noted.
2. Inputs and Vcc t erminals only.
3. Outputs and I/O term i nal s only .
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 6 10 pF
COUT Output Capacitance VOUT = 0V 8 12 pF
8T-link
NOTE:
1. This paramet er i s measur ed at charact eri zation but not tested.
PIN DESCRIPTION
Pin Names Description
DNData Inputs
MR Master Reset (Active LOW)
CP Clock Pulse Input (Active Rising Edge)
ONData Outputs
FUNCTION TABLE(1)
NOTE:
1. H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑ = LOW-to-HIGH Clock Transition
Inputs Outputs
Operating Mode MR CP DNON
Reset (Clear) L X X L
Load "1" H ↑hH
Load "0" H ↑IL
LCC
TOP VIEW
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IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test parameter for this parameter is ±5µA at TA = -55°C.
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
IIH Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1 µA
IIL Input LOW Current(4) VCC = Max. VI = 0.5V — — ±1 µA
IIInput HIGH Current(4) VCC = Max., VI = VCC (Max.) — — ±1 µA
VIK Clamp Diode Voltage VCC = Min., IN = –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.(3), VO = GND –60 –120 –225 mA
VOH Output HIGH Voltage VCC = Min.
VIN = VIH or VIL IOH = –6mA MIL
IOH = –8mA IND 2.4 3.3 — V
IOH = –12mA MIL
IOH = –15mA IND 23—
V
OL Output LOW Voltage VCC = Min.
VIN = VIH or VIL IOL = 32mA MIL
IOL = 48mA IND —0.30.5V
V
HInput Hysteresis —— 200 — mV
ICC Quiescent Power Supply Current VCC = Max.
VIN = GND or VCC —0.011 mA
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MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply Current TTL
Inputs HIGH VCC = Max.
VIN = 3.4V(3) —0.52mA
I
CCD Dynamic Power Supply Current(4) VCC = Max.
Outputs Open
MR = VCC
One Input Toggling
50% Duty Cycle
VIN = VCC
VIN = GND — 0.15 0.25 mA/
MHz
ICTotal Power Supply Current(6) VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
VIN = VCC
VIN = GND —1.53.5mA
MR = VCC
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VIN = 3.4V
VIN = GND —25.5
V
CC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
VIN = VCC
VIN = GND —3.87.3
(5)
MR = VCC
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
VIN = 3.4V
VIN = GND — 6 16.3(5)
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IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
IDT74FCT273T IDT74FCT273AT IDT74FCT273CT
Symbol Parameter Condition(1) Min. (2) Max.Min. (2) Max.Min. (2) Max.Unit
tPLH
tPHL Propagation Delay
CP to ONCL = 50pF
RL = 500Ω2 13 2 7.2 2 5.8 ns
tPHL Propagation Delay
MR to ON2 13 2 7.2 2 6.1 ns
tSU Set-up Time HIGH or LOW DN to CP 3—2—2—ns
t
H
Hold Time HIGH or LOW DN to CP 2 — 1.5 — 1.5 — ns
tWCP Pulse Width HIGH or LOW 7 — 6 — 6 — ns
tWMR Pulse Width LOW 7—6—6—ns
t
REM Recovery Time MR to CP 4—2—2—ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
IDT74FCT273T IDT74FCT273AT IDT74FCT273CT
Symbol Parameter Condition(1) Min. (2) Max.Min. (2) Max.Min. (2) Max.Unit
tPLH
tPHL Propagation Delay
CP to ONCL = 50pF
RL = 500Ω2 15 2 8.3 2 6.5 ns
tPHL Propagation Delay
MR to ON2 15 2 8.3 2 6.8 ns
tSU Set-up Time HIGH or LOW DN to CP 3.5—2—2—ns
t
H
Hold Time HIGH or LOW DN to CP 2 — 1.5 — 1.5 — ns
tWCP Pulse Width HIGH or LOW 7 — 6 — 6 — ns
tWMR Pulse Width LOW 7—6—6—ns
t
REM Recovery Time MR to CP 5 — 2.5 — 2.5 — ns
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MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
Pulse
Generator
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF 500Ω
500Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TI MI NG
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRO NOU S CONTRO L
tSU tH
tREM
tSU tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPU T TRAN SITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE P HASE
INPU T TRAN SITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
0.3V
tPLZ
tPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
Octal link
Octal link
Octal link
Octal link
Octal link
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES PULSE WIDTH
SWITCH POSITION
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
8-link
DEFINITIONS:
CL = Load capacit ance: incl udes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
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IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET MILITARY AND INDUSTRIAL TEMPERATURE RANGES
CORPORATE HEADQUARTERS for SALES:
2975 Stender Way 800-345-7015 or 408-727-6116
Santa Clara, CA 95054 fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
ID T X X
Tem p. Ra nge XXXX
D evice T ype XX
Package X
Process
SO
PY
Q
Industrial Op tions
S mall Ou tlin e IC (S O20 - 2 )
Shink Sm all O utline Package (SO 20-7)
Q u arter -siz e S ma ll O utline P a c kage (SO 2 0-8 )
O c ta l D F lip -F lo p with Ma s ter Re se t
54
74 – 55°C to +1 25°C
– 40°C to +85°C
D
E
L
M ilita r y Optio n s
CERDIP (D20-1)
CERPACK (E20-1)
Leadless Chip C arrier (L20-1)
Blank
BIndustrial
MIL-STD -883, Class B
FCT
273T
273AT
273CT
