MICROUSBCABLEBK - Raspberry Pi Foundation (NF)

DATASHEET

Raspberry Pi Compute Module (CM1)

Raspberry Pi Compute Module 3 (CM3)

Raspberry Pi Compute Module 3 Lite (CM3L)

Version 1.0, October 2016

Compute Module Datasheet

Table 1: Revision History

Revision Date Description

1.0 13/10/2016 First release

1 Version 1.0

Compute Module Datasheet

Contents

1 Introduction 5

2 Features 6

2.1 Hardware .......................................... 6

2.2 Peripherals ......................................... 6

2.3 Software........................................... 6

3 Block Diagram 7

4 Mechanical Speciﬁcation 9

5 Pin Assignments 11

6 Electrical Speciﬁcation 13

7 Power Supplies 14

7.1 SupplySequencing ..................................... 15

7.2 PowerRequirements .................................... 15

8 Booting 16

9 Peripherals 17

9.1 GPIO ............................................ 17

9.1.1 GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9.1.2 Secondary Memory Interface (SMI) . . . . . . . . . . . . . . . . . . . . . . . . 19

9.1.3 Display Parallel Interface (DPI) . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9.1.4 SD/SDIOInterface................................. 20

9.2 CSI(MIPISerialCamera) ................................. 20

9.3 DSI(MIPISerialDisplay) ................................. 20

9.4 USB............................................. 20

9.5 HDMI............................................ 20

9.6 Composite(TVOut) .................................... 21

10 Thermals 21

10.1TemperatureRange..................................... 21

11 Availability 21

12 Support 21

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Compute Module Datasheet

List of Figures

1 CM1BlockDiagram .................................... 7

2 CM3/CM3LBlockDiagram ................................ 8

3 CM1MechanicalDimensions ............................... 9

4 CM3 and CM3L Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 DigitalIOCharacteristics.................................. 14

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Compute Module Datasheet

List of Tables

1 RevisionHistory ...................................... 1

2 Compute Module SODIMM Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . 11

3 PinFunctions ........................................ 12

4 AbsoluteMaximumRatings ................................ 13

5 DCCharacteristics ..................................... 13

6 Digital I/O Pin AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Power Supply Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8 Mimimum Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9 GPIO Bank0 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10 GPIO Bank1 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Version 1.0

Compute Module Datasheet

1 Introduction

The Raspberry Pi Compute Module (CM1), Compute Module 3 (CM3) and Compute Module 3 Lite

(CM3L) are DDR2-SODIMM-mechanically-compatible System on Modules (SoMs) containing pro-

cessor, memory, eMMC Flash (for CM1 and CM3) and supporting power circuitry. These modules

allow a designer to leverage the Raspberry Pi hardware and software stack in their own custom systems

and form factors. In addition these module have extra IO interfaces over and above what is available on

the Raspberry Pi model A/B boards opening up more options for the designer.

The CM1 contains a BCM2835 processor (as used on the original Raspberry Pi and Raspberry Pi B+

models), 512MByte LPDDR2 RAM and 4Gbytes eMMC Flash. The CM3 contains a BCM2837 pro-

cessor (as used on the Raspberry Pi 3), 1Gbyte LPDDR2 RAM and 4Gbytes eMMC Flash. Finally the

CM3L product is the same as CM3 except the eMMC Flash is not ﬁtted, and the SD/eMMC interface

pins are available for the user to connect their own SD/eMMC device.

Note that the BCM2837 processor is an evolution of the BCM2835 processor. The only real differences

are that the BCM2837 can address more RAM (up to 1Gbyte) and the ARM CPU complex has been

upgraded from a single core ARM11 in BCM2835 to a Quad core Cortex A53 with dedicated 512Kbyte

L2 cache in BCM2837. All IO interfaces and peripherals stay the same and hence the two chips are

largely software and hardware compatible.

The pinout of CM1 and CM3 are identical. Apart from the CPU upgrade and increase in RAM the

other signiﬁcant hwardware differences to be aware of are that CM3 has grown from 30mm to 31mm

in height, the VBAT supply can now draw signiﬁcantly more power under heavy CPU load, and the

HDMI HPD N 1V8 (GPIO46 1V8 on CM1) and EMMC EN N 1V8 (GPIO47 1V8 on CM1) are now

driven from an IO expander rather than the processor. If a designer of a CM1 product has a suitably

speciﬁed VBAT, can accomodate the extra 1mm module height increase and has followed the design

rules with respect to GPIO46 1V8 and GPIO47 1V8 then a CM3 should work ﬁne in a board designed

for a CM1.

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Compute Module Datasheet

2 Features

2.1 Hardware

•Low cost

•Low power

•High availability

•High reliability

–Tested over millions of Raspberry Pis Produced to date

–Module IO pins have 35u hard gold plating

2.2 Peripherals

•48x GPIO

•2x I2C

•2x SPI

•2x UART

•2x SD/SDIO

•1x HDMI 1.3a

•1x USB2 HOST/OTG

•1x DPI (Parallel RGB Display)

•1x NAND interface (SMI)

•1x 4-lane CSI Camera Interface (up to 1Gbps per lane)

•1x 2-lane CSI Camera Interface (up to 1Gbps per lane)

•1x 4-lane DSI Display Interface (up to 1Gbps per lane)

•1x 2-lane DSI Display Interface (up to 1Gbps per lane)

2.3 Software

•ARMv6 (CM1) or ARMv7 (CM3, CM3L) Instruction Set

•Mature and stable Linux software stack

–Latest Linux Kernel support

–Many drivers upstreamed

–Stable and well supported userland

–Full availability of GPU functions using standard APIs

6 Version 1.0

Compute Module Datasheet

3 Block Diagram

512MByte

LPDDR2

200 Pin SODIMM Connector

Core SMPS

GPIO[0:27]

VDD_GPIO0-27

GPIO[28:45]

VDD_GPIO28-45

VBAT

3V3

1V8

VDAC

4GByte eMMC

TVDAC

CSI CAM0

CSI CAM1

2 Lane CSI Camera

4 Lane CSI Camera

BCM2835

DSI DISP0

DSI DISP1

2 Lane DSI Display

4 Lane DSI Display

HDMI TMDS

CLOCK & DATA

CHOKES

RUN

HDMI CEC, DDC

HDMI_HPD_N_1V8 (GPIO46_1V8)

EMMC_EN_N_1V8 (GPIO47_1V8)

JTAG

EMMC_DISABLE_N

USB

USB2

USB_OTGID

HDMI CEC & I2C

3V3 RUN

DAC

GPIO

BANK0

GPIO

BANK1

3V3

SD_CLK

SD_CMD, Dx

SD I/O VOLTAGE 1V8

eMMC I/O

Voltage fixed at

1V8

Figure 1: CM1 Block Diagram

7 Version 1.0

Compute Module Datasheet

1GByte LPDDR2

200 Pin SODIMM Connector

IO Expander

Core SMPS

GPIO[0:27]

VDD_GPIO0-27

GPIO[28:45]

VDD_GPIO28-45

VBAT

3V3

1V8

VDAC

4GByte eMMC

(CM3 only)

TVDAC

CSI CAM0

CSI CAM1

2 Lane CSI Camera

4 Lane CSI Camera

BCM2837

DSI DISP0

DSI DISP1

2 Lane DSI Display

4 Lane DSI Display

HDMI TMDS

CLOCK & DATA

CHOKES

RUN

HDMI CEC, DDC

HDMI_HPD_N_1V8

EMMC_EN_N_1V8

JTAG

EMMC_DISABLE_N

USB

USB2

USB_OTGID

HDMI CEC & I2C

SDX_CMD, Dx (CM3 Lite only)

SDX_CLK (CM3 Lite only)

3V3 RUN

DAC

GPIO

BANK0

GPIO

BANK1

3V3

SD_CLK

SD_CMD, Dx

SDX_VDD (CM3 Lite only)

SD I/O VOLTAGE 1V8

CM3 eMMC I/O

Voltage fixed at

1V8

CM3-Lite SD I/O

Voltage supplied

from SDX_VDD

Figure 2: CM3/CM3L Block Diagram

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Compute Module Datasheet

4 Mechanical Speciﬁcation

The Compute Modules conform to JEDEC MO-224 mechanical speciﬁcation for 200 pin DDR2 (1.8V)

SODIMM modules (with the exception that the CM3, CM3L modules are 31mm in height rather than

30mm of CM1) and therefore should work with the many DDR2 SODIMM sockets available on the

market. (Please note that the pinout of the Compute Module is not the same as a DDR2 SODIMM

module; they are not electrically compatible.)

The SODIMM form factor was chosen as a way to provide the 200 pin connections using a standard,

readily available and low cost connector compatible with low cost PCB manufacture.

The maximum component height on the underside of the Compute Module is 1.2mm.

The maximum component height on the top side of the Compute Module is 1.5mm.

The Compute Module PCB thickness is 1.0mm +/- 0.1mm.

Note that the location and arrangement of components on the Compute Module may change slightly

over time due to revisions for cost and manufacturing considerations; however, maximum component

heights and PCB thickness will be kept as speciﬁed.

Figure 3 gives the CM1 mechanical dimensions. Figure 4 gives the CM3 and CM3L mechanical dimen-

sions.

Figure 3: CM1 Mechanical Dimensions

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Compute Module Datasheet

Figure 4: CM3 and CM3L Mechanical Dimensions

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Compute Module Datasheet

5 Pin Assignments

CM1

CM3-Lite

CM3

CM3-Lite

CM1

SDX_VDD

SDX_CLK

SDX_CMD

SDX_D0

SDX_D1

SDX_D2

SDX_D3

GPIO46_1V8

GPIO47_1V8

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

3V3

GND

VBAT

HDMI_HPD_N_1V8

EMMC_EN_N_1V8

VDD_CORE (DO NOT CONNECT)

GND

1V8

GND

VDAC

USB_DM

GND

HDMI_CEC

HDMI_SDA

HDMI_SCL

RUN

CAM1_DN1

GND

CAM1_DP0

CAM1_DN0

GND

USB_DP

CAM1_DN2

GND

CAM1_CP

CAM1_CN

GND

CAM1_DP1

HDMI_D2_P

GND

CAM1_DP3

CAM1_DN3

GND

CAM1_DP2

HDMI_D0_P

GND

HDMI_D1_N

HDMI_D1_P

GND

HDMI_D2_N

DSI0_CP

GND

HDMI_CLK_N

HDMI_CLK_P

GND

HDMI_D0_N

DSI0_DP1

GND

DSI0_DN0

DSI0_DP0

GND

DSI0_CN

GPIO25

GND

GPIO26

GPIO27

GND

DSI0_DN1

GPIO21

GND

GPIO22

GPIO23

GND

GPIO24

GPIO17

GND

GPIO18

GPIO19

GND

GPIO20

GPIO13

GND

GPIO14

GPIO15

GND

GPIO16

GND

GPIO0-27_VDD

GPIO28-45_VDD

GND

GPIO12

GND

GPIO8

GPIO9

GND

GPIO10

GPIO11

GND

GPIO4

GPIO5

GND

GPIO6

GPIO7

GND

GPIO0

GPIO1

GND

GPIO2

GPIO3

VDAC

3V3

GND

VBAT

VC_TDO

VC_TCK

GND

1V8

GND

TVDAC

USB_OTGID

GND

VC_TRST_N

VC_TDI

VC_TMS

GND

CAM0_CP

CAM0_CN

GND

CAM0_DP1

CAM0_DN1

GND

CAM0_DP0

CAM0_DN0

GND

DSI1_DP1

DSI1_DN1

GND

DSI1_DP3

DSI1_DN3

GND

DSI1_DP2

DSI1_DN2

GND

DSI1_DP0

DSI1_DN0

GND

DSI1_CP

DSI1_CN

GND

GPIO44

GPIO45

GND

GPIO40

GPIO41

GND

GPIO42

GPIO43

GND

GPIO36

GPIO37

GND

GPIO38

GPIO39

GND

GPIO32

GPIO33

GND

GPIO34

GPIO35

GND

GPIO30

GPIO31

GND

GPIO0-27_VDD

GPIO28-45_VDD

GND

KEY

EMMC_DISABLE_N

GND

GPIO28

GPIO29

GND

Table 2: Compute Module SODIMM Connector Pinout

Table 2 gives the Compute Module pinout and Table 3 gives the Compute Module pin functions.

11 Version 1.0

Compute Module Datasheet

Pin Name DIR Voltage Ref PDNaState If Unused Description/Notes

RUN and Boot Control (see text for usage guide)

RUN I 3V3bPull High Leave open Has internal 10k pull up

EMMC DISABLE N I 3V3bPull High Leave open Has internal 10k pull up

EMMC EN N 1V8 O 1V8 Pull High Leave open Has internal 2k2 pull up

GPIO

GPIO[27:0] I/O GPIO0-27 VDD Pull or Hi-ZcLeave open GPIO Bank 0

GPIO[45:28] I/O GPIO28-45 VDD Pull or Hi-ZcLeave open GPIO Bank 1

Primary SD Interfaced,e

SDX CLK O SDX VDD Pull High Leave open Primary SD interface CLK

SDX CMD I/O SDX VDD Pull High Leave open Primary SD interface CMD

SDX Dx I/O SDX VDD Pull High Leave open Primary SD interface DATA

USB Interface

USB Dx I/O - Z Leave open Serial interface

USB OTGID I 3V3 Tie to GND OTG pin detect

HDMI Interface

HDMI SCL I/O 3V3bZfLeave open DDC Clock (5.5V tolerant)

HDMI SDA I/O 3V3bZfLeave open DDC Data (5.5V tolerant)

HDMI CEC I/O 3V3 Z Leave open CEC (has internal 27k pull up)

HDMI CLKx O - Z Leave open HDMI serial clock

HDMI Dx O - Z Leave open HDMI serial data

HDMI HPD N 1V8 I 1V8 Pull High Leave open HDMI hotplug detect

CAM0 (CSI0) 2-lane Interface

CAM0 Cx I - Z Leave open Serial clock

CAM0 Dx I - Z Leave open Serial data

CAM1 (CSI1) 4-lane Interface

CAM1 Cx I - Z Leave open Serial clock

CAM1 Dx I - Z Leave open Serial data

DSI0 (Display 0) 2-lane Interface

DSI0 Cx O - Z Leave open Serial clock

DSI0 Dx O - Z Leave open Serial data

DSI1 (Display 1) 4-lane Interface

DSI1 Cx O - Z Leave open Serial clock

DSI1 Dx O - Z Leave open Serial data

TV Out

TVDAC O - Z Leave open Composite video DAC output

JTAG Interface

TMS I 3V3 Z Leave open Has internal 50k pull up

TRST N I 3V3 Z Leave open Has internal 50k pull up

TCK I 3V3 Z Leave open Has internal 50k pull up

TDI I 3V3 Z Leave open Has internal 50k pull up

TDO O 3V3 O Leave open Has internal 50k pull up

aThe PDN column indicates power-down state (when RUN pin LOW)

bMust be driven by an open-collector driver

cGPIO have software enabled pulls which keep state over power-down

dOnly available on Lite variants

eThe CM will always try to boot from this interface ﬁrst

fRequires external pull-up resistor to 5V as per HDMI spec

Table 3: Pin Functions

12 Version 1.0

Compute Module Datasheet

6 Electrical Speciﬁcation

Caution! Stresses above those listed in Table 4 may cause permanent damage to the device. This is

a stress rating only; functional operation of the device under these or any other conditions above those

listed in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

Symbol Parameter Minimum Maximum Unit

VBAT Core SMPS Supply -0.5 6.0 V

3V3 3V3 Supply Voltage -0.5 4.10 V

1V8 1V8 Supply Voltage -0.5 2.10 V

VDAC TV DAC Supply -0.5 4.10 V

GPIO0-27 VDD GPIO0-27 I/O Supply Voltage -0.5 4.10 V

GPIO28-45 VDD GPIO28-27 I/O Supply Voltage -0.5 4.10 V

SDX VDD Primary SD/eMMC Supply Voltage -0.5 4.10 V

Table 4: Absolute Maximum Ratings

DC Characteristics are deﬁned in Table 5

Symbol Parameter Conditions Minimum Typical Maximum Unit

VIL Input low voltageaVDD IO = 1.8V - - 0.6 V

VDD IO = 2.7V - - 0.8 V

VIH Input high voltageaVDD IO = 1.8V 1.0 - - V

VDD IO = 2.7V 1.3 - - V

IIL Input leakage current TA = +85◦C - - 5 µA

CIN Input capacitance - - 5 - pF

VOL Output low voltagebVDD IO = 1.8V, IOL = -2mA - - 0.2 V

VDD IO = 2.7V, IOL = -2mA - - 0.15 V

VOH Output high voltagebVDD IO = 1.8V, IOH = 2mA 1.6 - - V

VDD IO = 2.7V, IOH = 2mA 2.5 - - V

IOL Output low currentcVDD IO = 1.8V, VO = 0.4V 12 - - mA

VDD IO = 2.7V, VO = 0.4V 17 - - mA

IOH Output high currentcVDD IO = 1.8V, VO = 1.4V 10 - - mA

VDD IO = 2.7V, VO = 2.3V 16 - - mA

RP U Pullup resistor - 50 - 65 kΩ

RP D Pulldown resistor - 50 - 65 kΩ

aHysteresis enabled

bDefault drive strength (8mA)

cMaximum drive strength (16mA)

Table 5: DC Characteristics

13 Version 1.0

Compute Module Datasheet

AC Characteristics are deﬁned in Table 6 and Fig. 5.

Pin Name Symbol Parameter Minimum Typical Maximum Unit

Digital outputs trise 10-90% rise timea- 1.6 - ns

Digital outputs tfall 90-10% fall timea- 1.7 - ns

GPCLK tJOSC Oscillator-derived GPCLK - - 20 ps

cycle-cycle jitter (RMS)

GPCLK tJP LL PLL-derived GPCLK - - 48 ps

cycle-cycle jitter (RMS)

aDefault drive strength, CL = 5pF, VDD IOx = 3.3V

Table 6: Digital I/O Pin AC Characteristics

tfall trise

DIGITAL

OUTPUT

Figure 5: Digital IO Characteristics

7 Power Supplies

The Compute Module has six separate supplies that must be present and powered at all times; you cannot

leave any of them unpowered, even if a speciﬁc interface or GPIO bank is unused. The six supplies are

as follows:

1. VBAT is used to power the BCM283x processor core. It feeds the SMPS that generates the chip

core voltage.

2. 3V3 powers various BCM283x PHYs, IO and the eMMC Flash.

3. 1V8 powers various BCM283x PHYs, IO and SDRAM.

4. VDAC powers the composite (TV-out) DAC.

5. GPIO0-27 VREF powers the GPIO 0-27 IO bank.

6. GPIO28-45 VREF powers the GPIO 28-45 IO bank.

14 Version 1.0

Compute Module Datasheet

Supply Descripion Minimum Typical Maximum Unit

VBAT Core SMPS Supply 2.5 - 5.0 + 5% V

3V3 3V3 Supply Voltage 3.3 - 5% 3.3 3.3 + 5% V

1V8 1V8 Supply Voltage 1.8 - 5% 1.8 1.8 + 5% V

VDAC TV DAC Supplya2.5 - 5% 2.8 3.3 + 5% V

GPIO0-27 VDD GPIO0-27 I/O Supply Voltage 1.8 - 5% - 3.3 + 5% V

GPIO28-45 VDD GPIO28-27 I/O Supply Voltage 1.8 - 5% - 3.3 + 5% V

SDX VDD Primary SD/eMMC Supply Voltage 1.8 - 5% - 3.3 + 5% V

aRequires a clean 2.5-2.8V supply if TV DAC is used, else connect to 3V3

Table 7: Power Supply Operating Ranges

7.1 Supply Sequencing

Supplies should be staggered so that the highest voltage comes up ﬁrst, then the remaining voltages

in descending order. This is to avoid forward biasing internal (on-chip) diodes between supplies, and

causing latch-up. Alternatively supplies can be synchronised to come up at exactly the same time as

long as at no point a lower voltage supply rail voltage exceeds a higher voltage supply rail voltage.

7.2 Power Requirements

Exact power requirements will be heavily dependent upon the individual use case. If an on-chip subsys-

tem is unused, it is usually in a low power state or completely turned off. For instance, if your application

does not use 3D graphics then a large part of the core digital logic will never turn on and need power.

This is also the case for camera and display interfaces, HDMI, USB interfaces, video encoders and

decoders, and so on.

Powerchain design is critical for stable and reliable operation of the Compute Module. We strongly

recommend that designers spend time measuring and verifying power requirements for their particular

use case and application, as well as paying careful attention to power supply sequencing and maximum

supply voltage tolerance.

Table 8 speciﬁes the recommneded minimum power supply outputs required to power the Compute

Module.

15 Version 1.0

Compute Module Datasheet

Supply Minimum Requirement Unit

VBAT (CM1) 2000amW

VBAT (CM3,3L) 3500amW

3V3 250 mA

1V8 250 mA

VDAC 25 mA

GPIO0-27 VDD 50bmA

GPIO28-45 VDD 50bmA

SDX VDD 50bmA

aRecommended minimum. Actual power drawn is very dependent on use-case

bEach GPIO can supply up to 16mA, aggregate current per bank must not exceed 50mA

Table 8: Mimimum Power Supply Requirements

8 Booting

The 4GB eMMC Flash device on CM3 is directly connected to the primary BCM2837 SD/eMMC inter-

face. These connections are not accessible on the module pins. On CM3L this SD interface is available

on the SDX pins.

When initially powered on, or after the RUN pin has been held low and then released, the BCM2837

will try to access the primary SD/eMMC interface. It will then look for a ﬁle called bootcode.bin on the

primary partition (which must be FAT) to start booting the system. If it cannot access the SD/eMMC

device or the boot code cannot be found, it will fall back to waiting for boot code to be written to it over

USB; in other words, its USB port is in slave mode waiting to accept boot code from a suitable host.

A USB boot tool is available on Github which allows a host PC running Linux to write the BCM2837

boot code over USB to the module. That boot code then runs and provides access to the SD/eMMC as a

USB mass storage device, which can then be read and written using the host PC. Note that a Raspberry Pi

can be used as the host machine. For those using Windows a precompiled and packeged tool is available.

For more information see here.

The Compute Module has a pin called EMMC DISABLE N which when shorted to GND will disable

the SD/eMMC interface (by physically disconnecting the SD CMD pin), forcing BCM2837 to boot from

USB. Note that when the eMMC is disabled in this way, it takes a couple of seconds from powering up

for the processor to stop attempting to talk to the SD/eMMC device and fall back to booting from USB.

Note that once booted over USB, BCM2837 needs to re-enable the SD/eMMC device (by releasing

EMMC DISABLE N) to allow access to it as mass storage. It expects to be able to do this by driving

the EMMC EN N 1V8 pin LOW, which at boot is initially an input with a pull up to 1V8. If an end user

wishes to add the ability to access the SD/eMMC over USB in their product, similar circuitry to that

used on the Compute Module IO Board to enable/disable the USB boot and SD/eMMC must be used;

that is, EMMC DISABLE N pulled low via MOSFET(s) and released again by MOSFET, with the gate

controlled by EMMC EN N 1V8. Ensure you use MOSFETs suitable for switching at 1.8V (i.e. use a

device with gate threshold voltage, Vt, suitable for 1.8V switching).

16 Version 1.0

Compute Module Datasheet

9 Peripherals

9.1 GPIO

BCM283x has in total 54 GPIO lines in 3 separate voltage banks. All GPIO pins have at least two

alternative functions within the SoC. When not used for the alternate peripheral function, each GPIO

pin may be set as an input (optionally as an interrupt) or an output. The alternate functions are usually

peripheral I/Os, and most peripherals appear twice to allow ﬂexibility on the choice of I/O voltage.

On CM1, CM3 and CM3L bank2 is used on the module to connect to the eMMC device and, on CM3

and CM3L, for an on-board I2C bus (to talk to the core SMPS and control the special function pins). On

CM3L most of bank 2 is exposed to allow a user to connect their choice of SD card or eMMC device (if

required).

Bank0 and 1 GPIOs are available for general use. GPIO0 to GPIO27 are bank 0 and GPIO28-45 make

up bank1. GPIO0-27 VDD is the power supply for bank0 and GPIO28-45 VDD is the power supply for

bank1. SDX VDD is the supply for bank2 on CM3L. These supplies can be in the range 1.8V-3.3V (see

Table 7) and are not optional; each bank must be powered, even when none of the GPIOs for that bank

are used.

Note that the HDMI HPD N 1V8 and EMMC EN N 1V8 pins (on CM1 these were called GPIO46 1V8

and GPIO47 1V8 respectively) are 1.8V IO and are used for special functions (HDMI hot plug de-

tect and boot control respectively). Please do not use these pins for any other purpose, as the

software for the Compute Module will always expect these pins to have these special functions. If

they are unused please leave them unconnected.

All GPIOs except GPIO28, 29, 44 and 45 have weak in-pad pull-ups or pull-downs enabled when the

device is powered on. It is recommended to add off-chip pulls to GPIO28, 29, 44 and 45 to make sure

they never ﬂoat during power on and initial boot.

17 Version 1.0

Compute Module Datasheet

9.1.1 GPIO Alternate Functions

Default

GPIO Pull ALT0 ALT1 ALT2 ALT3 ALT4 ALT5

0 High SDA0 SA5 PCLK - - -

1 High SCL0 SA4 DE - - -

2 High SDA1 SA3 LCD VSYNC - - -

3 High SCL1 SA2 LCD HSYNC - - -

4 High GPCLK0 SA1 DPI D0 - - ARM TDI

5 High GPCLK1 SA0 DPI D1 - - ARM TDO

6 High GPCLK2 SOE N DPI D2 - - ARM RTCK

7 High SPI0 CE1 N SWE N DPI D3 - - -

8 High SPI0 CE0 N SD0 DPI D4 - - -

9 Low SPI0 MISO SD1 DPI D5 - - -

10 Low SPI0 MOSI SD2 DPI D6 - - -

11 Low SPI0 SCLK SD3 DPI D7 - - -

12 Low PWM0 SD4 DPI D8 - - ARM TMS

13 Low PWM1 SD5 DPI D9 - - ARM TCK

14 Low TXD0 SD6 DPI D10 - - TXD1

15 Low RXD0 SD7 DPI D11 - - RXD1

16 Low FL0 SD8 DPI D12 CTS0 SPI1 CE2 N CTS1

17 Low FL1 SD9 DPI D13 RTS0 SPI1 CE1 N RTS1

18 Low PCM CLK SD10 DPI D14 - SPI1 CE0 N PWM0

19 Low PCM FS SD11 DPI D15 - SPI1 MISO PWM1

20 Low PCM DIN SD12 DPI D16 - SPI1 MOSI GPCLK0

21 Low PCM DOUT SD13 DPI D17 - SPI1 SCLK GPCLK1

22 Low SD0 CLK SD14 DPI D18 SD1 CLK ARM TRST -

23 Low SD0 CMD SD15 DPI D19 SD1 CMD ARM RTCK -

24 Low SD0 DAT0 SD16 DPI D20 SD1 DAT0 ARM TDO -

25 Low SD0 DAT1 SD17 DPI D21 SD1 DAT1 ARM TCK -

26 Low SD0 DAT2 TE0 DPI D22 SD1 DAT2 ARM TDI -

27 Low SD0 DAT3 TE1 DPI D23 SD1 DAT3 ARM TMS -

Table 9: GPIO Bank0 Alternate Functions

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Default

GPIO Pull ALT0 ALT1 ALT2 ALT3 ALT4 ALT5

28 None SDA0 SA5 PCM CLK FL0 - -

29 None SCL0 SA4 PCM FS FL1 - -

30 Low TE0 SA3 PCM DIN CTS0 - CTS1

31 Low FL0 SA2 PCM DOUT RTS0 - RTS1

32 Low GPCLK0 SA1 RING OCLK TXD0 - TXD1

33 Low FL1 SA0 TE1 RXD0 - RXD1

34 High GPCLK0 SOE N TE2 SD1 CLK - -

35 High SPI0 CE1 N SWE N - SD1 CMD - -

36 High SPI0 CE0 N SD0 TXD0 SD1 DAT0 - -

37 Low SPI0 MISO SD1 RXD0 SD1 DAT1 - -

38 Low SPI0 MOSI SD2 RTS0 SD1 DAT2 - -

39 Low SPI0 SCLK SD3 CTS0 SD1 DAT3 - -

40 Low PWM0 SD4 - SD1 DAT4 SPI2 MISO TXD1

41 Low PWM1 SD5 TE0 SD1 DAT5 SPI2 MOSI RXD1

42 Low GPCLK1 SD6 TE1 SD1 DAT6 SPI2 SCLK RTS1

43 Low GPCLK2 SD7 TE2 SD1 DAT7 SPI2 CE0 N CTS1

44 None GPCLK1 SDA0 SDA1 TE0 SPI2 CE1 N -

45 None PWM1 SCL0 SCL1 TE1 SPI2 CE2 N -

Table 10: GPIO Bank1 Alternate Functions

Table 9 and Table 10 detail the default pin pull state and available alternate GPIO functions. Most of

these alternate peripheral functions are described in detail in the Broadcom Peripherals Speciﬁcation

document and have Linux drivers available.

9.1.2 Secondary Memory Interface (SMI)

The SMI peripheral is an asynchronous NAND type bus supporting Intel mode80 type transfers at 8 or

16 bit widths and available in the ALT1 positions on GPIO banks 0 and 1 (see Table 9 and Table 10). It

is not publicly documented in the Broadcom Peripherals Speciﬁcation but a Linux driver is available in

the Raspberry Pi Github Linux repository (bcm2835 smi.c in linux/drivers/misc).

9.1.3 Display Parallel Interface (DPI)

A standard parallel RGB (DPI) interface is available on bank 0 GPIOs. This up-to-24-bit parallel inter-

face can support a secondary display. Again this interface is not documented in the Broadcom Peripher-

als Speciﬁcation but documentation can be found here.

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9.1.4 SD/SDIO Interface

The BCM283x supports two SD card interfaces, SD0 and SD1.

The ﬁrst (SD0) is a proprietary Broadcom controller that does not support SDIO and is the primary

interface used to boot and talk to the eMMC or SDX x signals.

The second interface (SD1) is standards compliant and can interface to SD, SDIO and eMMC devices;

for example on a Raspberry Pi 3 it is used to talk to the on-board BCM43438 WiFi device in SDIO

mode.

Both interfaces can support speeds up to 50MHz single ended (SD High Speed Mode).

9.2 CSI (MIPI Serial Camera)

Currently the CSI interface is not openly documented and only CSI camera sensors supported by the

ofﬁcial Raspberry Pi ﬁrmware will work with this interface. Supported sensors are the OmniVision

OV5647 and Sony IMX219.

It is recommended to attach other cameras via USB.

9.3 DSI (MIPI Serial Display)

Currently the DSI interface is not openly documented and only DSI displays supported by the ofﬁcial

Raspberry Pi ﬁrmware will work with this interface.

Displays can also be added via the parallel DPI interface which is available as a GPIO alternate function

- see Table 9 and Section 9.1.3

9.4 USB

The BCM283x USB port is On-The-Go (OTG) capable. If using either as a ﬁxed slave or ﬁxed master,

please tie the USB OTGID pin to ground.

The USB port (Pins USB DP and USB DM) must be routed as 90 ohm differential PCB traces.

Note that the port is capable of being used as a true OTG port however there is no ofﬁcial documentation.

Some users have had success making this work.

9.5 HDMI

BCM283x supports HDMI V1.3a.

It is recommended that users follow a similar arrangement to the Compute Module IO Board circuitry

for HDMI output.

The HDMI CK P/N (clock) and D0-D2 P/N (data) pins must each be routed as matched length 100

ohm differential PCB traces. It is also important to make sure that each differential pair is closely phase

matched. Finally, keep HDMI traces well away from other noise sources and as short as possible.

Failure to observe these design rules is likely to result in EMC failure.

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9.6 Composite (TV Out)

The TVDAC pin can be used to output composite video (PAL or NTSC). Please route this signal away

from noise sources and use a 75 ohm PCB trace.

Note that the TV DAC is powered from the VDAC supply which must be a clean supply of 2.5-2.8V. It

is recommended users generate this supply from 3V3 using a low noise LDO.

If the TVDAC output is not used VDAC can be connected to 3V3, but it must be powered even if the

TV-out functionality is unused.

10 Thermals

The BCM283x SoC employs DVFS (Dynamic Voltage and Frequency Scaling) on the core voltage.

When the processor is idle (low CPU utilisation), it will reduce the core frequency and voltage to reduce

current draw and heat output. When the core utilisation exceeds a certain threshold the core votlage

is increased and the core frequency is boosted to the maximum working frerquency. The voltage and

frequency are throttled back when the CPU load reduces back to an ’idle’ level OR when the silicon

temperature as mesured by the on-chip temperature sensor exceeds 85C (thermal throttling).

A designer must pay careful attention to the thermal design of products using the CM3/CM3L so that

performance is not artiﬁcially curtailed due to the processor thermal throttling, as the Quad ARM com-

plex in the BCM2837 can generate signiﬁcant heat output.

10.1 Temperature Range

The operating temperature range of the module is set by the lowest maximum and highest minimum of

any of the components used.

The eMMC and LPDDR2 have the narrowest range, these are rated for -25 to +80 degrees Celsius.

Therefore the nominal range for the CM3 and CM3L is -25C to +80C.

However, this range is the maximum for the silicon die; therefore, users would have to take into account

the heat generated when in use and make sure this does not cause the temperature to exceed 80 degrees

Celsius.

11 Availability

Raspberry Pi guarantee availability of CM1, CM3 and CM3 Lite until at least January 2023.

12 Support

For support please see the hardware documentation section of the Raspberry Pi website and post ques-

tions to the Raspberry Pi forum.

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