FN6624 Rev 1.00 Page 1 of 3
November 11, 2011
FN6624
Rev 1.00
November 11, 2011
ISL22346WM
Quad Digitally Controlled Potentiometers (XDCP™) Low Noise, Low Power I2C
Bus, 128 Taps
DATASHEET
The ISL22346WMVEP integrates four digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up, the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as a three-terminal potentiometers
or as a two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments and
signal processing.
Device Information
The specifications for an Enhanced Product (EP) device are
defined in a Vendor Item Drawing (VID), which is controlled
by the Defense Logistics Agency (DLA). “Hot-links” to the
applicable VID and other supporting application information
are provided on our website.
Pinout
Features
• Specifications per DSCC VID V62/08605-01XE
• Full Mil-Temp Electrical Performance from -55°C to +125°C
• Controlled Baseline with One Wafer Fabrication Site and
One Assembly/Test Site
• Full Homogeneous Lot Processing in Wafer Fab
• No Combination of Wafer Fabrication Lots in Assembly
• Full Traceability Through Assembly and Test by
Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a COTS Component
• Four Potentiometers in One Package
•128 Resistor Taps
•I
2C Serial Interface
- Three Address Pins, Up To Eight Devices/Bus
• Non-volatile Storage of Wiper Position
• Wiper Resistance: 70 Typical @ 3.3V
• Shutdown Mode
• Shutdown Current 5µA Max
• Power Supply: 2.7V to 5.5V
•10k Total Resistance
• High Reliability
- Endurance: 1,000,000 Data Changes Per Bit Per
Register
- Register Data Retention:
- 10 years @ T +125°C
- 15 years @ T +90°C
- 50 years @ T +55°C
• 20 Ld TSSOP
ISL22346WMVEP
(20 LD TSSOP)
TOP VIEW
RW0
RL0
RH0
SHDN
VCC
A1
A0
RH1
RL1
RW1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
RH3
RL3
RW3
A2
SCL
SDA
GND
RW2
RL2
RH2
Ordering Information
VENDOR PART NUMBER
(Notes 1, 2) VENDOR ITEM DRAWING PART MARKING
RESISTANCE OPTION
(k)
TEMP.
RANGE (°C) PACKAGE
PKG.
DWG. #
ISL22346WMVEP V62/08605-01XE 22346 WMVEP 10 -55 to +125 20 Ld TSSOP M20.173
NOTES:
1. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Devices must be procured to the VENDOR PART NUMBER.
ISL22346WM
FN6624 Rev 1.00 Page 2 of 3
November 11, 2011
Block Diagram
I2C
INTERFACE
VCC
RH0
RH1
RH2
RH3
GND
RL0
RL1
RL2
RL3
RW0
RW1
RW2
RW3
SCL
SDA
A0
A1
A2
WR3
WR2
WR1
WR0
SHDN
POWER-UP
INTERFACE,
CONTROL
AND STATUS
LOGIC
NON-
VOLATILE
REGISTERS
Pin Descriptions
TSSOP PIN SYMBOL DESCRIPTION
1 RH3 “High” terminal of DCP3
2 RL3 “Low” terminal of DCP3
3 RW3 “Wiper” terminal of DCP3
4 A2 Device address input for the I2C interface
5 SCL Open drain I2C interface clock input
6 SDA Open drain Serial data I/O for the I2C interface
7 GND Device ground pin
8 RW2 “Wiper” terminal of DCP2
9 RL2 “Low” terminal of DCP2
10 RH2 “High” terminal of DCP2
11 RW1 “Wiper” terminal of DCP1
12 RL1 “Low” terminal of DCP1
13 RH1 “High” terminal of DCP1
14 A0 Device address input for the I2C interface
15 A1 Device address input for the I2C interface
16 VCC Power supply pin
17 SHDN Shutdown active low input
18 RH0 “High” terminal of DCP0
19 RL0 “Low” terminal of DCP0
20 RW0 “Wiper” terminal of DCP0
FN6624 Rev 1.00 Page 3 of 3
November 11, 2011
ISL22346WM
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2007-2011. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
Thin Shrink Small Outline Plastic Packages (TSSOP)
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.252 0.260 6.40 6.60 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N20 207
0o8o0o8o-
Rev. 1 6/98