2009 Integrated Device Technology, Inc. DSC-6229/7
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 May 4, 2009
DUAL CHANNEL T1/E1/J1 LONG
HAUL/SHORT HAUL LINE INTER-
FACE UNIT
IDT82V2082
FEATURES:
• Dual channel T1/E1/J1 long haul/short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
• Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024
KHz
• Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
• Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
- AT&T Pub 62411
• Software programmable or hardware selectable on:
- Wave-shaping templates for short haul and long haul LBO (Line Build
Out)
- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1: 75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials for E1
- QRSS (Quasi Random Sequence Signals) generation and detection
with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
• Cable attenuation indication
• Adaptive receive sensitivity
• Non-intrusive monitoring per ITU G.772 specification
• Short circuit protection and internal protection diode for line
drivers
• LOS (Loss Of Signal) and AIS (Alarm Indication Signal) detection
• JTAG interface
• Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces and hardware control mode
• Pin compatible to 82V2042E T1/E1/J1 Short Haul LIU and
82V2052E E1 Short Haul LIU
• Available in 80-pin TQFP and 81-pin FPBGA
Green package options available
.
DESCRIPTION:
The IDT82V2082 can be configured as a dual channel T1, E1 or J1 Line
Interface Unit. In receive path, an Adaptive Equalizer is integrated to
remove the distortion introduced by the cable attenuation. The IDT82V2082
also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and
detects and reports the LOS conditions. In transmit path, there is an AMI/
B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter
Attenuator, which can be placed in either the receive path or the transmit
path. The Jitter Attenuator can also be disabled. The IDT82V2082 supports
both Single Rail and Dual Rail system interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
the chip, and different types of loopbacks can be set according to the appli-
cations. Four different kinds of line terminating impedance, 75 Ω,100 Ω,
110 Ω and 120 Ω are selectable on a per channel basis. The chip also pro-
vides driver short-circuit protection and internal protection diode and sup-
ports JTAG boundary scanning. The chip can be controlled by either
software or hardware.
The IDT82V2082 can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
FUNCTIONAL BLOCK DIAGRAM 2 May 4, 2009
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL BLOCK DIAGRAM
Figure-1 Block Diagram
LOSn
RCLKn
RDn/RDPn
CVn/RDNn
RTIPn
RRINGn
TCLKn
TDn/TDPn
TDNn
TTIPn
TRINGn
Jitter
Attenuator
PRBS Generator
IBLC Generator
TAOS
PRBS Detector
IBLC Detector
Clock
Generator Register
Files
Software Control Interface Pin Control
MODE[1:0]
TERMn
RXTXM[1:0]
PULSn[3:0]
EQn
PATTn[1:0]
JA[1:0]
MONTn
LPn[1:0]
THZ
RCLKE
RPDn
RST
INT
CS
SDO
SCLK
R/W/WR/SDI
RD/DS/SCLKE
A[5:0]
D[7:0]
One of the Two Identical Channels
Data and
Clock
Recovery
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detector
B8ZS/
HDB3/AMI
Decoder
Digital
Loopback
Remote
Loopback
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Waveform
Shaper/LBO
Line
Driver
Analog
Loopback
Receiver
Internal
Termination
Transmitter
Internal
Termination
TDO
TRST
TDI
TMS
TCK
VDDIO
VDDD
VDDA
VDDT
VDDR
JTAG TAP
G.772
Monitor
MCLK
Table of Contents 3 May 4, 2009
1 IDT82V2082 PIN CONFIGURATIONS .......................................................................................... 9
2 PIN DESCRIPTION ..................................................................................................................... 11
3 FUNCTIONAL DESCRIPTION .................................................................................................... 19
3.1 CONTROL MODE SELECTION ....................................................................................... 19
3.2 T1/E1/J1 MODE SELECTION .......................................................................................... 19
3.3 TRANSMIT PATH ............................................................................................................. 19
3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 19
3.3.2 ENCODER .............................................................................................................. 19
3.3.3 PULSE SHAPER .................................................................................................... 19
3.3.3.1 Preset Pulse Templates .......................................................................... 19
3.3.3.2 LBO (Line Build Out) ............................................................................... 20
3.3.3.3 User-Programmable Arbitrary Waveform ................................................ 21
3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 25
3.3.5 TRANSMIT PATH POWER DOWN ........................................................................ 26
3.4 RECEIVE PATH ............................................................................................................... 26
3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 26
3.4.2 LINE MONITOR ...................................................................................................... 27
3.4.3 ADAPTIVE EQUALIZER......................................................................................... 28
3.4.4 RECEIVE SENSITIVITY ......................................................................................... 28
3.4.5 DATA SLICER ........................................................................................................ 28
3.4.6 CDR (Clock & Data Recovery)................................................................................ 28
3.4.7 DECODER .............................................................................................................. 28
3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 28
3.4.9 RECEIVE PATH POWER DOWN........................................................................... 28
3.4.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 29
3.5 JITTER ATTENUATOR .................................................................................................... 30
3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 30
3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 30
3.6 LOS AND AIS DETECTION ............................................................................................. 31
3.6.1 LOS DETECTION................................................................................................... 31
3.6.2 AIS DETECTION .................................................................................................... 34
3.7 TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 35
3.7.1 TRANSMIT ALL ONES ........................................................................................... 35
3.7.2 TRANSMIT ALL ZEROS......................................................................................... 35
3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 35
3.8 LOOPBACK ...................................................................................................................... 35
3.8.1 ANALOG LOOPBACK ............................................................................................ 35
Table of Contents
4 May 4, 2009
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.8.2 DIGITAL LOOPBACK ............................................................................................. 35
3.8.3 REMOTE LOOPBACK............................................................................................ 36
3.8.4 INBAND LOOPBACK.............................................................................................. 37
3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 37
3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 37
3.8.4.3 Automatic Remote Loopback .................................................................. 38
3.9 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 39
3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 39
3.9.2 ERROR DETECTION AND COUNTING ................................................................ 39
3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 40
3.10 LINE DRIVER FAILURE MONITORING ........................................................................... 40
3.11 MCLK AND TCLK ............................................................................................................. 41
3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 41
3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 41
3.12 MICROCONTROLLER INTERFACES ............................................................................. 42
3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 42
3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 42
3.13 INTERRUPT HANDLING .................................................................................................. 43
3.14 5V TOLERANT I/O PINS .................................................................................................. 44
3.15 RESET OPERATION ........................................................................................................ 44
3.16 POWER SUPPLY ............................................................................................................. 44
4 PROGRAMMING INFORMATION .............................................................................................. 45
4.1 REGISTER LIST AND MAP ............................................................................................. 45
4.2 Reserved Registers ..........................................................................................................45
4.3 REGISTER DESCRIPTION .............................................................................................. 47
4.3.1 GLOBAL REGISTERS............................................................................................ 47
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 48
4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 48
4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 49
4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 51
4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 53
4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 56
4.3.8 LINE STATUS REGISTERS ................................................................................... 59
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 62
4.3.10 COUNTER REGISTERS ........................................................................................ 63
5 HARDWARE CONTROL PIN SUMMARY .................................................................................. 64
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 66
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 67
6.2 JTAG DATA REGISTER ................................................................................................... 67
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 67
6.2.2 BYPASS REGISTER (BR)...................................................................................... 67
5 May 4, 2009
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 67
6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 67
7 TEST SPECIFICATIONS ............................................................................................................ 70
8 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 83
8.1 SERIAL INTERFACE TIMING .......................................................................................... 83
8.2 PARALLEL INTERFACE TIMING ..................................................................................... 84
List of Tables 6 May 4, 2009
Table-1 Pin Description.............................................................................................................. 11
Table-2 Transmit Waveform Value For E1 75 Ohm ................................................................... 22
Table-3 Transmit Waveform Value For E1 120 Ohm ................................................................. 22
Table-4 Transmit Waveform Value For T1 0~133 ft................................................................... 22
Table-5 Transmit Waveform Value For T1 133~266 ft............................................................... 23
Table-6 Transmit Waveform Value For T1 266~399 ft............................................................... 23
Table-7 Transmit Waveform Value For T1 399~533 ft............................................................... 23
Table-8 Transmit Waveform Value For T1 533~655 ft............................................................... 23
Table-9 Transmit Waveform Value For J1 0~655 ft ................................................................... 24
Table-10 Transmit Waveform Value For DS1 0 dB LBO.............................................................. 24
Table-11 Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 24
Table-12 Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 24
Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 25
Table-14 Impedance Matching for Transmitter ............................................................................ 25
Table-15 Impedance Matching for Receiver ................................................................................ 26
Table-16 Criteria of Starting Speed Adjustment........................................................................... 30
Table-17 LOS Declare and Clear Criteria for Short Haul Mode ................................................... 32
Table-18 LOS Declare and Clear Criteria for Long Haul Mode.................................................... 33
Table-19 AIS Condition ................................................................................................................ 34
Table-20 Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 35
Table-21 EXZ Definition ............................................................................................................... 39
Table-22 Interrupt Event............................................................................................................... 43
Table-23 Global Register List and Map........................................................................................ 45
Table-24 Per Channel Register List and Map .............................................................................. 46
Table-25 ID: Device Revision Register ........................................................................................ 47
Table-26 RST: Reset Register ..................................................................................................... 47
Table-27 GCF: Global Configuration Register ............................................................................. 47
Table-28 INTCH: Interrupt Channel Indication Register............................................................... 47
Table-29 TERM: Transmit and Receive Termination Configuration Register .............................. 48
Table-30 JACF: Jitter Attenuation Configuration Register ........................................................... 48
Table-31 TCF0: Transmitter Configuration Register 0 ................................................................. 49
Table-32 TCF1: Transmitter Configuration Register 1 ................................................................. 50
Table-33 TCF2: Transmitter Configuration Register 2 ................................................................. 50
Table-34 TCF3: Transmitter Configuration Register 3 ................................................................. 51
Table-35 TCF4: Transmitter Configuration Register 4 ................................................................. 51
Table-36 RCF0: Receiver Configuration Register 0..................................................................... 51
Table-37 RCF1: Receiver Configuration Register 1..................................................................... 52
Table-38 RCF2: Receiver Configuration Register 2..................................................................... 53
Table-39 MAINT0: Maintenance Function Control Register 0...................................................... 53
Table-40 MAINT1: Maintenance Function Control Register 1...................................................... 54
Table-41 MAINT2: Maintenance Function Control Register 2...................................................... 54
List of Tables
7 May 4, 2009
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-42 MAINT3: Maintenance Function Control Register 3...................................................... 54
Table-43 MAINT4: Maintenance Function Control Register 4...................................................... 55
Table-44 MAINT5: Maintenance Function Control Register 5...................................................... 55
Table-45 MAINT6: Maintenance Function Control Register 6...................................................... 55
Table-46 INTM0: Interrupt Mask Register 0 ................................................................................. 56
Table-47 INTM1: Interrupt Masked Register 1 ............................................................................. 57
Table-48 INTES: Interrupt Trigger Edge Select Register ............................................................. 58
Table-49 STAT0: Line Status Register 0 (real time status monitor)............................................. 59
Table-50 STAT1: Line Status Register 1 (real time status monitor)............................................. 60
Table-51 INTS0: Interrupt Status Register 0................................................................................ 62
Table-52 INTS1: Interrupt Status Register 1................................................................................ 63
Table-53 CNT0: Error Counter L-byte Register 0......................................................................... 63
Table-54 CNT1: Error Counter H-byte Register 1 ........................................................................ 63
Table-55 Hardware Control Pin Summary ................................................................................... 64
Table-56 Instruction Register Description .................................................................................... 67
Table-57 Device Identification Register Description..................................................................... 67
Table-58 TAP Controller State Description .................................................................................. 68
Table-59 Absolute Maximum Rating ............................................................................................ 70
Table-60 Recommended Operation Conditions ........................................................................... 71
Table-61 Power Consumption...................................................................................................... 71
Table-62 DC Characteristics ........................................................................................................ 71
Table-63 E1 Receiver Electrical Characteristics .......................................................................... 72
Table-64 T1/J1 Receiver Electrical Characteristics...................................................................... 73
Table-65 E1 Transmitter Electrical Characteristics ...................................................................... 74
Table-66 T1/J1 Transmitter Electrical Characteristics.................................................................. 75
Table-67 Transmitter and Receiver Timing Characteristics ......................................................... 76
Table-68 Jitter Tolerance ............................................................................................................. 77
Table-69 Jitter Attenuator Characteristics.................................................................................... 79
Table-70 JTAG Timing Characteristics ........................................................................................ 81
Table-71 Serial Interface Timing Characteristics ......................................................................... 83
Table-72 Non-Multiplexed Motorola Read Timing Characteristics ............................................... 84
Table-73 Non-Multiplexed Motorola Write Timing Characteristics ............................................... 85
Table-74 Non-Multiplexed Intel Read Timing Characteristics ...................................................... 86
Table-75 Non-Multiplexed Intel Write Timing Characteristics ...................................................... 87
List of Figures 8 May 4, 2009
Figure-1 Block Diagram ................................................................................................................. 2
Figure-2 IDT82V2082 TQFP80 Package Pin Assignment ............................................................ 9
Figure-3 IDT82V2082 FPBGA81 Package Pin Assignment (Top View) ..................................... 10
Figure-4 E1 Waveform Template Diagram .................................................................................. 20
Figure-5 E1 Pulse Template Test Circuit ..................................................................................... 20
Figure-6 DSX-1 Waveform Template .......................................................................................... 20
Figure-7 T1 Pulse Template Test Circuit ..................................................................................... 20
Figure-8 Receive Path Function Block Diagram .......................................................................... 26
Figure-9 Transmit/Receive Line Circuit ....................................................................................... 27
Figure-10 Monitoring Receive Line in Another Chip ...................................................................... 27
Figure-11 Monitor Transmit Line in Another Chip .......................................................................... 27
Figure-12 G.772 Monitoring Diagram ............................................................................................ 29
Figure-13 Jitter Attenuator ............................................................................................................. 30
Figure-14 LOS Declare and Clear .................................................................................................31
Figure-15 Analog Loopback .......................................................................................................... 36
Figure-16 Digital Loopback ............................................................................................................ 36
Figure-17 Remote Loopback ......................................................................................................... 37
Figure-18 Auto Report Mode ......................................................................................................... 39
Figure-19 Manual Report Mode ..................................................................................................... 40
Figure-20 TCLK Operation Flowchart ............................................................................................ 41
Figure-21 Serial Microcontroller Interface Function Timing ........................................................... 42
Figure-22 JTAG Architecture ......................................................................................................... 66
Figure-23 JTAG State Diagram ..................................................................................................... 69
Figure-24 Transmit System Interface Timing ................................................................................ 77
Figure-25 Receive System Interface Timing ................................................................................. 77
Figure-26 E1 Jitter Tolerance Performance .................................................................................. 78
Figure-27 T1/J1 Jitter Tolerance Performance .............................................................................. 79
Figure-28 E1 Jitter Transfer Performance ..................................................................................... 80
Figure-29 T1/J1 Jitter Transfer Performance ................................................................................ 81
Figure-30 JTAG Interface Timing .................................................................................................. 82
Figure-31 Serial Interface Write Timing .........................................................................................83
Figure-32 Serial Interface Read Timing with SCLKE=1 ................................................................ 83
Figure-33 Serial Interface Read Timing with SCLKE=0 ................................................................ 83
Figure-34 Non-Multiplexed Motorola Read Timing ........................................................................ 84
Figure-35 Non-Multiplexed Motorola Write Timing ........................................................................ 85
Figure-36 Non-Multiplexed Intel Read Timing ............................................................................... 86
Figure-37 Non-Multiplexed Intel Write Timing ............................................................................... 87
List of Figures
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
IDT82V2082 PIN CONFIGURATIONS 9 May 4, 2009
1 IDT82V2082 PIN CONFIGURATIONS
Figure-2 IDT82V2082 TQFP80 Package Pin Assignment
IDT82V2082
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
49
50
51
52
53
54
55
56
21
24
22
23
25
28
26
27
29
32
30
31
80
77
79
78
76
73
75
74
72
69
71
70
68
65
67
66
A5 / EQ2
A4 / RPD2
A3 / EQ1
A2 / RPD1
A1 / PATT21
A0 / PATT20
D7 / PULS13
D6 / PULS12
D5 / PULS11
D4 / PULS10
D3 / PULS23
D2 / PULS22
D1 / PULS21
D0 / PULS20
SCLK / PATT11
DS / RD / SCLKE / PATT10
R/W / WR / SDI / LP21
SDO / LP20
CS / LP11
INT / LP10
VDDT1
TRING1
TTIP1
GNDT1
GNDR1
RRING1
RTIP1
VDDR1
VDDA
IC
REF
GNDA
VDDR2
RTIP2
RRING2
GNDR2
GNDT2
TTIP2
TRING2
VDDT2
20
19
18
17
40
39
38
37
36
35
34
33
60
59
58
57
61
62
63
64
VDDIO
GNDIO
TCLK1
TDP1 / TD1
TDN1
RCLK1
RDP1 / RD1
RDN1 / CV1
LOS1
VDDD
MCLK
GNDD
LOS2
RDN2 / CV2
RDP2 / RD2
RCLK2
TDN2
TDP2 / TD2
TCLK2
RST
TRST
TMS
TCK
TDO
TDI
IC
VDDIO
GNDIO
MODE1
MODE0
RCLKE
TERM2
TERM1
RXTXM1
RXTXM0
JA1
JA0
MONT2
MONT1
THZ
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
IDT82V2082 PIN CONFIGURATIONS 10 May 4, 2009
Figure-3 IDT82V2082 FPBGA81 Package Pin Assignment (Top View)
TRST
TMS
VDDIO
GNDIO
TERM2
RXTXM
0
MONT1
THZ
RCLK2
TRING2
TCK
TDO
IC
MODE1
JA1
MONT2
TDN2
RST
TTIP2
VDDT2
TDI
MODE0
TERM1
JA0
RDP2/
RD2
TDP2/
TD2
TCLK2
GNDT2
GNDR2
RRING2
RCLKE
RXTXM
1
LOS1
LOS2
GNDD
RDN2/
CV2
REF
GNDA
VDDR2
RTIP2
RTIP1
D6/
PULS12
RCLK1
VDDD
IC
VDDR1
VDDA
RRING1
A1/
PATT21
D1/
PULS21
TDN1
RDP1/
RD1
TTIP1
GNDT1
GNDR1
A2/
RPD1
D5/
PULS11
D0/
PULS20
SCLK/
PATT11
TDP1/
TD1
TRING1
VDDT1
A3/EQ1
D7/
PULS13
D3/
PULS23
DS/RD/
SCLKE/
PATT10
CS/LP11
R/W/WR/
SDI/
LP21
A5/EQ2
A4/
RPD2
A0/
PATT20
D4/
PULS10
D2/
PULS22
SDO/
LP20
INT/
LP10
VDDIO
MCLK RDN1/
CV1 TCLK1 GNDIO GNDIO
123456789
123456789
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION 11 May 4, 2009
Notes:
1. The footprint ‘n’ (n = 1~2) represents one of the two channels.
2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by ‘...’. Users can find
these omitted addresses in the Register Description section.
3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 MCLK cycles.
2 PIN DESCRIPTION
Table-1 Pin Description
Name Type TQFP80
Pin No.
FPBGA81
Pin No.
Description
TTIP1
TTIP2
TRING1
TRING2
Analog
Output
63
78
62
79
A7
A3
A8
A2
TTIPn1/TRINGn: Transmit Bipolar Tip/Ring for Channel 1~2
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic
high on THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)2 is set to ‘1’, the TTIPn/
TRINGn in the corresponding channel is set to high impedance state.
In summary, these pins will become high impedance in the following conditions:
• THZ pin is high: all TTIPn/TRINGn enter high impedance;
• THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance;
• Loss of MCLK: all TTIPn/TRINGn pins become high impedance;·
• Loss of TCLKn: the corresponding TTIPn/TRINGn become HZ (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
• Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance;
• After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance.
RTIP1
RTIP2
RRING1
RRING2
Analog
Input
67
74
66
75
E5
D5
D6
C4
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~2
These signals are the differential receiver inputs.
TD1/TDP1
TD2/TDP2
TDN1
TDN2
I37
23
36
24
H7
H3
G6
H2
TDn: Transmit Data for Channel 1~2
When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn pin is sampled
into the device on the active edge of TCLKn and is encoded by AMI, HDB3 or B8ZS line code rules before being trans-
mitted. In this mode, TDNn should be connected to ground.
TDPn/TDNn: Positive/Negative Transmit Data
When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins.
Data on TDPn/TDNn pin is sampled into the device on the active edge of TCLKn. The active polarity is also selectable.
Refer to 3.3.1 TRANSMIT PATH SYSTEM INTERFACE for details. The line code in dual rail mode is as follows:
TCLK1
TCLK2
I38
22
J7
J3
TCLKn: Transmit Clock for Channel 1~2
This pin inputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data at TDn/TDPn or
TDNn is sampled into the device on the active edge of TCLKn. If TCLKn is missing3 and the TCLKn missing interrupt is
not masked, an interrupt will be generated.
TDPn TDNn Output Pulse
0 0 Space
0 1 Positive Pulse
1 0 Negative Pulse
1 1 Space
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION 12 May 4, 2009
RD1/
RDP1
RD2/
RDP2
CV1/
RDN1
CV2/
RDN2
O34
26
33
27
H6
G3
J6
J4
RDn: Receive Data output for Channel 1~2
In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI, HDB3 or B8ZS line code rules.
CVn: Code Violation indication
In single rail mode, the BPV/CV errors in received data stream will be reported by driving the CVn pin to high level for a
full clock cycle. B8ZS/HDB3 line code violation can be indicated if the B8ZS/HDB3 decoder is enabled. When AMI
decoder is selected, bipolar violation will be indicated.
In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CVn pin if single
rail mode is chosen.
RDPn/RDNn: Positive/Negative Receive Data output for Channel 1~2
In dual rail mode, these pins output the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer
data if CDR is bypassed.
Active edge and level select:
Data on RDPn/RDNn or RDn is clocked with either the rising or the falling edge of RCLKn. The active polarity is also
selectable. Refer to 3.4.8 RECEIVE PATH SYSTEM INTERFACE for details.
RCLK1
RCLK2
O35
25
G5
J1
RCLKn: Receive Clock output for Channel 1~2
This pin outputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions with AIS
enabled (bit AISE=1), RCLKn is derived from MCLK.
In clock recovery mode, this signal provides the clock recovered from the RTIPn/RRINGn signal. The receive data (RDn
in single rail mode or RDPn and RDNn in dual rail mode) is clocked out of the device on the active edge of RCLKn.
If clock recovery is bypassed, RCLKn is the exclusive OR (XOR) output of the dual rail slicer data RDPn and RDNn. This
signal can be used in applications with external clock recovery circuitry.
MCLK I 30 J5 MCLK: Master Clock input
A built-in clock system that accepts selectable 2.048 MHz reference for E1 operating mode and 1.544 MHz reference for
T1/J1 operating mode. This reference clock is used to generate several internal reference signals:
• Timing reference for the integrated clock recovery unit.
• Timing reference for the integrated digital jitter attenuator.
• Timing reference for microcontroller interface.
• Generation of RCLKn signal during a loss of signal condition.
• Reference clock to transmit All Ones, all zeros, PRBS/QRSS pattern as well as activate or deactivate Inband
Loopback code if MCLK is selected as the reference clock. Note that for ATAO and AIS, MCLK is always used as
the reference clock.
• Reference clock during Transmit All Ones (TAO) condition or sending PRBS/QRSS in hardware control mode.
The loss of MCLK will turn TTIP/TRING into high impedance status.
LOS1
LOS2
O32
28
F4
G4
LOSn: Loss of Signal Output for Channel 1~2
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of
received signal in channel n. The LOS pin will become low automatically when valid received signal is detected again.
The criteria of loss of signal are described in 3.6 LOS AND AIS DETECTION.
REF I 71 A5 REF: reference resister
An external resistor (3kΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal
circuit.
Table-1 Pin Description (Continued)
Name Type TQFP80
Pin No.
FPBGA81
Pin No.
Description
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION 13 May 4, 2009
MODE1
MODE0
I9
10
E2
D3
MODE[1:0]: operation mode of control interface select
The level on this pin determines which control mode is used to control the device as follows:
• The serial microcontroller interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the
selection of the active edge of SCLK.
• The parallel non-multiplexed microcontroller interface consists of CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT
pins. (Refer to 3.12 MICROCONTROLLER INTERFACES for details)
• Hardware interface consists of PULSn[3:0], THZ, RCLKE, LPn[1:0], PATTn[1:0], JA[1:0], MONTn, TERMn, EQn,
RPDn, MODE[1:0] and RXTXM[1:0] (n=1, 2).
RCLKE I 11 D4 RCLKE: the active edge of RCLKn select
In hardware control mode, this pin selects the active edge of RCLKn
• L= update RDPn/RDNn on the rising edge of RCLKn
• H= update RDPn/RDNn on the falling edge of RCLKn
In software control mode, this pin should be connected to GNDIO.
RXTXM1
RXTXM0
I14
15
E4
F1
RXTXM[1:0]: Receive and transmit path operation mode select
In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or
HDB3/B8ZS line coding:
• 00= single rail with HDB3/B8ZS coding
• 01= single rail with AMI coding
• 10= dual rail interface with CDR enabled
• 11= slicer mode (dual rail interface with CDR disabled)
In software control mode, these pins should be connected to ground.
CS
LP11
I42G8CS: Chip Select
In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables
serial or parallel microcontroller interface.
LP11/LP10: Loopback mode select for channel 1
When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 1 (Inband Loop-
back is not provided in hardware control mode).
• 00 = no loopback
• 01 = analog loopback
• 10 = digital loopback
• 11 = remote loopback
INT
LP10
O
I
41 G9 INT: Interrupt Request
In software control mode, this pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF,
20H) is set to ‘1’, all the interrupt sources will be masked. These interrupt sources can be masked individually via registers
(INTM0, 13H...) and (INTM1, 14H...). The interrupt status is reported via the registers (INTCH, 21H), (INTS0, 18H...) and
(INTS1, 19H...).
Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by
setting bits INT_PIN[1:0] (GCF, 20H)
LP11/LP10: Loopback mode select for channel 1
See above LP11.
Table-1 Pin Description (Continued)
Name Type TQFP80
Pin No.
FPBGA81
Pin No.
Description
MODE[1:0] Control Interface mode
00 Hardware interface
01 Serial Microcontroller Interface
10 Motorola non-multiplexed
11 Intel non-multiplexed
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION 14 May 4, 2009
SCLK
PATT11
I 46 G7 SCLK: Shift Clock
In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin
is sampled on the rising edge of SCLK. Configuration and status data on SDO pin is clocked out of the device on the rising
edge of SCLK if SCLKE pin is low, or on the falling edge of SCLK if SCLKE pin is high.
In parallel non-multiplexed interface mode, this pin should be connected to ground.
PATT11/PATT10: Transmit pattern select for channel 1
In hardware control mode, this pin selects the transmit pattern
• 00 = normal
• 01= All Ones
•10= PRBS
• 11= transmitter power down
SCLKE
DS
RD
PATT10
I 45 F8 SCLKE: Serial Clock Edge Select
In serial microcontroller interface mode, this signal selects the active edge of SCLK for outputting SDO. The output data
is valid after some delay from the active clock edge. It can be sampled on the opposite edge of the clock. The active clock
edge which clocks the data out of the device is selected as shown below:
DS: Data Strobe
In Motorola parallel non-multiplexed interface mode, this signal is the data strobe of the parallel interface. In a write oper-
ation (R/W = 0), the data on D[7:0] is sampled into the device. In a read operation (R/W = 1), the data is driven to D[7:0]
by the device.
RD: Read Strobe
In Intel parallel non-Multiplexed interface mode, the data is driven to D[7:0] by the device during low level of RD in a read
operation.
PATT11/PATT10: Transmit pattern select for channel 1
See above PATT11.
SDI
R/W
WR
LP21
I 44 H8 SDI: Serial Data Input
In serial microcontroller interface mode, this signal is the input data to the serial interface. Configuration data at SDI pin
is sampled by the device on the rising edge of SCLK.
R/W: Read/Write Select
In Motorola parallel non-multiplexed interface mode, this pin is low for write operation and high for read operation.
WR: Write Strobe
In Intel parallel non-multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. The
data on D[7:0] is sampled into the device in a write operation.
LP21/LP20: loopback mode select for channel 2
When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 2 (Inband Loop-
back is not provided in hardware control mode).
• 00 = no loopback
• 01 = analog loopback
• 10 = digital loopback
• 11 = remote loopback
Table-1 Pin Description (Continued)
Name Type TQFP80
Pin No.
FPBGA81
Pin No.
Description
SCLKE SCLK
Low Rising edge is the active edge.
High Falling edge is the active edge.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION 15 May 4, 2009
SDO
LP20
O
I
43 F9 SDO: Serial Data Output
In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data
at SDO pin is clocked out of the device on the rising edge of SCLK if SCLKE pin is low, or on the falling edge of SCLK
if SCLKE pin is high.
In parallel non-multiplexed interface mode, this pin should be left open.
LP21/LP20: loopback mode select for channel 2
See above LP21.
D7
PULS13
I/O
I
54 D8 D7: Data Bus bit7
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
PULS1[3:0]: these pins are used to select the following functions for channel 1 in hardware control mode:
• T1/E1/J1 mode
• Transmit pulse template
• Internal termination impedance (75Ω/120Ω/100Ω/110Ω)
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
Note that PULS13 to PULS10 determine the T1/E1/J1 mode of common block.
D6
PULS12
I/O
I
53 F5 D6: Data Bus bit6
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
D5
PULS11
I/O
I
52 E7 D5: Data Bus bit5
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
D4
PULS10
I/O
I
51 D9 D4: Data Bus bit4
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
D3
PULS23
I/O
I
50 E8 D3: Data Bus bit3
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
PULS2[3:0]: these pins are used to select the following functions for channel 2 in hardware control mode:·
• T1/E1/J1 mode
• Transmit pulse template
• Internal termination impedance (75 Ω/120 Ω/100 Ω/110 Ω)
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
D2
PULS22
I/O
I
49 E9 D2: Data Bus bit2
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
D1
PULS21
I/O
I
48 F6 D1: Data Bus bit1
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
Table-1 Pin Description (Continued)
Name Type TQFP80
Pin No.
FPBGA81
Pin No.
Description
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION 16 May 4, 2009
D0
PULS20
I/O
I
47 F7 D0: Data Bus bit0
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
See above.
A5
EQ2
I 60 A9 A5: Address Bus bit5
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
EQ2: Equalizer on/off for receiver2 in hardware control mode
0= short haul (10 dB)
1= long haul (36 dB for T1/J1, 43 dB for E1)
A4
RPD2
I 59 B9 A4: Address Bus bit4
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
RPD2: Power down control for receiver2 in hardware control mode
0= receiver 2 normal operation
1= receiver 2 power down
A3
EQ1
I 58 C8 A3: Address Bus bit3
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
EQ1: Equalizer on/off for receiver1 in hardware control mode
0= short haul (10 dB)
1= long haul (36 dB for T1/J1, 43 dB for E1)
A2
RPD1
I 57 D7 A2: Address Bus bit2
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
RPD1: Power down control for receiver1 in hardware control mode
0= receiver 1 normal operation
1= receiver 1 power down
A1
PATT21
I 56 E6 A1: Address Bus bit1
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
PATT21/PATT20: Transmit pattern select for channel 2
In hardware control mode, this pin selects the transmit pattern
00 = normal
01= All Ones
10= PRBS
11= transmitter power down
A0
PATT20
I 55 C9 A0: Address Bus bit 0
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
See above
Table-1 Pin Description (Continued)
Name Type TQFP80
Pin No.
FPBGA81
Pin No.
Description
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION 17 May 4, 2009
TERM1
TERM2
I13
12
E3
E1
TERMn: Selects internal or external impedance matching for channel 1 and channel 2 in hardware control mode
0 = ternary interface with internal impedance matching network
1 = ternary interface with external impedance matching network in E1 mode; ternary interface with external impedance
matching network for receiver and ternary interface with internal impedance matching network for transmitter in T1/J1
mode.
(This applies to ZB die revision only.)
In software control mode, this pin should be connected to ground.
JA1 I 16 F2 JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select for channel 1 and channel 2 (only
used in hardware control mode)
• 00 = JA is disabled
• 01= JA in receiver, broad bandwidth, FIFO=64 bits
• 10 = JA in receiver, narrow bandwidth, FIFO=128 bits
• 11= JA in transmitter, narrow bandwidth, FIFO=128 bits
In software control mode, this pin should be connected to ground.
JA0 I 17 F3 See above.
MONT2 I 18 G2 MONT2: Receive Monitor gain select for channel 2
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
MONT1 I 19 G1 MONT1: Receive Monitor gain select for channel 1
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
RST I21J2RST: Hardware Reset
The chip is forced to reset state if a low signal is input on this pin for more than 100ns. MCLK must be active during reset.
THZ I 20 H1 THZ: Transmitter Driver High Impedance Enable
This signal enables or disables all transmitter drivers on a global basis. A low level on this pin enables the driver while
a high level on this pin places all drivers in high impedance state. Note that the functionality of the internal circuits is not
affected by this signal.
JTAG Signals
TRST I
Pullup
1A1TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure deter-
ministic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
If JTAG is not used, this pin must be connected to ground.
TMS I
Pullup
2 B1 TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edge of TCK. TMS has an internal
pull-up resistor.
If JTAG is not used, this pin may be left unconnected.
TCK I 3 B2 TCK: JTAG Test Clock
This is the input clock for JTAG. The data on TDI and TMS are clocked into the device on the rising edge of TCK while
the data on TDO is clocked out of the device on the falling edge of TCK. When TCK is idle at low state, all the stored-
state devices contained in the test logic will retain their state indefinitely.
If JTAG is not used, this pin may be left unconnected.
TDO O 4 C2 TDO: JTAG Test Data Output
This output pin is high impedance normally and is used for reading all the serial configuration and test data from the test
logic. The data on TDO is clocked out of the device on the falling edge of TCK.
If JTAG is not used, this pin should be left unconnected.
Table-1 Pin Description (Continued)
Name Type TQFP80
Pin No.
FPBGA81
Pin No.
Description
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION 18 May 4, 2009
TDI I
Pullup
5 C3 TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pull-up resistor. The data on TDI
is clocked into the device on the rising edge of TCK.
If JTAG is not used, this pin may be left unconnected.
Power Supplies and Grounds
VDDIO - 7,40 C1, H9 3.3 V I/O power supply
GNDIO - 8,39 D1, J8, J9 I/O ground
VDDT1
VDDT2
-61
80
B8
B3
3.3 V power supply for transmitter driver
GNDT1
GNDT2
-64
77
B7
A4
Analog ground for transmitter driver
VDDR1
VDDR2
-68
73
B6
C5
Power supply for receive analog circuit
GNDR1
GNDR2
-65
76
C7
B4
Analog ground for receive analog circuit
VDDD - 31 H5 3.3V digital core power supply
GNDD - 29 H4 Digital core ground
VDDA - 69 C6 Analog core circuit power supply
GNDA - 72 B5 Analog core circuit ground
Others
IC - 70 A6 IC: Internal Connection
Internal Use. This pin should be left open in normal operation.
IC - 6 D2 IC: Internal Connection
Internal Use. This pin should be connected to ground in normal operation.
Table-1 Pin Description (Continued)
Name Type TQFP80
Pin No.
FPBGA81
Pin No.
Description
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 19 May 4, 2009
3 FUNCTIONAL DESCRIPTION
3.1 CONTROL MODE SELECTION
The IDT82V2082 can be configured by software or by hardware. The
software control mode supports Serial Control Interface, Motorola non-Mul-
tiplexed Control Interface and Intel non-Multiplexed Control Interface. The
Control mode is selected by MODE1 and MODE0 pins as follows:
• The serial microcontroller Interface consists of CS, SCLK, SCLKE,
SDI, SDO and INT pins. SCLKE is used for the selection of active
edge of SCLK.
• The parallel non-Multiplexed microcontroller Interface consists of
CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
• Hardware interface consists of PULSn[3:0], THZ, RCLKE, LPn[1:0],
PATTn[1:0], JA[1:0], MONTn, TERMn, EQn, RPDn, MODE[1:0] and
RXTXM[1:0] (n=1, 2). Refer to 5 HARDWARE CONTROL PIN SUM-
MARY for details about hardware control.
3.2 T1/E1/J1 MODE SELECTION
When the chip is configured by software, T1/E1/J1 mode is selected by
the T1E1 bit (GCF, 20H). In E1 application, the T1E1 bit (GCF, 20H) should
be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’.
When the chip is configured by hardware, T1/E1/J1 mode is selected
by PULSn[3:0] pins on a per channel basis. These pins also determine
transmit pulse template and internal termination impedance. Refer to 5
HARDWARE CONTROL PIN SUMMARY for details.
3.3 TRANSMIT PATH
The transmit path of each channel of IDT82V2082 consists of an
Encoder, an optional Jitter Attenuator, a Waveform Shaper, a set of LBOs,
a Line Driver and a Programmable Transmit Termination.
3.3.1 TRANSMIT PATH SYSTEM INTERFACE
The transmit path system interface consists of TCLKn pin, TDn/TDPn
pin and TDNn pin. In E1 mode, TCLKn is a 2.048 MHz clock. In T1/J1 mode,
TCLKn is a 1.544 MHz clock. If TCLKn is missing for more than 70 MCLK
cycles, an interrupt will be generated if it is not masked.
Transmit data is sampled on the TDn/TDPn and TDNn pins by the active
edge of TCLKn. The active edge of TCLKn can be selected by the
TCLK_SEL bit (TCF0, 04H...). And the active level of the data on TDn/TDPn
and TDNn can be selected by the TD_INV bit (TCF0, 04H...). In hardware
control mode, the falling edge of TCLKn and the active high of transmit data
are always used.
The transmit data from the system side can be provided in two different
ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used
for transmitting data and the T_MD[1] bit (TCF0, 04H...) should be set to
‘0’. In Dual Rail Mode, both TDPn pin and TDNn pin are used for transmitting
data, the T_MD[1] bit (TCF0, 04H...) should be set to ‘1’.
3.3.2 ENCODER
In Single Rail mode, when T1/J1 mode is selected, the Encoder can be
selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 04H...).
In Single Rail mode, when E1 mode is selected, the Encoder can be con-
figured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit
(TCF0, 04H...).
In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit
T_MD[1] is ‘1’), the Encoder is by-passed. In Dual Rail mode, a logic ‘1’ on
the TDPn pin and a logic ‘0’ on the TDNn pin results in a negative pulse on
the TTIPn/TRINGn; a logic ‘0’ on TDPn pin and a logic ‘1’ on TDNn pin
results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn
are high or low, the TTIPn/TRINGn outputs a space (Refer to TDn/TDPn,
TDNn Pin Description).
In hardware control mode, the operation mode of receive and transmit
path can be selected by setting RXTXM1 and RXTXM0 pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.3.3 PULSE SHAPER
The IDT82V2082 provides three ways of manipulating the pulse shape
before sending it. The first is to use preset pulse templates for short haul
application, the second is to use LBO (Line Build Out) for long haul appli-
cation and the other way is to use user-programmable arbitrary waveform
template.
In software control mode, the pulse shape can be selected by setting
the related registers.
In hardware control mode, the pulse shape can be selected by setting
PULSn[3:0] pins on a per channel basis. Refer to 5 HARDWARE CONTROL
PIN SUMMARY for details.
3.3.3.1 Preset Pulse Templates
For E1 applications, the pulse shape is shown in Figure-4 according to
the G.703 and the measuring diagram is shown in Figure-5. In internal
impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0]
bits (TCF1, 05H...) should be set to ‘0000’; if the cable impedance is 120
Ω, the PULS[3:0] bits (TCF1, 05H...) should be set to ‘0001’. In external
impedance matching mode, for both E1/75 Ω and E1/120 Ω cable imped-
ance, PULS[3:0] should be set to ‘0001’.
Control Interface Mode
00 Hardware interface
01 Serial Microcontroller Interface.
10 Parallel -non-Multiplexed -Motorola Interface
11 Parallel -non-Multiplexed -Intel Interface
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 20 May 4, 2009
Figure-4 E1 Waveform Template Diagram
Figure-5 E1 Pulse Template Test Circuit
For T1 applications, the pulse shape is shown in Figure-6 according to
the T1.102 and the measuring diagram is shown in Figure-7. This also
meets the requirement of G.703, 2001. The cable length is divided into five
grades, and there are five pulse templates used for each of the cable length.
The pulse template is selected by PULS[3:0] bits (TCF1, 05H...).
Figure-6 DSX-1 Waveform Template
Figure-7 T1 Pulse Template Test Circuit
For J1 applications, the PULS[3:0] (TCF1, 05H...) should be set to
‘0111’. Table-14 lists these values.
3.3.3.2 LBO (Line Build Out)
To prevent the cross-talk at the far end, the output of TTIPn/TRINGn
could be attenuated before transmission for long haul applications. The
FCC Part 68 Regulations specifies four grades of attenuation with a step
of 7.5 dB. Three LBOs are used to implement the pulse attenuation. The
PULS[3:0] bits (TCF1, 05H...) are used to select the attenuation grade. Both
Table-14 and Table-15 list these values.
-0.6 -0.4 -0.2 0 0.2 0.4 0.6
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
Tim e in Unit Intervals
Normalized Amplitude
IDT82V2082 VOUTRLOAD
TTIPn
TRINGn
Note: 1. For RLOAD = 75 Ω (nom), Vout (Peak)=2.37V (nom)
2. For RLOAD =120 Ω (nom), Vout (Peak)=3.00V (nom)
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0 250 500 750 1000 1250
Time (ns)
Normalized Amplitude
IDT82V2082
TTIPn
TRINGn
Cable
RLOAD VOUT
Note: RLOAD = 100 Ω ± 5%
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 21 May 4, 2009
3.3.3.3 User-Programmable Arbitrary Waveform
When the PULS[3:0] bits are set to ‘11xx’, user-programmable arbitrary
waveform generator mode can be used in the corresponding channel. This
allows the transmitter performance to be tuned for a wide variety of line con-
dition or special application.
Each pulse shape can extend up to 4 UIs (Unit Interval), addressed by
UI[1:0] bits (TCF3, 07H...) and each UI is divided into 16 sub-phases,
addressed by the SAMP[3:0] bits (TCF3, 07H...). The pulse amplitude of
each phase is represented by a binary byte, within the range from +63 to -
63, stored in WDAT[6:0] bits (TCF4, 08H...) in signed magnitude form. The
most positive number +63 (D) represents the maximum positive amplitude
of the transmit pulse while the most negative number -63 (D) represents the
maximum negative amplitude of the transmit pulse. Therefore, up to 64
bytes are used. For each channel, a 64 bytes RAM is available.
There are twelve standard templates which are stored in an on-chip ROM.
User can select one of them as reference and make some changes to get
the desired waveform.
User can change the wave shape and the amplitude to get the desired
pulse shape. In order to do this, firstly, users can choose a set of waveform
value from the following twelve tables, which is the most similar to the
desired pulse shape. Table-2, Table-3, Table-4, Table-5, Table-6, Table-7,
Table-8, Table-9, Table-10, Table-11, Table-12 and Table-13 list the sample
data and scaling data of each of the twelve templates. Then modify the cor-
responding sample data to get the desired transmit pulse shape.
Secondly, through the value of SCAL[5:0] bits increased or decreased
by 1, the pulse amplitude can be scaled up or down at the percentage ratio
against the standard pulse amplitude if needed. For different pulse shapes,
the value of SCAL[5:0] bits and the scaling percentage ratio are different.
The following twelve tables list these values.
Do the followings step by step, the desired waveform can be pro-
grammed, based on the selected waveform template:
(1).Select the UI by UI[1:0] bits (TCF3, 07H...)
(2).Specify the sample address in the selected UI by SAMP [3:0] bits
(TCF3, 07H...)
(3).Write sample data to WDAT[6:0] bits (TCF4, 08H...). It contains the
data to be stored in the RAM, addressed by the selected UI and the
corresponding sample address.
(4).Set the RW bit (TCF3, 07H...) to ‘0’ to implement writing data to RAM,
or to ‘1’ to implement read data from RAM
(5).Implement the Read from RAM/Write to RAM by setting the DONE
bit (TCF3, 07H...)
Repeat the above steps until all the sample data are written to or read
from the internal RAM.
(6).Write the scaling data to SCAL[5:0] bits (TCF2, 06H...) to scale the
amplitude of the waveform based on the selected standard pulse
amplitude
When more than one UI is used to compose the pulse template, the over-
lap of two consecutive pulses could make the pulse amplitude overflow
(exceed the maximum limitation) if the pulse amplitude is not set properly.
This overflow is captured by DAC_OV_IS bit (INTS1, 19H...), and, if
enabled by the DAC_OV_IM bit (INTM1, 14H...), an interrupt will be gen-
erated.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 22 May 4, 2009
The following tables give all the sample data based on the preset pulse
templates and LBOs in detail for reference. For preset pulse templates and
LBOs, scaling up/down against the pulse amplitude is not supported.
1.Table-2 Transmit Waveform Value for E1 75 Ω
2.Table-3 Transmit Waveform Value for E1 120 Ω
3.Table-4 Transmit Waveform Value for T1 0~133 ft
4.Table-5 Transmit Waveform Value for T1 133~266 ft
5.Table-6 Transmit Waveform Value for T1 266~399 ft
6.Table-7 Transmit Waveform Value for T1 399~533 ft
7.Table-8 Transmit Waveform Value for T1 533~655 ft
8.Table-9 Transmit Waveform Value for J1 0~655 ft
9.Table-10 Transmit Waveform Value For DS1 0 dB LBO
10.Table-11 Transmit Waveform Value For DS1 -7.5 dB LBO
11.Table-12 Transmit Waveform Value For DS1 -15.0 dB LBO
12.Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO
Table-2 Transmit Waveform Value For E1 75 Ohm
Sample UI 1 UI 2 UI 3 UI 4
1 0000000 0000000 0000000 0000000
2 0000000 0000000 0000000 0000000
3 0000000 0000000 0000000 0000000
4 0001100 0000000 0000000 0000000
5 0110000 0000000 0000000 0000000
6 0110000 0000000 0000000 0000000
7 0110000 0000000 0000000 0000000
8 0110000 0000000 0000000 0000000
9 0110000 0000000 0000000 0000000
10 0110000 0000000 0000000 0000000
11 0110000 0000000 0000000 0000000
12 0110000 0000000 0000000 0000000
13 0000000 0000000 0000000 0000000
14 0000000 0000000 0000000 0000000
15 0000000 0000000 0000000 0000000
16 0000000 0000000 0000000 0000000
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0]
results in 3% scaling up/down against the pulse amplitude.
Table-3 Transmit Waveform Value For E1 120 Ohm
Sample UI 1 UI 2 UI 3 UI 4
1 0000000 0000000 0000000 0000000
2 0000000 0000000 0000000 0000000
3 0000000 0000000 0000000 0000000
4 0001111 0000000 0000000 0000000
5 0111100 0000000 0000000 0000000
6 0111100 0000000 0000000 0000000
7 0111100 0000000 0000000 0000000
8 0111100 0000000 0000000 0000000
9 0111100 0000000 0000000 0000000
10 0111100 0000000 0000000 0000000
11 0111100 0000000 0000000 0000000
12 0111100 0000000 0000000 0000000
13 0000000 0000000 0000000 0000000
14 0000000 0000000 0000000 0000000
15 0000000 0000000 0000000 0000000
16 0000000 0000000 0000000 0000000
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0]
results in 3% scaling up/down against the pulse amplitude.
Table-4 Transmit Waveform Value For T1 0~133 ft
Sample UI 1 UI 2 UI 3 UI 4
1 0010111 1000010 0000000 0000000
2 0100111 1000001 0000000 0000000
3 0100111 0000000 0000000 0000000
4 0100110 0000000 0000000 0000000
5 0100101 0000000 0000000 0000000
6 0100101 0000000 0000000 0000000
7 0100101 0000000 0000000 0000000
8 0100100 0000000 0000000 0000000
9 0100011 0000000 0000000 0000000
10 1001010 0000000 0000000 0000000
11 1001010 0000000 0000000 0000000
12 1001001 0000000 0000000 0000000
13 1000111 0000000 0000000 0000000
14 1000101 0000000 0000000 0000000
15 1000100 0000000 0000000 0000000
16 1000011 0000000 0000000 0000000
SCAL[5:0] = 1101101 (default), One step change of this value of SCAL[5:0]
results in 2% scaling up/down against the pulse amplitude.
1. In T1 mode, when arbitrary pulse for short haul application is configured,
users should write ‘110110’ to SCAL[5:0] bits if no scaling is required.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 23 May 4, 2009
Table-5 Transmit Waveform Value For T1 133~266 ft
Sample UI 1 UI 2 UI 3 UI 4
1 0011011 1000011 0000000 0000000
2 0101110 1000010 0000000 0000000
3 0101100 1000001 0000000 0000000
4 0101010 0000000 0000000 0000000
5 0101001 0000000 0000000 0000000
6 0101000 0000000 0000000 0000000
7 0100111 0000000 0000000 0000000
8 0100110 0000000 0000000 0000000
9 0100101 0000000 0000000 0000000
10 1010000 0000000 0000000 0000000
11 1001111 0000000 0000000 0000000
12 1001101 0000000 0000000 0000000
13 1001010 0000000 0000000 0000000
14 1001000 0000000 0000000 0000000
15 1000110 0000000 0000000 0000000
16 1000100 0000000 0000000 0000000
See Table -4
Table-6 Transmit Waveform Value For T1 266~399 ft
Sample UI 1 UI 2 UI 3 UI 4
1 0011111 1000011 0000000 0000000
2 0110100 1000010 0000000 0000000
3 0101111 1000001 0000000 0000000
4 0101100 0000000 0000000 0000000
5 0101011 0000000 0000000 0000000
6 0101010 0000000 0000000 0000000
7 0101001 0000000 0000000 0000000
8 0101000 0000000 0000000 0000000
9 0100101 0000000 0000000 0000000
10 1010111 0000000 0000000 0000000
11 1010011 0000000 0000000 0000000
12 1010000 0000000 0000000 0000000
13 1001011 0000000 0000000 0000000
14 1001000 0000000 0000000 0000000
15 1000110 0000000 0000000 0000000
16 1000100 0000000 0000000 0000000
See Table -4
Table-7 Transmit Waveform Value For T1 399~533 ft
Sample UI 1 UI 2 UI 3 UI 4
1 0100000 1000011 0000000 0000000
2 0111011 1000010 0000000 0000000
3 0110101 1000001 0000000 0000000
4 0101111 0000000 0000000 0000000
5 0101110 0000000 0000000 0000000
6 0101101 0000000 0000000 0000000
7 0101100 0000000 0000000 0000000
8 0101010 0000000 0000000 0000000
9 0101000 0000000 0000000 0000000
10 1011000 0000000 0000000 0000000
11 1011000 0000000 0000000 0000000
12 1010011 0000000 0000000 0000000
13 1001100 0000000 0000000 0000000
14 1001000 0000000 0000000 0000000
15 1000110 0000000 0000000 0000000
16 1000100 0000000 0000000 0000000
See Table-4
Table-8 Transmit Waveform Value For T1 533~655 ft
Sample UI 1 UI 2 UI 3 UI 4
1 0100000 1000011 0000000 0000000
2 0111111 1000010 0000000 0000000
3 0111000 1000001 0000000 0000000
4 0110011 0000000 0000000 0000000
5 0101111 0000000 0000000 0000000
6 0101110 0000000 0000000 0000000
7 0101101 0000000 0000000 0000000
8 0101100 0000000 0000000 0000000
9 0101001 0000000 0000000 0000000
10 1011111 0000000 0000000 0000000
11 1011110 0000000 0000000 0000000
12 1010111 0000000 0000000 0000000
13 1001111 0000000 0000000 0000000
14 1001001 0000000 0000000 0000000
15 1000111 0000000 0000000 0000000
16 1000100 0000000 0000000 0000000
See Table-4
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 24 May 4, 2009
Table-9 Transmit Waveform Value For J1 0~655 ft
Sample UI 1 UI 2 UI 3 UI 4
1 0010111 1000010 0000000 0000000
2 0100111 1000001 0000000 0000000
3 0100111 0000000 0000000 0000000
4 0100110 0000000 0000000 0000000
5 0100101 0000000 0000000 0000000
6 0100101 0000000 0000000 0000000
7 0100101 0000000 0000000 0000000
8 0100100 0000000 0000000 0000000
9 0100011 0000000 0000000 0000000
10 1001010 0000000 0000000 0000000
11 1001010 0000000 0000000 0000000
12 1001001 0000000 0000000 0000000
13 1000111 0000000 0000000 0000000
14 1000101 0000000 0000000 0000000
15 1000100 0000000 0000000 0000000
16 1000011 0000000 0000000 0000000
SCAL[5:0] = 110110 (default), One step change of this value of SCAL[5:0]
results in 2% scaling up/down against the pulse amplitude.
Table-10 Transmit Waveform Value For DS1 0 dB LBO
Sample UI 1 UI 2 UI 3 UI 4
1 0010111 1000010 0000000 0000000
2 0100111 1000001 0000000 0000000
3 0100111 0000000 0000000 0000000
4 0100110 0000000 0000000 0000000
5 0100101 0000000 0000000 0000000
6 0100101 0000000 0000000 0000000
7 0100101 0000000 0000000 0000000
8 0100100 0000000 0000000 0000000
9 0100011 0000000 0000000 0000000
10 1001010 0000000 0000000 0000000
11 1001010 0000000 0000000 0000000
12 1001001 0000000 0000000 0000000
13 1000111 0000000 0000000 0000000
14 1000101 0000000 0000000 0000000
15 1000100 0000000 0000000 0000000
16 1000011 0000000 0000000 0000000
SCAL[5:0] = 110110 (default), One step change of this Value results in 2%
scaling up/down against the pulse amplitude.
Table-11 Transmit Waveform Value For DS1 -7.5 dB LBO
Sample UI 1 UI 2 UI 3 UI 4
1 0000000 0010100 0000010 0000000
2 0000010 0010010 0000010 0000000
3 0001001 0010000 0000010 0000000
4 0010011 0001110 0000010 0000000
5 0011101 0001100 0000010 0000000
6 0100101 0001011 0000001 0000000
7 0101011 0001010 0000001 0000000
8 0110001 0001001 0000001 0000000
9 0110110 0001000 0000001 0000000
10 0111010 0000111 0000001 0000000
11 0111001 0000110 0000001 0000000
12 0110000 0000101 0000001 0000000
13 0101000 0000100 0000000 0000000
14 0100000 0000100 0000000 0000000
15 0011010 0000011 0000000 0000000
16 0010111 0000011 0000000 0000000
SCAL[5:0] = 010001 (default), One step change of this value of SCAL[5:0]
results in 6.25% scaling up/down against the pulse amplitude.
Table-12 Transmit Waveform Value For DS1 -15.0 dB LBO
Sample UI 1 UI 2 UI 3 UI 4
1 0000000 0110101 0001111 0000011
2 0000000 0110011 0001101 0000010
3 0000000 0110000 0001100 0000010
4 0000001 0101101 0001011 0000010
5 0000100 0101010 0001010 0000010
6 0001000 0100111 0001001 0000001
7 0001110 0100100 0001000 0000001
8 0010100 0100001 0000111 0000001
9 0011011 0011110 0000110 0000001
10 0100010 0011100 0000110 0000001
11 0101010 0011010 0000101 0000001
12 0110000 0010111 0000101 0000001
13 0110101 0010101 0000100 0000001
14 0110111 0010100 0000100 0000000
15 0111000 0010010 0000011 0000000
16 0110111 0010000 0000011 0000000
SCAL[5:0] = 001000 (default), One step change of the value of SCAL[5:0]
results in 12.5% scaling up/down against the pulse amplitude.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 25 May 4, 2009
3.3.4 TRANSMIT PATH LINE INTERFACE
The transmit line interface consists of TTIPn and TRINGn pins. The
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω, 100 Ω,
110 Ω or 120 Ω internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
to ‘1’, the internal impedance matching circuit will be disabled. In this case,
the external impedance matching circuit will be used to realize the imped-
ance matching. For T1/J1 mode, the external impedance matching circuit
for the transmitter is not supported.
Figure-9 shows the appropriate external components to connect with
the cable for one channel. Table-14 is the list of the recommended imped-
ance matching for transmitter.
In hardware control mode, TERMn pin can be used to select impedance
matching for both receiver and transmitter on a per channel basis. If TERMn
pin is low, internal impedance network will be used. If TERMn pin is high,
external impedance network will be used in E1 mode, or external imped-
ance network for receiver and internal impedance network for transmitter
will be used in T1/J1 mode. (This applies to ZB die revision only). When
internal impedance network is used, PULSn[3:0] pins should be set to
select the specific internal impedance in the corresponding channel. Refer
to 5 HARDWARE CONTROL PIN SUMMARY for details.
The TTIPn/TRINGn can also be turned into high impedance globally by
pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)
to ‘1’. In this state, the internal transmit circuits are still active.
In hardware control mode, TTIPn/TRINGn pins can be turned into high
impedance globally by pulling THZ pin to high. Refer to 5 HARDWARE CON-
TROL PIN SUMMARY for details.
Besides, in the following cases, TTIPn/TRINGn will also become high
impedance:
• Loss of MCLK;
• Loss of TCLKn (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
• Transmit path power down;
• After software reset; pin reset and power on.
Note: The precision of the resistors should be better than ± 1%
Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO
Sample UI 1 UI 2 UI 3 UI 4
1 0000000 0101100 0011110 0001000
2 0000000 0101110 0011100 0000111
3 0000000 0110000 0011010 0000110
4 0000000 0110001 0011000 0000101
5 0000001 0110010 0010111 0000101
6 0000011 0110010 0010101 0000100
7 0000111 0110010 0010100 0000100
8 0001011 0110001 0010011 0000011
9 0001111 0110000 0010001 0000011
10 0010101 0101110 0010000 0000010
11 0011001 0101100 0001111 0000010
12 0011100 0101001 0001110 0000010
13 0100000 0100111 0001101 0000001
14 0100011 0100100 0001100 0000001
15 0100111 0100010 0001010 0000001
16 0101010 0100000 0001001 0000001
SCAL[5:0] = 000100 (default), One step change of this value of SCAL[5:0]
results in 25% scaling up/down against the pulse amplitude.
Table-14 Impedance Matching for Transmitter
Cable Configuration Internal Termination External Termination
T_TERM[2:0] PULS[3:0] RTT_TERM[2:0] PULS[3:0] RT
E1/75 Ω000 0000 0 Ω1XX 0001 9.4 Ω
E1/120 Ω001 0001 0001
T1/0~133 ft 010 0010 - - -
T1/133~266 ft 0011
T1/266~399 ft 0100
T1/399~533 ft 0101
T1/533~655 ft 0110
J1/0~655 ft 011 0111
0 dB LBO 010 1000
-7.5 dB LBO 1001
-15.0 dB LBO 1010
-22.5 dB LBO 1011
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 26 May 4, 2009
3.3.5 TRANSMIT PATH POWER DOWN
The transmit path can be powered down individually by setting the
T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
In hardware control mode, the transmit path can be powered down by
setting PATTn[1:0] pins to ‘11’ on a per channel basis. Refer to 5 HARD-
WARE CONTROL PIN SUMMARY for details.
3.4 RECEIVE PATH
The receive path consists of Receive Internal Termination, Monitor
Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive
Equalizer, Data Slicer, CDR (Clock & Data Recovery), Optional Jitter Atten-
uator, Decoder and LOS/AIS Detector. Refer to Figure-8.
3.4.1 RECEIVE INTERNAL TERMINATION
The impedance matching can be realized by the internal impedance
matching circuit or the external impedance matching circuit. If R_TERM[2]
is set to ‘0’, the internal impedance matching circuit will be selected. In this
case, the R_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω, 100
Ω, 110 Ω or 120 Ω internal impedance of RTIPn/RRINGn. If R_TERM[2]
is set to ‘1’, the internal impedance matching circuit will be disabled. In this
case, the external impedance matching circuit will be used to realize the
impedance matching.
Figure-9 shows the appropriate external components to connect with
the cable for one channel. Table-15 is the list of the recommended imped-
ance matching for receiver.
Figure-8 Receive Path Function Block Diagram
Table-15 Impedance Matching for Receiver
Cable Configuration Internal Termination External Termination
R_TERM[2:0] RRR_TERM[2:0] RR
E1/75 Ω000 120 Ω1XX 75 Ω
E1/120 Ω001 120 Ω
T1 010 100 Ω
J1 011 110 Ω
Monitor Gain/
Adaptive Equalizer
LOS/AIS
Detector
Data Slicer Decoder
LOS
RCLK
RDP
RDN
RTIP Clock
and Data
Recovery
Receive
Internal
termination
RRING
Jitter
Attenuator
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 27 May 4, 2009
Figure-9 Transmit/Receive Line Circuit
In hardware control mode, TERMn, PULSn[3:0] pins can be used to
select impedance matching for both receiver and transmitter on a per chan-
nel basis. If TERMn pin is low, internal impedance network will be used. If
TERMn pin is high, external impedance network will be used in E1 mode,
or external impedance network for receiver and internal impedance net-
work for transmitter will be used in T1/J1 mode. (This applies to ZB die revi-
sion only). When internal impedance network is used, PULSn[3:0] pins
should be set to select specific internal impedance for the corresponding
channel. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.2 LINE MONITOR
In both T1/J1 and E1 short haul applications, the non-intrusive monitor-
ing on channels located in other chips can be performed by tapping the mon-
itored channel through a high impedance bridging circuit. Refer to Figure-
10 and Figure-11.
After a high resistance bridging circuit, the signal arriving at the RTIPn/
RRINGn is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selected by MG[1:0] bits (RCF2, 0BH...). For normal operation, the Monitor
Gain should be set to 0 dB.
In hardware control mode, MONTn pin can be used to set the Monitor
Gain on a per channel basis. When MONTn pin is low, the Monitor Gain for
the specific channel is 0 dB. When MONTn pin is high, the Monitor Gain for
the specific channel is 26 dB. Refer to 5 HARDWARE CONTROL PIN SUM-
MARY for details.
Figure-10 Monitoring Receive Line in Another Chip
Figure-11 Monitor Transmit Line in Another Chip
Note:
1. Common decoupling capacitor. One per chip
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060
4. RT/ RR: refer toTable-14 and Table-15 respecivley for RT and RR values
A
B
•
•
••
RX Line RR4
••
TX Line
RT4
RT4
RTIPn
RRINGn
TRINGn
TTIPn
•
0.1µF
GNDTn
VDDTn
IDT82V2082
VDDTn
VDDTn
D4
D3
D2
D1
1:1
2:1
68µF1
·
·
D6
D5
·
D8
D7
·
Cp
VDDRn
VDDRn
One of the Two Identical Channels
2
3
3.3 V
•
0.1µF
GNDRn
VDDRn 68µF
3.3 V
1
•
•
•
•
RTIP
RRING
RTIP
RRING
normal receive mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
monitor
gain=0dB
TTIP
TRING
RTIP
RRING
normal transmit mode
monitor mode
DSX cross connect
point
R
monitor gain
monitor gain
=22/26/32dB
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 28 May 4, 2009
3.4.3 ADAPTIVE EQUALIZER
The adaptive equalizer can remove most of the signal distortion due to
intersymbol interference caused by cable attenuation. It can be enabled or
disabled by setting EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0AH...).
When the adaptive equalizer is out of range, EQ_S bit (STAT0, 16H...)
will be set to ‘1’ to indicate the status of equalizer. If EQ_IES bit (INTES,
15H...) is set to ‘1’, any changes of EQ_S bit will generate an interrupt and
EQ_IS bit (INTS0, 18H...) will be set to ‘1’ if it is not masked. If EQ_IES bit
is set to ‘0’, only the ‘0’ to ‘1’ transition of the EQ_S bit will generate an inter-
rupt and EQ_IS bit will be set to ‘1’ if it is not masked. The EQ_IS bit will be
reset after being read.
The Amplitude/wave shape detector keeps on measuring the ampli-
tude/wave shape of the incoming signals during an observation period. This
observation period can be 32, 64, 128 or 256 symbol periods, as selected
by UPDW[1:0] bits (RCF2, 0BH...). A shorter observation period allows
quicker responses to pulse amplitude variation while a longer observation
period can minimize the possible overshoots. The default observation
period is 128 symbol periods.
Based on the observed peak value for a period, the equalizer will be
adjusted to achieve a normalized signal. LATT[4:0] bits (STAT1, 17H...)
indicate the signal attenuation introduced by the cable in approximately 2
dB per step.
3.4.4 RECEIVE SENSITIVITY
For short haul application, the Receive Sensitivity for both E1 and T1/
J1 is -10 dB. For long haul application, the receive sensitivity is -43 dB for
E1 and -36 dB for T1/J1.
When the chip is configured by hardware, the short haul or long haul
operating mode can be selected by setting EQn on a per channel basis. For
short haul mode, the Receive Sensitivity for both E1 and T1/J1 is -10 dB.
For long haul mode, the receive sensitivity is -43 dB for E1 and -36 dB for
T1/J1. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.5 DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
0BH...). The output of the Data Slicer is forwarded to the CDR (Clock & Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.4.6 CDR (Clock & Data Recovery)
The CDR is used to recover the clock and data from the received signal.
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDPn/RDNn pins directly.
3.4.7 DECODER
In T1/J1 applications, the R_MD[1:0] bits (RCF0, 09H...) is used to
select the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0]
bits (RCF0, 09H...) are used to select the AMI decoder or HDB3 decoder.
When the chip is configured by hardware, the operation mode of receive
and transmit path can be selected by setting RXTXM[1:0] pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.8 RECEIVE PATH SYSTEM INTERFACE
The receive path system interface consists of RCLKn pin, RDn/RDPn
pin and RDNn pin. In E1 mode, the RCLKn outputs a recovered 2.048 MHz
clock. In T1/J1 mode, the RCLKn outputs a recovered 1.544 MHz clock. The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/
RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...).
In hardware control mode, only the active edge of RCLKn can be
selected. If RCLKE is set to high, the falling edge will be chosen as the active
edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as
the active edge of RCLKn. The active level of the data on RDn/RDPn and
RDNn is the same as that in software control mode.
The received data can be output to the system side in two different ways:
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Sin-
gle Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
In the receive Dual Rail mode, the CDR unit can be by-passed by setting
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn out-
puts the exclusive OR (XOR) of the RDPn and RDNn. This is called receiver
slicer mode. In this case, the transmit path is still operating in Dual Rail
mode.
3.4.9 RECEIVE PATH POWER DOWN
The receive path can be powered down individually by setting R_OFF
bit (RCF0, 09H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDNn and
LOSn will be logic low.
In hardware control mode, receiver power down can be selected by pull-
ing RPDn pin to high on a per channel basis. Refer to 5 HARDWARE CON-
TROL PIN SUMMARY for more details.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 29 May 4, 2009
3.4.10 G.772 NON-INTRUSIVE MONITORING
In applications using only one channel, channel 1 can be configured to
monitor the data received or transmitted in channel 2. The MONT[1:0] bits
(GCF, 20H) determine which direction (transmit/receive) will be monitored.
The monitoring is non-intrusive per ITU-T G.772. Figure-12 illustrates the
concept.
The monitored line signal (transmit or receive) goes through Channel
1’s Clock and Data Recovery. The signal can be observed digitally at the
RCLK1, RD1/RDP1 and RDN1. If Channel 1 is configured to Remote Loop-
back while in the Monitoring mode, the monitored data will be output on
TTIP1/TRING1.
Figure-12 G.772 Monitoring Diagram
Channel 2
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
Line
Driver
Waveform
Shaper/LBO
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detection
Clock and
Data
Recovery
Transmitter
Internal
Termination
Receiver
Internal
Termination
TCLK2
TDN2
TD2/TDP2
RCLK2
CV2/RDN2
LOS2
RD2/RDP2
RRING2
TTIP2
TRING2
RTIP2
Channel 1
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
Line
Driver
Waveform
Shaper/LBO
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
DLOS/AIS
Detection
ALOS
Detection
Clock and
Data
Recovery
Transmitter
Internal
Termination
Receiver
Internal
Termination
TCLK1
TDN1
TD1/TDP1
RCLK1
CV1/RDN1
LOS1
RD1/RDP1
RRING1
TTIP1
TRING1
RTIP1
Remote
Loopback
G.772
Monitor
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 30 May 4, 2009
3.5 JITTER ATTENUATOR
There is one Jitter Attenuator in each channel of the LIU. The Jitter Atten-
uator can be deployed in the transmit path or the receive path, and can also
be disabled. This is selected by the JACF[1:0] bits (JACF, 03H...).
In hardware control mode, Jitter Attenuator position, bandwidth and the
depth of FIFO can be selected by JA[1:0] pins on a global basis. Refer to 5
HARDWARE CONTROL PIN SUMMARY for details.
3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
Figure-13. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF, 03H...). In hardware control mode, the depth of FIFO can be selected
by JA[1:0] pins on a global basis. Refer to 5 HARDWARE CONTROL PIN SUM-
MARY for details. Consequently, the constant delay of the Jitter Attenuator
will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but
at the cost of increasing data latency time.
Figure-13 Jitter Attenuator
In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or
6.8 Hz, as selected by the JABW bit (JACF, 03H...). In T1/J1 applications,
the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected
by the JABW bit (JACF, 03H...). The lower the Corner Frequency is, the
longer time is needed to achieve synchronization.
When the incoming data moves faster than the outgoing data, the FIFO
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 19H...).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the JAUD_IS bit (INTS1, 19H...).
For some applications that are sensitive to data corruption, the JA limit
mode can be enabled by setting JA_LIMIT bit (JACF, 03H...) to ‘1’. In the
JA limit mode, the speed of the outgoing data will be adjusted automatically
when the FIFO is close to its full or emptiness. The criteria of starting speed
adjustment are shown in Table-16. The JA limit mode can reduce the pos-
sibility of FIFO overflow and underflow, but the quality of jitter attenuation
is deteriorated.
3.5.2 JITTER ATTENUATOR PERFORMANCE
The performance of the Jitter Attenuator in the IDT82V2082 meets the
ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/
13, AT&T TR62411 specifications. Details of the Jitter Attenuator perfor-
mance is shown in Table-68 Jitter Tolerance and Table-69 Jitter Attenuator
Characteristics.
FIFO
32/64/128
DPLL
Jittered Data De-jittered Data
Jittered Clock De-jittered Clock
MCLK
WR
RCLKn
RDn/RDPn
RDNn
Table-16 Criteria of Starting Speed Adjustment
FIFO Depth Criteria for Adjusting Data Outgoing Speed
32 Bits 2 bits close to its full or emptiness
3 bits close to its full or emptiness
4 bits close to its full or emptiness
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 31 May 4, 2009
3.6 LOS AND AIS DETECTION
3.6.1 LOS DETECTION
The Loss of Signal Detector monitors the amplitude of the incoming sig-
nal level and pulse density of the received signal on RTIPn and RRINGn.
• LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0CH...). LOS will be
declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
• LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT0,
0CH...). LOS status is cleared by pulling LOSn pin to low.
Figure-14 LOS Declare and Clear
• LOS detect level threshold
In short haul mode, the amplitude threshold Q is fixed on 800 mVpp,
while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis).
In long haul mode, the value of Q can be selected by LOS[4:0] bit (RCF1,
0AH...), while P=Q+4 dB (4 dB is the LOS level detect hysteresis). The
LOS[4:0] default value is 10101 (-46 dB).
•When the chip is configured by hardware, the LOS detect level is fixed
if the IDT82V2082 operates in long haul mode. It is -46dB (E1) and -38dB
(T1/J1).
• Criteria for declare and clear of a LOS detect
The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and
G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected
by LAC bit (MAINT0, 0CH...) and T1E1 bit (GCF, 20H).
Table-17 and Table-18 summarize LOS declare and clear criteria for
both short haul and long haul application.
• All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transi-
tion” at the RTIPn/RRINGn side and output recovered clock (but the quality
of the output clock can not be guaranteed when the input level is lower than
the maximum receive sensitivity) when AISE bit (MAINT0, 0CH...) is 0; or
output All Ones as AIS when AISE bit (MAINT0, 0CH...) is 1. In this case
RCLKn output is replaced by MCLK.
On the line side, the TTIPn/TRINGn will output All Ones as AIS when
ATAO bit (MAINT0, 0CH...) is 1. The All Ones pattern uses MCLK as the
reference clock.
LOS indicator is always active for all kinds of loopback modes.
signal level<Q
(observing windows= N)
(observing windows= M)
signal level>P
density=OK
LOS=1
LOS=0
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 32 May 4, 2009
Table-17 LOS Declare and Clear Criteria for Short Haul Mode
Control bit LOS declare threshold LOS clear threshold
T1E1 LAC
1=T1/J1
0=T1.231 Level < 800 mVpp
N=175 bits
Level > 1 Vpp
M=128 bits
12.5% mark density
<100 consecutive zeroes
1=I.431 Level < 800 mVpp
N=1544 bits
Level > 1 Vpp
M=128 bits
12.5% mark density
<100 consecutive zeroes
0=E1
0=G.775 Level < 800 mVpp
N=32 bits
Level > 1 Vpp
M=32 bits
12.5% mark density
<16 consecutive zeroes
1=I.431/ETSI Level < 800 mVpp
N=2048 bits
Level > 1 Vpp
M=32 bits
12.5% mark density
<16 consecutive zeroes
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 33 May 4, 2009
Table-18 LOS Declare and Clear Criteria for Long Haul Mode
Control bit LOS declare threshold LOS clear threshold Note
T1E1 LAC LOS[4:0] Q (dB)
1=T1/J1
0
T1.231
00000
00001
…
10001
…
10101
10110-11111
-4
-6
…
-38
…
-46
-48
Level < Q
N=175 bits
Level > Q+ 4dB
M=128 bits
12.5% mark density
<100 consecutive zeroes
1
-
00000
…
00110
-4
-16
Level < Q
N=1544 bits
Level > Q+ 4dB
M=128 bits
12.5% mark density
<100 consecutive zeroes
I.431 Level detect range is -18 to -30
dB
I.431 00111
…
01101
-18
…
-30
-
01110
…
10001
…
10101
10110-11111
-32
…
-38
…
-46
-48
0=E1
0
-
00000
…
00010
-4
…
-8
Level < Q
N=32 bits
Level > Q+ 4dB
M=32 bits
12.5% mark density
<16 consecutive zeroes
G.775 Level detect range is -9 to -35
dB
G.775
00011
…
10000
-10
…
-36
-
10001
…
10101(default)
10110-11111
-38
…
-46
-48
1
-
00000 -4 Level < Q
N=2048 bits
Level > Q+ 4dB
M=32 bits
12.5% mark density
<16 consecutive zeroes
I.431 Level detect range is -6 to -20 dB
I.431/
ETSI
00001
…
01000
-6
…
-20
-
01001
…
10101(default)
10110-11111
-22
…
-46
-48
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 34 May 4, 2009
3.6.2 AIS DETECTION
The Alarm Indication Signal can be detected by the IDT82V2082 when
the Clock & Data Recovery unit is enabled. The status of AIS detection is
reflected in the AIS_S bit (STAT0, 16H...). In T1/J1 applications, the criteria
for declaring/clearing AIS detection are in compliance with the ANSI
T1.231. In E1 applications, the criteria for declaring/clearing AIS detection
comply with the ITU G.775 or the ETSI 300233, as selected by the LAC bit
(MAINT0, 0CH...). Table-19 summarizes different criteria for AIS detection
Declaring/Clearing.
Table-19 AIS Condition
ITU G.775 for E1
(LAC bit is set to ‘0’ by default)
ETSI 300233 for E1
(LAC bit is set to ‘1’)
ANSI T1.231 for T1/J1
AIS
detected
Less than 3 zeros contained in each of two consecutive
512-bit streams are received
Less than 3 zeros contained in a 512-bit
stream are received
Less than 9 zeros contained in an 8192-bit stream
(a ones density of 99.9% over a period of 5.3ms)
AIS
cleared
3 or more zeros contained in each of two consecutive
512-bit streams are received
3 or more zeros contained in a 512-bit
stream are received
9 or more zeros contained in an 8192-bit stream
are received
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 35 May 4, 2009
3.7 TRANSMIT AND DETECT INTERNAL PATTERNS
The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and
Activate/Deactivate Loopback Code) will be generated and detected by
IDT82V2082. TCLKn is used as the reference clock by default. MCLK can
also be used as the reference clock by setting the PATT_CLK bit (MAINT0,
0CH...) to ‘1’.
If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘0’ and the PATT[1:0] bits
(MAINT0, 0CH...) are set to ‘00’, the transmit path will operate in normal
mode.
When the chip is configured by hardware, the transmit path will operate
in normal mode by setting PATTn[1:0] pins to ‘00’ on a per channel basis.
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.7.1 TRANSMIT ALL ONES
In transmit direction, the All Ones data can be inserted into the data
stream when the PATT[1:0] bits (MAINT0, 0CH...) are set to ‘01’. The trans-
mit data stream is output from TTIPn/TRINGn. In this case, either TCLKn
or MCLK can be used as the transmit clock, as selected by the PATT_CLK
bit (MAINT0, 0CH...).
In hardware control mode, the All Ones data can be inserted into the data
stream in transmit direction by setting PATTn[1:0] pins to ‘01’ on a per chan-
nel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.7.2 TRANSMIT ALL ZEROS
If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘1’, the All Zeros will be
inserted into the transmit data stream when the PATT[1:0] bits (MAINT0,
0CH...) are set to ‘00’.
3.7.3 PRBS/QRSS GENERATION AND DETECTION
A PRBS/QRSS will be generated in the transmit direction and detected
in the receive direction by IDT82V2082. The QRSS is 220-1 for T1/J1 appli-
cations and the PRBS is 215-1 for E1 applications, with maximum zero
restrictions according to the AT&T TR62411 and ITU-T O.151.
When the PATT[1:0] bits (MAINT0, 0CH...) are set to ‘10’, the PRBS/
QRSS pattern will be inserted into the transmit data stream with the MSB
first. The PRBS/QRSS pattern will be transmitted directly or invertedly.
In hardware control mode, the PRBS data will be generated in the trans-
mit direction and inserted into the transmit data stream by setting
PATTn[1:0] pins to ‘10’ on a per channel basis. Refer to 5 HARDWARE CON-
TROL PIN SUMMARY for details.
The PRBS/QRSS in the received data stream will be monitored. If the
PRBS/QRSS has reached synchronization status, the PRBS_S bit
(STAT0, 16H...) will be set to ‘1’, even in the presence of a logic error rate
less than or equal to 10-1. The criteria for setting/clearing the PRBS_S bit
are shown in Table-20.
PRBS data can be inverted through setting the PRBS_INV bit (MAINT0,
0CH...).
Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,
18H...). The PRBS_IES bit (INTES, 15H...) can be used to determine
whether the ‘0’ to ‘1’ change of PRBS_S bit will be captured by the PRBS_IS
bit or any changes of PRBS_S bit will be captured by the PRBS_IS bit. When
the PRBS_IS bit is ‘1’, an interrupt will be generated if the PRBS_IM bit
(INTM0, 13H...) is set to ‘1’.
The received PRBS/QRSS logic errors can be counted in a 16-bit
counter if the ERR_SEL [1:0] bits (MAINT6, 12H...) are set to ‘00’. Refer to
3.9 ERROR DETECTION/COUNTING AND INSERTION for the operation
of the error counter.
3.8 LOOPBACK
To facilitate testing and diagnosis, the IDT82V2082 provides four dif-
ferent loopback configurations: Analog Loopback, Digital Loopback,
Remote Loopback and Inband Loopback.
3.8.1 ANALOG LOOPBACK
When the ALP bit (MAINT1, 0DH...) is set to ‘1’, the corresponding chan-
nel is configured in Analog Loopback mode. In this mode, the transmit sig-
nals are looped back to the Receiver Internal Termination in the receive
path then output from RCLKn, RDn, RDPn/RDNn. The all-ones pattern can
be generated during analog loopback. At the same time, the transmit sig-
nals are still output to TTIPn/TRINGn in transmit direction. Figure-15 shows
the process.
In hardware control mode, Analog Loopback can be selected by setting
LPn[1:0] pins to ‘01’ on a per channel basis.
3.8.2 DIGITAL LOOPBACK
When the DLP bit (MAINT1, 0DH...) is set to ‘1’, the corresponding chan-
nel is configured in Digital Loopback mode. In this mode, the transmit sig-
nals are looped back to the jitter attenuator (if enabled) and decoder in
receive path, then output from RCLKn, RDn, RDPn/RDNn. At the same
time, the transmit signals are still output to TTIPn/TRINGn in transmit direc-
tion. Figure-16 shows the process.
Both Analog Loopback mode and Digital Loopback mode allow the
sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will
overwrite the transmit signals. In this case, either TCLKn or MCLK can be
used as the reference clock for internal patterns transmission.
In hardware control mode, Digital Loopback can be selected by setting
LPn[1:0] pins to ‘10’ on a per channel basis.
Table-20 Criteria for Setting/Clearing the PRBS_S Bit
PRBS/QRSS
Detection
6 or less than 6 bit errors detected in a 64 bits hopping win-
dow.
PRBS/QRSS
Missing
More than 6 bit errors detected in a 64 bits hopping window.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 36 May 4, 2009
3.8.3 REMOTE LOOPBACK
When the RLP bit (MAINT1, 0DH...) is set to ‘1’, the corresponding chan-
nel is configured in Remote Loopback mode. In this mode, the recovered
clock and data output from Clock and Data Recovery on the receive path
is looped back to the jitter attenuator (if enabled) and Waveform Shaper in
transmit path. Figure-17 shows the process.
In hardware control mode, Remote Loopback can be selected by setting
LPn[1:0] pins to ‘11’ on a per channel basis.
Figure-15 Analog Loopback
Figure-16 Digital Loopback
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
Line
Driver
Waveform
Shaper/LBO
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detection
Clock and
Data
Recovery
Transmitter
Internal
Termination
Receiver
Internal
Termination
TCLKn
TDNn
TDn/TDPn
RCLKn
CVn/RDNn
LOSn
RDn/RDPn
RRINGn
TTIPn
TRINGn
RTIPn
Analog
Loopback
One of the Two Identical Channels
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detection
Clock and
Data
Recovery
Digital
Loopback
Receiver
Internal
Termination
TCLKn
TDNn
TDn/TDPn
RCLKn
CVn/RDNn
LOSn
RDn/RDPn
RRINGn
TTIPn
TRINGn
RTIPn
Line
Driver
Waveform
Shaper/LBO
Transmitter
Internal
Termination
One of the Two Identical Channels
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 37 May 4, 2009
Figure-17 Remote Loopback
3.8.4 INBAND LOOPBACK
When PATT[1:0] bits (MAINT0, 0CH...) are set to ‘11’, the correspond-
ing channel is configured in Inband Loopback mode. In this mode, an
unframed activate/Deactivate Loopback Code is generated repeatedly in
transmit direction per ANSI T1. 403 which overwrite the transmit signals.
In receive direction, the framed or unframed code is detected per ANSI T1.
403, even in the presence of 10-2 bit error rate.
If the Automatic Remote Loopback is enabled by setting ARLP bit
(MAINT1, 0DH...) to ‘1’, the chip will establish/demolish the Remote Loop-
back based on the reception of the Activate Loopback Code/ Deactivate
Loopback Code for 5.1 s. If the ARLP bit (MAINT1, 0DH...) is set to ‘0’, the
Remote Loopback can also be demolished forcedly.
3.8.4.1 Transmit Activate/Deactivate Loopback Code
The pattern of the transmit Activate/Deactivate Loopback Code is
defined by the TIBLB[7:0] bits (MAINT3, 0FH...). Whether the code repre-
sents an Activate Loopback Code or a Deactivate Loopback Code is judged
by the far end receiver. The length of the pattern ranges from 5 bits to 8 bits,
as selected by the TIBLB_L[1:0] bits (MAINT2, 0EH...). The pattern can be
programmed to 6-bit-long or 8-bit-long respectively by repeating itself if it
is 3-bit-long or 4-bit-long. When the PATT[1:0] bits (MAINT0, 0CH...) are
set to ‘11’, the transmission of the Activate/Deactivate Loopback Code is
initiated. If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘0’ and the
PATT[1:0] bits (MAINT0, 0CH...) are set to ‘00’, the transmission of the Acti-
vate/Deactivate Loopback Code will stop.
The local transmit activate/deactivate code setting should be the same
as the receive code setting in the remote end. It is the same thing for the
other way round.
3.8.4.2 Receive Activate/Deactivate Loopback Code
The pattern of the receive Activate Loopback Code is defined by the
RIBLBA[7:0] bits (MAINT4, 10H...). The length of this pattern ranges from
5 bits to 8 bits, as selected by the RIBLBA_L [1:0] bits (MAINT2, 0EH...).
The pattern can be programmed to 6-bit-long or 8-bit-long respectively by
repeating itself if it is 3-bit-long or 4-bit-long.
The pattern of the receive Deactivate Loopback Code is defined by the
RIBLBD[7:0] bits (MAINT5, 11H...). The length of the receive Deactivate
Loopback Code ranges from 5 bits to 8 bits, as selected by the
RIBLBD_L[1:0] bits (MAINT2, 0EH...). The pattern can be programmed to
6-bit-long or 8-bit-long respectively by repeating itself if it is 3-bit-long or 4-
bit-long.
After the Activate Loopback Code has been detected in the receive data
for more than 30 ms (in E1 mode) / 40 ms (in T1/J1 mode), the IBLBA_S
bit (STAT0, 16H...) will be set to ‘1’ to declare the reception of the Activate
Loopback Code.
After the Deactivate Loopback Code has been detected in the receive
data for more than 30 ms (In E1 mode) / 40 ms (In T1/J1 mode), the IBLBD_S
bit (STAT0, 16H...) will be set to ‘1’ to declare the reception of the Deactivate
Loopback Code.
When the IBLBA_IES bit (INTES, 15H...) is set to ‘0’, only the ‘0’ to ‘1’
transition of the IBLBA_S bit will generate an interrupt and set the IBLBA_IS
bit (INTS0, 18H...) to ‘1’. When the IBLBA_IES bit is set to ‘1’, any changes
of the IBLBA_S bit will generate an interrupt and set the IBLBA_IS bit
(INTS0, 18H...) to ‘1’. The IBLBA_IS bit will be reset to ‘0’ after being read.
When the IBLBD_IES bit (INTES, 15H...) is set to ‘0’, only the ‘0’ to ‘1’
transition of the IBLBD_S bit will generate an interrupt and set the IBLBD_IS
bit (INTS0, 18H...) to ‘1’. When the IBLBD_IES bit is set to ‘1’, any changes
of the IBLBD_S bit will generate an interrupt and set the IBLBD_IS bit
(INTS0, 18H...) to ‘1’. The IBLBD_IS bit will be reset to ‘0’ after being read.
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detection
Clock and
Data
Recovery
Receiver
Internal
Termination
TCLKn
TDNn
TDn/TDPn
RCLKn
CVn/RDNn
LOSn
RDn/RDPn
RRINGn
TTIPn
TRINGn
RTIPn
Remote
Loopback
Line
Driver
Waveform
Shaper/LBO
Transmitter
Internal
Termination
One of the Two Identical Channels
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 38 May 4, 2009
3.8.4.3 Automatic Remote Loopback
When ARLP bit (MAINT1, 0DH...) is set to ‘1’, the corresponding chan-
nel is configured into the Automatic Remote Loopback mode. In this mode,
if the Activate Loopback Code has been detected in the receive data for
more than 5.1 s, the Remote Loopback (shown as Figure-17) will be estab-
lished automatically, and the RLP_S bit (STAT1, 17H...) will be set to ‘1’ to
indicate the establishment of the Remote Loopback. The IBLBA_S bit
(STAT0, 16H...) is set to ‘1’ to generate an interrupt. In this case, the Remote
Loopback mode will still be kept even if the receiver stop receiving the Acti-
vate Loopback Code.
If the Deactivate Loopback Code has been detected in the receive data
for more than 5.1 s, the Remote Loopback will be demolished automatically,
and the RLP_S bit (STAT1, 17H...) will set to ‘0’ to indicate the demolish-
ment of the Remote Loopback. The IBLBD_S bit (STAT0, 16H...) is set to
‘1’ to generate an interrupt.
The Remote Loopback can also be demolished forcedly by setting
ARLP bit (MAINT1, 0DH...) to ‘0’.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 39 May 4, 2009
3.9 ERROR DETECTION/COUNTING AND INSERTION
3.9.1 DEFINITION OF LINE CODING ERROR
The following line encoding errors can be detected and counted by the
IDT82V2082:
• Received Bipolar Violation (BPV) Error: In AMI coding, when two
consecutive pulses of the same polarity are received, a BPV error
is declared.
• HDB3/B8ZS Code Violation (CV) Error: In HDB3/B8ZS coding, a
CV error is declared when two consecutive BPV errors are
detected, and the pulses that have the same polarity as the previ-
ous pulse are not the HDB3/B8ZS zero substitution pulses.
• Excess Zero (EXZ) Error: There are two standards defining the
EXZ errors: ANSI and FCC. The EXZ_DEF bit (MAINT6, 12H...)
chooses which standard will be adopted by the corresponding
channel to judge the EXZ error. Table-21 shows definition of EXZ.
In hardware control mode, only ANSI standard is adopted.
3.9.2 ERROR DETECTION AND COUNTING
Which type of the receiving errors (Received CV/BPV errors, excess
zero errors and PRBS logic errors) will be counted is determined by
ERR_SEL[1:0] bits (MAINT6, 12H...). Only one type of receiving error can
be counted at a time except that when the ERR_SEL[1:0] bits are set to ‘11’,
both CV/BPV and EXZ errors will be detected and counted.
The selected type of receiving errors is counted in an internal 16-bit Error
Counter. Once an error is detected, an error interrupt which is indicated by
corresponding bit in (INTS1, 19H...) will be generated if it is not masked.
This Error Counter can be operated in two modes: Auto Report Mode and
Manual Report Mode, as selected by the CNT_MD bit (MAINT6, 12H...).
In Single Rail mode, once BPV or CV errors are detected, the CVn pin will
be driven to high for one RCLK period.
• Auto Report Mode
In Auto Report Mode, the internal counter starts to count the received
errors when the CNT_MD bit (MAINT6, 12H...) is set to ‘1’. A one-second
timer is used to set the counting period. The received errors are counted
within one second. If the one-second timer expires, the value in the internal
counter will be transferred to (CNT0, 1AH...) and (CNT1, 1BH...), then the
internal counter will be reset and start to count received errors for the next
second. The errors occurred during the transfer will be accumulated to the
next round. The expiration of the one-second timer will set TMOV_IS bit
(INTS1, 19H...) to ‘1’, and will generate an interrupt if the TIMER_IM bit
(INTM1, 14H...) is set to ‘0’. The TMOV_IS bit (INTS1, 19H...) will be cleared
after the interrupt register is read. The content in the (CNT0, 1AH...) and
(CNT1, 1BH...) should be read within the next second. If the counter over-
flows, a counter overflow interrupt which is indicated by CNT_OV_IS bit
(INTS1, 19H...) will be generated if it is not masked by CNT_IM bit (INTM1,
14H...).
Figure-18 Auto Report Mode
• Manual Report Mode
In Manual Report Mode, the internal Error Counter starts to count the
received errors when the CNT_MD bit (MAINT6, 12H...) is set to ‘0’. When
there is a ‘0’ to ‘1’ transition on the CNT_TRF bit (MAINT6, 12H...), the data
in the counter will be transferred to (CNT0, 1AH...) and (CNT1, 1BH...), then
the counter will be reset. The errors occurred during the transfer will be
accumulated to the next round. If the counter overflows, a counter overflow
interrupt indicated by CNT_OV_IS bit (INTS1, 19H...) will be generated if
it is not masked by CNT_IM bit (INTM1, 14H...).
Table-21 EXZ Definition
EXZ Definition
ANSI FCC
AMI More than 15 consecutive zeros are detected More than 80 consecutive zeros are detected
HDB3 More than 3 consecutive zeros are detected More than 3 consecutive zeros are detected
B8ZS More than 7 consecutive zeros are detected More than 7 consecutive zeros are detected
One-Second Timer expired?
counting
Auto Report Mode
(CNT_MD=1)
Bit TMOV_IS is set to '1'
Y
N
CNT0, CNT1 data in counter
counter 0
read the data in CNT0, CNT1 within
the next second
next second
repeats the
same process
Bit TMOV_IS is cleared after
the interrupt register is read
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 40 May 4, 2009
Figure-19 Manual Report Mode
Note: It is recommended that users should do the followings within next round of error count-
ing: Read the data in CNT0 and CNT1; Reset CNT_TRF bit for the next ‘0’ to ‘1’ tran-
sition on this bit.
3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION
Only when three consecutive ‘1’s are detected in the transmit data
stream, will a ‘0’ to ‘1’ transition on the BPV_INS bit (MAINT6, 12H...) gen-
erate a bipolar violation pulse, and the polarity of the second ‘1’ in the series
will be inverted.
A ‘0’ to ‘1’ transition on the EER_INS bit (MAINT6, 12H...) will generate
a logic error during the PRBS/QRSS transmission.
3.10 LINE DRIVER FAILURE MONITORING
The transmit driver failure monitor can be enabled or disabled by setting
DFM_OFF bit (TCF1, 05H...). If the transmit driver failure monitor is
enabled, the transmit driver failure will be captured by DF_S bit (STAT0,
16H...). The transition of the DF_S bit is reflected by DF_IS bit (INTS0,
18H...), and, if enabled by DF_IM bit (INTM0, 13H...), will generate an inter-
rupt. When there is a short circuit on the TTIPn/TRINGn port, the output cur-
rent will be limited to 100 mA (typical), and an interrupt will be generated.
In hardware control mode, the transmit driver failure monitor is always
enabled.
A '0' to '1' transition
on CNT_TRF?
counting
Manual Report mode
(CNT_MD=0)
CNT0, CNT1 data in
counter
counter 0
Y
N
next round
repeat the
same process
Read the data in CNT0,
CNT1 within next round1
Reset CNT_TRF for the
next '0' to '1' transition
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 41 May 4, 2009
3.11 MCLK AND TCLK
3.11.1 MASTER CLOCK (MCLK)
MCLK is an independent, free-running reference clock. MCLK is 1.544
MHz for T1/J1 applications and 2.048 MHz in E1 mode. This reference clock
is used to generate several internal reference signals:
• Timing reference for the integrated clock recovery unit.
• Timing reference for the integrated digital jitter attenuator.
• Timing reference for microcontroller interface.
• Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
• Reference clock during Transmit All Ones (TAOS), all zeros, PRBS/
QRSS and Inband Loopback code if it is selected as the reference
clock. For ATAO and AIS, MCLK is always used as the reference
clock.
• Reference clock during Transmit All Ones (TAO) condition or send-
ing PRBS/QRSS in hardware control mode.
Figure-20 shows the chip operation status in different conditions of
MCLK and TCLKn. The missing of MCLK will set all the TTIPn/TRINGn to
high impedance state.
3.11.2 TRANSMIT CLOCK (TCLK)
TCLKn is used to sample the transmit data on TDn/TDPn, TDNn. The
active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0, 04H...).
During Transmit All Ones, PRBS/QRSS patterns or Inband Loopback
Code, either TCLKn or MCLK can be used as the reference clock. This is
selected by the PATT_CLK bit (MAINT0, 0CH...).
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0CH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0CH) is set to ‘1’.
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
bit (STAT0, 16H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
is not using MCLK to transmit internal patterns (TAOS, All Zeros, PRBS and
in-band loopback code). When TCLK is detected again, TCLK_LOS bit
(STAT0, 16H...) will be cleared. The reference frequency to detect a TCLK
loss is derived from MCLK.
Figure-20 TCLK Operation Flowchart
both the transmitters high
impedance
yes
MCLK=H/L?
normal operation
Clocked
TCLKn status?
L/H clocked
generate transmit clock loss
interrupt if not masked in
software control mode;
transmitter n high impedance
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 42 May 4, 2009
3.12 MICROCONTROLLER INTERFACES
The microcontroller interface provides access to read and write the reg-
isters in the device. The chip supports serial microcontroller interface and
two kinds of parallel microcontroller interface: Motorola non-Multiplexed
mode and Intel non-Multiplexed mode. Different microcontroller interfaces
can be selected by setting MODE[1:0] pins to different values. Refer to
MODE1 and MODE0 in pin description and 8 MICROCONTROLLER
INTERFACE TIMING CHARACTERISTICS for details
3.12.1 PARALLEL MICROCONTROLLER INTERFACE
The interface is compatible with Motorola or Intel microcontroller. When
MODE[1:0] pins are set to ‘10’, Parallel-non-Multiplexed-Motorola interface
is selected. When MODE[1:0] pins are set to ‘11’, Parallel-non-Multiplexed-
Intel Interface is selected. Refer to 8 MICROCONTROLLER INTERFACE
TIMING CHARACTERISTICS for details.
3.12.2 SERIAL MICROCONTROLLER INTERFACE
When MODE[1:0] pins are set to ‘01’, Serial Interface is selected. In this
mode, the registers are programmed through a 16-bit word which contains
an 8-bit address/command byte (6 address bits A0~A5 and bit R/W) and
an 8-bit data byte (D0~D7). When bit R/W is ‘1’, data is read out from pin
SDO. When bit R/W is ‘0’, data is written into SDI pin. Refer to Figure-21.
Figure-21 Serial Microcontroller Interface Function Timing
R/W
A0 A1 A2 A3 A4 A5 -D1 D2 D3 D4 D5 D6 D7
CS
SCLK
SDI
address/command byte input data byte (R/W=0)
D0 D1 D2 D3 D4 D5 D6 D7
remains high impedance
SDO
output data byte (R/W=1)
D0
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 43 May 4, 2009
3.13 INTERRUPT HANDLING
All kinds of interrupt of the IDT82V2082 are indicated by the INT pin.
When the INT_PIN[0] bit (GCF, 20H) is ‘0’, the INT pin is open drain active
low, with a 10 KΩ external pull-up resistor. When the INT_PIN[1:0] bits
(GCF, 20H) are ‘01’, the INT pin is push-pull active low; when the
INT_PIN[1:0] bits are ‘10’, the INT pin is push-pull active high.
All the interrupt can be disabled by the INTM_GLB bit (GCF, 20H). When
the INTM_GLB bit (GCF, 20H) is set to ‘0’, an active level on the INT pin
represents an interrupt of the IDT82V2082. The INT_CH[1:0] (GCF, 20H)
should be read to identify which channel(s) generate the interrupt.
The interrupt event is captured by the corresponding bit in the Interrupt
Status Register (INTS0, 18H...) or (INTS1, 19H...). Every kind of interrupt
can be enabled/disabled individually by the corresponding bit in the register
(INTM0, 13H...) or (INTM1, 14H...). Some event is reflected by the corre-
sponding bit in the Status Register (STAT0, 16H...) or (STAT1, 17H...), and
the Interrupt Trigger Edge Selection Register can be used to determine how
the Status Register sets the Interrupt Status Register.
After the Interrupt Status Register (INTS0, 18H...) or (INTS1, 19H...) is
read, the corresponding bit indicating which channel generates the inter-
rupt in the INTCH register (21H) will be reset. Only when all the pending
interrupt is acknowledged through reading the Interrupt Status Registers
of all the channels (INTS0, 18H...) or (INTS1, 19H...) will all the bits in the
INTCH register (21H) be reset and the INT pin become inactive.
There are totally fourteen kinds of events that could be the interrupt
source for one channel:
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).Inband Loopback Code Status
(11).Equalizer Out of Range
(12).One-Second Timer Expired
(13). Error Counter Overflow
(14).Arbitrary Waveform Generator Overflow
Table-22 is a summary of all kinds of interrupt and the associated Status
bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt
Mask bit.
Table-22 Interrupt Event
Interrupt Event Status bit
(STAT0, STAT1)
Interrupt Status bit
(INTS0, INTS1)
Interrupt Edge Selection
bit
(INTES)
Interrupt Mask bit
(INTM0, INTM1)
LOS Detected LOS_S LOS_IS LOS_IES LOS_IM
AIS Detected AIS_S AIS_IS AIS_IES AIS_IM
Driver Failure Detected DF_S DF_IS DF_IES DF_IM
TCLK Loss TCLK_LOS TCLK_LOS_IS TCLK_IES TCLK_IM
Synchronization Status of PRBS/QRSS PRBS_S PRBS_IS PRBS_IES PRBS_IM
PRBS/QRSS Error ERR_IS ERR_IM
Code Violation Received CV_IS CV_IM
Excessive Zeros Received EXZ_IS EXZ_IM
JA FIFO Overflow JAOV_IS JAOV_IM
JA FIFO Underflow JAUD_IS JAUD_IM
Equalizer Out of Range EQ_S EQ_IS EQ_IES EQ_IM
Inband Loopback Activate Code Status IBLBA_S IBLBA_IS IBLBA_IES IBLBA_IM
Inband Loopback Deactivate Code Status IBLBD_S IBLBD_IS IBLBD_IES IBLBD_IM
One-Second Timer Expired TMOV_IS TIMER_IM
Error Counter Overflow CNT_OV_IS CNT_IM
Arbitrary Waveform Generator Overflow DAC_OV_IS DAC_OV_IM
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION 44 May 4, 2009
3.14 5V TOLERANT I/O PINS
All digital input pins will tolerate 5.0 ± 10% volts and are compatible with
TTL logic.
3.15 RESET OPERATION
The chip can be reset in two ways:
• Software Reset: Writing to the RST register (01H) will reset the chip
in 1 µs.
• Hardware Reset: Asserting the RST pin low for a minimum of 100 ns
will reset the chip.
During Hardware Reset, the device requires an active clock on MCLK.
For T1/J1 operation, bit T1E1 (GCF0) is set after reset. Before access-
ing any other regisers a delay of 50 us is required to allow the internal
clocking to be settled.
After reset, all drivers output are in high impedance state, all the internal
flip-flops are reset, and all the registers are initialized to default values.
When performing a software reset, the T1E1 bit (GCF0) will not be reset
and stay with the set value.
3.16 POWER SUPPLY
This chip uses a single 3.3 V power supply.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION 45 May 4, 2009
4 PROGRAMMING INFORMATION
4.1 REGISTER LIST AND MAP
The IDT82V2082 registers can be divided into Global Registers and
Local Registers. The operation on the Global Registers affects both of the
two channels while the operation on Local Registers only affects the spe-
cific channel. For different channel, the address of Local Register is differ-
ent. Table-23 is the map of Global Registers and Table-24 is the map of
Local Registers. If the configuration of both of the two channels is the same,
the COPY bit (GCF, 20H) can be set to ‘1’ to establish the Broadcasting
mode. In the Broadcasting mode, the Writing operation on any of the two
channels’ registers will be copied to the corresponding registers of the other
channel.
4.2 Reserved Registers
When writing to registers with reserved bit locations, the default state
must be written to the reserved bits to ensure proper device operation.
Table-23 Global Register List and Map
Address (hex) Register R/W MAP
CH1 CH2 b7 b6 b5 b4 b3 b2 b1 b0
00 ID R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
01 RST W
20 GCF R/W MONT1 MONT0 - T1E1 COPY INTM_GLB INT_PIN1 INT_PIN0
21 INTCHR------INT_CH2INT_CH1
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION 46 May 4, 2009
Table-24 Per Channel Register List and Map
Address (hex) Register R/W MAP
CH1 CH2 b7 b6 b5 b4 b3 b2 b1 b0
Transmit and receive termination register
02 22 TERM R/W - - T_TERM2 T_TERM1 T_TERM0 R_TERM2 R_TERM1 R_TERM0
Jitter attenuation control register
03 23 JACF R/W - - JA_LIMIT JACF1 JACF0 JADP1 JADP0 JABW
Transmit path control registers
04 24 TCF0 R/W - - - T_OFF TD_INV TCLK_SEL T_MD1 T_MD0
05 25 TCF1 R/W - - DFM_OFF THZ PULS3 PULS2 PULS1 PULS0
06 26 TCF2 R/W - - SCAL5 SCAL4 SCAL3 SCAL2 SCAL1 SCAL0
07 27 TCF3 R/W DONE RW UI1 UI0 SAMP3 SAMP2 SAMP1 SAMP0
08 28 TCF4 R/W - WDAT6 WDAT5 WDAT4 WDAT3 WDAT2 WDAT1 WDAT0
Receive path control registers
09 29 RCF0 R/W - - - R_OFF RD_INV RCLK_SEL R_MD1 R_MD0
0A 2A RCF1 R/W - EQ_ON - LOS4 LOS3 LOS2 LOS1 LOS0
0B 2B RCF2 R/W - - SLICE1 SLICE0 UPDW1 UPDW0 MG1 MG0
Network Diagnostics control registers
0C 2C MAINT0 R/W - PATT1 PATT0 PATT_CLK PRBS_INV LAC AISE ATAO
0D 2D MAINT1 - - - - ARLP RLP ALP DLP
0E 2E MAINT2 R/W - - TIBLB_L1 TIBLB_L0 RIBLBA_L1 RIBLBA_L0 RIBLBD_L1 RIBLBD_L0
0F 2F MAINT3 R/W TIBLB7 TIBLB6 TIBLB5 TIBLB4 TIBLB3 TIBLB2 TIBLB1 TIBLB0
10 30 MAINT4 R/W RIBLBA7 RIBLBA6 RIBLBA5 RIBLBA4 RIBLBA3 RIBLBA2 RIBLBA1 RIBLBA0
11 31 MAINT5 R/W RIBLBD7 RIBLBD6 RIBLBD5 RIBLBD4 RIBLBD3 RIBLBD2 RIBLBD1 RIBLBD0
12 32 MAINT6 R/W - BPV_INS ERR_INS EXZ_DEF ERR_SEL1 ERR_SEL0 CNT_MD CNT_TRF
Interrupt control registers
13 33 INTM0 R/W EQ_IM IBLBA_IM IBLBD_IM PRBS_IM TCLK_IM DF_IM AIS_IM LOS_IM
14 34 INTM1 R/W DAC_OV_IM JAOV_IM JAUD_IM ERR_IM EXZ_IM CV_IM TIMER_IM CNT_IM
15 35 INTES R/W EQ_IES IBLBA_IES IBLBD_IES PRBS_IES TCLK_IES DF_IES AIS_IES LOS_IES
Line status registers
16 36 STAT0 R EQ_S IBLBA_S IBLBD_S PRBS_S TCLK_LOS DF_S AIS_S LOS_S
17 37 STAT1 R - - RLP_S LATT4 LATT3 LATT2 LATT1 LATT0
Interrupt status registers
18 38 INTS0 R EQ_IS IBLBA_IS IBLBD_IS PRBS_IS TCLK_LOS_IS DF_IS AIS_IS LOS_IS
19 39 INTS1 R DAC_OV_IS JAOV_IS JAUD_IS ERR_IS EXZ_IS CV_IS TMOV_IS CNT_OV_IS
Counter registers
1A 3A CNT0 R Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1B 3B CNT1 R Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION 47 May 4, 2009
4.3 REGISTER DESCRIPTION
4.3.1 GLOBAL REGISTERS
Table-25 ID: Device Revision Register
(R, Address = 00H)
Symbol Bit Default Description
ID[7:0] 7-0 00H Current Silicon Chip ID.
Table-26 RST: Reset Register
(W, Address = 01H)
Symbol Bit Default Description
RST[7:0] 7-0 00H Software reset. A write operation on this register will reset all internal registers to their default values, and the status
of all ports are set to the default status. The content in this register can not be changed. After reset, all drivers output
are in high impedance state. Note: Bit T1E1 (GCF0) will keep set value and will not be reset.
Table-27 GCF: Global Configuration Register
(R/W, Address = 20H)
Symbol Bit Default Description
MONT[1:0] 7-6 00 G.772 monitor
= 00/10: Normal
= 01: Receiver 1 monitors the receive path of channel 2
= 11: Receiver 1 monitors the transmit path of channel 2
- 5 0 Reserved.
T1E1 4 0 This bit selects the E1 or T1/J1 operation mode globally.
= 0: E1 mode is selected.
= 1: T1/J1 mode is selected.
Note: After bit T1E1 is changed: Before accessing any other regisers a delay of 50us is required to allow the internal
clocking to be settled.
COPY 3 0 Enable broadcasting mode.
= 0: Broadcasting mode disabled
= 1: Broadcasting mode enabled. Writing operation on one channel's register will be copied exactly to the corre-
sponding registers in other channel.
INTM_GLB 2 1 Global interrupt enable
= 0: Interrupt is globally enabled. But for each individual interrupt, it still can be disabled by its corresponding Inter-
rupt mask Bit.
= 1: All the interrupts are disabled for both channels.
INT_PIN[1:0] 1-0 00 Interrupt pin control
= x0: Open drain, active low (with an external pull-up resistor)
= 01: Push-pull, active low
= 11: Push-pull, active high
Table-28 INTCH: Interrupt Channel Indication Register
(R, Address =21H)
Symbol Bit Default Description
- 7-2 000000 Reserved.
INT_CH[1:0] 1-0 00 INT_CH[n]=0 indicates that an interrupt was generated by channel [n+1].
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION 48 May 4, 2009
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER
4.3.3 JITTER ATTENUATION CONTROL REGISTER
Table-29 TERM: Transmit and Receive Termination Configuration Register
(R/W, Address = 02H, 22H)
Symbol Bit Default Description
- 7-6 00 Reserved.
T_TERM[2:0] 5-3 000 These bits select the internal termination for transmit line impedance matching.
= 000: Internal 75 Ω impedance matching
= 001: Internal 120 Ω impedance matching
= 010: Internal 100 Ω impedance matching
= 011: Internal 110 Ω impedance matching
= 1xx: Selects external impedance matching resistors for E1 mode only. T1/J1 does not require external impedance
resistors (see Table-14).
R_TERM[2:0] 2-0 000 These bits select the internal termination for receive line impedance matching.
= 000: Internal 75 Ω impedance matching
= 001: Internal 120 Ω impedance matching
= 010: Internal 100 Ω impedance matching
= 011: Internal 110 Ω impedance matching
= 1xx: Selects external impedance matching resistors (see Table-15).
Table-30 JACF: Jitter Attenuation Configuration Register
(R/W, Address = 03H, 23H)
Symbol Bit Default Description
- 7-6 00 Reserved.
JA_LIMIT 5 1 = 0: Normal mode
= 1: JA limit mode
JACF[1:0] 4-3 00 Jitter Attenuation configuration
= 00/10: JA not used
= 01: JA in transmit path
= 11: JA in receive path
JADP[1:0] 2-1 00 Jitter Attenuation depth select
= 00: 128 bits
= 01: 64 bits
= 1x: 32 bits
JABW 0 0 Jitter transfer function bandwidth select
= 0: 6.8 Hz (E1)
5 Hz (T1/J1)
= 1: 0.9 Hz (E1)
1.25 Hz (T1/J1)
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION 49 May 4, 2009
4.3.4 TRANSMIT PATH CONTROL REGISTERS
Table-31 TCF0: Transmitter Configuration Register 0
(R/W, Address = 04H, 24H)
Symbol Bit Default Description
- 7-5 000 Reserved
T_OFF 4 0 Transmitter power down enable
= 0: Transmitter power up
= 1: Transmitter power down (line driver high impedance)
TD_INV 3 0 Transmit data invert
= 0: Data on TDn or TDPn/TDNn is active high
= 1: Data on TDn or TDPn/TDNn is active low
TCLK_SEL 2 0 Transmit clock edge select
= 0: Data on TDPn/TDNn is sampled on the falling edge of TCLKn
= 1: Data on TDPn/TDNn is sampled on the rising edge of TCLKn
T_MD[1:0] 0-1 00 Transmitter operation mode control
T_MD[1:0] select different stages of the transmit data path
= 00: Enable HDB3/B8ZS encoder and waveform shaper blocks. Input on pin TDn is single rail NRZ data
= 01: Enable AMI encoder and waveform shaper blocks. Input on pin TDn is single rail NRZ data
= 1x: Encoder is bypassed, dual rail NRZ transmit data input on pin TDPn/TDNn
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION 50 May 4, 2009
1. In internal impedance matching mode, for E1/75 Ω cable impedance, the PULS[3:0] bits (TCF1, 05H...) should be set to ‘0000’. In external impedance matching
mode, for E1/75 Ω cable impedance, the PULS[3:0] bits should be set to ‘0001’.
Table-32 TCF1: Transmitter Configuration Register 1
(R/W, Address = 05H, 25H)
Symbol Bit Default Description
- 7-6 00 Reserved. This bit should be ‘0’ for normal operation.
DFM_OFF 5 0 Transmit driver failure monitor disable
= 0: DFM is enabled
= 1: DFM is disabled
THZ 4 1 Transmit line driver high impedance enable
= 0: Normal state
= 1: Transmit line driver high impedance enable (other transmit path still work normally).
PULS[3:0] 3-0 0000 These bits select the transmit template/LBO for short-haul/long-haul applications.
T1/E1/J1 TCLK Cable impedance Cable range or
LBO
Allowable Cable
loss
00001E1 2.048 MHz 75 Ω- 0-43 dB
0001 E1 2.048 MHz 120
Ω- 0-43 dB
0010 DSX1 1.544 MHz 100
Ω0-133 ft 0-0.6 dB
0011 DSX1 1.544 MHz 100
Ω133-266 ft 0.6-1.2 dB
0100 DSX1 1.544 MHz 100
Ω266-399 ft 1.2-1.8 dB
0101 DSX1 1.544 MHz 100
Ω399-533 ft 1.8-2.4 dB
0110 DSX1 1.544 MHz 100
Ω533-655 ft 2.4-3.0 dB
0111 J1 1.544 MHz 110
Ω0-655 ft 0-3.0 dB
1000 DS1 1.544 MHz 100
Ω 0 dB LBO 0-36 dB
1001 DS1 1.544 MHz 100
Ω-7.5 dB LBO 0-28.5 dB
1010 DS1 1.544 MHz 100
Ω-15.0 dB LBO 0-21 dB
1011 DS1 1.544 MHz 100 Ω-22.5 dB LBO 0-13.5 dB
11xx User programmable waveform setting
Table-33 TCF2: Transmitter Configuration Register 2
(R/W, Address = 06H, 26H)
Symbol Bit Default Description
- 7-6 00 Reserved.
SCAL[5:0] 5-0 100001 SCAL specifies a scaling factor to be applied to the amplitude of the user-programmable arbitrary pulses which is
to be transmitted if needed. The default value of SCAL[5:0] is ‘100001’. Refer to 3.3.3.3 User-Programmable Arbi-
trary Waveform.
= 110110: Default value for T1 0~133 ft, T1 133~266 ft, T1 266~399 ft, T1 399~533 ft, T1 533~655 ft, J1 0~655 ft
and DS1 0 dB LBO. One step change of this value results in 2% scaling up/down against the pulse amplitude.
=010001: Default value for DS1 -7.5 dB LBO. One step change of this value results in 6.25% scaling up/down
against the pulse amplitude.
= 001000: Default value for DS1 -15.0 dB LBO. One step change of this value results in 12.5% scaling up/down
against the pulse amplitude.
= 000100: Default value for DS1 -22.5 dB LBO. One step change of this value results in 25% scaling up/down
against the pulse amplitude.
= 100001: Default value for E1 75 Ω and 120 Ω. One step change of this value results in 3% scaling up/down
against the pulse amplitude.
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4.3.5 RECEIVE PATH CONTROL REGISTERS
Table-34 TCF3: Transmitter Configuration Register 3
(R/W, Address = 07H, 27H)
Symbol Bit Default Description
DONE 7 0 After ‘1’ is written to this bit, a read or write operation is implemented.
RW 6 0 This bit selects read or write operation
= 0: Write to RAM
= 1: Read from RAM
UI[1:0] 5-4 00 These bits specify the unit interval address. There are totally 4 unit intervals.
= 00: UI address is 0 (The most left UI)
= 01: UI address is 1
= 10: UI address is 2
= 11: UI address is 3
SAMP[3:0] 3-0 0000 These bits specify the sample address. Each UI has totally 16 samples.
= 0000: Sample address is 0 (The most left sample)
= 0001: Sample address is 1
= 0010: Sample address is 2
……
= 1110: Sample address is 14
= 1111: Sample address is 15
Table-35 TCF4: Transmitter Configuration Register 4
(R/W, Address = 08H, 28H)
Symbol Bit Default Description
-70Reserved
WDAT[6:0] 6-0 0000000 In Indirect Write operation, the WDAT[6:0] will be loaded to the pulse template RAM, specifying the amplitude of
the Sample.
After an Indirect Read operation, the amplitude data of the Sample in the pulse template RAM will be output to the
WDAT[6:0].
Table-36 RCF0: Receiver Configuration Register 0
(R/W, Address = 09H, 29H)
Symbol Bit Default Description
- 7-5 000 Reserved
R_OFF 4 0 Receiver power down enable
= 0: Receiver power up
= 1: Receiver power down
RD_INV 3 0 Receive data invert
= 0: Data on RDn or RDPn/RDNn is active high
= 1: Data on RDn or RDPn/RDNn is active low
RCLK_SEL 2 0 Receive clock edge select (this bit is ignored in slicer mode)
= 0: Data on RDn or RDPn/RDNn is updated on the rising edge of RCLKn
= 1: Data on RDn or RDPn/RDNn is updated on the falling edge of RCLKn
R_MD[1:0] 1-0 00 Receive path decoding selection
= 00: Receive data is HDB3 (E1)/B8ZS (T1/J1) decoded and output on RDn pin with single rail NRZ format
= 01: Receive data is AMI decoded and output on RDn pin with single rail NRZ format
= 10: Decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with clock
recovery)
= 11: CDR and decoder are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
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Table-37 RCF1: Receiver Configuration Register 1
(R/W, Address= 0AH, 2AH)
Symbol Bit Default Description
-70Reserved
EQ_ON 6 0 = 0: Receive equalizer off (short haul receiver)
= 1: Receive equalizer on (long haul receiver)
- 5 0 Reserved.
LOS[4:0] 4:0 10101 LOS Clear Level (dB) LOS Declare Level (dB)
00000 0 <-4
00001 >-2 <-6
00010 >-4 <-8
00011 >-6 <-10
00100 >-8 <-12
00101 >-10 <-14
00110 >-12 <-16
00111 >-14 <-18
01000 >-16 <-20
01001 >-18 <-22
01010 >-20 <-24
01011 >-22 <-26
01100 >-24 <-28
01101 >-26 <-30
01110 >-28 <-32
01111 >-30 <-34
10000 >-32 <-36
10001 >-34 <-38
10010 >-36 <-40
10011 >-38 <-42
10100 >-40 <-44
10101 >-42 <-46
10110 -11111 >-44 <-48
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS
Table-38 RCF2: Receiver Configuration Register 2
(R/W, Address = 0BH, 2BH)
Symbol Bit Default Description
- 7-6 00 Reserved.
SLICE[1:0] 5-4 01 Receive slicer threshold
= 00: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 40% of the peak amplitude.
= 01: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 50% of the peak amplitude.
= 10: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 60% of the peak amplitude.
= 11: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 70% of the peak amplitude.
UPDW[1:0] 3-2 10 Equalizer observation window
= 00: 32 bits
= 01: 64 bits
= 10: 128 bits
= 11: 256 bits
MG[1:0] 1-0 00 Monitor gain setting: these bits select the internal linear gain boost
= 00: 0 dB
= 01: 22 dB
= 10: 26 dB
= 11: 32 dB
Table-39 MAINT0: Maintenance Function Control Register 0
(R/W, Address = 0CH, 2CH)
Symbol Bit Default Description
- 7 0 Reserved.
PATT[1:0] 6-5 00 These bits select the internal pattern and insert it into transmit data stream.
= 00: Normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1)
= 01: Insert All Ones
= 10: Insert PRBS (E1: 215-1) or QRSS (T1/J1: 220-1)
= 11: Insert programmable Inband loopback activate or deactivate code (default value 00001)
PATT_CLK 4 0 Selects reference clock for transmitting internal pattern
= 0: Uses TCLKn as the reference clock
= 1: Uses MCLK as the reference clock
PRBS_INV 3 0 Inverts PRBS
= 0: The PRBS data is not inverted
= 1: The PRBS data is inverted before transmission and detection
LAC 2 0 LOS/AIS criterion is selected as below:
= 0: G.775 (E1) / T1.231 (T1/J1)
= 1: ETSI 300233& I.431 (E1) / I.431 (T1/J1)
AISE 1 0 AIS enable during LOS
= 0: AIS insertion on RDPn/RDNn/RCLKn is disabled during LOS
= 1: AIS insertion on RDPn/RDNn/RCLKn is enabled during LOS
ATAO 0 0 Automatically Transmit All Ones (enabled only when PATT[1:0] = 00)
= 0: Disabled
= 1: Automatically Transmit All Ones pattern at TTIPn/TRINGn during LOS
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Table-40 MAINT1: Maintenance Function Control Register 1
(R/W, Address= 0DH, 2DH)
Symbol Bit Default Description
- 7-4 0000 Reserved
ARLP 3 0 Automatic remote loopback enable
= 0: Disables automatic remote loopback (normal transmit and receive operation)
= 1: Enables automatic remote loopback
RLP 2 0 Remote loopback enable
= 0: Disables remote loopback (normal transmit and receive operation)
= 1: Enables remote loopback
ALP 1 0 Analog loopback enable
= 0: Disables analog loopback (normal transmit and receive operation)
= 1: Enables analog loopback
DLP 0 0 Digital loopback enable
= 0: Disables digital loopback (normal transmit and receive operation)
= 1: Enables digital loopback
Table-41 MAINT2: Maintenance Function Control Register 2
(R/W, Address = 0EH, 2EH)
Symbol Bit Default Description
- 7-6 00 Reserved
TIBLB_L[1:0] 5-4 00 Defines the length of the user-programmable transmit loopback activate/deactivate code contained in TIBLB reg-
ister. The default selection is 5 bits length.
= 00: 5-bit long activate code in TIBLB [4:0]
= 01: 6-bit long activate code in TIBLB [5:0]
= 10: 7-bit long activate code in TIBLB [6:0]
= 11: 8-bit long activate code in TIBLB [7:0]
RIBLBA_L[1:0] 3-2 00 Defines the length of the user-programmable receive activate loopback code contained in RIBLBA register. The
default selection is 5 bits length.
= 00: 5-bit long activate code in RIBLBA [4:0]
= 01: 6-bit long activate code in RIBLBA [5:0]
= 10: 7-bit long activate code in RIBLBA [6:0]
= 11: 8-bit long activate code in RIBLBA [7:0]
RIBLBD_L[1:0] 1-0 01 Defines the length of the user-programmable receive deactivate loopback code contained in RIBLBD register. The
default selection is 6 bits length.
= 00: 5-bit long deactivate code in RIBLBD [4:0]
= 01: 6-bit long deactivate code in RIBLBD [5:0]
= 10: 7-bit long deactivate code in RIBLBD [6:0]
= 11: 8-bit long deactivate code in RIBLBD [7:0]
Table-42 MAINT3: Maintenance Function Control Register 3
(R/W, Address = 0FH, 2FH)
Symbol Bit Default Description
TIBLB[7:0] 7-0 (000)00001 Defines the user-programmable transmit Inband loopback activate or deactivate code. The default selection is
00001.
TIBLB [7:0] form the 8-bit repeating code
TIBLB [6:0] form the 7-bit repeating code
TIBLB [5:0] form the 6-bit repeating code
TIBLB [4:0] form the 5-bit repeating code
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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Table-43 MAINT4: Maintenance Function Control Register 4
(R/W, Address = 10H, 30H)
Symbol Bit Default Description
RIBLBA[7:0] 7-0 (000)00001 Defines the user-programmable receive Inband loopback activate code. The default selection is 00001.
RIBLBA [7:0] form the 8-bit repeating code
RIBLBA [6:0] form the 7-bit repeating code
RIBLBA [5:0] form the 6-bit repeating code
RIBLBA [4:0] form the 5-bit repeating code
Table-44 MAINT5: Maintenance Function Control Register 5
(R/W, Address = 11H, 31H)
Symbol Bit Default Description
RIBLBD[7:0] 7-0 (00)001001 Defines the user-programmable receive Inband loopback deactivate code. The default selection is 001001.
RIBLBD [7:0] form the 8-bit repeating code
RIBLBD [6:0] form the 7-bit repeating code
RIBLBD [5:0] form the 6-bit repeating code
RIBLBD [4:0] form the 5-bit repeating code
Table-45 MAINT6: Maintenance Function Control Register 6
(R/W, Address = 12H, 32H)
Symbol Bit Default Description
- 7 0 Reserved.
BPV_INS 6 0 BPV error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream.
This bit must be cleared and set again for a subsequent error to be inserted.
ERR_INS 5 0 PRBS logic error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single PRBS logic error to be inserted into the transmit PRBS data stream.
This bit must be cleared and set again for a subsequent error to be inserted.
EXZ_DEF 4 0 EXZ definition select
= 0: ANSI
= 1: FCC
ERR_SEL 3-2 00 These bits choose which type of error will be counted
= 00: The PRBS logic error is counted by a 16-bit error counter
= 01: The EXZ error is counted by a 16-bit error counter
= 10: The Received CV (BPV) error is counted by a 16-bit error counter
= 11: Both CV (BPV) and EXZ errors are counted by a 16-bit error counter.
CNT_MD 1 0 Counter operation mode select
= 0: Manual Report mode
= 1: Auto Report mode
CNT_TRF 0 0 = 0: Clear this bit for the next ‘0’ to ‘1’ transition on this bit.
= 1: Error counting result is transferred to CNT0 and CNT1 and the error counter is reset.
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4.3.7 INTERRUPT CONTROL REGISTERS
Table-46 INTM0: Interrupt Mask Register 0
(R/W, Address = 13H, 33H)
Symbol Bit Default Description
EQ_IM 7 1 Equalizer out of range interrupt mask
= 0: Equalizer out of range interrupt enabled
= 1: Equalizer out of range interrupt masked
IBLBA_IM 6 1 In-band Loopback activate code detect interrupt mask
= 0: In-band Loopback activate code detect interrupt enabled
= 1: In-band Loopback activate code detect interrupt masked
IBLBD_IM 5 1 In-band Loopback deactivate code detect interrupt mask
= 0: In-band Loopback deactivate code detect interrupt enabled
= 1: In-band Loopback deactivate code detect interrupt masked
PRBS_IM 4 1 PRBS synchronic signal detect interrupt mask
= 0: PRBS synchronic signal detect interrupt enabled
= 1: PRBS synchronic signal detect interrupt masked
TCLK_IM 3 1 TCLK loss detect interrupt mask
= 0: TCLK loss detect interrupt enabled
= 1: TCLK loss detect interrupt masked
DF_IM 2 1 Driver Failure interrupt mask
= 0: Driver Failure interrupt enabled
= 1: Driver Failure interrupt masked
AIS_IM 1 1 Alarm Indication Signal interrupt mask
= 0: Alarm Indication Signal interrupt enabled
= 1: Alarm Indication Signal interrupt masked
LOS_IM 0 1 Loss Of Signal interrupt mask
= 0: Loss Of Signal interrupt enabled
= 1: Loss Of Signal interrupt masked
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Table-47 INTM1: Interrupt Masked Register 1
(R/W, Address = 14H, 34H)
Symbol Bit Default Description
DAC_OV_IM 7 1 DAC arithmetic overflow interrupt mask
= 0: DAC arithmetic overflow interrupt enabled
= 1: DAC arithmetic overflow interrupt masked
JAOV_IM 6 1 JA overflow interrupt mask
= 0: JA overflow interrupt enabled
= 1: JA overflow interrupt masked
JAUD_IM 5 1 JA underflow interrupt mask
= 0: JA underflow interrupt enabled
= 1: JA underflow interrupt masked
ERR_IM 4 1 PRBS/QRSS logic error detect interrupt mask
= 0: PRBS/QRSS logic error detect interrupt enabled
= 1: PRBS/QRSS logic error detect interrupt masked
EXZ_IM 3 1 Receive excess zeros interrupt mask
= 0: Receive excess zeros interrupt enabled
= 1: Receive excess zeros interrupt masked
CV_IM 2 1 Receive error interrupt mask
= 0: Receive error interrupt enabled
= 1: Receive error interrupt masked
TIMER_IM 1 1 One-Second Timer expiration interrupt mask
= 0: One-Second Timer expiration interrupt enabled
= 1: One-Second Timer expiration interrupt masked
CNT_IM 0 1 Counter overflow interrupt mask
= 0: Counter overflow interrupt enabled
= 1: Counter overflow interrupt masked
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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Table-48 INTES: Interrupt Trigger Edge Select Register
(R/W, Address = 15H, 35H)
Symbol Bit Default Description
EQ_IES 7 0 This bit determines the Equalizer out of range interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the EQ_S bit in the STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the EQ_S bit in the STAT0
status register.
IBLBA_IES 6 0 This bit determines the Inband Loopback Activate Code interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBA_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBA_S bit in STAT0
status register
IBLBD_IES 5 0 This bit determines the Inband Loopback Deactivate Code interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBD_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBD_S bit in STAT0
status register
PRBS_IES 4 0 This bit determines the PRBS/QRSS synchronization status interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the PRBS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in STAT0
status register
TCLK_IES 3 0 This bit determines the TCLK Loss interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in STAT0
status register
DF_IES 2 0 This bit determines the Driver Failure interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the DF_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in STAT0 status
register
AIS_IES 1 0 This bit determines the AIS interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the AIS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in STAT0 status
register
LOS_IES 0 0 This bit determines the LOS interrupt event.
= 0: Interrupt is generated as a ‘0’ to ‘1’ transition of the LOS_S bit in STAT0 status register
= 1: Interrupt is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in STAT0 status
register
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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4.3.8 LINE STATUS REGISTERS
Table-49 STAT0: Line Status Register 0 (real time status monitor)
(R, Address = 16H, 36H)
Symbol Bit Default Description
EQ_S 7 0 Equalizer status indication
= 0: In range
= 1: Out of range
IBLBA_S 6 0 In-band Loopback activate code receive status indication
= 0: No Inband Loopback activate code is detected
= 1: Activate signal is detected and then received over a period of more than t ms, with a bit error rate less than 10-
2. The bit remains set as long as the bit error rate does not exceed 10-2.
Note1:
If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.
If automatic remote loopback switching is enabled (ARLP = 1), t= 5.1 s. The rising edge of this bit activates the
remote loopback operation in local end.
Note2:
If IBLBA_IM=0:
A ‘0’ to ‘1’ transition on this bit causes an activate code detected interrupt if IBLBA _IES bit is ‘0’;
Any changes of this bit causes an activate code detected interrupt if IBLBA _IES bit is set to ‘1’.
IBLBD_S 5 0 In-band Loopback deactivate code receive status indication
= 0: No Inband Loopback deactivate signal is detected
= 1: The Inband Loopback deactivate signal is detected and then received over a period of more than t, with a bit
error rate less than 10-2. The bit remains set as long as the bit error rate does not exceed 10-2.
Note1:
If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.
If automatic remote loopback switching is enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit disables the
remote loopback operation.
Note2:
If IBLBD_IM=0:
A ‘0’ to ‘1’ transition on this bit causes a deactivate code detected interrupt if IBLBD _IES bit is ‘0’;
Any changes of this bit causes a deactivate code detected interrupt if IBLBD _IES bit is set to ‘1’.
PRBS_S 4 0 Synchronous status indication of PRBS/QRSS (real time)
= 0: 215-1 (E1) PRBS or 220-1 (T1/J1) QRSS not detected
= 1: 215-1 (E1) PRBS or 220-1 (T1/J1) QRSS detected
Note:
If PRBS_IM=0:
A ‘0’ to ‘1’ transition on this bit causes a synchronous status detected interrupt if PRBS _IES bit is ‘0’.
Any changes of this bit causes an interrupt if PRBS_IES bit is set to ‘1’.
TCLK_LOS 3 0 TCLKn loss indication
= 0: Normal
= 1: TCLK pin has not toggled for more than 70 MCLK cycles
Note:
If TCLK_IM=0:
A ‘0’ to ‘1’ transition on this bit causes an interrupt if TCLK _IES bit is ‘0’.
Any changes of this bit causes an interrupt if TCLK_IES bit is set to ‘1’.
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DF_S 2 0 Line driver status indication
= 0: Normal operation
= 1: Line driver short circuit is detected.
Note:
If DF_IM=0
A ‘0’ to ‘1’ transition on this bit causes an interrupt if DF _IES bit is ‘0’.
Any changes of this bit causes an interrupt if DF_IES bit is set to ‘1’.
AIS_S 1 0 Alarm Indication Signal status detection
= 0: No AIS signal is detected in the receive path
= 1: AIS signal is detected in the receive path
Note:
If AIS_IM=0
A ‘0’ to ‘1’ transition on this bit causes an interrupt if AIS _IES bit is ‘0’.
Any changes of this bit causes an interrupt if AIS_IES bit is set to ‘1’.
LOS_S 0 0 Loss Of Signal status detection
= 0: Loss of signal on RTIPn/RRINGn is not detected
= 1: Loss of signal on RTIPn/RRINGn is detected.
Note:
If LOS_IM=0
A ‘0’ to ‘1’ transition on this bit causes an interrupt if LOS _IES bit is ‘0’.
Any changes of this bit causes an interrupt if LOS_IES bit is set to ‘1’.
Table-50 STAT1: Line Status Register 1 (real time status monitor)
(R, Address = 17H, 37H)
Symbol Bit Default Description
- 7-6 00 Reserved.
RLP_S 5 0 Indicating the status of Remote Loopback
= 0: The remote loopback is inactive.
= 1: The remote loopback is active (closed).
Table-49 STAT0: Line Status Register 0 (real time status monitor) (Continued)
(R, Address = 16H, 36H)
Symbol Bit Default Description
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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LATT[4:0] 4-0 00000 Line Attenuation Indication
00000 0 to 2 dB
00001 2 to 4 dB
00010 4 to 6 dB
00011 6 to 8 dB
00100 8 to 10 dB
00101 10 to 12 dB
00110 12 to 14 dB
00111 14 to 16 dB
01000 16 to 18 dB
01001 18 to 20 dB
01010 20 to 22 dB
01011 22 to 24 dB
01100 24 to 26 dB
01101 26 to 28 dB
01110 28 to 30 dB
01111 30 to 32 dB
10000 32 to 34 dB
10001 34 to 36 dB
10010 36 to 38 dB
10011 38 to 40 dB
10100 40 to 42 dB
10101 42 to 44 dB
10110 -11111 >44 dB
Table-50 STAT1: Line Status Register 1 (real time status monitor) (Continued)
(R, Address = 17H, 37H)
Symbol Bit Default Description
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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4.3.9 INTERRUPT STATUS REGISTERS
Table-51 INTS0: Interrupt Status Register 0
(R, Address = 18H, 38H) (this register is reset and relevant interrupt request is cleared after a read)
Symbol Bit Default Description
EQ_IS 7 0 This bit indicates the occurrence of Equalizer out of range interrupt event.
= 0: No interrupt event from the Equalizer out of range occurred
= 1: Interrupt event from the Equalizer out of range occurred
IBLBA_IS 6 0 This bit indicates the occurrence of the Inband Loopback Activate Code interrupt event.
= 0: No Inband Loopback Activate Code interrupt event occurred
= 1: Inband Loopback Activate Code interrupt event occurred
IBLBD_IS 5 0 This bit indicates the occurrence of the Inband Loopback Deactivate Code interrupt event.
= 0: No Inband Loopback Deactivate Code interrupt event occurred
= 1: Interrupt event of the received Inband Loopback Deactivate Code occurred.
PRBS_IS 4 0 This bit indicates the occurrence of the interrupt event generated by the PRBS/QRSS synchronization status.
= 0: No PRBS/QRSS synchronization status interrupt event occurred
= 1: PRBS/QRSS synchronization status interrupt event occurred
TCLK_LOS_IS 3 0 This bit indicates the occurrence of the interrupt event generated by the TCLK loss detection.
= 0: No TCLK loss interrupt event.
= 1:TCLK loss interrupt event occurred.
DF_IS 2 0 This bit indicates the occurrence of the interrupt event generated by the Driver Failure.
= 0: No Driver Failure interrupt event occurred
= 1: Driver Failure interrupt event occurred
AIS_IS 1 0 This bit indicates the occurrence of the AIS (Alarm Indication Signal) interrupt event.
= 0: No AIS interrupt event occurred
= 1: AIS interrupt event occurred
LOS_IS 0 0 This bit indicates the occurrence of the LOS (Loss of signal) interrupt event.
= 0: No LOS interrupt event occurred
= 1: LOS interrupt event occurred
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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4.3.10 COUNTER REGISTERS
Table-52 INTS1: Interrupt Status Register 1
(R, Address = 19H, 39H) (this register is reset and the relevant interrupt request is cleared after a read)
Symbol Bit Default Description
DAC_OV_IS 7 0 This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event.
= 0: No pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: The pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
JAOV_IS 6 0 This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
= 0: No JA Overflow interrupt event occurred
= 1: JA Overflow interrupt event occurred
JAUD_IS 5 0 This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: No JA Underflow interrupt event occurred
= 1: JA Underflow interrupt event occurred
ERR_IS 4 0 This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error.
= 0: No PRBS/QRSS logic error interrupt event occurred
= 1: PRBS/QRSS logic error interrupt event occurred
EXZ_IS 3 0 This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: No Excessive Zeros interrupt event occurred
= 1: EXZ interrupt event occurred
CV_IS 2 0 This bit indicates the occurrence of the Code Violation interrupt event.
= 0: No Code Violation interrupt event occurred
= 1: Code Violation interrupt event occurred
TMOV_IS 1 0 This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.
= 0: No One-Second Timer Expiration interrupt event occurred
= 1: One-Second Timer Expiration interrupt event occurred
CNT_OV_IS 0 0 This bit indicates the occurrence of the Counter Overflow interrupt event.
= 0: No Counter Overflow interrupt event occurred
= 1: Counter Overflow interrupt event occurred
Table-53 CNT0: Error Counter L-byte Register 0
(R, Address = 1AH, 3AH)
Symbol Bit Default Description
CNT_L[7:0] 7-0 00H This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
Table-54 CNT1: Error Counter H-byte Register 1
(R, Address = 1BH, 3BH)
Symbol Bit Default Description
CNT_H[7:0] 7-0 00H This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
HARDWARE CONTROL PIN SUMMARY 64 May 4, 2009
5 HARDWARE CONTROL PIN SUMMARY
Table-55 Hardware Control Pin Summary
Pin No.
TQFP
Pin No.
FPBGA
Symbol Description
9
10
E2
D3
MODE1
MODE0
MODE[1:0]: Operation mode of Control interface select (global control)
00= Hardware interface
01= Serial interface
10= Parallel - non-Multiplexed - Motorola Interface
11= Parallel - non-Multiplexed - Intel Interface
13
12
E3
E1
TERM1
TERM2
TERMn: Termination interface select (per channel control)
These pins select internal or external impedance matching for channel n (n=1 or 2)
0 = ternary interface with internal impedance matching network.
1 = ternary interface with external impedance matching network in E1 mode; ternary interface with external impedance matching
network for receiver and ternary interface with internal impedance matching network for transmitter in T1/J1 mode. (External imped-
ance matching is not supported by T1/J1 mode transmitter.)
(This applies to ZB die revision only).
14
15
E4
F1
RXTXM1
RXTXM0
RXTXM[1:0]: Receive and transmit path operation mode select (global control)
00= single rail with HDB3/B8ZS coding
01= single rail with AMI coding
10= dual rail interface with CDR enable
11= slicer mode
54
53
52
51
50
49
48
47
D8
F5
E7
D9
E8
E9
F6
F7
PULS13
PULS12
PULS11
PULS10
PULS23
PULS22
PULS21
PULS20
PULSn[3:0]: These pins are used to select the following functions (per channel control):
• T1/E1/J1 mode (T1/E1/J1 selection of common clock is decided by PULS1n/PULS2n, n=0~3)
• Transmit pulse template
• Internal termination impedance (75Ω/100Ω/110Ω/120Ω)
PULSn[3:0] T1/E1/J1 TCLK Cable impedance (internal
matching impedance)
Cable range or
LBO
Cable loss
0000 E1 2.048 MHz 75Ω- 0-43 dB
0001 E1 2.048 MHz 120Ω- 0-43 dB
0010 DSX1 1.544 MHz 100Ω0-133 ft 0-0.6 dB
0011 DSX1 1.544 MHz 100Ω133-266 ft 0.6-1.2 dB
0100 DSX1 1.544 MHz 100Ω266-399 ft 1.2-1.8 dB
0101 DSX1 1.544 MHz 100Ω399-533 ft 1.8-2.4 dB
0110 DSX1 1.544 MHz 100Ω533-655 ft 2.4-3.0 dB
0111 J1 1.544 MHz 110Ω0-655 ft 0-3.0 dB
1000 DS1 1.544 MHz 100Ω 0 dB LBO 0-36 dB
1001 DS1 1.544 MHz 100Ω-7.5 dB LBO 0-28.5 dB
1010 DS1 1.544 MHz 100Ω-15.0 dB LBO 0-21 dB
1011 DS1 1.544 MHz 100Ω-22.5 dB LBO 0-13.5 dB
1100 -1111 DS1 1.544 MHz 100Ω- 0-13.5 dB
58
60
C8
A9
EQ1
EQ2
EQn: Receive Equalizer on/off control (per channel control)
When the chip is configured by hardware with ternary interface, these pins select Short Haul or Long Haul operation mode for chan-
nel n (n=1 or 2)
0= short haul (10dB)
1= long haul (36dB for T1/J1, 43 dB for E1)
57
59
D7
B9
RPD1
RPD2
RPDn: Receiver power down control (per channel control)
0= Normal operation
1= receiver power down
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
HARDWARE CONTROL PIN SUMMARY 65 May 4, 2009
46
45
56
55
G7
F8
E6
C9
PATT11
PATT10
PATT21
PATT20
PATTn[1:0]: Transmit test pattern select (per channel control)
In hardware control mode, these pins select the transmit pattern for channel n (n=1 or 2)
00 = normal
01= All Ones
10= PRBS
11= transmitter power down
16
17
F2
F3
JA1
JA0
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select (global control)
00= JA is disabled
01= JA in receiver, broad bandwidth, FIFO=64 bits
10= JA in receiver, narrow bandwidth, FIFO=128 bits
11= JA in transmitter, narrow bandwidth, FIFO=128 bits
19
18
G1
G2
MONT1
MONT2
MONTn: Receive Monitor n gain select (per channel control)
In hardware control mode with ternary interface, this pin selects the receive monitor gain for receiver n (n=1 or 2)
0= 0 dB
1= 26 dB
42
41
44
43
G8
G9
H8
F9
LP11
LP10
LP21
LP20
LPn[1:0]: Loopback mode select (per channel control)
When the chip is configured by hardware, these pins are used to select loopback operation modes for channel n (Inband loopback
is not provided in hardware control mode).
00= no loopback
01= analog loopback
10= digital loopback
11= remote loopback
20 H1 THZ THZ: Transmitter Driver High Impedance Enable (global control)
This signal enables or disables both of the transmitter drivers. A low level on this pin enables both of the two drivers while a high
level on this pin places both of the two drivers in high impedance state.
11 D4 RCLKE RCLKE: the active edge of RCLKn select when hardware control mode is used (global control)
0= select the rising edge as active edge of RCLKn
1= select the falling edge as active edge of RCLKn
Table-55 Hardware Control Pin Summary (Continued)
Pin No.
TQFP
Pin No.
FPBGA
Symbol Description
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST ACCESS PORT 66 May 4, 2009
6 IEEE STD 1149.1 JTAG TEST ACCESS PORT
The IDT82V2082 supports the digital Boundary Scan Specification as
described in the IEEE 1149.1 standards.
The boundary scan architecture consists of data and instruction regis-
ters plus a Test Access Port (TAP) controller. Control of the TAP is per-
formed through signals applied to the Test Mode Select (TMS) and Test
Clock (TCK) pins. Data is shifted into the registers via the Test Data Input
(TDI) pin, and shifted out of the registers via the Test Data Output (TDO)
pin. Both TDI and TDO are clocked at a rate determined by TCK.
The JTAG boundary scan registers include BSR (Boundary Scan Reg-
ister), IDR (Device Identification Register), BR (Bypass Register) and IR
(Instruction Register). These will be described in the following pages. Refer
to Figure-22 for architecture.
Figure-22 JTAG Architecture
BSR (Boundary Scan Register)
IDR (Device Identification Register)
BR (Bypass Register)
IR (Instruction Register)
MUX
TDO
TDI
TCK
TMS
TRST
Control<6:0>
MUX
Select
high impedance enable
TAP
(Test Access Port)
Controller
parallel latched output
Digital output pins Digital input pins
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST ACCESS PORT 67 May 4, 2009
6.1 JTAG INSTRUCTIONS AND INSTRUCTION REG-
ISTER
The IR (Instruction Register) with instruction decode block is used to
select the test to be executed or the data register to be accessed or both.
The instructions are shifted in LSB first to this 3-bit register. See Table-
56 for details of the codes and the instructions related.
6.2 JTAG DATA REGISTER
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR)
The IDR can be set to define the producer number, part number and the
device revision, which can be used to verify the proper version or revision
number that has been used in the system under test. The IDR is 32 bits long
and is partitioned as in Table-57. Data from the IDR is shifted out to TDO
LSB first.
6.2.2 BYPASS REGISTER (BR)
The BR consists of a single bit. It can provide a serial path between the
TDI input and TDO output, bypassing the BSR to reduce test access times.
6.2.3 BOUNDARY SCAN REGISTER (BSR)
The BSR can apply and read test patterns in parallel to or from all the
digital I/O pins. The BSR is a 98 bits long shift register and is initialized and
read using the instruction EXTEST or SAMPLE/PRELOAD. Each pin is
related to one or more bits in the BSR. For details, please refer to the BSDL
file.
6.2.4 TEST ACCESS PORT CONTROLLER
The TAP controller is a 16-state synchronous state machine. Figure-23
shows its state diagram following the description of each state. Note that
the figure contains two main branches to access either the data or instruc-
tion registers. The value shown next to each state transition in this figure
states the value present at TMS at each rising edge of TCK. Please refer
to Table-58 for details of the state description.
Table-56 Instruction Register Description
IR CODE INSTRUCTION COMMENTS
000 Extest The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST
instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by load-
ing the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary
scan register using the Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through
input TDI into the boundary scan register using the Update-DR state.
100 Sample / Preload The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed
between TDI and TDO. The normal path between IDT82V2082 logic and the I/O pins is maintained. Primary device inputs
and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then
be viewed by shifting the boundary scan register using the Shift-DR state.
110 Idcode The identification instruction is used to connect the identification register between TDI and TDO. The device's identification
code can then be shifted out using the Shift-DR state.
111 Bypass The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to
bypass the device.
Table-57 Device Identification Register Description
Bit No. Comments
0 Set to ‘1’
1-11 Producer Number
12-27 Part Number
28-31 Device Revision
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST ACCESS PORT 68 May 4, 2009
Table-58 TAP Controller State Description
STATE DESCRIPTION
Test Logic Reset In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register
with the IDCODE instruction. Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS
input is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device processor automatically
enters this state at power-up.
Run-Test/Idle This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The
instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller
moves to the Select-DR state.
Select-DR-Scan This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction
retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR
state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller
moves to the Select-IR-Scan state.
Capture-DR In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction
does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in
this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
Shift-DR In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward
its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising
edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
Exit1-DR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Pause-DR The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI
and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test
sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this
state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves
to the Exit2-DR state.
Exit2-DR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-DR The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST
and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched
into the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output
changes only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and
the instruction does not change during this state.
Select-IR-Scan This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and
a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction reg-
ister is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction
does not change during this state.
Capture-IR In this controller state, the shift register contained in the instruction register loads a fixed value of '100' on the rising edge of TCK. This supports
fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction
does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR
state if TMS is held high, or the Shift-IR state if TMS is held low.
Shift-IR In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its
serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction
does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR
state if TMS is held high, or remains in the Shift-IR state if TMS is held low.
Exit1-IR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Pause-IR The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected
by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state
as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST ACCESS PORT 69 May 4, 2009
Figure-23 JTAG State Diagram
Exit2-IR This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-IR The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK.
When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain
their previous value.
Table-58 TAP Controller State Description (Continued)
STATE DESCRIPTION
Test-logic Reset
Run Test/Idle Select-DR Select-IR
Capture-DR Capture-IR
Shift-DR Shift-IR
Exit1-DR Exit1-IR
Pause-DR Pause-IR
Exit2-DR Exit2-IR
Update-DR Update-IR
1
0
0
111
00
00
0
0
11
1
0
1
0
1
1
1010
1
0
1
1
0
0
0
1
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 70 May 4, 2009
7 TEST SPECIFICATIONS
1.Reference to ground
2.Human body model
3.Charge device model
4.Constant input current
Table-59 Absolute Maximum Rating
Symbol Parameter Min Max Unit
VDDA, VDDD Core Power Supply -0.5 4.6 V
VDDIO I/O Power Supply -0.5 4.6 V
VDDT1-2 Transmit Power Supply -0.5 4.6 V
VDDR1-2 Receive Power Supply -0.5 4.6 V
Vin
Input Voltage, Any Digital Pin GND-0.5 5.5 V
Input Voltage, Any RTIPn and RRINGn pin1GND-0.5 VDDR+0.5 V
ESD Voltage, any pin 2000 2V
500 3V
Iin
Transient latch-up current, any pin 100 mA
Input current, any digital pin 4-10 10 mA
DC Input current, any analog pin 4±100 mA
Pd Maximum power dissipation in package 1.23 W
Tc Case Temperature 120 °C
Ts Storage Temperature -65 +150 °C
CAUTION:
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 71 May 4, 2009
1.Power consumption includes power consumption on device and load. Digital levels are 10% of the supply rails and digital outputs driving a 50 pF capacitive load.
2.Maximum power consumption over the full operating temperature and power supply voltage range.
3.In short haul mode, if internal impedance matching is chosen, E1 75Ω power dissipation values are measured with template PULS[3:0] = 0000; E1 120Ω power dissipation values are measured
with template PULS[3:0] = 0001; T1 power dissipation values are measured with template PULS[3:0] = 0110; J1 power dissipation values are measured with template PULS[3:0] = 0111.
1.Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels.
2.Power consumption includes power absorbed by line load and external transmitter components.
3.T1 is measured with maximum cable length.
Table-60 Recommended Operation Conditions
Symbol Parameter Min Typ Max Unit
VDDA,VDDD Core Power Supply 3.13 3.3 3.47 V
VDDIO I/O Power Supply 3.13 3.3 3.47 V
VDDT Transmitter Power Supply 3.13 3.3 3.47 V
VDDR Receive Power Supply 3.13 3.3 3.47 V
TA Ambient operating temperature -40 25 85 °C
Total current dissipation1,2,3
E1, 75 Ω load
50% ones density data
100% ones density data
-
-
100
130
110
140
mA
E1, 120 Ω Load
50% ones density data
100% ones density data
-
-
110
130
120
140
mA
T1, 100 Ω Load
50% ones density data
100% ones density data
-
-
120
170
130
180
mA
J1, 110 Ω Load
50% ones density data
100% ones density data
-
-
100
130
110
140
mA
Table-61 Power Consumption
Symbol Parameter Min Typ Max1,2 Unit
E1, 3.3 V, 75 Ω Load
50% ones density data:
100% ones density data:
-
-
330
430
-
490
mW
E1, 3.3 V, 120 Ω Load
50% ones density data:
100% ones density data:
-
-
370
430
-
490
mW
T1, 3.3 V, 100 Ω Load3
50% ones density data:
100% ones density data:
-
-
400
560
-
630
mW
J1, 3.3 V, 110 Ω Load
50% ones density data:
100% ones density data:
-
-
330
430
-
490
mW
Table-62 DC Characteristics
Symbol Parameter Min Typ Max Unit
VIL Input Low Level Voltage - - 0.8 V
VIH Input High Voltage 2.0 - - V
VOL Output Low level Voltage (Iout=1.6mA) - - 0.4 V
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 72 May 4, 2009
VOH Output High level Voltage (Iout=400µA) 2.4 - VDDIO V
VMA Analog Input Quiescent Voltage (RTIPn, RRINGn
pin while floating)
1.5 V
IIInput Leakage Current
TMS, TDI, TRST
All other digital input pins -10
50
10
µA
µA
IZL High Impedance Leakage Current -10 10 µA
Ci Input capacitance 15 pF
Co Output load capacitance 50 pF
Co Output load capacitance (bus pins) 100 pF
Table-63 E1 Receiver Electrical Characteristics
Symbol Parameter Min Typ Max Unit Test conditions
Receiver sensitivity
Short haul with cable loss@1024kHz:
Long haul with cable loss@1024kHz:
-10
-43
dB
Analog LOS level
Short haul
Long haul -4
800
-48
mVp-p
dB
A LOS level is programmable for Long Haul
Allowable consecutive zeros before LOS
G.775:
I.431/ETSI300233:
32
2048
LOS reset 12.5 % ones G.775, ETSI 300 233
Receive Intrinsic Jitter
20Hz - 100kHz 0.05 U.I.
JA enabled
Input Jitter Tolerance
1 Hz – 20 Hz
20 Hz – 2.4 KHz
18 KHz – 100 KHz
37
5
2
U.I.
U.I.
U.I.
G.823, with 6 dB cable attenuation
ZDM Receiver Differential Input Impedance 20 KΩInternal mode
Input termination resistor tolerance ±1%
RRX
Receive Return Loss
51 KHz – 102 KHz
102 KHz - 2.048 MHz
2.048 MHz – 3.072 MHz
20
20
20
dB
dB
dB
G.703 Internal termination
RPD
Receive path delay
Single rail
Dual rail
7
2
U.I.
U.I.
JA disabled
Table-62 DC Characteristics (Continued)
Symbol Parameter Min Typ Max Unit
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 73 May 4, 2009
Table-64 T1/J1 Receiver Electrical Characteristics
Symbol Parameter Min Typ Max Unit Test conditions
receiver sensitivity
Short haul with cable loss@772kHz:
Long haul with cable loss@772kHz:
-10
-36
dB
Analog LOS level
Short haul
Long haul -4
800
-48
mVp-p
dB
A LOS level is programmable for Long Haul
Allowable consecutive zeros before LOS
T1.231-1993
I.431
175
1544
LOS reset 12.5 % ones G.775, ETSI 300 233
Receive Intrinsic Jitter
10 Hz - 8 kHz
10 Hz - 40 kHz
8 kHz - 40 kHz
Wide band
0.02
0.025
0.025
0.050
U.I.
U.I.
U.I.
U.I.
JA enabled ( in receive path)
Input Jitter Tolerance
0.1 Hz – 1 Hz
4.9 Hz – 300 Hz
10 KHz – 100 KHz
138.0
28.0
0.4
U.I.
U.I.
U.I.
AT&T62411
ZDM Receiver Differential Input Impedance 20 KΩInternal mode
Input termination resistor tolerance ±1%
RRX Receive Return Loss
39 KHz – 77 KHz
77 KHz - 1.544 MHz
1.544 MHz – 2.316 MHz
20
20
20
dB
dB
dB
G.703
Internal termination
RPD Receive path delay
Single rail
Dual rail
7
2
U.I.
U.I.
JA disabled
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 74 May 4, 2009
Table-65 E1 Transmitter Electrical Characteristics
Symbol Parameter Min Typ Max Unit
Vo-p Output pulse amplitudes
E1, 75Ω load
E1, 120Ω load
2.14
2.7
2.37
3.0
2.60
3.3
V
V
Vo-s Zero (space) level
E1, 75Ω load
E1, 120Ω load
-0.237
-0.3
0.237
0.3
V
V
Transmit amplitude variation with supply -1 +1 %
Difference between pulse sequences for 17 consecutive pulses (T1.102) 200 mV
Tpw Output Pulse Width at 50% of nominal amplitude 232 244 256 ns
Ratio of the amplitudes of Positive and Negative Pulses at the center of the pulse interval
(G.703)
0.95 1.05
Ratio of the width of Positive and Negative Pulses at the center of the pulse interval (G.703) 0.95 1.05
RTX Transmit Return Loss (G.703)
51 KHz – 102 KHz
102 KHz - 2.048 MHz
2.048 MHz – 3.072 MHz
20
15
12
dB
dB
dB
JTXp-p Intrinsic Transmit Jitter (TCLK is jitter free)
20 Hz – 100 KHz 0.050 U.I.
Td Transmit path delay (JA is disabled)
Single rail
Dual rail
8.5
4.5
U.I.
U.I.
Isc Line short circuit current; tested on the TTIP/TRING pins 100 mAp
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 75 May 4, 2009
Table-66 T1/J1 Transmitter Electrical Characteristics
Symbol Parameter Min Typ Max Unit
Vo-p Output pulse amplitudes 2.4 3.0 3.6 V
Vo-s Zero (space) level -0.15 0.15 V
Transmit amplitude variation with supply -1 +1 %
Difference between pulse sequences for 17 consecutive pulses
(T1.102)
200 mV
TPW Output Pulse Width at 50% of nominal amplitude 338 350 362 ns
Pulse width variation at the half amplitude (T1.102) 20 ns
Imbalance between Positive and Negative Pulses amplitude
(T1.102)
0.95 1.05
Output power level (T1.102)
@772kHz
@1544kHz (referenced to power at 772kHz)
12.6
-29
17.9 dBm
dBm
RTX Transmit Return Loss
39 KHz – 77 KHz
77 KHz – 1.544 MHz
1.544 MHz – 2.316 MHz
20
15
12
dB
dB
dB
JTXP-P Intrinsic Transmit Jitter (TCLK is jitter free)
10 Hz – 8 KHz
8 KHz – 40 KHz
10 Hz – 40 KHz
wide band
0.020
0.025
0.025
0.050
U.I.p-p
U.I.p-p
U.I.p-p
U.I.p-p
Td Transmit path delay (JA is disabled)
Single rail
Dual rail
8.5
4.5
U.I.
U.I.
ISC Line short circuit current; tested on the TTIP/TRING pins 100 mAp
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 76 May 4, 2009
1.Relative to nominal frequency, MCLK= ± 100 ppm
2.RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement
for E1 per ITU G.823).
3.For all digital outputs. C load = 15pF
Table-67 Transmitter and Receiver Timing Characteristics
Symbol Parameter Min Typ Max Unit
MCLK frequency
E1:
T1/J1:
2.048
1.544
MHz
MCLK tolerance -100 100 ppm
MCLK duty cycle 30 70 %
Transmit path
TCLK frequency
E1:
T1/J1:
2.048
1.544
MHz
TCLK tolerance -50 +50 ppm
TCLK Duty Cycle 10 90 %
t1 Transmit Data Setup Time 40 ns
t2 Transmit Data Hold Time 40 ns
Delay time of THZ low to driver high impedance 10 us
Delay time of TCLK low to driver high impedance 75 U.I.
Receive path
Clock recovery capture
range 1
E1 ± 80 ppm
T1/J1 ± 180
RCLK duty cycle 240 50 60 %
t4 RCLK pulse width 2
E1:
T1/J1:
457
607
488
648
519
689
ns
t5 RCLK pulse width low time
E1:
T1/J1:
203
259
244
324
285
389
ns
t6 RCLK pulse width high time
E1:
T1/J1:
203
259
244
324
285
389
ns
Rise/fall time 320 ns
t7 Receive Data Setup Time
E1:
T1/J1:
200
200
244
324
ns
t8 Receive Data Hold Time
E1:
T1/J1:
200
200
244
324
ns
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 77 May 4, 2009
Figure-24 Transmit System Interface Timing
Figure-25 Receive System Interface Timing
Table-68 Jitter Tolerance
Jitter Tolerance Min Typ Max Unit Standard
E1: 1 Hz
20 Hz – 2.4 KHz
18 KHz – 100 KHz
37
1.5
0.2
U.I.
U.I.
U.I.
G.823
Cable attenuation is 6dB
T1/J1: 1 Hz
4.9 Hz – 300 Hz
10 KHz – 100 KHz
138.0
28.0
0.4
U.I.
U.I.
U.I.
AT&T 62411
TDNn
TDn/TDPn
TCLKn
t1 t2
RDNn/CVn
RDPn/RDn
RCLKn
t4
t7
t6
t7
t5
t8
t8
(RCLK_SEL = 0 software mode)
(RCLKE = 0 hardware mode)
RDPn/RDn
RDNn/CVn
(RCLK_SEL = 1 software mode)
(RCLKE = 1 hardware mode)
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 78 May 4, 2009
Figure-26 E1 Jitter Tolerance Performance
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 79 May 4, 2009
Figure-27 T1/J1 Jitter Tolerance Performance
Table-69 Jitter Attenuator Characteristics
Parameter Min Typ Max Unit
Jitter Transfer Function Corner (-3dB) Frequency
E1, 32/64/128 bits FIFO
JABW = 0:
JABW = 1:
T1/J1, 32/64/128 bits FIFO
JABW = 0:
JABW = 1:
6.8
0.9
5
1.25
Hz
Hz
Hz
Hz
Jitter Attenuator
E1: (G.736)
@ 3 Hz
@ 40 Hz
@ 400 Hz
@ 100 kHz
T1/J1: (Per AT&T pub.62411)
@ 1 Hz
@ 20 Hz
@ 1 kHz
@ 1.4 kHz
@ 70 kHz
-0.5
-0.5
+19.5
+19.5
dB
0
0
+33.3
40
40
Jitter Attenuator Latency Delay
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 80 May 4, 2009
Figure-28 E1 Jitter Transfer Performance
32 bits FIFO:
64 bits FIFO:
128 bits FIFO:
16
32
64
U.I.
U.I.
U.I.
Input jitter tolerance before FIFO overflow or underflow
32 bits FIFO:
64 bits FIFO:
128 bits FIFO:
28
58
120
U.I.
U.I.
U.I.
Table-69 Jitter Attenuator Characteristics (Continued)
Parameter Min Typ Max Unit
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 81 May 4, 2009
Figure-29 T1/J1 Jitter Transfer Performance
Table-70 JTAG Timing Characteristics
Symbol Parameter Min Typ Max Unit
t1 TCK Period 100 ns
t2 TMS to TCK setup Time
TDI to TCK Setup Time
25 ns
t3 TCK to TMS Hold Time
TCK to TDI Hold Time
25 ns
t4 TCK to TDO Delay Time 50 ns
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS 82 May 4, 2009
Figure-30 JTAG Interface Timing
TCK
t1
t2 t3
TDO
TMS
TDI
t4
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS83 May 4, 2009
8 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS
8.1 SERIAL INTERFACE TIMING
Figure-31 Serial Interface Write Timing
Figure-32 Serial Interface Read Timing with SCLKE=1
Figure-33 Serial Interface Read Timing with SCLKE=0
Table-71 Serial Interface Timing Characteristics
Symbol Parameter Min Typ Max Unit Comments
t1 SCLK High Time 100 ns
t2 SCLK Low Time 100 ns
t3 Active CS to SCLK Setup Time 5 ns
t4 Last SCLK Hold Time to Inactive CS Time 41 ns
t5 CS Idle Time 41 ns
t6 SDI to SCLK Setup Time 0 ns
t7 SCLK to SDI Hold Time 82 ns
t10 SCLK to SDO Valid Delay Time 95 ns
t11 Inactive CS to SDO High Impedance Hold Time 90 ns
MSB
LSBLSB
CS
SCLK
SDI
t1 t2t3 t4 t5
t6 t7 t7
12345678910111213141516
SDO
CS
SCLK
t11
t4
76543210
t10
12345678910111213141516
SDO
CS
SCLK
t4
t11
76543210
t10
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS84 May 4, 2009
8.2 PARALLEL INTERFACE TIMING
Figure-34 Non-Multiplexed Motorola Read Timing
Table-72 Non-Multiplexed Motorola Read Timing Characteristics
Symbol Parameter Min Max Unit
tRC Read Cycle Time 190 ns
tDW Valid DS Width 180 ns
tRWV Delay from DS to Valid Read Signal 15 ns
tRWH R/W to DS Hold Time 65 ns
tAV Delay from DS to Valid Address 15 ns
tADH Address to DS Hold Time 65 ns
tPRD DS to Valid Read Data Propagation Delay 175 ns
tDAZ Delay from DS inactive to data bus High Impedance 5 20 ns
tRecovery Recovery Time from Read Cycle 5 ns
A[x:0] Valid Address
DS+CS
R/W
READ D[7:0]
tRWV
Valid Data
tDAZ
tADH
tRWH
tPRD
tRC
tDW
tAV
tRecovery
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS85 May 4, 2009
Figure-35 Non-Multiplexed Motorola Write Timing
Table-73 Non-Multiplexed Motorola Write Timing Characteristics
Symbol Parameter Min Max Unit
tWC Write Cycle Time 120 ns
tDW Valid DS Width 100 ns
tRWV Delay from DS to Valid Write Signal 15 ns
tRWH R/W to DS Hold Time 65 ns
tAV Delay from DS to Valid Address 15 ns
tAH Address to DS Hold Time 65 ns
tDV Delay from DS to Valid Write Data 15 ns
tDHW Write Data to DS Hold Time 65 ns
tRecovery Recovery Time from Write Cycle 5 ns
A[x:0] Valid Address
DS+CS
R/W
Write D[7:0]
tRWV
tDHW
tAH
tRWH
tWC
tDW
tAV
Valid Data
tDV
tRecovery
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS86 May 4, 2009
Figure-36 Non-Multiplexed Intel Read Timing
Table-74 Non-Multiplexed Intel Read Timing Characteristics
Symbol Parameter Min Max Unit
tRC Read Cycle Time 190 ns
tRDW Valid RD Width 180 ns
tAV Delay from RD to Valid Address 15 ns
tAH Address to RD Hold Time 65 ns
tPRD RD to Valid Read Data Propagation Delay 175 ns
tDAZ Delay from RD inactive to data bus High Impedance 5 20 ns
tRecovery Recovery Time from Read Cycle 5 ns
A[x:0] Valid Address
CS+RD
READ D[7:0] Valid Data
tDAZ
tAH
tPRD
tRDW
tAV
Note: WR should be tied to high
tRecovery
tRC
IDT82V2082 DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS87 May 4, 2009
Figure-37 Non-Multiplexed Intel Write Timing
Table-75 Non-Multiplexed Intel Write Timing Characteristics
Symbol Parameter Min Max Unit
tWC Write Cycle Time 120 ns
tWRW Valid WR Width 100 ns
tAV Delay from WR to Valid Address 15 ns
tAH Address to WR Hold Time 65 ns
tDV Delay from WR to Valid Write Data 15 ns
tDHW Write Data to WR Hold Time 65 ns
tRecovery Recovery Time from Write Cycle 5 ns
A[x:0] Valid Address
Write D[7:0]
tDHW
tAH
tWC
tWRW
tAV
Valid Data
tDV
Note: RD should be tied to high
tRecovery
WR+ CS
88
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88 May 4, 2009
IDT82V2082 DUAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
ORDERING INFORMATION
DATASHEET DOCUMENT HISTORY
08/26/2003 pgs. 19, 20, 21,22, 33, 37, 45, 63, 64
04/09/2004 pgs. 14, 22, 24, 56
07/19/2004 pgs. 34, 66, 67
12/12/2005 pgs. 1, 16, 24, 25, 34, 43, 44, 52, 73, 74, 87
11/24/2009 pgs 10, 11,12, 13, 14, 15, 16, 17, 18, 64, 65, 88
XXXXXXX XX X
Device Type
Blank
Process/
Temperature
Range
PF
82V2082
Industrial (-40 °C to +85 °C)
Thin Quad Flatpack
(TQFP, PN80)
Long Haul/Short Haul LIU
Green Thin Quad Flatpack
(TQFP, PNG80)
PFG
BF Fine Pitch Ball Grid Array
(FPBGA, BF81)
Green Fine Pitch Ball Grid Array
(FPBGA, BFG81)
BFG
