TM Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Datasheet The Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (IXF1110 MAC) is a 10-port Ethernet Media Access Controller (MAC) that supports IEEE 802.3 1000 Mbps applications. The device supports a System Packet Interface Level 4 Phase 2 (SPI4-2) system interface to the network processor or ASIC. The IXF1110 MAC implements an internal Serializer/Deserializer (SerDes) to allow direct connection to optical modules. The integration of the SerDes functionality reduces PCB real-estate and system-cost requirements. Applications In general, the IXF1110 MAC is appropriate for high-end switching applications where MAC and SerDes functions are not integrated into the system ASIC. High-End Optical Ethernet Switches Multi-Service Optical Ethernet Switches High-End Ethernet LAN/WAN Routers Supports IEEE 802.3 fiber auto-negotiation, including forced mode SFP MSA compatible Internal 17.0 KB receive FIFO and 4.5 KB transmit FIFO per port Independent enable/disable of any port Detection of overly large packets Counters for dropped and errored packets CRC calculation and error detection Programmable options: Product Features SerDes interface with optical module connections/MDIO for Ethernet physical connectivity Integrated termination I2C Read/Write capability System Packet Interface Level 4 Phase 2 (SPI4-2) Capable of data transfers from 10.24 Gbps up to 12.8 Gbps Supports dynamic phase alignment Integrated termination Ten independent 1000 Mbps full-duplex Ethernet MAC ports 32-bit CPU interface Operating Temperature Range: -- Min: 0 C Max: +70 C RMON statistics JTAG boundary scan Compliant with IEEE 802.3x Standard for flow control Jumbo frame support for 9.6 KB packets .18 CMOS process technology -- Filter packets with errors -- Filter, broadcast, multicast, and unicast address packets -- Automatically pad transmitted packets less than the minimum frame size 552-Ceramic BGA (RoHS-compliant package available) Power consumption: 490 mW per-port typical 1.8 V and 2.5 V operation 250210, Revision 11.0 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Legal Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN CORTINA'S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. CORTINA SYSTEMS(R), CORTINATM, and the Cortina Earth Logo are trademarks or registered trademarks of Cortina Systems, Inc. or its subsidiaries in the US and other countries. Any other product and company names are the trademarks of their respective owners. Copyright (c) 2001-2009 Cortina Systems, Inc. All rights reserved. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 2 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Contents Contents 1.0 Introduction.................................................................................................................................. 14 1.1 1.2 What You Will Find in This Document ................................................................................ 14 Related Documents ............................................................................................................ 14 2.0 General Description .................................................................................................................... 15 3.0 Ball Assignments and Ball List Tables...................................................................................... 17 4.0 Ball Assignments and Signal Descriptions .............................................................................. 18 4.1 4.2 4.3 5.0 Naming Conventions .......................................................................................................... 18 4.1.1 Signal Name Conventions ..................................................................................... 18 4.1.2 Register Address Conventions .............................................................................. 18 Interface Signal Groups ...................................................................................................... 18 Ball List Tables ................................................................................................................... 30 4.3.1 Balls Listed in Alphanumeric Order by Signal Name ............................................. 30 4.3.2 Balls Listed in Alphanumeric Order by Ball Location ............................................. 35 Functional Description................................................................................................................ 41 5.1 5.2 Media Access Controller..................................................................................................... 41 5.1.1 General Description ............................................................................................... 41 5.1.2 MAC Functions ...................................................................................................... 41 5.1.2.1 Padding of Undersized Frames on Transmit ......................................... 41 5.1.2.2 Automatic CRC Generation ................................................................... 42 5.1.2.3 Filtering of Receive Packets .................................................................. 42 5.1.3 Flow Control........................................................................................................... 44 5.1.3.1 802.3x Flow Control (Full-Duplex Operation)......................................... 44 5.1.4 Fiber Operation...................................................................................................... 48 5.1.5 Auto-Negotiation .................................................................................................... 49 5.1.5.1 Determining If Link Is Established in Auto-Negotiation Mode ................ 49 5.1.6 Forced Mode Operation......................................................................................... 50 5.1.6.1 Determining If Link Is Established in Forced Mode................................ 50 5.1.7 Jumbo Packet Support .......................................................................................... 50 5.1.8 RMON Statistics Support....................................................................................... 51 5.1.8.1 RMON Statistics..................................................................................... 51 5.1.8.2 Conventions ........................................................................................... 52 5.1.8.3 Additional Statistics................................................................................ 53 System Packet Interface Level 4 Phase 2 .......................................................................... 53 5.2.1 Data Path............................................................................................................... 55 5.2.1.1 Control Words ........................................................................................ 56 5.2.1.2 EOP Abort.............................................................................................. 58 5.2.1.3 DIP4 ....................................................................................................... 59 5.2.2 Start-Up Parameters.............................................................................................. 60 5.2.2.1 CALENDAR_LEN .................................................................................. 60 5.2.2.2 CALENDAR_M ...................................................................................... 61 5.2.2.3 DIP2_Thr................................................................................................ 61 5.2.2.4 Loss_Of_Sync........................................................................................ 61 5.2.2.5 DATA_MAX_T ....................................................................................... 61 5.2.2.6 REP_T ................................................................................................... 61 5.2.2.7 DIP4_UnLock......................................................................................... 61 5.2.2.8 DIP4_Lock ............................................................................................. 61 5.2.2.9 MaxBurst1.............................................................................................. 62 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 3 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Contents 5.2.2.10 MaxBurst2.............................................................................................. 62 Dynamic Phase Alignment Training Sequence (Data Path De-skew) ................... 62 5.2.3.1 Training at Start-up ................................................................................ 62 5.2.3.2 Periodic Training .................................................................................... 62 5.2.3.3 Training in a Practical Implementation................................................... 63 5.2.4 FIFO Status Channel ............................................................................................. 63 5.2.5 DC Parameters ...................................................................................................... 67 SerDes Interface................................................................................................................. 67 5.3.1 Introduction ............................................................................................................ 67 5.3.2 Features................................................................................................................. 67 5.3.3 Functional Description ........................................................................................... 67 5.3.3.1 Transmitter Operational Overview ......................................................... 68 5.3.3.2 Transmitter Programmable Driver-Power Levels................................... 68 5.3.3.3 Receiver Operational Overview ............................................................. 69 5.3.3.4 Selective Power-Down........................................................................... 70 5.3.4 Timing and Electrical Characteristics..................................................................... 70 Optical Module Interface..................................................................................................... 70 5.4.1 Introduction ............................................................................................................ 70 5.4.2 Supported Optical Module Interface Signals ......................................................... 70 5.4.3 Functional Descriptions ......................................................................................... 71 5.4.3.1 High-Speed Serial Interface................................................................... 71 5.4.3.2 Low-Speed Status Signaling Interface................................................... 71 5.4.4 I2C Module Configuration Interface ....................................................................... 73 5.4.4.1 General Description ............................................................................... 73 5.4.4.2 I2C Protocol Specifics ............................................................................ 76 5.4.4.3 Port Protocol Operation ......................................................................... 76 5.4.4.4 Clock and Data Transitions.................................................................... 76 5.4.4.5 AC Timing Characteristics ..................................................................... 79 LED Interface...................................................................................................................... 79 5.5.1 Introduction ............................................................................................................ 79 5.5.2 Modes of Operation ............................................................................................... 80 5.5.2.1 Mode 0 ................................................................................................... 80 5.5.2.2 Mode 1 ................................................................................................... 80 5.5.3 LED Interface Signal Description........................................................................... 80 5.5.4 Mode 0: Detailed Operation................................................................................... 80 5.5.5 Mode 1: Detailed Operation................................................................................... 81 5.5.6 Power-On, Reset, and Initialization ....................................................................... 82 5.5.6.1 Enabling the LED Interface .................................................................... 82 5.5.7 LED Data Decodes ................................................................................................ 83 5.5.7.1 LED Signaling Behavior ......................................................................... 84 CPU Interface ..................................................................................................................... 84 5.6.1 General Description ............................................................................................... 84 5.6.2 Functional Description ........................................................................................... 85 5.6.2.1 Read Access.......................................................................................... 86 5.6.2.2 Write Access .......................................................................................... 87 5.6.2.3 Timing parameters ................................................................................. 88 5.6.3 Endian.................................................................................................................... 88 JTAG (Boundary Scan)....................................................................................................... 88 5.7.1 TAP Interface (JTAG) ............................................................................................ 88 5.7.2 TAP State Machine................................................................................................ 89 5.7.3 Instruction Register and Supported Instructions.................................................... 89 5.7.4 ID Register............................................................................................................. 89 5.2.3 5.3 5.4 5.5 5.6 5.7 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 4 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.8 6.0 6.2 6.3 6.4 6.5 6.6 6.7 Power Supply Sequencing.................................................................................................. 92 6.1.1 Power-Up Sequence.............................................................................................. 92 6.1.2 Power-Down Sequence ......................................................................................... 92 Analog Power Filtering........................................................................................................ 93 TX FIFO and RX FIFO Operation ....................................................................................... 93 6.3.1 TX FIFO ................................................................................................................. 94 6.3.1.1 MAC Transfer Threshold........................................................................ 94 6.3.1.2 TX FIFO Relation to the SPI4-2 Transmit FIFO Status (TSTAT)........... 95 6.3.1.3 TX FIFO Drain........................................................................................ 95 6.3.2 RX FIFO................................................................................................................. 96 Reset and Initialization........................................................................................................ 97 6.4.1 SPI4-2 Initialization ................................................................................................ 97 6.4.1.1 RX SPI4-2 .............................................................................................. 97 6.4.1.2 TX SPI4-2 .............................................................................................. 98 6.4.1.3 SerDes ................................................................................................... 98 6.4.1.4 CPU ....................................................................................................... 98 SerDes Power-Down Capabilities....................................................................................... 98 6.5.1 Placing the SerDes Port in Power-Down Mode ..................................................... 98 6.5.2 Bringing the SerDes Port Out of Power-Down Mode............................................. 98 IXF1110 MAC Unused Ports .............................................................................................. 99 Optical Module Connections to the IXF1110 MAC ............................................................. 99 6.7.1 SFP-to-IXF1110 MAC Connection......................................................................... 99 Electrical Specifications ........................................................................................................... 102 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8.0 5.7.5 Boundary Scan Register........................................................................................ 89 5.7.6 Bypass Register..................................................................................................... 89 Clocks ................................................................................................................................. 90 5.8.1 System Interface Reference Clocks ...................................................................... 90 5.8.1.1 CLK125 .................................................................................................. 90 5.8.1.2 CLK50 .................................................................................................... 90 5.8.2 SPI4-2 Receive and Transmit Data Path Clocks ................................................... 90 5.8.3 JTAG Clock............................................................................................................ 91 5.8.4 I2C Clock................................................................................................................ 91 5.8.5 LED Clock.............................................................................................................. 91 Applications ................................................................................................................................. 92 6.1 7.0 Contents DC Specifications ............................................................................................................. 104 Undershoot/Overshoot Specifications .............................................................................. 105 CPU Timing Specification ................................................................................................. 106 JTAG Timing Specification ............................................................................................... 107 Transmit Pause Control Timing Specifications ................................................................. 108 Optical Module Interrupt and I2C Timing Specification ..................................................... 109 System Timing Specifications........................................................................................... 111 LED Timing Specifications................................................................................................ 111 SerDes Timing Specification............................................................................................. 112 SPI4-2 Timing Specifications............................................................................................ 114 Register Definitions................................................................................................................... 116 8.1 8.2 8.3 8.4 Introduction ....................................................................................................................... 116 Document Structure.......................................................................................................... 116 Graphical Representation ................................................................................................. 116 Per Port Registers ............................................................................................................ 117 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 5 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 8.5 9.0 Contents Memory Map..................................................................................................................... 118 8.5.1 MAC Control Registers ........................................................................................ 125 8.5.2 MAC RX Statistics Register Overview ................................................................. 133 8.5.3 MAC TX Statistics Register Overview ................................................................. 136 8.5.4 Global Status and Configuration Register Overview ........................................... 139 8.5.5 Global RX Block Register Overview .................................................................... 144 8.5.6 TX Block Register Overview ................................................................................ 153 8.5.7 SPI4-2 Block Register Overview.......................................................................... 162 8.5.8 SerDes Register Overview .................................................................................. 165 8.5.9 Optical Module Interface Block Register Overview.............................................. 166 Mechanical Specifications........................................................................................................ 169 9.1 9.2 Features............................................................................................................................ 169 IXF1110 MAC Package Specifics..................................................................................... 169 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 6 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figures Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 IXF1110 MAC Block Diagram........................................................................................................ 15 IXF1110 MAC System Block Diagram........................................................................................... 16 552-Ball CBGA Assignments (Top View) ...................................................................................... 17 Interface Diagram .......................................................................................................................... 19 Packet Buffering FIFO ................................................................................................................... 45 Ethernet Frame Format ................................................................................................................. 45 PAUSE Frame Format................................................................................................................... 46 Transmit Pause Control Interface.................................................................................................. 48 SPI4-2 Interfacing with the Network Processor or Forwarding Engine.......................................... 54 Data Path State ............................................................................................................................. 56 Per-Port State Diagram with Transitions at Control Words ........................................................... 58 DIP-4 Calculation Boundaries ....................................................................................................... 59 DIP-4 Calculation Algorithm .......................................................................................................... 60 FIFO Status State Diagram ........................................................................................................... 64 Example of DIP-2 Encoding ......................................................................................................... 65 Transmitter Concept ...................................................................................................................... 68 Receiver Concept .......................................................................................................................... 69 Data Validity Timing....................................................................................................................... 76 Start and Stop Definition Timing.................................................................................................... 77 Acknowledge Timing ..................................................................................................................... 77 Random Read ............................................................................................................................... 78 Byte Write ...................................................................................................................................... 79 Mode 0 Timing............................................................................................................................... 81 Mode 1 Timing............................................................................................................................... 82 CPU Interface Inputs/Outputs........................................................................................................ 85 Read Timing - Asynchronous Interface ........................................................................................ 87 Write Timing - Asynchronous Interface......................................................................................... 87 Power Sequencing ........................................................................................................................ 92 Analog Power Supply Filter Network ............................................................................................. 93 Packet Buffering FIFO ................................................................................................................... 94 SFP-to-IXF1110 MAC Connection ................................................................................................ 99 CPU Port Read Timing ................................................................................................................ 106 CPU Port Write Timing ................................................................................................................ 106 JTAG Timing................................................................................................................................ 107 Transmit Pause Control Interface................................................................................................ 108 Optical Module Interrupt Timing .................................................................................................. 109 I2C Bus Timing ............................................................................................................................ 109 I2C Write Cycle ............................................................................................................................ 110 Hardware Reset Timing............................................................................................................... 111 LED Timing.................................................................................................................................. 111 SerDes Timing............................................................................................................................. 112 SPI4-2 Transmit FIFO Status Bus Timing ................................................................................... 114 SPI4-2 Receive FIFO Status Bus Timing .................................................................................... 114 Memory Overview........................................................................................................................ 117 Register Overview ....................................................................................................................... 118 RoHS Compliant CBGA Package Diagram (Side View).............................................................. 170 RoHS Compliant CBGA Package Diagram (Bottom and Top View) ........................................... 171 Non-RoHS Compliant CBGA Package Diagram (Side View)...................................................... 172 Non-RoHS Compliant CBGA Package Diagram (Bottom and Top View) ................................... 173 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 7 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Tables Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SPI4-2 Interface Signal Descriptions............................................................................................. 20 SerDes Interface Signal Descriptions............................................................................................ 22 CPU Interface Signal Descriptions ................................................................................................ 23 Pause Control Interface Signal Descriptions ................................................................................. 24 Optical Module Interface Signal Descriptions................................................................................ 25 LED Interface Signal Descriptions................................................................................................. 26 JTAG Interface Signal Descriptions............................................................................................... 26 System Interface Signal Descriptions............................................................................................ 27 Power Supply Signal Descriptions................................................................................................. 27 Unused Balls/Reserved ................................................................................................................. 29 Ball List in Alphanumeric Order by Signal Name........................................................................... 30 Ball List in Alphanumeric Order by Ball Location........................................................................... 35 Pause Packets Drop Enable Behavior .......................................................................................... 43 CRC Errored Packets Drop Enable Behavior................................................................................ 43 Valid Decodes for TXPAUSEADD[3:0].......................................................................................... 47 RMON Additional Statistics Registers ........................................................................................... 51 SPI4-2 Interface Signal Summary ................................................................................................. 54 Control Word Format ..................................................................................................................... 56 Control Word Definitions................................................................................................................ 57 FIFO Status Format....................................................................................................................... 66 SerDes Driver TX Power Levels.................................................................................................... 69 IXF1110 MAC-to-SFP Connections............................................................................................... 70 LED Signal Descriptions................................................................................................................ 80 Mode 0 Clock Cycle to Data Bit Relationship ................................................................................ 81 Mode 1 Clock Cycle to Data Bit Relationship ................................................................................ 82 LED Data Decodes........................................................................................................................ 83 LED Behavior ................................................................................................................................ 84 CPU Interface Signals ................................................................................................................... 85 Recommended JTAG Termination ................................................................................................ 88 Supported Boundary Scan Instructions ......................................................................................... 89 Power Sequencing ........................................................................................................................ 93 Analog Power Balls ....................................................................................................................... 93 SFP-to-IXF1110 MAC Connection ............................................................................................. 100 Absolute Maximum Ratings......................................................................................................... 102 Operating Conditions................................................................................................................... 103 2.5 V CMOS and 3.3 V LVTTL I/O Electrical Characteristics ...................................................... 104 LVDS I/O Electrical Characteristics ............................................................................................. 104 Undershoot/Overshoot Limits ...................................................................................................... 105 CPU Timing Parameters.............................................................................................................. 106 JTAG Timing Parameters ............................................................................................................ 108 Transmit Pause Control Interface Parameters ............................................................................ 108 Optical Module Interrupt Timing Parameters............................................................................... 109 I2C AC Timing Characteristics..................................................................................................... 110 Hardware Reset Timing Parameters ........................................................................................... 111 LED Timing Parameters .............................................................................................................. 112 Transmitter Characteristics.......................................................................................................... 113 Receiver Characteristics.............................................................................................................. 113 SPI4-2 Transmit FIFO Status Bus Timing Parameters................................................................ 114 SPI4-2 Receive FIFO Status Bus Timing Parameters................................................................. 115 SPI4-2 LVDS Rise/Fall Times ..................................................................................................... 115 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 8 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 Tables MAC Control Register Map.......................................................................................................... 118 MAC RX Statistics Register Map................................................................................................. 119 MAC TX Statistics Register Map ................................................................................................. 120 Global Status and Configuration Register Map ........................................................................... 121 RX Block Register Map ............................................................................................................... 121 TX Block Register Map................................................................................................................ 122 SPI4-2 Block Register Map ......................................................................................................... 124 SerDes Block Register Map ........................................................................................................ 124 Optical Module Interface Block Register Map ............................................................................. 124 Station Address Low ($ Port_Index + 0x00)................................................................................ 125 Station Address High ($ Port_Index + 0x01) ............................................................................... 125 FDFC Type ($ Port_Index + 0x03) .............................................................................................. 125 FC TX Timer Value ($ Port_Index + 0x07) .................................................................................. 125 FDFC Address Low ($ Port_Index + 0x08) ................................................................................. 126 FDFC Address High ($ Port_Index + 0x09)................................................................................. 126 IPG Transmit Time ($ Port_Index + 0x0C) .................................................................................. 126 Pause Threshold ($ Port_Index + 0x0E) ..................................................................................... 127 Max Frame Size ($ Port_Index + 0x0F) ...................................................................................... 127 FC Enable ($ Port_Index + 0x12)................................................................................................ 127 Discard Unknown Control Frame ($ Port_Index + 0x15)............................................................. 128 RX Config Word ($ Port_Index + 0x16)....................................................................................... 128 TX Config Word ($ Port_Index + 0x17) ....................................................................................... 129 Diverse Config ($ Port_Index + 0x18) ......................................................................................... 129 RX Packet Filter Control ($ Port_Index + 0x19) .......................................................................... 131 Port Multicast Address Low ($ Port_Index + 0x1A)..................................................................... 132 Port Multicast Address High ($ Port_Index + 0x1B) .................................................................... 132 MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) ................................................... 133 MAC TX Statistics ($ Port_Index + 0x40 - Port_Index + 0x58) ................................................... 137 Port Enable ($ 0x500).................................................................................................................. 140 Link LED Enable ($ 0x502).......................................................................................................... 141 Core Clock Soft Reset ($ 0x504)................................................................................................. 141 MAC Soft Reset ($ 0x505)........................................................................................................... 142 CPU Interface ($ 0x508).............................................................................................................. 142 LED Control ($ 0x509)................................................................................................................. 143 LED Flash Rate ($ 0x50A)........................................................................................................... 143 LED Fault Disable ($ 0x50B) ....................................................................................................... 143 JTAG ID Revision ($ 0x50C) ....................................................................................................... 144 RX FIFO High Watermark Ports 0 to 9 ($ 0x580 - 0x589)........................................................... 145 RX FIFO Low Watermark Ports 0 to 9 ($ 0x58A - 0x593) ........................................................... 146 RX FIFO Number of Frames Removed Ports 0 to 9 ($ 0x594 - 0x59D)...................................... 147 RX FIFO Port Reset ($ 0x59E).................................................................................................... 149 RX FIFO Errored Frame Drop Enable ($ 0x59F)......................................................................... 150 RX FIFO Overflow Event ($ 0x5A0) ............................................................................................ 152 TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609) ........................................................... 153 TX FIFO Low Watermark Ports 0 to 9 ($ 0x60A - 0x613)............................................................ 155 TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D) ............................................. 157 TX FIFO Overflow Event ($ 0x61E)............................................................................................. 159 TX FIFO Drain ($0x620) .............................................................................................................. 160 TX FIFO Info Out-of-Sequence ($ 0x621) ................................................................................... 161 TX FIFO Number of Frames Removed Ports 0-9 ($ 0x622 - 0x62B) .......................................... 162 SPI4-2 RX Burst Size ($ 0x700) .................................................................................................. 162 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 9 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 102 103 104 105 106 107 108 109 110 111 Tables SPI4-2 RX Training ($ 0x701) ..................................................................................................... 163 SPI4-2 RX Calendar ($ 0x702).................................................................................................... 164 SPI4-2 TX Synchronization ($ 0x703) ......................................................................................... 165 SerDes Tx Driver Power Level Ports 0-6 ($ 0x784) .................................................................... 165 SerDes Tx Driver Power Level Ports 7-9 ($ 0x785) .................................................................... 166 SerDes TX and RX Power-Down Ports 0-9 ($ 0x787)................................................................. 166 Optical Module Status Ports 0-9 ($ 0x799).................................................................................. 166 Optical Module Control Ports 0-9 ($ 0x79A)................................................................................ 167 I2C Control Ports 0-9 ($ 0x79B) .................................................................................................. 167 I2C Data Ports 0-9 ($ 0x79C) ...................................................................................................... 168 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 10 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Revision History Revision History Revision 11.0 Revision Date: 13 April 2009 Updated Section 5.4.4.2, I2C Protocol Specifics, on page 76. Updated Figure 29, Analog Power Supply Filter Network, on page 93. Updated Table 36, 2.5 V CMOS and 3.3 V LVTTL I/O Electrical Characteristics, on page 104. Changed the 3.3 V LVTTL overshoot limit to 5.5 V in Table 38, Undershoot/Overshoot Limits, on page 105. Updated the Tcdwd and Tcdrh parameter values in Table 39, CPU Timing Parameters, on page 106. Updated the Tdatd, Tlath and Tlatl parameter values in Table 45, LED Timing Parameters, on page 112. Updated the package drawings in Section 9.2, IXF1110 MAC Package Specifics, on page 169. Removed the ordering and marking information from Section 9.0, Mechanical Specifications, on page 169. This information is now available from www.cortina-systems.com. Revision 10.1 Revision Date: 8 September 2007 Corrected typographical error in Table 103, SPI4-2 RX Calendar ($0x702), on page 168, bits 12 and 13. Revision 10.0 Revision Date: 5 July 2007 First release of this document from Cortina Systems, Inc. Clock Specification Changes: * Changed frequency range for CLK50 from 40 MHz--50 MHz to 42 MHz--50 MHz * Changed frequency range for RDCLK_x (8 x CLK50) from 320 MHz--400 MHz to 336 MHz--400 MHz RxSymbolError counter clarification: * Added that the counter increments once for each packet that encounters symbol errors during reception. Symbol errors between packets are not counted. Clock Voltage Changes: * Changed voltage for CLK125 from 2.5 V CMOS to 3.3 V LVTTL * Changed voltage for CLK50 from 2.5 V CMOS to 3.3 V LVTTL Revision 009 Revision Date: 07 October 2005 Added Section n, 552-Ceramic BGA (RoHS-compliant) Table 7 "JTAG Interface Signal Descriptions" Changed Standard to 3.3 V LVTTL from 2.5 V CMOS Modified Table 11 "Ball List in Alphanumeric Order by Signal Name" and Table 12 "Ball List in Alphanumeric Order by Ball Location": Figure 6 "Ethernet Frame Format" Changed Preamble byte count to 7 bytes Figure 7 "PAUSE Frame Format" Changed Preamble byte count to 7 bytes Figure 44 "Markings" New image (Added RoHS marking) Modified Figure 47 "Ordering Information - Sample" Revision 008 Revision Date: August 10, 2004 Globally replaced the following: "AVDD" to "AVDD1P8_1, AVDD1P8_2" and "AVDD2" to "AVDD2P5_1, AVDD2P5_2". Globally replaced the following: "AIDD" to "AIDD1P8_1, AIDD1P8_2" and "AIDD2" to "AIDD2P5_1, AIDD2P5_2". Corrected ball number for RDAT15_P from K1 to K12 in Table 3 "SPI4-2 Interface Signal Descriptions". Removed Short Runts Threshold Register ($ Port_Index 0x14) and changed to Reserved in "Table 51 "MAC Control Register Map". Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 11 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Revision History Revision 007 Revision Date: May 5, 2004 Changed product ordering number to reflect B2 [HFIXF1110CC.B2: 860817]. Modified Table 11 "Power Supply Signal Descriptions" [changed AVDD to AVDD1P8_1/2 and AVDD2 to AVDD2P5_1/2]. Added note under Section 5.1.2.1, "Padding of Undersized Frames on Transmit". Modified Section 5.1.2.3.1, "Filter on Unicast Packet Match" [added text to end of paragraph]. Added Section 5.1.3, "Flow Control". Modified third and fourth paragraphs of Section 5.2.2.2, "CALENDAR_M". Added Section 6.2, "Analog Power Filtering" (IXF1110 only) Modified Section 6.3.1, "TX FIFO" [added note]. Added Section 6.3.1.3, "TX FIFO Drain (IXF1110 Version)". Added Table 48 "SPI4-2 LVDS Rise/Fall Times". Modified Table 72 "RX Packet Filter Control ($ Port_Index + 0x19)" (removed table note from the bit 4 description]. Modified Table 114 "SPI4-2 RX Calendar ($ 0x702)" [changed Register bits 3:0 to Reserved]. Modified Table 88 "JTAG ID Revision ($ 0x50C)" [added table note 2]. Added Table 105 "TX FIFO Drain ($0x620)". Modified Table 116 "IXF1010 MAC Product Information" [changed part number and mm number to reflect B2]. Revision 006 Revision Date: December 30, 2003 Deleted old Table 19: 1x9-to-IXF1110 Connection Modified text under Section 6.5, "SerDes Power-Down Capabilities (IXF1110 Only)". Changed Table 98: TX FIFO Port Reset Register (Addr: 0x620) to Reserved. Revision 005 (Sheet 1 of 2) Revision Date: November 24, 2003 Added product ordering and operating temperature range information, and changed SFF-8053, Revision 5.5 Compatible to SFP MSA compatible. Deleted old Figures 6, 7, and 8 (Revision 004) and replaced with Figure 6 "IXF1110 552-Ball CBGA Assignments (Top View)" Added new Section 3.1, "IXF1110 Ball List Tables" including Table 1 "IXF1110 Ball List in Alphanumeric Order by Signal Name" and Table 2 "IXF1110 Ball List in Alphanumeric Order by Ball Location". Modified Figure 4 "IXF1110 Interface Diagram". Broke up old Table 3 into Table 3 "IXF1110 SPI4-2 Interface Signal Descriptions" through Table 12 "IXF1110 System Interface Signal Descriptions". Modified Table 5 "IXF1110 CPU Interface Signal Descriptions". Modified Table 7 "IXF1110 Optical Module Interface Signal Descriptions". Added note under Section 5.1.2.3.5, "Filter PAUSE Packets". Added note under Section 5.1.2.3.6, "Filter CRC Errored Packets". Added third note to Section 5.1.3, "Fiber Operation". Modified text and added note under Section 5.1.4, "Fiber Auto-Negotiation". Modified Section 5.1.5, "Forced Mode Operation" Modified Figure 6 "IXF1110 SPI4-2 Interfacing with the Network Processor or Forwarding Engine". Added Table 17 "IXF1110 SPI4-2 Interface Signal Summary". Added new Section 5.2.1.2, "EOP Abort". Globally modified SFF-8053, Revision 5.5 Compatible to SFP MSA compatible under Section 5.3, "SerDes Interface". Modified Section 5.3.3, "Functional Description". Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 12 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Revision History Revision 005 (Sheet 2 of 2) Revision Date: November 24, 2003 Added Section 5.5.4.1 "Transmitter Programmable Driver-Power Levels". Added Table 21 "IXF1110 SerDes Driver TX Power Levels". Changed Gigabit Interface Converter section to Section 5.6, "Optical Module Interface". Globally changed GBIC to Optical Module. Modified Section 5.4.3.2.1, "MOD_DEF_9:0". Modified Section 5.6.3.2.2, "TX_FAULT_9:0". Modified Section 5.6.3.2.3, "RX_LOS_9:0". Added note to "UPX_RDY" under Section 5.8.2, "Functional Description". Added note under Section 6.2.1, "TX FIFO". Added note under Section 6.2.1.1, "MAC Transfer Threshold". Modified/added Power Consumption Max to Table 49 "IXF1110 Operating Conditions". Modified Table 36 "IXF1110 2.5 V LVTTL and CMOS I/O Electrical Characteristics". Added Section 7.2, "Undershoot/Overshoot Specifications". Modified Table 39 "IXF1110 CPU Timing Parameters". Modified Table 46 "IXF1110 Transmitter Characteristics". Modified Table 47 "IXF1110 Receiver Characteristics" (added Common Mode Voltage Spec). Added caution note under Section 8.0, "Register Definitions". Modified Table 53 "IXFIXF1110 Global Status and Configuration Register Map". Modified Table 65 "IPG Transmit Time Register (Addr: Port_Index + 0x0C)". Modified Table 66 "Pause Threshold Register (Addr: Port_Index + 0x0E)". Modified Table 68 "FC Enable Register (Addr: Port_Index + 0x12)". Modified Table 69 "Short Runts Threshold Register (Addr: Port_Index + 0x14)". Modified Table 71 "RX Config Word Register (Addr: Port_Index + 0x16)". Modified Table 72 "TX Config Word Register (Addr: Port_Index + 0x17)". Modified Table 73 "Diverse Config Register (Addr: Port_Index + 0x18)". Modified Table 74 "RX Packet Filter Control Register (Addr: Port_Index + 0x19)" (removed note 2 from bit 4, modified bit 5 description). Modified Table 77 "MAC RX Statistics Registers (Addr: Port_Index + 0x20 - Port_Index + 0x39)". Added Table 81 "Core Clock Soft Reset Register (Addr: 0x504)". Added Table 82 "MAC Soft Reset Register (Addr: 0x505)". Added Table 91 "RX FIFO Port Reset Register (Addr: 0x59E)". Added Section 98, "TX FIFO Port Reset Register (Addr: 0x620)". Modified Table 100 "TX FIFO Number of Frames Removed Ports 0-9 (Addr: 0x622 - 0x62B)". Modified Table 103 "SPI4-2 RX Calendar Register (Addr: 0x702)". Modified Table 104 "SPI4-2 TX Synchronization Register (Addr: 0x703) (B0 Silicon Revision)". Added Table 106 "SerDes Tx Driver Power Level Ports 0-6 Register (Addr: 0x784)". Added Table 107 "SerDes Tx Driver Power Level Ports 7-9 Register (Addr: 0x785)". Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 13 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 1.0 1.0 Introduction Introduction This datasheet describes the functionality and operation of the Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (IXF1110 MAC). 1.1 What You Will Find in This Document This document contains the following sections: * Section 2.0, General Description, on page 15 IXF1110 MAC block diagram system architecture. * Section 3.0, Ball Assignments and Ball List Tables, on page 17 IXF1110 MAC ball grid diagram with two ball list tables (by pin number and signal name) * Section 4.0, Ball Assignments and Signal Descriptions, on page 18 Signal naming methodology and signal descriptions. * Section 5.0, Functional Description, on page 41 Detailed information about the operation of the IXF1110 MAC including general features, and interface types and descriptions. * Section 6.0, Applications, on page 92 Discusses the following: -- Section 6.1, Power Supply Sequencing -- Section 6.3, TX FIFO and RX FIFO Operation -- Section 6.4, Reset and Initialization -- Section 6.7, Optical Module Connections to the IXF1110 MAC * Section 7.0, Electrical Specifications, on page 102 Information on the product-operating parameters, electrical specifications, and timing parameters. * Section 8.0, Register Definitions, on page 116 Memory map/detailed descriptions and default values for the register set. * Section 9.0, Mechanical Specifications, on page 169 IXF1110 MAC packaging information. 1.2 Related Documents Title Document Number IXF1110 MAC Specification Update 251436 IXF1110 MAC Design and Layout Guide 250676 IXF1110 MAC Demo Board Development Kit Manual 250807 (R) Cortina Systems SPI4 Phase 2 Performance in Gigabit Ethernet Media Access Controllers Application Note 250643 Interfacing with the IXF1010 MAC and IXF1110 MAC 10-Port Gigabit Ethernet Media Access Controllers Application Note 250856 IXF1110 MAC Thermal Design Considerations Application Note 250289 Flow Control in theIXF1010 MAC and IXF1110 MAC 10-Port Gigabit Ethernet Media Access Controllers Application Note 250236 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 14 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 2.0 2.0 General Description General Description The IXF1110 MAC is a 10-port 1000 Mbps Ethernet Media Access Controller (MAC). The 10 Gigabit interface to the network processor is supported through a System Packet Interface Level 4 Phase 2 (SPI4-2), and the media interface is an integrated Serializer/Deserializer (SerDes). Figure 1 illustrates the IXF1110 MAC block diagram.Figure 2 represents the IXF1110 MAC system block diagram. Figure 1 IXF1110 MAC Block Diagram IXF1110 LED Controller Optical Module Controller RMON Statistics SPI4-2 CPU Interface SPI4-2 Scheduler MAC Core RX/TX FIFOs 0 SerDes 0 MAC Core RX/TX FIFOs 1 SerDes 1 MAC Core RX/TX FIFOs 2 SerDes 2 MAC Core RX/TX FIFOs 3 SerDes 3 MAC Core RX/TX FIFOs 4 SerDes 4 MAC Core RX/TX FIFOs 5 SerDes 5 MAC Core RX/TX FIFOs 6 SerDes 6 MAC Core RX/TX FIFOs 7 SerDes 7 MAC Core RX/TX FIFOs 8 SerDes 8 MAC Core RX/TX FIFOs 9 SerDes 9 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 15 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 2 2.0 General Description IXF1110 MAC System Block Diagram Forwarding Engine Network Processor SPI4-2 LED Serial-to-Parallel Converter LED Serial Interface IXF1110 uP IF CPU SerDes/Optical Module Interface Port 0 Optics Module Port 1 Optics Module Port 2 Optics Module Port 3 Optics Module Port 4 Optics Module Port 5 Optics Module Port 6 Optics Module Port 7 Optics Module Port 8 Optics Module Port 9 Optics Module Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 16 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 3.0 3.0 Ball Assignments and Ball List Tables Ball Assignments and Ball List Tables Figure 3 illustrates the 552-Ball CBGA assignments. Table 11 and Table 12 provide ball list tables in alphanumeric order by signal name and ball location under Section 4.3, Ball List Tables, on page 30. Figure 3 552-Ball CBGA Assignments (Top View) AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 AD1 AC1 AB1 AA1 Y1 W1 V1 U1 T1 R1 L1 N1 M1 L1 K1 J1 H1 G1 F1 E1 D1 C1 B1 A1 1 2 AD2 AC2 AB2 AA2 Y2 W2 V2 U2 T2 R2 P2 N2 M2 L2 K2 J2 H2 G2 F2 E2 D2 C2 B2 A2 2 3 AD3 AC3 AB3 AA3 Y3 W3 V3 U3 T3 R3 P3 N3 M3 L3 K3 J3 H3 G3 F3 E3 D3 C3 B3 A3 3 4 AD4 AC4 AB4 AA4 Y4 W4 V4 U4 T4 R4 P4 N4 M4 L4 K4 J4 H4 G4 F4 E4 D4 C4 B4 A4 4 5 AD5 AC5 AB5 AA5 Y5 W5 V5 U5 T5 R5 P5 N5 M5 L5 K5 J5 H5 G5 F5 E5 D5 C5 B5 A5 5 6 AD6 AC6 AB6 AA6 Y6 W6 V6 U6 T6 R6 P6 N6 M6 L6 K6 J6 H6 G6 F6 E6 D6 C6 B6 A6 6 7 AD7 AC7 AB7 AA7 Y7 W7 V7 U7 T7 R7 P7 N7 M7 L7 K7 J7 H7 G7 F7 E7 D7 C7 B7 A7 7 8 AD8 AC8 AB8 AA8 Y8 W8 V8 U8 T8 R8 P8 N8 M8 L8 K8 J8 H8 G8 F8 E8 D8 C8 B8 A8 8 9 AD9 AC9 AB9 AA9 Y9 W9 V9 U9 T9 R9 P9 N9 M9 L9 K9 J9 H9 G9 F9 E9 D9 C9 B9 A9 9 10 AD10 AC10 AB10 AA10 Y10 W10 V10 U10 T10 R10 P10 N10 M10 L10 K10 J10 H10 G10 F10 E10 D10 C10 B10 A10 10 11 AD11 AC11 AB11 AA11 Y11 W11 V11 U11 T11 R11 P11 N11 M11 L11 K11 J11 H11 G11 F11 E11 D11 C11 B11 A11 11 12 AD12 AC12 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 K12 J12 H12 G12 F12 E12 D12 C12 B12 A12 12 13 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 P13 N13 M13 L13 K13 J13 H13 G13 F13 E13 D13 C13 B13 A13 13 14 AD14 AC14 AB14 AA14 Y14 W14 V14 U14 T14 R14 P14 N14 M14 L14 K14 J14 H14 G14 F14 E14 D14 C14 B14 A14 14 15 AD15 AC15 AB15 AA15 Y15 W15 V15 U15 T15 R15 P15 N15 M15 L15 K15 J15 H15 G15 F15 E15 D15 C15 B15 A15 15 16 AD16 AC16 AB16 AA16 Y16 W16 V16 U16 T16 R16 P16 N16 M16 L16 K16 J16 H16 G16 F16 E16 D16 C16 B16 A16 16 17 AD17 AC17 AB17 AA17 Y17 W17 V17 U17 T17 R17 P17 N17 M17 L17 K17 J17 H17 G17 F17 E17 D17 C17 B17 A17 17 18 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 R18 P18 N18 M18 L18 K18 J18 H18 G18 F18 E18 D18 C18 B18 A18 18 19 AD19 AC19 AB19 AA19 Y19 W19 V19 U19 T19 R19 P19 N19 M19 L19 K19 J19 H19 G19 F19 E19 D19 C19 B19 A19 19 20 AD20 AC20 AB20 AA20 Y20 W20 V20 U20 T20 R20 P20 N20 M20 L20 K20 J20 H20 G20 F20 E20 D20 C20 B20 A20 20 21 AD21 AC21 AB21 AA21 Y21 W21 V21 U21 T21 R21 P21 N21 M21 L21 K21 J21 H21 G21 F21 E21 D21 C21 B21 A21 21 22 AD22 AC22 AB22 AA22 Y22 W22 V22 U22 T22 R22 P22 N22 M22 L22 K22 J22 H22 G22 F22 E22 D22 C22 B22 A22 22 23 AD23 AC23 AB23 AA23 Y23 W23 V23 U23 T23 R23 P23 N23 M23 L23 K23 J23 H23 G23 F23 E23 D23 C23 B23 A23 23 24 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 P24 N24 M24 L24 K24 J24 H24 G24 F24 E24 D24 C24 B24 A24 24 L K J H G F E D C B A AD AC AB AA Y W V U T R P N M B2510-01 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 17 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.0 Ball Assignments and Signal Descriptions 4.0 Ball Assignments and Signal Descriptions 4.1 Naming Conventions 4.1.1 Signal Name Conventions Signal names begin with a Signal Mnemonic, and can also contain one or more of the following designations: a differential pair designation, a serial designation, a port designation and an Active Low designation. Signal naming conventions are as follows: Differential Pair + Port Designation. The positive and negative components of differential pairs tied to a specific port are designated by the Signal Mnemonic, immediately followed by an underscore and either P (positive component) or N (negative component), and an underscore followed by the port designation. For example, SerDes interface signals for port 0 are identified as TX_P_0 and TX_N_0. Serial Designation. A set of signals that are not tied to any specific port are designated by the Signal Mnemonic, followed by a bracketed serial designation. For example, the set of 11 CPU Address Bus signals is identified as UPX_ADD[10:0]. Port Designation. Individual signals that apply to a particular port are designated by the Signal Mnemonic, immediately followed by an underscore and the Port Designation. For example, Optical module I2C Serial Data signals would be identified as I2C_DATA_0, I2C_DATA_1, etc. Active Low Designation. A control input or indicator output that is active Low is designated by a final suffix consisting of an underscore followed by an upper case "L". For example, the CPU cycle complete identifier is shown as UPX_RDY_L. 4.1.2 Register Address Conventions Registers located in on-chip memory are accessed using a register address, which is provided in Hex notation. A Register Address is indicated by the dollar sign ($), followed by the memory location in Hex. 4.2 Interface Signal Groups This section describes the IXF1110 MAC signals in groups according to the associated interface or function. Figure 4 and Table 1, SPI4-2 Interface Signal Descriptions through Table 10, Unused Balls/Reserved, on page 29 describe the IXF1110 MAC signals. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 18 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 4 4.2 Interface Signal Groups Interface Diagram TDAT[15:0]_P/N TDCLK_P/N TCTL_P/N SPI4-2 Interface RX_P/N_0:9 TX_P/N_0:9 TSTAT[1:0] TSCLK RDAT[15:0]_P/N RDCLK_P/N RCTL_P/N RSTAT[1:0] RSCLK JTAG Interface TMS TDI TDO TCLK TRST_L Pause Control Interface TXPAUSEADD[3:0] TXPAUSEFR CPU Interface UPX_DATA[31:0] UPX_ADD[10:0] UPX_WR_L UPX_RD_L UPX_CS_L UPX_RDY_L IXF1110 MOD_DEF_0:9 TX_DISABLE_0:9 TX_FAULT_0:9 RX_LOS_0:9 TX_FAULT_INT RX_LOS_INT MOD_DEF_INT I2C_CLK I2C_DATA_0:9 SerDes Interface Optical Module Interface LED_CLK LED_DATA LED_LATCH LED Interface SYS_RES_L CLK125 CLK50 System Interface B2585-02 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 19 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 1 4.2 Interface Signal Groups SPI4-2 Interface Signal Descriptions (Sheet 1 of 2) Signal Name TDAT15_P, TDAT15_N TDAT14_P, TDAT14_N TDAT13_P, TDAT13_N TDAT12_P, TDAT12_N TDAT11_P, TDAT11_N TDAT10_P, TDAT10_N TDAT9_P, TDAT9_N TDAT8_P, TDAT8_N TDAT7_P, TDAT7_N TDAT6_P, TDAT6_N TDAT5_P, TDAT5_N TDAT4_P, TDAT4_N TDAT3_P, TDAT3_N TDAT2_P, TDAT2_N TDAT1_P, TDAT1_N TDAT0_P, TDAT0_N TDCLK_P TDCLK_N TCTL_P TCTL_N Ball Designator G11 C9 J9 H7 E8 E9 B7 L5 C7 L8 G5 F7 G9 B5 H3 J6 D3 E4 M10 N10 H11 D9 K10 J8 E7 F9 C8 M5 C6 L7 H5 G6 H9 C5 J3 J5 Type Input Standard LVDS Signal Description Transmit Data Bus: Carries payload data and in-band control words to the IXF1110 MAC link-layer device. Internally terminated differentially with 100 . LVDS Transmit Data Clock: Clock associated with TDAT[15:0] and TCTL. Data and control lines are driven off the rising and falling edges of the clock. Internally terminated differentially with 100 . NOTE: If TDCLK is applied to the IXF1110 MAC after the device has come out of reset, the system designer must ensure the TDCLK is stable when applied. Failure to due so can result in the IXF1110 MAC training on a non-stable clock, causing DIP4 errors and data corruption. Input LVDS Transmit Control: TCTL is High when a control word is present on TDAT[15:0]. Otherwise, TCTL is Low. Internally terminated differentially with 100 . Input TSCLK C11 Output 2.5 V LVTTL TSTAT1 TSTAT0 E6 E5 Output 2.5 V LVTTL Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Transmit Status Clock: Clock associated with TSTAT [1:0]. Frequency is equal to one-quarter TDCLK. Transmit FIFO Status: Carries round-robin FIFO status information, along with associated error detection and framing. Page 20 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 1 4.2 Interface Signal Groups SPI4-2 Interface Signal Descriptions (Sheet 2 of 2) Signal Name RDAT15_P, RDAT15_N RDAT14_P, RDAT14_N RDAT13_P, RDAT13_N RDAT12_P, RDAT12_N RDAT11_P, RDAT11_N RDAT10_P, RDAT10_N RDAT9_P, RDAT9_N RDAT8_P, RDAT8_N RDAT7_P, RDAT7_N RDAT6_P, RDAT6_N RDAT5_P, RDAT5_N RDAT4_P, RDAT4_N RDAT3_P, RDAT3_N RDAT2_P, RDAT2_NRDAT1_P, RDAT1_N RDAT0_P, RDAT0_N RDCLK_P RDCLK_N RCTL_P RCTL_N Ball Designator K12 F16 E13 A13 J16 G17 D18 C16 M15 E16 L17 J18 G21 F18 B20 E19 C18 C19 H16 H18 K13 G16 E14 A14 K15 G18 E18 D16 N15 E17 L18 J19 H20 G19 C20 E20 Type Output Standard LVDS Signal Description Receive Data: Carries payload data and in-band control from the IXF1110 MAC link-layer device. Internally terminated differentially with 100 . Receive Data Clock: Clock associated with RDAT[15:0] and RCTL. Data and control lines are driven off the rising and falling edges of the clock. Output Output LVDS LVDS The frequency range is 336-400 Mhz. Frequency is always a multiplied- by-8 Version of the CLK50 reference clock. Internally terminated differentially with 100 . Receive Control: RCTL is High when a control word is present on RDAT[15:0]. Otherwise, RCTL is Low. Internally terminated differentially with 100 . RSCLK J17 Input 2.5 V LVTTL Receive Status Clock: The clock associated with RSTAT[1:0]. RSTAT1 RSTAT0 J20 L20 Input 2.5 V LVTTL Receive FIFO Status: Carries round-robin FIFO status information, along with associated error detection and framing. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 21 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 2 4.2 Interface Signal Groups SerDes Interface Signal Descriptions Signal Name Ball Designator TX_P_0, TX_N_0 TX_P_1, TX_N_1 TX_P_2, TX_N_2 TX_P_3, TX_N_3 TX_P_4, TX_N_4 TX_P_5, TX_N_5 TX_P_6, TX_N_6 TX_P_7, TX_N_7 TX_P_8, TX_N_8 TX_P_9, TX_N_9 V20 Y19 V22 Y23 AB12 AD12 AB9 AD9 T3 T5 V21 Y20 W22 Y22 AB11 AD11 AC9 AD10 U3 U5 RX_P_0, RX_N_0 RX_P_1, RX_N_1 RX_P_2, RX_N_2 RX_P_3, RX_N_3 RX_P_4, RX_N_4 RX_P_5, RX_N_5 RX_P_6, RX_N_6 RX_P_7, RX_N_7 RX_P_8, RX_N_8 RX_P_9, RX_N_9 T22 T20 U24 W24 AB13 AD13 AB16 AD16 V5 Y6 U22 U20 T24 V24 AB14 AD14 AC16 AD15 V4 Y5 Type Output Input Standard SerDes SerDes Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Signal Description Transmit Differential Output: Carries the 1.25 GHz data to the optics module. Receive Differential Input: Carries the 1.25 GHz data from the optics module. Internally terminated differentially with 100 . Page 22 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 3 4.2 Interface Signal Groups CPU Interface Signal Descriptions (Sheet 1 of 2) Signal Name Ball Designator Type Standard Signal Description UPX_ADD10 UPX_ADD9 UPX_ADD8 UPX_ADD7 UPX_ADD6 UPX_ADD5 UPX_ADD4 UPX_ADD3 UPX_ADD2 UPX_ADD1 UPX_ADD0 C2 F1 F5 C3 G1 E2 E3 H1 F3 G4 J1 Input 2.5 V CMOS Address bus: 11-bit address bus UPX_CS_L F20 Input 2.5 V CMOS Chip Select Signal: Active Low chip select UPX_DATA31 UPX_DATA30 UPX_DATA29 UPX_DATA28 UPX_DATA27 UPX_DATA26 UPX_DATA25 UPX_DATA24 UPX_DATA23 UPX_DATA22 UPX_DATA21 UPX_DATA20 UPX_DATA19 UPX_DATA18 UPX_DATA17 UPX_DATA16 UPX_DATA15 UPX_DATA14 UPX_DATA13 UPX_DATA12 UPX_DATA11 UPX_DATA10 UPX_DATA9 UPX_DATA8 UPX_DATA7 UPX_DATA6 UPX_DATA5 UPX_DATA4 UPX_DATA3 UPX_DATA2 UPX_DATA1 UPX_DATA0 C23 B22 A21 B18 A17 C17 A16 G14 E15 B16 G13 A15 A12 F14 C14 D14 D7 F11 E10 G12 A11 E12 A9 A10 A8 C13 E11 C12 A7 B9 A4 B3 Input/O utput 2.5 V CMOS Bi-directional data bus: 32-bit bi-directional data bus 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 23 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 3 4.2 Interface Signal Groups CPU Interface Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator Type Standard Signal Description UPX_WR_L A18 Input 2.5 V CMOS Write Strobe: Active Low Write strobe UPX_RD_L H14 Input 2.5 V CMOS Read Strobe: Active Low Read strobe Cycle complete indicator: Indicates that Read or Write is complete. UPX_RDY_L C22 Open Drain Output* Note: 2.5 V CMOS1 Note: An external pull-up resistor is required for proper operation. *Dual-mode I/O. Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. Table 4 Pause Control Interface Signal Descriptions Signal Name Ball Designator Type Standard Signal Description TXPAUSEFR J7 Input 2.5 V CMOS Pause Strobe: Indicates when a Pause frame is to be sent TXPAUSEADD3 TXPAUSEADD2 TXPAUSEADD1 TXPAUSEADD0 K1 J2 G2 G3 Input 2.5 V CMOS Pause Address Bus: Selects the port for the Pause frames Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 24 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 5 4.2 Interface Signal Groups Optical Module Interface Signal Descriptions (Sheet 1 of 2) Signal Name Ball Designator Type Standard Signal Description TX_FAULT_0 TX_FAULT_1 TX_FAULT_2 TX_FAULT_3 TX_FAULT_4 TX_FAULT_5 TX_FAULT_6 TX_FAULT_7 TX_FAULT_8 TX_FAULT_9 M24 V23 Y17 R15 W14 W11 W9 AC5 P8 L2 Input 2.5 V CMOS Transmitter Fault: Input used to determine when there is a optical module transmitter fault. RX_LOS_0 RX_LOS_1 RX_LOS_2 RX_LOS_3 RX_LOS_4 RX_LOS_5 RX_LOS_6 RX_LOS_7 RX_LOS_8 RX_LOS_9 L22 V17 AD18 R12 AB15 V12 Y9 AC3 T2 P2 Input 2.5 V CMOS Receiver Loss of Signal: Input used to determine when the optical module receiver loses synchronization. MOD_DEF_0 MOD_DEF_1 MOD_DEF_2 MOD_DEF_3 MOD_DEF_4 MOD_DEF_5 MOD_DEF_6 MOD_DEF_7 MOD_DEF_8 MOD_DEF_9 N24 Y21 AA16 M20 AC14 U11 T4 AB2 R7 L1 Input 2.5 V CMOS Module Definition: Input used to determine when a optical module module is present. TX_DISABLE_0 TX_DISABLE_1 TX_DISABLE_2 TX_DISABLE_3 TX_DISABLE_4 TX_DISABLE_5 TX_DISABLE_6 TX_DISABLE_7 TX_DISABLE_8 TX_DISABLE_9 K22 M22 AC22 U18 U14 AA18 U9 AA9 V7 L4 Open Drain Output* 2.5 V CMOS1 Transmitter Disable: Output used to disable a optical module transmitter. External pull-up resistor usually resident in a optical module is required for proper operation. Note: *Dual-mode I/O. Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output Transmitter Fault interrupt: Open drain output interrupt to signal a TX_FAULT condition. TX_FAULT_INT B11 Open Drain Output* 2.5 V CMOS1 Note: *Dual-mode I/O. Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 25 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 5 4.2 Interface Signal Groups Optical Module Interface Signal Descriptions (Sheet 2 of 2) Signal Name RX_LOS_INT Ball Designator Type Open Drain Output* B14 Standard Signal Description Receiver Loss of Signal Interrupt: Open drain output interrupt to signal an RX_LOS condition. 2.5 V CMOS1 *Dual-mode I/O. Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output Note: Module Definition Interrupt: Open drain output interrupt to signal a MOD_DEF condition. MOD_DEF_INT G15 Open Drain Output* 2.5 V CMOS1 Note: I2C_CLK L19 Output 2.5 V CMOS I2C Reference Clock: Clock used for I2C bus interface. I2C_DATA_0 I2C_DATA_1 I2C_DATA_2 I2C_DATA_3 I2C_DATA_4 I2C_DATA_5 I2C_DATA_6 I2C_DATA_7 I2C_DATA_8 I2C_DATA_9 G22 G23 J24 F22 E23 H24 G20 E22 G24 F24 *Dual-mode I/O. Normal operation: Open drain output Boundary Scan Mode: Standard CMOS output I2C Data Bus: Data I/O for the I2C bus interface. Input/O utput* 2.5 V CMOS1 *Dual-mode I/O. Normal operation: Input/output Boundary Scan Mode: Standard CMOS output Note: 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. Table 6 LED Interface Signal Descriptions Signal Name Table 7 Ball Designator Type Standard Signal Description LED_CLK A19 Output 2.5 V CMOS LED Clock: Clock output for the LED block. LED_DATA A20 Output 2.5 V CMOS LED Data: Data output for the LED block. LED_LATCH K18 Output 2.5 V CMOS LED Latch: Latch enable for the LED block. JTAG Interface Signal Descriptions (Sheet 1 of 2) Signal Name Ball Designator Type Standard Signal Description TCK AA24 Input 3.3 V LVTTL JTAG Test Clock: Reference clock for JTAG. TMS T16 Input 3.3 V LVTTL JTAG Test Mode Select: Selects test mode for JTAG. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 26 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 7 4.2 Interface Signal Groups JTAG Interface Signal Descriptions (Sheet 2 of 2) Signal Name Table 8 Ball Designator Standard Signal Description TDI AC18 Input 3.3 V LVTTL JTAG Test Data Input: Test data sampled with respect to the rising edge of TCK. TRST_L N18 Input 3.3 V LVTTL JTAG Test Reset: Reset input for JTAG test. TDO Y24 Output 3.3 V LVTTL JTAG Test Data Output: Test data driven with respect to the falling edge of TCK. System Interface Signal Descriptions Signal Name CLK125 Table 9 Type Ball Designator AA5 Type Input Standard Signal Description 3.3 V LVTTL 125 MHz Reference Clock: Input clock to PLL. CLK50 C21 Input 3.3 V LVTTL SPI4-2 Reference Clock: Input clock to SPI4-2 RX PLL. Input range is 42 MHz to 50 MHz. This clock multiplied by eight must equal the required RX SPI4-2 data clock frequency. SYS_RES_L Y4 Input 2.5 V CMOS System Reset: System hard reset (active Low). Power Supply Signal Descriptions (Sheet 1 of 2) Signal Name Ball Designator AVDD1P8_1 D1 E24 AVDD1P8_2 P7 V14 P18 V18 AVDD2P5_1 Y1 AVDD2P5_2 N3 V10 N22 V15 V6 P3 V11 P22 Type Standard - - 1.8 V Analog Power Supply: 1.8 V supply for analog circuits. - - 1.8 V Analog Power Supply: 1.8 V supply for analog circuits. - - 2.5 V Analog Power Supply: 2.5 V supply for analog circuits. - - 2.5 V Analog Power Supply: 2.5 V supply for analog circuits. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Signal Description Page 27 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 9 4.2 Interface Signal Groups Power Supply Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator VDD D6 D19 F21 J11 K5 L9 P9 R4 T11 W4 AA15 D10 D20 H10 J14 K8 L11 P11 R8 T14 W21 AA19 D11 E21 H15 K3 K17 L14 P14 R17 U10 AA6 AB4 D15 F4 J4 K4 K21 L16 P16 R21 U15 AA10 VDD2 B4 B17 F8 H2 J12 M9 M19 N9 N19 U2 W8 AA2 AC12 B8 B21 F12 H6 J13 M12 M23 N12 N23 U6 W12 AA23 AC13 B12 D2 F13 H19 M2 M13 N2 N13 T12 U19 W13 AC4 AC17 B13 D23 F17 H23 M6 M16 N6 N16 T13 U23 W17 AC8 AC21 GND B6 C4 D12, D22 F6 F23 H12 J10 K2 K14 K23 L10 L24 M11 M21 N14 P10 P21 R2 R10 R19 T8 T17 T23 U12, U21 V16 W6 W19 Y3 Y15 AA3 AA12 AA21 AB17 AC7 AC19 B10 D4 D13 D24 F10 G10 H13 J15 K6 K16 K24 L12 M3 M14 N4 N17 P12 P23 R3 R11 R23 T9 T18 U4 U13 V2 W2 W7 W20 Y8 Y16 AA4 AA13 AB6 AB21 AC10 AC20 B15 D5 D17 E1 F15 H4 H17 J21 K9 K19 L3 L13 M4 M17 N8 N21 P13 P24 R6 R14 R24 T10 T19 U7 U16 V3 W3 W10 W23 Y12 Y18 AA7 AA14 AB7 AB23 AC11 AD21 B19 D8 D21 F2 F19 H8 H21 J23 K11 K20 L6 L15 M8 M18 N11 P1 P15 R1 R9 R16 T7 T15 T21 U8 U17 V13 W5 W15 Y2 Y13 AA1 AA8 AA17 AB10 AC6 AC15 Type Standard - - 1.8 V Digital Power Supply: 1.8 V core supply. - - 2.5 V Digital Power Supply: 2.5 V I/O supply. - - Ground: Ground return for all signals. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Signal Description Page 28 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 10 4.2 Interface Signal Groups Unused Balls/Reserved Signal Name Ball Designator NC A5 G7 K7 M7 N20 P17 R13 T1 V8 W16 Y11 AA22 AB18 AD4 AD8 A6 G8 L21 N1 P4 P19 R18 T6 V9 W18 Y14 AB3 AB19 AD5 AD17 C10 H22 L23 N5 P5 P20 R20 U1 V19 Y7 AA11 AB5 AB20 AD6 AD19 C15 J22 M1 N7 P6 R5 R22 V1 W1 Y10 AA20 AB8 AB22 AD7 AD20 No Ball A2 A24 B24 AB24 AC24 AD22 A3 B1 C1 AC1 AD1 AD23 A22 B2 C24 AC2 AD2 AD24 A23 B23 AB1 AC23 AD3 No Pad A1 Type Standar d - - No connection. - - Balls removed from substrate. - Pad removed from substrate. Use this ball location as a key for device placement onto the PCB. - Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Signal Description Page 29 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 4.3 Ball List Tables Ball List Tables Ball list tables are provided in alphanumeric order by signal name (Table 11) and by ball location order (Table 12). Note: Cortina recommends that all unconnected balls be tied to their inactive states through external pull-ups or pull-downs. 4.3.1 Balls Listed in Alphanumeric Order by Signal Name Table 11 shows the ball locations and signal names arranged in alphanumeric order by signal name. Table 11 Ball List in Alphanumeric Order by Signal Name Signal Ball Signal AVDD1P8_1 D1 GND AVDD1P8_1 E24 AVDD1P8_2 P7 AVDD1P8_2 AVDD1P8_2 Ball Signal Ball D22 GND L15 GND D24 GND M4 GND E1 GND M8 P18 GND F2 GND M11 V6 GND F6 GND M14 AVDD1P8_2 V11 GND F10 GND M17 AVDD1P8_2 V14 GND F15 GND M21 AVDD1P8_2 V18 GND F19 GND N4 AVDD2P5_1 Y1 GND F23 GND N8 AVDD2P5_2 N3 GND H4 GND N11 AVDD2P5_2 N22 GND H8 GND N14 AVDD2P5_2 P3 GND H12 GND N17 AVDD2P5_2 P22 GND H13 GND N21 AVDD2P5_2 V10 GND H17 GND P10 AVDD2P5_2 V15 GND H21 GND P12 CLK125 AA5 GND J10 GND P13 CLK50 C21 GND J15 GND P15 GND B6 GND J23 GND R2 GND B10 GND K2 GND R6 GND B15 GND K6 GND R9 GND B19 GND K9 GND R11 GND C4 GND K11 GND R14 GND D4 GND K14 GND R16 GND D5 GND K16 GND R19 GND D8 GND K19 GND R23 GND D12 GND K23 GND T10 GND D13 GND L10 GND T15 GND D17 GND L12 GND U4 GND D21 GND L13 GND U8 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 30 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Signal GND GND GND Ball U12 U13 U17 Signal GND GND GND Ball T17 V16 AB10 Signal I2C_DATA_0 Ball G22 2 G23 2 J24 2 I C_DATA_1 I C_DATA_2 GND U21 GND T9 I C_DATA_3 F22 GND V3 GND AB7 I2C_DATA_4 E23 GND GND W2 W3 GND GND T7 P1 2 H24 2 G20 2 I C_DATA_5 I C_DATA_6 GND W6 GND M18 I C_DATA_7 E22 GND W10 GND P23 I2C_DATA_8 G24 2 GND W15 GND AB21 I C_DATA_9 F24 GND W19 GND U16 LED_CLK A19 GND W23 GND V13 LED_DATA A20 GND Y2 GND Y12 LED_LATCH K18 GND Y3 GND V2 MOD_DEF_0 N24 GND Y15 GND Y8 MOD_DEF_1 Y21 GND AA1 GND W5 MOD_DEF_2 AA16 GND AA4 GND R3 MOD_DEF_3 M20 GND AA8 GND L24 MOD_DEF_4 AC14 GND AA12 GND R24 MOD_DEF_5 U11 GND AA13 GND W20 MOD_DEF_6 T4 GND AA17 GND T18 MOD_DEF_7 AB2 GND AA21 GND AA14 MOD_DEF_8 R7 GND AC6 GND AC11 MOD_DEF_9 L1 GND AC10 GND T8 MOD_DEF_INT G15 GND AC15 GND AA7 NC H22 GND AC19 GND AA3 NC J22 GND K24 GND L3 NC A5 GND P24 GND J21 NC A6 GND AD21 GND T23 NC C10 GND T19 GND AB23 NC C15 GND Y16 GND P21 NC G7 GND Y13 GND Y18 NC G8 GND L6 GND AB17 NC K7 GND AC7 GND R10 NC M7 GND U7 GND W7 NC N7 GND M3 GND AB6 NC P5 GND K20 GND R1 NC P6 GND T21 GND G10 NC P19 L19 NC P20 GND AC20 2 I C_CLK Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 31 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Signal Ball Signal Ball Signal Ball NC R18 NC W16 RDAT3_P G21 NC T1 NC AA11 RDAT4_N J19 NC U1 NC Y11 RDAT4_P J18 NC V1 NC AD6 RDAT5_N L18 NC V8 NC N5 RDAT5_P L17 NC V19 NC N1 RDAT6_N E17 NC W1 No Ball A2 RDAT6_P E16 NC Y14 No Ball A3 RDAT7_N N15 NC AB3 No Ball A22 RDAT7_P M15 NC AB5 No Ball A23 RDAT8_N D16 NC AB20 No Ball A24 RDAT8_P C16 NC AB22 No Ball B1 RDAT9_N E18 NC AD7 No Ball B2 RDAT9_P D18 NC AD8 No Ball B23 RDAT10_N G18 NC AD17 No Ball B24 RDAT10_P G17 NC L23 No Ball C1 RDAT11_N K15 NC P17 No Ball C24 RDAT11_P J16 NC AB18 No Ball AB1 RDAT12_N A14 NC AA22 No Ball AB24 RDAT12_P A13 NC W18 No Ball AC1 RDAT13_N E14 NC Y10 No Ball AC2 RDAT13_P E13 NC Y7 No Ball AC23 RDAT14_N G16 NC AD5 No Ball AC24 RDAT14_P F16 NC T6 No Ball AD1 RDAT15_N K13 NC P4 No Ball AD2 RDAT15_P K12 NC L21 No Ball AD3 RDCLK_N C19 NC N20 No Ball AD22 RDCLK_P C18 NC AD19 No Ball AD23 RSCLK J17 NC R13 No Ball AD24 RSTAT0 L20 NC AA20 No Pad A1 RSTAT1 J20 NC V9 RCTL_N H18 RX_LOS_0 L22 NC AB8 RCTL_P H16 RX_LOS_1 V17 NC AD4 RDAT0_N E20 RX_LOS_2 AD18 NC R5 RDAT0_P E19 RX_LOS_3 R12 NC M1 RDAT1_N C20 RX_LOS_4 AB15 NC R22 RDAT1_P B20 RX_LOS_5 V12 NC R20 RDAT2_N G19 RX_LOS_6 Y9 NC AD20 RDAT2_P F18 RX_LOS_7 AC3 NC AB19 RDAT3_N H20 RX_LOS_8 T2 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 32 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Signal Ball Signal Ball Signal Ball RX_LOS_9 P2 TDAT7_N C6 TX_FAULT_1 V23 RX_LOS_INT B14 TDAT7_P C7 TX_FAULT_2 Y17 RX_N_0 U22 TDAT8_N M5 TX_FAULT_3 R15 RX_N_1 U20 TDAT8_P L5 TX_FAULT_4 W14 RX_N_2 T24 TDAT9_N C8 TX_FAULT_5 W11 RX_N_3 V24 TDAT9_P B7 TX_FAULT_6 W9 RX_N_4 AB14 TDAT10_N F9 TX_FAULT_7 AC5 RX_N_5 AD14 TDAT10_P E9 TX_FAULT_8 P8 RX_N_6 AC16 TDAT11_N E7 TX_FAULT_9 L2 RX_N_7 AD15 TDAT11_P E8 TX_FAULT_INT B11 RX_N_8 V4 TDAT12_N J8 TX_N_0 V21 RX_N_9 Y5 TDAT12_P H7 TX_N_1 Y20 RX_P_0 T22 TDAT13_N K10 TX_N_2 W22 RX_P_1 T20 TDAT13_P J9 TX_N_3 Y22 RX_P_2 U24 TDAT14_N D9 TX_N_4 AB11 RX_P_3 W24 TDAT14_P C9 TX_N_5 AD11 RX_P_4 AB13 TDAT15_N H11 TX_N_6 AC9 RX_P_5 AD13 TDAT15_P G11 TX_N_7 AD10 RX_P_6 AB16 TDAT2_N C5 TX_N_8 U3 RX_P_7 AD16 TDCLK- E4 TX_N_9 U5 RX_P_8 V5 TDCLK_P D3 TX_P_0 V20 RX_P_9 Y6 TDI AC18 TX_P_1 Y19 SYS_RES_L Y4 TDO Y24 TX_P_2 V22 TCK AA24 TMS T16 TX_P_3 Y23 TCTL_N N10 TRST_L N18 TX_P_4 AB12 TCTL_P M10 TSCLK C11 TX_P_5 AD12 TDAT0_N J5 TSTAT0 E5 TX_P_6 AB9 TDAT0_P J6 TSTAT1 E6 TX_P_7 AD9 TDAT1_N J3 TX_DISABLE_0 K22 TX_P_8 T3 TDAT1_P H3 TX_DISABLE_1 M22 TX_P_9 T5 TDAT2_P B5 TX_DISABLE_2 AC22 TXPAUSEADD0 G3 TDAT3_N H9 TX_DISABLE_3 U18 TXPAUSEADD1 G2 TDAT3_P G9 TX_DISABLE_4 U14 TXPAUSEADD2 J2 TDAT4_N G6 TX_DISABLE_5 AA18 TXPAUSEADD3 K1 TDAT4_P F7 TX_DISABLE_6 U9 TXPAUSEFR J7 TDAT5_N H5 TX_DISABLE_7 AA9 UPX_ADD0 J1 TDAT5_P G5 TX_DISABLE_8 V7 UPX_ADD2 F3 TDAT6_N L7 TX_DISABLE_9 L4 UPX_ADD3 H1 TDAT6_P L8 TX_FAULT_0 M24 UPX_ADD4 E3 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 33 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Signal Ball Signal Ball Signal Ball UPX_ADD5 E2 UPX_DATA31 C23 VDD U15 UPX_ADD6 G1 UPX_RD_L H14 VDD W4 UPX_ADD7 C3 UPX_RDY_L C22 VDD W21 UPX_ADD8 F5 UPX_WR_L A18 VDD AA6 UPX_ADD9 F1 VDD D6 VDD AA10 UPX_ADD1 G4 VDD D10 VDD AA15 UPX_ADD10 C2 VDD D11 VDD AA19 UPX_CS_L F20 VDD D15 VDD AB4 UPX_DATA0 B3 VDD D19 VDD2 B4 UPX_DATA1 A4 VDD D20 VDD2 B8 UPX_DATA2 B9 VDD E21 VDD2 B12 UPX_DATA3 A7 VDD F4 VDD2 B13 UPX_DATA4 C12 VDD F21 VDD2 B17 UPX_DATA5 E11 VDD H10 VDD2 B21 UPX_DATA6 C13 VDD H15 VDD2 D2 UPX_DATA7 A8 VDD J4 VDD2 D23 UPX_DATA8 A10 VDD J11 VDD2 F8 UPX_DATA9 A9 VDD J14 VDD2 F12 UPX_DATA10 E12 VDD K3 VDD2 F13 UPX_DATA11 A11 VDD K4 VDD2 F17 UPX_DATA12 G12 VDD K5 VDD2 H2 UPX_DATA13 E10 VDD K8 VDD2 H6 UPX_DATA14 F11 VDD K17 VDD2 H19 UPX_DATA15 D7 VDD K21 VDD2 H23 UPX_DATA16 D14 VDD L9 VDD2 J12 UPX_DATA17 C14 VDD L11 VDD2 J13 UPX_DATA18 F14 VDD L14 VDD2 M2 UPX_DATA19 A12 VDD L16 VDD2 M6 UPX_DATA20 A15 VDD P9 VDD2 M9 UPX_DATA21 G13 VDD P11 VDD2 M12 UPX_DATA22 B16 VDD P14 VDD2 M13 UPX_DATA23 E15 VDD P16 VDD2 M16 UPX_DATA24 G14 VDD R4 VDD2 M19 UPX_DATA25 A16 VDD R8 VDD2 M23 UPX_DATA26 C17 VDD R17 VDD2 N2 UPX_DATA27 A17 VDD R21 VDD2 N6 UPX_DATA28 B18 VDD T11 VDD2 N9 UPX_DATA29 A21 VDD T14 VDD2 N12 UPX_DATA30 B22 VDD U10 VDD2 N13 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 34 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Signal 4.3.2 Ball VDD2 N16 VDD2 N19 VDD2 N23 VDD2 T12 VDD2 T13 VDD2 U2 VDD2 U6 VDD2 U19 VDD2 U23 VDD2 W8 VDD2 W12 VDD2 W13 VDD2 W17 VDD2 AA2 VDD2 AA23 VDD2 AC4 VDD2 AC8 VDD2 AC12 VDD2 AC13 VDD2 AC17 VDD2 AC21 Balls Listed in Alphanumeric Order by Ball Location Table 12 shows the ball locations and signal names arranged in alphanumeric order by ball location. Note: Cortina recommends that all unconnected balls be tied to their inactive states through external pull-ups or pull-downs. Table 12 Ball List in Alphanumeric Order by Ball Location Ball Signal Ball A1 No Pad A11 A2 No Ball A3 No Ball A4 A5 Signal Ball Signal UPX_DATA11 A21 UPX_DATA29 A12 UPX_DATA19 A22 No Ball A13 RDAT12_P A23 No Ball UPX_DATA1 A14 RDAT12_N A24 No Ball NC A15 UPX_DATA20 B1 No Ball A6 NC A16 UPX_DATA25 B2 No Ball A7 UPX_DATA3 A17 UPX_DATA27 B3 UPX_DATA0 A8 UPX_DATA7 A18 UPX_WR_L B4 VDD2 A9 UPX_DATA9 A19 LED_CLK B5 TDAT2_P A10 UPX_DATA8 A20 LED_DATA B6 GND Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 35 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Ball Signal Ball Signal Ball Signal B7 TDAT9_P C22 UPX_RDY_L E13 RDAT13_P B8 VDD2 C23 UPX_DATA31 E14 RDAT13_N B9 UPX_DATA2 C24 No Ball E15 UPX_DATA23 B10 GND D1 AVDD1P8_1 E16 RDAT6_P B11 TX_FAULT_INT D2 VDD2 E17 RDAT6_N B12 VDD2 D3 TDCLK_P E18 RDAT9_N B13 VDD2 D4 GND E19 RDAT0_P B14 RX_LOS_INT D5 GND E20 RDAT0_N B15 GND D6 VDD E21 VDD B16 UPX_DATA22 D7 UPX_DATA15 E22 I2C_DATA_7 B17 VDD2 D8 GND E23 I2C_DATA_4 B18 UPX_DATA28 D9 TDAT14_N E24 AVDD1P8_1 B19 GND D10 VDD F1 UPX_ADD9 B20 RDAT1_P D11 VDD F2 GND B21 VDD2 D12 GND F3 UPX_ADD2 B22 UPX_DATA30 D13 GND F4 VDD B23 No Ball D14 UPX_DATA16 F5 UPX_ADD8 B24 No Ball D15 VDD F6 GND C1 No Ball D16 RDAT8_N F7 TDAT4_P C2 UPX_ADD10 D17 GND F8 VDD2 C3 UPX_ADD7 D18 RDAT9_P F9 TDAT10_N C4 GND D19 VDD F10 GND C5 TDAT2_N D20 VDD F11 UPX_DATA14 C6 TDAT7_N D21 GND F12 VDD2 C7 TDAT7_P D22 GND F13 VDD2 C8 TDAT9_N D23 VDD2 F14 UPX_DATA18 C9 TDAT14_P D24 GND F15 GND C10 NC E1 GND F16 RDAT14_P C11 TSCLK E2 UPX_ADD5 F17 VDD2 C12 UPX_DATA4 E3 UPX_ADD4 F18 RDAT2_P C13 UPX_DATA6 E4 TDCLK- F19 GND C14 UPX_DATA17 E5 TSTAT0 F20 UPX_CS_L C15 NC E6 TSTAT1 F21 VDD C16 RDAT8_P E7 TDAT11_N F22 I2C_DATA_3 C17 UPX_DATA26 E8 TDAT11_P F23 GND C18 RDCLK_P E9 TDAT10_P F24 I2C_DATA_9 C19 RDCLK_N E10 UPX_DATA13 G1 UPX_ADD6 C20 RDAT1_N E11 UPX_DATA5 G2 TXPAUSEADD1 C21 CLK50 E12 UPX_DATA10 G3 TXPAUSEADD0 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 36 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Ball Signal Ball Signal Ball Signal G4 UPX_ADD1 H19 VDD2 K10 TDAT13_N G5 TDAT5_P H20 RDAT3_N K11 GND G6 TDAT4_N H21 GND K12 RDAT15_P G7 NC H22 NC K13 RDAT15_N G8 NC H23 VDD2 K14 GND G9 TDAT3_P H24 I2C_DATA_5 K15 RDAT11_N G10 GND J1 UPX_ADD0 K16 GND G11 TDAT15_P J2 TXPAUSEADD2 K17 VDD G12 UPX_DATA12 J3 TDAT1_N K18 LED_LATCH G13 UPX_DATA21 J4 VDD K19 GND G14 UPX_DATA24 J5 TDAT0_N K20 GND G15 MOD_DEF_INT J6 TDAT0_P K21 VDD G16 RDAT14_N J7 TXPAUSEFR K22 TX_DISABLE_0 G17 RDAT10_P J8 TDAT12_N K23 GND G18 RDAT10_N J9 TDAT13_P K24 GND G19 RDAT2_N J10 GND L1 MOD_DEF_9 G20 I2C_DATA_6 J11 VDD L2 TX_FAULT_9 G21 RDAT3_P G22 J12 VDD2 L3 GND 2 J13 VDD2 L4 TX_DISABLE_9 2 I C_DATA_0 G23 I C_DATA_1 J14 VDD L5 TDAT8_P G24 I2C_DATA_8 J15 GND L6 GND H1 UPX_ADD3 J16 RDAT11_P L7 TDAT6_N H2 VDD2 J17 RSCLK L8 TDAT6_P H3 TDAT1_P J18 RDAT4_P L9 VDD H4 GND J19 RDAT4_N L10 GND H5 TDAT5_N J20 RSTAT1 L11 VDD H6 VDD2 J21 GND L12 GND H7 TDAT12_P J22 NC L13 GND H8 GND J23 GND L14 VDD 2 H9 TDAT3_N J24 I C_DATA_2 L15 GND H10 VDD K1 TXPAUSEADD3 L16 VDD H11 TDAT15_N K2 GND L17 RDAT5_P H12 GND K3 VDD L18 RDAT5_N H13 GND K4 VDD L19 I2C_CLK H14 UPX_RD_L K5 VDD L20 RSTAT0 H15 VDD K6 GND L21 NC H16 RCTL_P K7 NC L22 RX_LOS_0 H17 GND K8 VDD L23 NC H18 RCTL_N K9 GND L24 GND Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 37 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Ball Signal Ball Signal Ball Signal M1 NC N16 VDD2 R7 MOD_DEF_8 M2 VDD2 N17 GND R8 VDD M3 GND N18 TRST_L R9 GND M4 GND N19 VDD2 R10 GND M5 TDAT8_N N20 NC R11 GND M6 VDD2 N21 GND R12 RX_LOS_3 M7 NC N22 AVDD2P5_2 R13 NC M8 GND N23 VDD2 R14 GND M9 VDD2 N24 MOD_DEF_0 R15 TX_FAULT_3 M10 TCTL_P P1 GND R16 GND M11 GND P2 RX_LOS_9 R17 VDD M12 VDD2 P3 AVDD2P5_2 R18 NC M13 VDD2 P4 NC R19 GND M14 GND P5 NC R20 NC M15 RDAT7_P P6 NC R21 VDD M16 VDD2 P7 AVDD1P8_2 R22 NC M17 GND P8 TX_FAULT_8 R23 GND M18 GND P9 VDD R24 GND M19 VDD2 P10 GND T1 NC M20 MOD_DEF_3 P11 VDD T2 RX_LOS_8 M21 GND P12 GND T3 TX_P_8 M22 TX_DISABLE_1 P13 GND T4 MOD_DEF_6 M23 VDD2 P14 VDD T5 TX_P_9 M24 TX_FAULT_0 P15 GND T6 NC N1 NC P16 VDD T7 GND N2 VDD2 P17 NC T8 GND N3 AVDD2P5_2 P18 AVDD1P8_2 T9 GND N4 GND P19 NC T10 GND N5 NC P20 NC T11 VDD N6 VDD2 P21 GND T12 VDD2 N7 NC P22 AVDD2P5_2 T13 VDD2 N8 GND P23 GND T14 VDD N9 VDD2 P24 GND T15 GND N10 TCTL_N R1 GND T16 TMS N11 GND R2 GND T17 GND N12 VDD2 R3 GND T18 GND N13 VDD2 R4 VDD T19 GND N14 GND R5 NC T20 RX_P_1 N15 RDAT7_N R6 GND T21 GND Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 38 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Ball Signal Ball Signal Ball Signal T22 RX_P_0 V13 GND Y4 SYS_RES_L T23 GND V14 AVDD1P8_2 Y5 RX_N_9 T24 RX_N_2 V15 AVDD2P5_2 Y6 RX_P_9 U1 NC V16 GND Y7 NC U2 VDD2 V17 RX_LOS_1 Y8 GND U3 TX_N_8 V18 AVDD1P8_2 Y9 RX_LOS_6 U4 GND V19 NC Y10 NC U5 TX_N_9 V20 TX_P_0 Y11 NC U6 VDD2 V21 TX_N_0 Y12 GND U7 GND V22 TX_P_2 Y13 GND U8 GND V23 TX_FAULT_1 Y14 NC U9 TX_DISABLE_6 V24 RX_N_3 Y15 GND U10 VDD W1 NC Y16 GND U11 MOD_DEF_5 W2 GND Y17 TX_FAULT_2 U12 GND W3 GND Y18 GND U13 GND W4 VDD Y19 TX_P_1 U14 TX_DISABLE_4 W5 GND Y20 TX_N_1 U15 VDD W6 GND Y21 MOD_DEF_1 U16 GND W7 GND Y22 TX_N_3 U17 GND W8 VDD2 Y23 TX_P_3 U18 TX_DISABLE_3 W9 TX_FAULT_6 Y24 TDO U19 VDD2 W10 GND AA1 GND U20 RX_N_1 W11 TX_FAULT_5 AA2 VDD2 U21 GND W12 VDD2 AA3 GND U22 RX_N_0 W13 VDD2 AA4 GND U23 VDD2 W14 TX_FAULT_4 AA5 CLK125 U24 RX_P_2 W15 GND AA6 VDD V1 NC W16 NC AA7 GND V2 GND W17 VDD2 AA8 GND V3 GND W18 NC AA9 TX_DISABLE_7 V4 RX_N_8 W19 GND AA10 VDD V5 RX_P_8 W20 GND AA11 NC V6 AVDD1P8_2 W21 VDD AA12 GND V7 TX_DISABLE_8 W22 TX_N_2 AA13 GND V8 NC W23 GND AA14 GND V9 NC W24 RX_P_3 AA15 VDD V10 AVDD2P5_2 Y1 AVDD2P5_1 AA16 MOD_DEF_2 V11 AVDD1P8_2 Y2 GND AA17 GND V12 RX_LOS_5 Y3 GND AA18 TX_DISABLE_5 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 39 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Ball Signal Ball Signal AA19 VDD AC10 GND AA20 NC AC11 GND AA21 GND AC12 VDD2 AA22 NC AC13 VDD2 AA23 VDD2 AC14 MOD_DEF_4 AA24 TCK AC15 GND AB1 No Ball AC16 RX_N_6 AB2 MOD_DEF_7 AC17 VDD2 AB3 NC AC18 TDI AB4 VDD AC19 GND AB5 NC AC20 GND AB6 GND AC21 VDD2 AB7 GND AC22 TX_DISABLE_2 AB8 NC AC23 No Ball AB9 TX_P_6 AC24 No Ball AB10 GND AD1 No Ball AB11 TX_N_4 AD2 No Ball AB12 TX_P_4 AD3 No Ball AB13 RX_P_4 AD4 NC AB14 RX_N_4 AD5 NC AB15 RX_LOS_4 AD6 NC AB16 RX_P_6 AD7 NC AB17 GND AD8 NC AB18 NC AD9 TX_P_7 AB19 NC AD10 TX_N_7 AB20 NC AD11 TX_N_5 AB21 GND AD12 TX_P_5 AB22 NC AD13 RX_P_5 AB23 GND AD14 RX_N_5 AB24 No Ball AD15 RX_N_7 AC1 No Ball AD16 RX_P_7 AC2 No Ball AD17 NC AC3 RX_LOS_7 AD18 RX_LOS_2 AC4 VDD2 AD19 NC AC5 TX_FAULT_7 AD20 NC AC6 GND AD21 GND AC7 GND AD22 No Ball AC8 VDD2 AD23 No Ball AC9 TX_N_6 AD24 No Ball Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 40 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.0 Functional Description 5.1 Media Access Controller 5.1.1 General Description 5.0 Functional Description The IXF1110 MAC main functional block consists of a 1000 Mbps Ethernet Media Access Controller (MAC), supporting the following features: * 10-bit interface to the SerDes block * 1000 Mbps full-duplex operation * Independent enable/disable of any port * Detection of lengtherror of overly large packets * RMON statistics and error counters * Cyclic Redundancy Check (CRC) calculation and error detection * Programmable options: -- Filter packets with errors -- Filter, broadcast, multicast, and unicast address packets -- Automatically pad transmitted packets less than the minimum frame size * Compliance with IEEE 802.3x Standard for Flow Control (symmetric pause capability) The MAC is fully integrated, designed for use with Ethernet 802.3 Frame types, and is compliant with all of the required IEEE 802.3 MAC requirements. The MAC adds preamble and Start-of-Frame Delimiter (SFD) to all frames sent to it (transmit path) and removes preamble and SFD on all frames received by it (receive path). A CRC check is also applied to all transmit and receive packets. Packets with a bad CRC are marked, counted in the statistics block, and may be optionally dropped or sent to the SPI4-2 interface. 5.1.2 MAC Functions Section 5.1.2.1, Padding of Undersized Frames on Transmit, on page 41 through Section 5.1.2.3, Filtering of Receive Packets, on page 42 cover the MAC functions. 5.1.2.1 Padding of Undersized Frames on Transmit The padding feature allows Ethernet frames smaller than 64 bytes to be transferred across the SPI4-2 interface and automatically padded up to 64 bytes by the MAC. This feature is enabled by setting bit 7 of the Diverse Config ($ Port_Index + 0x18), on page 129. Note: If frames under 64 bytes are sent to the MAC, the padding feature must be enabled for proper operation. A 9-byte packet is the minimum size packet that can be padded up to 64 bytes. Packets under 9 bytes are not padded and are automatically dropped. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 41 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1.2.2 5.1 Media Access Controller Automatic CRC Generation The Automatic CRC Generation is used in conjunction with the padding feature to generate and append a correct CRC to any incoming frame from the SPI4-2 interface. This feature is enabled by setting bit 6 of the Diverse Config ($ Port_Index + 0x18), on page 129. Note: When padding of undersized frames on transmit is enabled, the automatic CRC generation must be enabled for proper operation of the IXF1110 MAC. 5.1.2.3 Filtering of Receive Packets This feature allows the MAC to filter receive packets under various conditions and drop the packets via an interaction with the Receive FIFO control. Note: Jumbo frames (1519 - 9600 bytes) matching the filter conditions, which would cause the frame to be dropped by the RX FIFO, are not dropped. Instead, jumbo frames that are expected to be dropped by the RX FIFO, based on the filter settings in the RX Packet Filter Control ($ Port_Index + 0x19), on page 131, are sent across the SPI4-2 interface as an EOP abort frame. Jumbo frames matching the filter conditions are not counted in the RX FIFO Number of Frames Removed Register because they are not removed by the RX FIFO. Only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in the RX Packet Filter Control ($ Port_Index + 0x19), on page 131 are actually dropped by the RX FIFO and counted in the RX FIFO Number of Frames Removed. 5.1.2.3.1 Filter on Unicast Packet Match This feature is enabled when bit 0 of the RX Packet Filter Control Register = 1. Any frame received in this mode containing a Unicast Destination Address that does not match the Station Address is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable Register = 1. Otherwise, all unicast frames are sent to the SPI4-2 interface, but with an EOP Abort code to the switch or Network Processor. Note: The VLAN filter overrides the unicast filter. Thus, a VLAN frame cannot be filtered based on the unicast address. 5.1.2.3.2 Filter on Multicast Packet Match This feature is enabled when bit 1 of the RX Packet Filter Control Register = 1. Any frame received in this mode containing a Multicast Destination Address which does not match the Port Multicast Address is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable register = 1. Otherwise, all multicast frames are sent to the SPI4-2 interface, but with an EOP Abort code to the switch or Network Processor. 5.1.2.3.3 Filter Broadcast Packets This feature is enabled when bit 2 of the RX Packet Filter Control ($ Port_Index + 0x19) = 1. Any broadcast frame received in this mode is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable Register = 1. Otherwise, all broadcast frames are sent to the SPI4-2 interface, but with an EOP Abort code to the switch or Network Processor. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 42 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1.2.3.4 5.1 Media Access Controller Filter VLAN Packets This feature is enabled when bit 3 of the RX Packet Filter Control ($ Port_Index + 0x19) = 1. VLAN frames received in this mode are marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable Register = 1. Otherwise, all VLAN frames are sent to the SPI4-2 interface, but with an EOP Abort code to the switch or Network Processor. 5.1.2.3.5 Filter PAUSE Packets This feature is enabled when bit 4 of the RX Packet Filter Control ($ Port_Index + 0x19) = 0. PAUSE frames received in this mode are marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the RX FIFO Errored Frame Drop Enable ($ 0x59F) = 1. Otherwise, all PAUSE frames are sent to the SPI4-2 interface. Table 13 5.1.2.3.6 Pause Packets Drop Enable Behavior Pause Frame Pass Frame Drop En Actions 1 0 Packets are passed to the SPI4-2 interface. They are not marked as bad and are sent to the switch or Network Processor. 0 0 Packets are marked as bad but not dropped in the RX FIFO. These packets are sent to the SPI4-2 interface, but with an EOP Abort code to the switch or Network Processor. 1 1 Packets are not marked as bad and sent to the switch or Network Processor, regardless of the Frame Drop En setting. 0 1 PAUSE Packets are marked as bad, are dropped in the RX FIFO, and never appear at the SPI4-2 interface. Filter CRC Errored Packets This feature is enabled when bit 5 of the RX Packet Filter Control ($ Port_Index + 0x19) = 0. Frames received with an errored CRC are marked as bad frames and may optionally be dropped in the RX FIFO. Otherwise, the frames are sent to the SPI4-2 interface and may be dropped by the switch or system controller (see CRC Errored Packets Drop Enable Behavior, on page 43). Note: When the CRC Error Pass Filter bit = 0 (RX Packet Filter Control ($ Port_Index + 0x19), on page 131), it takes precedence over the other filter bits. Any packet (Pause, Unicast, Multicast or Broadcast packet) with a CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0. Table 14 CRC Errored Packets Drop Enable Behavior CRC Errored PASS Frame Drop En Actions 1 0 Packets are passed to the SPI4-2 interface. They are not marked as bad and are sent to the switch or Network Processor. 0 0 Packets are marked as bad but not dropped in the RX FIFO. These packets are sent to the SPI4-2 interface, but with an EOP Abort code to the switch or Network Processor. 1 1 Packets are not marked as bad and are sent to the switch or Network Processor regardless of the Frame Drop En setting. 0 1 CRC errored packets are marked as bad, dropped in the RX FIFO, and never appear at the SPI4-2 interface. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 43 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1.3 5.1 Media Access Controller Flow Control Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link partner take a temporary "Pause" in packet transmission. This allows the requesting network node to prevent FIFO overruns and dropped packets, by managing incoming traffic to fit its available memory. The temporary pause allows the device to process packets already received or in transit, thus freeing up the FIFO space allocated to those packets. The IXF1110 MAC implements the IEEE 802.3x standard RX FIFO threshold-based Flow Control. When appropriately programmed, the MAC can both generate and respond to IEEE standard pause frames. The IXF1110 MAC also supports externally triggered flow control through the Transmit Pause Control interface. 5.1.3.1 802.3x Flow Control (Full-Duplex Operation) The IEEE 802.3x standard identifies four options related to system flow control: * No Pause * Symmetric Pause (both directions) * Asymmetric Pause (Receive direction only) * Asymmetric Pause (Transmit direction only) The IXF1110 MAC supports all four options on a per-port basis. Bits 1:0 of the FC Enable ($ Port_Index + 0x12), on page 127 provide programmable control for enabling or disabling flow control in each direction independently. The IEEE 802.3x flow control mechanism is accomplished within the MAC sublayer, and is based on RX FIFO thresholds called watermarks. The RX FIFO level rises and falls as packets are received and processed. When the RX FIFO reaches a watermark (either exceeding a High or dropping below a Low after exceeding a High), the IXF1110 MAC control sublayer signals an internal state machine to transmit a PAUSE frame. The FIFOs automatically generate PAUSE frames (also called control frames) to initiate the following: * Halt the link partner when the High watermark is reached. * Restart the link partner when the data stored in the FIFO falls below the Low watermark. Figure 5 illustrates the IEEE 802.3 FIFO flow control functions. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 44 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 5 5.1 Media Access Controller Packet Buffering FIFO MDI SPI4-2 Interface High Water Mark TX FIFO Data Flow TX Side MAC Data Flow RX Side MAC MAC Transfer Threshold * Low Water Mark High Water Mark RX FIFO Low Water Mark RX FIFO High 802.3 Flow control TxPauseFr (External strobe) 5.1.3.1.1 802.3x Pause Frame Generation Pause Frame Format PAUSE frames are MAC control frames that are padded to the minimum size (64 bytes). Figure 6 and Figure 6 illustrate the frame format and contents. Figure 6 Ethernet Frame Format Number of bytes Note: !""# $ % ! &"# Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 45 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 7 5.1 Media Access Controller PAUSE Frame Format 46 Number of bytes 7 Preamble 1 6 S F D DA* or 01-80C2-0000-01 6 SA 2 2 2 42 4 88-08 Pause Opcode (00-01) Pause Length Pad (with 0s) FCS 64 Bytes Note: In the IXF1110 architecture, the TX block of the MAC sets this as the pause multicast address. The RX interface of the MAC will process this as the pause multicast or the MAC address. B3426-02 An IEEE 802.3 MAC PAUSE frame is identified by detecting all of the following: * OpCode of 00-01 * Length/Type field of 88-08 * DA matching the unique multicast address (01-80-C2-00-00-01) XOFF. A PAUSE frame informs the link partner to halt transmission for a specified length of time. The PauseLength octets specify the duration of the no-transmit period. If this time is greater than zero, the link partner must stop sending any further packets until this time has elapsed. This is referred to as XOFF. XON. The MAC continues to transmit PAUSE frames with the specified Pause Length as long as the FIFO level exceeds the threshold. If the FIFO level falls below the threshold before the Pause Length time expires, the MAC sends another PAUSE frame with the Pause Length time specified as zero. This is referred to as XON and informs the link partner to resume normal transmission of packets. 5.1.3.1.2 Pause Settings The MAC must send PAUSE frames repeatedly to maintain the link partner in a Pause state. The following two inter-related variables control this process: * Pause Length is the amount of time, measured in multiples of 512 bit times, that the MAC requests the link partner to halt transmission for. * Pause Threshold is the amount of time, measured in multiples of 512 bit times, prior to the expiration of the Pause Length that the MAC transmits another Pause frame to maintain the link partner in the pause state. The transmitted Pause Length in the IXF1110 MAC is set by the FC TX Timer Value ($ Port_Index + 0x07), on page 125. The IXF1110 MAC PAUSE frame transmission interval is set by the Pause Threshold ($ Port_Index + 0x0E), on page 127. 5.1.3.1.3 Response to Received PAUSE Command Frames When Flow Control is enabled in the receive direction (bit 0 in the FC Enable ($ Port_Index + 0x12), on page 127), the IXF1110 MAC responds to PAUSE Command frames received from the link partner as follows: Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 46 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1 Media Access Controller 1. The IXF1110 MAC checks the entire frame to verify that it is a valid PAUSE control frame addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE 802.3, Annex 31B) or has a Destinations Address matching the address programmed in the Station Address Low ($ Port_Index + 0x00), on page 125 through Station Address High ($ Port_Index + 0x01), on page 125. 2. If the PAUSE frame is valid, the transmit side of the IXF1110 MAC pauses for the required number of PAUSE Quanta, as specified in IEEE 802.3, Clause 31. 3. PAUSE does not begin until completion of the frame currently being transmitted. The IXF1110 MAC response to valid received PAUSE frames is independent of the PAUSE frame filter settings. Refer to Section 5.1.2.3.5, Filter PAUSE Packets, on page 43 for additional details. 5.1.3.1.4 Transmit Pause Control Interface The Transmit Pause Control interface allows an external device to trigger the generation of pause frames. The Transmit Pause Control interface is completely asynchronous. It consists of four address signals (TXPAUSEADD[3:0]) and a strobe signal (TXPAUSEFR). The required address for this interface operation is placed on the TXPAUSEADD[3:0] signals and the TXPAUSEFR is pulsed High and returned Low. Refer to Figure 8, Transmit Pause Control Interface, on page 48 and Transmit Pause Control Interface Parameters, on page 108. Table 15, Valid Decodes for TXPAUSEADD[3:0], on page 47 shows the valid decodes for the TXPAUSEADD[3:0] signals. Figure 8, Transmit Pause Control Interface, on page 48 illustrates the transmit pause control interface. Note: Flow control must be enabled in the FC Enable ($ Port_Index + 0x12), on page 127 for Transmit Pause Control interface operation. Note: There are two additional decodes provided that allow the user to generate either an XOFF frame or XON frame from all ports simultaneously. The default pause quanta for each port is held by the FC TX Timer Value ($ Port_Index + 0x07), on page 125). The default value of this register is 0x05E after reset is applied. Table 15 Valid Decodes for TXPAUSEADD[3:0] (Sheet 1 of 2) TXPAUSEADD[3:0] TX Pause Control Interface Operation 0x0 Transmits a PAUSE frame on every port with a pause_time = ZERO (XON) (Cancels all previous pause commands). 0x1 Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed in the port 0 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0x2 Transmits a PAUSE frame on port 1 with pause_time equal to the value programmed in the port 1 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0x3 Transmits a PAUSE frame on port 2 with pause_time equal to the value programmed in the port 2 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0x4 Transmits a PAUSE frame on port 3 with pause_time equal to the value programmed in the port 3 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0x5 Transmits a PAUSE frame on port 4 with pause_time equal to the value programmed in the port 4 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0x6 Transmits a PAUSE frame on port 5 with pause_time equal to the value programmed in the port 5 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0x7 Transmits a PAUSE frame on port 6 with pause_time equal to the value programmed in the port 6 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 47 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 15 5.1 Media Access Controller Valid Decodes for TXPAUSEADD[3:0] (Sheet 2 of 2) TXPAUSEADD[3:0] Figure 8 TX Pause Control Interface Operation 0x8 Transmits a PAUSE frame on port 7 with pause_time equal to the value programmed in the port 7 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0x9 Transmits a PAUSE frame on port 8 with pause_time equal to the value programmed in the port 8 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0xA Transmits a PAUSE frame on port 9 with pause_time equal to the value programmed in the port 9 FC TX Timer Value ($ Port_Index + 0x07) (XOFF). 0xB - 0XE Reserved 0xF Transmits a PAUSE frame on every port with pause_time equal to the value programmed in the FC TX Timer Value ($ Port_Index + 0x07) for each port (XOFF). Transmit Pause Control Interface TXPAUSEFR TXPAUSEADD0 TXPAUSEADD1 TXPAUSEADD2 TXPAUSEADD3 This example shows the following conditions: Strobe 1: Port 0: Transmit Pause Packet (XOFF) Strobe 2: All Ports: Transmit Pause Packet with pause_time = 0 (XON) Strobe 3: Port 3: Transmit Pause Packet (XOFF) 5.1.4 B3366-01 Fiber Operation The data path in the MAC is an internal 10-bit interface, as described in the IEEE 802.3z Standard. It is connected directly to an internal SerDes block for Serialization/Deserialization and transmission/reception on the fiber medium to/from the link partner. Note: The MAC contains all the PCS (8B/10B encoding and 10B/8B decoding) required to encode and decode the data. The MAC also supports auto-negotiation per the IEEE 802.3z Standard via access to the TX Config Word ($ Port_Index + 0x17), on page 129, RX Config Word ($ Port_Index + 0x16), on page 128, and Diverse Config Registers (see Diverse Config ($ Port_Index + 0x18), on page 129. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 48 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1 Media Access Controller By default, IXF1110 MAC auto-negotiation is disabled by Register bit 5 (AN_enable) of the Diverse Config ($ Port_Index + 0x18), on page 129. When auto-negotiation is disabled, the IXF1110 MAC can operate in forced mode, which is 1000 Mbps full duplex only. This is equivalent to entering the state AN_DISABLE_LINK_OK as described in Figure 37-6 of IEEE 802.3. The IXF1110 MAC can pass packets when auto-negotiation is disabled only when the internal Synchronization State Machine indicates that the sync_status is OK as described in Figure 36-9 of IEEE 802.3. Note: Packet IPG must contain a minimum of three consecutive /I1/ or /I2/ ordered sets per IEEE 802.3 for correct operation. Note: The IXF1110 MAC treats the K28.1 code word as an unknown control word; therefore, it should not be used. 5.1.5 Auto-Negotiation Auto-negotiation is carried out by an internal state machine within the MAC block in the IXF1110 MAC. The IXF1110 MAC is fully IEEE 802.3z standard compliant. The following three registers are involved in this auto-negotiation process: RX Config Word TX Config Word, and Diverse Config: * The RX Config Word ($ Port_Index + 0x16), on page 128 performs the operation of auto-negotiation base page ability. * The TX Config Word ($ Port_Index + 0x17), on page 129 performs the operation of auto-negotiation advertisement. * The Diverse Config ($ Port_Index + 0x18), on page 129 enables auto-negotiation. The TX Config Word ($ Port_Index + 0x17) must be written to program the modes advertised. The Diverse Config ($ Port_Index + 0x18) bit 5 (AN_enable) must be written to enable auto-negotiation. The RX Config Word ($ Port_Index + 0x16) bit 21 (AN_complete) must be polled to determine when auto-negotiation is complete. The following MAC registers must be programmed to match the results upon completion: * Link LED: Link LED Enable ($ 0x502), on page 141 * Flow Control: If the link partner does not support flow control, the FC Enable ($ Port_Index + 0x12), on page 127 must be updated to reflect this change. Note: In auto-negotiation mode, the TX SPI4-2 status bus (TSTAT[1:0]) is held in the SATISFIED state until auto-negotiation completes and a valid link is established. This prevents the TX FIFO from being filled prior to transmission of packets. 5.1.5.1 Determining If Link Is Established in Auto-Negotiation Mode A valid link is established when the (AN_complete) bit is set and the RX_Sync bit reports synchronization has occurred. Both register bits are located in the RX Config Word ($ Port_Index + 0x16), on page 128. If the link goes down after auto-negotiation is completed, RX_Sync indicates that a loss of synchronization occurred. The IXF1110 MAC restarts auto-negotiation and attempts to re-establish a link. Once a link has been re-established, the AN_complete bit is set and the RX_sync bit shows that synchronization has occurred. To manually restart auto-negotiation, bit 5 of the Diverse Config ($ Port_Index + 0x18), on page 129 (AN_enable) must be de-asserted, then re-asserted. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 49 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1.6 5.1 Media Access Controller Forced Mode Operation The fiber operation of the MAC can be forced to operated at 1000 Mbps, full duplex without completion of the auto negotiation function. In this mode, the receive path of the MAC must achieve synchronization with the link partner. Once this has been achieved, the transmit path of the MAC will be enabled to allow data transmission, which is known as "forced mode" operation. Forced mode is limited to operation with a link partner that operates with a full-duplex link at a speed of 1000 Mbps. Forced mode is enabled by Register bit 5 (AN_enable) in the Diverse Config ($ Port_Index + 0x18), on page 129. By default, the IXF1110 MAC is set to forced mode operation. Note: In forced mode, the TX SPI4-2 status bus (TSTAT[1:0]) is held in the SATISFIED state until sync_status is OK. This prevents the TX FIFO from being filled prior to transmission of packets. 5.1.6.1 Determining If Link Is Established in Forced Mode When the IXF1110 MAC is in forced mode operation, the RX Config Word ($ Port_Index + 0x16), on page 128 bit 20 RX Sync indicates when synchronization has occurred and valid link is established. Note: The Rx Sync bit indicates a loss of synchronization when the link is down. 5.1.7 Jumbo Packet Support The IXF1110 MAC supports the concept of jumbo frames. The jumbo frame length is dependent on the application, and the IXF1110 MAC design has been optimized for 9.6 KB jumbo frame length. Lengths larger than this can be programmed, but will limit system performance. The value programmed into the Max Frame Size Register (Addr: Port_Index + 0x0F) determines the maximum length frame size the MAC can receive or transmit without activating any error counters, and without truncation. The Max Frame Size Register (Addr: Port_Index + 0x0F) bits 13:0 set the frame length. The default value programmed into this register is 0x05EE (1518). The value is internally adjusted by +4 if the frame has a VLAN tag. The overall programmable maximum is 0x3FFF or 16383 bytes. The register should be programmed to 0x2667 for the 9.6 KB length jumbo frame for which the IXF1110 MAC is optimized. The RMON counters are also affected for jumbo frame support as follows: RX Statistics: * RXOctetsTotalOK (Addr: Port_Index + 0x20) * RXPkts1519toMaxOctets (Addr: Port_Index + 0x2B) * RXFCSErrors (Addr: Port_Index + 0x2C) * RXDataError (Addr: Port_Index + 0x02E) * RXAlignErrors (Addr: Port_Index + 0x2F) * RXLongErrors (Addr: Port_Index + 0x30) * RXJabberErrors (Addr: Port_Index + 0x31) * RXVeryLongErrors (Addr: Port_Index + 0x34) TX Statistics: Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 50 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1 Media Access Controller * TXOctetsTotalOK (Addr: Port_Index + 0x40) * TxPkts1519toMaxOctets (Addr: Port_Index + 0x4B) * TxExcessiveLengthDrop (Addr: Port_Index + 0x53) * TXCRCError (Addr: Port_Index + 0x56) The IXF1110 MAC checks the CRC for all legal length jumbo frames (frames between 1519 and the Max Frame Size). On transmission, the MAC can be programmed to append the CRC to the frame or check the CRC and increment the appropriate counter. On reception, the MAC transmits these frames across the SPI4-2 interface (jumbo frames with a bad CRC cannot be dropped and are sent across the SPI4-2 interface). If the receive frame has a bad CRC, the appropriate counter is incremented and the EOP Abort code is set in the SPI4-2 control word. Jumbo frames also impact flow control. The maximum frame size needs to be taken into account when determining the FIFO watermarks. The current transmission must be completed before a Pause frame can be transmitted (needed when the receiver FIFO high watermark has been exceeded). If the current transmission is a jumbo frame, the delay may be significant and increase data loss due to insufficient available FIFO space. 5.1.8 RMON Statistics Support 5.1.8.1 RMON Statistics The IXF1110 MAC supplies RMON statistics via the CPU interface. These statistics are available in the form of counter values that can be accessed at specific addresses in the IXF1110 MAC memory map. Once read, these counters automatically reset and begin counting from zero. A separate set of RMON statistics is available for each MAC device in the IXF1110 MAC. Implementation of the RMON Statistics block is similar to the functionality provided by existing Cortina switch and router products. This implementation allows the IXF1110 MAC to provide all of the RMON Statistics group as defined by RFC2819. The IXF1110 MAC supports the RMON RFC2819 Group 1 statistics counters. Table 16 notes the differences and additional statistics registers supported by the IXF1110 MAC that are outside the scope of the RMON RFC2819 document. Table 16 RMON Additional Statistics Registers (Sheet 1 of 2) RMON Ethernet Statistics Group 1 Statistics Type IXF1110 MAC Equivalent Statistics Type Definition of RMON Versus IXF1110 MAC Documentation etherStatsIndex Integer32 N/A N/A N/A etherStatsDataSource Object Identifier N/A N/A N/A etherStatsDropEvents Counter32 RX/TX FIFO Number of Frames Removed Counter32 See Table note 1. 1. The RMON spec requires that this is, "The total number of events where packets were dropped by the probe due to a lack of resources. Note that this number is not necessarily the number of packets dropped; it is the number of times this condition has been detected." The RX/TX FIFO Number of Frames Removed Register in the IXF1110 MAC supports this and will increment when either an RX or TX FIFO has over flowed. If any IXF1110 MAC programmable packet filtering is enabled, the RX/TX Number of Frames Removed Register increments with every frame removed in addition to the existing frames counted due to FIFO overflow. 2. TheIXF1110 MAC has an extra counter RX/TXUCPkts that can be used. 3. The IXF1110 MAC has an extra counter RX/TXPktstoMaxOctets that can be used in addition to the RMON stats. This is required to accommodate the Jumbo packet frames requirement. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 51 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 16 5.1 Media Access Controller RMON Additional Statistics Registers (Sheet 2 of 2) RMON Ethernet Statistics Group 1 Statistics Type IXF1110 MAC Equivalent Statistics Type Definition of RMON Versus IXF1110 MAC Documentation Counter32 Note: The IXF1110 MAC has two counters for RX and TX that use different naming conventions for total Octets and Octets bad. These counters need to be combined to meet the RMON spec. Counter32 RXOctetsTotalOK RXOctetsBad TXOctetsTotalOK TXOctetsBad etherStatsPkts Counter32 RX/TXUCPkts RX/TXBCPkts RX/TXMCPkts Counter32 Note: The IXF1110 MAC has three counters for etherStatsPkts that need to be combined to give the total packets as defined by the RMON spec. etherStatsBroadcastPkts Counter32 RX/TXBCPkts Counter32 OK etherStatsMulticastPkts Counter32 RX/TXMCPkts Counter32 See table note 2. etherStatsCRCAlignErrors Counter32 RXAlignErrors RXFCSErrors TXCRCError Counter32 Note: The IXF1110 MAC has two counters for alignment and CRC errors for the RX side only. The IXF1110 MAC has CRCError for the TX side. etherStatsOversizePkts Counter32 RXLongErrors TXExcessiveLengthDrop Counter32 OK etherStatsJabbers Counter32 RXJabberErrors Counter32 OK etherStatsCollisions Counter32 TXSingleCollisions TXMultipleCollisions TXLateCollisions TXTotalCollisions Counter32 OK Note: Registers exist on the TX side but should not increment since the IXF1110 MAC only supports full-duplex. etherStatsPkts64Octets Counter32 RX/TXPkts64Octets Counter32 OK etherStatsPkts65to127Octets Counter32 RX/TXPkts65to127Octets Counter32 OK etherStatsPkts128to255Octets Counter32 RX/TXPkts128to255Octets Counter32 OK etherStatsPkts256to511Octets Counter32 RX/TXPkts256to511Octets Counter32 OK etherStatsPkts512to1023Octets Counter32 RX/TXPkts512to1023Octets Counter32 OK etherStatsPkts1024to1518Octets Counter32 RX/TXPkts1024to1518Octet s Counter32 See table note 3. etherStatsOwner Owner String N/A N/A N/A etherStatsStatus Entry Status N/A N/A N/A etherStatsOctets 1. The RMON spec requires that this is, "The total number of events where packets were dropped by the probe due to a lack of resources. Note that this number is not necessarily the number of packets dropped; it is the number of times this condition has been detected." The RX/TX FIFO Number of Frames Removed Register in the IXF1110 MAC supports this and will increment when either an RX or TX FIFO has over flowed. If any IXF1110 MAC programmable packet filtering is enabled, the RX/TX Number of Frames Removed Register increments with every frame removed in addition to the existing frames counted due to FIFO overflow. 2. TheIXF1110 MAC has an extra counter RX/TXUCPkts that can be used. 3. The IXF1110 MAC has an extra counter RX/TXPktstoMaxOctets that can be used in addition to the RMON stats. This is required to accommodate the Jumbo packet frames requirement. 5.1.8.2 Conventions The following conventions are used throughout the RMON MIB and its companion documents. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 52 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2 System Packet Interface Level 4 Phase 2 * Good Packets: Error-free packets that have a valid frame length. For example, on Ethernet, good packets are error-free packets that are between 64 octets long and 1518 octets long. They follow the form defined in IEEE 802.3, Section 3.2. * Bad Packets: Packets that have proper framing and are therefore recognized as packets, but contain errors within the packet or have an invalid length. For example, on Ethernet, bad packets have a valid preamble and SFD, but have a bad CRC, or are either shorter than 64 octets or longer than 1518 octets. 5.1.8.3 Additional Statistics The following additional IXF1110 MAC registers support features not documented in RMON: * MAC (flow) control frames * VLAN tagged frames * Sequence errors * Symbol errors * CRC errors These additional counters allow for additional differentiation over and above standard RMON probes. Note: A packet transfer with an invalid 10-bit symbol will not always update the statistics registers correctly. * Behavior: The IXF1110 MAC 8B10B decoder substitutes a valid code word octet in its place. The packet transfer is aborted and marked as bad. The new internal length of the packet is equal to the byte position where the invalid symbol was. No packet fragments are seen at the next packet transfer. * Issue: If the invalid 10-bit code is inserted in a byte position of 64 or greater, expected RX statistics are reported. However, if the invalid code is inserted in a byte position of less than 64, expected RX statistics are not stored. 5.2 System Packet Interface Level 4 Phase 2 The System Packet Interface Level 4 Phase 2 (SPI4-2) provides a high-speed connection to a network processor or an ASIC. The interface implemented on the IXF1110 MAC operates at data rates up to 12.8 Gbps and supports up to ten 1 Gbps MAC ports. The data path is 16 lanes wide in each direction, with each lane operating from 640 Mbps up to 800 Mbps. Port addressing, start/end packet control, and error control codes are all transferred "in-band" on the data bus. In-band addressing supports up to 10 ports. Separate transmit and receive FIFO status lines are used for flow control. By keeping the FIFO status Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 53 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2 System Packet Interface Level 4 Phase 2 information out-of-band, the transmit and receive interfaces may be de-coupled to operate independently. Figure 9 and Table 17 provide an overview of the IXF1110 MAC SPI4-2 interface. Figure 9 SPI4-2 Interfacing with the Network Processor or Forwarding Engine Transmit FIFO Status/ SPI-4.2 Flow Control Signals TSCLK TSTAT[1:0] Transmit Data Control TSCLK TSTAT[1:0] TDCLK_P/N TDCLK_P/N TDAT[15:0]_P/N TDAT[15:0]_P/N TCTL_P/N TCTL_P/N Receive FIFO Status/ Flow Control IXF1x10 MAC RSCLK RSTAT[1:0] Network Processor or Forwarding Engine with SPI4-2 Interface RSCLK Receive Data Control RSTAT[1:0] RDCLK_P/N RDCLK_P/N RDAT[15:0]_P/N RDAT[15:0]_P/N RCTL_P/N RCTL_P/N B3432-01 Table 17 SPI4-2 Interface Signal Summary (Sheet 1 of 2) Signal Name Signal Description Transmit TDAT[15:0]_P/N Transmit Data Bus: Differential LVDS lines used to carry payload data and in-band control words. Internally terminated differentially with 100 . Transmit Data Clock: Differential LVDS clock associated with TDAT[15:0] and TCTL. Data and control lines are driven off the rising and falling edges of the clock. TDCLK_P/N Internally terminated differentially with 100 . NOTE: If TDCLK is applied to the IXF1110 MAC after the device has come out of reset, the system designer must ensure the TDCLK is stable when applied. Failure to due so can result in the IXF1110 MAC training on a non-stable clock, causing DIP4 errors and data corruption. TCTL_P/N Transmit Control: Differential LVDS lines used to indicate when a control word is being transmitted. A High level indicates a control word present on TDAT[15:0]. Internally terminated differentially with 100 . TSCLK Transmit Status Clock: LVTTL clock associated with TSTAT [1:0]. Frequency is equal to one-quarter TDCLK. TSTAT1, TSTAT0 Transmit FIFO Status: LVTTL lines used to carry round-robin FIFO status information, along with associated error detection and framing. Receive RDAT[15:0]_P/N Receive Data: Carries payload data and in-band control from the IXF1110 MAC link-layer device. Internally terminated differentially with 100 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 54 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 17 5.2 System Packet Interface Level 4 Phase 2 SPI4-2 Interface Signal Summary (Sheet 2 of 2) Signal Name RDCLK_P/N Signal Description Receive Data Clock: Differential LVDS clock associated with RDAT[15:0] and RCTL. Data and control lines are driven off the rising and falling edges of the clock. Internally terminated differentially with 100 RCTL_P/N Receive Control: RCTL is High when a control word is present on RDAT[15:0]. Otherwise, RCTL is Low. Internally terminated differentially with 100 5.2.1 RSCLK Receive Status Clock: LVTTL clock associated with RSTAT[1:0]. RSTAT1, RSTAT0 Receive FIFO Status: LVTTL lines used to carry round-robin FIFO status information, along with associated error detection and framing. Data Path Transfer of complete packets or shorter bursts is controlled by the programmed MaxBurst1 or MaxBurst2 in conjunction with the FIFO status bus. The maximum configured payload data transfer size must be a multiple of 16 bytes. Control words are inserted between burst transfers only. Once a transfer begins, data words are sent uninterrupted until an end-of-packet, or until a multiple of 16 bytes is reached as programmed in MaxBurst1 and MaxBurst2. The interval between the end of a given transfer and the next payload control word (marking the start of another transfer) consists of zero or more idle control words and/or training patterns. Note: The system designer should be aware that the MAC Transfer Threshold Register must be set to a value which exceeds the MaxBurst1 setting of the network processor or ASIC. Otherwise, a TX FIFO under-run may result. The minimum and maximum supported packet lengths are determined by the application. Because the IXF1110 MAC is targeted at the Ethernet environment, the minimum frame size is 64 bytes and the maximum frame size is 1522 bytes for VLAN packets (1518 bytes for non-VLAN packets). For larger frames, adjust the value of Max Frame Size ($ Port_Index + 0x0F), on page 127. For ease of implementation, successive start-of-packets must occur not less than eight cycles apart, where a cycle is one control or data word. The gap between shorter packets is filled with idle control words. Note: Data packets with frame lengths less than 64 bytes should not be transferred to the IXF1110 MAC unless packet padding is enabled. If this rule is disregarded, unwanted fragments may be generated on the network at the SerDes interface. Figure 10 on page 56 shows cycle-by-cycle behavior of the data path for valid state transitions. The states correspond to the type of words transferred on the data path. Transitions from the "Data Burst" state (to "Payload Control" or "Idle Control") are possible only on the integer multiples of eight cycles (corresponding to multiples of 16-byte segmentations) or upon end-of-packet. A data burst must immediately follow a payload control word on the next cycle. Arcs not annotated correspond to single cycles. In the IXF1110 MAC, the RX FIFO Status channel operates in a "pessimistic mode." It is termed as pessimistic because it has the longest latency and largest impact on usable bandwidth. However, as a DIP-2 check error is a rare event, there will be no `real world' effect on bandwidth utilization and no possibility of data loss. For example, if there is a DIP-2 check error found, all previously granted credits are cancelled and the internal status for each port is set to SATISFIED. Any current data burst in transmission is completed. No Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 55 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2 System Packet Interface Level 4 Phase 2 new credits are granted until a complete FIFO status cycle has been received and validated by a correct DIP-2 check. This is the only method of operation that can eliminate the possibility of an overrun in the link partner device. Figure 10 Data Path State 5.2.1.1 Control Words A common control word format is used in both the transmit and receive interfaces. Table 18 describes the fields in the control word. When inserted in the data path, the control word is aligned such that its MSB is sent on the MSB of the transmit or receive data lines. A payload control word that separates two adjacent burst transfers contains status information pertaining to the previous transfer and the following transfer. Table 19 provides a list of control-word definitions. Table 18 Control Word Format (Sheet 1 of 2) Bit Position Label Description Control Word Type. 15 Type Set to either of the following values: 0 = Idle or training control word 1 = Payload control word (payload transfer will immediately follow the control word) End-of-Packet (EOP) Status. 14:13 EOPS Set to the following values according to the status of the immediately preceding payload transfer: 00 = Not an EOP. 01 = EOP Abort (application-specific error condition 10 = EOP Normal termination, 2 bytes valid 11 = EOP Normal termination, 1 byte valid EOPS is valid in the first control word following a burst transfer. It is ignored and set to "00" otherwise. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 56 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 18 5.2 System Packet Interface Level 4 Phase 2 Control Word Format (Continued) (Sheet 2 of 2) Bit Position Label Description Start-of-Packet. 12 SOP Set to 1 if the payload transfer immediately following the control word corresponds to the start of a packet. Set to 0 otherwise. Set to 0 in all idle and training control words Port Address. 11:4 ADR 3:0 DIP-4 8-bit port address of the payload data transfer immediately following the control word. None of the addresses are reserved (all are available for payload transfer). Set to all zeroes in all idle control words Set to all ones in all training control words 4-bit Diagonal Interleaved Parity. Table 19 4-bit odd parity computed over the current control word and the immediately preceding data words (if any) following the last control word Control Word Definitions Bit [15:12] Next Word Status Prior Word Status Meaning 0 0000 Idle Continued Idle, not EOP, training control word 1 0001 Reserved Reserved Reserved 2 0010 Idle EOP w/abort Idle, Abort last packet 3 0011 Reserved Reserved Reserved 4 0100 Idle EOP w/ 2 bytes Idle, EOP with 2 bytes valid 5 0101 Reserved Reserved Reserved 6 0110 Idle EOP w/ 1 byte Idle, EOP with 1byte valid 7 0111 Reserved Reserved Reserved 8 1000 Valid None Valid, no SOP, no EOP 9 1001 Valid/SOP None Valid, SOP, no EOP A 1010 Valid EOP w/abort Valid, no SOP, abort B 1011 Valid/SOP EOP w/abort Valid, SOP, abort C 1100 Valid EOP w/ 2 bytes Valid, no SOP, EOP with 2 bytes valid D 1101 Valid EOP w/ 2 bytes Valid, SOP, EOP with 2 bytes valid E 1110 Valid EOP w/ 1 byte Valid, no SOP, EOP with 1byte valid F 1111 Valid EOP w/ 1 byte Valid, SOP, EOP with 1byte valid The SPI4-2 specification details all available Payload Control Words and should be used to reference the specific meaning of each. The IXF1110 MAC supports all required functions per this specification. However, there are various specifics in the way certain Control Words affect the balance of the IXF1110 MAC operation, such as how the device deals with EOP Aborts. The SPI4-2 specification allows the EOP Abort Payload Control word, which signals that the data associated with a particular frame is errored and should be dropped, or errored and dropped by the far-end link partner. In the IXF1110 MAC, all TX SPI4-2 transfers that end with an EOP Abort code have the TX SerDes CRC corrupted. This is true regardless of the MAC configuration. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 57 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2 System Packet Interface Level 4 Phase 2 Figure 11 shows per-port state transitions at control-word boundaries. At any given time, a port may be active (sending data), paused (not sending data but pending the completion of an outstanding packet), or inactive (not sending data, no outstanding packet). Figure 11 Per-Port State Diagram with Transitions at Control Words PC[n] & EOP & SOP PC[n] & -SOP PC[n] & SOP PORT [n] INACTIVE (IC I PC[-n]) & EOP PORT [n] ACTIVE (IC I PC[-n]) & -EOP PORT [n] PAUSED PC[n] & -EOP & -SOP Key: IC: PC[n]: PC[-n): SOP: -SOP: EOP: -EOP: &: I: 5.2.1.2 Idle Control Word Payload Control Word for port n Payload Control Word for a port other than port n Start-of-Packet in Payload Control Word No Start-of-Packet in Payload Control Word End-of-:acket in Control Word No End-of-Packet in Control Word AND OR EOP Abort EOP Aborts is an End-of-Packet (EOP) termination that is sent out of the IXF1110 MAC SPI4-2 to tell the upstream SPI4-2 device that a packet is bad. EOP Abort packets are sent by the IXF1110 MAC under the following conditions: * Standard size (64-1518 byte) packets that are filtered (RX Packet Filter Control ($ Port_Index + 0x19), on page 131) but not dropped due to the setting in RX FIFO Errored Frame Drop Enable ($ 0x59F), on page 150 (see Section 5.1.2.3, Filtering of Receive Packets, on page 42). * Standard size (64-1518 byte) packets that are greater in size than the setting in Max Frame Size ($ Port_Index + 0x0F), on page 127 and are not dropped due to the setting in RX FIFO Errored Frame Drop Enable ($ 0x59F), on page 150. * Jumbo frames that meet the filter conditions set in RX Packet Filter Control ($ Port_Index + 0x19), on page 131 or are above Max Frame Size ($ Port_Index + 0x0F), on page 127. * RX FIFO overflows. * Packets received with /V/ error codes on the SerDes interface that are not dropped due to settings in RX FIFO Errored Frame Drop Enable ($ 0x59F), on page 150. * Runt Packets (under 64 bytes) received that are not dropped due to the setting in RX FIFO Errored Frame Drop Enable ($ 0x59F), on page 150. Note: EOP Abort packets sent out on the RX SPI4-2 may have the packet size modified. When an EOP abort packet is received on the TX SPI4-2, the IXF1110 MAC sends the packet out to the SerDes interface with an invalid CRC and is recorded in the TX statistics as a CRC error. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 58 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2.1.3 5.2 System Packet Interface Level 4 Phase 2 DIP4 Figure 12 shows the range over which the Diagonal Interleaved Parity (DIP-4) parity bits are computed. A functional description of calculating the DIP-4 code is given as follows. Assume that the stream of 16-bit data words are arranged as shown in Figure 13 (MSB at the left most column, time moving downward). (The first word received is at the top of the figure; the last word is at the bottom of the figure.) The parity bits are generated by summing diagonally (in the control word, the space occupied by the DIP-4 code (bits a, b, c, d) is set to all 1s during encoding). The first 16-bit result is split into two bytes, which are added to each other modulo-2 to produce an 8-bit result. The 8-bit result is then divided into two 4-bit nibbles, which are added to each other modulo-2 to produce the final DIP-4 code. The procedure described applies to either parity generation on the Rx path or to check parity on the Tx path. Figure 12 DIP-4 Calculation Boundaries Payload Control Control Control Payload Control DIP-4 Codewords A9039-01 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 59 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 13 5.2 System Packet Interface Level 4 Phase 2 DIP-4 Calculation Algorithm 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 1 0 1 1 w x y z 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 to 2 1st SPI-4 Phase II data word of incoming burst 2 0 0 0 0 1 0 1 0 1 1 1 1 0 0 0 0 to 3 2nd SPI-4 Phase II data word of incoming burst 3 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 to 4 3rd SPI-4 Phase II data word of incoming burst 4 0 1 1 1 0 0 1 0 0 0 1 1 1 1 1 0 to 5 4th SPI-4 Phase II data word of incoming burst 5 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 to 6 5th SPI-4 Phase II data word of incoming burst 6 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 to 7 6th SPI-4 Phase II data word of incoming burst 7 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 to 8 7th SPI-4 Phase II data word of incoming burst 8 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 to 9 8th SPI-4 Phase II data word of incoming burst 9 1 1 1 1 0 0 0 0 1 0 0 0 a b c d 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 control word: not included in parity calculations below control word: included in parity calculations (contains the results of parity for the 8 SPI-4 Phase II data words above and this control word) 16-bit parity sum (DIP16[15:0]) a, b, c and d are all set to 1 during encoding. 1 1 0 0 1 0 0 1 1 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 3 2 1 0 Each bit of this 16-bit parity sum is the result of a XOR operation along the corresponding dashed line. 8-bit parity sum DIP4 parity bits (DIP4[3:0]) DIP4[3] = DIP16[15] DIP16[11] DIP16[7] DIP16[3] DIP4[2] = DIP16[14] DIP16[10] DIP16[6] DIP16[2] DIP4[1] = DIP16[13] DIP16[9] DIP16[5] DIP16[1] DIP4[0] = DIP16[12] DIP16[8] DIP16[4] DIP16[0] A9040-01 5.2.2 Start-Up Parameters 5.2.2.1 CALENDAR_LEN CALENDAR_LEN specifies the length of each calendar sequence. As the IXF1110 MAC is a 10-port device, CALENDAR_LEN is fixed at 10 for both TX and RX data paths. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 60 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2.2.2 5.2 System Packet Interface Level 4 Phase 2 CALENDAR_M CALENDAR_M specifies the number of times the calendar port status sequence is repeated between the framing and DIP2 cycle of the calendar sequence. In the IXF1110 MAC, the TX path CALENDAR_M is fixed at 1; thus, the port status for ports 0 - 9 will be transmitted only once between the framing and DIP2 cycle of the calendar sequence. In the IXF1110 MAC, the RX path CALENDAR_M is also fixed at 1. Thus, the status for port 0-9 must only be sent once between framing and DIP2. Therefore, the value of both Tx and RX CALENDAR_M parameters is always fixed a 1. 5.2.2.3 DIP2_Thr DIP2_Thr is a parameter specifying the number of consecutive correct DIP2s required by the RX SPI4-2 to validate a calendar sequence and therefore terminate sending training sequences. In SPI4-2 RX Calendar ($ 0x702), on page 164, bits 19 to 16 specify this parameter. The default value for DIP2_Thr is 1. 5.2.2.4 Loss_Of_Sync Loss_of_Sync is a parameter specifying the number of consecutive framing calendar cycles required to indicate a loss of synchronization and therefore restart training sequences. In SPI4-2 RX Calendar ($ 0x702), on page 164, bits 11 to 8 specify this parameter. The default value for Loss_Of_Sync is three. 5.2.2.5 DATA_MAX_T DATA_MAX_T is an RX SPI4-2 parameter specifying the interval between transmission of periodic training sequences. In SPI4-2 RX Training ($ 0x701), on page 163, bits 15 to 0 specify this parameter. The default value for DATA_MAX_T is 0x0000, which disables periodic training sequence transmission. 5.2.2.6 REP_T REP_T is an RX SPI4-2 parameter specifying the number of repetitions of the training sequence to be scheduled every DATA_MAX_T interval. In SPI4-2 RX Training ($ 0x701), on page 163, bits 23 to 16 specify this parameter. The default value for REP_T is 0x00. 5.2.2.7 DIP4_UnLock DIP4_UnLock is a TX SPI4-2 parameter specifying the number of consecutive incorrect DIP4 fields to be detected in order to declare loss of synchronization and drive TSTAT[1:0] bus with framing. In SPI4-2 TX Synchronization ($ 0x703), on page 165, bits 15 to 8 specify this parameter. The default value for DIP4_UnLock is 0x4. 5.2.2.8 DIP4_Lock DIP4_Lock is a TX SPI4-2 parameter specifying the number of consecutive correct DIP4 fields to be detected in order to declare synchronization achieved and enable the calendar sequence. In SPI4-2 TX Synchronization ($ 0x703), on page 165, bits 7 to 0 specify this parameter. The default value for DIP4_Lock is 0x20. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 61 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2.2.9 5.2 System Packet Interface Level 4 Phase 2 MaxBurst1 MaxBurst1 is an RX SPI4-2 parameter specifying the maximum number of 16 byte blocks that may be transmitted when the associated FIFO status indicates "starving". Bits 24 to 16 of the SPI4-2 RX Burst Size Register specify this parameter. The default value for MaxBurst1 is 0x006, indicating a MaxBurst1 of 96 bytes [see SPI4-2 RX Burst Size ($ 0x700), on page 162]. 5.2.2.10 MaxBurst2 MaxBurst2 is an RX SPI4-2 parameter specifying the maximum number of 16 byte blocks that may be transmitted when the associated FIFO status indicates "hungry". Bits 8 to 0 of the SPI4-2 RX Burst Size Register specify this parameter. The default value for MaxBurst2 is 0x002, indicating a MaxBurst2 of 32 bytes (see SPI4-2 RX Burst Size ($ 0x700), on page 162). 5.2.3 Dynamic Phase Alignment Training Sequence (Data Path De-skew) 5.2.3.1 Training at Start-up The SPI4-2 Specification states that on power-up or after a reset, the training sequence (as defined in the SPI4-2 Specification) is sent indefinitely by the source side until it receives valid FIFO status on the FIFO bus. The specification also states that it is possible for the bus de-skew to be completed after one training sequence takes place. It is unlikely that the bus can be de-skewed in a single training sequence because of the presence of both random and deterministic jitter. The only way to account for the random element is to determine an average over repeated training sequences. Since the required number of repeats is dependent on several characteristics of the system in which the IXF1110 MAC is being used, power on training (or training following loss of synchronization) will continue until synchronization is achieved and the calendar is provisioned. The length of power on training will not be a fixed number of repeats. The number of training sequence repeats could be fairly large (16, 32, or 64). If this is necessary every time training is required, a significant use of interface bandwidth is needed just to train and de-skew the data path. This is only done at power-up or reset for an optimal starting point interface. After this, periodic training provides a better adjustment and a substantially lower bandwidth overhead. 5.2.3.2 Periodic Training A scheduled training sequence is sent at least once every pre-configured bounded interval (DATA_MAX_T) on both the transmit and receive paths. These training sequences are used by the receiving end of each interface for de-skewing bit arrival times on the data and control lines. The sequence allows the receiving end to correct for relative skew difference of up to +/- 1 bit time. The training sequence consists of one (1) idle control word followed by one or more repetitions of a 20- word training pattern consisting of 10 (repeated) training-control words followed by 10 (repeated) training-data words. The initial idle control word removes dependencies of the DIP-4 in the training control words from preceding data words. Assuming a maximum of +/- bit time alignment jitter on each line, and a maximum of +/- bit time relative skew between lines, there are at least eight bit times when a receiver can detect a training control word prior to de-skew. The training data word is chosen to be orthogonal to the training control word. In the absence of bit errors in the training pattern, a receiver should be able successfully to de-skew the data and control Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 62 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2 System Packet Interface Level 4 Phase 2 lines with one training pattern. The sending side of the data path on both the transmit and receive interfaces must schedule the training sequence at least once every DATA_MAX_T cycles. Note: DATA_MAX_T may be set to zero, disabling periodic training on the interface (see SPI4-2 RX Training ($ 0x701), on page 163). This is done when a system shows very little drift during normal operation, and no fine-grain correction on an on-going basis is needed. This allows the maximum possible bandwidth for data transfer. The transmit and receive interface training sequences are scheduled independently. 5.2.3.3 Training in a Practical Implementation The OIF Standard states that it should be possible to train and de-skew the data input in a single training cycle. However, from the research carried out and the variances in jitter and skew due to board layout and clock tolerance issues, some sort of averaging over several repeated training patterns is required to reliably determine the optimal point at which to capture the incoming data. This is true for both static alignment and dynamic phase alignment. Therefore, several training patterns are required for an average. The more training patterns, the more accurate the average. The de-skew circuit in the IXF1110 MAC uses dynamic phase alignment with a typical averaging requirement of 32 training patterns required to deliver a reliable result. During power-on training, an unlimited number of training cycles is sent by the data sourcing device. (The standard states that training must be sourced until a calendar has been provisioned.) In the IXF1110 MAC, the de-skew circuit waits until completion of its programmed average over the training patterns, ensuring that the required number of good DIP-4s is seen. Only then is a calendar provisioned. During periodic training, it is important to ensure that the training result is no less accurate than that already used for the initial decision during power-on training. Thus, a similar number of training cycles must be averaged over (32). This could make the overhead associated with periodic training large if it is required to be carried out too often. We therefore recommend that periodic training be scheduled infrequently (DATA_MAX_T = a large number) and that the number of repetitions of training be = 32(). 5.2.4 FIFO Status Channel FIFO status information is sent periodically over the TSTAT link from the IXF1110 MAC to the upper layer processor device, and over the RSTAT link from the upper layer processor to the IXF1110 MAC. The status channels operate independently. Figure 14 shows the operation of the FIFO status channel. The sending side of the FIFO status channel is initially in the DISABLE state and sends the "1 1" pattern repeatedly. When FIFO status transmission is enabled, there is a transition to the SYNC state and the "1 1" framing pattern is sent. FIFO status words are then sent according to the calendar sequence, repeating the sequence CALENDAR_M times, followed by the DIP-2 code. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 63 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 14 5.2 System Packet Interface Level 4 Phase 2 FIFO Status State Diagram DIP-2 SYNC 11 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Enable Disable Disable 11 The FIFO status of each port is encoded in a 2-bit data structure, which is defined in FIFO Status Format, on page 66. The most significant bit of each port status is sent over TSTAT[1]/RSTAT[1] and the least significant bit is sent over TSTAT[0]/RSTAT[0]. The "1 1" pattern is reserved for In-band framing, which must be sent once prior to the start of the FIFO status sequence. Immediately before the "1 1" framing pattern, a DIP-2 odd parity checksum is sent at the end of each complete sequence. The DIP-2 code is computed diagonally over TSTAT[1]/RSTAT[1] and TSTAT[0]/RSTAT[0] for all preceding FIFO status indications sent after the last "1 1" framing pattern, as shown in Figure 15, Example of DIP-2 Encoding, on page 65. The first word is at the top of the figure and the last word is at the bottom. The parity bits are computed by summing diagonally. Bits a and b in line 9 correspond to the space occupied by the DIP-2 parity bits and are set to 1 during encoding. The "1 1" framing pattern is not included in the parity calculation. The procedure described applies to either parity generation on the egress path or to check parity on the ingress path. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 64 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 15 5.2 System Packet Interface Level 4 Phase 2 Example of DIP-2 Encoding 1 0 1 1 1 0 to 2 1st Status Word 2 0 0 to 3 2nd Status Word 3 1 0 to 4 3rd Status Word 4 0 0 to 5 4th Status Word 5 0 0 to 6 5th Status Word 6 0 0 to 7 6th Status Word 7 1 0 to 8 7th Status Word 8 0 1 to 9 8th Status Word 9 0 1 a b Framing Pattern (not included parity in calculations) DIP2 Parity Bits DIP2 Parity Bits (DIP2[1:0]) a and b are set to 1 during enccoding When the parity bits mimic the "1 1" pattern, the receiving end still frames successfully by syncing onto the last cycle in a repeated "1 1" pattern, and by making use of the configured sequence length when searching for the framing pattern. To permit more efficient FIFO utilization, the MaxBurst1 and MaxBurst2 credits are granted and consumed in increments of 16-byte blocks. For any given port, these credits correspond to the most recently received FIFO status. They are not cumulative and supersede previously granted credits for the given port. A burst transfer shorter than 16 bytes (for example, an end-of-packet fragment) consumes an entire 16-byte credit. A continuous stream of repeated "1 1" framing patterns indicates a disabled status link. For example, it may be sent to indicate that the data path de-skew is not yet completed or confirmed. When a repeated "1 1" pattern is detected, all outstanding credits are cancelled and set to zero. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 65 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 20 5.2 System Packet Interface Level 4 Phase 2 FIFO Status Format MSB LSB Description 1 1 Reserved for framing or to indicate a disabled status link. 1 0 SATISFIED: Indicates that the corresponding port's FIFO is almost full. When SATISFIED is received, only transfers using the remaining previously granted 16-byte blocks (if any) may be sent to the corresponding port until the next status update. No additional transfers to that port are permitted while SATISFIED is indicated. 0 1 HUNGRY: When HUNGRY is received, transfers for up to MaxBurst2 16-byte blocks, or the remainder of what was previously granted (whatever is greater), may be sent to the corresponding port until the next status update. 0 0 STARVING: Indicates that buffer underflow is imminent in the corresponding PHY port. When STARVING is received, transfers for up to MaxBurst1 16-byte blocks may be sent to the corresponding port until the next status update The indicated FIFO status is based on the latest available information. A STARVING indication provides additional feedback information, so that transfers are scheduled accordingly. Applications that do not distinguish between HUNGRY and STARVING may only examine the most significant FIFO status bit. Note: If a port is disabled on the IXF1110 MAC, FIFO status for the port is set to SATISFIED to avoid the possibility of any data being sent to it by the controlling device. This applies to the IXF1110 MAC transmit path. Upon reset, the FIFOs in the data path receiver are emptied, and any outstanding credits are cleared in the data path transmitter. After reset, and before active traffic is generated, the data transmitter sends continuous training patterns. Transmission of the training patterns continues until valid information is received on the FIFO Status channel. The receiver ignores all incoming data until it has observed the training pattern and acquired synchronization with the data. Synchronization may be declared after a provisional number of consecutive correct DIP-4 code words is seen. Loss of synchronization may be reported after a provisional number of consecutive DIP-4 code words is detected. [For details, see SPI4-2 TX Synchronization ($ 0x703), on page 165.] The DIP-4 thresholds are programmable. However, there is a potential issue with the possibility of a given link showing DIP-4 errors that may never lose synchronization and re-train to fix the issue. This would mean an on-going and potentially significant loss of data on the link affecting all ports transferring data at that time. This issue may be seen in the following two instances: * During training (most likely periodic training) * During data transfers where each of the data transfers (MaxBurst1 or MaxBurst2) are separated by more than one idle control word The mechanism for both issues is the same because data will not change during a repeated period of the same control word being transmitted on the link. If there have been some consecutive DIP-4 errors, they will be incremented towards the Loss-of-Sync threshold. This is most likely to occur from a path requiring de-skew. If either a stream of idles or training control words follow the burst and the DIP-4 associated with each of the words is checked, only the first one and the last one will be seen as invalid. Any other control words in the middle will be seen as having a valid DIP-4 and will reset the Loss-of-Sync threshold counter back to zero. In order to avoid this, the IXF1110 MAC has altered the way in which the check is done for idle control words and training control words. We now only validate the first occurrence of the DIP-4 in both training control words and idle control words for correctness. We do still Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 66 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.3 SerDes Interface check each of the words but only use the first occurrence to clear the DIP-4 error counter. Any DIP-4 error in any of these words is still counted towards the Loss-of-Sync threshold counter. It is now impossible to mask the DIP-4 error on our interface. 5.2.5 DC Parameters For DC parameters on the SPI4-2 interface, please refer to Table 36 on page 104 and Table 37 on page 104. 5.3 SerDes Interface 5.3.1 Introduction The IXF1110 MAC has ten integrated Serializer/Deserializer (SerDes) devices that allow direct connection to optical modules. Each SerDes interface is fully compliant with the relevant IEEE 802.3 Specifications, including auto-negotiation (see Section 5.1.4, Fiber Operation, on page 48. Each port is also compliant with and supports the requirements of the Small Form Factor Pluggable (SFP) Multi-Source Agreement (MSA), see Section 5.4, Optical Module Interface, on page 70. The following sections describe the operations supported by each SerDes interface, the configurable options, and register bits that control these options. (A full list of the register addresses and full bit definitions are found in the Register Map (SerDes Block Register Map, on page 124). 5.3.2 Features The SerDes cores are designed to operate in point-to-point data transmission applications. While the core can be used across various media types, such as PCB or backplanes, it is configured specifically for use in 1000BASE-X Ethernet fiber applications in the IXF1110 MAC. The following features are supported. * 10-bit data path, which connects to the output/input of the 8B/10B encoder/decoder PCS that resides in the MAC controller * Data frequency of 1.25 GHz * Low power: <200 mW per SerDes port * Asynchronous clock data recovery 5.3.3 Functional Description The SerDes transmit interface sends serialized data at 1.25 GHz. The interface is differential with two pins for transmit operation. The transmit interface is designed to operate in a 100 differential environment and all the terminations are included on the device. The outputs are high speed SerDes and AC coupling is recommended for this interface to ensure that the correct input bias current is supplied at the receiver. The SerDes receive interface receives serialized data at 1.25 GHz. The interface is differential with two pins for the receive operation. The equalizer receives a differential signal that is equalized for the assumed media channel. The SerDes transmit and receive interfaces are designed to operate within a 100 differential environment and all terminations are included on the device. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 67 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.3.3.1 5.3 SerDes Interface Transmitter Operational Overview The transmit section of the IXF1110 MAC has to serialize the Ten Bit Interface (TBI) data from the IXF1110 MAC section and outputs this data at 1.25 GHz differential signal levels. The 1.25 GHz differential SerDes signals are compliant with the Small Form Factor Pluggable (SFP) Multi-Source Agreement (MSA). The transmitter section takes the contents of the data register within the MAC and synchronously transfers the data out, ten bits at a time - Least Significant Bit (LSB) first, followed by the next Most Significant Bit (MSB). When these ten bits have been serialized and transmitted, the next word of 10-bit data from the MAC is ready to be serialized for transmission. The data is transmitted by the high-speed current mode differential SerDes output stage using an internal 1.25 GHz clock generated from the 125 MHz clock input. Figure 16 Transmitter Concept Pseudorandom code generator Pattern recognition logic LBERROR x Latch Mux Mux TD0:TD9 Latch Select Driver/ Equalizer TXxDP/TXxON 8-/10-Bit Register LBENABLEx Latch Counter PLL Note: PLL is shared across the four links DLCKx TXDATAx TXBYPASS 5.3.3.2 B3377-01 Transmitter Programmable Driver-Power Levels The IXF1110 MAC SerDes core has programmable transmitter power levels to enhance usability in any given application.The SerDes Registers are programmable to allow adjustment of the transmit core driver output power. When driving a 100 differential terminated network, these output power settings effectively establish the differential voltage swings at the driver output. The (Register) allows the selection of 4 discrete power settings. The selected power setting of these inputs is applied to each of the transmit cores drivers on a per-port basis. Table 17, SPI4-2 Interface Signal Summary, on page 54 lists the Normalized power setting of the transmit drivers as a function of the Driver Power Control inputs. The normalized current Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 68 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.3 SerDes Interface setting is 10 mA which corresponds to the normalized power setting of 1.0. This is the default setting of the IXF1110 MAC SerDes interface. Other values listed in the Normalized Driver Power Setting column are multiples of 10 mA. For example, with inputs at 1110, the driver power is 0.5 x 10 mA = 5 mA. Table 21 SerDes Driver TX Power Levels DRVPWRx[3] DRVPWRx[2 ] DRVPWRx[1] DRVPWRx[0] Normalized Driver Power Setting Driver Power 0 0 1 1 1.33 13.3 mA 1 0 1 1 2.0 20 mA 1 1 0 1 1.0 10 mA 1 1 1 0 0.5 5 mA Note: 5.3.3.3 All other values are reserved. Receiver Operational Overview The receiver structure performs Clock and Data Recovery (CDR) on the incoming serial data stream. The quality of this operation is a dominant factor for the Bit Error Rate (BER) system performance. Feed forward and feedback controls are combined in one receiver architecture for enhanced performance. The data is over-sampled and a digital circuit detects the edge position in the data stream. A signal is not generated if an edge is not found. A feedback loop takes care of low-frequency jitter phenomenon of unlimited amplitude, while a feed forward section suppresses high-frequency jitter having limited amplitude. The static edge position is held at a constant position in the over-sampled by a constant adjustment of the sampling phases with the early and late signals. Figure 17 Receiver Concept RXxIP/RXxIN Receiver Pseudorandom code generator Sample latches Mux Pattern recognition logic LBERRORx Selector LEWRAPx Digital data detection Digital edge detection PLL RD0:RD9 Shift Register 8-/10-Bit Register Early/late gate Note: PLL is shared across the four links TXxDP/TXxON RG Counter AND DLCKx DATASYNC RXDATAx B3378-01 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 69 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.3.3.4 5.4 Optical Module Interface Selective Power-Down The IXF1110 MAC offers the ability to selectively power-down any of the SerDes TX or RX ports that are not being used. This is done via Section Table 107, SerDes TX and RX Power-Down Ports 0-9 ($ 0x787), on page 166. 5.3.4 Timing and Electrical Characteristics For timing and electrical characteristics for the IXF1110 MAC, see Figure 41, SerDes Timing, on page 112, Table 46, Transmitter Characteristics, on page 113 and Table 47, Receiver Characteristics, on page 113. 5.4 Optical Module Interface 5.4.1 Introduction This section describes the connection of the IXF1110 MAC ports to an optical module, and the connections supported for correct operation are detailed. The registers used to write control and read status information are documented in Section 8.5.9, Optical Module Interface Block Register Overview, on page 166). The optical module interface allows the IXF1110 MAC a seamless connection to the Small Form Factor Optical Modules (SFP) that form the system's physical media connection, eliminating the need for any FPGAs or CPUs to process data. All required information of the optical modules is available to the system CPU through the IXF1110 MAC CPU interface, leading to a more integrated, reliable, and cost-effective system. 5.4.2 Supported Optical Module Interface Signals For optical module interface operation, three supported signal subgroups are required, allowing a more explicit definition of each function and implementation. The three subgroups are as follows: * High-Speed Serial Interface * Low-Speed Status Signaling Interface * I2C Module Configuration Interface Table 22 provides descriptions for IXF1110 MAC-to-SFP optical module connection pins. Table 22 IXF1110 MAC-to-SFP Connections (Sheet 1 of 2) IXF1110 MAC Pin Names SFP Module Pin Name Description Notes Transmit Data, Differential SerDes Output from the IXF1110 MAC Receive Data, Differential SerDes Input to the IXF1110 MAC Output from the IXF1110 MAC TX_9:0_P TD+ TX_9:0_N TD- RX_9:0_P RD+ RX_9:0_N RD- I2C_CLK MOD-DEF1 I2C_CLK Output from IXF1110 MAC (SCL) I2C_DATA_9:0 MOD-DEF2 I2C_DATA I/O (SDA) Input/Output MOD-DEF0 MOD_DEF(0) should be TTL Low level during normal operation. Input to the IXF1110 MAC MOD_DEF_9:0 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 70 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 22 5.4 Optical Module Interface IXF1110 MAC-to-SFP Connections (Sheet 2 of 2) IXF1110 MAC Pin Names SFP Module Pin Name Description Notes TX_DISABLE_9:0 TX DISABLE Transmitter Disable, Logic High, Open collector compatible Output from the IXF1110 MAC TX_FAULT_9:0 TX FAULT Transmitter Fault, Logic High, Open collector compatible Input to the IXF1110 MAC RX_LOS_9:0 LOS Receiver Loss of Signal, Logic High, Open collector compatible Input to the IXF1110 MAC 5.4.3 Functional Descriptions 5.4.3.1 High-Speed Serial Interface These signals are responsible for transfer of the actual data at 1.25 Gbps. The data is 8B/10B encoded and transmitted differentially at SerDes levels per the required specifications. The signals required to implement the high-speed serial interface are: * TX_9:0_P * TX_9:0_N * RX_9:0_P * RX_9:0_N 5.4.3.2 Low-Speed Status Signaling Interface The following low-speed signals indicate the state of the line via the optical module: * MOD_DEF_9:0 * TX_FAULT_9:0 * RX_LOS_9:0 * TX_DISABLE_9:0 * MOD_DEF_Int * TX_FAULT_Int * RX_LOS_Int 5.4.3.2.1 MOD_DEF_9:0 These signals are direct inputs to the IXF1110 MAC and are pulled to a logic Low level during normal operation, indicating that a module is present for each port, respectively. If a module is not present, a logic High is received, which is achieved by an external pull-up resistor at the IXF1110 MAC pad. The status of each bit (one for each port) is found in bits 9:0 of the Optical Module Status Register (refer to Table 108, Optical Module Status Ports 0-9 ($ 0x799), on page 166). Any change in the state of these bits causes a logic Low level on the MOD_DEF_Int output if this operation is enabled. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 71 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.4.3.2.2 5.4 Optical Module Interface TX_FAULT_9:0 These 10 pins are inputs to the IXF1110 MAC. These signals are pulled to a logic Low level by the optical module during normal operation, which indicates no fault condition exists. If a fault is present, a logic High is received via the use of an external pull-up resistor at the IXF1110 MAC pad. The status of each bit (one for each port) can be found in bits 19:10 of the Optical Module Status Register (see Table 108, Optical Module Status Ports 0-9 ($ 0x799), on page 166). Any change in the state of these bits causes a logic Low level on the TX_FAULT_Int output if this operation is enabled. 5.4.3.2.3 RX_LOS_9:0 These 10 pins are inputs to the IXF1110 MAC. During normal operation, these signals are pulled to a logic Low level by the optical module, which indicates that no Loss-of-Signal exists. If a Loss-of-Signal occurs, a logic High is received on these inputs via the use of an external pull-up resistor at the IXF1110 MAC pad. The status of each bit (one for each port) is found in Optical Module Status Ports 0-9 ($ 0x799), on page 166 bits 29:20. Any change in the state of these bits causes a logic Low level on the RX_LOS_Int output if this operation is enabled. 5.4.3.2.4 TX_DISABLE_0:9 These 10 pins are outputs from the IXF1110 MAC. During normal operation, these signals are pulled to a logic Low level by the IXF1110 MAC, indicating that the optical module transmitter is enabled. If the optical module transmitter is disabled, these signals are switched to a logic High level. On the IXF1110 MAC, these outputs are open-drain types and pulled up by the 4.7k to 10k pull-up resistor at the optical module. Each of these signals is controlled via Optical Module Control Ports 0-9 ($ 0x79A), on page 167 bits 9:0, respectively. 5.4.3.2.5 MOD_DEF_INT MOD_DEF_Int is a single output, open-drain type signal, and is active Low. A change in state of any of the MOD_DEF_9:0 inputs causes this signal to switch Low and remain in this state until a Read of the Optical Module Status Ports 0-9 ($ 0x799), on page 166 takes place. The signal then returns to an inactive state. Note: The MOD_DEF_9:0 inputs shown in Optical Module Status Ports 0-9 ($ 0x799), on page 166 are synchronized with an internal system clock. This results in a delay from the time the signal is active to the register bit and/or interrupt being set. 5.4.3.2.6 Tx_FAULT_INT TX_FAULT_Int is a single output, open-drain type signal, and is active Low. A change in state of any of the TX_FAULT_9:0 inputs causes this signal to switch Low and remain in this state until a Read of the Optical Module Status Ports 0-9 ($ 0x799), on page 166 takes place. The signal then returns to an inactive state. Note: The TX_FAULT_9:0 inputs shown in Optical Module Status Ports 0-9 ($ 0x799), on page 166 are synchronized with an internal system clock. This results in a delay from the time the signal is active to the register bit and/or interrupt being set. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 72 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.4.3.2.7 5.4 Optical Module Interface RX_LOS_INT RX_LOS_INT is a single output, open-drain type signal, and is active Low. A change in state of any of the RX_LOS_0:9 inputs causes this signal to switch Low and remain in this state until a Read of the Optical Module Status register has taken place. The signal then returns to an inactive state. Note: The RX_LOS_0:9 inputs shown in Optical Module Status Ports 0-9 ($ 0x799), on page 166 are synchronized with an internal system clock. This results in a delay from the time the signal is active to the register bit and/or interrupt being set. Note: MOD_DEF_INT, TX_FAULT_INT, and RX_LOS_INT are open-drain type outputs. With the three signals on the device, the system can decide which Optical module Status Register bits to look at to identify the interrupt condition source port. However, this is achieved at the expense of two device pins. In systems that cannot support multiple interrupt signals (applications that do not have extra hardware pins), these three outputs can be connected to a single pull-up resistor and used as a single interrupt pin. 5.4.4 I2C Module Configuration Interface The I2C interface is supported on SFP optical modules. Details of the operation are found in the SFP multi-source agreement (MSA). This document details the contents of the registers and addresses accessible on a given optical module supporting this interface. The SFP MSA identifies up to 512 8-bit registers that are accessible in each optical module. The I2C interface is Read/Write capable and supports either sequential or random access to the 8-bit parameters. The maximum clock rate of the interface is 100 kHz. All address select pins on the internal E2PROM are tied Low to give a device address equal to zero (00h). The specific interface in the IXF1110 MAC supports only a subset of the full I2C interface, and only the features required to support the optical modules are implemented, leading to the following support features: * Single I2C_CLK pin connected to all modules, and implemented to save unnecessary pin use. * Ten per-port I2C_DATA pins optical (I2C_DATA_9:0) are required due to the optical module requirement that all modules must be addressed as 00h. * Due to the single internal controller, only one optical module may be accessed at any one time. Optical module accesses contains a single register Read. Since these register accesses will most likely be done during power-up or discovery of a new module, these restrictions should not affect normal operation. * The I2C interface also supports byte write accesses to the full address range. 5.4.4.1 General Description In the IXF1110 MAC, the entire I2C interface is controlled through separate I2C Control and Data Registers (see I2C Control Ports 0-9 ($ 0x79B), on page 167 and I2C Data Ports 0-9 ($ 0x79C), on page 168. The general operation is described below. The I2C Control Register is divided into the following sections: * Port Address Error * Write Protect Error bit * No Acknowledge Error bit Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 73 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.4 Optical Module Interface * I2C Enable bit * I2C Start Access bit * Write Access Complete bit * Read DataValid bit * 4-bit Port Address Select * Read/Write access select * 4-bit Device ID * 11-bit Register Address The I2C Data Register is divided into the following sections: * 8-bit Write Data * 8-bit Read Data The 4-bit Device ID field defaults to Ah, this value is compatible with standard fiber module based on the Atmel Serial E2Prom family. I2C accesses to non-Atmel compatible devices will require to update this field with the appropriate value. The 11-bit Register Address is split into two sub-fields: * Bits [10:8] must be set to 0h to be compatible with standard fiber optical module. Alternatively these bits can be set to 1h - 7h to permit access to seven other I2C component on the same bus. * Bits [7:0] specify the particular location to be accessed within the device specified by the Device ID field and Register Address[10:8]. Initiating an access where the 4-bit Port Address field to a value > 9h will not generate an I2C access. Instead the Port Address Error will be set. Initiating a write access where the Device ID field = Ah and the Register Address[10:8] = 0h will generate an I2C access. In addition the Write Protect Error bit will be set to indicate a write has been initiated to the write protected optical module. 5.4.4.1.1 Read Access Operation Example The following sequence provides an example of reading the data stored in the Optical Module Register 0x000 for Port 5: 1. Program the I2C Control Ports 0-9 ($ 0x79B), on page 167 with the following information: a. Enable I2C Block by setting bit 25 to `1'. b. Set the port to be accessed by setting bits [19:16] to 0x5. c. Select a READ access by setting bit 15 to `1'. d. Set the Device ID, bits [14:11] to be 0xA (Atmel compatible). e. Set the 11-bit Register Address, bits [10:0] to 0x000. f. Initiate the I2C transfer by setting bit 24 to `1'. All other bits in this register should be written with the value `0'. This data is written into the I2C Control Register in a single cycle via the CPU interface. 2. When this register is written and the I2C Start bit is at a Logic 1, the I2C access state machine examines the Port Address Select and enables the I2C_DATA_0:9 output for the selected port. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 74 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.4 Optical Module Interface 3. The state machine uses the data in the Device ID and Register Address fields to build the data frame to be sent to the optical module. 4. The I2C DATA_READ_FSM internal state machine takes over the task of transferring the actual data between the IXF1110 MAC and the selected optical module (refer to the details in Section 5.4.4.2, I2C Protocol Specifics, on page 76). 5. The I2C DATA_READ_FSM internal state machine places the received data into the Read_Data field, bits [7:0] of the I2C Data Register, and sets the Read Data Valid bit, bit 20 of the I2C Control Register to `1' to signify that the Read data is valid. 6. The data is read through the CPU interface. The CPU must poll the Read Data Valid bit until it is set to `1. Only once this bit is set, it is safe to read the data in the I2C Data Register. 5.4.4.1.2 Write Access Operation Example The following sequence provides an example of writing data to the Optical Module Register 0xFF for Port 9: 1. Program the I2C Control Ports 0-9 ($ 0x79B), on page 167 with the following information: a. Enable I2C Block by setting bit 25 to `1'. b. Set the port to be accessed by setting bits [19:16] to 0x9. c. Select a WRITE access by setting bit 15 to `0'. d. Set the Device ID, bits [14:11] to be 0xA (Atmel compatible). e. Set the 11-bit Register Address, bits [10:0] to 0xFF. f. Initiate the I2C transfer by setting bit 24 to `1'. All other bits in this register should be written with the value `0'. This data is written into the I2C Control Register in a single cycle via the CPU interface. 2. When this register is written and the I2C Start bit is at a Logic 1, the I2C access state machine examines the Port Address Select and enables the I2C_DATA_0:9 output for the selected port. 3. The state machine uses the data in the Device ID and Register Address fields to build the data frame to be sent to the optical module. 4. The I2C DATA_WRITE_FSM internal state machine takes over the task of transferring the actual data between the IXF1110 MAC and the selected optical module (refer to the details in Section 5.4.4.2, I2C Protocol Specifics, on page 76). 5. The I2C DATA_WRITE_FSM internal state machine uses the data from the Write_Data field, bits [23:16] of the I2C Data Register, and sets the Write_Complete bit, bit 22 of the I2C Control Register to `1' to signify that the Write Access is complete. 6. The data is written through the CPU interface. The CPU must poll the Write_Complete bit until it is set to `1. Only once this bit is set, it is safe to request a new access. Note: Only one optical module I2C access sequence can be run at any given time. If a second Write is carried out to the I2C Control Register before a result is returned for the previous Write, the data for the first Write is lost. To ensure no data is lost, make sure Write complete = 1 before starting the next Write sequence. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 75 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.4.4.2 5.4 Optical Module Interface I2C Protocol Specifics This section describes the I2C protocol behavior supported by the IXF1110 MAC, which is controlled by an internal state machine. The Serial Clock Line (I2C_CLK) is an IXF1110 MAC output. The serial data is synchronous with this clock and is driven off the rising edge by the IXF1110 MAC and off the falling edge by the optical module. The IXF1110 MAC has only one I2C_CLK line that drives all of the optical modules. I2C_CLK is active only during a READ or WRITE operation, when a valid READ or WRITE is initiated by writing the I2C Control Ports 0 - 3 ($0x79B) Register (as defined in Section 5.4.4.1.1, Read Access Operation Example, on page 74 or Section 5.4.4.1.2, Write Access Operation Example, on page 75). The Serial Data (I2C_DATA_0:9) pins (one per port) are bi-directional for serial data transfer, and are open drain. 5.4.4.3 Port Protocol Operation 5.4.4.4 Clock and Data Transitions The I2C_DATA is normally pulled High with an extra device. Data on the I2C_DATA pin changes only during the I2C_CLK Low time periods (see Figure 18). Data changes during I2C_CLK High periods indicate a start or stop condition. Figure 18 Data Validity Timing I2C_DATA I2C_CLK DATA STABLE DATA STABLE DATA CHANGE 5.4.4.4.1 Start Condition A High-to-Low transition of I2C_DATA, with I2C_CLK High, is a start condition that must precede any other command (see Figure 19). 5.4.4.4.2 Stop Condition A Low-to-High transition of the I2C_DATA with I2C_CLK High is a stop condition. After a Read sequence, the stop command places the E2PROM in the optical in a standby power mode (see Figure 19). Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 76 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 19 5.4 Optical Module Interface Start and Stop Definition Timing I 2 C_DATA I2 C_CLK START 5.4.4.4.3 STOP Acknowledge All addresses and data words are serially transmitted to and from the optical module in 8-bit words. The optical module E2PROM sends a zero to acknowledge that it has received each word, which happens during the ninth clock cycle (see Figure 20). Figure 20 Acknowledge Timing I2C_DATA DATA IN DATA OUT START 5.4.4.4.4 ACKNOWLEDGE Memory Reset After an interruption in protocol, power loss, or system reset, any two-wire Optical Module can be reset by following three steps: 1. Clock up to nine cycles 2. Wait for I2C_DATA High in each cycle while I2C_CLK is High 3. Initiate a start condition The following defines device memory reset: * Always add a stop condition following the start as there is no clean finish to end the reset of the memory with a start condition after completing steps one through three. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 77 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.4 Optical Module Interface This ensures a clean protocol termination if there is no more data to transfer at the end of the reset cycle. 5.4.4.4.5 Device Addressing All E2PROMs in Optical Module devices require an 8-bit device address word following a start condition to enable the chip to read or write. The device address word consists of a mandatory one, zero sequence for the four most significant bits. This is common to all devices. The next 3 bits are the A2, A1 and A0 device address bits that are tied to zero in a optical module. The eighth bit of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit is High and a Write operation is initiated if this bit is Low. Upon comparison of the device address, the optical module outputs a zero. If a comparison is not made, the optical module E2PROM returns to a standby state. When not accessing the optical module E2PROM, the device address or device ID is completely programmable for maximum flexibility. 5.4.4.4.6 Random Read Operation A random Read requires a "dummy" Byte/Write sequence to load the data word address. The following describes how to achieve the "dummy" Write: * The IXF1110 MAC generates a start condition. * The IXF1110 MAC sends a device address word with the Read/Write bit cleared to Low, signaling a Write operation. * The optical module acknowledges receipt of the device address word. * The IXF1110 MAC sends the data word address, which is again acknowledged by the optical module. * The IXF1110 MAC generates another start condition. This completes the "dummy" Write and sets the optical module E2PROM pointers to the desired location. The following describes how the IXF1110 MAC initiates a current address Read: * The IXF1110 MAC sends a device address with the Read/Write bit set High * The optical module acknowledges the device address and serially clocks out the data word. * The IXF1110 MAC does not respond with a zero but generates a stop condition (see Figure 21). Figure 21 Random Read S T A R T DEVICE ADDRESS W R I T E S T A R T WORD ADDRESS R E A D DEVICE ADDRESS S T O P M S B L R S / B W START SDA LINE M S B L A S C B K M S B DUMMY WRITE L S B A C K DATAn N O A C K (* = DON'T CARE bit for 1k) Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 78 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.5 LED Interface Timing diagrams and tables can be found in Section 7.0, Electrical Specifications, on page 102. 5.4.4.4.7 Byte Write Operation The following describes how to achieve the byte write operation: * The IXF1110 MAC generates a start condition. * The IXF1110 MAC sends a device address word with the Read/Write bit cleared to Low, signaling a Write operation. * The optical module acknowledges receipt of the device address word. * The IXF1110 MAC sends the data word address. * The optical module acknowledges receipt of the data word address. * The IXF1110 MAC sends the data byte to be written. * The optical module acknowledges the data word. * The IXF1110 MAC generates a stop condition (see Figure 22). Figure 22 Byte Write S T A R T W R I T E DEVICE ADDRESS S T O P WORD ADDRESS * I2C_Data Line M S B L S B R A / C W K M S B L S B A C K DATAn A C K (* = DON'T CARE bit for 1k) 5.4.4.5 AC Timing Characteristics Table 43, I2C AC Timing Characteristics, on page 110, Figure 37, I2C Bus Timing, on page 109, and Figure 38, I2C Write Cycle, on page 110 provide the AC timing characteristics of the optical module interface. 5.5 LED Interface 5.5.1 Introduction The IXF1110 MAC uses a serial interface consisting of three signals to provide LED data to a serial-to-parallel logic external driver. The three signals are as follows: * LED CLK: This clock is provided by the IXF1110 MAC to clock the external parallel-to-serial shift registers. * LED DATA: This serial data is provided by the IXF1110 MAC to the external parallel-to-serial shift registers. * LED LATCH: This latch is provided by the IXF1110 MAC to latch the data on the parallel-to-serial shift registers. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 79 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.5 LED Interface The LED_DATA stream provides data for 30 separate direct drive LEDs and allows three LEDs per MAC port. The three LED pins outlined above are detailed in LED Signal Descriptions, on page 80. There are two modes of operation, each with its own separate LED decode mapping. Modes of operation and LEDs are detailed in Section 5.5.2, Modes of Operation. 5.5.2 Modes of Operation Mode selection is accomplished by using bit 0 of the LED Control ($ 0x509), on page 143. This bit is globally selected and controls the mode of operation of all ports Section 5.5.2.1 and Section 5.5.2.2 provide the two modes of operation. 5.5.2.1 Mode 0 This mode selects operations compatible with the SGS Thompson M5450 Led Display Driver Device. This device converts the serial data stream, output by the IXF1110 MAC, into 30 direct-drive LED outputs. In this mode, the latch signal is not required. This mode is selected by setting bit 0 of the LED Control ($ 0x509) to 0 (default). 5.5.2.2 Mode 1 This mode selects operations compatible with TTL (74LS595) or HCMOS (74HC595) octal shift registers. This device converts the serial data stream, output by the IXF1110 MAC, into 30 direct-drive LED outputs. In this mode the LED DATA, LED CLK and LED LATCH signals are used. This mode is selected by setting bit 0 of the LED Control ($ 0x509) to 1. 5.5.3 LED Interface Signal Description The IXF1110 MAC LED interface consists of three output signal pins that are 2.5 V CMOS level pads. Table 23 provides LED signal names, pin numbers, and descriptions. Table 23 LED Signal Descriptions Signal Name LED_CLK Ball Designator A20 Signal Description LED_CLK: This signal is an output that provides a continuous clock synchronous to the serial data stream output on the LED_DATA pin. This clock has a maximum speed of 720 hz. The behavior of this signal remains constant in all modes of operation. LED_DATA A19 LED_LATCH K18 LED_DATA: This signal provides the data, in various formats, as a serial bit stream. The data must be valid on the rising edge of the LED_CLK signal. In Mode 0, the data presented on this pin is TRUE (Logic 1 = High). In Mode 1, the data presented on this pin is INVERTED (Logic 1 = Low). LED_LATCH: This is an output pin and the signal is used only in Mode 1 as the Latch enable for the shift register chain. This signal is not used in Mode 0, and should be left unconnected. 5.5.4 Mode 0: Detailed Operation Note: Please refer to the SGS Thompson M5450 datasheet for device-operation information. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 80 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.5 LED Interface The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for each LED is placed in turn on the serial data line and clocked out by the LED_CLK. Figure 23 shows the basic timing relationship and relative positioning in the data stream of each bit. Figure 23 shows the 36 clocks that are output on the LED_CLK pin. The data changes on the falling edge of the clock and is valid for almost the entire clock cycle. This ensures that the data is valid during the rising edge of the LED_CLK, which is used to clock the data into the M5450 device.The actual data shown in Figure 23 consists of a chain of 36 bits only, 30 of which are valid LED DATA. The 36-bit data chain is built up as follows: Figure 23 Mode 0 Timing 1 2 3 4 26 27 28 29 30 31 32 33 34 35 36 1 23 24 25 26 27 28 29 30 LED_CLK LED_DATA LED_LATCH Table 24 Mode 0 Clock Cycle to Data Bit Relationship LED_CLK CYCLE LED_DATA NAME LED_DATA DESCRIPTION 1 START BIT This bit is used to synchronize the M5450 device to expect 35 bits of data to follow. 2:3 PAD BITS These bits are used only as fillers in the data stream to extend the length from the actual 30 bit LED DATA to the required 36-bit frame length. These bits should always be a Logic 0. 4:33 LED DATA 1-30 These bits are the actual data transmitted to the M5450 device. The decode for each individual bit in each mode is defined in LED Signal Descriptions, on page 80. The data is TRUE. Logic 1(LED ON) = High 34:36 PAD BITS These bits are used as fillers in the data stream to extend the length from the actual 30-bit LED DATA to the required 36-bit frame length. These bits should always be a Logic 0. When implemented on a board with the M5450 device, the LED DATA bit 1 appears on output bit 3 of the M5450 and the LED DATA bit 2 appears on output bit 4, etc. This means that output bits 1, 2, 3, 34, and 35 will never have valid data and should not be used. 5.5.5 Mode 1: Detailed Operation Note: Please refer to manufacturers' 74LS/HC595 datasheet for information on device operation. The operation of the LED Interface in Mode 1 is again based on a 36-bit counter loop. The data for each LED is placed in turn on the serial data line and clocked out by the LED_CLK. Figure 24 on page 82 shows the basic timing relationship and relative positioning in the data stream of each bit. Figure 24 shows the 36 clocks that are output on the LED_CLK pin. The data changes on the falling edge of the clock and is valid for almost the entire clock cycle. This ensures that the data is valid during the rising edge of the LED_CLK, which is used to clock the data into the Shift Register chain devices. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 81 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.5 LED Interface The LED_LATCH signal is required in Mode 1, and is used to latch the data shifted into the shift register chain into the output latches of the 74HC595 device. As seen in Figure 24, the LED_LATCH signal is active High during the Low period on the 36th LED_CLK cycle. This avoids any possibility of trying to latch data as it is shifting through the register. When this operation mode is implemented on a board with a shift register chain containing three 74HC595 devices, the LED DATA bit 1 is output on Shift Register bit 1, and so on up the chain. Only Shift Register bits 31 and 32 do not contain valid data. The actual data shown in Figure 24 consists of a 36-bit chain, of which 30 bits are valid LED DATA. The 36-bit data chain is built up as follows: Note: The LED_DATA signal is now inverted from the state in Mode 0. Figure 24 Mode 1 Timing 1 2 3 4 26 27 28 29 30 31 32 33 34 35 1 23 24 25 26 27 28 29 30 36 LED_CLK LED_DATA LED_LATCH Table 25 Mode 1 Clock Cycle to Data Bit Relationship LED_CLK CYCLE 5.5.6 LED_DATA NAME LED_DATA DESCRIPTION 1 START BIT This bit has no meaning in Mode 1 operation and is shifted out of the 32-stage shift register chain before the LED_LATCH signal is asserted. 2:3 PAD BITS These bits have no meaning in Mode 1 operation and are shifted out of the 32-stage shift register chain before the LED_LATCH signal is asserted. 4:33 LED DATA 1-30 These bits are the actual data to be transmitted to the 32-stage shift register chain. The decode for each bit in each mode is defined in Mode 1 Clock Cycle to Data Bit Relationship, on page 82. The data is INVERTED. Logic 1 (LED ON) = Low. 34:36 PAD BITS These bits have no meaning in Mode 1 operation and are latched into positions 31 and 32 in the shift register chain. These bits are not considered as valid data and should be ignored. They should always be a Logic 0 = High. Power-On, Reset, and Initialization The LED interface is disabled at power-on or reset. The system software controller must enable the LED interface. The internal state machines and output pins are held in reset until the full IXF1110 MAC configuration is completed. 5.5.6.1 Enabling the LED Interface LED Control ($ 0x509), on page 143: This register must be set to globally enable LED interface. This is done by setting the LED_ENABLE bit to a logic 1. The power-on default for this bit is Logic 0. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 82 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.5 LED Interface Port Enable ($ 0x500), on page 140: This register enables and disables ports on a per port basis. A port must be enabled for the LEDs to operate for that port. If the port is not enabled, the LEDs will be off for that port. The power-on default for this register is 0x3FF, which means all ports are enabled. Link LED Enable ($ 0x502), on page 141: This register must be set on a per port basis when link is detected by the system software. This enables the per-port link LEDs for the IXF1110 MAC. Link LEDs do not automatically update. For more details on which LEDs are affected by this register, refer to section Section 5.5.7.1, LED Signaling Behavior, on page 84. 5.5.7 LED Data Decodes Table 26 shows the data decode of the data for the IXF1110 MAC. Table 26 LED Data Decodes (Sheet 1 of 2) LED_DATA# MACPORT# IXF1110 MAC Designation 1 2 Rx LED - Amber 0 Rx LED - Green 3 Tx LED - Green 4 Rx LED - Amber 5 1 Rx LED - Green 6 Tx LED - Green 7 Rx LED - Amber 8 2 Rx LED - Green 9 Tx LED - Green 10 Rx LED - Amber 11 3 12 Tx LED - Green 13 14 Rx LED - Green Rx LED - Amber 4 Rx LED - Green 15 Tx LED - Green 16 Rx LED - Amber 17 5 Rx LED - Green 18 Tx LED - Green 19 Rx LED - Amber 20 6 Rx LED - Green 21 Tx LED - Green 22 Rx LED - Amber 23 7 24 Tx LED - Green 25 26 Rx LED - Green Rx LED - Amber 8 27 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Rx LED - Green Tx LED - Green Page 83 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 26 5.6 CPU Interface LED Data Decodes (Sheet 2 of 2) LED_DATA# MACPORT# IXF1110 MAC Designation 28 Rx LED - Amber 29 9 Rx LED - Green 30 5.5.7.1 Tx LED - Green LED Signaling Behavior The operation in each mode for the decoded LED data in Table 26 is detailed in Table 27. Table 27 LED Behavior Type RXLED Status Off Synchronization has occurred but no packets are being received and Link LED Enable ($ 0x502), on page 141 has not been set. Amber On RX Synchronization has not occurred or no optical signal exists. Amber Blinking Port has remote fault and LED Fault Disable ($ 0x50B), on page 143 is not set. Based on remote fault bit setting received in RX_Config word. Green On RX Synchronization has occurred and the Link LED Enable ($ 0x502), on page 141 bit is set. Green Blinking RX Synchronization has occurred and port is receiving data. Off Port is not transmitting data or Link LED Enable ($ 0x502), on page 141 is not set. Green Blinking Port is transmitting data and Link LED Enable ($ 0x502), on page 141 bit is set TXLED Note: Description The LED behavior table assumes the port is enabled in the Port Enable ($ 0x500), on page 140 and the LEDs are enabled in the LED Control ($ 0x509), on page 143. If a port is not enabled, all the LEDs for that port will be off. If the LEDs are not enabled, all of the LEDs will be off. 5.6 CPU Interface 5.6.1 General Description The CPU Interface block provides access to registers and statistics in the IXF1110 MAC. The interface is asynchronous externally and operates within the 125 MHz clock domain internally. The interface provides access to the following registers: * MAC Control * MAC RX Statistics * MAC TX Statistics * Global Status and Configuration * RX Block * TX Block * SPI4-2 Block * SerDes Block Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 84 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.6 CPU Interface * Optical Module Block Figure 25 illustrates the I/O for the CPU interface on the IXF1110 MAC. Figure 25 CPU Interface Inputs/Outputs UPX_WR_L UPX_RD_L UPX_CS_L CPU Interface UPX_RDY_L UPX_DATA[31:0] 32 UPX_ADDR[10:0] 11 B3379-01 5.6.2 Functional Description The CPU interface is designed for a generic 32-bit asynchronous CPU bus. The bus is a 32-bit data bus only and has an 11-bit address bus. The IXF1110 MAC external CPU interface is asynchronous and has no clock. This allows flexibility for CPU selection.The interface to all IXF1110 MAC registers is synchronous to 125 MHz internally. In some applications, synchronous-to-asynchronous glue logic is required between the IXF1110 MAC and the system CPU. This glue logic must be designed so that the IXF1110 MAC Read and Write access times are not violated. It may be possible to interface without glue logic if the CPU can meet the timing seen in Figure 26, Read Timing - Asynchronous Interface, on page 87, Figure 27, Write Timing - Asynchronous Interface, on page 87, and Table 39, CPU Timing Parameters, on page 106 Table 28 CPU Interface Signals Name UPX_ADD[10:0] Direction Input Standard CMOS 2.5 V Description Address bus UPX_CS_L Input CMOS 2.5 V Chip Select Signal UPX_DATA[31:0] Bi_Dir CMOS 2.5 V Bi-directional data bus UPX_WR_L Input CMOS 2.5 V Write Strobe UPX_RD_L Input CMOS 2.5 V Read Strobe UPX_RDY_L Output CMOS 2.5 V Cycle complete indicator UPX_ADD[10:0] Internal IXF1110 MAC registers and counters are selected using the 11-bit address bus input provided at the CPU interface. This address must be stable for the entire cycle. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 85 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.6 CPU Interface UPX_CS_L The chip select input when active Low selects IXF1110 MAC for the current cycle. No CPU cycle is recognized without this signal being active. At the end of the cycle, the chip select can be driven High to deselect the device or it can be left active if the next access is to the same device (as long as both Read and Write control signals are inactive between cycles). The CPU usually supports multiple chip selects, and glue logic is required to drive separate chip selects if more than one IXF1110 MAC is being controlled by one CPU. UPX_DATA[31:0] These pins comprise the 32-bit data bus pins containing data to and from the CPU interface. This data is asynchronous on the IXF1110 MAC. The Write data provided by the CPU must be stable during the entire CPU cycle to prevent erroneous Write operations to a register. UPX_WR_L This pin indicates there is data on the CPU data bus to be written to the IXF1110 MAC. A Low-to-High transition latches the data and a High-to-Low transition latches the address. This Write operation is active Low. UPX_RD_L This pin indicates there is data on the CPU data bus to be read from the IXF1110 MAC. A High-to-Low transition latches the address. This Read operation is active Low. UPX_RDY_L This pin indicates the Read or Write cycle is complete for the IXF1110 MAC. This operation is active Low. Note: External pull-up resistor required for proper operation. 5.6.2.1 Read Access The IXF1110 MAC read access cycle operation is done in the following order: 1. Chip Select (UPX_CS_L) is asserted at all times for the duration of the operation. The address to be read should be on the IXF1110 MAC address bus (UPX_ADD[10:0]). 2. UPX_RD_L should be asserted by the CPU. The IXF1110 MAC latches the address. 3. IXF1110 MAC drives valid data onto the processor bus (UPX_DATA[31:0]). 4. IXF1110 MAC asserts asynchronous-ready (UPX_RDY_L). This indicates to the CPU that the Read cycle is complete. Figure 26 provides the timing of the asynchronous interface for Read access. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 86 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.6 CPU Interface . Figure 26 Read Timing - Asynchronous Interface Tcas Tcah UPX_ADD[10:0] UPX_CS_L Tcrh UPX_RD_L Tcrr Tcdrh UPX_DATA[31:0] Tcdrs UPX_RDY_L Tcdrh B3381-01 5.6.2.2 Write Access The IXF1110 MAC Write access cycle operation is done in the following order: 1. Chip Select (UPX_CS_L) is asserted at all times for the duration of the operation. The address to be read should be on the IXF1110 MAC address bus (UPX_ADD[10:0]). 2. UPX_WR_L should be asserted by the CPU. The IXF1110 MAC latches the address. 3. The CPU drives valid data onto the processor bus (UPX_DATA[31:0]). 4. The CPU de-asserts the asynchronous Write signal (UPX_WR_L) of the IXF1110 MAC. The IXF1110 MAC latches the data. 5. The IXF1110 MAC asserts asynchronous-ready (UPX_RDY_L). The glue logic indicates to the CPU that the Write cycle is complete. Figure 27 provides the timing of the asynchronous interface for Write access. Figure 27 Write Timing - Asynchronous Interface TCAS TCAH UPX_ADD[10:0] UPX_CS_L TCWL UPX_WR_L TCWH TCDWH UPX_DATA[31:0] TCDWS TCYD UPX_RDY_L TCDWD B3382-01 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 87 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.6.2.3 5.7 JTAG (Boundary Scan) Timing parameters Timing parameters for the CPU interface are seen in Table 39, CPU Timing Parameters, on page 106. 5.6.3 Endian The Endian of the CPU interface may be changed to allow connection of various CPUs to the IXF1110 MAC. The Endian selection is determined by setting the Endian bit in the CPU Interface ($ 0x508), on page 142. 5.7 JTAG (Boundary Scan) The IXF1110 MAC includes an IEEE 1149.1 boundary scan test port for board level testing. All inputs are accessible. The BSDL file for this device is available by accessing the Cortina website. 5.7.1 TAP Interface (JTAG) The IXF1110 MAC includes an IEEE 1149.1 compliant Test Access Port (TAP) interface used during boundary scan testing. The interface consists of the following five pins: * TDI - Serial data input * TMS - Test mode select * TCLK - TAP clock * TRST_L - Active low asynchronous reset for the TAP * TDO - Serial data output TDI and TMS require external pull-up resistors to float the pins High per the IEEE 1149.1 specification. Pull-ups are recommended on TCK and TDO. For normal operation, TRST_L can be pulled Low, permanently disabling the JTAG interface. If the JTAG interface is used, the TAP controller must be reset as described in Section 5.7.2, TAP State Machine, on page 89 and returned to a logic High. Note: The JTAG pins must be terminated correctly for proper device operation. Table 29 Recommended JTAG Termination Signal Description TRST_L1 Pull-down through 10 K resistor TDO Pull-up through 10 K resistor TDI Pull-up through 10 K resistor TMS Pull-up through 10 K resistor TCK Pull-up through 10 K resistor 1. TRST_L must be pulled Low to ensure proper IXF1110 MAC operation. When TRST_L is Low, the JTAG interface is disabled. If the boundary scan logic is used, TRST_L must be pulsed Low after power-up to ensure reset of the TAP controller. For more information, refer to Section 5.7.2, TAP State Machine, on page 89 or the IEEE 1149.1 Boundary Scan Specification. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 88 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.7.2 5.7 JTAG (Boundary Scan) TAP State Machine The TAP pins drive a TAP controller, which implements the 16-state machine specified by the IEEE 1149.1 specification. Following power up, the TAP controller must be reset by one of following two mechanisms: * Asynchronous reset - achieved by pulsing or holding TRST_L low * Synchronous reset - achieved by clocking TCK with five clock pulses while TMS is held or floats High. This ensures that the boundary scan cells do not block the pin to core connections in theIXF1110 MAC. 5.7.3 Instruction Register and Supported Instructions The instruction register is a 4-bit register that enacts the boundary scan instructions. After the state machine resets, the default instruction is IDCODE. The decode logic in the TAP controller selects the appropriate data register and configures the boundary scan cells for the current instruction. The table below shows the supported boundary scan instructions. Table 30 5.7.4 Supported Boundary Scan Instructions Instruction Code Description Data Register EXTEST 0000 External Test Boundary Scan SAMPLE 0001 Sample Boundary Boundary Scan HIGHZ 0101 Float Boundary Bypass IDCODE 0110 ID Code Inspection ID CLAMP 0111 Clamp Boundary Bypass BYPASS 1111 1-bit Bypass Bypass ID Register The ID register is a 32-bit register. The IDCODE instruction connects this register between TDI and TDO. Refer to Table 87, JTAG ID Revision ($ 0x50C), on page 144 for register bit descriptions. Note: The four bit version field is stepping dependent. The seven bit Manufacturers ID is the manufacturer JEDEC ID less the parity bit per the IEEE 1149.1 specification. 5.7.5 Boundary Scan Register The boundary scan register is a shift register made up of all the boundary scan cells associated with the device pins. The number, type, and order of the boundary scan cells are specified in the IXF1110 MAC BSDL file. The EXTEST and SAMPLE instructions connect this register between TDI and TDO. 5.7.6 Bypass Register The bypass register is a one bit register that is used so the IXF1110 MAC can be bypassed to reduce the length of the JTAG chain when trying to access other devices on the chain besides the IXF1110 MAC. The BYPASS, HIGHZ, and CLAMP instructions connect this register between TDI and TDO. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 89 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.8 5.8 Clocks Clocks The IXF1110 MAC has system interface reference clocks, SPI4-2 data path input and output clocks, a JTAG input clock, a I2C output clock, and an LED output clock. Section 5.8 details the unique clock source requirements. 5.8.1 System Interface Reference Clocks There are two system interface clocks required by the IXF1110 MAC: 5.8.1.1 CLK125 The system interface clock, which supplies the clock to the majority of the internal circuitry, is the 125 MHz clock. The source of this clock must meet the following specifications: * 3.3 V LVTTL drive * +/- 50 ppm * Maximum duty cycle distortion 40/60 5.8.1.2 CLK50 The other system interface clock supplies the clock source to the SPI4-2 receive circuitry. The source of this clock must meet the following specifications: * 3.3 V LVTTL drive * 1/8 frequency of the SPI4-2 data path clock (RDCLK_P/N) * Maximum duty cycle distortion 45/55 * Maximum peak-to-peak jitter (low and high frequency) of 125 pS * Range = 42 Mhz to 50 MHz 5.8.2 SPI4-2 Receive and Transmit Data Path Clocks The SPI4-2 data path clocks are compliant with the OIF 2000.88.4 Specification. The IXF1110 MAC has the following requirements on the transmit data path: * 2.5 V LVDS drive * Maximum duty cycle distortion 45/55 * Maximum peak-to-peak jitter (low and high frequency) of 125 pS * Stable (frequency and level) when reset is removed or when sourced, whichever happens last * TSCLK frequency is one-quarter TDCLK frequency The IXF1110 MAC meets the following specifications on the receive data path: * 2.5 V LVDS drive * Maximum duty cycle distortion 45/55 * Maximum peak-to-peak jitter (low and high frequency) of 125 pS * Stable when sourced Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 90 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.8.3 5.8 Clocks JTAG Clock The IXF1110 MAC supports JTAG. The source of this clock must meet the following specifications: * 2.5 V CMOS drive * Maximum clock frequency 11 MHz * Maximum duty cycle distortion 40/60 5.8.4 I2C Clock The IXF1110 MAC supports a single output I2C clock to support all 10 optical module interfaces. The IXF1110 MAC meets the following specifications for this clock: * 2.5 V CMOS drive * Maximum clock frequency of 100 kHz 5.8.5 LED Clock The IXF1110 MAC supports a serial LED data stream. This interface implements a 2.5 V CMOS output clock with a maximum frequency of 720 Hz. The IXF1110 MAC supports a serial LED data stream. The IXF1110 MAC meets the following specifications for this clock: * 2.5 V CMOS drive * Maximum frequency of 720 Hz * Maximum duty cycle distortion: 50/50 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 91 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.0 Applications 6.0 Applications 6.1 Power Supply Sequencing Follow the power-up and power-down sequence described in this section to ensure correct IXF1110 MAC operation. The sequence covers all IXF1110 MAC digital and analog supplies. Caution: Failure to follow the power-up and power-down sequences will damage the IXF1110 MAC. 6.1.1 Power-Up Sequence Ensure that the 1.8 V supplies (VDD/AVDD1P8_1/AVDD1P8_2) are applied and stable prior to the application of the 2.5 V supplies (VDD2/AVDD2P5_1/AVDD2P5_2). Caution: If the 2.5 V supplies (VDD2/AVDD2P5_1/AVDD2P5_2) exceed the 1.8 V (VDD/AVDD1P8_1/AVDD1P8_2) supplies by more than 2.0 V during power-up, the ESD structures within the analog I/Os can be damaged. 6.1.2 Power-Down Sequence The power-down sequence is the reverse of the power-up sequence. Remove the 2.5 V supplies prior to removing the 1.8 V supplies. Figure 28 and Table 31 provide information on power sequencing. Note: If the 2.5 V supplies (VDD2/AVDD2P5_1/AVDD2P5_2) exceed the 1.8 V (VDD/AVDD1P8_1/AVDD1P8_2) supplies by more than 2.0 V during power-down, damage can occur to the ESD structures within the analog I/Os. Figure 28 Power Sequencing 1.8 V Supplies Stable t=0 Apply VDD, AVDD1P8_1/ AVDD1P8_2 2.5 V Supplies Stable Apply VDD2, AVDD2P5_1/ AVDD2P5_2 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Time Apply SYS_RES_L Page 92 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 31 6.2 Analog Power Filtering Power Sequencing Power Supply Power-Up Order Time Delta to Next Supply1 VDD, AVDD1P8_1/AVDD1P8 _2 First 0 1.8 V supplies VDD2, AVDD2P5_1/AVDD2P5 _2 Second 10 s 2.5 V supplies Description 1. The value of 10 s given is a nominal value only. The exact time difference between the application of the 2.5 V analog supply will be determined by a number of factors dependent on the power management method used. 6.2 Analog Power Filtering Figure 29 illustrates an analog power supply filter network and Table 32 lists the analog power balls. Figure 29 Analog Power Supply Filter Network FB 100/100 MHz 2.5 V or 1.8 V VDD Analog Power Ball R 0.1 F Table 32 Analog Power Balls Signal Name 6.3 0.1 F Ball Designator AVDD1P8_1 D1 AVDD2P5_1 Y1 AVDD1P8_2 P7 V14 P18 V18 V6 AVDD2P5_2 N3 V10 N22 V15 P3 Comments E24 Need to provide a filter (see Figure 29). R: AVDD1P8_1 and AVDD2P5_1 = 5.6 resistor. V11 Need to provide a filter (see Figure 29). P22 R: AVDD1P8_2 and AVDD2P5_2 = 1.0 resistor. TX FIFO and RX FIFO Operation The IXF1110 MAC packet buffering is comprised of individual port FIFOs and system-interface FIFOs. Figure 30 illustrates the interaction of these FIFOs. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 93 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 30 6.3 TX FIFO and RX FIFO Operation Packet Buffering FIFO MDI SPI4-2 Interface High Water Mark TX FIFO Data Flow TX Side MAC Data Flow RX Side MAC MAC Transfer Threshold * Low Water Mark High Water Mark RX FIFO Low Water Mark RX FIFO High TxPauseFr (External strobe) Note: 6.3.1 802.3 Flow control 802.3x Pause Frame Generation The MAC Transfer Threshold determines when the transmit data is transferred from the TX FIFO to the TX side of the MAC. Once the data has been sent from the TX FIFO to the MAC, it will be transmitted to the PHY and cannot be flow controlled from the link partner. TX FIFO The IXF1110 MAC TX FIFOs are implemented with 4.5 KB for each port. This provides enough space for at least one maximum size packet per-port storage and ensures that no under-run conditions occur, assuming that the sending device can supply data at the required data rate. Note: The TX FIFO High and Low Watermark must be programmed correctly to ensure that the TX FIFO does not overflow. 6.3.1.1 MAC Transfer Threshold The TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D), on page 157 parameter, which is user programmable, determines when data is transmitted out of the TX FIFO to the MAC. This parameter is configurable for specific block sizes and the user must ensure that an under-run does not occur. The threshold must be set to a value that exceeds the programmed MaxBurst1 parameter from the Network Processor (NPU) or SPI4-2 ASIC. This method of operation eliminates the possibility of under-run, except when the controlling NPU device fails. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 94 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.3 TX FIFO and RX FIFO Operation The MAC transfer threshold operates on a per packet basis. Once the number of bytes of a packet received in the TX FIFO exceeds the MAC transfer threshold, it will start to be transmitted to the MAC. If the MAC transfer is greater than the packet size, the packet is sent to the MAC once an EOP is received. The MAC transfer threshold should be set below the TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609), on page 153. If the MAC transfer threshold is set above the TX FIFO high watermark, the TX FIFO high watermark will act as the MAC transfer threshold. Data is transmitted out of the TX FIFO to the MAC when the TX FIFO high watermark is reached. 6.3.1.2 TX FIFO Relation to the SPI4-2 Transmit FIFO Status (TSTAT) The amount of data in the TX FIFO dictates the FIFO status sent to the NPU on the TSTAT bus. The following lists how the FIFO status is determined from the TX FIFO High and Low Watermarks. SATISFIED: The status given for a port when the amount of data in the per port TX FIFO is greater than the programmed TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609), on page 153. HUNGRY: The status given for a port when the amount of data in the per port TX FIFO is between the programmed TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609), on page 153 and the TX FIFO Low Watermark Ports 0 to 9 ($ 0x60A - 0x613), on page 155. STARVING: The status given for a port when the amount of data in the per port TX FIFO is below the programmed value in TX FIFO Low Watermark Ports 0 to 9 ($ 0x60A - 0x613), on page 155. Note: The user must ensure the TX FIFO High and Low Watermarks are programmed correctly to ensure no underrrun or overflow occur. Failure to do this may result in packet loss. 6.3.1.3 TX FIFO Drain The IXF1110 MAC can allow the SPI4-2 NPU or ASIC to dump data to the IXF1110 MAC while the link is down. This allows the NPU or ASIC to empty its FIFOs, if necessary. The IXF1110 MAC operates in the following manner under normal operating conditions: * The IXF1110 MAC supports IEEE 802.3 fiber auto-negotiation, including forced mode. In auto-negotiation mode (Setting bit 5 to 1 (AN_enable) of the Diverse Config Register ($ Port_Index + 0x18)), when the MAC detects that the link is down for a given port (Bit 20 = 0 (RX Sync) of the RX Config Word Register ($ Port_Index + 0x16)) the TX FIFO is automatically reset. This will result in the SPI-4.2 interface TX FIFO Status bus indicating Satisfied. This tells the NPU or ASIC that no data can be passed across the SPI-4.2. In forced mode (Setting bit 5 to 0 (AN_enable) of the Diverse Config Register ($ Port_Index + 0x18)), when the MAC detects that the link is down for a given port (Bit 20 = 0 (RX Sync) of the RX Config Word Register ($ Port_Index + 0x16)) the TX FIFO is not automatically reset. The result is that the SPI-4.2 interface TX FIFO Status bus continues to report the available data space in the TX FIFO as defined by the TX FIFO High and TX FIFO Low watermarks: Satisfied, Hungry, or Starving. The IXF1110 MAC operates in the following the manner when the TX FIFO drain is enabled: * The SPI4-2 FIFO status bus indicates STARVING for the given port. This tells the NPU or ASIC that it can pass data to the IXF1110 MAC for that port, regardless of the link status, and all data sent to that port will be discarded. Note: The TX FIFO drain is enabled using the TX FIFO Drain ($0x620), on page 160. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 95 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.3.1.3.1 6.3 TX FIFO and RX FIFO Operation Enabling the TX FIFO Drain The TX FIFO drain is enabled using the TX FIFO Drain ($0x620), on page 160. The following occurs when the TX FIFO drain is enabled for a given port: * The TX FIFO is held in reset * The FIFO status for that port indicates SATISFIED * All data sent to that port is discarded 6.3.1.3.2 Putting the TX FIFO in Drain Mode Use the TX FIFO drain when the link is down. The following is a step-by-step sequence to put a port(s) into the TX FIFO drain mode: 1. The system detects that link is down for a given port using bits 21:20 of the RX Config Word Register ($ Port_Index + 0x16). The SPI4-2 TX FIFO port status is SATISFIED when the link is down. 2. Set the appropriate bit to 1 for the given port in the TX FIFO Drain Register ($0x620) once link is down. This incurs the following: a. Enables the drain mode b. Causes the TX FIFO for the selected port to enter a reset state c. Causes the TX FIFO SPI4-2 FIFO status for that port to change to STARVING. 3. Set the MAC Soft Reset Register bit to 1 for the port(s) that has entered the TX FIFO drain mode. 4. De-assert the MAC Soft Reset Register. Redo the MAC configurations. If applicable, re-enable auto-negotiation for the selected port(s) by setting bit 5 of the Diverse Config Register back to 1. 5. The connected SPI4-2 NPU or ASIC can now dump data to the port(s) that has entered the drain mode. All data sent to the port(s) selected is discarded and not recorded in any register in the IXF1110 MAC. 6. Monitor the RX Config Word Register to reestablish link with the link partner. Exit the TX FIFO drain mode when the system software detects link establishment. 6.3.1.3.3 Exiting the TX FIFO Drain Mode To exit the TX FIFO drain mode. 1. Set the TX FIFO Drain Register bits back to 0. This exits the TX FIFO drain mode and the TX FIFO status bus now indicates the actual TX FIFO status. 2. The IXF1110 MAC is ready to resume normal data transmission. 6.3.2 RX FIFO The IXF1110 MAC RX FIFOs are provisioned so that each port has its own 17.0 KB memory space. This is enough memory to ensure against an over-run on any port while transferring normal Ethernet frame-size data. The RX FIFOs are configured by default to automatically generate Pause control frames to initiate the following: * Halt the link partner when the RX FIFO High Watermark is reached * Restart the link partner when the data stored in the RXFIFO falls below the Low Watermark. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 96 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.4 Reset and Initialization Pause control frame generation is enabled by default in the FC Enable ($ Port_Index + 0x12), on page 127. Global RX Block Register Overview, on page 144 documents the registers needed to set the RX FIFO watermarks. Note: Users should ensure that flow control is enabled to prevent RX FIFO overflows. If an RX FIFO overflow occurs, data is sent out on the SPI4-2 interface regardless of the RX FIFO Errored Frame Drop Enable ($ 0x59F), on page 150 settings. The data is marked with an EOP abort code to inform the upstream device that this data is corrupted. 6.4 Reset and Initialization When powering up the IXF1110 MAC, the hardware reset signal (SYS_RES_L) should be held active Low for a minimum of 100 ns after all of the power rails have fully stabilized to their nominal values and the input clocks have reached their nominal frequency (TDCLK = 400 MHz, CLK125 = 125 MHz, and CLK50 = 50 MHz). Note: In systems where the SYS_RES_L pin is driven from a single board-wide reset signal, the switch or network processor only comes out of reset at the same time as the IXF1110 MAC, or possibly later. This means the TDCLK may not be applied to theIXF1110 MAC when the SYS_RES_L pin is released. However, the system designer must ensure that the switch or network processor does not output TDCLK until it is stable and has reached its nominal operating frequency. Failure to apply a stable TDCLK to the IXF1110 MAC can result in the IXF1110 MAC training on a non-stable clock thus causing DIP4 errors and data corruption. This will require a re-training once the TDCLK is stable. When the TDCLK is applied after the reset pin is released, a built-in feature in the IXF1110 MAC reactivates the internal reset once TDCLK is applied. The IXF1110 MAC extends this hardware reset internally to ensure synchronization of all internal blocks within the system. The internal reset is extended for a minimum of 4.11 ms after all clocks are stable. The device is correctly initialized at this point and ready for use. Clocks start to appear at the relevant device ports and the SPI4-2 interface begins to source a training pattern on the receive side while waiting for a training pattern on the transmit side. The SPI4-2 interface synchronizes with the connected switch or network processor per the SPI4-2 Specification. The CPU accesses can begin to configure the device for any existing user preferences desired.By default, all ports on the IXF1110 MAC are enabled after power-up. The device is ready for use at this time if the default settings are to be used. Otherwise, access the required registers via the CPU interface and configure the control registers to the required settings. 6.4.1 SPI4-2 Initialization 6.4.1.1 RX SPI4-2 After reset or Power-up the RX SPI4-2 interface will start to source training patterns on the data bus to the upstream SPI4-2 device. The IXF1110 MAC will continue to send the training patterns until a valid calendar is sent on RSTAT[1:0] from the upstream device to the IXF1110 MAC. At this point, synchronization with the upstream device is complete and the IXF1110 MAC will start to send data once data is available and a credit has been granted from the RSTAT[1:0] bus. When synchronization is completed, bit 13 of the SPI4-2 RX Calendar ($ 0x702), on page 164 is "1". Before completion, bit 13 is "0", indicating the IXF1110 MAC is sending out training patterns on the RX SPI4-2 data bus. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 97 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.4.1.2 6.5 SerDes Power-Down Capabilities TX SPI4-2 After reset or power-up, the TX SPI4-2 interface outputs a constant framing pattern on TSTAT until it receives the proper SPI4-2 training pattern from the upstream SPI4-2 device. For more information on the required training pattern, see Section 5.2.3, Dynamic Phase Alignment Training Sequence (Data Path De-skew), on page 62. Note: If TDCLK is applied to the IXF1110 MAC after the device has come out of reset, the system designer must ensure the TDCLK is stable when applied. Failure to due so can result in the IXF1110 MAC training on a non-stable clock, causing DIP4 errors and data corruption. Once the valid training pattern is received and the IXF1110 MAC outputs a 10-port calendar on TSAT, bit 12 of the SPI4-2 RX Calendar ($ 0x702), on page 164 will be set. This indicates that synchronization on the TX SPI4-2 is complete. Ports will show a SATISFIED status on the SPI4-2 TSTAT bus until a valid link is established for that port. To determine if a valid link is established, see Section 5.1.4, Fiber Operation, on page 48. 6.4.1.3 SerDes After reset or power-up the SerDes interface will start to output idles on the TX_P/N for forced mode operation. If Auto-Negotiation mode is required bit 5 of the Diverse Config ($ Port_Index + 0x18), on page 129 must be set. A link is established when the RX SerDes has received the appropriate code words from the link partner. Refer to Section 5.1.4, Fiber Operation, on page 48 for more information. 6.4.1.4 CPU The CPU interface is ready for operation after power-up or reset. Through this interface, the user can configure the device for any desired setting from the defaults. (Refer to Section 5.6, CPU Interface, on page 84 for more information.) 6.5 SerDes Power-Down Capabilities The IXF1110 MAC has the ability to power down the TX and RX SerDes individually on each port (see Section 5.3, SerDes Interface, on page 67). Use the following sequence to correctly power up and power down the SerDes ports. Note: These sequences must be followed to ensure a port correctly operates when brought out of a power-down mode: 6.5.1 Placing the SerDes Port in Power-Down Mode 1. Disable the port(s) by de-asserting the appropriate bit(s) in the Port Enable ($ 0x500), on page 140. 2. Power-down SerDes TX and RX Power-Down Ports 0-9 ($ 0x787), on page 166. 3. The SerDes port is now powered down and the TSAT Status for the port is SATISFIED. 6.5.2 Bringing the SerDes Port Out of Power-Down Mode 1. Power up TX and RX SerDes. 2. Enable the port(s) by de-asserting the appropriate bit(s) in the Port Enable ($ 0x500), on page 140. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 98 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.6 IXF1110 MAC Unused Ports 3. Enable auto-negotiation (if applicable). The device defaults to forced mode if it is not enabled. 4. Once a valid link is established, the TSTAT status bus for that port changes from SATISFED to STARVING. 6.6 IXF1110 MAC Unused Ports Cortina recommends the following be used to disable an unused port. The SPI4-2 TSTAT status bus will always reflect status for ten ports regardless of the number of IXF1110 MAC unused ports. Any port which is disabled will have a constant status of SATISFIED. RSTAT must also be input to reflect the status of all ten ports regardless of how many are disabled. 1. Disable ports by setting the appropriate bits in the Port Enable ($ 0x500), on page 140. 2. Power down SerDes for the unused port by setting the appropriate bits in the SerDes TX and RX Power-Down Ports 0-9 ($ 0x787), on page 166. 3. TX SerDes pairs can be left unconnected. 4. RX SerDes pairs should be connected to ground. 6.7 Optical Module Connections to the IXF1110 MAC 6.7.1 SFP-to-IXF1110 MAC Connection The IXF1110 MAC SerDes and Optical Module interfaces allow system designers to connect the IXF1110 MAC to various optical transceivers. When using Small Form Factor Pluggable (SFP) optical transceivers to connect to the IXF1110 MAC, all SerDes and Optical Module status pins are used. Use Figure 31, SFP-to-IXF1110 MAC Connection and Table 33, SFP-to-IXF1110 MAC Connection to connect an SFP to the IXF1110 MAC. Figure 31 SFP-to-IXF1110 MAC Connection VDD 3.3 V 4.7 k 4.7 k 4.7 k 4.7 k 4.7 k IXF1110 SFP VDD 3.3 V TX_FAULT 2 TXFault I C_DATA 4 MOD_DEF(2) I2C_CLK 5 MOD_DEF(1) MOD_DEF 6 MOD_DEF(0) RX_LOS 8 LOS TX_DISABLE 3 TXDisable 2 TX+ 18 TD+ TX- 19 TD- VccR 15 VccT 16 VeeR 9 VeeR 10 VeeR 11 RX- 12 RD- RX+ 13 RD+ VeeR 14 VeeT 1 TX_FAULT_Int 7 Rate_Select VDD 3.3 V RX_LOS_Int VeeT 17 VeeT 20 MOD_DEF_Int 4.7 k External CPU Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 99 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 33 6.7 Optical Module Connections to the IXF1110 MAC SFP-to-IXF1110 MAC Connection (Sheet 1 of 2) SFP Pin # SFP Pin Name 1 VeeT 2 TxFault 3 IXF1110 MAC Pin # 0:9 IXF1110 MAC Pin Name Description NA NA Connect to ground. M24, V23, Y17, R15, W14, W11, W9, AC5, P8, L2 TX_FAULT_[0:9] Use an external 4.7 k pull-up resistor to 3.3 V. TxDisable K22, M22, AC22, U18, U14, AA18, U9, AA9, V7, L4 TX_DISABLE_[0:9] SFP module has internal pull-up. 4 MOD_DEF (2) G22, G23, J24, F22, E23, H24, G20, E22, G24, F24 I2C_DATA_[0:9] Use an external 4.7 k pull-up resistor to 3.3 V. 5 MOD_DEF (1) L19 I2C_CLK Use an external 4.7 k pull-up resistor to 3.3 V. 6 MOD_DEF (0) N24, Y21, AA16, M20, AC14, U11, T4, AB2, R7, L1 MOD_DEF_[0:9] Use an external 4.7 k pull-up resistor to 3.3 V. 7 Rate Select NA NA Leave floating. 8 LOS L22, V17, AD18, R12, AB15, V12, Y9, AC3, T2, P2 RX_LOS_[0:9] Use an external 4.7 k pull-up resistor to 3.3 V. 9 VeeR NA NA Connect to ground. 10 VeeR NA NA Connect to ground. 11 VeeR NA NA Connect to ground. 12 RD- U22, U20, T24, V24, AB14, AD14, AC16, AD15, V4, Y5 RX_N_[0:9] 13 RD+ T22, T20, U24, W24, AB13, AD13, AB16, AD16, V5, Y6 RX_P_[0:9] The IXF1110 MAC has a 100 differential termination on the chip that requires it to be AC-coupled. AC-coupling is done inside the SFP module and is not required on the host board. 14 VeeR NA NA Connect to ground. 15 VccR NA NA Connect to filtered 3.3 V. 16 VccT NA NA Connect to filtered 3.3 V. 17 VeeT NA NA Connect to ground. 18 TD+ V20, Y19, V22, Y23, AB12, AD12, AB9, AD9, T3, T5 TX_P_[0:9] 19 TD- V21, Y20, W22, Y22, AB11, AD11, AC9, AD10, U3, U5 TX_N_[0:9] 20 VeeT NA NA These pins are the differential transmitter inputs. They are AC-coupled differential lines with 100 differential termination inside the SFP module. The AC-coupling is done inside the SFP module and is not required on the host board. Connect to ground. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 100 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 33 6.7 Optical Module Connections to the IXF1110 MAC SFP-to-IXF1110 MAC Connection (Sheet 2 of 2) SFP Pin # SFP Pin Name IXF1110 MAC Pin # 0:9 IXF1110 MAC Pin Name N/A N/A B11 TX_FAULT_Int Connect to Interrupt Service Routine. Use an external 4.7 k pull-up resistor to 3.3 V. N/A N/A B14 RX_LOS_Int Connect to Interrupt Service Routine. Use an external 4.7 k pull-up resistor to 3.3 V. N/A N/A G15 MOD_DEF_Int Connect to Interrupt Service Routine. Use an external 4.7 k pull-up resistor to 3.3 V. Description Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 101 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.0 7.0 Electrical Specifications Electrical Specifications Table 34 through Table 49 on page 115 and Figure 32 on page 106 through Figure 43 on page 114 represent the target specifications of the following IXF1110 MAC interfaces: * Section 7.3, CPU Timing Specification * Section 7.4, JTAG Timing Specification * Section 7.5, Transmit Pause Control Timing Specifications * Section 7.6, Optical Module Interrupt and I2C Timing Specification * Section 7.7, System Timing Specifications * Section 7.8, LED Timing Specifications * Section 7.9, SerDes Timing Specification * Section 7.10, SPI4-2 Timing Specifications Note: These specifications are not guaranteed and are subject to change without notice. Minimum and maximum values listed in Table 34 through Table 49 on page 115 apply over the recommended operating conditions specified in Table 34. Table 34 Absolute Maximum Ratings Parameter Symbol Supply Voltage Operating Temperature Storage Temperature Caution: Ambient Case Min Max Units VDD -0.3 2.4 Volts AVDD1P8_1/ AVDD1P8_2 -0.3 2.4 Volts VDD2 -0.3 3.0 Volts AVDD2P5_1/ AVDD2P5_2 -0.3 3.0 Volts TOPA -15 +85 o +130 o +125 o TOPC TST - -65 C C C Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 102 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 35 7.0 Electrical Specifications Operating Conditions Symbol Min Typ1 Max Units VDD, AVDD1P8_1, AVDD1P8_2 1.71 1.80 1.89 Volts VDD2, AVDD2P5_1, AVDD2P5_2 2.375 2.50 2.625 Volts IDD and AIDD1P8_1, AIDD1P8_2 - 2.31 2.75 Amps IDD2 and AIDD2P5_1, AIDD2P5_2 - 0.310 0.42 Amps TOPA 0 - 70 o C C Parameter Recommended Supply Voltage Operating Current 1000BASE-SX Ambient Recommended Operating Temperature2 Case with Heat Sink TOPC-HS 0 - 119 o Case without Heat Sink TOPC-NHS 0 - 118 o C -65 - 40 o C Recommended Storage Temperature Power Consumption TOST 1000BASE-SX full-duplex all ports enabled and passing data P - 4.9 6.3 Watts 1000BASE-SX full-duplex six ports enabled and passing data P - 4.5 5.2 Watts 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. 2. Refer to the Cortina Systems(R) IXF1110 MAC Thermal Design Guidelines (document number 250289). Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 103 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.1 DC Specifications 7.1 DC Specifications Note: All 3.3 V LVTTL input buffers are 5 V tolerant and all 2.5 V CMOS input buffers are 3.3 V LVTTL level tolerant. Table 36 2.5 V CMOS and 3.3 V LVTTL I/O Electrical Characteristics Parameter Symbol Min Typ1 Max Units Comments 2.5 V CMOS I/O Cells 2.5 V I/Os Input High Voltage VIH 1.7 - - V Input Low Voltage VIL - - 0.7 V Output High Voltage VOH 2.0 - - V Output Low Voltag VOL - - 0.4 V Test Condition: VCC = MIN, IOL = 3.9 mA IOZ - - 10 A VCC = MAX Test Condition: VCC = MIN 2.5 V I/Os Test Condition: VCC = MIN 2.5 V I/Os Test Condition: VCC = MIN, IOH = -2.9 mA 2.5 V I/Os Output Leakage Current 3.3 V LVTTL I/O Cells 3.3 V LVTTL I/Os Input High Voltage VIH 2.0 - - V Input low Voltage VIL - - 0.8 V Output High voltage VOH 2.4 - - V Output low voltage VOL - - 0.4 V Test Condition: VCC = MIN, IOL = 3.9 mA IOZ - - 10 A VCC = MAX Test Condition: VCC = MIN 3.3 V LVTTL I/Os Test Condition: VCC = MIN 3.3 V LVTTL I/Os Test Condition: VCC = MIN, IOH = -2.9 mA 3.3 V LVTTL I/Os Output Leakage Current 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. 2. 3.3 V CMOS tolerant. Table 37 LVDS I/O Electrical Characteristics (Sheet 1 of 2) Symbol Min Typ1 Max Units Test Conditions VI -0.20 - VddMax+ 0.20 V - Differential Input Voltage |VID| 100 - - mV @ 400 MHz Input Common-Mode Current ICM - - - A LVDS Input VOS = 1.2 V Parameter Input Voltage Range 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 104 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 37 7.2 Undershoot/Overshoot Specifications LVDS I/O Electrical Characteristics (Sheet 2 of 2) Parameter Symbol Min Typ1 Max Units Test Conditions Threshold Hysteresis TH 25 - - mV - Differential Input Impedance RIN 85 100 115 Typical 100 Output Low Voltage VOL 0.95 - - V - Output High Voltage VOH - - 1.51 V - |VOD| 330 - 446 mV - Delta Differential Output Voltage (Complementary States) |VOD| - - 25 mV - Offset (Common-Mode) Voltage VOS 1.12 - 1.30 V - Output Leakage Current IOZ - - 10 A - Differential Output Voltage 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. 7.2 Undershoot/Overshoot Specifications The overshoot figures given in this section represent the maximum voltage that can be applied without affecting the reliability of the device (see Table 38). Caution: Exceeding these values will damage the device. Table 38 Undershoot/Overshoot Limits Ball Type Undershoot Overshoot 2.5 V CMOS -0.60 V 3.9 V 3.3 V LVTTL -0.60 V 5.5 V Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 105 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.3 CPU Timing Specification 7.3 CPU Timing Specification Figure 32 CPU Port Read Timing TCAS TCAH uPx_Add[10:0] uPx_Cs TCRR uPx_Rd TCRH uPx_Data[31:0] TCDRS TCDRH uPx_Rdy TCDRD Figure 33 CPU Port Write Timing TCAS TCAH uPx_Add[10:0] uPx_Cs TCWL uPx_Wr TCWH TCDWH uPx_Data[31:0] TCDWS TCYD uPx_Rdy TCDWD Table 39 CPU Timing Parameters (Sheet 1 of 2) Parameter Symbol Min Typ1 Max Units Test Conditions UPX_ADD[12:0], UPX_CS_L Setup Time TCAS 10 - - ns - UPX_ADD[12:0], UPX_CS_L Hold Time TCAH 10 - - ns - UPX_RDY_L Assertion to UPX_RD_L De-assertion TCRR 10 - - ns - UPX_RD_L High Width TCRH 24 (3x cycle) - - ns - 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 106 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 39 7.4 JTAG Timing Specification CPU Timing Parameters (Sheet 2 of 2) Parameter Symbol Min Typ1 Max Units Test Conditions UPX_DATA[31:0] to UPX_RDY_L Setup Time TCDRS 10 - - ns - UPX_DATA[31:0] to UPX_RD_L Hold Time TCDRH 8 - - ns - Read UPX_DATA[31:0] Driving Delay TCDRD 24 - 355 ns - UPX_WR_L Width TCWL 40 - - ns - UPX_RDY_L to UPX_WR_L Hold Time TCWH 16 - - ns - UPX_DATA[31:0] to UPX_WR_L Setup Time TCDWS 10 - - ns - UPX_RDY_L to UPX_DATA[31:0] Hold Time TCDWH 10 - - ns - UPX_DATA[31:0] Latching Delay TCDWD 8 - 40 ns - UPX_RDY_L Width in Write Cycle TCYD 24 - 40 ns - Read UPX_RDY_L de-assertion to UPX_WR_L Assertion TRTW 32 - - ns - Write UPX_RDY_L de-assertion to UPX_RD_L Assertion TWTR 32 - - ns - 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. 7.4 JTAG Timing Specification Figure 34 JTAG Timing Tjc Tjl TCLK Tjh Tjval TDO Tjsh TMS, TDI Tjsu Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 107 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 40 7.5 Transmit Pause Control Timing Specifications JTAG Timing Parameters Symbol Min Typ1 Max Units Test Conditions TCLK Cycle Time TJC 90 - - ns - TCLK High Time TJH 0.4 x TJC - 0.6 x TJC ns - TCLK Low Time Parameter TJL 0.4 x TJC - 0.6 x TJC ns - TCLK Falling Edge to TDO Valid TJVAL - - 25 ns - TMS/TDI Setup to TCLK TJSU 20 - - ns - TMS/TDI Hold from TCLK TJSH 5 - - ns - 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. 7.5 Transmit Pause Control Timing Specifications Figure 35 Transmit Pause Control Interface Tbtp TxPauseFr Tpw TxPauseAddr[3:0] Tsu Table 41 Thd Transmit Pause Control Interface Parameters Symbol Min Typ1 Max Units Test Conditions TXPAUSEFR Width TPW 16 - - ns - TXPAUSEADDR[3:0] Setup to TXPAUSEFR TSU 16 - - ns - TXPAUSEADDR[3:0] Hold from TXPAUSEFR THD 32 - - ns - TXPAUSEFR Pulse to Pulse TBTP 48 - - ns - Parameter 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 108 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.6 Optical Module Interrupt and I2C Timing Specification 7.6 Optical Module Interrupt and I2C Timing Specification Figure 36 Optical Module Interrupt Timing MOD_DEF_9:0 TX_FAULT_9:0 RX_LOS_9:0 Tdi MOD_DEF_Int TX_FAULT_Int RX_LOS_Int Table 42 Optical Module Interrupt Timing Parameters Parameter Symbol Min Typ1 Max Units Test Conditions Change of state on MOD_DEF_9:0 or TX_FAULT_9:0 or RX_LOS_9:0 to assertion (active Low) on MOD_DEF_Int or TX_FAULT_Int or RX_LOS_Int TDI 24 - - ns - 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. Figure 37 I2C Bus Timing tHIGH tF t LOW I2C_CLK t SU.STA t HD.STA tR tLOW t HD.DAT tSU.STO t SU.DAT I2C_DATA In tAA tDH t BUF I2C_DATA Out Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 109 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 38 7.6 Optical Module Interrupt and I2C Timing Specification I2C Write Cycle I2C_CLK 8th BIT I2C_DATA ACK WORD n t WR(1) STOP CONDITION Table 43 START CONDITION I2C AC Timing Characteristics Parameter Symbol Min Typ1 Max Units Test Conditions 100 kHz - Clock Frequency, SCL fSCL - - Clock Pulse Width Low tLOW 4.7 - s - Clock Pulse Width High tHIGH 4.0 - s - Noise Suppression tI - - 100 ns - Clock Low to Data Valid Out tAA 0.1 - 4.5 s - Time bus must be free before a new transmission starts tBUF 4.7 - - s - Start Hold Time tHD.STA 4.0 - - s - Start Setup Time tSU.STA 4.7 - - s - Data In Hold Time tHD.DAT 0 - - s - Data In Setup time tSU.DAT 200 - - ns - Inputs Rise Time tR - - 1.0 s - Inputs Fall Time tF - - 300 ns - Stop Setup Time tSU.STO 4.7 - - s - Data Out Hold Time tDH 100 - - ns - tWR - - 10 ms - Write Cycle Time o 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 110 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.7 System Timing Specifications 7.7 System Timing Specifications Figure 39 Hardware Reset Timing Trw _______ Sys_Res Trt CPU Access Table 44 Hardware Reset Timing Parameters Symbol Min Typ1 Max Units Test Conditions Reset Pulse Width TRW 100 - - ns - Reset Recovery Time TRT 4.11 - - ms - Parameter o 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 7.8 LED Timing Specifications Figure 40 LED Timing Tcyc Tlow LED_CLK Thi Tdatd LED_DATA Thatl Tlath LED_LATCH Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 111 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 45 7.9 SerDes Timing Specification LED Timing Parameters Parameter Symbol Min Typ1 Max Units Test Conditions2 LED_CLK Cycle Time TCYC 1.36 - 1.40 ms - LED_CLK High Time THI 680 - 700 s 50% duty cycle LED_CLK Low Time TLOW 680 - 700 s 50% duty cycle LED_CLK Falling Edge to LED_DATA Valid TDATD - - 5 ns - LED_CLK Rising Edge to LED_LATCH Falling Edge THATL - - 5 ns - LED_CLK Falling Edge to LED_LATCH Rising Edge TLATH - - 5 ns - 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. 2. Flash Rate = 100 ms, LED Mode 1. 7.9 SerDes Timing Specification Table 46 specifies the transmit electrical specifications based on a recommended 1.8 V AVDD1P8_1 and AVDD1P8_2 termination voltage and the required 50 termination and Table 46 specifies the receiver electrical specifications based on a recommended 1.8 V AVDD1P8_1 and AVDD1P8_2 termination voltage. Figure 41 illustrates the timing requirements for the IXF1110 MAC transmit and receive SerDes signals. Note: It is essential that both positive and negative drive levels at the receiver input maintain a minimum voltage of 0.8 V relative to ground to help ensure proper circuit operation. Figure 41 SerDes Timing Rv Tv Rt Tt Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 112 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 46 7.9 SerDes Timing Specification Transmitter Characteristics Parameter Symbol Transmit differential signal level Transmitter Common Mode Voltage Range Normalized Power Driver Setting Min Typ1 Max 0.50 180 230 325 1.00 350 440 700 1.33 425 580 900 2.00 600 770 1050 0.50 1300 1600 1940 1.00 1000 1400 1870 1.33 800 1300 1825 2.00 700 1100 1760 TV - Units Test Conditions mVpp diff AVDD1P8_1 and AVDD1P8_2 terminated to 1.8 V; Rload = 50 ; mV - - Transmit Eye Width TT 1.00 800 - - pS Differential signal rise/fall time - 1.00 60 96 132 pS Differential Output Impedance - - 60 100 150 diff DC Transmitter short circuit current - - -100 - 100 mA - Transmitter Frequency - - 1.2498 75 1.25 1.25012 5 GHz Reference Oscillator 125 MHz +/100 ppm Total Transmitter output jitter - - - - 122 pS p-p Total Jitter at BER 1E-12 Rload = 50 ; 20% to 80% max 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. Note: Refer to Table 21, SerDes Driver TX Power Levels, on page 69 for valid SerDes power levels. Table 47 Receiver Characteristics Symbol Min Typ1 Max Units Test Conditions RV 200 - - mVp-p diff - 900 1275 1650 mV - RT 280 - - pS - Receiver termination impedance - 40 - 62.5 W - Signal detect level - 125 - 400 mVp-p diff - pS p-p Total Jitter at BER 1E-12 Parameter Receiver differential voltage requirement at center of receive-eye Receiver common mode voltage range Receive Eye Width Total Receiver jitter tolerance - - - 600 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 113 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.10 SPI4-2 Timing Specifications 7.10 SPI4-2 Timing Specifications Figure 42 SPI4-2 Transmit FIFO Status Bus Timing TSCLK Td1 TSTAT[1:0] Td2 TSTAT[1:0] Table 48 SPI4-2 Transmit FIFO Status Bus Timing Parameters Symbol Min Typ1 Max Units Test Conditions TSCLK Falling Edge to TSTAT[1:0] Valid (Active edge flipped to falling) TD1 - - 280 pS - TSCLK Rising Edge to TSTAT[1:0] Valid (Default operation) T D2 - - 280 pS - Parameter 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. Figure 43 SPI4-2 Receive FIFO Status Bus Timing RSCLK Tsu1 RSTAT[1:0] Th1 Th2 RSTAT[1:0] Tsu2 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 114 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 49 7.10 SPI4-2 Timing Specifications SPI4-2 Receive FIFO Status Bus Timing Parameters Symbol Min Typ1 Max Units Test Conditions RSTAT[1:0] Setup to RSCLK Rising Edge (Default operation) TSU1 2 - - ns - RSTAT[1:0] Hold From RSCLK Rising Edge (Default operation) TH1 0.5 - - ns - RSTAT[1:0] Setup to RSCLK Falling Edge (When active edge flipped to falling) TSU2 2 - - ns - RSTAT[1:0] Hold From RSCLK Falling Edge (When active edge flipped to falling) TH2 0.5 - - ns - Parameter 1. Typical values are at 25 oC and are for design aid only; not guaranteed and not subject to production testing. Table 50 SPI4-2 LVDS Rise/Fall Times Parameter Rise/Fall at source Rise/Fall at sink Symbol Min Typ Max Units RTsrc - - 0.2 ns 400 Mhz operation - measured using conditions set forth in ANSI/TIA/EIA-644-A-2001 RTsnk - - 0.4 ns 400 Mhz operation - measured using conditions set forth in ANSI/TIA/EIA-644-A-2001 Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Test Conditions Page 115 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 8.0 Register Definitions 8.1 Introduction 8.0 Register Definitions This section provides information on the location and functionality of the IXF1110 MAC Control and Status Registers. 8.2 Document Structure This document is structured to give a general overview of the register map and an in-depth description of each bit of a register in later sections. 8.3 Graphical Representation Figure 44 represents an overview of the IXF1110 MAC Global Control Status Registers that are used to configure or report on all ports. Caution: Do not write to any reserved register unless specified. Writing to a reserved register address may cause improper device operation. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 116 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 44 8.4 Per Port Registers Memory Overview Global Configuration -RX Block Configuration -TX Block Configuraiton 0x7FF 0x500 Port 9 MAC Control & Statistics 0x480 Port 8 MAC Control & Statistics 0x400 Port 7 MAC Control & Statistics 0x380 Port 6 MAC Control & Statistics 0x300 Port 5 MAC Control & Statistics 0x280 Port 4 MAC Control & Statistics 0x200 Port 3 MAC Control & Statistics 0x180 Port2 MAC Control & Statistics 0x100 Port 1 MAC Control & Statistics 0x080 Port 0 MAC Control & Statistics 0x000 8.4 Per Port Registers The following section covers all of the registers that are replicated in each of the 10 ports in the IXF1110 MAC. These registers perform an identical function in each port. The address vector for the IXF1110 MAC is 11 bits wide. This allows for 7 bits of port-specific access and a 4-bit vector to address each port and all global registers. The address format is shown in Figure 45. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 117 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 45 8.5 Memory Map Register Overview 10 6 0 Port Select & Global Registers 8.5 Per-Port Registers Memory Map Table 51 through Table 59 on page 124 provide theIXF1110 MAC memory maps. A number of global control and status registers are used to configure or report on all ports, and some registers are replicated on a per-port basis. Note: All registers in the IXF1110 MAC are 32 bits. Table 51 MAC Control Register Map (Sheet 1 of 2) Register Bit Size Mode1 Ref Page Offset MAC Control Registers (Port Index + Offset) Station Address Low ($ Port_Index + 0x00) 32 R/W page 125 0x00 Station Address High ($ Port_Index + 0x01) 32 R/W page 125 0x01 Reserved 32 RO - 0x02 FDFC Type ($ Port_Index + 0x03) 32 R/W page 125 0x03 Reserved 32 R - 0x04 Reserved 32 RO - 0x05 Reserved 32 RO - 0X06 FC TX Timer Value ($ Port_Index + 0x07) 32 R/W page 125 0x07 FDFC Address Low ($ Port_Index + 0x08) 32 R/W page 126 0x08 FDFC Address High ($ Port_Index + 0x09) 32 R/W page 126 0x09 Reserved 32 R - 0x0A Reserved 32 R - Ox0B IPG Transmit Time ($ Port_Index + 0x0C) 32 R/W page 126 0x0C Reserved 32 R/W -- 0x0D Pause Threshold ($ Port_Index + 0x0E) 32 R/W page 127 0x0E Max Frame Size ($ Port_Index + 0x0F) 32 R/W page 127 0x0F Reserved 32 RO - 0x10 Reserved 32 RO - 0x11 FC Enable ($ Port_Index + 0x12) 32 R/W page 127 0x12 Reserved 32 RO - 0x13-0x1 4 Discard Unknown Control Frame ($ Port_Index + 0x15) 32 R/W page 128 0x15 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 118 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 51 8.5 Memory Map MAC Control Register Map (Sheet 2 of 2) Register Bit Size Mode1 Ref Page Offset MAC Control Registers (Port Index + Offset) RX Config Word ($ Port_Index + 0x16) 32 R/W page 128 0x16 TX Config Word ($ Port_Index + 0x17) 32 R/W page 129 0x17 Diverse Config ($ Port_Index + 0x18) 32 R/W page 129 0x18 RX Packet Filter Control ($ Port_Index + 0x19) 32 R/W page 131 0x19 Port Multicast Address Low ($ Port_Index + 0x1A) 32 R/W page 132 0x1A Port Multicast Address High ($ Port_Index + 0x1B) 32 R/W page 132 0x1B Mode1 Ref Page Offset 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 52 MAC RX Statistics Register Map (Sheet 1 of 2) Register Bit Size MAC RX Statistics Registers (Port Index + Offset) RXOctetsTotalOK 32 CoR page 133 0x20 RXOctetsBAD 32 CoR page 133 0x21 RXUCPckts 32 CoR page 133 0x22 RXMCPkts 32 CoR page 133 0x23 RXBCPkts 32 CoR page 133 0x24 RXPkts64Octets 32 CoR page 133 0x25 RXPkts65to127Octets 32 CoR page 133 0x26 RXPkts128to255Octets 32 CoR page 133 0x27 RXPkts256to511Octets 32 CoR page 133 0x28 RXPkts512to1023Octets 32 CoR page 133 0x29 RXPkts1024to1518Octets 32 CoR page 133 0x2A RXPkts1519toMaxOctets 32 CoR page 133 0x2B RXFCSErrors 32 CoR page 133 0x2C RXTagged 32 CoR page 133 0x2D RXDataError 32 CoR page 133 0x2E RXAlignErrors 32 CoR page 133 0x2F RXLongErrors 32 CoR page 133 0x30 RXJabberErrors 32 CoR page 133 0x31 RXPauseMacControlCounter 32 CoR page 133 0x32 RXUnknownMacControlFrameCounter 32 CoR page 133 0x33 RXVeryLongErrors 32 CoR page 133 0x34 RXRuntErrors 32 CoR page 133 0x35 RXShortErrors 32 CoR page 133 0x36 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 119 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 52 8.5 Memory Map MAC RX Statistics Register Map (Sheet 2 of 2) Register Bit Size Mode1 Ref Page Offset MAC RX Statistics Registers (Port Index + Offset) RXCarrierExtendError 32 CoR page 133 0x37 RXSequenceErrors 32 CoR page 133 0x38 RXSymbolErrors 32 CoR page 133 0x39 Mode1 Ref Page Offset 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 53 MAC TX Statistics Register Map Register Bit Size MAC TX Statistics Registers (Port Index + Offset) TXOctetsTotalOK 32 CoR page 137 0x40 TXOctetsBad 32 CoR page 137 0x41 TXUCPkts 32 CoR page 137 0x42 TXMCPkts 32 CoR page 137 0x43 TXBCPkts 32 CoR page 137 0x44 TXPkts64Octets 32 CoR page 137 0x45 TXPkts65to127Octets 32 CoR page 137 0x46 TXPkts128to255Octets 32 CoR page 137 0x47 TXPkts256to511Octets 32 CoR page 137 0x48 TXPkts512to1023Octets 32 CoR page 137 0x49 TXPkts1024to1518Octets 32 CoR page 137 0x4A TXPkts1519toMaxOctets 32 CoR page 137 0x4B TXDeferred 32 CoR page 137 0x4C TXTotalCollisions 32 CoR page 137 0x4D TXSingleCollisions 32 CoR page 137 0x4E TXMultipleCollisions 32 CoR page 137 0x4F TXLateCollisions 32 CoR page 137 0x50 TXExcessiveCollisionErrors 32 CoR page 137 0x51 TXExcessiveDeferralErrors 32 CoR page 137 0x52 TXExcessiveLengthDrop 32 CoR page 137 0x53 TXUnderrun 32 CoR page 137 0x54 TXTagged 32 CoR page 137 0x55 TXCRCError 32 CoR page 137 0x56 TXPauseFrames 32 CoR page 137 0x57 TXFlowControlCollisionsSend 32 CoR page 137 0x58 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 120 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 54 8.5 Memory Map Global Status and Configuration Register Map Register Bit Size Mode1 Ref Page Address Global Status and Configuration Registers Port Enable ($ 0x500) 32 R/W page 140 0x500 Reserved 32 R - 0x501 Link LED Enable ($ 0x502) 32 R/W page 141 0x502 Reserved 32 RO - 0x503 Core Clock Soft Reset ($ 0x504) 32 R/W page 141 0x504 MAC Soft Reset ($ 0x505) 32 R/W page 142 0x505 Reserved 32 RO - 0x506 Reserved 32 R - 0x507 CPU Interface ($ 0x508) 32 R/W page 142 0x508 LED Control ($ 0x509) 32 R/W page 143 0x509 LED Flash Rate ($ 0x50A) 32 R/W page 143 0x50A LED Fault Disable ($ 0x50B) 32 R/W page 143 0x50B JTAG ID Revision ($ 0x50C) 32 R/W page 144 0x50C Bit Size Mode1 Ref Page Address RX FIFO High Watermark Port 0 32 R/W page 145 0x580 RX FIFO High Watermark Port 1 32 R/W page 145 0x581 RX FIFO High Watermark Port 2 32 R/W page 145 0x582 RX FIFO High Watermark Port 3 32 R/W page 145 0x583 RX FIFO High Watermark Port 4 32 R/W page 145 0x584 RX FIFO High Watermark Port 5 32 R/W page 145 0x585 RX FIFO High Watermark Port 6 32 R/W page 145 0x586 RX FIFO High Watermark Port 7 32 R/W page 145 0x587 RX FIFO High Watermark Port 8 32 R/W page 145 0x588 RX FIFO High Watermark Port 9 32 R/W page 145 0x589 RX FIFO Low Watermark Port 0 32 R/W page 146 0x58A RX FIFO Low Watermark Port 1 32 R/W page 146 0x58B RX FIFO Low Watermark Port 2 32 R/W page 146 0x58C RX FIFO Low Watermark Port 3 32 R/W page 146 0x58D RX FIFO Low Watermark Port 4 32 R/W page 146 0x58E RX FIFO Low Watermark Port 5 32 R/W page 146 0x58F 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 55 RX Block Register Map (Sheet 1 of 2) Register RX Block Registers 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 121 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 55 8.5 Memory Map RX Block Register Map (Sheet 2 of 2) Bit Size Mode1 Ref Page Address RX FIFO Low Watermark Port 6 32 R/W page 146 0x590 RX FIFO Low Watermark Port 7 32 R/W page 146 0x591 RX FIFO Low Watermark Port 8 32 R/W page 146 0x592 RX FIFO Low Watermark Port 9 32 R/W page 146 0x593 RX FIFO Number of Frames Removed on Port 0 32 CoR page 147 0x594 RX FIFO Number of Frames Removed on Port 1 32 CoR page 147 0x595 RX FIFO Number of Frames Removed on Port 2 32 CoR page 147 0x596 RX FIFO Number of Frames Removed on Port 3 32 CoR page 147 0x597 RX FIFO Number of Frames Removed on Port 4 32 CoR page 147 0x598 RX FIFO Number of Frames Removed on Port 5 32 CoR page 147 0x599 Register RX Block Registers RX FIFO Number of Frames Removed on Port 6 32 CoR page 147 0x59A RXFIFO Number of Frames Removed on Port 7 32 CoR page 147 0x59B RX FIFO Number of Frames Removed on Port 8 32 CoR page 147 0x59C RX FIFO Number of Frames Removed on Port 9 32 CoR page 147 0x59D RX FIFO Port Reset ($ 0x59E) 32 R/W page 149 0x59E RX FIFO Errored Frame Drop Enable ($ 0x59F) 32 R/W page 150 0x59F RX FIFO Overflow Event ($ 0x5A0) 32 CoR page 152 0x5A0 Bit Size Mode1 Ref Page Address TX FIFO High Watermark Port 0 32 R/W page 153 0x600 TX FIFO High Watermark Port 1 32 R/W page 153 0x601 TX FIFO High Watermark Port 2 32 R/W page 153 0x602 TX FIFO High Watermark Port 3 32 R/W page 153 0x603 TX FIFO High Watermark Port 4 32 R/W page 153 0x604 TX FIFO High Watermark Port 5 32 R/W page 153 0x605 TX FIFO High Watermark Port 6 32 R/W page 153 0x606 TX FIFO High Watermark Port 7 32 R/W page 153 0x607 TX FIFO High Watermark Port 8 32 R/W page 153 0x608 TX FIFO High Watermark Port 9 32 R/W page 153 0x609 TX FIFO Low Watermark Port 0 32 R/W page 153 0x60A TX FIFO Low Watermark Port 1 32 R/W page 155 0x60B TX FIFO Low Watermark Port 2 32 R/W page 155 0x60C TX FIFO Low Watermark Port 3 32 R/W page 155 0x60D 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 56 TX Block Register Map (Sheet 1 of 2) Register 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 122 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 56 8.5 Memory Map TX Block Register Map (Sheet 2 of 2) Bit Size Mode1 Ref Page Address TX FIFO Low Watermark Port 4 32 R/W page 155 0x60E TX FIFO Low Watermark Port 5 32 R/W page 155 0x60F TX FIFO Low Watermark Port 6 32 R/W page 155 0x610 TX FIFO Low Watermark Port 7 32 R/W page 155 0x611 TX FIFO Low Watermark Port 8 32 R/W page 155 0x612 TX FIFO Low Watermark Port 9 32 R/W page 155 0x613 TX FIFO MAC Transfer Threshold Port 0 32 R/W page 157 0x614 TX FIFO MAC Transfer Threshold Port 1 32 R/W page 157 0x615 TX FIFO MAC Transfer Threshold Port 2 32 R/W page 157 0x616 TX FIFO MAC Transfer Threshold Port 3 32 R/W page 157 0x617 TX FIFO MAC Transfer Threshold Port 4 32 R/W page 157 0x618 TX FIFO MAC Transfer Threshold Port 5 32 R/W page 157 0x619 TX FIFO MAC Transfer Threshold Port 6 32 R/W page 157 0x61A TX FIFO MAC Transfer Threshold Port 7 32 R/W page 157 0x61B TX FIFO MAC Transfer Threshold Port 8 32 R/W page 157 0x61C TX FIFO MAC Transfer Threshold Port 9 32 R/W page 157 0x61D Register TX FIFO Overflow Event ($ 0x61E) 32 CoR page 159 0x61E Reserved 32 R - 0x61F TX FIFO Drain ($0x620) 32 R/W page 160 0x620 TX FIFO Info Out-of-Sequence ($ 0x621) 32 CoR page 161 0x621 TX FIFO Number of Frames Removed on Port 0 32 CoR page 162 0x622 TX FIFO Number of Frames Removed on Port 1 32 CoR page 162 0x623 TX FIFO Number of Frames Removed on Port 2 32 CoR page 162 0x624 TX FIFO Number of Frames Removed on Port 3 32 CoR page 162 0x625 TX FIFO Number of Frames Removed on Port 4 32 CoR page 162 0x626 TX FIFO Number of Frames Removed on Port 5 32 CoR page 162 0x627 TX FIFO Number of Frames Removed on Port 6 32 CoR page 162 0x628 TX FIFO Number of Frames Removed on Port 7 32 CoR page 162 0x629 TX FIFO Number of Frames Removed on Port 8 32 CoR page 162 0x62A TX FIFO Number of Frames Removed on Port 9 32 CoR page 162 0x62B 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 123 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 57 8.5 Memory Map SPI4-2 Block Register Map Bit Size Mode1 Ref Page Address SPI4-2 RX Burst Size ($ 0x700) 32 R/W page 162 0x700 SPI4-2 RX Training ($ 0x701) 32 R/W page 163 0x701 SPI4-2 RX Calendar ($ 0x702) 32 R/W page 164 0x702 SPI4-2 TX Synchronization ($ 0x703) 32 R/W page 165 0x703 Register 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 58 SerDes Block Register Map Bit Size Mode1 Ref Page Address Reserved 32 RO - 0x781 Reserved 32 RO - 0x782 Reserved 32 RO - 0x783 SerDes Tx Driver Power Level Ports 0-6 ($ 0x784) 32 RO - 0x784 SerDes Tx Driver Power Level Ports 7-9 ($ 0x785) 32 RO - 0x785 Reserved 32 RO - 0x786 SerDes TX and RX Power-Down Ports 0-9 ($ 0x787) 32 R/W page 16 6 0x787 Reserved 32 RO - 0x788-0x 792 Reserved 32 RO - 0x793 Reserved 32 RO - 0x794 Reserved 32 RO - 0x795 Reserved 32 RO - 0x796 Reserved 32 RO - 0x797 Reserved 32 RO - 0x798 Register 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 59 Optical Module Interface Block Register Map Bit Size Mode1 Ref Page Address Optical Module Status Ports 0-9 ($ 0x799) 32 R page 166 0x799 Optical Module Control Ports 0-9 ($ 0x79A) 32 R/W page 167 0x79A I C Control Ports 0-9 ($ 0x79B) 32 R/W page 168 0x79B I2C Data Ports 0-9 ($ 0x79C) 32 R/W page 168 0x79C Register 2 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 124 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 8.5.1 8.5 Memory Map MAC Control Registers Table 60 through Table 76 on page 132 provide details on the control and status registers associated with each MAC port. The register address is `Port_index + 0x**', where the port index is set at any value from 0x000 through 0x500. All registers are 32 bits. Table 60 Station Address Low ($ Port_Index + 0x00) Bit 31:0 Description Type1 Default Source MAC address bits 31-0. This address is inserted in the source address field when transmitting Pause frames, and is also used to compare against unicast Pause frames at the receiving side. R/W 0x00000000 Type1 Default R 0x0000 R/W 0x0000 Type1 Default R 0x0000 R/W 0x8808 Type1 Default R 0x0000 R/W 0x005E Name Station Address Low 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 61 Station Address High ($ Port_Index + 0x01) Bit Name Description 31:16 Reserved Reserved 15:0 Station Address High Source MAC address bits 47-32. This address is inserted in the source address field when transmitting Pause frames, and is also used to compare against unicast Pause frames at the receiving side. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 62 FDFC Type ($ Port_Index + 0x03) Bit 31:16 15:0 Name Description Reserved Reserved FDFC Type Contains the value of the type field transmitted in an internally generated flow control (pause) frame. Internally generated flow control frames are generated via the external pause interface or when the RX FIFO exceeds its high watermark. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 63 FC TX Timer Value ($ Port_Index + 0x07) Bit Name Description 31:16 Reserved Reserved 15:0 FC TX Timer Value The pause length sent to the receiving station in 512 bit times 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 125 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 64 8.5 Memory Map FDFC Address Low ($ Port_Index + 0x08) Bit 31:0 Name FDFC Address Low Description Contains the value of the lowest 32 bits of the destination address field transmitted in an internally generated flow control (pause) frame. Internally generated flow control frames are generated via the external pause interface or when the RX FIFO exceeds it high watermark. Type1 Default R/W 0xC2000001 Type1 Default R 0x0000 R/W 0x0180 Type1 Default R 0x0000 R/W 0x0008 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 65 FDFC Address High ($ Port_Index + 0x09) Bit 31:16 15:0 Name Description Reserved Reserved FDFC Address High Contains the value of the highest 16 bits of the destination address filed transmitted in an internally generated flow control (pause) frame. Internally generated flow control frames are generated via the external pause interface or when the RX FIFO exceeds it high watermark. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 66 IPG Transmit Time ($ Port_Index + 0x0C) Bit 31:10 Name Reserved Description Reserved IPG time for back-to-back transmissions (specified in multiples of 8 bit times). 9:0 IPG Transmit Time The value specified in this register is calculated as follows: (register value + 4) *8 = IPG length in terms of bit times. Therefore, the default value of 8 gives: (8+4) *8 = 96 bit times. 96 bit times is the minimum IPG. If a value of 8 or less is written to this register, the IPG remains 96 bit times. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 126 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 67 8.5 Memory Map Pause Threshold ($ Port_Index + 0x0E) Bit 31:16 15:0 Name Reserved Pause Threshold Description Reserved When a pause frame is sent, an internal timer checks when a new pause frame must be scheduled for transmission to keep the link partner in pause mode. The pause threshold value is the minimum time to send before the earlier pause frame is aged out (specified in multiples of 512 bit times). Type1 Default R 0x0000 R/W 0x002F Type1 Default R 0x0000 R/W 0x05EE Type1 Default Note: The value in this register is subtracted from the value in the FC TX Timer Value ($ Port_Index + 0x07) to set the internal pause threshold. This value determines how often a Pause frame is sent out to keep the link partner in pause mode. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 68 Max Frame Size ($ Port_Index + 0x0F) Bit Name 31:14 Reserved 13:0 Max Frame Size Description Reserved The maximum frame size the MAC can receive or transmit without activating any error counters, and without truncation. The maximum frame size is internally adjusted by +4 if VLAN is tagged. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 69 FC Enable ($ Port_Index + 0x12) Bit Name Description Register Description: Indicates which flow control mode is used for the RX and TX MAC. 31:2 1 0 Reserved Reserved 0x00000007 R 0x00000000 TX FDFC 0 = Disable TX full-duplex flow control [the MAC will not generate internally any flow control frames based on the RX FIFO watermarks or the Transmit Pause Control interface 1 = Enable TX full-duplex flow control [enables the MAC to send flow control frames to the link partner based on the RX FIFO programmable watermarks or the Transmit Pause Control interface] R/W 1 RX FDFC 0 = Disable RX full-duplex flow control [the MAC will not respond to flow control frames sent to it by the link partner] 1 = Enable RX full-duplex flow control [MAC will respond to flow control frames sent by the link partner and will stop packet transmission for the time specified in the flow control frame] R/W 1 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 127 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 70 8.5 Memory Map Discard Unknown Control Frame ($ Port_Index + 0x15) Bit 31:1 0 Name Description Reserved Reserved Discard Unknown Control Frame 0 = Keep unknown control frames 1 = Discard unknown control frames. Type1 Default R 0x00000000 R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 71 RX Config Word ($ Port_Index + 0x16) (Sheet 1 of 2) Bit Name Description Type1 Register Description: This register is used in the IXF1110 MAC only for auto-negotiation. Register bits 15:0 are the "config_word" received from the link partner, as described in IEEE 802.3, Sub clause 37.2.1. 31:22 21 Reserved An_complete Auto-negotiation complete. This bit remains cleared from the time auto-negotiation is reset until auto-negotiation reaches the "LINK_OK" state. It remains set until auto-negotiation is disabled or restarted. Default 0x00000000 RO 0 R 0 CoR 0 (This bit is only valid if auto-negotiation is enabled.) 20 RX Sync 0 = Loss of synchronization 1 = Bit synchronization (bit remains Low until register is read) 19 RX Config 0 = Receiving idle/data stream 1 = Receiving /C/ ordered sets 18 Config Changed 0 = RxConfigWord has changed since last read 1 = RxConfigWord has not changed since last read (This bit remains High until register is read) CoR 0 17 Invalid Word 0 = Have not received an invalid symbol 1 = Have received an invalid symbol (This bit remains High until register is read) CoR 0 16 Carrier Sense 0 = Device is not receiving idle characters (carrier sense is true). 1 = Device is receiving idle characters (carrier sense is false). R 0 15 Next Page Next Page request R 0 14 Reserved Reserved R 0 R 00 R Remote Fault Definitions: 00 = No error, link okay 13:12 RemoteFault[1:0] 01 = Offline 10 = Link failure 11 = Auto-negotiation_Error 11:9 Reserved Reserved R 000 8 Asym Pause Asym Pause (ability to send pause frames) R 0 7 Sym Pause Sym Pause (ability to send and receive pause frames) R 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 128 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 71 8.5 Memory Map RX Config Word ($ Port_Index + 0x16) (Sheet 2 of 2) Bit Name Type1 Description Default 6 Half Duplex Half-duplex R 0 5 Full Duplex Full-duplex R 0 Reserved Reserved R 00000 4:0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 72 TX Config Word ($ Port_Index + 0x17) Bit Name Description Type1 Register Description: This register is used in the IXF1110 MAC for auto-negotiation only. The contents of this register are sent as the config_word. 31:16 Reserved Reserved 15 NextPage 14 3 Reserved Default 0x000001A0 R 0x0000 Next Page request R/W 0 Write as 0, ignore on Read R/W 0 R/W 00 Remote fault definitions: 13:122 Remote Fault [1:0] 00 = No error, link okay 01 = Offline 10 = Link failure 11 = Auto-negotiation_Error Reserved3 Write as 0, ignore on Read R/W 000 8 Asym Pause Ability to send pause frames R/W 1 7 Sym Pause Ability to send and receive pause frames R/W 1 6 Half Duplex Half-duplex R/W 0 5 Full Duplex Full-duplex R/W 1 4:0 Reserved3 Write as 0, ignore on Read R/W 00000 11:9 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. There is no way to automatically update the state of the Remote Fault bits for transmission. The state of these bits must be set by the system controller through the uP interface prior to enabling auto-negotiation. 3. Reserved bits must be written to `0' to prevent illegal advertisement. Table 73 Diverse Config ($ Port_Index + 0x18) (Sheet 1 of 2) Bit Name Description Type1 Register Description: This register contains various configuration bits for general use. 31:19 Reserved Reserved Default 0x0000110D R 0x0000 Reserved 2 Write as 0, ignore on Read R/W 000000 Reserved 2 Write as 1, ignore on Read R/W 1 11:9 Reserved 2 Write as 0, ignore on Read R/W 000 8 Reserved2 Write as 1, ignore on Read R/W 1 7 pad_enable Enable padding of undersized packets R/W 0 6 crc_add Enable automatic CRC appending R/W 0 18:13 12 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. Reserved bits must be written to the default value for proper operation Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 129 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 73 8.5 Memory Map Diverse Config ($ Port_Index + 0x18) (Sheet 2 of 2) Bit 5 Name AN_enable 42 Description Auto-negotiation enable: 1 = Setting this bit to 1 puts the port in an auto-negotiation mode and starts auto-negotiation. 0 = Setting this bit to 0 disables auto-negotiation and puts the IXF1110 MAC in forced mode. Note: Since default = 0, this bit must be changed to a 1 via the CPU to enable auto-negotiation. Auto-negotiation can be restarted by de-asserting this bit, then re-asserting. Type1 Default R/W 0 Reserved Write as 0, ignore on Read R/W 0 3:2 Reserved Write as 1, ignore on Read R/W 11 2 Reserved Write as 0, ignore on Read R/W 0 2 Reserved Write as 1, ignore on Read R/W 1 2 1 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. Reserved bits must be written to the default value for proper operation Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 130 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 74 8.5 Memory Map RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2) Bit Name Description Type1 Register Description: This register allows for specific packet types to be marked for filtering, and is used in conjunction with the RX FIFO Errored Frames Drop Enable Register 31:6 Reserved Reserved Default 0x00000000 R 0x000000 R/W 0 R/W 0 R/W 0 This bit enables a Global filter on frames with a CRC Error. When CRCErrorPASS = 0, all frames with a CRC Error are marked as bad. 5 CRC Error Pass2 NOTE: When used in conjunction with the RX FIFO ErroredFrameDropEnable[9:0] Register (see RX FIFO Errored Frame Drop Enable ($ 0x59F)). This allows the frame to be dropped in the RX FIFO. Otherwise, the frame is sent across the SPI4-2 interface but marked as an EOP Abort frame. When the CRC Error Pass Filter bit = 0, it takes precedence over the other filter bits. Any packet regardless if it is a Pause, Unicast, Multicast or Broadcast packet with a CRC error will be marked as bad frames when CRC Error Pass = 0 When CRCErrorPASS = 1, frames with a CRC Error are not marked as bad and are passed to the SPI4-2 interface for transfer as good frames, regardless of the state of the FrameDropEn[9:0] bits. This bit enables a Global filter on Pause frames. When PauseFramePass = 0, all Pause frames are marked as bad. 4 Pause Frame Pass NOTE: When used in conjunction with the RX FIFO ErroredFrameDropEnable[9:0] Register (see RX FIFO Errored Frame Drop Enable ($ 0x59F)). This allows the frame to be dropped in the RX FIFO. Otherwise, the frame is sent across the SPI4-2 interface but marked as an EOP Abort frame. Note: When PauseFramePass = 1, all Pause frames are not marked as bad and are passed to the SPI4-2 interface for transfer as good frames, regardless of the state of the FrameDropEn[9:0] bits. This bit enables a Global filter on VLAN frames. 3 VLAN Drop En2 When VLANDropEn = 0, all VLAN frames are passed to the SPI4-2 Interface. When VLANDropEn = 1, all VLAN frames are dropped.3 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. Jumbo frames (1519 - 9600 bytes), matching the filter conditions, which would cause the frame to be dropped by the RX FIFO, will not be dropped. Instead, jumbo frames that are marked to be dropped by the RX FIFO, based on the filter setting in this register, will still be sent across the SPI4-2 interface, but will be marked as an EOP abort frame. Thus, jumbo frames matching the filter conditions will not be counted in the RX FIFO Number of Frames Removed Register because they are not removed by the RX FIFO. Only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be dropped by the RX FIFO and counted in the RX FIFO Number of Frames Removed. 3. Frames are dropped only when the appropriate bits are set in the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)). When the appropriate bits are not set, the frames are sent across the SPI4-2 interface and marked as EOP abort frames. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 131 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 74 8.5 Memory Map RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 2 of 2) Bit Name Description Type1 Default R/W 0 R/W 0 R/W 0 This bit enables a Global filter on Broadcast frames. 2 B/Cast Drop En2 When B/CastDropEn = 0, all broadcast frames are passed to the SPI4-2 Interface. When B/CastDropEn = 1, all broadcast frames are dropped.3 1 M/Cast Match En2 This bit enables a filter on multicast frames. If this bit = 0, all multicast frames are good and are passed to the SPI4-2 Interface. If this bit = 1, only multicast frames with a destination address that matches the PortMulticastAddress is forwarded. All other multicast frames are dropped.3 This bit enables a filter on unicast frames. If this bit = 0, all unicast frames are good and are passed to the SPI4-2 interface. 0 U/Cast Match En2 If this bit = 1, only unicast frames with a destination address that matches the Station Address is forwarded. All other unicast frames are dropped.3 Note: The VLAN filter overrides the Unicast filter. Thus, a VLAN frame cannot be filtered based on the Unicast address. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. Jumbo frames (1519 - 9600 bytes), matching the filter conditions, which would cause the frame to be dropped by the RX FIFO, will not be dropped. Instead, jumbo frames that are marked to be dropped by the RX FIFO, based on the filter setting in this register, will still be sent across the SPI4-2 interface, but will be marked as an EOP abort frame. Thus, jumbo frames matching the filter conditions will not be counted in the RX FIFO Number of Frames Removed Register because they are not removed by the RX FIFO. Only standard packet sizes (64 - 1518 bytes) meeting the filter conditions set in this register will actually be dropped by the RX FIFO and counted in the RX FIFO Number of Frames Removed. 3. Frames are dropped only when the appropriate bits are set in the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)). When the appropriate bits are not set, the frames are sent across the SPI4-2 interface and marked as EOP abort frames. Table 75 Port Multicast Address Low ($ Port_Index + 0x1A) Bit 31:0 Description Type1 Default This address is used to compare against multicast frames at the receiving side if multicast filtering is enabled. R/W 0x00000000 Type1 Default R 0x0000 R/W 0x0000 Name Port Multicast Address Low This register contains bits 31:0 of the address. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 76 Port Multicast Address High ($ Port_Index + 0x1B) Bit Name Description 31:16 Reserved Reserved 15:0 Port Multicast Address High This address is used to compare against multicast frames at the receiving side if Multicast filtering is enabled. This register contains bits 47:32 of the address. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 132 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 8.5.2 8.5 Memory Map MAC RX Statistics Register Overview The MAC RX Statistics Registers contain the MAC receiver statistic counters and are cleared when read. The software polls these registers and accumulates values to ensure that the counters do not wrap. The 32-bit counters wrap after approximately 30 seconds. Table 77 covers the MAC RX Statistics Registers for all 10 MAC ports. The address is identical to the port number. Table 77 MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet 1 of 4) Name RxOctetsTotalOK RxOctetsBAD2 Description Counts the bytes received in all legal frames, including all bytes from the destination MAC address to and including the CRC. The initial preamble and SFD bytes are not counted. Counts the bytes received in all bad frames of a size greater than or equal to 64 bytes. A bad frame is defined as a properly framed packet containing a CRC, alignment error, or code violation. The 64-byte value is measured from the destination address, up to and including CRC. The initial preamble and SFD are not included in this value. Address Type1 Default Port_Index + 0x20 CoR 0x00000000 Port_Index + 0x21 CoR 0x00000000 Port_Index + 0x22 CoR 0x00000000 Port_Index + 0x23 CoR 0x00000000 Note: This register does not increment the Bad Octet count on undersized receive packets. The total number of unicast packets received (excluding bad packets) RxUCPkts Note: This count includes non-pause control and VLAN packets, which are also counted in other counters. These packet types are counted twice. Take care when summing register counts for reporting MIB information. The total number of multicast packets received (excluding bad packets) RxMCPkts Note: This count includes pause control packets, which are also counted in the PauseMacControl-ReceivedCounter. These packet types are counted twice. Take care when summing register counts for reporting MIB information. RxBCPkts The total number of Broadcast packets received (excluding bad packets) Port_Index + 0x24 CoR 0x00000000 RxPkts64Octets The total number of packets received (including bad packets) that were 64 octets in length. Incremented for tagged packets with a length of 64 bytes, including tag field Port_Index + 0x25 CoR 0x00000000 RxPkts65to127 Octets The total number of packets received (including bad packets) that were [65-127] octets in length. Incremented for tagged packets with a length of 65 - 127 bytes, including tag field Port_Index + 0x26 CoR 0x00000000 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. When sending in large frames, the counters can only deal with certain limits. The behavior of the LongErrors and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*MaxFrameSize, dependent on where the MaxFrameSize variable is set. If MaxFrameSize sets greater than half of the available count in RxOctetsBad (2^14-1), VeryLongErrors is never incremented, but LongErrors is incremented. This is due to a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2^14-1. MaxFrameSize is determined by the settings in the Max Frame Size ($ Port_Index + 0x0F), on page 127. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 133 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 77 8.5 Memory Map MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet 2 of 4) Name Description Address Type1 Default RxPkts128to255 Octets The total number of packets received (including bad packets) that were [128-255] octets in length. Incremented for tagged packets with a length of 128-255 bytes, including tag field Port_Index + 0x27 CoR 0x00000000 RxPkts256to511 Octets The total number of packets received (including bad packets) that were [256-511] octets in length. Incremented for tagged packets with a length of 256 - 511 bytes, including tag field Port_Index + 0x28 CoR 0x00000000 RxPkts512to1023 Octets The total number of packets received (including bad packets) that were [512-1023] octets in length. Incremented for tagged packets with a length of 512 - 1023 bytes, including tag field Port_Index + 0x29 CoR 0x00000000 RxPkts1024to1518 Octets The total number of packets received (including bad packets) that were [1024-1518] octets in length. Incremented for tagged packet with a length between 1024-1522, including the tag Port_Index + 0x2A CoR 0x00000000 RxPkts1519toMax Octets The total number of packets received (including bad packets) that were >1518 octets in length. Incremented for tagged packet with a length between 1523-max frame size, including the tag Port_Index + 0x2B CoR 0x00000000 Port_Index + 0x2C CoR 0x00000000 Number of frames received with legal size, but with wrong CRC field (also called FCS field) RxFCSErrors Note: Legal size is 64 bytes through the value stored in the Max Frame Size ($ Port_Index + 0x0F). RxTagged Number of frames with VLAN tag (Type field = 0x8100) Port_Index + 0x2D CoR 0x00000000 RxDataError Number of frames received with legal length, containing a code violation (signaled with RX_ERR on RGMII) Note: The IXF1110 MAC does not support an RGMII interface; thus, this counter is not applicable to the IXF1110 MAC. Port_Index + 0x2E CoR 0x00000000 Port_Index + 0x2F CoR 0x00000000 Note: RxAlignErrors Number of frames with a legal frame size, but containing less than 8 additional bits. This occurs when a frame is not byte-aligned. The CRC of the frame is wrong when the additional bits are stripped. If the CRC is OK, the frame is not counted, but treated as an OK frame.The IXF1110 MAC does not support an RGMII interface; thus, this counter is not applicable to the IXF1110 MAC 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. When sending in large frames, the counters can only deal with certain limits. The behavior of the LongErrors and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*MaxFrameSize, dependent on where the MaxFrameSize variable is set. If MaxFrameSize sets greater than half of the available count in RxOctetsBad (2^14-1), VeryLongErrors is never incremented, but LongErrors is incremented. This is due to a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2^14-1. MaxFrameSize is determined by the settings in the Max Frame Size ($ Port_Index + 0x0F), on page 127. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 134 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 77 8.5 Memory Map MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet 3 of 4) Name Description Address Type1 Default Port_Index + 0x30 CoR 0x00000000 Port_Index + 0x31 CoR 0x00000000 Port_Index + 0x32 CoR 0x00000000 Frames bigger than the maximum allowed, with both OK CRC and the integral number of octets RxLongErrors2 Default maximum allowed is 1518 bytes untagged and 1522 bytes tagged, but the value can be changed by a register Frames bigger than the larger of 2*MaxFrameSize and 50000 bits are not counted here, but counted in the VeryLongError counter. RxJabberErrors Frames bigger than the maximum allowed, with either a bad CRC or a non-integral number of octets. The default maximum allowed is 1518 bytes untagged and 1522 bytes tagged, but the value can be changed by a register. Frames bigger than the larger of 2*MaxFrameSize and 50000 bits are not counted here, but counted in the VeryLongError counter. Number of Pause MAC control frames received RxPauseMac ControlCounter This statistic register increments on any valid 64byte Pause frame with valid CRC and will also increment on 64byte Pause Frames with an invalid CRC if bit 5 of the RX Packet Filter Control ($ Port_Index + 0x19) is set to 1. RxUnknownMac ControlFrame Counter Number of MAC control frames received with an op code different from 0001 (Pause) Port_Index + 0x33 CoR 0x00000000 RxVeryLongErrors2 Frames bigger than the larger of 2*MaxFrameSize and 50000 bits Port_Index + 0x34 CoR 0x00000000 Port_Index + 0x35 CoR 0x00000000 The total number of packets received that are less than 64 octets in length, but longer than or equal to 96 bit times. RxRuntErrors Note: RxRuntErrors is not supported in the IXF1110 MAC. Any runt or short packets received are not counted in this register. Note: The "ShortRuntsThreshold" Register controls the byte count used to determine the difference between Runts and Shorts, and therefore controls which counter is incremented for a given frame size. This counter is only updated after receipt of two good frames. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. When sending in large frames, the counters can only deal with certain limits. The behavior of the LongErrors and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*MaxFrameSize, dependent on where the MaxFrameSize variable is set. If MaxFrameSize sets greater than half of the available count in RxOctetsBad (2^14-1), VeryLongErrors is never incremented, but LongErrors is incremented. This is due to a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2^14-1. MaxFrameSize is determined by the settings in the Max Frame Size ($ Port_Index + 0x0F), on page 127. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 135 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 77 8.5 Memory Map MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet 4 of 4) Description Address Type1 Default The total number of packets received that are less than 96 bit times, which corresponds to a 4byte frame with a well formed preamble and SFD. This counter indicates fragment sizes illegal in all modes, and is only fully updated after reception of a good frame following a fragment. Port_Index + 0x36 CoR 0x00000000 Note: N/A - half-duplex only Port_Index + 0x37 CoR 0x00000000 RxSequenceErrors Records the number of sequencing errors that occur. Port_Index + 0x38 CoR 0x00000000 RxSymbolErrors Records the number of symbol errors encountered. The counter increments once for each packet that encounters symbol errors during reception. Symbol errors between packets are not counted. Port_Index + 0x39 CoR 0x00000000 Name RxShortErrors Note: RxShortErrors is not supported in the IXF1110 MAC. Any runt or short packets received are not counted in this register. RxCarrierExtend Error Gigabit half-duplex event only 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. When sending in large frames, the counters can only deal with certain limits. The behavior of the LongErrors and VeryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*MaxFrameSize, dependent on where the MaxFrameSize variable is set. If MaxFrameSize sets greater than half of the available count in RxOctetsBad (2^14-1), VeryLongErrors is never incremented, but LongErrors is incremented. This is due to a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD counter if the frame is larger than 2^14-1. MaxFrameSize is determined by the settings in the Max Frame Size ($ Port_Index + 0x0F), on page 127. 8.5.3 MAC TX Statistics Register Overview The MAC TX Statistics Registers contain all the MAC transmit statistic counters and are cleared when read. The software must poll these registers to accumulate values and ensure that the counters do not wrap. The 32-bit counters wrap after approximately 30 seconds. Table 78 covers the MAC TX Statistics Registers for all 10 MAC ports. The address is identical to the port number. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 136 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 78 8.5 Memory Map MAC TX Statistics ($ Port_Index + 0x40 - Port_Index + 0x58) (Sheet 1 of 3) Name TXOctetsTotalOK Description Address Type1 Default Counts the bytes transmitted in all legal frames. The count includes all bytes from the destination MAC address to and including the CRC. The initial preamble and SFD bytes are not counted. Port_Index + 0x40 CoR 0x00000000 Port_Index + 0x41 CoR 0x00000000 Port_Index + 0x42 CoR 0x00000000 Port_Index + 0x43 CoR 0x00000000 Counts the bytes transmitted in all bad frames. The count includes all bytes from the destination MAC address to and including the CRC. The initial preamble and SFD bytes are not counted. TXOctetsBad TX underrun counted: The count is expected to match the number of bytes actually transmitted before the frame is discarded. TX CRC error counted: All bytes not sent with success are counted by this counter TXUCPkts The total number of unicast packets transmitted (excluding bad packets) The total number of multicast packets transmitted (excluding bad packets) TXMCPkts Note: This count includes pause control packets which are also counted in the TxPauseFrames Counter. Thus, these types of packets are counted twice. Take care when summing register counts for reporting MIB information. TXBCPkts The total number of broadcast packets transmitted (excluding bad packets) Port_Index + 0x44 CoR 0x00000000 TXPkts64Octets The total number of packets transmitted (including bad packets) that were 64 octets in length. Incremented for tagged packets with a length of 64 bytes, including tag field Port_Index + 0x45 CoR 0x00000000 TXPkts65to127Octets The total number of packets transmitted (including bad packets) that were [65-127] octets in length. Incremented for tagged packets with a length of 65 - 127 bytes, including tag field Port_Index + 0x46 CoR 0x00000000 TXPkts128to255Octets The total number of packets transmitted (including bad packets) that were [128-255] octets in length. Incremented for tagged packets with a length of 128 - 255 bytes, including tag field Port_Index + 0x47 CoR 0x00000000 TXPkts256to511Octets The total number of packets transmitted (including bad packets) that were [256-511] octets in length. Incremented for tagged packets with a length of 256 - 511 bytes, including tag field Port_Index + 0x48 CoR 0x00000000 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 137 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 78 8.5 Memory Map MAC TX Statistics ($ Port_Index + 0x40 - Port_Index + 0x58) (Sheet 2 of 3) Description Address Type1 Default TXPkts512to1023Octets The total number of packets transmitted (including bad packets) that were [512 - 1023] octets in length. Incremented for tagged packets with a length of 512 - 1023 bytes, including tag field Port_Index + 0x49 CoR 0x00000000 TXPkts1024to1518Octets The total number of packets transmitted (including bad packets) that were [1024-1518] octets in length. Incremented for tagged packet with a length between 1024-1522, including the tag Port_Index + 0x4A CoR 0x00000000 TXPkts1519toMaxOctets The total number of packets transmitted (including bad packets) that were >1518 octets in length. Incremented for tagged packet with a length between 1523-max frame size, including the tag Port_Index + 0x4B CoR 0x00000000 Port_Index + 0x4C CoR 0x00000000 Port_Index + 0x4D CoR 0x00000000 Port_Index + 0x4E CoR 0x00000000 Port_Index + 0x4F CoR 0x00000000 Port_Index + 0x50 CoR 0x00000000 Name TXDeferred Number of times the initial transmission attempt of a frame is postponed due to another frame already being transmitted on the Ethernet network. Note: N/A - half-duplex only TXTotalCollisions TXSingleCollisions Sum of all collision events Note: N/A - half-duplex only A count of successfully transmitted frames on a particular interface where the transmission is inhibited by exactly one collision. A frame that is counted by an instance of this object is also counted by the corresponding instance of either the UnicastPkts, MulticastPkts, or BroadcastPkts, and is not counted by the corresponding instance of the MultipleCollisionFrames object. Note: N/A - half-duplex only TXMultipleCollisions A count of successfully transmitted frames on a particular interface for which transmission is inhibited by more than one collision. A frame that is counted by an instance of this object is also counted by the corresponding instance of either the UnicastPkts, MulticastPkts, or BroadcastPkts, and is not counted by the corresponding instance of the SingleCollisionFrames object. Note: N/A - half-duplex only TXLateCollisions The number of times a collision is detected on a particular interface later than 512 bit-times into the transmission of a packet. Such frame are terminated and discarded. Note: N/A - half-duplex only 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 138 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 78 8.5 Memory Map MAC TX Statistics ($ Port_Index + 0x40 - Port_Index + 0x58) (Sheet 3 of 3) Name Description Address Type1 Default TXExcessiveCollisionErrors A count of frames, which collides 16 times and is then discarded by the MAC. Not effecting xMultipleCollisions Port_Index + 0x51 CoR 0x00000000 Port_Index + 0x52 CoR 0x00000000 TXExcessiveLengthDrop Frame transmissions aborted by the MAC because the frame is longer than maximum frame size. These frames are truncated by the MAC when the maximum frame size violation is detected by the MAC. Port_Index + 0x53 CoR 0x00000000 TXUnderrun Internal TX error which causes the MAC to end the transmission before the end of the frame because the MAC did not get the needed data in time for transmission. The frames are lost and a fragment or a CRC error is transmitted. Port_Index + 0x54 CoR 0x00000000 TXTagged Number of OK frames with VLAN tag. (Type field = 0x8100). Port_Index + 0x55 CoR 0x00000000 TXCRCError Number of frames transmitted with a legal size, but with the wrong CRC field (also called FCS field) Port_Index + 0x56 CoR 0x00000000 TXPauseFrames Number of pause MAC frames transmitted Port_Index + 0x57 CoR 0x00000000 Port_Index + 0x58 CoR 0x00000000 Note: N/A - half-duplex only TXExcessiveDeferralErrors Number of times frame transmission is postponed more than 2*MaxFrameSize due to another frame already being transmitted on the Ethernet network. This causes the MAC to discard the frame. Note: N/A - half-duplex only TXFlowControlCollisions Send Collisions generated on purpose on incoming frames, to avoid reception of traffic, while the port is in half-duplex and has flow control enabled, and do not have sufficient memory to receive more frames. Note: Due to the internal counting technique, a last frame might have to be transmitted after last flow control collision send to get the correct statistic. Note: N/A - half-duplex only 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 8.5.4 Global Status and Configuration Register Overview Table 79 through Table 86 on page 143 provide an overview of the Global Control and Status Registers. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 139 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 79 8.5 Memory Map Port Enable ($ 0x500) Bit Name Description Type1 Register Description: A control register for each port in the IXF1110 MAC. Port ID = bit position in the register. To make a port active, the bit must be set High (for example, port 4 active implies register value = 0001.0000). Setting the bit to 0 disables the port. The default state for this register is for all 10 ports to be active. 31:10 Default 0x000003FF Reserved Reserved R 0x00000 9 Port 9 Enable Port 9 0 = Disable 1 = Enable R/W 1 8 Port 8 Enable Port 8 0 = Disable 1 = Enable R/W 1 7 Port 7 Enable Port 7 0 = Disable 1 = Enable R/W 1 6 Port 6 Enable Port 6 0 = Disable 1 = Enable R/W 1 5 Port 5 Enable Port 5 0 = Disable 1 = Enable R/W 1 4 Port 4 Enable Port 4 0 = Disable 1 = Enable R/W 1 3 Port 3 Enable Port 3 0 = Disable 1 = Enable R/W 1 2 Port 2 Enable Port 2 0 = Disable 1 = Enable R/W 1 1 Port 1 Enable Port 1 0 = Disable 1 = Enable R/W 1 0 Port 0 Enable Port 0 0 = Disable 1 = Enable R/W 1 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. If a port is disabled mid-packet on the receive side in SerDes mode, the RX Stats will not update for that packet due to power-down of SerDes when the port is disabled. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 140 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 80 8.5 Memory Map Link LED Enable ($ 0x502) Bit Name Description Type1 Register Description: Per-port bit should be set upon detection of link by system CPU to enable proper operation of the link LEDs. 31:10 Default 0x00000000 Reserved Reserved R 0x00000 9 Link LED Enable Port 9 Port 9 link 0 = No link 1 = Link R/W 0 8 Link LED Enable Port 8 Port 8 link 0 = No link 1 = Link R/W 0 7 Link LED Enable Port 7 Port 7 link 0 = No link 1 = Link R/W 0 6 Link LED Enable Port 6 Port 6 link 0 = No link 1 = Link R/W 0 5 Link LED Enable Port 5 Port 5 link 0 = No link 1 = Link R/W 0 4 Link LED Enable Port 4 Port 4 link 0 = No link 1 = Link R/W 0 3 Link LED Enable Port 3 Port 3 link 0 = No link 1 = Link R/W 0 2 Link LED Enable Port 2 Port 2 link 0 = No link 1 = Link R/W 0 1 Link LED Enable Port 1 Port 1 link 0 = No link 1 = Link R/W 0 0 Link LED Enable Port 0 Port 0 link 0 = No link 1 = Link R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 81 Core Clock Soft Reset ($ 0x504) Bit Name Description Type1 Register Description: A soft reset register for the core clock system (for example, the SYS125 clock). 31:1 Reserved Reserved 0 Core Soft Reset 0 = CoreSoftReset reset is inactive 1 = CoreSoftReset reset is active Default 0x00000000 R 0x00000000 R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 141 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 82 8.5 Memory Map MAC Soft Reset ($ 0x505) Bit Name Description Type1 Register Description: Per-port software activated reset of the MAC core. 31:10 Reserved Reserved 9 MAC Soft Reset Port 9 8 Default 0x00000000 R 0x00000 Port 9 0 = Reset inactive 1 = Reset active R/W 0 MAC Soft Reset Port 8 Port 8 0 = Reset inactive 1 = Reset active R/W 0 7 MAC Soft Reset Port 7 Port 7 0 = Reset inactive 1 = Reset active R/W 0 6 MAC Soft Reset Port 6 Port 6 0 = Reset inactive 1 = Reset active R/W 0 5 MAC Soft Reset Port 5 Port 5 0 = Reset inactive 1 = Reset active R/W 0 4 MAC Soft Reset Port 4 Port 4 0 = Reset inactive 1 = Reset active R/W 0 3 MAC Soft Reset Port 3 Port 3 0 = Reset inactive 1 = Reset active R/W 0 2 MAC Soft Reset Port 2 Port 2 0 = Reset inactive 1 = Reset active R/W 0 1 MAC Soft Reset Port 1 Port 1 0 = Reset inactive 1 = Reset active R/W 0 0 MAC Soft Reset Port 0 Port 0 0 = Reset inactive 1 = Reset active R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 83 CPU Interface ($ 0x508) Bit Name Description Type1 Register Description: CPU interface Endian select. This register allows the user to select the Endian of the CPU interface to allow various different CPUs to be connected to the IXF1110 MAC. 31:1 0 Reserved Reserved Endian 0 = Little Endian 1 = Big Endian Default 0x00000000 R 0x00000000 R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 142 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 84 8.5 Memory Map LED Control ($ 0x509) Bit Name Description Type1 Register Description: Globally selects and enables the LED mode. 31-2 Reserved Reserved 1 LED Enable 0 LED_SEL_MODE Default 0x00000000 R 0x00000000 0 = Disable LEDs 1 = Enable LEDs R/W 0 0 = Enable LED Mode 0 for use with SGS Thompson M5450 LED driver (Default) 1 = LED Mode 1 for use with Standard Octal Shift Register R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 85 LED Flash Rate ($ 0x50A) Bit Name Description Type1 Register Description: Globally selects and enables the flash rate. 31:3 2:0 Reserved Reserved LED Flash Rate 000 = 100 ms flash rate 001 = 200 ms flash rate 010 = 300 ms flash rate 011 = 400 ms flash rate 100 = 500 ms flash rate 101 = Reserved 110 = Reserved 111 = Reserved Default 0x00000000 R 0x00000000 R/W 000 Type1 Default 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 86 LED Fault Disable ($ 0x50B) (Sheet 1 of 2) Bit Name Description Register Description: Per-port fault disable: Disables the LED flashing for local or remote faults 31:10 Reserved Reserved 9 LED Fault Disable Port 9 8 0x00000000 R 0x000000 Port 9 0 = Fault enabled 1 = Fault disabled R/W 0 LED Fault Disable Port 8 Port 8 0 = Fault enabled 1 = Fault disabled R/W 0 7 LED Fault Disable Port 7 Port 7 0 = Fault enabled 1 = Fault disabled R/W 0 6 LED Fault Disable Port 6 Port 6 0 = Fault enabled 1 = Fault disabled R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 143 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 86 8.5 Memory Map LED Fault Disable ($ 0x50B) (Sheet 2 of 2) Type1 Default Port 5 0 = Fault enabled 1 = Fault disabled R/W 0 LED Fault Disable Port 4 Port 4 0 = Fault enabled 1 = Fault disabled R/W 0 3 LED Fault Disable Port 3 Port 3 0 = Fault enabled 1 = Fault disabled R/W 0 2 LED Fault Disable Port 2 Port 2 0 = Fault enabled 1 = Fault disabled R/W 0 1 LED Fault Disable Port 1 Port 1 0 = Fault enabled 1 = Fault disabled R/W 0 0 LED Fault Disable Port 0 Port 0 0 = Fault enabled 1 = Fault disabled R/W 0 Bit Name 5 LED Fault Disable Port 5 4 Description 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 87 JTAG ID Revision ($ 0x50C) Bit Name Description Type Register Description: The value of this register follows the same scheme as the device identification register found in the IEEE 1149.1 specification. The upper 4 bits correspond to silicon stepping. The next 16 bits store a Part ID Number. The next 11 bits contain a JEDEC Manufacturer ID. Bit zero = 1 if the chip is the first in a stack. The encoding scheme used for the Product ID field is implementation dependent. Default 0x40456013 31:28 Version2 Version2 R 0100 27:12 Part ID Part ID R 0000010001010110 11:8 JEDEC Cont. JEDEC Cont. R 0000 7:1 JEDEC ID JEDEC ID R 0001001 0 Reserved Reserved R 1 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. See the IXF1110 MAC Specification Update for the latest version. 8.5.5 Global RX Block Register Overview Table 88 through Table 93 on page 152 provide an overview of the RX Block Registers, which include the RX FIFO High and Low watermarks. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 144 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 88 8.5 Memory Map RX FIFO High Watermark Ports 0 to 9 ($ 0x580 - 0x589) Name2 Description Address Type1 Default RX FIFO High Watermark Port 0 High watermark for RX FIFO port 0. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x580 R/W 0x00000740 RX FIFO High Watermark Port 1 High watermark for RX FIFO port 1. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x581 R/W 0x00000740 RX FIFO High Watermark Port 2 High watermark for RX FIFO port 2. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x582 R/W 0x00000740 RX FIFO High Watermark Port 3 High watermark for RX FIFO port 3. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x583 R/W 0x00000740 RX FIFO High Watermark Port 4 High watermark for RX FIFO port 4. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x584 R/W 0x00000740 RX FIFO High Watermark Port 5 High watermark for RX FIFO port 5. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x585 R/W 0x00000740 RX FIFO High Watermark Port 6 High watermark for RX FIFO port 6. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x586 R/W 0x00000740 RX FIFO High Watermark Port 7 High watermark for RX FIFO port 7. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x587 R/W 0x00000740 RX FIFO High Watermark Port 8 High watermark for RX FIFO port 8. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC 0x588 R/W 0x00000740 RX FIFO High Watermark Port 9 High watermark for RX FIFO port 9. The default value is 1856 bytes. When the amount of data stored in the FIFO exceeds this value, a flow control command is sent to the corresponding TX MAC. 0x589 R/W 0x00000740 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. For all RX FIFO High Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:15 - Reserved and R. Bits 14:0 - Described above. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 145 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 89 8.5 Memory Map RX FIFO Low Watermark Ports 0 to 9 ($ 0x58A - 0x593) Name2 Description Address Type1 Default RX FIFO Low Watermark Port 0 Low watermark for RX FIFO port 0. The default value is 1840 bytes. When the port is in flow control, and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x58A R/W 0x00000730 RX FIFO Low Watermark Port 1 Low watermark for RX FIFO port 1. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x58B R/W 0x00000730 RX FIFO Low Watermark Port 2 Low watermark for RX FIFO port 2. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x58C R/W 0x00000730 RX FIFO Low Watermark Port 3 Low watermark for RX FIFO port 3. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x58D R/W 0x00000730 RX FIFO Low Watermark Port 4 Low watermark for RX FIFO port 4. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x58E R/W 0x00000730 RX FIFO Low Watermark Port 5 Low watermark for RX FIFO port 5. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x58F R/W 0x00000730 RX FIFO Low Watermark Port 6 Low watermark for RX FIFO port 6. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x590 R/W 0x00000730 RX FIFO Low Watermark Port 7 Low watermark for RX FIFO port 7. The default value is 1840 bytes.When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x591 R/W 0x00000730 RX FIFO Low Watermark Port 8 Low watermark for RX FIFO port 8. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x592 R/W 0x00000730 RX FIFO Low Watermark Port 9 Low watermark for RX FIFO port 9. The default value is 1840 bytes. When the port is in flow control and the amount of data stored in the FIFO goes below this value, the flow control command is terminated in the corresponding TX MAC. 0x593 R/W 0x00000730 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. For all RX FIFO Low Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:15 - Reserved and R. Bits 14:0 - Described above. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 146 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 90 8.5 Memory Map RX FIFO Number of Frames Removed Ports 0 to 9 ($ 0x594 - 0x59D) (Sheet 1 of 3) Name2 Description Address Type1 Default 0x594 CoR 0x00000000 0x595 CoR 0x00000000 0x596 CoR 0x00000000 0x597 CoR 0x00000000 This register counts all frames removed from the RX FIFO for port 0 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 0 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) This register counts all frames removed from the RX FIFO for port 1 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 1 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) This register counts all frames removed from the RX FIFO for port 2 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 2 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) This register counts all frames removed from the RX FIFO for port 3 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 3 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write. 2. For all Number of Frames Removed Registers, the following bit definitions apply to all ports (0:9): Bits 31:22 - Reserved and R. Bits 21:0 - Described above. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 147 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 90 8.5 Memory Map RX FIFO Number of Frames Removed Ports 0 to 9 ($ 0x594 - 0x59D) (Sheet 2 of 3) Name2 Description Address Type1 Default 0x598 CoR 0x00000000 0x599 CoR 0x00000000 0x59A CoR 0x00000000 This register counts all frames removed from the RX FIFO for port 4 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 4 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) This register counts all frames removed from the RX FIFO for port 5 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 5 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) This register counts all frames removed from the RX FIFO for port 6 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 6 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write. 2. For all Number of Frames Removed Registers, the following bit definitions apply to all ports (0:9): Bits 31:22 - Reserved and R. Bits 21:0 - Described above. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 148 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 90 8.5 Memory Map RX FIFO Number of Frames Removed Ports 0 to 9 ($ 0x594 - 0x59D) (Sheet 3 of 3) Name2 Description Address Type1 Default 0x59B CoR 0x00000000 0x59C CoR 0x00000000 0x59D CoR 0x00000000 This register counts all frames removed from the RX FIFO for port 7 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 7 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) This register counts all frames removed from the RX FIFO for port 8 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 8 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) This register counts all frames removed from the RX FIFO for port 9 by meeting one of the following conditions: * The RX FIFO on this port becomes full RX FIFO Number of Frames Removed on Port 9 * Frames are removed in conjunction with the RX FIFO Errored Frame Drop Enable Register (RX FIFO Errored Frame Drop Enable ($ 0x59F)) * Frames are greater than the MaxFrameSize (Max Frame Size ($ Port_Index + 0x0F)) 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write. 2. For all Number of Frames Removed Registers, the following bit definitions apply to all ports (0:9): Bits 31:22 - Reserved and R. Bits 21:0 - Described above. Table 91 RX FIFO Port Reset ($ 0x59E) (Sheet 1 of 2) Bit Name Description Type1 Register Description: The soft reset register for each port in the RX block. Port ID = bit position in the register. To make the reset active, the bit must be set High. For example, reset of port 4 implies register value = 0001.0000. Setting the bit to 0 de-asserts the reset. 31:10 Reserved Reserved 9 RXFIFOPort 9 Reset 8 RXFIFOPort 8 Reset Default 0x00000000 R 0x000000 Port 9 0 = De-assert reset 1 = Reset R/W 0 Port 8 0 = De-assert reset 1 = Reset R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 149 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 91 8.5 Memory Map RX FIFO Port Reset ($ 0x59E) (Sheet 2 of 2) Bit Name Description Type1 Default 7 RXFIFOPort 7 Reset Port 7 0 = De-assert reset 1 = Reset R/W 0 6 RXFIFOPort 6 Reset Port 6 0 = De-assert reset 1 = Reset R/W 0 5 RXFIFOPort 5 Reset Port 5 0 = De-assert reset 1 = Reset R/W 0 4 RXFIFOPort 4 Reset Port 4 0 = De-assert reset 1 = Reset R/W 0 3 RXFIFOPort 3 Reset Port 3 0 = De-assert reset 1 = Reset R/W 0 2 RXFIFOPort 2 Reset Port 2 0 = De-assert reset 1 = Reset R/W 0 1 RXFIFOPort 1 Reset Port 1 0 = De-assert reset 1 = Reset R/W 0 0 RXFIFOPort 0 Reset Port 0 0 = De-assert reset 1 = Reset R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 92 RX FIFO Errored Frame Drop Enable ($ 0x59F) (Sheet 1 of 3) Bit Name Description Type1 Register Description: This register is used in conjunction with the RX Packet Filter Control Register bits to select whether errored or filtered frames are to be dropped. 31:10 9 8 Reserved Reserved RX FIFO Errored Frame Drop Enable Port 9 These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. Port 9: 0 = Do not drop frames 1 = Drop frames RX FIFO Errored Frame Drop Enable Port 8 These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. Default 0x00000000 R 0x000000 R/W 0 R/W 0 Port 8: 0 = Do not drop frames 1 = Drop frames 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 150 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 92 8.5 Memory Map RX FIFO Errored Frame Drop Enable ($ 0x59F) (Sheet 2 of 3) Bit 7 6 5 4 3 Name RX FIFO Errored Frame Drop Enable Port 7 RX FIFO Errored Frame Drop Enable Port 6 RX FIFO Errored Frame Drop Enable Port 5 RX FIFO Errored Frame Drop Enable Port 4 RX FIFO Errored Frame Drop Enable Port 3 Description Type1 Default These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Port 7: 0 = Do not drop frames 1 = Drop frames These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. Port 6: 0 = Do not drop frames 1 = Drop frames These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. Port 5: 0 = Do not drop frames 1 = Drop frames These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. Port 4: 0 = Do not drop frames 1 = Drop frames These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. Port 3: 0 = Do not drop frames 1 = Drop frames 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 151 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 92 8.5 Memory Map RX FIFO Errored Frame Drop Enable ($ 0x59F) (Sheet 3 of 3) Bit 2 1 0 Description Type1 Default These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. R/W 0 R/W 0 R/W 0 Name RX FIFO Errored Frame Drop Enable Port 2 RX FIFO Errored Frame Drop Enable Port 1 RX FIFO Errored Frame Drop Enable Port 0 Port 2: 0 = Do not drop frames 1 = Drop frames These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. Port 1: 0 = Do not drop frames 1 = Drop frames These bits are used in conjunction with the RX Packet Filter Control ($ Port_Index + 0x19) bits, allowing the user to select whether errored or filtered frames are to be dropped or not. Port 0: 0 = Do not drop frames 1 = Drop frames 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 93 RX FIFO Overflow Event ($ 0x5A0) (Sheet 1 of 2) Bit Name Description Type1 Register Description: This register provides a status if a FIFO-full situation has occurred (for example, a FIFO overflow). The bit position equals the port number. This register is cleared on Read. 31:10 Default 0x00000000 Reserved Reserved R 0x000000 9 RX FIFO Overflow Event Port 9 Port 9 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 8 RX FIFO Overflow Event Port 8 Port 8 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 7 RX FIFO Overflow Event Port 7 Port 7 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 6 RX FIFO Overflow Event Port 6 Port 6 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 5 RX FIFO Overflow Event Port 5 Port 5 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 4 RX FIFO Overflow Event Port 4 Port 4 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 152 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 93 8.5 Memory Map RX FIFO Overflow Event ($ 0x5A0) (Sheet 2 of 2) Bit Name Description Type1 Default 3 RX FIFO Overflow Event Port 3 Port 3 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 2 RX FIFO Overflow Event Port 2 Port 2 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 1 RX FIFO Overflow Event Port 1 Port 1 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 0 RX FIFO Overflow Event Port 0 Port 0 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 8.5.6 TX Block Register Overview Table 94 through Table 100 on page 162 provide an overview of the TX Block Registers, which include the TX FIFO High and Low Watermark. Table 94 TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609) (Sheet 1 of 2) Name2 Address Type1 Default High watermark for TX FIFO port 0. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 0 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x600 R/W 0x00000630 High watermark for TX FIFO port 1. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 1 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x601 R/W 0x00000630 High watermark for TX FIFO port 2. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 2 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x602 R/W 0x00000630 High watermark for TX FIFO port 3. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 3 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x603 R/W 0x00000630 Description 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. For all TX FIFO High Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 153 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 94 8.5 Memory Map TX FIFO High Watermark Ports 0 to 9 ($ 0x600 - 0x609) (Sheet 2 of 2) Name2 Address Type1 Default High watermark for TX FIFO port 4. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 4 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x604 R/W 0x00000630 High watermark for TX FIFO port 5. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 5 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x605 R/W 0x00000630 High watermark for TX FIFO port 6. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 6 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x606 R/W 0x00000630 High watermark for TX FIFO port 7. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 7 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x607 R/W 0x00000630 High watermark for TX FIFO port 8. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 8 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x608 R/W 0x00000630 High watermark for TX FIFO port 9. The default value is 1584 bytes. When the amount of data stored in the FIFO exceeds this value, the TX TX FIFO High Watermark Port 9 FIFO indicates "SATISFIED." This implies further up in the system that no more data must be sent to this port. 0x609 R/W 0x00000630 Description 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. For all TX FIFO High Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 154 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 95 8.5 Memory Map TX FIFO Low Watermark Ports 0 to 9 ($ 0x60A - 0x613) (Sheet 1 of 2) Name2 Address Type1 Default Low watermark for TX FIFO port 0. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 0 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60A R/W 0x000001D0 Low watermark for TX FIFO port 1. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 1 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60B R/W 0x000001D0 Low watermark for TX FIFO port 2. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 2 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60C R/W 0x000001D0 Low watermark for TX FIFO port 3. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 3 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60D R/W 0x000001D0 Low watermark for TX FIFO port 4. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 4 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60E R/W 0x000001D0 Low watermark for TX FIFO port 5. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 5 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x60F R/W 0x000001D0 Low watermark for TX FIFO port 6. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 6 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x610 R/W 0x000001D0 Description 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. For all TX FIFO Low Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 155 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 95 8.5 Memory Map TX FIFO Low Watermark Ports 0 to 9 ($ 0x60A - 0x613) (Sheet 2 of 2) Name2 Address Type1 Default Low watermark for TX FIFO port 7. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 7 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x611 R/W 0x000001D0 Low watermark for TX FIFO port 8. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 8 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x612 R/W 0x000001D0 Low watermark for TX FIFO port 9. The default value is 464 bytes. When the amount of data falls below this value, the TX FIFO status TX FIFO Low Watermark Port 9 indicates "STARVING". This implies further up in the system that more data must be sent to this port to prevent an underrun. 0x613 R/W 0x000001D0 Description 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. For all TX FIFO Low Watermark Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 156 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 96 8.5 Memory Map TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D) (Sheet 1 of 2) Name2 TX FIFO MAC Transfer Threshold Port 0 Description3 Address Type1 Default 0x614 R/W 0x00000100 0x615 R/W 0x00000100 0x616 R/W 0x00000100 0x617 R/W 0x00000100 0x618 R/W 0x00000100 Sets the value at which the FIFO begins to transfer data to the MAC. The bottom 3 bits of this register are ignored, and the threshold is set in increments of 8-byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. TX FIFO MAC Transfer Threshold Port 1 Sets the value at which the FIFO begins to transfer data to the MAC. The bottom 3 bits of this register are ignored, and the threshold is set in increments of 8-byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. TX FIFO MAC Transfer Threshold Port 2 Sets the value at which the FIFO begins to transfer data to MAC. The bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. TX FIFO MAC Transfer Threshold Port 3 Sets the value at which the FIFO begins to transfer data to MAC. The bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. TX FIFO MAC Transfer Threshold Port 4 Sets the value at which the FIFO begins to transfer data to MAC. The bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. 3. For proper operation of the IXF1110 MAC, the MAC transfer threshold must be set to greater than the MaxBurst1 on the SPI4-2. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 157 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 96 8.5 Memory Map TX FIFO MAC Transfer Threshold Ports 0 to 9 ($ 0x614 - 0x61D) (Sheet 2 of 2) Name2 TX FIFO MAC Transfer Threshold Port 5 Description3 Address Type1 Default 0x619 R/W 0x00000100 0x61A R/W 0x00000100 0x61B R/W 0x00000100 0x61C R/W 0x00000100 0x61D R/W 0x00000100 Sets the value at which the FIFO begins to transfer data to MAC. The bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. TX FIFO MAC Transfer Threshold Port 6 Sets the value at which the FIFO begins to transfer data to MAC. The bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. TX FIFO MAC Transfer Threshold Port 7 Sets the value at which the FIFO begins to transfer data to MAC. The bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. TX FIFO MAC Transfer Threshold Port 8 Sets the value at which the FIFO begins to transfer data to the MAC. The bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. TX FIFO MAC Transfer Threshold Port 9 Sets the value at which the FIFO begins to transfer data to the MAC. The bottom 3 bits of this register are ignored, thus the threshold is set in increments of 8 byte steps. If this register is set above the standard packet size (including the 8-byte round-up), full packet transfers from the FIFO only are allowed. Transfer begins when either the count value in this register is exceeded or an End-of-Frame is received. 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. For all MAC Transfer Threshold Registers, the following bit definitions apply to all ports (0:9): Bits 31:13 - Reserved and R. Bits 12:0 - Described above. 3. For proper operation of the IXF1110 MAC, the MAC transfer threshold must be set to greater than the MaxBurst1 on the SPI4-2. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 158 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 97 8.5 Memory Map TX FIFO Overflow Event ($ 0x61E) Bit Name Description Type1 Register Description: This register provides status that a FIFO- full situation has occurred (for example, a FIFO overflow). The bit position equals the port number. Default 0x00000000 This register is cleared on Read. 31:10 Reserved 9 TX FIFO Overflow Event Port 9 8 Reserved R 0x000000 Port 9 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 TX FIFO Overflow Event Port 8 Port 8 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 7 TX FIFO Overflow Event Port 7 Port 7 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 6 TX FIFO Overflow Event Port 6 Port 6 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 5 TX FIFO Overflow Event Port 5 Port 5 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 4 TX FIFO Overflow Event Port 4 Port 4 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 3 TX FIFO Overflow Event Port 3 Port 3 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 2 TX FIFO Overflow Event Port 2 Port 2 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 1 TX FIFO Overflow Event Port 1 Port 1 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 0 TX FIFO Overflow Event Port 0 Port 0 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred CoR 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 159 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 98 8.5 Memory Map TX FIFO Drain ($0x620) Bit Name Description Type1 Register Description: This register enables the TX FIFO drain mode for the selected port by holding the TX FIFO for that port in reset. All data stored in the TX FIFO is lost when this bit is set to 1. When this bit is set to 1, the TX FIFO status for the selected port is STARVING. 31:10 Reserved Reserved 9 TX FIFO Drain Port 9 8 Default 0x00000000 R 0x000000 Port 9 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 TX FIFO Drain Port 8 Port 8 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 7 TX FIFO Drain Port 7 Port 7 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 6 TX FIFO Drain Port 6 Port 6 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 5 TX FIFO Drain Port 5 Port 5 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 4 TX FIFO Drain Port 4 Port 4 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 3 TX FIFO Drain Port 3 Port 3 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 2 TX FIFO Drain Port 2 Port 2 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 1 TX FIFO Drain Port 1 Port 1 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 0 TX FIFO Drain Port 0 Port 0 0 = Disable TX FIFO drain mode 1 = Enable TX FIFO drain mode R/W 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 160 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 99 8.5 Memory Map TX FIFO Info Out-of-Sequence ($ 0x621) Bit Name Description Type1 Register Description: This register signals when out-of-sequence data is detected in the TX FIFO. Events such as SOP followed by another SOP cause this bit to be set and remain so until read. This register is cleared on Read. 31:10 Reserved Reserved 9 TX FIFO Info Out-of-Sequenc e Port 9 8 Default 0x00000000 R 0x000000 Port 9 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 TX FIFO Info Out-of-Sequenc e Port 8 Port 8 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 7 TX FIFO Info Out-of-Sequenc e Port 7 Port 7 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 6 TX FIFO Info Out-of-Sequenc e Port 6 Port 6 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 5 TX FIFO Info Out-of-Sequenc e Port 5 Port 5 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 4 TX FIFO Info Out-of-Sequenc e Port 4 Port 4 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 3 TX FIFO Info Out-of-Sequenc e Port 3 Port 3 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 2 TX FIFO Info Out-of-Sequenc e Port 2 Port 2 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 1 TX FIFO Info Out-of-Sequenc e Port 1 Port 1 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 0 TX FIFO Info Out-of-Sequenc e Port 0 Port 0 0 = FIFO out-of-sequence event did not occur 1 = FIFO out-of-sequence event occurred CoR 0 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 161 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 100 8.5 Memory Map TX FIFO Number of Frames Removed Ports 0-9 ($ 0x622 - 0x62B) Name Description Address Type1 Default TX FIFO Number of Frames Removed on Port 0 This register counts the number of frames removed on port 0 due to a TX FIFO overflow. 0x622 CoR 0x00000000 TX FIFO Number of Frames Removed on Port 1 This register counts the number of frames removed on port 1 due to a TX FIFO overflow. 0x623 CoR 0x00000000 TX FIFO Number of Frames Removed on Port 2 This register counts the number of frames removed on port 2 due to a TX FIFO overflow. 0x624 CoR 0x00000000 TX FIFO Number of Frames Removed on Port 3 This register counts the number of frames removed on port 3 due to a TX FIFO overflow. 0x625 CoR 0x00000000 TX FIFO Number of Frames Removed on Port 4 This register counts the number of frames removed on port 4 due to a TX FIFO overflow. 0x626 CoR 0x00000000 TX FIFO Number of Frames Removed on Port 5 This register counts the number of frames removed on port 5 due to a TX FIFO overflow. 0x627 CoR 0x00000000 TX FIFO Number of Frames Removed on Port 6 This register counts the number of frames removed on port 6 due to a TX FIFO overflow. 0x628 CoR 0x00000000 TX FIFO Number of Frames Removed on Port 7 This register counts the number of frames removed on port 7 due to a TX FIFO overflow. 0x629 CoR 0x00000000 TX FIFO Number of Frames Removed on Port 8 This register counts the number of frames removed on port 8 due to a TX FIFO overflow. 0x62A CoR 0x00000000 TX FIFO Number of Frames Removed on Port 9 This register counts the number of frames removed on port 9 due to a TX FIFO overflow. 0x62B CoR 0x00000000 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 8.5.7 SPI4-2 Block Register Overview Table 101 through Table 104 on page 165 provide an overview of the SPI4-2 Block Registers. Table 101 SPI4-2 RX Burst Size ($ 0x700) (Sheet 1 of 2) Bit Name Description Type1 Register Description: SPI4-2 RX interface start-up parameters for burst size. 31 30:25 idles 0 = Zero idle insertion between transfer bursts 1 = Inserts four idle control words between each burst. (This occurs not only on an EOP, but also at the end of every MaxBurst1 or MaxBurst2. Reserved Reserved Default 0x00060002 R/W 0x0 R 0x00 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 162 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 101 8.5 Memory Map SPI4-2 RX Burst Size ($ 0x700) (Sheet 2 of 2) Bit 24:16 Name MaxBurst1 Description Maximum number of 16-byte blocks that the FIFO in the receive path, external to the IXF1110 MAC, can accept when the FIFO Status channel indicates STARVING. Note: 15:9 8:0 Default R/W 0x006 R 0x00 R/W 0x002 Type1 Default Do not program these bits below 0x2 (32 byte burst). Reserved Reserved MaxBurst2 Maximum number of 16-byte blocks that the FIFO in the receive path, external to the IXF1110 MAC, can accept when the FIFO Status channel indicates HUNGRY. Note: Type1 Do not program these bits below 0x2 (32 byte burst). 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 102 SPI4-2 RX Training ($ 0x701) Bit Name Description Register Description: SPI4-2 RX interface start-up parameters for training sequences 31:24 Reserved Reserved 23:16 REP_T DATA_MAX_T2 15:0 0x00000000 R 0x00 Number of repetitions of the data training sequence that must be scheduled every DATA_MAX_T cycles R/W 0x00 Maximum interval (in number of cycles) between scheduling of training sequences on receive data path interface An all zero value disables periodic training sequences. R/W 0x0000 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. The value of DATA_MAX_T is the Most Significant 16 bits of a 24-bit counter value. The Least Significant 8 bits are always 0x00. This allows for a much larger DAT_MAX_T time-out period and provides a more than adequate granularity of selection. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 163 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 103 8.5 Memory Map SPI4-2 RX Calendar ($ 0x702) Bit Name Description Type1 Register Description: SPI4-2 RX interface start-up parameters for FIFO status calendar operation. Default Value 0x00010300 00 = Normal mode 31:30 RX Train Test Modes 01 = Do not enter training based on a repeating "11" pattern on RSTAT[1:0] R/W 0x0 R/W 0 R/W 0 R 0x000 1x = Train continuously 29 RSCLK_invert 0 = The FIFO status is captured on the rising edge of the RSCLK as per the SPI4-2 specification 1 = The FIFO status is captured on the falling edge of RSCLK Note: For proper operation, set this bit to the desired setting before the RSCLK is applied to the device. TSCLK_invert 0 = The FIFO status is launched on the rising edge of the TSCLK as per the SPI4-2 specification 1 = The FIFO status is launched on the falling edge of TSCLK Reserved Reserved 20 DIP2_Error Set based on an incorrect RX DIP2 result. This bit is cleared upon a read CoR 0x0 19:16 DIP-2_Thr Defines how many consecutive correct DIP-2s are required to disable sending of training sequences on the RX SPI4-2. R/W 0x1 15:14 Reserved Reserved R 00 RX SPI4-2 Sync 0 = RX SPI4 In Training (RDAT = training) 1 = RX SPI4 Out Of Training (RDAT = idles) R 0 R 0 R/W 0x3 28 27:21 13 12 TX SPI4 Sync 0 = TX SPI4-2 Calendar is in constant Framing 1 = The TX SPI4-2 has received the valid training patterns on TDAT and is now sending a 10 port Calendar on TSAT with valid FIFO information 11:8 Loss_of_Sync Loss-of-Sync is a parameter specifying the number of consecutive framing calendar cycles required to indicate a loss of synchronization and restart training sequences. 7:4 Reserved Reserved 3:0 Reserved Write as 0, ignore on Read. R 0x0 R/W 0x0 1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 164 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 104 8.5 Memory Map SPI4-2 TX Synchronization ($ 0x703) Bit Name Description Type1 Register Description: SPI4-2 synchronization DIP-4 counters. Default 0x00000420 DIP4_Errors DIP4_Errors is the total number of DIP4 errors detected since this register was last read. CoR 0x0000 15:8 DIP4_UnLock2 DIP-4_Unlock is a SPI4-2 parameter specifying the number of incorrect DIP4 fields to be detected to declare loss of synchronization and drive the TSTAT[1:0] bus with framing. R/W 0x04 7:0 DIP4_Lock Number of consecutive correct DIP4 results to achieve synchronization and end training R/W 0x20 31:16 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 2. When Periodic Training is enabled, the actual count of DIP4 errors required to lose synchronization is 1 less than the programmed value in this register. Therefore, this value should always be programmed to be 1 more than the desired value and should never be programmed to either 0 or 1. 8.5.8 SerDes Register Overview Table 105 through Table 107 on page 166 define the contents of the SerDes Register Block at base location 0x780 which contain the control and status for the ten SerDes interfaces on the IXF1110 MAC. Table 105 SerDes Tx Driver Power Level Ports 0-6 ($ 0x784) Bit Name Description Type1 Register Description: Allows selection of various programmable drive strengths on each of the SerDes ports. Note: Refer to Table 21, SerDes Driver TX Power Levels, on page 69 for valid SerDes power levels. 31:28 Reserved 27:25 24:21 Reserved Default 0X00000000 R 0x0 DRVPWR6[3:0] Encoded input that sets Power Level for Port 6 R/W 1101 DRVPWR5[3:0] Encoded input that sets Power Level for Port 5 R/W 1101 20:16 DRVPWR4[3:0] Encoded input that sets Power Level for Port 4 R/W 1101 15:12 DRVPWR3[3:0] Encoded input that sets Power Level for Port 3 R/W 1101 11:8 DRVPWR2[3:0] Encoded input that sets Power Level for Port 2 R/W 1101 7:4 DRVPWR1[3:0] Encoded input that sets Power Level for Port 1 R/W 1101 3:0 DRVPWR0[3:0] Encoded input that sets Power Level for Port 0 R/W 1101 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 165 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 106 8.5 Memory Map SerDes Tx Driver Power Level Ports 7-9 ($ 0x785) Bit Name Description Type1 Register Description: Allows selection of various programmable drive strengths on each of the SerDes ports. Note: Refer to Table 21, SerDes Driver TX Power Levels, on page 69 for valid SerDes power levels. 31:12 Reserved Reserved Default 0X00000000 R 0x00000 11:8 DRVPWR9[3:0] Encoded input that sets Power Level for Port 9 R/W 1101 7:4 DRVPWR8[3:0] Encoded input that sets Power Level for Port 8 R/W 1101 3:0 DRVPWR7[3:0] Encoded input that sets Power Level for Port 7 R/W 1101 Type1 Default 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write Table 107 SerDes TX and RX Power-Down Ports 0-9 ($ 0x787) Bit Name Description Register Description: Tx and Rx power-down bits to allow per-port power-down of unused ports 31:20 0x00000000 Reserved Reserved R 0x000 19:10 TPWRDWN[9:0] Tx power-down for Ports 0-9 (1 = Power-down) R/W 0000000000 9:0 RPWRDWN[9:0] Rx power-down for Ports 0-9 (1 = Power-down) R/W 0000000000 1. R = Read Only; CoR = Clear on Read; W = Write; R/W = Read/Write 8.5.9 Optical Module Interface Block Register Overview Table 108 through Table 111 provide an overview of the Optical Module Interface Block Registers. These registers provide a means to control and monitor the interface to the optical modules. Table 108 Optical Module Status Ports 0-9 ($ 0x799) Bit Name Description Type1 Register Description: This register provides optical module status information. Default 0x00000000 31:30 Reserved Reserved R 00 29:20 RX_LOS_9:0 RX_LOS inputs for Ports 0-9 R 0000000000 19:10 TX_FAULT_9:0 TX_FAULT inputs for Ports 0-9 R 0000000000 9:0 MOD_DEF_9:0 MOD_DEF inputs for Ports 0-9 R 0000000000 1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 166 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 109 8.5 Memory Map Optical Module Control Ports 0-9 ($ 0x79A) Bit Name Description Type1 Register Description: This register provides access to optical module interrupt enables and sets the TX_DISABLE outputs. Default 0x00000000 R 0000000000 000000000 Enable for RX_LOS_Int operation 0 = Disabled 1 = Enabled R/W 0 TX_FAULT_En Enable for TX_FAULT_Int operation 0 = Disabled 1 = Enabled R/W 0 10 MOD_DEF_En Enable for MOD_DEF_Int operation 0 = Disabled 1 = Enabled R/W 0 9:0 TX_DISABLE_9:0 TX_DISABLE outputs for Ports 0-9 R/W 0000000000 31:13 Reserved Reserved 12 RX_LOS_En 11 1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write Table 110 I2C Control Ports 0-9 ($ 0x79B) (Sheet 1 of 2) Bit Name Description Type1 2 Register Description: This register controls I C Reads and Writes. 31:29 Default 0x00000000 Reserved Reserved R 000 Port Address Error Port Address Error is set to 1 when an access is requested to port address > 0x9. R 0 27 WP_Err Write Protect error is set to 1 when a write access is requested to Device ID = 0xA and Register Address [10:8] = 0. This address combination is used solely for the read only optical module. R 0 26 no_ack-err This bit is set to 1 when a optical module has failed to assert an acknowledge cycle. This signal should be used to validate the data being read. Data is only valid if this bit is equal to zero. R 0 25 I2CEnable Enables device wide I2C Accesses (Enabled = 1) R/W 0 CoR 0 28 2 2 24 I2C Start I C Start = 1 will initiate the I C cycle. This bit is clear on read. 23 Reserved Reserved R 0 22 Write Complete Write Complete is set to a 1 when the byte write cycle has completed. R 0 21 Reserved Reserved R 0 20 Read Valid Read Valid is set to a 1 when valid data is available in the DataRead7:0 field. R 0 Port Address Select 3:0 IXF1110 MAC port address to be accessed R/W 0x0 19:16 1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 167 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 110 8.5 Memory Map I2C Control Ports 0-9 ($ 0x79B) (Sheet 2 of 2) Bit Name 15 Read/Write 14:11 Device ID 10:0 Register Address Type1 Default 0 = Write 1 = Read R/W 1 Most significant 4 bits of Device ID/Address field. R/W 0xA Bits 10:8 define least significant 3 bits of Device ID/Address field. R/W 00000000000 Type1 Default Description Bits 7:0 define the register address. 1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write Table 111 I2C Data Ports 0-9 ($ 0x79C) Bit Name Description 2 Register Description: This register provides I C Reads and Writes. 31:24 Reserved Reserved 23:16 Write Data Write_Data contains the data to be written during the I2C byte write cycle. 15:8 Reserved Read_Data 7:0 0x00000000 R 0x00 R/W 0x00 Reserved R 0x00 Read_Data contains the byte received during the last I2C Read Cycle. R 0x00 1. R = Read Only; CoR = Clear on Read; W = Write only; R/W = Read/Write Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 168 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 9.0 9.0 Mechanical Specifications Mechanical Specifications CBGA packages are suited for applications requiring high I/O counts and high electrical performance. They are recommended for high-power applications, having high noise immunity requirements. 9.1 Features * Flip chip die attach; surface mount second-level interconnect * High electrical performance * High I/O counts * Area array I/O options * Multiple power zone offering supports core and four additional voltages * JEDEC-compliant package 9.2 IXF1110 MAC Package Specifics The IXF1110 MAC may use the RoHS Compliant packaging shown in Figure 46 on page 170 and Figure 47 on page 171 or non-RoHS compliant packaging shown in Figure 48 on page 172 and Figure 49 on page 173. There are minor differences between the two types of packages, but the general specifications for both types of packages are the same: * 575-pad BGA package with 23 balls removed for a total of 552 balls used measuring 25 mm x 25 mm * Ball pitch of 1.0 mm * Overall package dimensions of 25 mm x 25 mm Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 169 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 46 9.2 IXF1110 MAC Package Specifics RoHS Compliant CBGA Package Diagram (Side View) 552 Solder balls C4 Encapsulant Fillet Chip (0.6 Max) (0.4 Min) (2.48 Max) (2.02 Min) (0.908 Max) (0.779 Min) (3.08 Max) (2.42 Min) (3.988 Max) (3.199 Min) 0.2 C Seating Plane Note: All dimensions are in mm. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 170 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 RoHS Compliant CBGA Package Diagram (Bottom and Top View) (1.03 MAX) (0.37 MIN) (552X) o ( 0.7 0.01) o0.25 M C A S B S o0.10 M C (SAC SOLDERBA LL) (23) = Ball = No ball (23x) TYP (25 0.2) (Reference) Figure 47 9.2 IXF1110 MAC Package Specifics (23x) TYP 1 Chip Carrier A01 Corner (23) 2 B (25 0.2) Chip (25 0.2) 3.9 7.8 Substrate 3.9 7.8 (25 0.2) Note: All dimensions ar e in mm. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 171 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 48 9.2 IXF1110 MAC Package Specifics Non-RoHS Compliant CBGA Package Diagram (Side View) 552 Solder balls C4 Encapsulant Fillet Chip (0.91 Max) (0.71 Min) (2.48 Max) (2.02 Min) (0.857 Max) (0.779 Min) (4.247 Max) (3.509 Min) 0.15 C Seating Plane Note: All dimensions are in mm. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 172 IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Non-RoHS Compliant CBGA Package Diagram (Bottom and Top View) (0.91 MAX) (0.33 MIN) (552X) o ( 0.8 0.04) o 0.30 M C A S B S o 0.10 M C (SOLDER BALLS - 1mm PITCH) (552X BALLS. 23x DEPOP . TOTAL - 575X PADS (23) = Ball = No ball (23x) TYP (25 0.2) (Reference) Figure 49 9.2 IXF1110 MAC Package Specifics (23x) TYP 1 Chip Carrier A01 Corner (23) 2 B (25 0.2) Chip (25 0.2) 3.9 7.8 Substrate 3.9 7.8 (25 0.2) Note: All dimensions ar e in mm. Cortina Systems(R) IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Page 173 TM For additional product and ordering information: www.cortina-systems.com ~ End of Document ~