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FEATURES
APPLICATIONS
RELATED PRODUCTS
DESCRIPTION
ADS5444-EP
SGLS360 – AUGUST 2006
13-BIT 250-MSPS ANALOG-TO-DIGITAL CONVERTER
•TQFP-80 PowerPAD™ Package•Controlled Baseline •Pin Compatible With the ADS5440– One Assembly •Military Temperature Range = –55 °C to 125 °C– One Test Site
(1)
Component qualification in accordance with JEDEC andindustry standards to ensure reliable operation over an– One Fabrication Site
extended temperature range. This includes, but is not limitedto, Highly Accelerated Stress Test (HAST) or biased 85/85,•Extended Temperature Performance of –55 °C
temperature cycle, autoclave or unbiased HAST,to 125 °C
electromigration, bond intermetallic life, and mold compoundlife. Such qualification testing should not be viewed as•Enhanced Diminishing Manufacturing
justifying use of this component beyond specifiedSources (DMS) Support
performance and environmental limits.•Enhanced Product-Change Notification•Qualification Pedigree
(1)
•Test and Measurement•13-Bit Resolution
•Software-Defined Radio•250-MSPS Sample Rate
•Multichannel Base Station Receivers•SNR = 69 dBc at 100-MHz IF and 250 MSPS
•Base Station Tx Digital Predistortion•SFDR = 76 dBc at 100-MHz IF and 250 MSPS
•Communications Instrumentation•SNR = 67.7 dBc at 230-MHz IF and 250 MSPS•SFDR = 77 dBc at 230-MHz IF and 250 MSPS•2.2-V
PP
Differential Input Voltage
•ADS5424 - 14-Bit, 105 MSPS ADC•Fully Buffered Analog Inputs
•ADS5423 - 14-Bit, 80 MSPS ADC•5-V Analog Supply Voltage
•ADS5440 - 13-Bit, 210 MSPS ADC•LVDS Compatible Outputs•Total Power Dissipation: 2 W•Offset Binary Output Format
The ADS5444 is a 13-bit 250-MSPS analog-to-digital converter (ADC) that operates from a 5-V supply, whileproviding LVDS-compatible digital outputs from a 3.3-V supply. The ADS5444 input buffer isolates the internalswitching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generatoris also provided to further simplify the system design. The ADS5444 has outstanding low noise and linearity overinput frequency.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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Reference
Timing
CLK
OVR D[12:0]
CLK
5
DRY
VREF
AIN
AIN TH1
5 5
Σ
DAC2
ADC2
ADC3
Σ
DAC1
ADC1
AVDD DVDD
GND
Digital Error Correction
+
−
+
−
B0061-01
DRYOVR
A1 TH2 A2 A3TH3
ADS5444-EP
SGLS360 – AUGUST 2006
The ADS5444 is available in an 80-pin TQFP PowerPAD™ package. The ADS5444 is built on a state-of-the-artTexas Instruments complementary bipolar process (BiCom3X) and is specified over the full military temperaturerange (–55 °C to 125 °C).
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ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
(1)
ADS5444-EP
SGLS360 – AUGUST 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
PACKAGING/ORDERING INFORMATION
(1)
Product Package- Package Specified Package Ordering TransportLead Designator
(1)
Temperature Marking Number Media,Range Quantity
HTQFP-80
(2)ADS5444 PFP –55 °C to 125 °C ADS5444M-EP ADS5444MPFPEP Tray, 96PowerPAD
(1) For the most current product and ordering information, see the Package Option Addendum located at the end of this document, or seethe TI website at www.ti.com .(2) Thermal pad size: 7,5 mm x 7,5 mm (typ)
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE / UNIT
AV
DD
to GND 6 VSupply voltage
DRV
DD
to GND 5 VAnalog input to GND –0.3 V to AV
DD
+ 0.3 VClock input to GND –0.3 V to AV
DD
+ 0.3 VCLK to CLK ±2.5 VDigital data output to GND –0.3 V to DRV
DD
+ 0.3 VOperating temperature range –55 °C to 125 °CMaximum junction temperature 150 °CStorage temperature range –65 °C to 150 °CESD Human Body Model (HBM) 2.5 kV
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyondthose specified is not implied.
PARAMETER TEST CONDITIONS TYP UNIT
Soldered slug, no airflow 21.7 °C/WSoldered slug, 250-LFPM airflow 15.4 °C/Wθ
JA
Unsoldered slug, no airflow 50 °C/WUnsoldered slug, 250-LFPM airflow 43.4 °C/Wθ
JC
Bottom of package (heatslug) 2.99 °C/W
(1) Using 36 thermal vias (6 x 6 array). See the Application Section.
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0.1
1
10
100
1000
120 130 140 150 160 170 180
Wirebond Voiding Fail Mode
Electromigration Fail Mode
Continuous TJ − 5C
Years Estimated LIfe
ADS5444-EP
SGLS360 – AUGUST 2006
Figure 1. ADS5444MPFPEP Operating Life Derating Chart
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RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
ADS5444-EP
SGLS360 – AUGUST 2006
MIN NOM MAX UNIT
SUPPLIES
AV
DD
Analog supply voltage 4.75 5 5.25 VDRV
DD
Output driver supply voltage 3 3.3 3.6 V
ANALOG INPUT
Differential input range 2.2 V
PP
V
CM
Input common mode 2.4 V
CLOCK INPUT
1/t
C
ADCLK input sample rate (sine wave) 10 250 MSPSClock amplitude, differential sine wave 3 V
PP
Clock duty cycle 50%T
A
Open free-air temperature –55 125 °C
Min, Typ, and Max values at T
A
= 25 °C, full temperature range is T
MIN
= –55 °C to T
MAX
= 125 °C, sampling rate = 250 MSPS,50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, –1-dBFS differential input, and 3-V
PP
differential clock (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 13 Bits
ANALOG INPUTS
Differential input range 2.2 V
pp
Differential input resistance (DC) 1 k ΩDifferential input capacitance 1.5 pFAnalog input bandwidth 800 MHz
INTERNAL REFERENCE VOLTAGE
VREF Reference voltage 2.4 V
DYNAMIC ACCURACY
No missing codes AssuredDNL f
IN
= 10 MHz T
A
= 25 °C –1 ±0.4 1Differential linearity error LSBFull temp range –1 ±0.4 2INL f
IN
= 10 MHz T
A
= 25 °C –2.2 ±0.9 2.2Integral linearity error LSBFull temp range –4.3 ±2.7 4.3Offset error –11 11 mVOffset temperature coefficient 0.0005 mV/ °CGain error –5 5 %FSGain temperature coefficient –0.02 ∆%/ °CPSRR f
IN
= 100 MHz 1 mV/V
POWER SUPPLY
I
AVDD
Analog supply current 340 430 mAV
IN
= full scale, f
IN
= 100 MHz, F
S
= 250I
DRVDD
Output buffer supply current 80 100 mAMSPSPower dissipation 2 2.37 W
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ADS5444-EP
SGLS360 – AUGUST 2006
ELECTRICAL CHARACTERISTICS (continued)Min, Typ, and Max values at T
A
= 25 °C, full temperature range is T
MIN
= –55 °C to T
MAX
= 125 °C, sampling rate = 250 MSPS,50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, –1-dBFS differential input, and 3-V
PP
differential clock (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC AC CHARACTERISTICS
f
IN
= 10 MHz 69.3f
IN
= 70 MHz 69f
IN
= 100 MHz T
A
= 25 °C 67 69Full temp range 64.25 69SNR Signal-to-noise ratio dBcf
IN
= 170 MHz 68.3f
IN
= 230 MHz 67.7f
IN
= 300 MHz 67f
IN
= 400 MHz 66f
IN
= 10 MHz 85f
IN
= 70 MHz 77T
A
= 25 °C 70 77f
IN
= 100 MHz
Full temp range 64 77SFDR Spurious free dynamic range dBcf
IN
= 170 MHz 74f
IN
= 230 MHz 77f
IN
= 300 MHz 70f
IN
= 400 MHz 64f
IN
= 10 MHz 87f
IN
= 70 MHz 77f
IN
= 100 MHz 80HD2 Second harmonic f
IN
= 170 MHz 74 dBcf
IN
= 230 MHz 78f
IN
= 300 MHz 70f
IN
= 400 MHz 64f
IN
= 10 MHz 86f
IN
= 70 MHz 82f
IN
= 100 MHz 79HD3 Third harmonic f
IN
= 170 MHz 80 dBcf
IN
= 230 MHz 91f
IN
= 300 MHz 80f
IN
= 400 MHz 69f
IN
= 10 MHz 90f
IN
= 70 MHz 95f
IN
= 100 MHz 82Worst other harmonic/spur (other than
f
IN
= 170 MHz 80 dBcHD2 and HD3)
f
IN
= 230 MHz 83f
IN
= 300 MHz 86f
IN
= 400 MHz 85
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ADS5444-EP
SGLS360 – AUGUST 2006
ELECTRICAL CHARACTERISTICS (continued)Min, Typ, and Max values at T
A
= 25 °C, full temperature range is T
MIN
= –55 °C to T
MAX
= 125 °C, sampling rate = 250 MSPS,50% clock duty cycle, AV
DD
= 5 V, DRV
DD
= 3.3 V, –1-dBFS differential input, and 3-V
PP
differential clock (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
IN
= 10 MHz 69f
IN
= 70 MHz 68f
IN
= 100 MHz 67.6SINAD f
IN
= 170 MHz 66.5 dBcf
IN
= 230 MHz 67f
IN
= 300 MHz 65f
IN
= 400 MHz 61ENOB Effective number of bits f
IN
= 10 MHz 11.2 BitsRMS idle channel noise Inputs tied to common-mode 0.4 LSB
DIGITAL CHARACTERISTICS – LVDS DIGITAL OUTPUTS
Differential output voltage 0.247 0.452 VOutput offset voltage 1.125 1.25 1.375 V
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TIMING CHARACTERISTICS
N
N+1
N+2
N+3
N+4
NN−1N−2N−3
tA
tsu_c th_c
th_DR
N + 1
NN + 2 N + 3 N + 4
tC_DR
tCLK tCLKL
CLK, CLK
D[12:0],
OVR, OVR
DRY, DRY
AIN
tCLKH
tDR
tsu_DR
T0073-01
trtf
TIMING CHARACTERISTICS
ADS5444-EP
SGLS360 – AUGUST 2006
Figure 2. Timing Diagram
Min, Typ, Max over full temperature range, 50% clock duty cycle, sampling rate = 250 MSPS, AV
DD
= 5 V, DRV
DD
= 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
A
Aperture delay 500 pst
J
Clock slope independent aperture uncertainty (jitter) 200 fs RMSLatency 4 cycles
Clock Input
t
CLK
Clock period 4 nst
CLKH
Clock pulse width high 2 nst
CLKL
Clock pulse width low 2 ns
Clock to DataReady (DRY)
t
DR
Clock rising to DataReady falling 1.1 nst
C_DR
Clock rising to DataReady rising Clock duty cycle = 50%
(1)
2.7 3.1 3.5 ns
Clock to DATA, OVR
(2)
t
r
Data rise time (20% to 80%) 0.6 nst
f
Data fall time(80% to 20%) 0.6 nst
su_c
Data valid to clock (setup time) 3.1 nst
h_c
Clock to invalid Data (hold time) 0.2 ns
DataReady (DRY)/DATA, OVR
(2)
t
su(DR)
Data valid to DRY 1.7 2 nst
h(DR)
DRY to invalid Data 0.9 1.3 ns
(1) t
C_DR
= t
DR
+ t
CLKH
for clock duty cycles other than 50%(2) Data is updated with clock falling edge or DRY rising edge.
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DEVICE INFORMATION
2 3
GND
AVDD
GND
AVDD
GND
AVDD
GND
NC
GND
AVDD
GND
NC
GND
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
4
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
D5
D5
D6
D6
GND
DVDD
D7
D7
D8
D8
D9
D9
D10
D10
D11
D11
D12
D12
DRY
DRY 5 6 7 8
PFP PACKAGE
(TOP VIEW)
59 58 57 56 5560 54 52 51 5053
9 10 11 12 13
49 48
1
47 46 45 44
14 15 16 17 18 19 20
43 42 41
D4
D4
D3
D3
D2
D2
D1
D1
GND
DVDD
D0
D0
NC
NC
NC
NC
NC
NC
OVR
OVR
DVDD
GND
AVDD
NC
NC
VREF
GND
AVDD
GND
CLK
CLK
GND
AVDD
AVDD
GND
AIN
AIN
GND
AVDD
GND
GND
P0027-01
ADS5444-EP
SGLS360 – AUGUST 2006
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DEFINITION OF SPECIFICATIONS
ADS5444-EP
SGLS360 – AUGUST 2006
DEVICE INFORMATION (continued)TERMINAL FUNCTIONS
TERMINAL
DESCRIPTIONNAME NO.
3, 8, 13, 14, 19, 21,AVDD 23, 25, 27, 31, 35, 37, Analog power supply39DVDD 1, 51, 66 Output driver power supply2, 7, 9, 12, 15, 18, 20,GND 22, 24, 26, 28, 30, 32, Ground34, 36, 38, 40, 52, 65VREF 6 Reference voltageCLK 10 Differential input clock (positive). Conversion initiated on rising edge.CLK 11 Differential input clock (negative)AIN 16 Differential input signal (positive)AIN 17 Differential input signal (negative)Over range indicator LVDS output. A logic high signals an analog input in excess of theOVR, OVR 42, 41
full-scale range.D0, D0 50, 49 LVDS digital output pair, least-significant bit (LSB)D1–D6, D1– D6 53–64 LVDS digital output pairsD7–D11, D7– D11 67–76 LVDS digital output pairsD12, D12 78, 77 LVDS digital output pair, most-significant bit (MSB)DRY, DRY 80, 79 Data ready LVDS output pairNC 4, 5, 29, 33, 43–48 No connect
Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to thelow frequency value.
Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which thesampling occurs.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logichigh (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a percentage. Aperfect differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing isperformed at this sampling rate unless otherwise noted.
Minimum Conversion Rate The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart.The DNL is the deviation of any single step from this ideal value, measured in units of LSB.
Integral Nonlinearity (INL) The INL is the deviation of the ADCs transfer function from a best fit line determined by a leastsquares curve fit of that transfer function. The INL at each analog input value is the difference between theactual transfer function and this best fit line, measured in units of LSB.
Gain Error The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain error isgiven as a percentage of the ideal input full-scale range.
Offset Error Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode.
Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the value at thenominal temperature to the value at T
MIN
or T
MAX
. It is computed as the maximum variation the parametersover the whole temperature range divided by T
MIN
– T
MAX
.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (P
S
) to the noise floor power (P
N
), excludingthe power at dc and the first five harmonics.
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SNR +10log10 PS
PN
(1)
SINAD +10log10 PS
PN)PD
(2)
THD +10log10 PS
PD
(3)
ADS5444-EP
SGLS360 – AUGUST 2006
DEFINITION OF SPECIFICATIONS (continued)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as thereference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’sfull-scale range.
Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (P
S
) to the power of all theother spectral components including noise (P
N
) and distortion (P
D
), but excluding dc.
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used asthe reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’sfull-scale range.
Effective Resolution Bandwidth The highest input frequency where the SNR (dB) is dropped by 3 dB for a full-scale inputamplitude.
Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (P
S
) to the power of the first fiveharmonics (P
D
).
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f
1
, f
2
) to the powerof the worst spectral component at either frequency 2f
1
– f
2
or 2f
2
– f
1
). IMD3 is either given in units of dBc (dBto carrier) when the absolute power of the fundamental is used as the reference or dBFS (dB to full scale)when the power of the fundamental is extrapolated to the converter’s full-scale range.
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TYPICAL CHARACTERISTICS
Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
SFDR = 76.1 dBc
SNR = 69 dBc
THD = 72.6 dBc
SINAD = 67.4 dBc
Amplitude − dB
G002
Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Amplitude − dB
G004
SFDR = 77 dBc
SNR = 67.3 dBc
THD = 75.6 dBc
SINAD = 66.7 dBc
Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Amplitude − dB
G003
SFDR = 74.6 dBc
SNR = 68.4 dBc
THD = 72.5 dBc
SINAD = 67 dBc
ADS5444-EP
SGLS360 – AUGUST 2006
Spectral Performance Spectral Performance(FFT For 10 MHz Input Signal) (FFT For 100 MHz Input Signal)
Figure 3. Figure 4.
Spectral Performance Spectral Performance(FFT For 170 MHz Input Signal) (FFT For 230 MHz Input Signal)
Figure 5. Figure 6.
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Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Amplitude − dB
G005
SFDR = 70.2 dBc
SNR = 67 dBc
THD = 69.5 dBc
SINAD = 65 dBc
Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Amplitude − dB
G006
SFDR = 62.5 dBc
SNR = 66.2 dBc
THD = 61.8 dBc
SINAD = 60.4 dBc
Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Amplitude − dB
G008
FIN1 = 51.5 MHz, −16 dBFS
FIN2 = 52.5 MHz, −16 dBFS
IMD3 = 99.6 dBFS
ADS5444-EP
SGLS360 – AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Spectral Performance Spectral Performance(FFT For 300 MHz Input Signal) (FFT For 400 MHz Input Signal)
Figure 7. Figure 8.
Two-Tone Intermodulation Distortion Two-Tone Intermodulation Distortion(FFT For 51.5 MHz and 52.5 MHz Input Signals) (FFT For 51.5 MHz and 52.5 MHz Input Signals)
Figure 9. Figure 10.
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Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
FIN1 = 151 MHz, −7 dBFS
FIN2 = 152 MHz, −7 dBFS
IMD3 = 89.4 dBFS
Amplitude − dB
G009
Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
FIN1 = 151 MHz, −16 dBFS
FIN2 = 152 MHz, −16 dBFS
IMD3 = 92.5 dBFS
Amplitude − dB
G010
Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Amplitude − dB
G012
FIN1 = 229 MHz, −16 dBFS
FIN2 = 230 MHz, −16 dBFS
IMD3 = 101.4 dBFS
ADS5444-EP
SGLS360 – AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Two-Tone Intermodulation Distortion Two-Tone Intermodulation Distortion(FFT For 151 MHz and 152 MHz Input Signals) (FFT For 151 MHz and 152 MHz Input Signals)
Figure 11. Figure 12.
Two-Tone Intermodulation Distortion Two-Tone Intermodulation Distortion(FFT For 229 MHz and 230 MHz Input Signals) (FFT For 229 MHz and 230 MHz Input Signals)
Figure 13. Figure 14.
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Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Amplitude − dB
G013
FIN1 = 300 MHz, −7 dBFS
FIN2 = 301 MHz, −7 dBFS
IMD3 = 83.3 dBFS
Frequency − MHz
−120
−100
−80
−60
−40
−20
0
0 10 20 30 40 50 60 70 80 90 100 110 120
Amplitude − dB
G014
FIN1 = 300 MHz, −16 dBFS
FIN2 = 301 MHz, −16 dBFS
IMD3 = 101.9 dBFS
Code
−0.4
−0.2
0.0
0.2
0.4
50 1050 2050 3050 4050 5050 6050 7050 8050
fS = 250 MSPS
fIN = 10 MHz
Differential Nonlinearity − LSB
G018
ADS5444-EP
SGLS360 – AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Two-Tone Intermodulation Distortion Two-Tone Intermodulation Distortion(FFT For 300 MHz and 301 MHz Input Signals) (FFT For 300 MHz and 301 MHz Input Signals)
Figure 15. Figure 16.
Input Bandwidth Differential Nonlinearity
Figure 17. Figure 18.
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Code
−2.0
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
2.0
0 1000 2000 3000 4000 5000 6000 7000 8000
fS = 250 MSPS
fIN = 10 MHz
INL − Integral Nonlinearity − LSB
G019
Code Number
0
5
10
15
20
25
30
35
40
45
50
4109 4110 4111 4112 4113 4114 4115 4116
Percentage − %
G020
fS = 250 MSPS
Input Amplitude − dBFS
−40
−20
0
20
40
60
80
100
120
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
fS = 250 MSPS
fIN = 230 MHz
Performance − dB
G022
SFDR (dBFS)
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
ADS5444-EP
SGLS360 – AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Integral Nonlinearity Noise Histogram With Inputs Shorted
Figure 19. Figure 20.
AC Performance AC Performancevs vsInput Amplitude Input Amplitude
Figure 21. Figure 22.
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Input Amplitude − dBFS
−20
0
20
40
60
80
100
120
−110−100−90 −80 −70 −60 −50 −40 −30 −20 −10 0
fS = 250 MSPS
fIN = 100 MHz
SFDR − Spurious-Free Dynamic Range − dB
G023
SFDR (dBFS)
90 dBFS Line
SFDR (dBc)
Duty Cycle − %
60.0
62.5
65.0
67.5
70.0
72.5
75.0
77.5
80.0
0 20 40 60 80 100
fS = 250 MSPS
SFDR − Spurious-Free Dynamic Range − dBc
G024
fIN = 100 MHz
fIN = 230 MHz
Clock Amplitude − VP−P
60
61
62
63
64
65
66
67
68
69
70
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SNR − Signal-to-Noise Ratio − dBc
G026
fIN = 100 MHz
fIN = 230 MHz
fS = 250 MSPS
Clock Amplitude − VP−P
60
62
64
66
68
70
72
74
76
78
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SFDR − Spurious-Free Dynamic Range − dBc
G025
fS = 250 MSPS
fIN = 100 MHz
fIN = 230 MHz
ADS5444-EP
SGLS360 – AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Two-Tone Spurious Free Dynamic Range Spurious Free Dynamic Rangevs vsInput Amplitude Clock Duty Cycle
Figure 23. Figure 24.
Spurious Free Dynamic Range Signal-to-Noise Ratiovs vsClock Level Clock Level
Figure 25. Figure 26.
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AVDD − Supply Voltage − V
68
69
70
71
72
73
74
4.65 4.75 4.85 4.95 5.05 5.15 5.25 5.35
SFDR − Spurious-Free Dynamic Range − dBc
G028
fS = 250 MSPS
fIN = 100 MHz
TA = −40°C
TA = 0°C
TA = 25°C
TA = 65°C
TA = 85°C
DRVDD − Supply Voltage − V
69.0
69.5
70.0
70.5
71.0
71.5
72.0
72.5
2.9 3.1 3.3 3.5 3.7
SFDR − Spurious-Free Dynamic Range − dBc
G030
fS = 250 MSPS
fIN = 100 MHz
TA = −40°C
TA = 0°C
TA = 25°C
TA = 65°CTA = 85°C
AVDD − Supply Voltage − V
67.0
67.5
68.0
68.5
69.0
69.5
70.0
4.65 4.75 4.85 4.95 5.05 5.15 5.25 5.35
SNR − Signal-to-Noise Ratio − dBc
G029
fS = 250 MSPS
fIN = 100 MHz
TA = 0°C
TA = 65°C
TA = −40°C
TA = 85°C
TA = 25°C
ADS5444-EP
SGLS360 – AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Performance Spurious Free Dynamic Rangevs vsClock Common Mode Level AVDD Across Temperature
Figure 27. Figure 28.
Signal-to-Noise Ratio Spurious Free Dynamic Rangevs vsAVDD Across Temperature DRVDD Across Temperature
Figure 29. Figure 30.
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50 100 150
69 68.5
67.5
69.5
68
67
66.5
66 65.5
200
f -InputFrequency-MHz
IN
f-SamplingFrequency-MHz
S
SNR-dBc
250 300 350 400
50
100
150
200
250
300
64
63 65 66 67 68 69
M0048-05
ADS5444-EP
SGLS360 – AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
Signal-to-Noise RatiovsDRVDD Across Temperature
Figure 31.
SNR
vsInput Frequency and Sampling Frequency
Figure 32.
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50 100 150
89
89
89
83
83
83
80
80
77
77
77
83
80
86
86
86 77
71 71
80
71
71
74
74
74
74
68
68
65 68
68
68
200
f -InputFrequency-MHz
IN
f-SamplingFrequency-MHz
S
SFDR-dBc
250 300 350 400
50
100
150
200
250
300
M0048-06
65 70 75 80 85
ADS5444-EP
SGLS360 – AUGUST 2006
TYPICAL CHARACTERISTICS (continued)SFDR
vsInput Frequency and Sampling Frequency
Figure 33.
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APPLICATION INFORMATION
Theory of Operation
Input Configuration
ADT1-1WT
1 : 1 AIN
AIN
ADS5444
AC Signal
Source
R0
50 W
Z0
50 W
R
50 W
RT
100 Ω
+
−
OPA695
5 V
R1
400 Ω
ADS5444
CIN
RIN
0.1 µF1:1
−5 V
R2
57.5 Ω
VIN
AV = 8V/V
(18 dB)
RS
100 Ω
1000 µF
RIN AIN
AIN
ADS5444-EP
SGLS360 – AUGUST 2006
The ADS5444 is a 13-bit, 250-MSPS, monolithic pipeline analog-to-digital converter (ADC). Its bipolar analogcore operates from a 5 V supply, while the output uses a 3.3-V supply to provide LVDS compatible outputs. Theconversion process is initiated by the rising edge of the external input clock. At that instant, the differential inputsignal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a seriesof small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and thefalling clock edges are used to propagate the sample through the pipeline every half clock cycle. This processresults in a data latency of four clock cycles, after which the output data is available as a 13-bit parallel word,coded in offset binary format.
The analog input for the ADS5444 consists of an analog differential buffer followed by a bipolar T&H. Theanalog buffer isolates the source driving the input of the ADC from any internal switching. The input commonmode is set internally through a 500- Ωresistor connected from 2.4 V to each of the inputs. This results in adifferential input impedance of 1 k Ω.
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swingssymmetrically between 2.4 + 0.55 V and 2.4 – 0.55 V. This means that each input has a maximum signal swingof 1.1 V
PP
for a total differential input signal swing of 2.2 V
PP
. The maximum swing is determined by the internalreference voltage generator eliminating the need for any external circuitry for this purpose.
The ADS5444 obtains optimum performance when the analog inputs are driven differentially. The circuit inFigure 34 shows one possible configuration using an RF transformer with termination either on the primary or onthe secondary of the transformer. If voltage gain is required, a step up transformer can be used. For voltagegains that would require an impractical transformer turn ratio, a single-ended amplifier driving the transformer isshown in Figure 35 ).
Figure 34. Converting a Single-Ended Input to a Differential Signal Using RF Transformers
Figure 35. Using the OPA695 With the ADS5444
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18 pF
13-Bit
250 MSPS
AIN
AIN VREF
ADS5444
+5V
THS4509
CM
348 Ω
348 Ω
100 Ω
100 Ω
78.9 Ω
VIN
From
50 Ω
Source
49.9 Ω
49.9 Ω
78.9 Ω49.9 Ω
49.9 Ω
0.22 µF0.22 µF0.1 µF0.1 µF
0.22 µF
Clock Inputs
CLK
ADS5444
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
ADS5444-EP
SGLS360 – AUGUST 2006
Application Information (continued)
Figure 36. Using the THS4509 With the ADS5444
Besides the OPA695, TI offers a wide selection of single-ended operational amplifiers that can be selecteddepending on the application. An RF gain block amplifier, such as the TI THS9001, can also be used with an RFtransformer for high input frequency applications. For applications requiring dc-coupling with the signal source, adifferential input/differential output amplifier like the THS4509 (see Figure 36 ) is a good solution, as it minimizesboard space and reduces the number of components.
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input todifferential, and sets the proper input common-mode voltage to the ADS5444.
The 50- Ωresistors and 18-pF capacitor between the THS4509 outputs and ADS5444 inputs (along with theinput capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB).
Input termination is accomplished via the 78.9- Ωresistor and 0.22- µF capacitor to ground in conjunction with theinput impedance of the amplifier circuit. A 0.22- µF capacitor and 49.9- Ωresistor is inserted to ground across the78.9- Ωresistor and 0.22- µF capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348- Ωfeedback resistor. See the THS4509 datasheet for further component values to set proper 50- Ωtermination for other common gains.
Since the ADS5444 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a singlepower supply input with V
S+
= 5 V and V
S–
= 0 V (ground). This maintains maximum headroom on the internaltransistors of the THS4509.
The ADS5444 clock input can be driven with either a differential clock signal or a single-ended clock input, withlittle or no difference in performance between both configurations. In low input frequency applications, wherejitter may not be a big concern, the use of single-ended clock (see Figure 37 ) could save some cost and boardspace without any trade-off in performance. When driven on this configuration, it is best to connect CLK toground with a 0.01 µF capacitor, while CLK is ac-coupled with a 0.01- µF capacitor to the clock source, as shownin Figure 37 .
Figure 37. Single-Ended Clock
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CLK
ADS5444
CLK
0.1 µF1:4
Clock
Source
MA3X71600LCT−ND
CLK
ADS5444
CLK
D
VBB
MC100EP16DT
50 Ω
100 nF
100 nF
50 Ω
113 Ω
Q
Q
D
100 nF
100 nF
100 nF
499 W499 W
Digital Outputs
ADS5444-EP
SGLS360 – AUGUST 2006
Application Information (continued)
Figure 38. Differential Clock
For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) atthe system level. The first advantage is that it allows for common-mode noise rejection at the PCB level.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximumratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noiseon jitter. See Clocking High Speed Data Converters (SLYT075 ) for more details.
Figure 38 shows this approach. The back-to-back Schottky diodes can be added to limit the clock amplitude incases where this would exceed the absolute maximum ratings, even when using a differential clock.
Figure 39. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, such as PECL. In this case, the slew rate of the edges willmost likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock.This solution would minimize the effect of the slope dependent ADC jitter. Using logic gates to square asinusoidal clock may not produce the best results as logic gates may not have been optimized to act ascomparators, adding too much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-k Ωresistors. It isrecommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,the ADS5444 features good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% dutycycle clock signal should be provided.
The ADC provides 13 data outputs (D12 to D0, with D12 being the MSB and D0 the LSB), a data-ready signal(DRY), and an over-range indicator (OVR) that equals a logic high when the output reaches the full-scale limits.The output format is offset binary. It is recommended to use the DRY signal to capture the output data of theADS5444.
The ADS5444 digital outputs are LVDS compatible.
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Power Supplies
Layout Information
PowerPAD Package
Assembly Process
ADS5444-EP
SGLS360 – AUGUST 2006
Application Information (continued)
The use of low noise power supplies with adequate decoupling is recommended. Linear supplies are thepreferred choice versus switched ones, which tend to generate more noise components that can be coupled tothe ADS5444.
The ADS5444 uses two power supplies. For the analog portion of the design, a 5-V AVDD is used, while for thedigital outputs supply (DRVDD) we recommend the use of 3.3 V. All the ground pins are marked as GND,although AGND pins and DRGND pins are not tied together inside the package.
The evaluation board represents a good guideline of how to layout the board to obtain the maximumperformance out of the ADS5444. General design rules as the use of multilayer boards, single ground plane forADC ground connections and local decoupling ceramic chip capacitors should be applied. The input tracesshould be isolated from any external source of interference or noise including the digital outputs, as well as theclock traces. The clock signal traces should also be isolated from other signals, especially in applications wherelow jitter is required as high IF sampling.
Besides performance oriented rules, care has to be taken when considering the heat dissipation out of thedevice. The thermal heatsink should be soldered to the board as described in the PowerPad Package section.
The PowerPAD package is a thermally-enhanced standard size IC package designed to eliminate the use ofbulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted usingstandard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standardrepair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom ofthe IC. This provides an extremely low thermal resistance path between the die and the exterior of the package.The thermal pad on the bottom of the IC can then be soldered directly to the PCB using the PCB as a heatsink.
1. Prepare the PCB top-side etch pattern including etch for the leads, as well as the thermal pad as illustratedin the Mechanical Data section.2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter.The small size prevents wicking of the solder through the holes.3. It is recommended to place a small number of 25-mil diameter holes under the package, but outside thethermal pad area to provide an additional heat path.4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such asa ground plane).5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the groundplane. The spoke pattern increases the thermal resistance to the ground plane.6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either theSLMA004 application brief, PowerPAD Made Easy, or the technical brief, PowerPAD Thermally EnhancedPackage (SLMA002 ).
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
ADS5444MPFPEP ACTIVE HTQFP PFP 80 96 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 ADS5444M-EP
V62/06668-01XE ACTIVE HTQFP PFP 80 96 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 ADS5444M-EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5444-EP :
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
•Catalog: ADS5444
•Space: ADS5444-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
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