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LM2524D/LM3524D Regulating Pulse Width Modulator
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The LM3524D has a ±1% precision 5V reference.
1FEATURES The current carrying capability of the output drive
2• Fully Interchangeable With Standard LM3524 transistors has been raised to 200 mA while reducing
Family VCEsat and increasing VCE breakdown to 60V. The
• ±1% Precision 5V Reference With Thermal common mode voltage range of the error-amp has
been raised to 5.5V to eliminate the need for a
Shut-Down resistive divider from the 5V reference.
• Output Current to 200 mA DC In the LM3524D the circuit bias line has been isolated
• 60V Output Capability from the shut-down pin. This prevents the oscillator
• Wide Common Mode Input Range for Error- pulse amplitude and frequency from being disturbed
Amp by shut-down. Also at high frequencies (≃300 kHz)
• One Pulse per Period (Noise Suppression) the max. duty cycle per output has been improved to
44% compared to 35% max. duty cycle in other
• Improved Max. Duty Cycle at High Frequencies 3524s.
• Double Pulse Suppression In addition, the LM3524D can now be synchronized
• Synchronize Through Pin 3 externally, through pin 3. Also a latch has been
added to insure one pulse per period even in noisy
DESCRIPTION environments. The LM3524D includes double pulse
The LM3524D family is an improved version of the suppression logic that insures when a shut-down
industry standard LM3524. It has improved condition is removed the state of the T-flip-flop will
specifications and additional features yet is pin for pin change only after the first clock pulse has arrived.
compatible with existing 3524 families. New features This feature prevents the same output from being
reduce the need for additional external circuitry often pulsed twice in a row, thus reducing the possibility of
required in the original version. core saturation in push-pull designs.
Connection Diagram
Figure 1. Top View
See Package Number NFG
See Package Number D
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM2524D, LM3524D
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage 40V
Collector Supply Voltage LM2524D 55V
LM3524D 40V
Output Current DC (each) 200 mA
Oscillator Charging Current (Pin 7) 5 mA
Internal Power Dissipation 1W
Operating Junction Temperature Range (3) LM2524D −40°C to +125°C
LM3524D 0°C to +125°C
Maximum Junction Temperature 150°
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 4 sec.) NFG, D Pkg. 260°C
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not
apply when operating the device beyond its rated operating conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For operation at elevated temperatures, devices in the NFG package must be derated based on a thermal resistance of 86°C/W,
junction to ambient. Devices in the D package must be derated at 125°C/W, junction to ambient.
Electrical Characteristics(1)
Symbol Parameter Conditions LM2524D LM3524D Units
Typ Tested Design Typ Tested Design
Limit(2) Limit(3) Limit(2) Limit(3)
REFERENCE SECTION
VREF Output Voltage 5 4.85 4.80 5 4.75 VMin
5.15 5.20 5.25 VMax
VRLine Line Regulation VIN = 8V to 40V 10 15 30 10 25 50 mVMax
VRLoad Load Regulation IL= 0 mA to 20 mA 10 15 25 10 25 50 mVMax
ΔVIN/ΔVREF Ripple Rejection f = 120 Hz 66 66 dB
IOS Short Circuit Current VREF = 0 25 25 mA Min
50 50
180 200 mA Max
NOOutput Noise 10 Hz ≤f≤10 kHz 40 100 40 100 μVrms
Max
Long Term Stability TA= 125°C 20 20 mV/kHr
OSCILLATOR SECTION
fOSC Max. Freq. RT= 1k, CT= 0.001 μF(4) 550 500 350 kHzMin
fOSC Initial Accuracy RT= 5.6k, CT= 0.01 μF(4) 17.5 17.5 kHzMin
20 20
22.5 22.5 kHzMax
RT= 2.7k, CT= 0.01 μF(4) 34 30 kHzMin
38 38
42 46 kHzMax
(1) Unless otherwise stated, these specifications apply for TA= TJ= 25°C. Boldface numbers apply over the rated temperature range:
LM2524D is −40° to 85°C and LM3524D is 0°C to 70°C. VIN = 20V and fOSC = 20 kHz.
(2) Tested limits are ensured and 100% tested in production.
(3) Design limits are ensured (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are
not used to calculate outgoing quality level.
(4) The value of a Ctcapacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation.
Polystyrene was used in this test. NPO ceramic or polypropylene can also be used.
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Electrical Characteristics(1) (continued)
Symbol Parameter Conditions LM2524D LM3524D Units
Typ Tested Design Typ Tested Design
Limit(2) Limit(3) Limit(2) Limit(3)
ΔfOSC Freq. Change with VIN VIN = 8 to 40V 0.5 1 0.5 1.0 %Max
ΔfOSC Freq. Change with Temp. TA=−55°C to +125°C 5 5 %
at 20 kHz RT= 5.6k,
CT= 0.01 μF
VOSC Output Amplitude (Pin 3) RT= 5.6k, CT= 0.01 μF3 2.4 3 2.4 VMin
(5)
tPW Output Pulse Width (Pin 3) RT= 5.6k, CT= 0.01 μF 0.5 1.5 0.5 1.5 μsMax
Sawtooth Peak Voltage RT= 5.6k, CT= 0.01 μF 3.4 3.6 3.8 3.8 VMax
Sawtooth Valley Voltage RT= 5.6k, CT= 0.01 μF 1.1 0.8 0.6 0.6 VMin
ERROR-AMP SECTION
VIO Input Offset Voltage VCM = 2.5V 2 8 10 2 10 mVMax
IIB Input Bias Current VCM = 2.5V 1 8 10 1 10 μAMax
IIO Input Offset Current VCM = 2.5V 0.5 1.0 10.5 1 μAMax
ICOSI Compensation Current VIN(I) −VIN(NI) = 150 mV 65 65 μAMin
(Sink) 95 95
125 125 μAMax
ICOSO Compensation Current VIN(NI) −VIN(I) = 150 mV −125 −125 μAMin
(Source) −95 −95
−65 −65 μAMax
AVOL Open Loop Gain RL=∞, VCM = 2.5 V 80 74 60 80 70 60 dBMin
VCMR Common Mode Input 1.5 1.4 1.5 VMin
Voltage Range 5.5 5.4 5.5 VMax
CMRR Common Mode Rejection 90 80 90 80 dBMin
Ratio
GBW Unity Gain Bandwidth AVOL = 0 dB, VCM = 2.5V 3 2 MHz
VOOutput Voltage Swing RL=∞0.5 0.5 VMin
5.5 5.5 VMax
PSRR Power Supply Rejection VIN = 8 to 40V 80 70 80 65 dbMin
Ratio
COMPARATOR SECTION
Minimum Duty Cycle Pin 9 = 0.8V,
tON/tOSC 0 0 0 0 %Max
[RT= 5.6k, CT= 0.01 μF]
Maximum Duty Cycle Pin 9 = 3.9V,
tON/tOSC 49 45 49 45 %Min
[RT= 5.6k, CT= 0.01 μF]
Maximum Duty Cycle Pin 9 = 3.9V,
tON/tOSC 44 35 44 35 %Min
[RT= 1k, CT= 0.001 μF]
VCOMPZ Input Threshold Zero Duty Cycle 1 1 V
(Pin 9)
VCOMPM Input Threshold (Pin 9) Maximum Duty Cycle 3.5 3.5 V
IIB Input Bias Current −1−1μA
CURRENT LIMIT SECTION
VSEN Sense Voltage V(Pin 2) −V(Pin 1) ≥150 mV 180 180 mVMin
200 200
220 220 mVMax
TC-Vsense Sense Voltage T.C. 0.2 0.2 mV/°C
Common Mode Voltage V5−V4= 300 mV −0.7 −0.7 VMin
Range 1 1 VMax
(5) OSC amplitude is measured open circuit. Available current is limited to 1 mA so care must be exercised to limit capacitive loading of fast
pulses.
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Electrical Characteristics(1) (continued)
Symbol Parameter Conditions LM2524D LM3524D Units
Typ Tested Design Typ Tested Design
Limit(2) Limit(3) Limit(2) Limit(3)
SHUT DOWN SECTION
VSD High Input Voltage V(Pin 2) −V(Pin 1) ≥150 mV 1 0.5 1 0.5 VMin
1.5 1.5 VMax
ISD High Input Current I(pin 10) 1 1 mA
OUTPUT SECTION (EACH OUTPUT)
VCES Collector Emitter Voltage IC≤100 μA55 40 VMin
Breakdown
ICES Collector Leakage Current VCE = 60V
VCE = 55V 0.1 50 μAMax
VCE = 40V 0.1 50
VCESAT Saturation Voltage IE= 20 mA 0.2 0.5 0.2 0.7 VMax
IE= 200 mA 1.5 2.2 1.5 2.5
VEO Emitter Output Voltage IE= 50 mA 18 17 18 17 VMin
tRRise Time VIN = 20V, 200 200 ns
IE=−250 μA
RC= 2k
tFFall Time RC= 2k 100 100 ns
SUPPLY CHARACTERISTICS SECTION
VIN Input Voltage Range After Turn-on 8 8 VMin
40 40 VMax
T Thermal Shutdown Temp. (6) 160 160 °C
IIN Stand By Current VIN = 40V(7) 5 10 5 10 mA
(6) For operation at elevated temperatures, devices in the NFG package must be derated based on a thermal resistance of 86°C/W,
junction to ambient. Devices in the D package must be derated at 125°C/W, junction to ambient.
(7) Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2 = 2V. All other inputs and outputs open.
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Typical Performance Characteristics
Switching Transistor Peak Output Current
vs Temperature Maximum Average Power Dissipation (NFG, D Packages)
Figure 2. Figure 3.
Maximum & Minimum Output Transistor
Duty Cycle Threshold Voltage Saturation Voltage
Figure 4. Figure 5.
Output Transistor Emitter Reference Transistor
Voltage Peak Output Current
Figure 6. Figure 7.
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Typical Performance Characteristics (continued)
Standby Current Standby Current
vs Voltage vs Temperature
Figure 8. Figure 9.
Current Limit Sense Voltage
Figure 10.
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Functional Description
Internal Voltage Regulator
The LM3524D has an on-chip 5V, 50 mA, short circuit protected voltage regulator. This voltage regulator
provides a supply for all internal circuitry of the device and can be used as an external reference.
For input voltages of less than 8V the 5V output should be shorted to pin 15, VIN, which disables the 5V
regulator. With these pins shorted the input voltage must be limited to a maximum of 6V. If input voltages of
6V–8V are to be used, a pre-regulator, as shown in Figure 11, must be added.
*Minimum COof 10 μF required for stability.
Figure 11.
Oscillator
The LM3524D provides a stable on-board oscillator. Its frequency is set by an external resistor, RTand capacitor,
CT. A graph of RT, CTvs oscillator frequency is shown is Figure 12. The oscillator's output provides the signals
for triggering an internal flip-flop, which directs the PWM information to the outputs, and a blanking pulse to turn
off both outputs during transitions to ensure that cross conduction does not occur. The width of the blanking
pulse, or dead time, is controlled by the value of CT, as shown in Figure 13. The recommended values of RTare
1.8 kΩto 100 kΩ, and for CT, 0.001 μF to 0.1 μF.
If two or more LM3524D's must be synchronized together, the easiest method is to interconnect all pin 3
terminals, tie all pin 7's (together) to a single CT, and leave all pin 6's open except one which is connected to a
single RT. This method works well unless the LM3524D's are more than 6″apart.
A second synchronization method is appropriate for any circuit layout. One LM3524D, designated as master,
must have its RTCTset for the correct period. The other slave LM3524D(s) should each have an RTCTset for a
10% longer period. All pin 3's must then be interconnected to allow the master to properly reset the slave units.
The oscillator may be synchronized to an external clock source by setting the internal free-running oscillator
frequency 10% slower than the external clock and driving pin 3 with a pulse train (approx. 3V) from the clock.
Pulse width should be greater than 50 ns to insure full synchronization.
Figure 12.
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Figure 13.
Error Amplifier
The error amplifier is a differential input, transconductance amplifier. Its gain, nominally 86 dB, is set by either
feedback or output loading. This output loading can be done with either purely resistive or a combination of
resistive and reactive components. A graph of the amplifier's gain vs output load resistance is shown in
Figure 14.
Figure 14.
The output of the amplifier, or input to the pulse width modulator, can be overridden easily as its output
impedance is very high (ZO≃5 MΩ). For this reason a DC voltage can be applied to pin 9 which will override the
error amplifier and force a particular duty cycle to the outputs. An example of this could be a non-regulating
motor speed control where a variable voltage was applied to pin 9 to control motor speed. A graph of the output
duty cycle vs the voltage on pin 9 is shown in Figure 15.
The duty cycle is calculated as the percentage ratio of each output's ON-time to the oscillator period. Paralleling
the outputs doubles the observed duty cycle.
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Figure 15.
The amplifier's inputs have a common-mode input range of 1.5V–5.5V. The on board regulator is useful for
biasing the inputs to within this range.
Current Limiting
The function of the current limit amplifier is to override the error amplifier's output and take control of the pulse
width. The output duty cycle drops to about 25% when a current limit sense voltage of 200 mV is applied
between the +CLand −CLsense terminals. Increasing the sense voltage approximately 5% results in a 0% output
duty cycle. Care should be taken to ensure the −0.7V to +1.0V input common-mode range is not exceeded.
In most applications, the current limit sense voltage is produced by a current through a sense resistor. The
accuracy of this measurement is limited by the accuracy of the sense resistor, and by a small offset current,
typically 100 μA, flowing from +CL to −CL.
Output Stages
The outputs of the LM3524D are NPN transistors, capable of a maximum current of 200 mA. These transistors
are driven 180° out of phase and have non-committed open collectors and emitters as shown in Figure 16.
Figure 16.
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Typical Applications
Figure 17. Positive Regulator, Step-Up Basic Configuration (IIN(MAX) = 80 mA)
(1)
Figure 18. Positive Regulator, Step-Up Boosted Current Configuration
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Figure 19. Positive Regulator, Step-Down Basic Configuration (IIN(MAX) = 80 mA)
(2)
Figure 20. Positive Regulator, Step-Down Boosted Current Configuration
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Figure 21. Boosted Current Polarity Inverter
(3)
Basic Switching Regulator Theory and Applications
The basic circuit of a step-down switching regulator circuit is shown in Figure 22, along with a practical circuit
design using the LM3524D in Figure 25.
Figure 22. Basic Step-Down Switching Regulator
The circuit works as follows: Q1 is used as a switch, which has ON and OFF times controlled by the pulse width
modulator. When Q1 is ON, power is drawn from VIN and supplied to the load through L1; VAis at approximately
VIN, D1 is reverse biased, and Cois charging. When Q1 turns OFF the inductor L1 will force VAnegative to keep
the current flowing in it, D1 will start conducting and the load current will flow through D1 and L1. The voltage at
VAis smoothed by the L1, Cofilter giving a clean DC output. The current flowing through L1 is equal to the
nominal DC load current plus some ΔILwhich is due to the changing voltage across it. A good rule of thumb is to
set ΔILP-P
≃
40% × Io.
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Figure 23. Relation of Switch Timing to Inductor Current in Step-Down Regulator
(4)
Neglecting VSAT, VD, and settling ΔIL+=ΔIL−;
(5)
where T = Total Period
The above shows the relation between VIN, Voand duty cycle.
(6)
as Q1 only conducts during tON.
(7)
The efficiency, η, of the circuit is:
(8)
ηMAX will be further decreased due to switching losses in Q1. For this reason Q1 should be selected to have the
maximum possible fT, which implies very fast rise and fall times.
Calculating Inductor L1
(9)
Since ΔIL+ = ΔIL−= 0.4Io
Solving the above for L1
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(10)
where: L1 is in Henrys
f is switching frequency in Hz
Also, see LM1578 data sheet for graphical methods of inductor selection.
Calculating Output Filter Capacitor Co
Figure 23 shows L1's current with respect to Q1's tON and tOFF times (VAis at the collector of Q1). This curent
must flow to the load and Co. Co's current will then be the difference between IL, and Io.
Ico= IL−Io(11)
From Figure 23 it can be seen that current will be flowing into Cofor the second half of tON through the first half of
tOFF, or a time, tON/2 + tOFF/2. The current flowing for this time is ΔIL/4. The resulting ΔVcor ΔVois described by:
(12)
For best regulation, the inductor's current cannot be allowed to fall to zero. Some minimum load current Io, and
thus inductor current, is required as shown below:
(13)
Figure 24. Inductor Current Slope in Step-Down Regulator
A complete step-down switching regulator schematic, using the LM3524D, is illustrated in Figure 25. Transistors
Q1 and Q2 have been added to boost the output to 1A. The 5V regulator of the LM3524D has been divided in
half to bias the error amplifier's non-inverting input to within its common-mode range. Since each output
transistor is on for half the period, actually 45%, they have been paralleled to allow longer possible duty cycle, up
to 90%. This makes a lower possible input voltage. The output voltage is set by:
(14)
where VNI is the voltage at the error amplifier's non-inverting input.
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Resistor R3 sets the current limit to:
(15)
Figure 26 and Figure 27 show a PC board layout and stuffing diagram for the 5V, 1A regulator of Figure 25. The
regulator's performance is listed in Table 1.
*Mounted to Staver Heatsink No. V5-1.
Q1 = BD344
Q2 = 2N5023
L1 = >40 turns No. 22 wire on Ferroxcube No. K300502 Torroid core.
Figure 25. 5V, 1 Amp Step-Down Switching Regulator
Table 1.
Parameter Conditions Typical Characteristics
Output Voltage VIN = 10V, Io= 1A 5V
Switching Frequency VIN = 10V, Io= 1A 20 kHz
Short Circuit Current Limit VIN = 10V 1.3A
Load Regulation VIN = 10V 3 mV
Io= 0.2 −1A
Line Regulation ΔVIN = 10 −20V, 6 mV
Io= 1A
Efficiency VIN = 10V, Io= 1A 80%
Output Ripple VIN = 10V, Io= 1A 10 mVp-p
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Figure 26. 5V, 1 Amp Switching Regulator, Foil Side
Figure 27. Stuffing Diagram, Component Side
The Step-Up Switching Regulator
Figure 28 shows the basic circuit for a step-up switching regulator. In this circuit Q1 is used as a switch to
alternately apply VIN across inductor L1. During the time, tON, Q1 is ON and energy is drawn from VIN and stored
in L1; D1 is reverse biased and Iois supplied from the charge stored in Co. When Q1 opens, tOFF, voltage V1 will
rise positively to the point where D1 turns ON. The output current is now supplied through L1, D1 to the load and
any charge lost from Coduring tON is replenished. Here also, as in the step-down regulator, the current through
L1 has a DC component plus some ΔIL.ΔILis again selected to be approximately 40% of IL.Figure 29 shows the
inductor's current in relation to Q1's ON and OFF times.
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Figure 28. Basic Step-Up Switching Regulator
Figure 29. Relation of Switch Timing to Inductor Current in Step-Up Regulator
(16)
Since ΔIL+ = ΔIL−, VINtON = VotOFF −VINtOFF,
and neglecting VSAT and VD1
(17)
The above equation shows the relationship between VIN, Voand duty cycle.
In calculating input current IIN(DC), which equals the inductor's DC current, assume first 100% efficiency:
(18)
for η= 100%, POUT = PIN
(19)
This equation shows that the input, or inductor, current is larger than the output current by the factor (1 +
tON/tOFF). Since this factor is the same as the relation between Voand VIN, IIN(DC) can also be expressed as:
(20)
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So far it is assumed η= 100%, where the actual efficiency or ηMAX will be somewhat less due to the saturation
voltage of Q1 and forward on voltage of D1. The internal power loss due to these voltages is the average IL
current flowing, or IIN, through either VSAT or VD1. For VSAT = VD1 = 1V this power loss becomes IIN(DC) (1V). ηMAX
is then:
(21)
(22)
This equation assumes only DC losses, however ηMAX is further decreased because of the switching time of Q1
and D1.
In calculating the output capacitor Coit can be seen that Cosupplies Ioduring tON. The voltage change on Co
during this time will be some ΔVc=ΔVoor the output ripple of the regulator. Calculation of Cois:
(23)
where: Cois in farads, f is the switching frequency,
ΔVois the p-p output ripple
Calculation of inductor L1 is as follows:
(24)
VIN is applied across L1
(25)
where: L1 is in henrys, f is the switching frequency in Hz
To apply the above theory, a complete step-up switching regulator is shown in Figure 30. Since VIN is 5V, VREF is
tied to VIN. The input voltage is divided by 2 to bias the error amplifier's inverting input. The output voltage is:
(26)
The network D1, C1 forms a slow start circuit.
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This holds the output of the error amplifier initially low thus reducing the duty-cycle to a minimum. Without the
slow start circuit the inductor may saturate at turn-on because it has to supply high peak currents to charge the
output capacitor from 0V. It should also be noted that this circuit has no supply rejection. By adding a reference
voltage at the non-inverting input to the error amplifier, see Figure 31, the input voltage variations are rejected.
The LM3524D can also be used in inductorless switching regulators. Figure 32 shows a polarity inverter which if
connected to Figure 30 provides a −15V unregulated output.
L1 = > 25 turns No. 24 wire on Ferroxcube No. K300502 Toroid core.
Figure 30. 15V, 0.5A Step-Up Switching Regulator
Figure 31. Replacing R3/R4 Divider in Figure 30 with Reference Circuit Improves Line Regulation
Figure 32. Polarity Inverter Provides Auxiliary −15V Unregulated Output from Circuit of Figure 30
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REVISION HISTORY
Changes from Revision D (May 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM2524DN/NOPB ACTIVE PDIP NFG 16 25 Pb-Free
(RoHS) CU SN Level-1-NA-UNLIM -40 to 125 LM2524DN
LM3524DM NRND SOIC D 16 48 TBD Call TI Call TI 0 to 80 LM3524DM
LM3524DM/NOPB ACTIVE SOIC D 16 48 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 80 LM3524DM
LM3524DMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 80 LM3524DM
LM3524DN NRND PDIP NFG 16 25 TBD Call TI Call TI 0 to 80 LM3524DN
LM3524DN/NOPB ACTIVE PDIP NFG 16 25 Green (RoHS
& no Sb/Br) SN Level-1-NA-UNLIM 0 to 80 LM3524DN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM3524DMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM3524DMX/NOPB SOIC D 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
MECHANICAL DATA
N0016E
www.ti.com
N16E (Rev G)
NFG0016E
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